ADC128S102PWTSEP [TI]
抗辐射、八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | PW | 16 | -55 to 125;
| 型号： | ADC128S102PWTSEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 抗辐射、八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | PW | 16 | -55 to 125 转换器 模数转换器 |
| 文件： | 总31页 (文件大小：1669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
ADC128S102-SEP 耐辐射8 通道、50-kSPS 至1-MSPS、12 位ADC
1 特性
3 说明
• 抗辐射：
ADC128S102-SEP 是一款低功耗、8 通道、CMOS、
12 位模数转换器 (ADC)，具有 50 kSPS 至 1 MSPS
的转换吞吐率。该转换器以逐次逼近寄存器 (SAR) 架
构为基础，具有内部追踪保持电路。该器件经配置可接
收多达八路输入信号（IN0 至IN7）。
– 在125°C 的环境温度下，单粒子锁定(SEL) 抗
扰度高达
LET = 43 MeV-cm2/mg
– 单粒子功能中断(SEFI) 的LET 特征值高达43
MeV-cm2/mg
– 电离辐射总剂量(TID) RLAT/RHA 特征值高达
30 krad(Si)
串行数据输出采用标准二进制，兼容多个标准（如
SPI、QSPI、MICROWIRE）和许多常见的 DSP 串行
接口。
• 增强型航天塑料（航天EP）：
ADC128S102-SEP 可由独立的模拟和数字电源供电。
模拟电源 (VA) 的电压范围为 2.7V 至5.25V，数字电源
(VD) 的电压范围为 2.7V 至 VA。使用 3V 或 5V 电源的
正常功耗分别为 2.3 mW 和 10.7 mW。使用 3V 和 5V
电源时，断电特性可分别将功耗降至 16.5 μW 和 30
μW。
– 符合ASTM E595 释气规格要求
– 供应商项目图(VID) V62/22608
– 军用温度范围：-55°C 至125°C
– 制造、组装和测试一体化基地
– 金键合线，NiPdAu 铅涂层
– 晶圆批次可追溯性
– 延长了产品生命周期
– 延长了产品变更通知
• 宽电源电压范围：
器件信息(1)
封装尺寸（标称值）
器件型号
封装
ADC128S102-SEP
TSSOP (16)
5.00mm × 4.40mm
– VA：2.7V 至5.25V
– VD：2.7V 至VA
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 兼容SPI™、QSPI™、MICROWIRE®、DSP
• 转换速率：50 kSPS 至1 MSPS
• DNL：+1.8 LSB 至-0.99 LSB（最大值）
• INL：+1.6 LSB 至-1.6 LSB（最大值）
• 功耗：
– 3V 电源：2.7 mW（典型值）
– 5V 电源：11 mW（典型值）
2 应用
• 卫星电力系统(EPS)
• 命令和数据处理(C&DH)
• 光学成像有效载荷
• 电压、电流和温度监控
• 加速器
VA is used as the Reference
VD can be set independently
for the ADC
of VA
“Analog” Supply Rail
“Digital” Supply Rail
VD
VA
VIN7
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
4-wire SPI
SAR
ADC
MCU
VIN3
VIN0
AGND
DGND
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS825
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 18
8 Application and Implementation..................................20
8.1 Application Information............................................. 20
8.2 Typical Application.................................................... 20
9 Power Supply Recommendations................................22
9.1 Power-Supply Sequence.......................................... 22
9.2 Power Management..................................................22
9.3 Power-Supply Noise Considerations........................ 22
10 Layout...........................................................................23
10.1 Layout Guidelines................................................... 23
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 接收文档更新通知................................................... 24
11.2 支持资源..................................................................24
11.3 Trademarks............................................................. 24
11.4 Electrostatic Discharge Caution..............................24
11.5 术语表..................................................................... 24
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Switching Characteristics............................................8
6.8 Timing Diagrams.........................................................9
6.9 Typical Characteristics..............................................10
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................17
Information.................................................................... 24
12.1 Engineering Samples..............................................24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2021) to Revision A (April 2022)
Page
• 将文档状态从预告信息更改为量产数据..............................................................................................................1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
5 Pin Configuration and Functions
CS
VA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
DOUT
DIN
AGND
IN0
VD
IN1
DGND
IN7
IN2
IN3
IN6
IN4
IN5
Not to scale
图5-1. PW Package, 16-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as
CS is held low.
1
CS
IN
Positive analog supply pin. This voltage is also used as the reference voltage. Connect this pin to a
2
VA
Supply quiet 2.7-V to 5.25-V source and bypass this pin to GND with 1-µF and 0.1-µF monolithic ceramic
capacitors located within 1 cm of the power pin.
3
AGND
IN0
Supply The ground return for the analog supply and signals.
4
IN
IN
IN
IN
IN
IN
IN
IN
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
Analog input. This signal can range from 0 V to VREF
.
.
.
.
.
.
.
5
IN1
6
IN2
7
IN3
8
IN4
9
IN5
10
11
12
IN6
IN7
Analog input. This signals can range from 0 V to VREF.
DGND
Supply The ground return for the digital supply and signals.
Positive digital supply pin. Connect this pin to a 2.7-V to VA supply, and bypass this pin to GND with a
0.1-µF monolithic ceramic capacitor located within 1 cm of the power pin.
13
14
15
VD
DIN
Supply
IN
Digital data input. The control register is loaded through this pin on rising edges of the SCLK pin.
Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK
pin.
DOUT
OUT
Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz to
16 MHz. This clock directly controls the conversion and readout processes.
16
SCLK
IN
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
6.5
UNIT
V
Analog supply voltage (VA)
Digital supply voltage (VD)(2)
Voltage on analog input pins to AGND(2)
Voltage on digital input and digital output pins to DGND(2)
DGND to AGND
VA + 0.3
VA + 0.3
VD + 0.3
0.3
V
–0.3
V
AGND –0.3
DGND –0.3
–0.3
V
V
Input current at any pin
10
mA
mA
–10
Package input current
20
–20
Power-dissipation at TA = 25°C
Junction temperature, TJ
See(3)
150
°C
°C
Storage temperature, Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The maximum voltage is not to exceed 6.5 V
(3) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated
in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Such conditions should always be avoided.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Analog power supply
Digital power supply
Digital input voltage
Full-scale analog input range
Clock frequency
TEST CONDITIONS
VA to AGND
VD to DGND
MIN
2.7
2.7
0
NOM
MAX UNIT
VA
5.25
VA
V
V
V
V
VD
VIN
FSR
VA
0
VA
0.8
–55
16 MHz
125 °C
TA
Ambient temperature
25
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.4 Thermal Information
ADC128S102-SEP
THERMAL METRIC(1)
PW (TSSOP)
UNIT
16 PINS
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
110
42
56
5
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
55
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.5 Electrical Characteristics
at AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF (unless otherwise
noted); minimum and maximum values at TA = –55°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
IDCL
CIN
Input leakage current
Input capacitance(1)
µA
pF
–1
1
Track mode
Hold mode
33
3
DC PERFORMANCE
Resolution
No missing codes
VA = VD = 3 V
12
0.5
Bits
1.8
1.7
–0.99
–0.3
0.9
DNL
Differential nonlinearity
LSB
VA = VD = 5 V
–0.99
–1.6
–1.5
–2.3
–2.3
–1.5
–1.5
–2.1
–2.1
–1.6
–1.6
–0.5
±0.6
±0.9
0.8
VA = VD = 3 V
VA = VD = 5 V
VA = VD = 3 V
VA = VD = 5 V
VA = VD = 3 V
VA = VD = 5 V
VA = VD = 3 V
VA = VD = 5 V
VA = VD = 3 V
VA = VD = 5 V
1.6
1.5
2.3
2.3
1.5
1.5
2.1
2.1
1.6
1.6
INL
Integral nonlinearity
Input offset error
LSB
LSB
LSB
LSB
LSB
VOFF
OEM
FSE
1.1
±0.1
±0.3
0.8
Offset error match
Full-scale error
0.3
±0.1
±0.3
FSEM
Full-scale error match
AC PERFORMANCE
VA = VD = 3 V
VA = VD = 5 V
6.8
10
FPBW
Full-power bandwidth
MHz
dB
VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS
68
68
72
72
SINAD
Signal-to-noise + distortion ratio
Signal-to-noise ratio
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS
VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS
68.5
68
72
SNR
THD
dB
dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS
72
VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS
–86
–87
91
–72
–72
Total harmonic distortion
Spurious-free dynamic range
Effective number of bits
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS
VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS
75
75
SFDR
ENOB
ISO
dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS
90
VA = VD = 3 V,
fIN = 40.2 kHz, –0.02 dBFS
11.1
11
11.6
11.6
84
Bits
dB
VA = VD = 5 V,
fIN = 40.2 kHz, –0.02 dBFS
VA = VD = 3 V,
fIN = 20 kHz, –0.02 dBFS
Channel-to-channel isolation
VA = VD = 5 V,
fIN = 20 kHz, –0.02 dBFS
85
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.5 Electrical Characteristics (continued)
at AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50 pF (unless otherwise
noted); minimum and maximum values at TA = –55°C to +125°C; typical values at TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VA = VD = 3 V,
fIN = 19.5 kHz, –0.02 dBFS
–93
–77
Intermodulation distortion,
second order terms
VA = VD = 5 V,
fIN = 19.5 kHz, –0.02 dBFS
–93
–91
–91
–77
–70
–70
IMD
dB
VA = VD = 3 V,
fIN = 19.5 kHz, –0.02 dBFS
Intermodulation distortion,
third order terms
VA = VD = 5 V,
fIN = 19.5 kHz, –0.02 dBFS
DIGITAL INPUTS
VA = VD = 2.7 V to 3.6 V
VA = VD = 4.75 V to 5.25 V
VA = VD = 2.7 V to 5.25 V
VIN = 0 V or VD
2.1
2.4
VIH
VIL
Input high logic level
V
Input low logic level
Input current
0.8
±2
V
±0.01
µA
pF
Digital input capacitance(1)
3.5
DIGITAL OUTPUTS
Output format
Straight binary
VD - 0.5
ISOURCE = 200 µA,
VA = VD = 2.7 V to 5.25 V
VOH
VOL
Output high logic level
Output low logic level
V
V
ISOURCE = 200 µA to 1 mA,
VA = VD = 2.7 V to 5.25 V
0.4
±1
Hiigh-impedance output leakage
current
VA = VD = 2.7 V to 5.25 V
±0.01
µA
pF
Hiigh-impedance output
capacitance(1)
3.5
POWER SUPPLY
VA = VD = 2.7 V to 3.6 V
fSAMPLE = 1 MSPS, fIN = 40 kHz
0.9
2.2
5.5
6
1.5
3.2
50
Total supply current,
normal mode (CS low)
mA
µA
VA = VD = 4.75 V to 5.25 V
fSAMPLE = 1 MSPS, fIN = 40 kHz
IA + ID
VA = VD = 2.7 V to 3.6 V
fSAMPLE = 0 kSPS
Total supply current,
shutdown mode (CS high)
VA = VD = 4.75 V to 5.25 V
fSAMPLE = 0 kSPS
70
VA = VD = 3 V
fSAMPLE = 1 MSPS, fIN = 40 kHz
2.7
11
4.5
15.5
150
350
Power consumption,
normal mode (CS low)
mW
µW
VA = VD = 5 V
fSAMPLE = 1 MSPS, fIN = 40 kHz
PC
VA = VD = 3 V
fSAMPLE = 0 kSPS
16.5
30
Power consumption,
shutdown mode (CS high)
VA = VD = 5 V
fSAMPLE = 0 kSPS
(1) This parameter is specified by design and/or characterization and is not tested in production.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.6 Timing Requirements
at VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50
pF (unless otherwise noted); minimum and maximum values at TA = –55°C to +125°C; typical values at TA = 25°C.
MIN
TYP
MAX
UNIT
CONVERSION CYCLE
fSCLK
Serial clock frequency
VA = VD = 2.7 V to 5.25 V
VA = VD = 2.7 V to 5.25 V
VA = VD = 2.7 V to 5.25 V
VA = VD = 2.7 V to 5.25 V
VA = VD = 2.7 V to 5.25 V
0.8
40%
50
16
MHz
Serial clock duty cycle
60%
fS
Sample rate in continuous mode
Conversion (hold) time
kSPS
SCLK
SCLK
tCONVERT
tACQ
13
3
Acquisition (track) time
(tCONV + tACQ) at
VA = VD = 2.7 V to 5.25 V
tCYCLE
Throughput time
16
SCLK
SPI INTERFACE TIMINGS
tCSH
tCSS
tDS
CS hold time after SCLK rising edge
CS setup time prior to SCLK rising edge
10
10
10
10
2
ns
ns
ns
ns
ns
ns
4.5
DIN setup time prior to SCLK rising edge
DIN hold time after SCLK rising edge
SCLK high time
tDH
tCH
tCL
0.4 x tSCLK
0.4 x tSCLK
SCLK low time
6.7 Switching Characteristics
at VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, and CL = 50
pF (unless otherwise noted); minimum and maximum values at TA = –55°C to +125°C; typical values at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SPI INTERFACE TIMINGS
tEN
CS falling edge to DOUT enabled
5
30
27
ns
ns
ns
ns
ns
tDACC
tDHLD
DOUT access time after SCLK falling edge
DOUT hold time after SCLK falling edge
17
7
DOUT falling
DOUT rising
2.4
0.9
20
20
tDIS
CS rising edge to DOUT high-impedance
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.8 Timing Diagrams
Power
Down
Power Up
Power Up
Hold
Track
Track
Hold
10
CS
8
9
11
12
13
14
15
16
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
SCLK
Control register N
ADD2 ADD1 ADD0
Control register N + 1
ADD2 ADD1 ADD0
DIN
Data N œ 1
Data N
DOUT
FOUR ZEROS
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
FOUR ZEROS
DB11 DB10 DB9
图6-1. ADC128S102-SEP Operational Timing Diagram
CS
tCONVERT
tACQ
tCH
SCLK
1
2
3
4
5
6
7
8
16
tCL
tDACC
tDHLD
tDIS
tEN
DB11
DB10
DB1
DB0
DOUT
FOUR ZEROS
tDH
DB9
DB8
tDS
DONTC DONTC
DONTC
ADD2
ADD1
ADD0
DONTC DONTC
DIN
图6-2. ADC128S102-SEP Serial Timing Diagram
SCLK
t
CSS
CS
CS
t
CSH
图6-3. SCLK and CS Timing Parameters
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.9 Typical Characteristics
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, and fIN = 40.2 kHz (unless otherwise noted)
图6-4. DNL
图6-5. DNL
图6-6. INL
图6-7. INL
图6-8. DNL vs Supply
图6-9. INL vs Supply
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.9 Typical Characteristics (continued)
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, and fIN = 40.2 kHz (unless otherwise noted)
图6-10. SNR vs Supply
图6-11. THD vs Supply
图6-12. ENOB vs Supply
图6-13. DNL vs SCLK Duty Cycle
图6-14. INL vs SCLK Duty Cycle
图6-15. SNR vs SCLK Duty Cycle
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.9 Typical Characteristics (continued)
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, and fIN = 40.2 kHz (unless otherwise noted)
图6-16. THD vs SCLK Duty Cycle
图6-17. ENOB vs SCLK Duty Cycle
图6-18. DNL vs SCLK
图6-19. INL vs SCLK
图6-20. DNL vs SCLK
图6-21. INL vs SCLK
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.9 Typical Characteristics (continued)
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, and fIN = 40.2 kHz (unless otherwise noted)
图6-22. SNR vs SCLK
图6-23. SNR vs SCLK
图6-24. THD vs SCLK
图6-25. THD vs SCLK
图6-26. ENOB vs SCLK
图6-27. ENOB vs SCLK
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
6.9 Typical Characteristics (continued)
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, and fIN = 40.2 kHz (unless otherwise noted)
图6-28. ENOB vs Temperature
图6-30. INL vs Temperature
图6-32. THD vs Temperature
图6-29. DNL vs Temperature
图6-31. SNR vs Temperature
图6-33. Power Consumption vs SCLK
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
7 Detailed Description
7.1 Overview
The ADC128S102-SEP is a small, eight-channel, multiplexed, 12-bit, successive-approximation register analog-
to-digital converter (SAR ADC) designed around a charge redistribution digital-to-analog converter (DAC). In
addition to having 8 input channels, the ADC128S102-SEP can operate at sampling rates up to 1 MSPS.
The device provides an SPI-compatible serial interface.
7.2 Functional Block Diagram
IN0
VA
.
.
.
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
MUX
T/H
AGND
AGND
IN7
VD
SCLK
ADC128S102
CS
CONTROL
LOGIC
DIN
DOUT
DGND
7.3 Feature Description
7.3.1 ADC128S102-SEP Transfer Function
The output format of the ADC128S102-SEP is straight binary. Code transitions occur midway between
successive integer LSB values. The LSB width for the ADC128S102-SEP is VA / 4096. 图7-1 illustrates the ideal
transfer characteristic. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at
1/2 LSB, or a voltage of VA / 8192. Other code transitions occur at steps of one LSB.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
111...111
111...110
111...000
ö
1LSB = VA/4096
011...111
000...010
000...001
000...000
+VA - 1.5LSB
0.5LSB
0V
ANALOG INPUT
图7-1. Ideal Transfer Characteristic
7.3.2 Analog Inputs
图 7-2 shows an equivalent circuit for one of the input channels of the ADC128S102-SEP. Diodes D1 and D2
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going
beyond this range causes the ESD diodes to conduct and results in erratic operation.
Capacitor C1 in 图 7-2 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the
ON-resistance of the multiplexer and track-and-hold switch and is typically 500 Ω. Capacitor C2 is the
ADC128S102-SEP sampling capacitor, and is typically 30 pF. The ADC128S102-SEP delivers best performance
when driven by a low-impedance source (less than 100 Ω). This source is especially important when using the
ADC128S102-SEP to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or
low-pass filter, which reduces harmonics and noise in the input. These filters are often referred to as antialiasing
filters.
VA
C2
D1
30 pF
R1
VIN
C1
3 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
图7-2. Equivalent Input Circuit
7.3.3 Digital Inputs and Outputs
The digital inputs of the ADC128S102-SEP (SCLK, CS, and DIN) have an operating range of 0 V to VA. The
inputs are not prone to latch-up and can be asserted before the digital supply (VD) without any risk. The digital
output (DOUT) operating range is controlled by VD. The output high voltage is VD – 0.5 V (minimum) when the
output low voltage is 0.4 V (maximum).
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
7.3.4 Radiation Environments
Careful consideration must be given to environmental conditions when using a product in a radiation
environment.
7.3.4.1 Total Ionizing Dose
Testing and qualification of these products is done on a wafer level according to MIL-STD-883G, Test Method
1019.7. Testing is done according to condition A and the extended room temperature anneal test described in
section 3.11 for application environment dose rates less than 51.61 rad(Si)/s. Wafer level TID data are available
with lot shipments.
7.3.4.2 Single Event Latch-Up
One-time single event latch-up (SEL) was preformed according to EIA/JEDEC Standard, EIA/JEDEC57. The
linear energy transfer threshold (LETth) shown in the 特性 section is the maximum LET tested. A test report is
available upon request.
7.4 Device Functional Modes
7.4.1 ADC128S102-SEP Operation
Simplified schematics of the ADC128S102-SEP in both track and hold operation are provided in 图 7-3 and 图
7-4, respectively. In 图 7-3, the ADC128S102-SEP is in track mode: switch SW1 connects the sampling
capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator
inputs. The ADC128S102-SEP is in this state for the first three SCLK cycles after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
R
CAPACITO
SW1
+
-
IN7
CONTROL
LOGIC
SW2
AGND
V /2
A
图7-3. ADC128S102-SEP in Track Mode
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
图 7-4 shows the ADC128S102-SEP in hold mode: switch SW1 connects the sampling capacitor to ground,
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC128S102-SEP is in this state for the last 13 SCLK cycles
after CS is brought low.
IN0
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1
+
-
IN7
CONTROL
LOGIC
SW2
AGND
V
A
/2
图7-4. ADC128S102-SEP in Hold Mode
7.5 Programming
7.5.1 Serial Interface
An operational timing diagram and a serial interface timing diagram for the ADC128S102-SEP are illustrated in
the Timing Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output
pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the control register
are placed on DIN, the serial data input pin. New data are written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain
an integer multiple of 16 rising SCLK edges. The ADC DOUT pin is in a high-impedance state when CS is high
and is active when CS is low. CS is asynchronous and therefore functions as an output enable. Similarly, SCLK
is internally gated off when CS is brought high.
During the first three SCLK cycles, the ADC is in track mode, acquiring the input voltage. For the next 13 SCLK
cycles the conversion is accomplished and the data are clocked out. SCLK falling edges 1 through 4 clock out
leading zeros and falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than one
conversion in a frame (continuous conversion mode), the ADC re-enters track mode on the SCLK falling edge
after the N × 16th SCLK rising edge and re-enters the hold/convert mode on the N × 16 + 4th SCLK falling edge.
N is an integer value.
The ADC128S102-SEP enters track mode under three different conditions. In 图 6-1, CS goes low with SCLK
high and the ADC enters track mode on the first SCLK falling edge. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the CS falling edge is taken as the
first SCLK falling edge. In the third condition, CS and SCLK go low simultaneously and the ADC enters track
mode. Although there is no timing restriction with respect to the falling edges of CS and SCLK, see 图 6-3 for
setup and hold time requirements for the CS falling edge with respect to the SCLK rising edge.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
During each conversion, data are clocked into a control register through the DIN pin on the first eight SCLK
rising edges after the fall of CS. As given in 表 7-1, 表 7-2, and 表 7-3, the control register is loaded with data
indicating the input channel to be converted on the subsequent conversion.
Although the ADC128S102-SEP can acquire the input signal to full resolution in the first conversion immediately
following power up, the first conversion result after power up is that of a randomly selected channel. Therefore,
incorporate a dummy conversion to set the required channel to be used on the subsequent conversion.
表7-1. Control Register Bits
BIT 7 (MSB)
DONTC
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DONTC
ADD2
ADD1
ADD0
DONTC
DONTC
DONTC
表7-2. Control Register Bit Descriptions
BIT
SYMBOL
DESCRIPTION
7, 6, 2, 1, 0 DONTC
Don't care. The values of these bits do not affect the device.
5
4
3
ADD2
ADD1
ADD0
These three bits determine which input channel is sampled and converted at the next conversion cycle. The
mapping between codes and channels is given in 表7-3.
表7-3. Input Channel Selection
ADD2
ADD1
ADD0
INPUT CHANNEL
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ADC128S102-SEP is a low-power, eight-channel, 12-bit ADC with specified performance specifications from
50 kSPS to 1 MSPS. The ADC128S102-SEP can be used at sample rates below 50 kSPS by powering the
device down (deasserting CS) in between conversions. The Electrical Characteristics table highlights the clock
frequency where ADC performance is specified. There is no limitation on periods of time for shutdown between
conversions.
8.2 Typical Application
图 8-1 shows a typical application block diagram. The split analog and digital supply pins are both powered in
this example by the Texas Instruments' LP2950-N low-dropout voltage regulator. The analog supply is bypassed
with a capacitor network located close to the ADC128S102-SEP. The digital supply is separated from the analog
supply by an isolation resistor and bypassed with additional capacitors. The ADC128S102-SEP uses the analog
supply (VA) as its reference voltage; thus, VA must be kept as clean as possible. Because of the low power
requirements of the ADC128S102-SEP, a precision reference can also be used as a power supply.
51W
LP2950
5V
1 mF
0.1 mF
1.0 mF
0.1 mF
1.0 mF
0.1 mF
VD
VA
22W
SCLK
CS
INPUT
IN0
.
.
.
MICROPROCESSOR
DSP
ADC128S102
1 nF
DIN
IN7
DOUT
DGND
AGND
图8-1. Typical Application Circuit
8.2.1 Design Requirements
A positive-supply-only data acquisition (DAQ) system is capable of digitizing up to eight single-ended input
signals ranging from 0 V to 5 V with BW = 10 kHz and a throughput up to 500 kSPS. The ADC128S102-SEP
must interface to an MCU whose supply is set at 5 V. To interface with an MCU that operates at 3.3 V or lower,
VA and VD must be separated and care must be taken to ensure that VA is powered before VD.
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
8.2.2 Detailed Design Procedure
The signal range requirement forces the design to use a 5-V analog supply at VA, the analog supply. This
requirement stems from the fact that VA is also a reference potential for the ADC. If the requirement of
interfacing to the MCU changes to 3.3 V, the VD supply voltage must also change to 3.3 V. The maximum
sampling rate of the ADC128S102-SEP when all channels (eight) are enabled is fS = fSCLK / (16 × 8).
Faster sampling rates can be achieved when fewer channels are sampled. A single channel can be sampled at
the maximum rate of fS (single) = fSCLK / 16.
The VA and VD pins are separated by a 51-Ω resistor to minimize digital noise from corrupting the analog
reference input. If additional filtering is required, the resistor can be replaced by a ferrite bead, thus achieving a
second-order filter response. Further noise consideration can be provided to the SPI interface, especially when
the controller MCU is capable of producing fast rising edges on the digital bus signals. Inserting small
resistances in the digital signal path can help reduce ground bounce, and thus improve overall noise
performance of the system. Care must be taken when the signal source is capable of producing voltages beyond
VA. In such instances, the internal ESD diodes can start conducting. The ESD diodes are not intended as input
signal clamps. To provide the desired clamping action, use Schottky diodes.
8.2.3 Application Curve
图8-2. ENOB vs Temperature
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
9 Power Supply Recommendations
There are three major power supply concerns with this product: power-supply sequencing, power management,
and the effect of digital supply noise on the analog supply.
9.1 Power-Supply Sequence
The ADC128S102-SEP is a dual-supply device. The two supply pins share ESD resources, so care must be
exercised to ensure that power is applied in the correct sequence. To avoid turning on the ESD diodes, the
digital supply (VD) cannot exceed the analog supply (VA) by more than 300 mV. Therefore, VA must ramp up
before or concurrently with VD.
9.2 Power Management
The ADC128S102-SEP is fully powered up when CS is low and is fully powered down when CS is high, with one
exception. If operating in continuous conversion mode, the ADC128S102-SEP automatically enters power-down
mode between the 16th SCLK falling edge of a conversion and the 1st SCLK falling edge of the subsequent
conversion (see 图6-1).
In continuous conversion mode, the ADC128S102-SEP can perform multiple conversions back to back. Each
conversion requires 16 SCLK cycles and the ADC128S102-SEP performs conversions continuously as long as
CS is held low. Continuous mode offers maximum throughput.
In burst mode, throughput can be traded off for power consumption by performing fewer conversions per unit
time. In other words, more time is spent in power-down mode and less time is spent in normal mode. By using
this technique, very low sample rates can be achieved while still using an SCLK frequency within the electrical
specifications. To calculate the power consumption (PC), simply multiply the fraction of time spent in normal
mode (tN) by the normal mode power consumption (PN), as shown in 方程式1, and add the fraction of time spent
in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS).
tN
tS
PC =
´PN +
´PS
tN + tS
tN + tS
(1)
9.3 Power-Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses
required from the supply to charge the output capacitance cause voltage variations on the digital supply. If these
variations are large enough, they can degrade SNR and SINAD performance of the ADC. Furthermore, if the
analog and digital supplies are tied directly together, the noise on the digital supply is coupled directly into the
analog supply, causing greater performance degradation than noise alone causes on the digital supply. Similarly,
discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current
into the die substrate, which is resistive. Load discharge currents cause ground bounce noise in the substrate
that degrades noise performance if that current is large enough. The larger the output capacitance, the more
current flows through the die substrate and the greater the noise coupled into the analog channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at
the ADC output, located as close to the ADC output pin as practical. This resistor limits the charge and discharge
current of the output capacitance and improves noise performance. Because the series resistor and the load
capacitance form a low-frequency pole, verify signal integrity when the series resistor is added.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: ADC128S102-SEP
ADC128S102-SEP
ZHCSNM2A –DECEMBER 2021 –REVISED APRIL 2022
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as
short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated can have
significant impact upon system noise performance. To avoid performance degradation of the ADC128S102-SEP
resulting from supply noise, do not use the same supply for the ADC128S102-SEP that is used for digital logic.
Generally, analog and digital lines cross each other at 90° to avoid crosstalk. However, to maximize accuracy in
high-resolution systems, avoid crossing analog and digital lines altogether. Clock lines must be kept as short as
possible and isolated from all other lines, including other digital lines. In addition, the clock line must be treated
as a transmission line and be properly terminated.
Isolate the analog input from noisy signal traces to avoid coupling of spurious signals into the input. Any external
component (for example, a filter capacitor) connected between the converter input pins and ground or to the
reference input pin and ground must be connected to a very clean point in the ground plane.
Use a single, uniform ground plane and split power planes. The power planes must be located within the same
board layer. Place all analog circuitry (input amplifiers, filters, reference components, and so forth) over the
analog power plane. Place all digital circuitry and I/O lines over the digital power plane. Furthermore, all
components in the reference circuitry and the input signal chain that are connected to ground must be connected
together with short traces and enter the analog ground plane at a single, quiet point.
10.2 Layout Example
ANALOG
SUPPLY
RAIL
CS
VA
SCLK
DOUT
DIN
toMCU
AGND
IN0
VD
^5LDLÇ
ADC128S102WG-QV
IC SUCCESSIVE APPROXIMATION ADC, CDSO16, CERRAMIC, SOIC-16, Analog to Digital Converter
NSC
ADC128S102WGMLS
IC 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDSO16, CERRAMIC, SOIC-16, Analog to Digital Converter
NSC
©2020 ICPDF网 联系我们和版权申明