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ADC128S102WGRQV [TI]

耐辐射、八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | NAC | 16 | -55 to 125;
ADC128S102WGRQV
型号： ADC128S102WGRQV
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

耐辐射、八通道、50kSPS 至 1MSPS、12 位模数转换器 (ADC) | NAC | 16 | -55 to 125

转换器 模数转换器
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ADC128S102QML-SP  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
ADC128S102QML-SP Radiation Hardened 8-Channel, 50 kSPS to 1 MSPS, 12-Bit A/D  
Converter  
1 Features  
3 Description  
The ADC128S102 device is a low-power, eight-  
channel CMOS 12-bit analog-to-digital converter  
specified for conversion throughput rates of 50 kSPS  
to 1 MSPS. The converter is based on a successive-  
approximation register architecture with an internal  
track-and-hold circuit. The device can be configured  
to accept up to eight input signals at inputs IN0  
through IN7.  
1
•
5962R07227  
–
–
Total Ionizing Dose 100 krad(Si)  
Single Event Latch-Up Immune 120 MeV-  
cm2/mg  
–
Single Event Functional Interrupt Immune 120  
MeV-cm2/mg  
(See Radiation Report)  
The output serial data is straight binary and is  
compatible with several standards, such as SPI,  
QSPI, MICROWIRE, and many common DSP serial  
interfaces.  
•
•
•
•
•
•
Eight Input Channels  
Variable Power Management  
Independent Analog and Digital Supplies  
SPI™/QSPI™/MICROWIRE™/DSP Compatible  
Packaged in 16-Lead Ceramic SOIC  
Key Specifications  
The ADC128S102 may be operated with independent  
analog and digital supplies. The analog supply (VA)  
can range from 2.7 V to 5.25 V, and the digital supply  
(VD) can range from 2.7 V to VA. Normal power  
consumption using a 3-V or 5-V supply is 2.3 mW  
and 10.7 mW, respectively. The power-down feature  
reduces the power consumption to 0.06 µW using a  
3-V supply and 0.25 µW using a 5-V supply.  
–
–
Conversion Rate: 50 kSPS to 1 MSPS  
DNL (VA = VD = 5 V): +1.5 / −0.9 LSB  
(Maximum)  
–
–
INL (VA = VD = 5 V): +1.4 / −1.25 LSB  
(Maximum)  
Device Information(1)  
Power Consumption  
PART NUMBER  
GRADE  
PACKAGE  
–
–
3-V Supply: 2.3 mW (Typical)  
5-V Supply: 10.7 mW (Typical)  
5962R0722701VZA  
100 krad  
ADC128S102WGRQV  
16-lead ceramic SOIC  
5962R0722701VFA  
100 krad  
ADC128S102WRQV  
ADC128S102-MDR  
16-lead ceramic flatpack  
Die  
2 Applications  
5962R0722701V9A  
100 krad  
•
Satellites  
Pre-Flight  
ADC128S102WGMPR Engineering  
Prototype  
–
–
–
Attitude and Orbit Control  
16-lead ceramic SOIC  
Precision Sensors  
Motor Control  
Ceramic Evaluation  
Board  
ADC128S102CVAL  
•
•
•
High Temperature  
Medical Systems  
Accelerators  
(1) For all available packages, see the orderable addendum at  
the end of the data sheet.  
Block Diagram  
IN0  
VA  
.
.
.
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
MUX  
T/H  
AGND  
AGND  
IN7  
VD  
SCLK  
ADC128S102  
CS  
CONTROL  
LOGIC  
DIN  
DOUT  
DGND  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 
 
 
ADC128S102QML-SP  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
www.ti.com  
Table of Contents  
7.5 Programming........................................................... 19  
Application and Implementation ........................ 21  
8.1 Application Information............................................ 21  
8.2 Typical Application ................................................. 21  
Power Supply Recommendations...................... 23  
9.1 Power Supply Sequence......................................... 23  
9.2 Power Management................................................ 23  
9.3 Power Supply Noise Considerations....................... 23  
1
2
3
4
5
6
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configuration and Functions......................... 4  
Specifications......................................................... 5  
6.1 Absolute Maximum Ratings ...................................... 5  
6.2 ESD Ratings.............................................................. 5  
6.3 Recommended Operating Conditions....................... 5  
6.4 Thermal Information.................................................. 6  
8
9
10 Layout................................................................... 24  
10.1 Layout Guidelines ................................................. 24  
10.2 Layout Example .................................................... 24  
11 Device and Documentation Support ................. 25  
11.1 Device Support .................................................... 25  
11.2 Receiving Notification of Documentation Updates 26  
11.3 Community Resources.......................................... 26  
11.4 Trademarks........................................................... 26  
11.5 Electrostatic Discharge Caution............................ 26  
11.6 Glossary................................................................ 26  
6.5 Electrical Characteristics: ADC128S102QML-SP  
Converter ................................................................... 6  
6.6 Electrical Characteristics: Radiation ......................... 8  
6.7 Electrical Characteristics: Burn in Delta Parameters -  
TA at 25°C.................................................................. 9  
6.8 Timing Requirements................................................ 9  
6.9 Typical Characteristics............................................ 11  
Detailed Description ............................................ 16  
7.1 Overview ................................................................. 16  
7.2 Functional Block Diagram ....................................... 16  
7.3 Feature Description................................................. 16  
7.4 Device Functional Modes........................................ 18  
7
12 Mechanical, Packaging, and Orderable  
Information ........................................................... 27  
12.1 Engineering Samples............................................ 27  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision O (November 2016) to Revision P  
Page  
•
Changed feature link from 5962R07727 to 5962R07227....................................................................................................... 1  
Changes from Revision N (September 2015) to Revision O  
Page  
•
•
•
•
•
•
•
•
•
•
•
Changed the title of the ADC128S102QML-SP data sheet ................................................................................................... 1  
Added Radiation Report link to Features ............................................................................................................................... 1  
Changed Applications............................................................................................................................................................. 1  
Changed Device Information table ........................................................................................................................................ 1  
Added 14-pin CFP package option to the data sheet ........................................................................................................... 1  
Added TYPE column to the Pin Functions table ................................................................................................................... 4  
Added tablenote for digital supply voltage maximums allowed in the Absolute Maximum Ratings table.............................. 5  
Updated maximum tablenote for the digital supply voltage in the Absolute Maximum Ratings table.................................... 5  
Added tablenote for the voltage on any pin to GND maximums allowed in the Absolute Maximum Ratings table............... 5  
Added links to the Quality Conformance Inspection table to the Electrical Characteristics tables ........................................ 6  
Added MIN and MAX test conditions for the SCLK duty cycle in the Electrical Characteristics: ADC128S102QML-SP  
Converter table ....................................................................................................................................................................... 8  
•
•
•
•
•
•
Changed ADC128S102 Operational Timing Diagram image ............................................................................................... 10  
Changed first sentence and added MIL-STD-883G, Test Method 1019.7 link to the Total Ionizing Dose section.............. 18  
Changed total ionizing dose rate from 0.16 to 0.027 rad(Si)/s............................................................................................. 18  
Changed Single Event Latch-Up section to Single Event Latch-Up and Functional Interrupt ............................................. 18  
Added sentence to Serial Interface section: Note that CS is asynchronous........................................................................ 19  
Added Engineering Samples section.................................................................................................................................... 27  
2
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Copyright © 2008–2017, Texas Instruments Incorporated  
Product Folder Links: ADC128S102QML-SP  
 
ADC128S102QML-SP  
www.ti.com  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
Changes from Revision H (October 2009) to Revision N  
Page  
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional  
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device  
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1  
Changes from Revision G (October 2009) to Revision H  
Page  
•
•
•
•
Added reference to Note 11. ................................................................................................................................................. 5  
Added Note:11........................................................................................................................................................................ 5  
Deleted 'TYPICAL' numbers from tDHID, tDS and tDIH ............................................................................................................... 6  
Changed Min limit on tDHID from 11 to 7. ............................................................................................................................... 6  
Changes from Revision F (June 2009) to Revision G  
Page  
•
Deleted reference to Ta Min and Ta Max under titled sections. ........................................................................................... 6  
Changes from Revision E (April 2009) to Revision F  
Page  
•
Changed AC Electrical Characteristics - SCLK Duty Cycle, typ limits .................................................................................. 8  
Changes from Revision C (November 2008) to Revision D  
Page  
•
•
•
Moved Rad information from Key Specifications to Features ................................................................................................ 1  
Deleted ADC128S102WGMLS reference .............................................................................................................................. 6  
Added Burn In Delta Table ..................................................................................................................................................... 9  
Changes from Revision B (August 2008) to Revision C  
Page  
•
Corrected package reference from 16-lead TSSOP to 16-lead Ceramic SOIC, Removed QV NSID reference and  
Added SMD Number to RQV NSID in Features. ................................................................................................................... 1  
Changes from Revision A (August 2008) to Revision B  
Page  
•
Typo, Changed Figure 2, tDIS lower left hand side changed to tDS and tDIH lower left hand side change to tDH in  
Timing Diagrams. ................................................................................................................................................................ 10  
Copyright © 2008–2017, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: ADC128S102QML-SP  
ADC128S102QML-SP  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
www.ti.com  
5 Pin Configuration and Functions  
NAC Package  
16-Pin CFP  
Top View  
CS  
VA  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SCLK  
DOUT  
DIN  
AGND  
IN0  
VD  
IN1  
DGND  
IN7  
IN2  
IN3  
IN6  
IN4  
IN5  
Not to scale  
Pin Functions  
PIN  
TYPE  
DESCRIPTION  
NAME  
NO.  
ANALOG I/O  
4
5
6
7
Input  
(Analog)  
IN0 to IN7  
Analog inputs. These signals can range from 0 V to VREF.  
8
9
10  
11  
DIGITAL I/O  
Input  
Chip select. On the falling edge of CS, a conversion process begins. Conversions  
CS  
1
(Digital) continue as long as CS is held low.  
Input Digital data input. The ADC128S102QML-SP's Control Register is loaded through this  
(Digital) pin on rising edges of the SCLK pin.  
DIN  
14  
15  
16  
Output Digital data output. The output samples are clocked out of this pin on the falling edges  
(Digital) of the SCLK pin.  
DOUT  
SCLK  
Input  
Digital clock input. The specified performance range of frequencies for this input is 0.8  
(Digital) MHz to 16 MHz. This clock directly controls the conversion and readout processes.  
POWER SUPPLY  
AGND  
3
Ground The ground return for the analog supply and signals.  
Ground The ground return for the digital supply and signals.  
DGND  
12  
Positive analog supply pin. This voltage is also used as the reference voltage. This  
Supply pin should be connected to a quiet 2.7 V to 5.25 V source and bypassed to GND with  
1-µF and 0.1-µF monolithic ceramic capacitors located within 1 cm of the power pin.  
VA  
VD  
2
Positive digital supply pin. This pin should be connected to a 2.7 V to VA supply, and  
Supply bypassed to GND with a 0.1-µF monolithic ceramic capacitor located within 1 cm of  
the power pin.  
13  
4
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Copyright © 2008–2017, Texas Instruments Incorporated  
Product Folder Links: ADC128S102QML-SP  
ADC128S102QML-SP  
www.ti.com  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
6 Specifications  
6.1 Absolute Maximum Ratings(1)  
MIN  
–0.3  
–0.3  
–0.3  
MAX  
6.5  
UNIT  
V
VA  
VD  
Analog supply voltage  
Digital supply voltage(2)  
Voltage on any pin to GND  
VA + 0.3  
VA + 0.3  
±10  
V
V
(3)  
Input current at any pin  
mA  
(4)  
Power dissipation TA = 25°C  
Package input current(3)  
Soldering temperature, 10 seconds  
Junction temperature  
See  
±20 mA  
260  
mA  
°C  
°C  
°C  
175  
Tstg  
Storage temperature  
–65  
150  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating  
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The maximum voltage is not to exceed 6.5 V  
(3) When the input voltage at any pin exceeds the power supplies (that is, VIN less than AGND or VIN greater than VA or VD), the current at  
that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed  
the power supplies with an input current of 10 mA to two.  
(4) The absolute maximum junction temperature (TJmax) for this device is 175°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (RθJA), and the ambient temperature (TA), and can be calculated using the formula  
PDMAX = (TJmax − TA)/RθJA. The values for maximum power dissipation listed above will be reached only when the ADC128S102QML-  
SP is operated in a severe fault condition (for example, when input or output pins are driven beyond the power supply voltages, or the  
power supply polarity is reversed). Obviously, such conditions should always be avoided.  
6.2 ESD Ratings  
VALUE  
UNIT  
V(ESD)  
Electrostatic discharge  
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)  
±8000  
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.  
6.3 Recommended Operating Conditions  
(1)(2)  
See  
MIN  
–55  
2.7  
2.7  
0
MAX  
125  
5.25  
VA  
UNIT  
°C  
V
Operating temperature  
VA supply voltage  
VD supply voltage  
Digital input voltage  
Analog input voltage  
Clock frequency  
V
VA  
V
0
VA  
V
0.8  
16  
MHz  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate  
conditions for which the device is functional, but do not verify specific performance limits. For specifications and test conditions, see the  
Electrical Characteristics. The specified specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.  
Copyright © 2008–2017, Texas Instruments Incorporated  
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5
Product Folder Links: ADC128S102QML-SP  
 
ADC128S102QML-SP  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
www.ti.com  
6.4 Thermal Information  
ACD128S102QML-SP  
THERMAL METRIC(1)  
NAC (CFP)  
16 PINS  
127  
UNIT  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
°C/W  
°C/W  
RθJC(top)  
11.2  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
6.5 Electrical Characteristics: ADC128S102QML-SP Converter  
The following specifications apply for AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, CL =  
50pF, unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
SUBGROUP  
MIN TYP(1)  
MAX UNIT  
STATIC CONVERTER CHARACTERISTICS  
Resolution with no missing  
codes  
12  
Bits  
VA = VD = 3 V  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
–1  
±0.6  
±0.9  
0.5  
1.1  
1.4  
0.9  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
LSB  
Integral non-linearity (end  
point method)  
INL  
VA = VD = 5 V  
–1.25  
VA = VD = 3 V  
–0.7  
–0.3  
0.9  
DNL  
VOFF  
Differential non-linearity  
Offset error  
1.5  
VA = VD = 5 V  
–0.9  
–2.3  
–2.3  
–1.5  
–1.5  
–2  
−0.5  
0.8  
VA = VD = 3 V  
VA = VD = 5 V  
VA = VD = 3 V  
VA = VD = 5 V  
VA = VD = 3 V  
VA = VD = 5 V  
VA = VD = 3 V  
VA = VD = 5 V  
2.3  
2.3  
1.5  
1.5  
2
1.1  
±0.1  
±0.3  
0.8  
OEM Offset error match  
FSE  
Full scale error  
–2  
0.3  
2
–1.5  
–1.5  
±0.1  
±0.3  
1.5  
1.5  
FSEM Full scale error match  
DYNAMIC CONVERTER CHARACTERISTICS  
VA = VD = 3 V  
VA = VD = 5 V  
6.8  
10  
MHz  
MHz  
Full power bandwidth (–3  
dB)  
FPBW  
VA = VD = 3 V,  
fIN = 40.2 kHz, −0.02 dBFS  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
68  
68  
72  
72  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
SINA Signal-to-noise plus  
D
distortion ratio  
VA = VD = 5 V,  
fIN = 40.2 kHz, −0.02 dBFS  
VA = VD = 3 V,  
fIN = 40.2 kHz, −0.02 dBFS  
69  
72  
SNR  
Signal-to-noise ratio  
VA = VD = 5 V,  
fIN = 40.2 kHz, −0.02 dBFS  
68.5  
72  
VA = VD = 3 V,  
fIN = 40.2 kHz, −0.02 dBFS  
–86  
–87  
91  
–74  
–74  
THD  
Total harmonic distortion  
VA = VD = 5 V,  
fIN = 40.2 kHz, −0.02 dBFS  
VA = VD = 3 V,  
fIN = 40.2 kHz, −0.02 dBFS  
75  
75  
SFDR Spurious-free dynamic range  
VA = VD = 5 V,  
fIN = 40.2 kHz, −0.02 dBFS  
90  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms.  
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Copyright © 2008–2017, Texas Instruments Incorporated  
Product Folder Links: ADC128S102QML-SP  
ADC128S102QML-SP  
www.ti.com  
SNAS411P –AUGUST 2008–REVISED APRIL 2017  
Electrical Characteristics: ADC128S102QML-SP Converter (continued)  
The following specifications apply for AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, CL =  
50pF, unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
SUBGROUP  
MIN TYP(1)  
MAX UNIT  
VA = VD = 3 V,  
fIN = 40.2 kHz  
[4, 5, 6]  
11.1  
11.1  
11.6  
11.6  
84  
Bits  
ENOB Effective number of bits  
VA = VD = 5 V,  
fIN = 40.2 kHz, −0.02 dBFS  
[4, 5, 6]  
Bits  
dB  
VA = VD = 3 V,  
fIN = 20 kHz  
ISO  
IMD  
Channel-to-channel isolation  
VA = VD = 5 V,  
fIN = 20 kHz, −0.02 dBFS  
85  
dB  
VA = VD = 3 V,  
fa = 19.5 kHz, fb = 20.5 kHz  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
[4, 5, 6]  
–93  
–93  
–91  
–91  
–78  
–78  
–70  
–70  
dB  
dB  
dB  
dB  
Intermodulation distortion,  
second order terms  
VA = VD = 5 V,  
fa = 19.5 kHz, fb = 20.5 kHz  
VA = VD = 3 V,  
fa = 19.5 kHz, fb = 20.5 kHz  
Intermodulation distortion,  
third order terms  
VA = VD = 5 V,  
fa = 19.5 kHz, fb = 20.5 kHz  
ANALOG INPUT CHARACTERISTICS  
VIN  
Input range  
0 to VA  
±0.01  
38  
V
IDCL  
DC leakage current  
[1, 2, 3]  
±1  
µA  
pF  
pF  
(2)  
Track mode, see  
CINA  
Input capacitance  
(2)  
Hold mode, see  
4.5  
DIGITAL INPUT CHARACTERISTICS  
VA = VD = 2.7 V to 3.6 V  
VA = VD = 4.75 V to 5.25 V  
VA = VD = 2.7 V to 5.25 V  
VIN = 0 V or VD  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
2.1  
2.4  
V
V
VIH  
Input high voltage  
VIL  
Input low voltage  
Input current  
0.8  
±1  
V
IIN  
±1  
µA  
pF  
(2)  
CIND  
Digital input capacitance  
See  
3.5  
DIGITAL OUTPUT CHARACTERISTICS  
ISOURCE = 200 µA,  
VA = VD = 2.7 V to 5.25 V  
VD  
–0.5  
VOH  
VOL  
Output high voltage  
Output low voltage  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
V
V
ISINK = 200 µA to 1 mA,  
VA = VD = 2.7 V to 5.25 V  
0.4  
±1  
IOZH  
IOZL  
,
Hi-impedance output  
leakage current  
VA = VD = 2.7 V to 5.25 V  
±0.01  
µA  
pF  
Hi-impedance output  
capacitance  
(2)  
COUT  
See  
3.5  
Output coding  
Straight (Natural) Binary  
POWER SUPPLY CHARACTERISTICS (CL = 10 pF)  
[1, 2, 3]  
[1, 2, 3]  
2.7  
V
V
Analog and digital supply  
voltages  
VA, VD  
VA ≥ VD  
5.25  
VA = VD = 2.7 V to 3.6 V,  
fSAMPLE = 1 MSPS, fIN = 40 kHz  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
0.9  
2.2  
1.5  
3.1  
1
mA  
mA  
μA  
Total supply current,  
normal mode ( CS low)  
VA = VD = 4.75 V to 5.25 V,  
fSAMPLE = 1 MSPS, fIN = 40 kHz  
IA + ID  
VA = VD = 2.7 V to 3.6 V,  
fSCLK = 0 kSPS  
0.11  
0.12  
Total supply current,  
shutdown mode (CS high)  
VA = VD = 4.75 V to 5.25 V,  
fSCLK = 0 kSPS  
1.4  
μA  
(2) This parameter is specified by design and/or characterization and is not tested in production.  
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Electrical Characteristics: ADC128S102QML-SP Converter (continued)  
The following specifications apply for AGND = DGND = 0V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE = 50 kSPS to 1 MSPS, CL =  
50pF, unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
SUBGROUP  
MIN TYP(1)  
MAX UNIT  
VA = VD = 3 V  
fSAMPLE = 1 MSPS, fIN = 40 kHz  
[1, 2, 3]  
2.7  
4.5  
15.5  
3
mW  
mW  
µW  
µW  
Power consumption,  
normal mode ( CS low)  
VA = VD = 5 V  
fSAMPLE = 1 MSPS, fIN = 40 kHz  
[1, 2, 3]  
[1, 2, 3]  
[1, 2, 3]  
11.0  
0.33  
0.6  
PC  
VA = VD = 3 V  
fSCLK = 0 kSPS  
Power consumption,  
shutdown mode (CS high)  
VA = VD = 5 V  
fSCLK = 0 kSPS  
7
AC ELECTRICAL CHARACTERISTICS  
fSCLK  
Minimum clock frequency  
MIN  
VA = VD = 2.7 V to 5.25 V  
VA = VD = 2.7 V to 5.25 V  
[9, 10, 11]  
0.8  
50  
MHz  
fSCLK  
Maximum clock frequency  
[9, 10, 11]  
[9, 10, 11]  
[9, 10, 11]  
16  
MHz  
kSPS  
MSPS  
Sample rate continuous  
mode  
fS  
VA = VD = 2.7 V to 5.25 V  
VA = VD = 2.7 V to 5.25 V  
1
tCONVE  
RT  
SCLK  
cycles  
Conversion (hold) time  
SCLK duty cycle  
[9, 10, 11]  
13  
MIN  
40%  
60%  
VA = VD = 2.7 V to 5.25  
V
DC  
MAX  
SCLK  
cycles  
tACQ  
Acquisition (track) time  
VA = VD = 2.7 V to 5.25 V  
[9, 10, 11]  
[9, 10, 11]  
3
Acquisition time + conversion time  
VA = VD = 2.7 V to 5.25 V  
SCLK  
cycles  
Throughput time  
Aperture delay  
16  
tAD  
VA = VD = 2.7 V to 5.25 V  
4
ns  
6.6 Electrical Characteristics: Radiation  
The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE  
50 kSPS to 1 MSPS, and CL = 50 pF.(1)  
=
PARAMETER  
TEST CONDITIONS  
SUBGROUP  
MIN TYP  
MAX UNIT  
VA = VD = 2.7 V to 3.6 V,  
fSCLK = 0 kSPS  
[1]  
30  
µA  
Total supply current shutdown mode  
(CS high)  
IA + ID  
VA = VD = 4.75 V to 5.25 V,  
fSCLK = 0 kSPS  
[1]  
[1]  
100  
±10  
µA  
µA  
IOZH, IOZL  
Hi-impedance output leakage current  
VA = VD = 2.7 V to 5.25 V  
(1) Pre and post irradiation limits are identical to those listed in the DC Parameters and AC and Timing Characteristics, except as listed in  
Electrical Characteristics: Radiation. When performing post irradiation electrical measurements for any RHA level, TA = 25°C.  
8
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6.7 Electrical Characteristics: Burn in Delta Parameters - TA at 25°C  
The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE  
50 kSPS to 1 MSPS, and CL = 50 pF.(1)  
=
PARAMETER  
TEST CONDITIONS  
VA = VD = 3 V  
MIN  
–0.5  
–0.35  
–14  
TYP  
0.106  
0.016  
1.35  
1.67  
0.47  
0.9  
MAX  
0.5  
0.35  
14  
UNIT  
LSB  
LSB  
dB  
INL  
Integral non-linearity  
VA = VD = 5 V  
VA = VD = 3 V  
VA = VD = 5 V  
VA = VD = 3 V  
VA = VD = 5 V  
Intermodulation distortion,  
second order terms  
IMD  
IMD  
–17  
17  
dB  
–10  
10  
dB  
Intermodulation distortion, third  
order terms  
–10  
10  
dB  
(1) This is worse case drift, Deltas are performed at room temperature post operational life. All other parameters, no deltas are required.  
6.8 Timing Requirements  
The following specifications apply for VA = VD = 2.7 V to 5.25 V, AGND = DGND = 0 V, fSCLK = 0.8 MHz to 16 MHz, fSAMPLE  
50 kSPS to 1 MSPS, and CL = 50 pF.  
=
SUBGROUP  
MIN  
NOM(1)  
MAX  
UNIT  
CS hold time after SCLK rising  
edge  
(2)  
(2)  
tCSH  
tCSS  
See  
See  
[9, 10, 11]  
10  
0
ns  
ns  
CS setup time prior to SCLK  
rising edge  
[9, 10, 11]  
10  
4.5  
tEN  
CS falling edge to DOUT enabled  
[9, 10, 11]  
[9, 10, 11]  
[9, 10, 11]  
[9, 10, 11]  
[9, 10, 11]  
5
30  
27  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDACC  
tDHLD  
tDS  
DOUT access time after SCLK falling edge  
DOUT hold time after SCLK falling edge  
DIN setup time prior to SCLK rising edge  
DIN hold time after SCLK rising edge  
SCLK high time  
17  
7
10  
10  
tDH  
tCH  
0.4 × tSCLK  
0.4 × tSCLK  
2.4  
tCL  
SCLK low time  
DOUT falling  
DOUT rising  
[9, 10, 11]  
[9, 10, 11]  
20  
20  
CS rising edge to DOUT high-  
impedance  
tDIS  
0.9  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms.  
(2) Clock may be in any state (high or low) when CS goes high. Setup and hold time restrictions apply only to CS going low.  
Table 1. Quality Conformance Inspection(1)  
SUBGROUP  
DESCRIPTION  
Static tests at  
TEMP (°C)  
25  
1
2
Static tests at  
125  
–55  
25  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
Setting time at  
5
125  
–55  
25  
6
7
8A  
8B  
9
125  
–55  
25  
10  
11  
12  
13  
14  
125  
–55  
25  
Setting time at  
125  
–55  
Setting time at  
(1) MIL-STD-883, Method 5005 - Group A  
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Power  
Down  
Power Up  
Power Up  
Hold  
Track  
Track  
Hold  
10  
CS  
8
9
11  
12  
13  
14  
15  
16  
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
SCLK  
Control register N  
Control register N + 1  
ADD2 ADD1 ADD0  
ADD2 ADD1 ADD0  
DIN  
Data N œ 1  
Data N  
DOUT  
FOUR ZEROS  
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
FOUR ZEROS  
DB11 DB10 DB9  
Figure 1. ADC128S102 Operational Timing Diagram  
CS  
tCONVERT  
tACQ  
tCH  
SCLK  
1
2
3
4
5
6
7
8
16  
tCL  
tDACC  
tDHLD  
tDIS  
tEN  
DB11  
DB10  
DB1  
DB0  
DOUT  
DIN  
FOUR ZEROS  
tDH  
DB9  
DB8  
tDS  
DONTC  
DONTC DONTC  
ADD2  
ADD1  
ADD0  
DONTC DONTC  
Figure 2. ADC128S102 Serial Timing Diagram  
SCLK  
t
CSS  
CS  
CS  
t
CSH  
Figure 3. SCLK and CS Timing Parameters  
10  
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6.9 Typical Characteristics  
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.  
Figure 4. DNL  
Figure 5. DNL  
Figure 6. INL  
Figure 7. INL  
Figure 8. DNL vs Supply  
Figure 9. INL vs Supply  
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Typical Characteristics (continued)  
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.  
Figure 10. SNR vs Supply  
Figure 11. THD vs Supply  
Figure 12. ENOB vs Supply  
Figure 13. DNL vs SCLK Duty Cycle  
Figure 14. INL vs SCLK Duty Cycle  
Figure 15. SNR vs SCLK Duty Cycle  
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Typical Characteristics (continued)  
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.  
Figure 16. THD vs SCLK Duty Cycle  
Figure 17. ENOB vs SCLK Duty Cycle  
Figure 18. DNL vs SCLK  
Figure 19. INL vs SCLK  
Figure 20. DNL vs SCLK  
Figure 21. INL vs SCLK  
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Typical Characteristics (continued)  
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.  
Figure 22. SNR vs SCLK  
Figure 24. THD vs SCLK  
Figure 26. ENOB vs SCLK  
Figure 23. SNR vs SCLK  
Figure 25. THD vs SCLK  
Figure 27. ENOB vs SCLK  
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Typical Characteristics (continued)  
TA = 25°C, fSAMPLE = 1 MSPS, fSCLK = 16 MHz, fIN = 40.2 kHz unless otherwise stated.  
Figure 28. ENOB vs Temperature  
Figure 29. DNL vs Temperature  
Figure 30. INL vs Temperature  
Figure 31. SNR vs Temperature  
Figure 32. THD vs Temperature  
Figure 33. Power Consumption vs SCLK  
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7 Detailed Description  
7.1 Overview  
The ADC128S102 is a successive-approximation analog-to-digital converter designed around a charge  
redistribution digital-to-analog converter.  
7.2 Functional Block Diagram  
IN0  
VA  
.
.
.
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
MUX  
T/H  
AGND  
AGND  
IN7  
VD  
SCLK  
ADC128S102  
CS  
CONTROL  
LOGIC  
DIN  
DOUT  
DGND  
7.3 Feature Description  
7.3.1 ADC128S102 Transfer Function  
The output format of the ADC128S102 is straight binary. Code transitions occur midway between successive  
integer LSB values. The LSB width for the ADC128S102 is VA / 4096. The ideal transfer characteristic is shown  
in Figure 34. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,  
or a voltage of VA / 8192. Other code transitions occur at steps of one LSB.  
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Feature Description (continued)  
111...111  
111...110  
111...000  
ö
1LSB = VA/4096  
011...111  
000...010  
000...001  
000...000  
+VA - 1.5LSB  
0.5LSB  
0ë  
!b![hD LbtÜÇ  
Figure 34. Ideal Transfer Characteristic  
7.3.2 Analog Inputs  
An equivalent circuit for one of the input channels of the ADC128S102 is shown in Figure 35. Diodes D1 and D2  
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going  
beyond this range will cause the ESD diodes to conduct and result in erratic operation.  
The capacitor C1 in Figure 35 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1  
is the ON-resistance of the multiplexer and track or hold switch and is typically 500 Ω. Capacitor C2 is the  
ADC128S102 sampling capacitor, and is typically 30 pF. The ADC128S102 will deliver best performance when  
driven by a low-impedance source (less than 100 Ω). This is especially important when using the ADC128S102  
to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-pass filter  
which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing filters.  
VA  
/2  
51  
30 pC  
w1  
VIN  
/1  
3 pC  
52  
/onversion thase - {ꢀiꢁch ꢂpen  
Çrack thase - {ꢀiꢁch /losed  
Figure 35. Equivalent Input Circuit  
7.3.3 Digital Inputs and Outputs  
The digital inputs of the ADC128S102 (SCLK, CS, and DIN) have an operating range of 0 V to VA. The inputs are  
not prone to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output  
(DOUT) operating range is controlled by VD. The output high voltage is VD – 0.5 V (minimum) while the output  
low voltage is 0.4 V (maximum).  
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Feature Description (continued)  
7.3.4 Radiation Environments  
Careful consideration should be given to environmental conditions when using a product in a radiation  
environment.  
7.3.4.1 Total Ionizing Dose  
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level listed in  
the Device Information table in the Description section. Testing and qualification of these products is done on a  
wafer level according to MIL-STD-883G, Test Method 1019.7. Testing is done according to Condition A and the  
Extended room temperature anneal test described in section 3.11 for application environment dose rates less  
than 0.027 rad(Si)/s. Wafer level TID data is available with lot shipments.  
7.3.4.2 Single Event Latch-Up and Functional Interrupt  
One-time single event latch-up (SEL) and single event functional interrupt (SEFI) testing was preformed  
according to EIA/JEDEC Standard, EIA/JEDEC57. The linear energy transfer threshold (LETth) shown in  
Features is the maximum LET tested. A test report is available upon request.  
7.3.4.3 Single Event Upset  
A report on single event upset (SEU) is available upon request.  
7.4 Device Functional Modes  
7.4.1 ADC128S102 Operation  
Simplified schematics of the ADC128S102 in both track and hold operation are shown in Figure 36 and Figure 37  
respectively. In Figure 36, the ADC128S102 is in track mode: switch SW1 connects the sampling capacitor to  
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The  
ADC128S102 is in this state for the first three SCLK cycles after CS is brought low.  
Figure 37 shows the ADC128S102 in hold mode: switch SW1 connects the sampling capacitor to ground,  
maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs  
the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until  
the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital  
representation of the analog input voltage. The ADC128S102 is in this state for the last thirteen SCLK cycles  
after CS is brought low.  
IN0  
CHARGE  
REDISTRIBUTION  
DAC  
MUX  
SAMPLING  
R
CAPACITO  
SW1  
+
-
IN7  
CONTROL  
LOGIC  
SW2  
AGND  
V /2  
A
Figure 36. ADC128S102 in Track Mode  
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Device Functional Modes (continued)  
IN0  
CHARGE  
REDISTRIBUTION  
DAC  
MUX  
SAMPLING  
CAPACITOR  
SW1  
+
IN7  
CONTROL  
LOGIC  
-
SW2  
AGND  
V
/2  
A
Figure 37. ADC128S102 in Hold Mode  
7.5 Programming  
7.5.1 Serial Interface  
An operational timing diagram and a serial interface timing diagram for the ADC128S102 are shown in Figure 1  
to Figure 3. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock)  
controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a  
conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC128S102's Control  
Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.  
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain  
an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high  
and is active when CS is low. Note that CS is asynchronous. Thus, CS acts as an output enable. Similarly, SCLK  
is internally gated off when CS is brought high.  
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13  
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock  
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than  
one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling  
edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N×16+4th falling  
edge of SCLK. "N" is an integer value.  
The ADC128S102 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high  
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with  
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as  
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters  
track mode. While there is no timing restriction with respect to the falling edges of CS and SCLK, see Figure 3  
for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.  
During each conversion, data is clocked into a control register through the DIN pin on the first 8 rising edges of  
SCLK after the fall of CS. The control register is loaded with data indicating the input channel to be converted on  
the subsequent conversion (see Table 2, Table 3, and Table 4).  
Although the ADC128S102 is able to acquire the input signal to full resolution in the first conversion immediately  
following power-up, the first conversion result after power-up will be that of a randomly selected channel.  
Therefore, the user needs to incorporate a dummy conversion to set the required channel that will be used on  
the subsequent conversion.  
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Programming (continued)  
Table 2. Control Register Bits  
BIT 7 (MSB)  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
BIT 0  
DONTC  
DONTC  
ADD2  
ADD1  
ADD0  
DONTC  
DONTC  
DONTC  
Table 3. Control Register Bit Descriptions  
BIT  
SYMBOL  
DESCRIPTION  
Don't care. The values of these bits do not affect the device.  
7, 6, 2, 1, 0 DONTC  
5
4
3
ADD2  
ADD1  
ADD0  
These three bits determine which input channel will be sampled and converted at the next conversion cycle.  
The mapping between codes and channels is shown in Table 4.  
Table 4. Input Channel Selection  
ADD2  
ADD1  
ADD0  
INPUT CHANNEL  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IN0  
IN1  
IN2  
IN3  
IN4  
IN5  
IN6  
IN7  
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8 Application and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
8.1 Application Information  
The ADC128S102 device is a low-power, eight-channel 12-bit ADC with ensured performance specifications from  
50 kSPS to 1 MSPS. It is appropriate to utilize the ADC128S102 at sample rates below 50 kSPS by powering the  
device down (de-asserting CSB) in between conversions. The Electrical Characteristics information highlights the  
clock frequency where the ADC’s performance is ensured. There is no limitation on periods of time for shutdown  
between conversions.  
8.2 Typical Application  
A typical application is shown in Figure 38. The split analog and digital supply pins are both powered in this  
example by the Texas Instruments LP2950-N low-dropout voltage regulator. The analog supply is bypassed with  
a capacitor network located close to the ADC128S102. The digital supply is separated from the analog supply by  
an isolation resistor and bypassed with additional capacitors. The ADC128S102 uses the analog supply (VA) as  
its reference voltage, so it is very important that VA be kept as clean as possible. Due to the low power  
requirements of the ADC128S102, it is also possible to use a precision reference as a power supply.  
51W  
LP2950  
5V  
1 mF  
0.1 mF  
1.0 mF  
0.1 mF  
1.0 mF  
0.1 mF  
VD  
VA  
22W  
SCLK  
CS  
INPUT  
IN0  
.
.
.
MICROPROCESSOR  
DSP  
ADC128S102  
1 nF  
DIN  
IN7  
DOUT  
DGND  
AGND  
Figure 38. Typical Application Circuit  
8.2.1 Design Requirements  
A positive supply only data acquisition system capable of digitizing up to eight single-ended input signals ranging  
from 0 to 5 V with BW = 10 kHz and a throughput up to 500 kSPS. The ADC128S102 has to interface to an MCU  
whose supply is set at 5 V. If it is necessary to interface with an MCU that operates at 3.3 V or lower, VA and VD  
will need to be separated and care must be taken to ensure that VA is powered before VD.  
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Typical Application (continued)  
8.2.2 Detailed Design Procedure  
The signal range requirement forces the design to use 5-V analog supply at VA, analog supply. This follows from  
the fact that VA is also a reference potential for the ADC. If the requirement of interfacing to the MCU changes to  
3.3-V, it will be necessary to change the VD supply voltage to 3.3 V. The maximum sampling rate of the  
ADC128S102 when all channels (eight) are enabled is, Fs = FSCLK / (16 × 8).  
Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be  
sampled at the maximum rate of Fs (single) = FSCLK / 16.  
The VA and VD pins are separated by a 51-Ω resistor in order to minimize digital noise from corrupting the  
analog reference input. If additional filtering is required, the resistor can be replaced by a ferrite bead, thus  
achieving a 2nd-order filter response. Further noise consideration could be given to the SPI interface, especially  
when the master MCU is capable of producing fast rising edges on the digital bus signals. Inserting small  
resistances in the digital signal path may help in reducing the ground bounce, and thus improve the overall noise  
performance of the system. Care should be taken when the signal source is capable of producing voltages  
beyond VA. In such instances, the internal ESD diodes may start conducting. The ESD diodes are not intended  
as input signal clamps. To provide the desired clamping action use Schottky diodes.  
8.2.3 Application Curve  
Figure 39. ENOB vs Temperature  
22  
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9 Power Supply Recommendations  
There are three major power supply concerns with this product: power supply sequencing, power management,  
and the effect of digital supply noise on the analog supply.  
9.1 Power Supply Sequence  
The ADC128S102 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised  
to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital  
supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, during a conversion cycle. Therefore,  
VA must ramp up before or concurrently with VD.  
9.2 Power Management  
The ADC128S102 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with  
one exception. If operating in continuous conversion mode, the ADC128S102 automatically enters power-down  
mode between SCLK's 16th falling edge of a conversion and SCLK's 1st falling edge of the subsequent  
conversion (see Figure 1).  
In continuous conversion mode, the ADC128S102 can perform multiple conversions back to back. Each  
conversion requires 16 SCLK cycles and the ADC128S102 will perform conversions continuously as long as CS  
is held low. Continuous mode offers maximum throughput.  
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per  
unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this  
technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical  
specifications. The Power Consumption versus SCLK curve in the Typical Characteristics shows the typical  
power consumption of the ADC128S102. To calculate the power consumption (PC), simply multiply the fraction of  
time spent in the normal mode (tN) by the normal mode power consumption (PN), and add the fraction of time  
spent in shutdown mode (tS) multiplied by the shutdown mode power consumption (PS) as shown in Equation 1.  
tN  
tS  
PC =  
´PN +  
´PS  
tN + tS  
tN + tS  
(1)  
9.3 Power Supply Noise Considerations  
The charging of any output load capacitance requires current from the digital supply, VD. The current pulses  
required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If  
these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if  
the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly  
into the analog supply, causing greater performance degradation than would noise on the digital supply alone.  
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will  
dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise  
in the substrate that will degrade noise performance if that current is large enough. The larger the output  
capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog  
channel.  
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies  
from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load  
capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100-Ω series resistor at  
the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge  
current of the output capacitance and improve noise performance. Because the series resistor and the load  
capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.  
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10 Layout  
10.1 Layout Guidelines  
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor  
performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as  
short as possible.  
Digital circuits create substantial supply and ground current transients. The logic noise generated could have  
significant impact upon system noise performance. To avoid performance degradation of the ADC128S102 due  
to supply noise, do not use the same supply for the ADC128S102 that is used for digital logic.  
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize  
accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep  
clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the  
clock line should also be treated as a transmission line and be properly terminated.  
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.  
Any external component (for example, a filter capacitor) connected between the converter's input pins and  
ground or to the reference input pin and ground should be connected to a very clean point in the ground plane.  
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes  
should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference  
components, and so forth) should be placed over the analog power plane. All digital circuitry and I/O lines should  
be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input  
signal chain that are connected to ground should be connected together with short traces and enter the analog  
ground plane at a single, quiet point.  
10.2 Layout Example  
!b![hD  
{Ütt[ò  
w!L[  
/{  
ë!  
{/[Y  
5hÜÇ  
5Lb  
ꢁoa/Ü  
!Db5  
Lb0  
ë5  
^5LDLÇ![_ {Ütt[ò w!L[  
Lb1  
5Db5  
Lb7  
Lb2  
Lb3  
Lb6  
ꢁo ꢂnꢂlog  
signꢂl sources  
Lb4  
Lbꢀ  
ëL! ꢁo DwhÜb5 t[!b9  
DwhÜb5 t[!b9  
Figure 40. Layout Diagram  
24  
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ADC128S102QML-SP  
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SNAS411P –AUGUST 2008–REVISED APRIL 2017  
11 Device and Documentation Support  
11.1 Device Support  
11.1.1 Development Support  
For related documentation, see the following:  
•
•
•
5962R07727  
Radiation Report  
MIL-STD-883G, Test Method 1019.7  
11.1.2 Device Nomenclature  
11.1.2.1 Specification Definitions  
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold  
capacitor is charged by the input voltage.  
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is  
internally acquired or held for conversion.  
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another  
channel.  
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input  
voltage to a digital word.  
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-  
Channel Isolation, except for the sign of the data.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB.  
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The  
specification here refers to the SCLK.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise  
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is  
equivalent to a perfect ADC of this (ENOB) number of bits.  
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental  
drops 3 dB below its low frequency value for a full scale input.  
GAIN ERRORis the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5 LSB),  
after adjusting for offset error.  
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from  
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above  
the last code transition). The deviation of any given code from this straight line is measured from  
the center of that code value.  
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two  
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as  
the ratio of the power in either the second or the third order intermodulation products to the sum of  
the power in both of the original frequencies. Second order products are fa ± fb, where fa and fb are  
the two sine wave input frequencies. Third order products are (2fa ± fb ) and (fa ± 2fb). IMD is  
usually expressed in dB.  
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC128S102 is  
verified not to have any missing codes.  
OFFSET ERRORis the deviation of the first code transition (000...000) to (000...001) from the ideal (that is, GND  
+ 0.5 LSB).  
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms  
value of the sum of all other spectral components below one-half the sampling frequency, not  
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Device Support (continued)  
including harmonics or d.c.  
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of  
the input signal to the rms value of all of the other spectral components below half the clock  
frequency, including harmonics but excluding d.c.  
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal  
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral  
component is any signal present in the output spectrum that is not present at the input and may or  
may not be a harmonic.  
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the  
acquisition time plus the conversion time.  
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic  
components at the output to the rms level of the input signal frequency as seen at the output. THD  
is calculated as:  
2
2
A
+3+ A  
f2  
f10  
THD = 20 log  
•
10  
2
A
f1  
where  
•
•
Af1 is the RMS power of the input frequency at the output  
Af2 through Af10 are the RMS power in the first 9 harmonic frequencies  
(2)  
11.2 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper  
right corner, click on Alert me to register and receive a weekly digest of any product information that has  
changed. For change details, review the revision history included in any revised document.  
11.3 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
11.4 Trademarks  
MICROWIRE, E2E are trademarks of Texas Instruments.  
SPI, QSPI are trademarks of Motorola, Inc..  
All other trademarks are the property of their respective owners.  
11.5 Electrostatic Discharge Caution  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
11.6 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
26  
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SNAS411P –AUGUST 2008–REVISED APRIL 2017  
12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
12.1 Engineering Samples  
Engineering samples are available for order and are identified by the "MPR" in the orderable device name (see  
Packaging Information in the Addendum). Engineering (MPR) samples meet the performance specifications of  
the datasheet at room temperature only and have not received the full space production flow or testing.  
Engineering samples may be QCI rejects that failed tests that would not impact the performance at room  
temperature, such as radiation or reliability testing.  
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27  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Sep-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
5962R0722701V9A  
5962R0722701VFA  
ACTIVE  
ACTIVE  
DIESALE  
CFP  
Y
0
20  
19  
RoHS & Green  
Call TI  
Level-1-NA-UNLIM  
Level-1-NA-UNLIM  
-55 to 125  
-55 to 125  
NAD  
16  
Non-RoHS  
& Green  
Call TI  
Call TI  
ADC128S102  
WRQMLV Q  
5962R07227  
01VFA ACO  
01VFA >T  
5962R0722701VZA  
ACTIVE  
CFP  
NAC  
16  
42  
Non-RoHS  
& Green  
Level-1-NA-UNLIM  
-55 to 125  
ADC128S102  
WGRQMLV Q  
5962R07227  
01VZA ACO  
01VZA >T  
ADC128S102 MDR  
ACTIVE  
ACTIVE  
DIESALE  
CFP  
Y
0
20  
42  
RoHS & Green  
Call TI  
Call TI  
Level-1-NA-UNLIM  
Level-1-NA-UNLIM  
-55 to 125  
25 to 25  
ADC128S102WGMPR  
NAC  
16  
Non-RoHS  
& Green  
ADC128S102  
WGMPR ES ACO  
WGMPR ES >T  
ADC128S102WGRQV  
ADC128S102WRQV  
ACTIVE  
ACTIVE  
CFP  
CFP  
NAC  
NAD  
16  
16  
42  
19  
Non-RoHS  
& Green  
Call TI  
Call TI  
Level-1-NA-UNLIM  
Level-1-NA-UNLIM  
-55 to 125  
-55 to 125  
ADC128S102  
WGRQMLV Q  
5962R07227  
01VZA ACO  
01VZA >T  
Non-RoHS  
& Green  
ADC128S102  
WRQMLV Q  
5962R07227  
01VFA ACO  
01VFA >T  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Sep-2021  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TUBE  
T - Tube  
height  
L - Tube length  
W - Tube  
width  
B - Alignment groove width  
*All dimensions are nominal  
Device  
Package Name Package Type  
Pins  
SPQ  
L (mm)  
W (mm)  
T (µm)  
B (mm)  
5962R0722701VFA  
ADC128S102WRQV  
NAD  
NAD  
CFP  
CFP  
16  
16  
19  
19  
502  
502  
23  
23  
9398  
9398  
9.78  
9.78  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TRAY  
L - Outer tray length without tabs  
KO -  
Outer  
tray  
height  
W -  
Outer  
tray  
width  
Text  
P1 - Tray unit pocket pitch  
CW - Measurement for tray edge (Y direction) to corner pocket center  
CL - Measurement for tray edge (X direction) to corner pocket center  
Chamfer on Tray corner indicates Pin 1 orientation of packed units.  
*All dimensions are nominal  
Device  
Package Package Pins SPQ Unit array  
Max  
matrix temperature  
(°C)  
L (mm)  
W
K0  
P1  
CL  
CW  
Name  
Type  
(mm) (µm) (mm) (mm) (mm)  
5962R0722701VZA  
ADC128S102WGMPR  
ADC128S102WGRQV  
NAC  
NAC  
NAC  
CFP  
CFP  
CFP  
16  
16  
16  
42  
42  
42  
7 X 6  
7 X 6  
7 X 6  
NA  
NA  
NA  
101.6 101.6 8001 2.84 15.24 15.24  
101.6 101.6 8001 2.84 15.24 15.24  
101.6 101.6 8001 2.84 15.24 15.24  
Pack Materials-Page 2  
PACKAGE OUTLINE  
NAC0016A  
CFP - 2.33mm max height  
S
C
A
L
E
1
.
5
0
0
CERAMIC FLATPACK  
SUPPLIER OPTION  
NOTE 3  
LEAD 1 ID  
NOTE 3  
.018 MAX TYP  
[0.46]  
.010 .002  
[0.254 0.0508]  
.00 MIN TYP  
[0.0]  
1
16  
14X .050 .002  
[1.27 0.0508]  
.3870 .0030  
[9.83 0.076]  
16X .017 .002  
[0.4318 0.0508]  
9
8
+.010  
+.020  
-.005  
.070  
.250  
-.020  
+0.254  
+0.508  
-0.127  
1.778  
6.35  
[
-0.508  
]
[
]
.410 .010  
[10.414 0.254]  
.008 .004  
[0.2032 0.1016]  
TYP  
SEE DETAIL A  
.004 [0.1]  
SEATING PLANE  
.006 .002  
TYP  
[0.1524 0.0508]  
R.015 .002  
[0.381 0.0508]  
.040 .003  
[1.016 0.0762]  
0 -4  
  D
SCALE  
:E1  
2
   T
.0  
   A
00  
IL  
 A
[
DETAIL A  
TYPICAL  
4215198/C 08/2022  
NOTES:  
1. Controlling dimension is Inch. Values in [ ] are milimeters. Dimensions in ( ) for reference only.  
2. For solder thickness and composition, see the "Lead Finish Composition/Thickness" link in the packaging section of the  
Texas Instruments website  
3. Lead 1 identification shall be:  
a) A notch or other mark within this area  
b) A tab on lead 1, either side  
4. No JEDEC registration as of December 2021  
www.ti.com  
EXAMPLE BOARD LAYOUT  
NAC0016A  
CFP - 2.33mm max height  
CERAMIC FLATPACK  
(16X .090 )  
[2.29]  
SYMM  
(14X .050 )  
[1.27]  
(16X .027 )  
[0.69]  
SYMM  
R.002 TYP  
[0.05]  
(.37 )  
[9.4]  
RECOMMENDED LAND PATTERN  
.003 MAX  
[0.07]  
ALL AROUND  
.003 MIN  
[0.07]  
ALL AROUND  
METAL  
SOLDERMASK  
OPENING  
METAL UNDER  
SOLDER MASK  
SOLDERMASK  
OPENING  
SOLDERMASK  
DEFINED  
NON SOLDERMASK  
DEFINED  
4215198/C 08/2022  
www.ti.com  
REVISIONS  
REV  
A
DESCRIPTION  
E.C.N.  
DATE  
BY/APP'D  
RELEASE TO DOCUMENT CONTROL  
2197879  
2198832  
2200917  
12/30/2021  
02/15/2022  
08/08/2022  
TINA TRAN / ANIS FAUZI  
K. SINCERBOX  
B
NO CHANGE TO DRAWING; REVISION FOR YODA RELEASE;  
.387 .003 WAS .39000 .00012;  
C
D. CHIN / K. SINCERBOX  
REV  
SCALE  
SIZE  
PAGE  
OF  
4215198  
C
4
4
A
MECHANICAL DATA  
NAD0016A  
W16A (Rev T)  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
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resources.  
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with  
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for  
TI products.  
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2023, Texas Instruments Incorporated  

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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