ADC12D040 [TI]

双通道、12 位、40MSPS 模数转换器 (ADC);


型号：	ADC12D040
厂家：	TEXAS INSTRUMENTS
描述：	双通道、12 位、40MSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总31页 (文件大小：896K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12D040

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SNAS171E –JUNE 2002–REVISED MARCH 2013

ADC12D040 Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference

Check for Samples: ADC12D040

FEATURES

DESCRIPTION

The ADC12D040 is a dual, low power monolithic

CMOS analog-to-digital converter capable of

converting analog input signals into 12-bit digital

words at 40 Megasamples per second (Msps),

minimum. This converter uses a differential, pipeline

architecture with digital error correction and an on-

chip sample-and-hold circuit to minimize die size and

power consumption while providing excellent dynamic

performance. Operating on a single 5V power supply,

the ADC12D040 achieves 10.9 effective bits at 10

MHz input and consumes just 600 mW at 40 Msps,

including the reference current. The Power Down

feature reduces power consumption to 75 mW.

•

Binary or 2’s Complement Output Format

Single Supply Operation

•

Internal Sample-and-Hold

Outputs 2.4V to 5V Compatible

Power Down Mode

Pin-Compatible with ADC12DL066

Internal/External Reference

APPLICATIONS

•

Ultrasound and Imaging

Instrumentation

Communications Receivers

Sonar/Radar

The differential inputs provide a full scale differential

input swing equal to 2V_REFwith the possibility of a

single-ended input. Full use of the differential input is

recommended for optimum performance. The digital

outputs for the two ADCs are available on separate

12-bit buses with an output data format choice of

offset binary or 2’s complement.

xDSL

Cable Modems

KEY SPECIFICATIONS

For ease of interface, the digital output driver power

pins of the ADC12D040 can be connected to a

separate supply voltage in the range of 2.4V to the

digital supply voltage, making the outputs compatible

with low voltage systems. The ADC12D040’s speed,

resolution and single supply operation make it well

suited for a variety of applications.

•

SNR (f_IN= 10 MHz): 68 dB (typ)

ENOB (f_IN= 10 MHz): 10.9 bits (typ)

SFDR (f_IN= 10 MHz): 80 dB (typ)

Data Latency: 6 Clock Cycles

Supply Voltage: +5V ±5%

Power Consumption, Operating

This device is available in the 64-lead TQFP package

and will operate over the industrial temperature range

of −40°C to +85°C. An evaluation board is available

to facilitate the product evaluation process

–

(Operating): 600 mW (typ)

(Power Down Mode): 75 mW (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12D040

SNAS171E –JUNE 2002–REVISED MARCH 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Connection Diagram

Figure 1. 64-Lead TQFP Package

Package Number PAG

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Block Diagram

A+

A-

Stage

S/H

AGND

Timing

Control

11-Stage Pipeline Converter

CLK

Digital Correction

DGND

DA0-DA11

OEA

Output

Buffers

INT/EXT REF

DR GND

Bandgap

Reference

REF

DB0-DB11

OEB

Output

Buffers

DGND

Digital Correction

11-Stage Pipeline Converter

Timing

Control

B-

Stage

S/H

AGND

B+

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

Non-Inverting analog signal Inputs. With a 2.0V reference the full-

scale input signal level is 2.0 V_P-Pon each pin of the input pair,

V_INA+

V_INB+

centered on a common V_CM

Inverting analog signal Input. With a 2.0V reference the full-scale

input signal level is 2.0 V_P-Pon each pin of the input pair, centered

on a common V_CM. These (-) input pins may be connected to a

common V_CMfor single-ended operation, but a differential input

signal is required for best performance.

V_INA−

V_INB−

Reference input. This pin should be bypassed to AGND with a 0.1

µF monolithic capacitor when external reference is used. V_REFis

2.0V nominal and should be between 1.0V to 2.4V.

V_REF

V_REFselect pin. With a logic low at this pin the internal 2.0V

reference is selected. With a logic high on this pin an external

reference voltage must be applied to V_REFinput pin 7.

INT/EXT REF

V_RP

V_RM

These pins are high impedance reference bypass pins only. Connect

a 0.1 µF capacitor from each of these pins to AGND. DO NOT LOAD

these pins.

V_RN

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 100 kHz

to 55 MHz (typical) with guaranteed performance at 40 MHz. The

input is sampled on the rising edge of this input.

CLK

OEA and OEB are the output enable pins that, when low, enables

their respective TRI-STATE data output pins. When either of these

pins is high, the corresponding outputs are in a high impedance

state.

OEA

OEB

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

Output Format pin. A logic low on this pin causes output data to be

in offset binary format. A logic high on this pin causes the output

data to be in 2’s complement format.

DGND

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Pin No.

SNAS171E –JUNE 2002–REVISED MARCH 2013

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Symbol

Equivalent Circuit

Description

24–29

34–39

DA0–DA11

Digital data output pins that make up the 12-bit conversion results of

their respective converters. DA0 and DB0 are the LSBs, while DA11

and DB11 are the MSBs of the output word. Output levels are

TTL/CMOS compatible.

42–47

52–57

DB0–DB11

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet +5V source and bypassed to AGND with 0.1 µF monolithic

capacitors located within 1 cm of these power pins, and with a 10 µF

capacitor.

9, 18, 19,

62, 63

V_A

3, 8, 10, 17,

20, 61, 64

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same

quiet +5V source as is V_Aand be bypassed to DGND with a 0.1 µF

monolithic capacitor located within 1 cm of the power pin and with a

10 µF capacitor.

33, 48

V_D

32, 49

DGND

The ground return for the digital supply.

Positive digital supply pins for the ADC12D040's output drivers.

These pins should be connected to a voltage source of +2.4V to +5V

and bypassed to DR GND with a 0.1 µF monolithic capacitor. If the

supply for these pins are different from the supply used for V_Aand

V_D, they should also be bypassed with a 10 µF tantalum capacitor.

V_DRshould never exceed the voltage on V_D. All bypass capacitors

should be located within 1 cm of the supply pin.

30, 51

V_DR

The ground return for the digital supply for the ADC12D040's output

drivers. These pins should be connected to the system digital

ground, but not be connected in close proximity to the ADC12D040's

DGND or AGND pins. See LAYOUT AND GROUNDING (Layout and

Grounding) for more details.

23, 31, 40,

50, 58

DR GND

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Absolute Maximum Ratings^(1)(2)(3)

V_A, V_D, V_DR

6.5V

V_D+ 0.3V

V_DR

|V_A–V_D|

≤ 100 mV

Voltage on Any Input or Output Pin

Input Current at Any Pin⁽⁴⁾

Package Input Current⁽⁴⁾

Package Dissipation at T_A= 25°C

ESD Susceptibility⁽⁶⁾

−0.3V to (V_Aor V_D+0.3V)

±25 mA

±50 mA

(5)

See

Human Body Model

Machine Model

2500V

250V

Soldering Temperature, Infrared, 10 sec.⁽⁷⁾

Storage Temperature

235°C

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND DR GND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature, (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A)/θ_JA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

(7) The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the

temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body

must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.

Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

V_REFInput

−40°C ≤ T_A≤ +85°C

+4.75V to +5.25V

+2.35V to V_D

)

1.0V to 2.4V

CLK, PD, OE

−0.5V to (V_D+ 0.5V)

−0V to (V_A− 0.5V)

V_REF/2 to V_A− V_REF

≤100mV

Analog Input Pins

Input Common Mode Voltage (V_CM

)

|AGND–DGND|

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AGND = DGND DR GND = 0V, unless otherwise specified.

Package Thermal Resistance

Package

θ_J-A

64-Lead TQFP

50°C / W

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SNAS171E –JUNE 2002–REVISED MARCH 2013

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_AV_D+5V, V_DR+3.0V, PD

= 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits apply for T_J

= T_MINto T_MAX: all other limits T_J= 25°C⁽¹⁾⁽²⁾

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(3)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Integral Non Linearity⁽⁴⁾

±2.0

Bits (min)

LSB (max)

%FS

INL

±0.7

±0.4

0.51

0.68

DNL

Differential Non Linearity

±1.0

Positive Error

Negative Error

+2.8/−1.9

+4/−2.7

Gain Error

%FS

External Reference

Internal Reference

ppm/ºC

TC GE

V_OFF

Gain Error Tempco

100

−0.1

ppm/ºC

Offset Error (V_IN+ = V_IN−)

±1.2

%FS (max)

ppm/ºC

External Reference

Internal Reference

TC V_OFFOffset Error Tempco

ppm/ºC

Under Range Output Code

Over Range Output Code

4095

DYNAMIC CONVERTER CHARACTERISTICS

FPBW

Full Power Bandwidth

0 dBFS Input, Output at −3 dB

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

100

MHz

SNR

Signal-to-Noise Ratio

66.5

65.6

10.6

−69

dB (min)

SINAD

ENOB

THD

Signal-to-Noise and Distortion

Effective Number of Bits

Total Harmonic Distortion

Second Harmonic

dB (min)

Bits

11.1

10.9

−80

−78

−84

−80

−84

−82

Bits (min)

dB (max)

−73

dB (max)

Third Harmonic

−69.5

69.5

dB (max)

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

dB (min)

f_IN= 9.6 MHz and 10.2 MHz, each = −6.0

dBFS

−80

dBFS

INTER-CHANNEL CHARACTERISTICS

Channel—Channel Offset Match

±0.02

±0.05

%FS

Channel—Channel Gain Error Match

10 MHz Tested Channel. 15 MHz Other

Channel

Crosstalk

−80

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited, see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average

Outgoing Quality Level).

(4) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

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Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_AV_D+5V, V_DR+3.0V, PD

= 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits apply for T_J

= T_MINto T_MAX: all other limits T_J= 25°C⁽¹⁾⁽²⁾

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(3)

REFERENCE AND ANALOG INPUT CHARACTERISTICS

(CLK LOW)

(CLK HIGH)

C_IN

V_INInput Capacitance (each pin to GND) V_IN= 2.5 Vdc + 0.7 V_rms

1.0

2.4

V (min)

V (max)

MΩ (min)

V (min)

V (max)

V_REF

R_REF

V_IN

Input Reference Voltage⁽⁵⁾

Reference Input Resistance

Analog Input Voltage Range

2.00

100

(5) Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.4V range. The LM4051CIM3-ADJ (SOT23

package) is recommended for this application.

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits

apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(4)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

V_D= 5.25V

V_D= 4.75V

V_IN= 5.0V

V_IN= 0V

2.0

1.0

V (min)

V (max)

µA

−10

µA

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited, see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +2.0V (4V_P-Pdifferential input), the 12-bit LSB is 977 µV.

(4) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average

Outgoing Quality Level).

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DC and Logic Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits

apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(4)

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V_DR= 2.5V

V_DR= 3V

2.3

2.7

0.4

V (min)

V (max)

V_OUT(1)

V_OUT(0)

I_OZ

Logical “1” Output Voltage

Logical “0” Output Voltage

TRI-STATE Output Current

I_OUT= −0.5 mA

I_OUT= 1.6 mA, V_DR= 3V

V_OUT= 2.5V or 5V

V_OUT= 0V

100

−100

−20

+I_SC

−I_SC

C_OUT

Output Short Circuit Source Current

Output Short Circuit Sink Current

Digital Output Capacitance

V_OUT= 0V

V_OUT= V_DR

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, V_REF= 2.0V

PD Pin = V_DR

110

mA (max)

I_A

Analog Supply Current

PD Pin = DGND

PD Pin = V_DR

mA (max)

I_D

Digital Supply Current

PD Pin = DGND, C_L= 0 pF⁽⁵⁾

PD Pin = V_DR

PD Pin = DGND, C_L= 0 pF⁽⁶⁾

PD Pin = V_DR

10.5

mA (max)

I_DR

Digital Output Supply Current

Total Power Consumption

600

700

Rejection of Full-Scale Error with

V_A= 4.75V vs. 5.25V

PSRR1 Power Supply Rejection

(5) I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁

f₁₁) where V_DRis the output driver power supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at

which that pin is toggling.

(6) Excludes I_DR. See⁽⁶⁾

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits

apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)(4)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(5)

f_CLK

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

MHz (min)

f_CLK

100

kHz

t_CH

t_CL

Clock Low Time

t_CONV

t_OD

Conversion Latency

Clock Cycles

ns (max)

Data Output Delay after Rising CLK Edge V_DR= 3.0V

Aperture Delay

1.2

17.5

t_AD

t_AJ

Aperture Jitter

ps rms

t_HOLD

Clock Edge to Data Transition

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited, see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais 4.75V, the full-scale input voltage must be ≤4.85V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +2.0V (4V_P-Pdifferential input), the 12-bit LSB is 977 µV.

(4) Timing specifications are tested at TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge.

(5) Typical figures are at T_A= T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average

Outgoing Quality Level).

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AC Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +5V, V_DR

+3.0V, PD = 0V, INT/EXT = V_D, V_REF= +2.0V,OEA, OEB = 0V, f_CLK= 40 MHz, t_r= t_f= 3 ns, C_L= 20 pF/pin. Boldface limits

apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)(4)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(5)

t_DIS

t_EN

t_PD

Data outputs into TRI-STATE Mode

Data Outputs Active after TRI-STATE

Power Down Mode Exit Cycle

500

Figure 2.

Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the d.c. potential present at both signal inputs to the ADC.

CONVERSION LATENCY See PIPELINE DELAY.

CROSSTALK is coupling of energy from one channel into the other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full-Scale Error

(1)

Gain Error can also be separated into Positive Gain Error and Negative Gain Error, which are.

PGE = Positive Full-Scale Error − Offset Error

(2)

(3)

NGE = Offset Error − Negative Full-Scale Error

GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average

gain of the converters.

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INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is V_REF

2ⁿ, where “n” is the ADC resolution in bits, which is 12 in the case of the ADC12D040.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12D040 is

guaranteed not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages (V_IN+ –V_IN−) required to cause a transition

from code 2047 to 2048.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

OVER RANGE RECOVERY TIME is the time required after V_INgoes from a specified voltage out of the normal

input range to a specified voltage within the normal input range and the converter makes a conversion with its

rated accuracy.

PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that data

is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline

Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data

lags the conversion by the pipeline delay.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC12D040, PSRR1 is the ratio of the change in Full-Scale Error that results from a

change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding

upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

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TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first seven

harmonic levels at the output to the level of the fundamental at the output. THD is calculated as

where

•

f₁is the RMS power of the fundamental (output) frequency and f₂through f₁₀are the RMS power of the first 9

harmonic frequencies in the output spectrum. (4)

– Second Harmonic Distortion (2ND HARM) is the difference expressed in dB, between the RMS power in the

input frequency at the output and the power in its 2nd harmonic level at the output.

– Third Harmonic Distortion (3RD HARM) is the difference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic level at the output.

Timing Diagram

Figure 3. Output Timing

Transfer Characteristic

Figure 4. Transfer Characteristic

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Typical Performance Characteristics

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

DNL

INL

0.5

0.4

0.3

0.2

0.1

0.5

-0.1

-0.2

-0.3

-0.4

-0.5

-1

1024

2048

3072

4096

1024

2048

3072

4096

OUTPUT CODE

Figure 5.

Figure 6.

INL & DNL

vs.

Supply Voltage

DNL & INL

vs.

Clock Frequency

0.8

0.6

0.4

0.2

1.5

+INL

+DNL

0.5

+DNL

-DNL

-INL

-0.2

-0.4

-0.6

-0.8

-1

-DNL

-INL

-0.5

-1

-1.5

-2

4.5/ 4.75/ 5.0/ 5.0/ 5.0/ 5.0/ 5.25/ 5.5/

4.5 4.75 2.5 3.0 4.0 5.0 5.25 5.5

VA/V_DR

CLOCK FREQUENCY (MHz)

Figure 7.

Figure 8.

DNL & INL

vs.

Clock Duty Cycle

DNL & INL

vs.

Reference Voltage

1.5

+INL

0.5

+INL

+DNL

-DNL

-INL

-DNL

-INL

-1

-0.5

-1

-2

-3

-1.5

0.8

1.2 1.4 1.6

2.4 2.6 2.8

CLOCK DUTY CYCLE

REFERENCE VOLTAGE, V

Figure 9.

Figure 10.

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Typical Performance Characteristics (continued)

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

INL & DNL

vs. Temperature

SNR, SINAD, SFDR

vs. Supply Voltage

0.8

SFDR

+INL

0.6

0.4

+DNL

0.2

-0.2

SNR

-DNL

-0.4

-0.6

SINAD

-INL

-0.8

-1

-40

4.5/ 4.75/ 5.0/ 5.0/ 5.0/ 5.0/ 5.25/ 5.5/

4.5 4.75 2.5

3.0 4.0

5.0 5.25 5.5

TEMPERATURE (°C)

V_A/V_DR, Volts

Figure 11.

Figure 12.

SNR, SINAD, SFDR

vs.

Clock Frequency

SNR, SINAD, SFDR

vs.

Clock Duty Cycle

SFDR

SNR

SINAD

CLOCK DUTY CYCLE, %

CLOCK FREQUENCY, MHz

Figure 13.

Figure 14.

SNR, SINAD, SFDR

vs.

Input Frequency

SNR, SINAD, SFDR

vs.

Reference Voltage

SFDR

SNR

SINAD

SNR

SINAD

0.8

1.2 1.4

2.6

2.8

1.6

2.4

INPUT FREQUENCY (MHZ)

REFERENCE VOLTAGE, V

Figure 15.

Figure 16.

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Typical Performance Characteristics (continued)

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

SNR, SINAD, SFDR

vs. Temperature

Distortion

vs.Supply Voltage

-70

-72

-74

-76

-78

-80

-82

-84

-86

-88

-90

THD

3rd Harmonic

2nd Harmonic

4.5/ 4.75/ 5.0/ 5.0/ 5.0/ 5.0/ 5.25/ 5.5/

4.5 4.75 2.5 3.0 4.0 5.0 5.25 5.5

V_A/V_DR, Volts

Figure 17.

Figure 18.

Distortion

vs.

Clock Duty Cycle

Distortion vs.

Clock Frequency

-68

-60

-65

-70

-72

-74

-76

-78

-80

-82

-84

-86

THD

-75

THD

HAR2

-80

HAR3

-85

-90

HAR2

HAR3

CLOCK DUTY CYCLE

FCLK, MHz

Figure 19.

Figure 20.

Distortion

vs.

Input Frequency

Distortion

vs.

Reference Voltage

-40

-60

-65

-70

-75

-80

-85

-90

-95

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

THD

HAR3

HAR2

THD

3rd Harmonic

2nd Harmonic

20 30

0.8

1.2 1.4 1.6

2.4 2.6 2.8

INPUT FREQUENCY, MHz

VREF, V

Figure 21.

Figure 22.

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Typical Performance Characteristics (continued)

V_A= V_D= 5V, V_DR= 3V, f_CLK= 40 MHz, f_IN= 10 MHz unless otherwise stated

Distortion

vs.Temperature

Power Consumption

vs.Reference Voltage

800

750

700

650

600

550

500

450

400

0.8

1.2 1.4 1.6

2.4 2.6 2.8 3

VREF, V

Figure 23.

Figure 24.

Power Consumption

vs.

Spectral Response @ Fin = 9.95 MHz,

F_CLK= 40 MHz

Temperature

-10

750

SINAD: 68.569

Fundamental

SNR: 68.894

THD: -79.989

45 MSPS

40 MSPS

50 MSPS

60 MSPS

55 MSPS

9.95 MHz

SFDR: 81.384

ENOB: 11.098

700

650

600

550

500

450

400

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

H 3

SFDR

10.15 MHz

H 2

19.9 MHz

H 5

9.75 MHz

H 7

10.35 MHz

H 4

200.195 kHz

H 6

19.7 MHz

20 MSPS

30 MSPS

10 MSPS

5 MSPS

10 12 14 16

-40

FREQUENCY, MHz

TEMPERATURE, °C

Figure 25.

Figure 26.

IMD Response Fin = 9.6 MHz, 10.2 MHz,

F_CLK= 40 MHz

Crosstalk Response Fin = 9.95 MHz,

F_CROSSTALK= 15 MHz, F_CLK= 40 MHz

-10

SINAD: 68.452

Fundamental

SNR: 68.83

-10

-20

-30

-40

-50

-60

-70

-80

SNR: 68.83

9.95 MHz

THD: -79.241

SFDR: 80.201

9.6 MHz

SFDR: 80.201

10.2 MHz

ENOB: 11.078

IMD -85.837

-20

-30

-40

-50

-60

-70

-80

-90

H 3

SFDR

10.15 MHz

SFDR

H 2

19.9 MHz

H 5

9.75 MHz

H 7

10.35 MHz

H 6

19.7 MHz

H 4

200.195 kHz

H 7

10.35 MHz

19.8 MHz

-90

600.586 kHz

-100

-110

-120

-100

-110

-120

10 12 14 16

10 12 14 16 18 20

FREQUENCY, MHz

Figure 27.

Figure 28.

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FUNCTIONAL DESCRIPTION

Operating on a single +5V supply, the ADC12D040 uses a pipeline architecture and has error correction circuitry

to help ensure maximum performance. The differential analog input signal is digitized to 12 bits and the reference

input is buffered to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 100 ksps (typical) and 40 Msps

with fully specified performance at 40 Msps. The analog input voltage for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 6 clock cycles. A choice of

Offset Binary or Two's Complement output format is selected with the OF pin.

A logic high on the power down (PD) pin reduces the converter power consumption to 75 mW.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12D040:

4.75V ≤ V_A≤ 5.25V

V_D= V_A

2.35V ≤ V_DR≤ V_D

V_REF/2 ≤ V_CM≤ V_A- V_REF

100 kHz ≤ f_CLK≤ 40 MHz

1.0V ≤ V_REF≤ 2.4V

Analog Inputs

The ADC12D040 has two analog signal inputs, V_IN+ and V_IN−. These two pins form a differential input pair. There

is one reference input pin, V_REF

The analog input circuitry contains an input boost circuit that provides improved linearity over a wide range of

analog input voltages. To prevent an on-chip over voltage condition that could impair device reliability, the input

signal should never exceed the voltage described as

V_A- V_REF/2.

(5)

Reference Pins

The ADC12D040 is designed to operate with a 2.0V reference, but performs well with reference voltages in the

range of 1.0V to 2.4V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the ADC12D040.

Increasing the reference voltage (and the input signal swing) beyond 2.4V may degrade THD for a full-scale input

especially at higher input frequencies. It is important that all grounds associated with the reference voltage and

the input signal make connection to the analog ground plane at a single point in that plane to minimize the

effects of noise currents in the ground path.

The ADC12040 will perform well with reference voltages up to 2.4V for full-scale input frequencies up to 10 MHz.

However, more headroom is needed as the input frequency increases, so the maximum reference voltage (and

input swing) will decrease for higher full-scale input frequencies.

The six Reference Bypass Pins (V_RPA, V_RMA, V_RNA, V_RPB, V_RMB and V_RNB) are made available for bypass

purposes. These pins should each be bypassed to ground with a 0.1 µF capacitor. Smaller capacitor values will

allow faster recovery from the power down mode, but may result in degraded noise performance. DO NOT LOAD

these pins. Loading any of these pins may result in performance degradation.

The nominal voltages for the reference bypass pins are as follows:

V_RMA = V_RMB = V_A/ 2

V_RPA = V_RPB = V_RM+ V_REF/ 2

V_RNA = V_RNB = V_RM− V_REF/ 2

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The V_RNpins may be used as a common mode voltage source (V_CM) for the analog input pins as long as no d.c.

current is drawn from it. However, because the voltages at these pins are half that of the V_Asupply pin, using

these pins for a common mode source will result in reduced input headroom (the difference between the V_A

supply voltage and the peak signal voltage at either analog input) and the possibility of reduced THD and SFDR

performance. For this reason, it is recommended that V_Aalways exceed V_REFby at least 2 Volts. For high input

frequencies it may be necessary to increase this headroom to maintain THD and SFDR performance.

Signal Inputs

The signal inputs are V_IN+ and V_IN−. The input signal, V_IN, is defined as

V_IN= (V_IN+) – (V_IN−)

(6)

Figure 29 shows the expected input signal range.

Note that the common mode input voltage range is 1V to 3V with a nominal value of V_A/2. The input signals

should remain between ground and 4V.

The Peaks of the individual input signals (V_IN+ and V_IN−) should each never exceed the voltage described as

V_IN+, V_IN− = (V_REF/ 2 + V_CM) ≤ 4V (differential)

(7)

to maintain THD and SINAD performance.

Figure 29. Expected Input Signal Range

The ADC12D040 performs best with a differential input with each input centered around a common V_CM. The

peak-to-peak voltage swing at both V_IN+ and V_IN− should not exceed the value of the reference voltage or the

output data will be clipped.

The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single

frequency inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform,

however, angular errors will result in distortion.

For single frequency sine waves with angular errors of less than 45° (π/4) between the two inputs, the full scale

error in LSB can be described as approximately

E_FS= 2^(n-1)* ( 1 - cos (dev) ) = 2048 * ( 1 - cos (dev) )

(8)

Where dev is the angular difference between the two signals having a 180° relative phase relationship to each

other (see Figure 30). Drive the analog inputs with a source impedance less than 100Ω.

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Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause Distortion

Figure 30. Angular Errors Between Two Input Signals

Table 1. Input to Output Relationship – Differential Input

−

V_IN

Binary Output

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

2’s Complement Output

1000 0000 0000

1100 0000 0000

0000 0000 0000

0100 0000 0000

0111 1111 1111

_CM− V_REF/2

V_CM+ V_REF/2

V_CM+ V_REF/4

V_CM

_CM− V_REF/4

V_CM

V_CM+ V_REF/4

V_CM+ V_REF/2

_CM− V_REF/4

_CM− V_REF/2

Table 2. Input to Output Relationship – Single-Ended Input

V_IN

−

Binary Output

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

2’s Complement Output

1000 0000 0000

1100 0000 0000

0000 0000 0000

0100 0000 0000

0111 1111 1111

_CM− V_REF

V_CM

_CM− V_REF/2

V_CM

V_CM+ V_REF/2

V_CM+ V_REF

Single-Ended Operation

Single-ended performance is lower than with differential input signals. For this reason, single-ended operation is

not recommended. However, if single ended-operation is required and the resulting performance degradation is

acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the driven input. The

peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD

performance (Figure 29b).

For example, set V_REFto 1.0V, bias V_IN− to 2.5V and drive V_IN+ with a signal range of 1.5V to 3.5V.

Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and

Table 2 indicate the input to output relationship of the ADC12D040.

Driving the Analog Input

The V_IN+ and the V_IN− inputs of the ADC12D040 consist of an analog switch followed by a switched-capacitor

amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when

the clock is low, and 7 pF when the clock is high.

As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in

voltage spikes at the signal input pins. As a driving amplifier attempts to counteract these voltage spikes, a

damped oscillation may appear at the ADC analog inputs. The best amplifiers for driving the ADC12D040 input

pins must be able to react to these spikes and settle before the switch opens and another sample is taken. The

LMH6702 LMH6628 and the LMH6622, LMH6655 are good amplifiers for driving the ADC12D040.

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To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in

Figure 31 and Figure 32. These components should be placed close to the ADC inputs because the input pins of

the ADC is the most sensitive part of the system and this is the last opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the

sample mode should be considered when setting the RC pole. Setting the pole in this manner will provide best

SNR performance.

To obtain best SINAD and ENOB performance, reduce the RC time constant until SNR and THD are numerically

equal to each other. To obtain best distortion and SFDR performance, eliminate the RC altogether.

For undersampling applications, RC pole should be set at about 1.5 to 2 times the maximum input frequency to

maintain a linear delay response.

Note that the ADC12DL040 is not designed to operate with single-ended inputs. However, doing so is possible if

the degraded performance is acceptable. See Single-Ended Operation

Figure 31 shows a narrow band application with a transformer used to convert single-ended input signals to

differential. Figure 32 shows the use of a fully differential amplifier for single-ended to differential conversion.

Figure 31. Application Circuit using Transformer or Differential Op-Amp Drive Circuit

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511, 1%

To ADC

255, 1%

280, 1%

50W

SIGNAL

INPUT

68 pF

Amplifier:

LMH6650

49.9,

68 pF

To ADC

511, 1%

Figure 32. Differential Drive Circuit using a fully differential amplifier.

Input Common Mode Voltage

The input common mode voltage, V_CM, should be of a value such that the peak excursions of the analog signal

does not go more negative than ground or more positive than 1.0 Volts below the V_Asupply voltage. The nominal

V_CMshould generally be about V_REF/2. V_RBA and V_RBB can be used as V_CMsources as long as no d.c. current is

drawn from these pins.

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, OF, INT/EXT REF, and PD.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 100 kHz to 55 MHz with rise and fall times of less than 3ns. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is what limits the lowest sample

The ADC clock line should be considered to be a transmission line and be series terminated at the source end to

match the source impedance with the characteristic impedance of the clock line. It generally is not necessary to

terminate the far (ADC) end of the clock line, but if a single clock source is driving more than one device (a

condition that is generally not recommended), far end termination may be needed. Far end termination is a series

RC with the resistor being the same as the characteristic impedance of the clock line. The capacitor should have

a minimum value of

(9)

where t_PDis the propagation time in ns/unit length, "L" is the length of the line and Z_Ois the characteristic

impedance of the line. The units of t_PDand "L" should be consistent with each other. The typical board of FR-4

material has a t_PDof about 150 ps/inch, or about 60 ps/cm.

The far end termination should be near but beyond the ADC clock pin as seen from the clock source.

The duty cycle of the clock signal can affect the performance of any A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12040 is designed to maintain performance over a range of duty cycles. While it is

specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over a

clock duty cycle range of 40% to 60%.

Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application

Note AN-905 (SNLA035) for information on setting characteristic impedance.

OEA, OEB

The OEA and OEB pin, when high, put the output pins of their respective converters into a high impedance state.

When either of these pins is low the corresponding outputs are in the active state. The ADC12D040 will continue

to convert whether these pins are high or low, but the output can not be read while the pin is high.

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Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-

STATE outputs of the ADC12L066 to drive a bus. Rather, each output pin should be located close to and drive a

single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output pin,

located close to their respective pins, should be added to the circuit.

The PD Pin

The PD pin, when high, holds the ADC12D040 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 75 mW with a 40 MHz clock and 40mW if the clock is

stopped when PD is high. The output data pins are undefined in the power down mode and the data in the

pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 4, 5, 6, 12, 13 and

14. These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry

before conversions can be accurate. Smaller capacitor values allow faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

The OF Pin

The output data format is offset binary when the OF pin is at a logic low or 2’s complement when the OF pin is at

a logic high. While the sense of this pin may be changed "on the fly," doing this is not recommended as the

output data could be erroneous for a few clock cycles after this change is made.

The INT/EXT REF Pin

The INT/EXT REF pin determines whether the internal reference or an external reference voltage is used. With

this pin at a logic low, the internal 2.0V reference is in use. With this pin at a logic high an external reference

must be applied to the V_REFpin, which should then be bypassed to ground. There is no need to bypass the V_REF

pin when the internal reference is used. There is no access to the internal reference voltage, but its value is

approximately equal to V_RP− V_RN. See Reference Pins

DATA OUTPUT PINS

The ADC12D040 has 24 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while

the OE and PD pins are low. While the t_ODtime provides information about output timing, t_ODwill change with a

change of clock frequency. At the rated 40 MHz clock rate, the data transition is about 6 to 10 ns after the rise of

the clock and about 4 to 10 ns before the fall of the clock (depending upon V_DR), so either clock edge may be

used to capture data, depending upon the data setup time of the circuit accepting the data. Also, circuit board

layout will affect relative delays of the clock and data, so it is important to consider these relative delays when

designing the digital interface. At sample frequencies below 40 MHz, there is a longer time between data

transition and the fall of the clock, so that the falling edge of the clock is generally the best edge to use for output

data capture at low sample rates.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large charging

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond the specified 20 pF/pin will cause t_ODto increase,

making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital

outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the

output currents, which could otherwise result in performance degradation. See Figure 31.

Note that, although the ADC12D040 has Tri-State outputs, these outputs should not be used to drive a bus and

the charging and discharging of large capacitances can degrade SNR performance. Each output pin should drive

only one pin of a receiving device and the interconnecting lines should be as short as practical.

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POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series

inductance.

As is the case with all high-speed converters, the ADC12D040 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mV_P-P

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during turn on and turn off of power.

The V_DRpin provides power for the output drivers and may be operated from a supply in the range of 2.35V to

V_D(nominal 5V). This can simplify interfacing to low voltage devices and systems. Note, however, that t_OD

increases with reduced V_DR. DO NOT operate the V_DRpin at a voltage higher than V_D.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12D040 between these areas, is required to achieve

specified performance.

The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12D040's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

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Figure 33. Example of a Suitable Layout

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies

beside each other.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the analog ground plane.

Figure 33 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference

components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be

placed in the digital area of the board. The ADC12DL040 should be between these two areas. Furthermore, all

components in the reference circuitry and the input signal chain that are connected to ground should be

connected together with short traces and enter the analog ground plane at a single, quiet point. All ground

connections should have a low inductance path to ground.

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DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate

the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 34. The gates used in

the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be

prevented.

Best performance will be obtained with a differential input drive, compared with a single-ended drive, as

discussed in Single-Ended Operation and Driving the Analog Input.

As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 34. Isolating the ADC Clock from other Circuitry with a Clock Tree

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above

the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not

uncommon for high speed digital components (e.g., 74F devices) to exhibit overshoot or undershoot that goes

above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending digital

input, close to the signal source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12D040 with a device that is powered from supplies outside the

range of the ADC12D040 supply. Such practice may lead to conversion inaccuracies and even to device

damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large

charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.

Additionally, bus capacitance beyond the specified 20 pF/pin will cause t_ODto increase, making it difficult to

properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance.

The digital data outputs should be buffered (with 74AC541, for example). Dynamic performance can also be

improved by adding series resistors at each digital output, close to the ADC12D040, which reduces the energy

coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors

is 100Ω.

Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen

at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is

more difficult to drive than is a fixed capacitance.

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If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor at each amplifier output and a capacitor across the analog inputs (as shown

in Figure 32) will improve performance. The LMH6702 and the LMH6628 have been successfully used to drive

the analog inputs of the ADC12D040.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, V_REF

should be in the range of

1.0V ≤ V_REF≤ 2.4V

(10)

Operating outside of these limits could lead to performance degradation.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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REVISION HISTORY

Changes from Revision D (March 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 26

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC12D040CIVS/NOPB

ACTIVE

TQFP

PAG

160

RoHS & Green

Level-3-260C-168 HR

-40 to 85

ADC12D040

CIVS

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Jun-2023

TRAY

L - Outer tray length without tabs

KO -

Outer

tray

height

W -

Outer

tray

width

Text

P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center

CL - Measurement for tray edge (X direction) to corner pocket center

Chamfer on Tray corner indicates Pin 1 orientation of packed units.

*All dimensions are nominal

Device

Package Package Pins SPQ Unit array

Max

matrix temperature

(°C)

L (mm)

Name

Type

(mm) (µm) (mm) (mm) (mm)

ADC12D040CIVS/NOPB

PAG

TQFP

160

8 X 20

150

322.6 135.9 7620 15.2

13.1

Pack Materials-Page 1

MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PAG (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

7,50 TYP

Gage Plane

10,20

9,80

0,25

12,20

0,05 MIN

11,80

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4040282/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ADC12D040 [TI]

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