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ADC12DL065 [TI]

双通道、12 位、65MSPS 模数转换器 (ADC);
ADC12DL065
型号： ADC12DL065
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

双通道、12 位、65MSPS 模数转换器 (ADC)

转换器 模数转换器
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ADC12DL065  
www.ti.com  
SNAS249D –MARCH 2005–REVISED APRIL 2013  
ADC12DL065 Dual 12-Bit, 65 MSPS, 3.3V, 360mW A/D Converter  
Check for Samples: ADC12DL065  
1
FEATURES  
DESCRIPTION  
The ADC12DL065 is a dual, low power monolithic  
CMOS analog-to-digital converter capable of  
converting analog input signals into 12-bit digital  
words at 65 Megasamples per second (MSPS). This  
converter uses a differential, pipeline architecture with  
digital error correction and an on-chip sample-and-  
hold circuit to minimize power consumption while  
providing excellent dynamic performance and a 250  
MHz Full Power Bandwidth. Operating on a single  
+3.3V power supply, the ADC12DL065 achieves 11.0  
effective bits at nyquist and consumes just 360 mW  
at 65 MSPS, including the reference current. The  
Power Down feature reduces power consumption to  
36 mW.  
2
•
•
•
•
•
•
•
Single +3.3V Supply operation  
Internal Sample-and-Hold  
Internal Reference  
Outputs 2.4V to 3.6V Compatible  
Power Down Mode  
Duty Cycle Stabilizer  
Multiplexed Output Mode  
APPLICATIONS  
•
•
•
•
•
•
•
Ultrasound and Imaging  
Instrumentation  
Communications Receivers  
Sonar/Radar  
The differential inputs provide a full scale differential  
input swing equal to 2 times VREF with the possibility  
of a single-ended input. Full use of the differential  
input is recommended for optimum performance. The  
digital outputs from the two ADC's are available on a  
single multiplexed 12-bit bus or on separate buses.  
Duty cycle stabilization and output data format are  
selectable using a quad state function pin. The output  
data can be set for offset binary or two's complement.  
xDSL  
Cable Modems  
DSP Front Ends  
KEY SPECIFICATIONS  
•
•
•
•
•
•
Resolution: 12 Bits  
To ease interfacing to lower voltage systems, the  
digital output driver power pins of the ADC12DL065  
can be connected to a separate supply voltage in the  
range of 2.4V to the analog supply voltage. This  
device is available in the 64-lead TQFP package and  
will operate over the industrial temperature range of  
−40°C to +85°C. An evaluation board is available to  
ease the evaluation process.  
DNL: ±0.4 LSB (typ)  
SNR (fIN = 10 MHz): 69 dB (typ)  
SFDR (fIN = 10 MHz): 86 dB (typ)  
Data Latency: 7 Clock Cycles  
Power Consumption  
–
–
Operating: 360 mW (typ)  
Power Down Mode: 36 mW (typ)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
ADC12DL065  
SNAS249D –MARCH 2005–REVISED APRIL 2013  
www.ti.com  
Connection Diagram  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
V
V
B-  
B+  
V
IN  
D
DB5  
DB4  
IN  
3
AGND  
4
DB3  
V
V
V
V
B
RM  
5
DB2  
B
RP  
RN  
6
DB1  
B
7
DB0/ABb  
OEB  
REF  
8
AGND  
ADC12DL065  
9
V
A
DR GND  
DA11  
DA10  
DA9  
10  
11  
12  
13  
14  
15  
16  
AGND  
MULTIPLEX  
V
V
V
V
V
A
RN  
DA8  
A
RP  
DA7  
A
RM  
DA6  
A+  
A-  
IN  
IN  
V
D
Figure 1. TQFP Package  
See Package Number PAG0064A  
2
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ADC12DL065  
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
Block Diagram  
VINA+  
VINA-  
S/H  
Stage 1  
Stage 2  
Stage 3  
Stage 8  
Stage 9  
Stage 10  
2
2
3
2
2
2
2
2
2
2
2
2
Timing  
Control  
10-Stage Pipeline Converter  
MULTIPLEX  
21  
12  
DA0-DA11 or  
D0-D11 (MUX)  
12  
Output  
MUX  
Digital  
Correction  
Buffers  
OEA  
Duty Cycle  
Stabilizer  
CLK  
2
VRP  
VRM  
VRN  
A
A
A
Reference  
Select  
Internal  
Reference  
VREF  
VRP  
VRM  
VRN  
B
B
B
11  
12  
DB1-DB11  
DB0/ABb  
OEB  
Digital  
Correction  
Output  
Buffers  
2
21  
10-Stage Pipeline Converter  
Timing  
Control  
2
2
2
2
2
2
2
3
2
2
2
2
VINB+  
VINB-  
S/H  
Stage 1  
Stage 2  
Stage 3  
Stage 8  
Stage 9  
Stage 10  
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
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Pin Descriptions and Equivalent Circuits  
Pin No.  
Symbol  
Equivalent Circuit  
Description  
ANALOG I/O  
V
A
15  
2
VINA+  
VINB+  
Differential analog input pins. With a 1.0V reference voltage the  
differential full-scale input signal level is 2.0 VP-P with each input pin  
voltage centered on a common mode voltage, VCM. The negative  
input pins may be connected to VCM for single-ended operation, but  
a differential input signal is required for best performance.  
16  
1
VINA−  
VINB−  
AGND  
V
A
This pin is the reference select pin and the external reference input.  
If (VA - 0.3V) < VREF < VA, the internal 1.0V reference is selected.  
If AGND < VREF < (AGND + 0.3V), the internal 0.5V reference is  
selected.  
7
VREF  
If a voltage in the range of 0.8V to 1.2V is applied to this pin, that  
voltage is used as the reference. VREF should be bypassed to AGND  
with a 0.1 µF capacitor when an external reference is used.  
AGND  
V
A
V
Float  
This is a four-state pin.  
DF/DCS = VA, output data format is offset binary with duty cycle  
stabilization applied to the input clock  
DF/DCS = AGND, output data format is 2's complement, with duty  
cycle stabilization applied to the input clock.  
21  
DF/DCS  
DF/DCS = VRMA or VRMB , output data is 2's complement without  
duty cycle stabilization applied to the input clock  
DF/DCS = "float", output data is offset binary without duty cycle  
stabilization applied to the input clock.  
AGND  
V
A
13  
5
VRP  
VRP  
A
B
14  
4
VRM  
VRM  
A
B
V
A
V
A
These pins are high impedance reference bypass pins. All these pins  
should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF  
capacitor should be placed between the VRPA and VRNA pins and  
between the VRPB and VRNB pins.  
VRMA and VRMB may be loaded to 1mA for use as a temperature  
stable 1.5V reference. The remaining pins should not be loaded.  
12  
6
VRN  
VRN  
A
B
V
A
AGND  
AGND  
DIGITAL I/O  
4
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
Pin Descriptions and Equivalent Circuits (continued)  
Pin No.  
Symbol  
Equivalent Circuit  
Description  
V
D
Digital clock input. The range of frequencies for this input is as  
specified in the electrical tables with ensured performance at 65  
MHz. The input is sampled on the rising edge.  
V
A
60  
CLK  
OEA and OEB are the output enable pins that, when low, holds their  
respective data output pins in the active state. When either of these  
pins is high, the corresponding outputs are in a high impedance  
state.  
22  
41  
OEA  
OEB  
AGND  
DGND  
V
D
PD is the Power Down input pin. When high, this input puts the  
converter into the power down mode. When this pin is low, the  
converter is in the active mode.  
V
A
59  
11  
PD  
When low, "A" & "B" data is present on it's respective data output  
lines (Parallel Mode).  
When high, both "A" and "B" channel data is present on the  
"DA0:DA11" digital outputs (Multiplex Mode). The DB0/ABb pin is  
used to synchronize the data.  
MULTIPLEX  
AGND  
DGND  
V
DR  
V
A
24–29  
34–39  
Digital data output pins that make up the 12-bit conversion results of  
their respective converters. DA0 and DB0 are the LSBs, while DA11  
and DB11 are the MSBs of the output word. Output levels are  
TTL/CMOS compatible. Optimum loading is < 10pF.  
DA0–DA11  
DB1–DB11  
43–47  
52–57  
When MULTIPLEX is low, this is DB0.  
When MULTIPLEX is high this is the ABb signal, which is used to  
synchronize the multiplexed data. ABb changes synchronously with  
the Multiplexed "A" and "B" channels. ABb is "high" when "A"  
channel data is valid and is "low" when "B" channel data is valid.  
42  
DB0/ABb  
AGND  
DR GND  
ANALOG POWER  
Positive analog supply pins. These pins should be connected to a  
quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors  
located within 1 cm of these power pins, and with a 10 µF capacitor.  
9, 18, 19, 62,  
63  
VA  
3, 8, 10, 17,  
20, 61, 64  
AGND  
The ground return for the analog supply.  
DIGITAL POWER  
Positive digital supply pin. This pin should be connected to the same  
quiet +3.3V source as is VA and be bypassed to DGND with a 0.1 µF  
capacitor located within 1 cm of the power pin and with a 10 µF  
capacitor.  
33, 48  
VD  
32, 49  
DGND  
The ground return for the digital supply.  
Positive driver supply pin for the ADC12DL065's output drivers. This  
pin should be connected to a voltage source of +2.4V to VD and be  
bypassed to DR GND with a 0.1 µF capacitor. If the supply for this  
pin is different from the supply used for VA and VD, it should also be  
bypassed with a 10 µF capacitor. VDR should never exceed the  
voltage on VD. All 0.1 µF bypass capacitors should be located within  
1 cm of the supply pin.  
30, 51  
VDR  
The ground return for the digital supply for the ADC12DL065's output  
drivers. These pins should be connected to the system digital  
ground, but not be connected in close proximity to the  
ADC12DL065's DGND or AGND pins. See LAYOUT AND  
GROUNDING for more details.  
23, 31, 40,  
50, 58  
DR GND  
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)(3)  
VA, VD, VDR  
4.2V  
|VA–VD|  
≤ 100 mV  
Voltage on Any Input or Output Pin  
Input Current at Any Pin(4)  
Package Input Current(4)  
Package Dissipation at TA = 25°C  
ESD Susceptibility  
−0.3V to (VA or VD +0.3V)  
±25 mA  
±50 mA  
See(5)  
Human Body Model(6)  
Machine Model(6)  
2500V  
250V  
Soldering Temperature, Infrared, 10 sec.(7)  
Storage Temperature  
235°C  
−65°C to +150°C  
Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(7)  
(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.  
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and  
specifications.  
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be  
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies  
with an input current of 25 mA to two.  
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula  
PDMAX = (TJmax - TA )/θJA. In the 64-pin TQFP, θJA is 50°C/W, so PDMAX = 2 Watts at 25°C and 800 mW at the maximum operating  
ambient temperature of 85°C. Note that the power consumption of this device under normal operation will typically be about 390 mW  
(360 typical power consumption + 30 mW TTL output loading). The values for maximum power dissipation listed above will be reached  
only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply  
voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.  
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.  
(7) Reflow temperature profiles are different for lead-free and non-lead-free packages.  
Operating Ratings(1)(2)  
Operating Temperature  
Supply Voltage (VA, VD)  
Output Driver Supply (VDR  
CLK, PD, OEA, OEB  
Analog Input Pins  
VCM  
−40°C ≤ TA ≤ +85°C  
+3.0V to +3.6V  
+2.4V to VD  
)
−0.05V to (VD + 0.05V)  
0V to 2.6V  
0.5V to 2.0V  
|AGND–DGND|  
≤100mV  
Clock Duty Cycle (DCS On)  
Clock Duty Cycle (DCS Off)  
20% to 80%  
40% to 60%  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions.  
(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.  
6
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ADC12DL065  
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
Converter Electrical Characteristics  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,  
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3)  
Units  
(Limits)  
Parameter  
Test Conditions  
Typical(4) Limits(4)  
STATIC CONVERTER CHARACTERISTICS  
Resolution with No Missing Codes  
12  
Bits (min)  
LSB (max)  
LSB (max)  
%FS (max)  
%FS (max)  
ppm/°C  
INL  
Integral Non Linearity(5)  
Differential Non Linearity  
Positive Gain Error  
±0.75  
±0.4  
±0.2  
±0.2  
10  
±1.7  
±1.0  
±2.9  
±3.2  
DNL  
PGE  
NGE  
TC GE  
Negative Gain Error  
Gain Error Tempco  
−40°C ≤ TA ≤ +85°C  
%FS (max)  
%FS (min)  
VOFF  
Offset Error (VIN+ = VIN−)  
0.18  
±0.85  
TC VOFF Offset Error Tempco  
Under Range Output Code  
Over Range Output Code  
−40°C ≤ TA ≤ +85°C  
3.6  
0
ppm/°C  
0
4095  
4095  
REFERENCE AND ANALOG INPUT CHARACTERISTICS  
0.5  
2.0  
V (min)  
V (max)  
VCM  
Common Mode Input Voltage  
Reference Output Voltage  
1.5  
1.5  
VRMA,  
Output load = 1 mA  
V
VRMB  
(CLK LOW)  
(CLK HIGH)  
8
7
pF  
CIN  
VIN Input Capacitance (each pin to GND) VIN = 2.5 Vdc + 0.7 Vrms  
pF  
0.8  
1.2  
V (min)  
V (max)  
MΩ (min)  
VREF  
External Reference Voltage(6)  
Reference Input Resistance  
1.00  
1
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes  
above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure  
accurate conversions. See Figure 2.  
(2) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.  
(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.  
(4) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing  
Quality Level).  
(5) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through  
positive and negative full-scale.  
(6) Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.2V range. The LM4051CIM3-ADJ (SOT-23  
package) is recommended for external reference applications.  
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Converter Electrical Characteristics (continued)  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,  
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3)  
Units  
(Limits)  
Parameter  
Test Conditions  
Typical(4) Limits(4)  
DYNAMIC CONVERTER CHARACTERISTICS  
FPBW  
Full Power Bandwidth  
0 dBFS Input, Output at −3 dB  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
fIN = 1 MHz, VIN = −0.5 dBFS  
fIN = 10 MHz, VIN = −0.5 dBFS  
fIN = 32.5 MHz, VIN = −0.5 dBFS  
250  
69  
MHz  
dBc  
SNR  
Signal-to-Noise Ratio  
69  
68.5  
68.5  
68.5  
68  
67.5  
67  
dBc (min)  
dBc (min)  
dBc  
SINAD  
ENOB  
THD  
H2  
Signal-to-Noise and Distortion  
Effective Number of Bits  
Total Harmonic Distortion  
Second Harmonic Distortion  
Third Harmonic Distortion  
67.5  
67  
dBc (min)  
dBc (min)  
Bits  
11.1  
11.1  
11.0  
−82  
−83.5  
−83  
−88  
−90  
−90  
−88  
−86  
−84  
86  
10.9  
10.8  
Bits (min)  
Bits (min)  
dBc  
-75  
-75  
dBc (min)  
dBc (min)  
dBc  
-80  
-80  
dBc (min)  
dBc (min)  
dBc  
H3  
-78.5  
-77  
dBc (min)  
dBc (min)  
dBc  
SFDR  
IMD  
Spurious Free Dynamic Range  
Intermodulation Distortion  
86  
78.5  
77  
dBc (min)  
dBc (min)  
85  
fIN = 9.6 MHz and 10.2 MHz, each = −6.0  
dBFS  
−74  
dBFS  
INTER-CHANNEL CHARACTERISTICS  
Channel—Channel Offset Match  
Channel—Channel Gain Match  
±0.3  
±4  
%FS  
%FS  
10 MHz Tested, Channel;  
32.5 MHz Other Channel  
90  
90  
dBc  
dBc  
Crosstalk  
10 MHz Tested, Channel;  
65 MHz Other Channel  
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DC and Logic Electrical Characteristics  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,  
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3)  
Units  
(Limits)  
Parameter  
Test Conditions  
Typical(4) Limits(4)  
CLK, PD, OEA, OEB DIGITAL INPUT CHARACTERISTICS  
VIN(1)  
VIN(0)  
IIN(1)  
IIN(0)  
CIN  
Logical “1” Input Voltage  
Logical “0” Input Voltage  
Logical “1” Input Current  
Logical “0” Input Current  
Digital Input Capacitance  
VD = 3.6V  
VD = 3.0V  
VIN = 3.3V  
VIN = 0V  
2.0  
V (min)  
V (max)  
µA  
1.0  
10  
−10  
5
µA  
pF  
DA0–DA11, DB0-DB11 DIGITAL OUTPUT CHARACTERISTICS  
VDR = 2.5V  
VDR = 3V  
2.3  
V (min)  
V (min)  
V (max)  
nA  
VOUT(1)  
VOUT(0)  
IOZ  
Logical “1” Output Voltage  
Logical “0” Output Voltage  
TRI-STATE Output Current  
IOUT = −0.5 mA  
2.7  
IOUT = 1.6 mA, VDR = 3V  
VOUT = 2.5V or 3.3V  
VOUT = 0V  
0.4  
100  
−100  
−20  
20  
nA  
+ISC  
−ISC  
COUT  
Output Short Circuit Source Current  
Output Short Circuit Sink Current  
Digital Output Capacitance  
VOUT = 0V  
mA  
VOUT = VDR  
mA  
5
pF  
POWER SUPPLY CHARACTERISTICS  
PD Pin = DGND, VREF = VA  
PD Pin = VD  
90  
12  
108  
22  
mA (max)  
mA  
IA  
Analog Supply Current  
PD Pin = DGND  
PD Pin = VD , fCLK = 0  
19  
0
mA (max)  
mA  
ID  
Digital Supply Current  
PD Pin = DGND, CL = 10 pF(5)  
PD Pin = VD, fCLK = 0  
PD Pin = DGND, CL = 10 pF(6)  
PD Pin = VD  
15  
0
mA  
mA  
IDR  
Digital Output Supply Current  
Total Power Consumption  
360  
36  
430  
mW (max)  
mW  
Rejection of Full-Scale Error with  
VA =3.0V vs. 3.6V  
PSRR1 Power Supply Rejection Ratio  
62  
dB  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes  
above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure  
accurate conversions. See Figure 2.  
(2) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.  
(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.  
(4) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing  
Quality Level).  
(5) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,  
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11  
f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at  
which that pin is toggling.  
x
(6) Excludes IDR. See DC and Logic Electrical Characteristics, Note 5.  
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AC Electrical Characteristics  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 65 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,  
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C(1)(2)(3)(4)  
Units  
Parameter  
Test Conditions  
Typical(5)  
Limits(5)  
65  
(Limits)  
MHz (min)  
MHz  
1
2
fCLK  
fCLK  
tCH  
tCL  
Maximum Clock Frequency  
Minimum Clock Frequency  
Clock High Time  
15  
7.7  
7.7  
2
Duty Cycle Stabilizer On  
3
3
ns (min)  
ns (min)  
ns (max)  
ns (min)  
ns (min)  
ns (max)  
Clock Cycles  
ns (min)  
ns (max)  
Clock Cycles  
Clock Cycles  
ns (min)  
ns (max)  
ns (max)  
ns  
Clock Low Time  
Duty Cycle Stabilizer On  
Duty Cycle Stabilizer On  
Duty Cycle Stabilizer Off  
Duty Cycle Stabilizer Off  
Duty Cycle Stabilizer Off  
Parallel mode  
tr, tf  
tCH  
tCL  
Clock Rise and Fall Times  
Clock High Time  
4
7.7  
7.7  
2
6.2  
6.2  
Clock Low Time  
tr, tf  
Clock Rise and Fall Times  
Conversion Latency  
tCONV  
7
3.5  
9
Data Output Delay after Rising Clock  
Edge  
tOD  
Parallel mode  
6.0  
6.0  
tCONV  
tCONV  
Conversion Latency  
Conversion Latency  
Multiplex mode, Channel A  
Multiplex mode, Channel B  
7.5  
8
3.5  
8
tOD  
Data Output Delay after Clock Edge  
Multiplex mode  
tSKEW  
tAD  
ABb to Data Skew  
±0.5  
2
Aperture Delay  
tAJ  
Aperture Jitter  
1.2  
10  
10  
ps rms  
tDIS  
tEN  
Data outputs into Hi-Z Mode  
Data Outputs Active after Hi-Z Mode  
ns  
ns  
1.0 µF on pins 4, 14; 0.1 µF on pins  
5,6,12,13; 10 µF between pins 5, 6 and  
between pins 12, 13  
tPD  
Power Down Mode Exit Cycle  
1
µs  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes  
above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure  
accurate conversions. See Figure 2.  
(2) To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.  
(3) With the test condition for VREF = +1.0V (2VP-P differential input), the 12-bit LSB is 488 µV.  
(4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.  
(5) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing  
Quality Level).  
V
A
I/O  
To Internal Circuitry  
AGND  
Figure 2.  
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Specification Definitions  
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for  
conversion.  
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.  
Aperture jitter manifests itself as noise in the output.  
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the  
total time of one period. The specification here refers to the ADC clock input signal.  
COMMON MODE VOLTAGE (VCM) is the common d.c. voltage applied to both input terminals of the ADC.  
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is  
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay  
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the  
conversion by the pipeline delay.  
CROSSTALK is coupling of energy from one channel into the other channel.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise  
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a  
perfect ADC of this (ENOB) number of bits.  
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental  
drops 3 dB below its low frequency value for a full scale input.  
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:  
Gain Error = Positive Full Scale Error − Offset Error  
(1)  
A gain of unity occurs when the negative and positive full scale errors are equal to each other, including having  
the same sign.  
GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average  
gain of the converters.  
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from  
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code  
transition). The deviation of any given code from this straight line is measured from the center of that code value.  
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two  
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in  
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.  
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,  
where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.  
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12DL065 is  
ensured not to have any missing codes.  
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.  
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of  
½ LSB above negative full scale.  
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN−)] required to cause a transition  
from code 2047 to 2048.  
OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the  
output pins.  
OVER RANGE RECOVERY TIME is the time required after VIN goes from a specified voltage out of the normal  
input range to a specified voltage within the normal input range and the converter makes a conversion with its  
rated accuracy.  
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.  
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POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of  
1½ LSB below positive full scale.  
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power  
supply voltage. For the ADC12DL065, PSRR1 is the ratio of the change in Full-Scale Error that results from a  
change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding  
upon the power supply is rejected at the output.  
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms  
value of the sum of all other spectral components below one-half the sampling frequency, not including  
harmonics or d.c.  
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the  
input signal to the rms value of all of the other spectral components below half the clock frequency, including  
harmonics but excluding d.c.  
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the  
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum  
that is not present at the input.  
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic  
levels at the output to the level of the fundamental at the output. THD is calculated as  
(2)  
where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power of the  
first 9 harmonic frequencies in the output spectrum.  
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in  
the input frequency at the output and the power in its 2nd harmonic level at the output.  
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in  
the input frequency at the output and the power in its 3rd harmonic level at the output.  
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Timing Diagram  
Sample N + 8  
Sample N + 7  
Sample N + 6  
Sample N  
Sample N + 9  
Sample N + 10  
V
IN  
t
AD  
1
f
CLK  
Clock N  
Clock N + 7  
90%  
10%  
90%  
10%  
CLK  
t
t
CL  
CH  
t
f
t
r
OE  
(A or B)  
t
t
t
EN  
OD  
DIS  
Parallel Output Mode  
D0 - D11  
(A or B)  
Data N - 1  
Data N  
Data N + 2  
Latency  
Multiplex Output Mode  
DB0/ABb  
t
SKEW  
t
OD  
t
OD  
DataA  
N+1  
DataB  
N+1  
DataA  
N+2  
DataB  
N+2  
DataA  
N-1  
DataB  
N-1  
DataA DataB  
D0 - D11  
N
N
Channel A Latency  
Channel B Latency  
Figure 3. Output Timing  
Transfer Characteristic  
Figure 4. Transfer Characteristic  
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Typical Performance Characteristics DNL, INL  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output  
mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
DNL  
INL  
Figure 5.  
Figure 6.  
DNL vs. fCLK  
INL vs. fCLK  
Figure 7.  
Figure 8.  
DNL vs. Clock Duty Cycle  
INL vs. Clock Duty Cycle  
Figure 9.  
Figure 10.  
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Typical Performance Characteristics DNL, INL (continued)  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output  
mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
DNL vs. Temperature  
INL vs. Temperature  
Figure 11.  
Figure 12.  
DNL vs. VDR, VA = VD = 3.6V  
INL vs. VDR, VA = VD = 3.6V  
Figure 13.  
Figure 14.  
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Typical Performance Characteristics  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 32 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel  
output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
SNR,SINAD,SFDR vs. VA  
Distortion vs. VA  
Figure 15.  
Figure 16.  
SNR,SINAD,SFDR vs. VDR, VA = VD = 3.6V  
Distortion vs. VDR, VA = VD = 3.6V  
Figure 17.  
Figure 18.  
SNR,SINAD,SFDR vs. VCM  
Distortion vs. VCM  
Figure 19.  
Figure 20.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 32 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel  
output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
SNR,SINAD,SFDR vs. fCLK  
Distortion vs. fCLK  
Figure 21.  
Figure 22.  
SNR,SINAD,SFDR vs. Clock Duty Cycle  
Distortion vs. Clock Duty Cycle  
Figure 23.  
Figure 24.  
SNR,SINAD,SFDR vs. VREF  
Distortion vs. VREF  
Figure 25.  
Figure 26.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 32 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel  
output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
SNR,SINAD,SFDR vs. fIN  
Distortion vs. fIN  
Figure 27.  
Figure 28.  
SNR,SINAD,SFDR vs. Temperature  
Distortion vs. Temperature  
Figure 29.  
Figure 30.  
tOD vs. VDR, VA = VD = 3.6V  
Parallel Output Mode  
tOD vs. VDR, VA = VD = 3.6V  
Multiplex Output Mode  
Figure 31.  
Figure 32.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.3V, VDR  
=
+2.5V, PD = 0V, VREF = +1.0V, fCLK = 65 MHz, fIN = 32 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel  
output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25°C  
Spectral Response @ 10 MHz Input  
Spectral Response @ 32 MHz Input  
Figure 33.  
Figure 34.  
Intermodulation Distortion, fIN1= 9.6 MHz, fIN2 = 10.2 MHz  
Figure 35.  
FUNCTIONAL DESCRIPTION  
Operating on a single +3.3V supply, the ADC12DL065 uses a pipeline architecture and has error correction  
circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The  
user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any  
external reference is buffered on-chip to ease the task of driving that pin.  
The output word rate is the same as the clock frequency, which can be between 15 MSPS and 65 MSPS  
(typical) with fully specified performance at 65 MSPS. The analog input for both channels is acquired at the rising  
edge of the clock and the digital data for a given sample is delayed by the pipeline for 7 clock cycles. Duty cycle  
stabilization and output data format are selectable using the quad state function DF/DCS pin. The output data  
can be set for offset binary or two's complement.  
A logic high on the power down (PD) pin reduces the converter power consumption to 36 mW.  
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Applications Information  
OPERATING CONDITIONS  
We recommend that the following conditions be observed for operation of the ADC12DL065:  
3.0V ≤ VA ≤ 3.6V  
VD = VA  
2.4V ≤ VDR ≤ VA  
15 MHz ≤ fCLK ≤ 65 MHz  
0.8V ≤ VREF ≤ 1.2V (for an external reference)  
0.5V ≤ VCM ≤ 2.0V  
Analog Inputs  
There is one reference input pin, VREF, which is used to select an internal reference, or to supply an external  
reference. The ADC12DL065 has two analog signal input pairs, VIN A+ and VIN A- for one converter and VIN B+  
and VIN B- for the other converter. Each pair of pins forms a differential input pair.  
Reference Pins  
The ADC12DL065 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference,  
but performs well with reference voltages in the range of 0.8V to 1.2V. Lower reference voltages will decrease  
the signal-to-noise ratio (SNR) of the ADC12DL065. Increasing the reference voltage (and the input signal swing)  
beyond 1.2V may degrade THD for a full-scale input, especially at higher input frequencies.  
It is important that all grounds associated with the reference voltage and the analog input signal make connection  
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.  
The six Reference Bypass Pins (VRPA, VRMA, VRNA, VRPB, VRMB and VRNB) are made available for bypass  
purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10 µF capacitor should  
be placed between the VRPA and VRNA pins and between the VRPB and VRNB pins, as shown in Figure 38. This  
configuration is necessary to avoid reference oscillation, which could result in reduced SFDR and/or SNR.  
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may  
result in degraded noise performance. Loading any of these pins other than VRMA and VRMB may result in  
performance degradation.  
The nominal voltages for the reference bypass pins are as follows:  
VRM = 1.5 V  
VRP = VRM + VREF / 2  
VRN = VRM − VREF / 2  
User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use  
when the the VREF pin is connected to VA. When the VREF pin is connected to AGND, the internal 0.5 Volt  
reference is in use. If a voltage in the range of 0.8V to 1.2V is applied to the VREF pin, that is used for the voltage  
reference. When an external reference is used, the VREF pin should be bypassed to ground with a 0.1 µF  
capacitor close to the reference input pin. There is no need to bypass the VREF pin when the internal reference is  
used.  
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Signal Inputs  
The signal inputs are VIN A+ and VINA− for one ADC and VINB+ and VINB− for the other ADC . The input signal,  
VIN, is defined as  
VIN A = (VINA+) – (VINA−)  
(3)  
for the "A" converter and  
VIN B = (VINB+) – (VINB−)  
(4)  
for the "B" converter. Figure 36 shows the expected input signal range. Note that the common mode input  
voltage, VCM, should be in the range of 0.5V to 2.0V.  
The peaks of the individual input signals should each never exceed 2.6V.  
The ADC12DL065 performs best with a differential input signal with each input centered around a common mode  
voltage, VCM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the  
reference voltage or the output data will be clipped.  
The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single  
frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms,  
however, angular errors will result in distortion.  
Figure 36. Expected Input Signal Range  
For single frequency sine waves the full scale error in LSB can be described as approximately  
EFS = 4096 ( 1 - sin (90° + dev))  
(5)  
Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship  
to each other (see Figure 37). Drive the analog inputs with a source impedance less than 100Ω.  
Figure 37. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause  
Distortion  
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal  
to the reference voltage, VREF, be 180 degrees out of phase with each other and be centered around VCM  
.
Single-Ended Operation  
Performance with differential input signals is better than with single-ended signals. For this reason, single-ended  
operation is not recommended. However, if single ended-operation is required and the resulting performance  
degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the  
driven input. The peak-to-peak differential input signal at the driven input pin should be twice the reference  
voltage to maximize SNR and SINAD performance (Figure 36b). For example, set VREF to 0.5V, bias VIN− to 1.0V  
and drive VIN+ with a signal range of 0.5V to 1.5V.  
Because very large input signal swings can degrade distortion performance, better performance with a single-  
ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and  
Table 2 indicate the input to output relationship of the ADC12DL065.  
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Table 1. Input to Output Relationship – Differential Input  
+
−
VIN  
VIN  
Binary Output  
0000 0000 0000  
0100 0000 0000  
1000 0000 0000  
1100 0000 0000  
1111 1111 1111  
2’s Complement Output  
V
CM − VREF/2  
CM − VREF/4  
VCM  
VCM + VREF/2  
VCM + VREF/4  
VCM  
1000 0000 0000  
1100 0000 0000  
0000 0000 0000  
0100 0000 0000  
0111 1111 1111  
V
VCM + VREF/4  
VCM + VREF/2  
V
CM − VREF/4  
CM − VREF/2  
V
Table 2. Input to Output Relationship – Single-Ended Input  
+
−
VIN  
VIN  
Binary Output  
0000 0000 0000  
0100 0000 0000  
1000 0000 0000  
1100 0000 0000  
1111 1111 1111  
2’s Complement Output  
1000 0000 0000  
1100 0000 0000  
0000 0000 0000  
0100 0000 0000  
0111 1111 1111  
V
CM − VREF  
VCM  
VCM  
VCM  
VCM  
VCM  
V
CM − VREF/2  
VCM  
VCM + VREF/2  
VCM + VREF  
Driving the Analog Inputs  
The VIN+ and the VIN− inputs of the ADC12DL065 consist of an analog switch followed by a switched-capacitor  
amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when  
the clock is low, and 7 pF when the clock is high.  
As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in  
voltage spikes at the signal input pins. As a driving amplifier attempts to counteract these voltage spikes, a  
damped oscillation may appear at the ADC analog input. Do not attempt to filter out these pulses. Rather, use  
amplifiers to drive the ADC12DL065 input pins that are able to react to these pulses and settle before the switch  
opens and another sample is taken. The LMH6702 LMH6628, LMH6622 and the LMH6655 are good amplifiers  
for driving the ADC12DL065.  
To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in  
Figure 38 through Figure 40. These components should be placed close to the ADC inputs because the input  
pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter that input.  
For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the  
sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC  
pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response.  
A single-ended to differential conversion circuit is shown in Figure 40. Table 3 gives resistor values for that circuit  
to provide input signals in a range of 1.0V ±0.5V at each of the differential input pins of the ADC12DL065.  
Table 3. Resistor Values for Circuit of Figure 40  
SIGNAL RANGE  
0 - 0.25V  
R1  
open  
0Ω  
R2  
0Ω  
R3  
R4  
R5, R6  
1000Ω  
499Ω  
124Ω  
499Ω  
100Ω  
1500Ω  
1500Ω  
698Ω  
0 - 0.5V  
openΩ  
698Ω  
±0.25V  
100Ω  
499Ω  
Input Common Mode Voltage  
The input common mode voltage, VCM, should be in the range of 0.5V to 2.0V and be a value such that the peak  
excursions of the analog signal does not go more negative than ground or more positive than 2.6V. See  
Reference Pins.  
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DIGITAL INPUTS  
Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, PD, DF/DCS, and MULTIPLEX.  
CLK  
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock  
signal in the range of 15 MHz to 65 MHz with rise and fall times of 2 ns or less. The trace carrying the clock  
signal should be as short as possible and should not cross any other signal line, analog or digital, not even at  
90°.  
The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the  
charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This  
is what limits the lowest sample rate.  
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to  
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905  
(SNLA035) for information on setting characteristic impedance.  
It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is  
used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in  
Figure 38, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor  
value is  
(6)  
where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic  
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it  
as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of  
"L" and tPD should be the same (inches or centimeters).  
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise  
duty cycle is difficult, the ADC12DL065 has a Duty Cycle Stabilizer which can be enabled using the DF/DCS pin.  
It is designed to maintain performance over a clock duty cycle range of 20% to 80% at 65 MSPS. The Duty Cycle  
Stabilizer circuit requires a fast clock edge to produce the internal clock, which is the reason for the rise and fall  
time requirement listed in the specifications table.  
OEA, OEB  
The OEA and OEB pins, when high, put the output pins of their respective converters into a high impedance  
state. When either of these pin is low, the corresponding outputs are in the active state. The ADC12DL065 will  
continue to convert whether these pins are high or low, but the output can not be read while the pin is high.  
Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-  
STATE outputs of the ADC12DL065 to drive a bus. Rather, each output pin should be located close to and drive  
a single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output  
pin, located close to their respective pins, should be added to the circuit.  
PD  
The PD pin, when high, holds the ADC12DL065 in a power-down mode to conserve power when the converter is  
not being used. The power consumption in this state is 36 mW with a 65MHz clock and 40mW if the clock is  
stopped when PD is high. The output data pins are undefined and the data in the pipeline is corrupted while in  
the power down mode.  
The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and  
14 and is about 500 µs with the recommended components on the VRP, VRM and VRN reference bypass pins.  
These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before  
conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,  
but can result in a reduction in SNR, SINAD and ENOB performance.  
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DF/DCS  
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,  
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 20% to 80% and generate  
a stable internal clock, improving the performance of the part. The Duty Cycle Stabilizer circuit requires a fast  
clock edge to produce the internal clock, which is the reason for the rise and fall time requirement listed in the  
specifications table. With DF/DCS = VA the output data format is offset binary and duty cycle stabilization is  
applied to the clock. With DF/DCS = 0 the output data format is 2's complement and duty cycle stabilization is  
applied to the clock. With DF/DCS = VRMA or VRMB the output data format is 2's complement and duty cycle  
stabilization is not used. If DF/DCS is floating, the output data format is offset binary and duty cycle stabilization  
is not used. While the sense of this pin may be changed "on the fly," doing this is not recommended as the  
output data could be erroneous for a few clock cycles after this change is made.  
MULTIPLEX  
With the MULTIPLEX pin at a logic low, the digital output words from channels A and B are available on separate  
digital output buses (Parallel mode). When MULTIPLEX is high, the digital output words are multiplexed on pins  
DA0:DA11 (Multiplex Mode). The DB0/ABb pin changes synchronously with the multiplexed outputs, and is high  
when channel A data is present on the outputs, and low when channel B data is present.  
OUTPUTS  
The ADC12DL065 has 12 TTL/CMOS compatible Data Output pins for each output. Valid data is present at  
these outputs while the OE and PD pins are low. In the parallel mode, the data should be captured with the CLK  
signal. Depending on the setup and hold time requirements of the receiving circuit (ASIC), either the rising edge  
or the falling edge of the CLK signal can be used to latch the data. Generally, rising-edge-capture would  
maximize setup time with minimal hold time; while falling-edge-capture would maximize hold time with minimal  
setup time. However, actual timing for the falling-edge case depends greatly on the CLK frequency and both  
cases also depend on the delays inside the ASIC. Refer to the Tod spec in AC Electrical Characteristics.  
In Multiplex mode, both channel outputs are available on DA0:DA11. The ABb signal is available to de-multiplex  
the output bus. The ABb signal may also be used to latch the data in the ASIC thus avoiding the use of the CLK  
signal altogether. However, since the ABb signal edges are provided in-phase with the data transitions, generally  
the ASIC circuitry would have to delay the ABb signal with respect to the data in order to use it as the clock for  
the capturing latches. It is also possible to use the CLK signal to latch the data in the multiplexed mode as well -  
as described in the previous paragraph.  
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for  
each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging  
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic  
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will  
reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase,  
making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic  
performance.  
To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by  
connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven  
input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital  
outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the  
output currents, which could otherwise result in performance degradation. See Figure 38.  
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+3.0V  
+
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
CHOKE  
3x 0.1 mF  
2x 0.1 mF  
2x 0.1 mF  
10 mF  
11  
1
1k  
CLK  
OE  
7
57  
ChB  
Output Word  
V
DB11  
REF  
56  
55  
54  
53  
52  
47  
46  
45  
44  
43  
42  
DB10  
DB9  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
74ACT574  
4
5
6
V
V
B
RM  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
1 mF  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
B
330  
RP  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
10 mF  
V
B
RN  
0.1 mF  
0.1 mF  
14  
13  
12  
V
V
A
RM  
1 mF  
0.1 mF  
**  
A
RP  
DB0/ABb  
10 mF  
51  
51  
11  
1
V
IN_B  
0.1 mF  
CLK  
OE  
V
A
RN  
12x100W  
1
6
4
T2  
0.1 mF  
39 pF  
39 pF  
0.1 mF  
2
3
1
2
74ACT574  
V
V
B-  
IN  
B+  
IN  
T4-6T  
ADC12DL065  
330  
**  
V
51  
51  
IN_A  
0.1 mF  
1
6
4
T2  
39 pF  
39 pF  
0.1 mF  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
2
16  
15  
V
V
A-  
IN  
39  
38  
37  
36  
35  
34  
29  
28  
27  
26  
25  
24  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
DA11  
DA10  
DA9  
DA8  
DA7  
DA6  
DA5  
DA4  
DA3  
DA2  
DA1  
DA0  
A+  
3
IN  
T4-6T  
47  
60  
21  
11  
22  
41  
59  
Crystal Oscillator  
DF/DCS  
CLK  
11  
1
CLK  
OE  
DF/DCS  
ChA  
Output Word  
MULTIPLEX  
OEA  
74ACT574  
OEA  
OEB  
PD  
OEB  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
12x100W  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
PD  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
See  
Text  
11  
1
CLK  
OE  
74ACT574  
A. ** – May be replaced by Ckt in Figure 40.  
Figure 38. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Parallel mode  
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2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
+3.0V  
CHOKE  
3x 0.1 mF  
2x 0.1 mF  
2x 0.1 mF  
+
10 mF  
11  
1
CLK  
OE  
Channel B  
Output Word  
1k  
74ACT574  
7
57  
V
DB11  
REF  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
56  
55  
54  
53  
52  
47  
46  
45  
44  
43  
42  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
DB10  
DB9  
DB8  
DB7  
DB6  
DB5  
DB4  
DB3  
DB2  
DB1  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
4
5
6
V
V
B
RM  
0.1 mF  
B
330  
RP  
10 mF  
V
B
RN  
0.1 mF  
0.1 mF  
14  
13  
12  
11  
1
V
V
A
RM  
CLK  
OE  
0.1 mF  
***  
***  
0.1 mF  
**  
A
RP  
DB0/ABb  
10 mF  
51  
51  
V
IN_B  
0.1 mF  
V
A
RN  
74ACT574  
1
6
4
T2  
0.1 mF  
39 pF  
39 pF  
0.1 mF  
2
3
1
2
V
V
B-  
IN  
B+  
IN  
T4-6T  
ADC12DL065  
330  
**  
V
51  
51  
IN_A  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
0.1 mF  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
1
6
4
T2  
39  
38  
37  
36  
35  
34  
29  
28  
27  
26  
25  
24  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
39 pF  
39 pF  
0.1 mF  
DA11  
DA10  
DA9  
DA8  
DA7  
DA6  
DA5  
DA4  
DA3  
DA2  
DA1  
DA0  
2
3
16  
15  
V
V
A-  
IN  
A+  
IN  
T4-6T  
11  
1
47  
CLK  
OE  
60  
21  
11  
22  
41  
59  
Clock In  
DF/DCS  
Multiplex  
CLK  
Channel A  
Output Word  
DF/DCS  
74ACT574  
MULTIPLEX  
OEA  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
12x100W  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D8  
Q1  
OEA  
OEB  
PD  
Q2  
Q3  
Q4  
Q5  
Q6  
Q7  
Q8  
OEB  
PD  
See  
Text  
11  
1
CLK  
OE  
74ACT574  
A. ** – May be replaced by Ckt in Figure 40.  
B. *** – The delay through the inverters should be adjusted to allow the correct setup and hold time for the latches.  
Figure 39. Application Circuit using Transformer or Differential Op-Amp Drive Circuit, Multiplex mode  
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2V  
R2, 1%  
R1, 1%  
5k, 1%  
+
2.4k  
*
to  
U2B  
+
*
V
+
IN  
-
51  
U1A  
-
5k, 1%  
#
SIGNAL  
INPUT  
39 pF  
51  
R5, 1%  
5k, 1%  
5k, 1%  
*
R4, 1%  
#
39 pF  
R3, 1%  
5k, 1%  
2.4k  
+
*
to  
U1B  
+
V
-
IN  
-
51  
U2A  
5k, 1%  
-
*
R6, 1%  
5k, 1%  
A. Amplifiers: two LMH6622s or LMH6655s  
B. * – The ground connections indicated with an "*" should be connected to a common point in the analog ground plane.  
C. # – The 39 pF capacitors between the two inputs are for Nyquiest applications and should be removed for  
undersampling applications.  
Figure 40. Differential Drive Circuit of Figure 38  
POWER SUPPLY CONSIDERATIONS  
The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor  
within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series  
inductance.  
As is the case with all high-speed converters, the ADC12DL065 is sensitive to power supply noise. Accordingly,  
the noise on the analog supply pin should be kept below 100 mVP-P  
.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be  
especially careful of this during power turn on and turn off.  
The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.4V to VD.  
This can simplify interfacing to lower voltage devices and systems. Note, however, that tOD increases with  
reduced VDR. DO NOT operate the VDR pin at a voltage higher than VD.  
LAYOUT AND GROUNDING  
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining  
separate analog and digital areas of the board, with the ADC12DL065 between these areas, is required to  
achieve specified performance.  
The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output  
current can exhibit high transients that could add noise to the conversion process. To prevent this from  
happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the  
ADC12DL065's other ground pins.  
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor  
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the  
clock line as short as possible.  
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could  
have significant impact upon system noise performance. The best logic family to use in systems with A/D  
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the  
74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest  
supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.  
The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω  
resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.  
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Since digital switching transients are composed largely of high frequency components, total ground plane copper  
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area  
is more important than is total ground plane volume.  
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in  
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to  
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the  
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause  
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to  
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.  
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the  
signal path through all components should form a straight line wherever possible.  
6 x 100W  
Clock line should be short  
and cross no other lines.  
COMMON  
OSC  
GROUND  
PLANE  
LATCH  
All Analog Components  
mounted over Analog  
area of Ground Plane  
All Digital  
Components  
mounted over  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
Xfmr/Amplifier  
Digital area of  
Ground Plane  
1
2
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
6 x 100W  
V
V
V
B-  
IN  
IN  
D
DB5  
DB4  
B+  
3
AGND  
4
V
B
DB3  
RM  
LATCH  
5
V
B
B
DB2  
RP  
6
V
DB1  
Driving source  
located close  
to converter.  
RN  
7
V
DB0  
Single Ground entry for all  
Reference Components  
REF  
AGND  
8
OEB  
DR GND  
DA11  
DA10  
DA9  
9
ADC12DL065  
V
A
10  
11  
12  
13  
14  
15  
16  
AGND  
INT/EXT REF  
V
A
A
A
RN  
V
DA8  
RP  
V
V
V
DA7  
RM  
DA6  
A+  
A-  
IN  
IN  
V
D
Analog power line should be routed  
away from Digital power trace.  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
Digital power line should be routed  
away from analog power trace.  
Ground entry points  
close to ground pins.  
Figure 41. Example of a Suitable Layout  
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit  
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies  
beside each other.  
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.  
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to  
the reference input pin and ground should be connected to a very clean point in the ground plane.  
Figure 41 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference  
components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be  
placed in the digital area of the board. The ADC12DL065 should be between these two areas. Furthermore, all  
components in the reference circuitry and the input signal chain that are connected to ground should be  
connected together with short traces and enter the ground plane at a single, quiet point. All ground connections  
should have a low inductance path to ground.  
28  
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DYNAMIC PERFORMANCE  
To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate  
the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 42. The gates used in  
the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be  
prevented.  
Best performance will be obtained with a differential input drive, compared with a single-ended drive, as  
discussed in Single-Ended Operation and Driving the Analog Inputs.  
As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible  
and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can  
lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°  
crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.  
Figure 42. Isolating the ADC Clock from other Circuitry with a Clock Tree  
COMMON APPLICATION PITFALLS  
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should  
not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above  
the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not  
uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot  
that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending  
digital input, close to the signal source, will eliminate the problem.  
Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or  
power down.  
Be careful not to overdrive the inputs of the ADC12DL065 with a device that is powered from supplies outside  
the range of the ADC12DL065 supply. Such practice may lead to conversion inaccuracies and even to device  
damage.  
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must  
charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large  
charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate  
bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.  
Additionally, bus capacitance beyond the specified 15 pF/pin will cause tOD to increase, making it difficult to  
properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance.  
The digital data outputs should be buffered (with 74ACQ541, for example). Dynamic performance can also be  
improved by adding series resistors at each digital output, close to the ADC12DL065, which reduces the energy  
coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors  
is 100Ω.  
Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen  
at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is  
more difficult to drive than is a fixed capacitance.  
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If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade  
performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in  
Figure 39 and Figure 40) will improve performance. The LMH6702 and the LMH6628 have been successfully  
used to drive the analog inputs of the ADC12DL065.  
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of  
phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will  
affect the effective phase between these two signals. Remember that an operational amplifier operated in the  
non-inverting configuration will exhibit more time delay than will the same device operating in the inverting  
configuration.  
Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, VREF  
should be in the range of  
0.8V ≤ VREF ≤ 1.2V  
(7)  
Operating outside of these limits could lead to performance degradation.  
Inadequate network on Reference Bypass pins (VRPA, VRNA, VRMA, VRPB, VRNB and VRMB). As mentioned in  
Reference Pins, these pins should be bypassed with 0.1 µF capacitors to ground at VRMA and VRMB and with a  
series RC of 1.5 Ω and 1.0 µF between pins VRPA and VRNA and between VRPB and VRNB for best performance.  
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other  
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive  
output noise and a reduction in SNR and SINAD performance.  
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SNAS249D –MARCH 2005–REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision C (April 2013) to Revision D  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 30  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
ADC12DL065CIVS/NOPB  
ACTIVE  
TQFP  
PAG  
64  
160  
RoHS & Green  
SN  
Level-3-260C-168 HR  
-40 to 85  
ADC12DL065  
CIVS  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jun-2023  
TRAY  
L - Outer tray length without tabs  
KO -  
Outer  
tray  
height  
W -  
Outer  
tray  
width  
Text  
P1 - Tray unit pocket pitch  
CW - Measurement for tray edge (Y direction) to corner pocket center  
CL - Measurement for tray edge (X direction) to corner pocket center  
Chamfer on Tray corner indicates Pin 1 orientation of packed units.  
*All dimensions are nominal  
Device  
Package Package Pins SPQ Unit array  
Max  
matrix temperature  
(°C)  
L (mm)  
W
K0  
P1  
CL  
CW  
Name  
Type  
(mm) (µm) (mm) (mm) (mm)  
ADC12DL065CIVS/  
NOPB  
PAG  
TQFP  
64  
160  
8 X 20  
150  
322.6 135.9 7620 15.2  
13.1  
13  
Pack Materials-Page 1  
MECHANICAL DATA  
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996  
PAG (S-PQFP-G64)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
48  
M
0,08  
33  
49  
32  
64  
17  
0,13 NOM  
1
16  
7,50 TYP  
Gage Plane  
10,20  
SQ  
9,80  
0,25  
12,20  
SQ  
0,05 MIN  
11,80  
0°–7°  
1,05  
0,95  
0,75  
0,45  
Seating Plane  
0,08  
1,20 MAX  
4040282/C 11/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
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TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
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