ADC12DL066CIVS/NOPB_技术文档

ADC12DL066

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ADC12DL066 Dual 12-Bit, 66 Msps, 450 MHz Input Bandwidth A/D Converter w/Internal

Reference

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1

FEATURES

DESCRIPTION

The ADC12DL066 is a dual, low power monolithic

CMOS analog-to-digital converter capable of

converting analog input signals into 12-bit digital

words at 66 Megasamples per second (Msps),

minimum. This converter uses a differential, pipeline

architecture with digital error correction and an on-

chip sample-and-hold circuit to minimize die size and

power consumption while providing excellent dynamic

performance and a 450 MHz Full Power Bandwidth.

Operating on a single 3.3V power supply, the

ADC12DL066 achieves 10.7 effective bits and

consumes just 686 mW at 66 Msps, including the

reference current. The Power Down feature reduces

power consumption to 75 mW.

2

•

Choice of Binary or 2’s Complement Output

Format

•

Single +3.3V Supply Operation

Outputs 2.4V to 3.3V Compatible

Pin Compatible with ADC12D040

Power Down Mode

Internal/External Reference

KEY SPECIFICATIONS

•

Resolution: 12 Bits

DNL: ±0.5 LSB (typ)

SNR (f_IN= 10 MHz): 66 dB (typ)

SFDR (f_IN= 10 MHz): 81 dB (typ)

Power Consumption

The differential inputs provide a full scale differential

input swing equal to 2 times V_REFwith the possibility

of a single-ended input. Full use of the differential

input is recommended for optimum performance. The

digital outputs from the two ADCs are available on

separate 12-bit buses with an output data format

choice of offset binary or two’s complement.

–

Operating: 686 mW (typ)

Power Down Mode: 75 mW (typ)

APPLICATIONS

To ease interfacing to lower voltage systems, the

digital output driver power pins of the ADC12DL066

can be connected to a separate supply voltage in the

range of 2.4V to the digital supply voltage.

•

Ultrasound and Imaging

Instrumentation

Communications Receivers

Sonar/Radar

This device is available in the 64-lead TQFP package

and will operate over the industrial temperature range

of −40°C to +85°C. An evaluation board is available

to ease the evaluation process.

xDSL

Cable Modems

DSP Front Ends

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12DL066

SNAS188G –FEBRUARY 2004–REVISED FEBRUARY 2013

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Block Diagram

V

A+

A-

IN

V

Stage

1

Stage

2

Stage

3

Stage

n

Stage

9

Stage

10

Stage

11

A

S/H

V

IN

AGND

2

Timing

Control

22

11-Stage Pipeline Converter

3

CLK

V

D

Digital Correction

DGND

12

DA0-DA11

OEA

V

A

RP

Output

Buffers

V

A

RM

V

RN

V

DR

INT/EXT REF

DR GND

OF

Bandgap

Reference

V

REF

V

B

RP

12

DB0-DB11

OEB

Output

Buffers

V

RM

V

RN

12

DGND

PD

Digital Correction

V

D

3

11-Stage Pipeline Converter

Timing

Control

22

2

V

A

V

B-

IN

Stage

1

Stage

2

Stage

3

Stage

n

Stage

9

Stage

10

Stage

11

S/H

AGND

V

B+

IN

2

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Connection Diagram

Figure 1. 64-Lead TQFP Package

Package Number PAG

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

15

2

V_INA+

V_INB+

Differential analog input pins. With a 1.0V reference voltage the

differential full-scale input signal level is 2.0 V_P-Pwith each input pin

voltage centered on a common mode voltage, V_CM. The negative

input pins may be connected to V_CMfor single-ended operation, but

a differential input signal is required for best performance.

16

1

V_INA−

V_INB−

Reference input. This pin should be bypassed to AGND with a 0.1

µF capacitor when an external reference is used. V_REFis 1.0V

nominal and should be between 0.8V to 1.5V.

V

A

7

V_REF

Reference source select pin. With a logic low at this pin the internal

1.0V reference is selected and the V_REFpin need not be driven.

With a logic high on this pin an external reference voltage should

be applied to V_REFinput pin 7.

11

INT/EXT REF

DGND

V_RP

A

B

13

5

These pins are high impedance reference bypass pins only; they

are not reference output pins. Bypass per Reference Pins. DO

NOT LOAD these pins.

14

4

V_RM

A

B

V_RN

A

B

12

6

4

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)

Pin No.

Symbol

Equivalent Circuit

Description

DIGITAL I/O

Digital clock input. The range of frequencies for this input is as

specified in the electrical tables with guaranteed performance at 66

MHz. The input is sampled on the rising edge of this input.

60

CLK

V

A

OEA and OEB are the output enable pins that, when low, holds

their respective data output pins in the active state. When either of

these pins is high, the corresponding outputs are in a high

impedance state.

22

41

OEA

OEB

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

59

21

PD

OF

Output Format pin. A logic low on this pin causes output data to be

in offset binary format. A logic high on this pin causes the output

data to be in 2’s complement format.

DGND

24–29

34–39

DA0–DA11

Digital data output pins that make up the 12-bit conversion results

of their respective converters. DA0 and DB0 are the LSBs, while

DA11 and DB11 are the MSBs of the output words. Output levels

are TTL/CMOS compatible.

42–47

52–57

DB0–DB11

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet +3.3V source and bypassed to AGND with 0.1 µF capacitors

located within 1 cm of these power pins, and with a 10 µF

capacitor.

9, 18, 19, 62,

63

V_A

3, 8, 10, 17,

20, 61, 64

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the

same quiet +3.3V source as is V_Aand be bypassed to DGND with

a 0.1 µF capacitor located within 1 cm of the power pin and with a

10 µF capacitor.

33, 48

V_D

32, 49

DGND

The ground return for the digital supply.

Positive digital supply pin for the ADC12DL066's output drivers.

This pin should be connected to a voltage source of +2.4V to V_D

and be bypassed to DR GND with a 0.1 µF capacitor. If the supply

for this pin is different from the supply used for V_Aand V_D, it should

also be bypassed with a 10 µF capacitor. V_DRshould never exceed

the voltage on V_D. All bypass capacitors should be located within 1

cm of the supply pin.

30, 51

V_DR

The ground return for the digital supply for the ADC12DL066's

output drivers. These pins should be connected to the system

digital ground, but not be connected in close proximity to the

ADC12DL066's DGND or AGND pins. See LAYOUT AND

GROUNDING (Layout and Grounding) for more details.

23, 31, 40,

50, 58

DR GND

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings^(1)(2)(3)

V_A, V_D, V_DR

4.2V

|V_A–V_D|

≤ 100 mV

Voltage on Any Input or Output Pin

Input Current at Any Pin⁽⁴⁾

Package Input Current⁽⁴⁾

Package Dissipation at T_A= 25°C

ESD Susceptibility⁽⁶⁾

−0.3V to (V_Aor V_D+0.3V)

±25 mA

±50 mA

See⁽⁵⁾

Human Body Model

Machine Model

2500V

250V

Soldering Temperature, Infrared, 10 sec.⁽⁷⁾

Storage Temperature

235°C

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature, (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A) / θ_JA. The values for maximum power dissipation will only be reached when the device is operated in a severe

fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).

Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

(7) The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the

temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body

must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.

Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

V_REFInput

−40°C ≤ T_A≤ +85°C

+3.0V to +3.6V

+2.4V to V_D

)

0.8V to 1.5V

CLK, PD, OE

−0.05V to (V_D+ 0.05V)

0V to (V_A− 0.5V)

0.5V to 1.5V

Analog Input Pins

Common Mode Input Voltage

(V_CM

)

|AGND–DGND|

≤100mV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see

the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics

may degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Package Thermal Resistance

Package

θ_J-A

64-Lead TQFP

50°C / W

6

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

=

+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V_REF= +1.0V, f_CLK= 66 MHz, f_IN= 10 MHz, t_r= t_f= 2 ns, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(4)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12

Bits (min)

LSB (max)

%FS (max)

ppm/°C

INL

Integral Non Linearity⁽⁵⁾

Differential Non Linearity

Positive Gain Error

±1.2

±0.5

±0.2

−60

±3.0

±1.0

±3.6

DNL

PGE

NGE

TC GE

Negative gain Error

Gain Error Tempco

−40°C ≤ T_A≤ +85°C

+1.3

-0.9

%FS (max)

%FS (min)

V_OFF

Offset Error (V_IN+ = V_IN−)

0.18

TC V_OFFOffset Error Tempco

Under Range Output Code

Over Range Output Code

−40°C ≤ T_A≤ +85°C

−2.4

0

ppm/°C

0

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

0.5

1.5

V (min)

V (max)

pF

V_CM

Common Mode Input Voltage

1.0

(CLK LOW)

(CLK HIGH)

8

7

C_IN

V_INInput Capacitance (each pin to GND) V_IN= 2.5 Vdc + 0.7 V_rms

pF

0.8

1.5

V (min)

V (max)

MΩ (min)

V_REF

R_REF

External Reference Voltage⁽⁶⁾

Reference Input Resistance

1.00

100

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average Outgoing

Quality Level).

(5) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through

positive and negative full-scale.

(6) Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ (SOT-23

package) is recommended for external reference applications.

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Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V_REF= +1.0V, f_CLK= 66 MHz, f_IN= 10 MHz, t_r= t_f= 2 ns, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)

=

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(4)

DYNAMIC CONVERTER CHARACTERISTICS

FPBW

SNR

Full Power Bandwidth

Signal-to-Noise Ratio

0 dBFS Input, Output at −3 dB

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146 MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0,5 dBFS

f_IN= 33 MHz, V_IN= −0,5 dBFS

f_IN= 146MHz, V_IN= −0,5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146MHz, V_IN= −0.5 dBFS

f_IN= 1 MHz, V_IN= −0.5 dBFS

f_IN= 10 MHz, V_IN= −0.5 dBFS

f_IN= 33 MHz, V_IN= −0.5 dBFS

f_IN= 146MHz, V_IN= −0.5 dBFS

450

66

MHz

dB

66

64

dB (min)

dB

64

55

dB

66

dB

66

63.3

dB (min)

dB

SINAD

ENOB

THD

H2

Signal-to-Noise and Distortion

Effective Number of Bits

Total Harmonic Distortion

Second Harmonic Distortion

Third Harmonic Distortion

63

53

dB

10.7

10.3

8.7

−78

−70

−59

−90

−85

−72

−67

−83

−85

−76

−66

79

Bits

10.2

Bits (min)

Bits

dB

−67.8

−70.4

−71.0

68.5

dB (min)

dB

dB (min)

dB

dB (min)

dB

H3

dB

81

dB (min)

dB

SFDR

IMD

Spurious Free Dynamic Range

Intermodulation Distortion

72

63

dB

f_IN= 9.6 MHz and 10.2 MHz, each = −6.0

dBFS

−64

dBFS

INTER-CHANNEL CHARACTERISTICS

Channel—Channel Offset Match

Channel—Channel Gain Match

±0.03

±0.1

%FS

10 MHz Tested, Channel;

20 MHz Other Channel

80

63

dB

Crosstalk

10 MHz Tested, Channel;

195 MHz Other Channel

8

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

=

+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V_REF= +1.0V, f_CLK= 66 MHz, f_IN= 10 MHz, t_r= t_f= 2 ns, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25°C^(1)(2)(3)

Typical

Limits

Units

(Limits)

Symbol

Parameter

Conditions

(4)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

V_D= 3.6V

V_D= 3.0V

V_IN= 3.3V

V_IN= 0V

2.0

1.0

V (min)

V (max)

µA

10

−10

5

µA

pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V_DR= 2.5V

V_DR= 3V

2.3

2.7

0.4

V (min)

V (max)

nA

V_OUT(1)

V_OUT(0)

I_OZ

Logical “1” Output Voltage

Logical “0” Output Voltage

TRI-STATE Output Current

I_OUT= −0.5 mA

I_OUT= 1.6 mA, V_DR= 3V

V_OUT= 2.5V or 3.3V

V_OUT= 0V

100

−100

−20

20

nA

+I_SC

−I_SC

C_OUT

Output Short Circuit Source Current

Output Short Circuit Sink Current

Digital Output Capacitance

V_OUT= 0V

mA

V_OUT= V_DR

mA

5

pF

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND, V_REF= 1.0V

PD Pin = V_D

177

14

237

34

mA (max)

mA

I_A

Analog Supply Current

PD Pin = DGND

PD Pin = V_D, f_CLK= 0

31

8.7

mA (max)

mA

I_D

Digital Supply Current

PD Pin = DGND, C_L= 0 pF⁽⁵⁾

PD Pin = V_D, f_CLK= 0

PD Pin = DGND, C_L= 0 pF⁽⁶⁾

PD Pin = V_D, f_CLK= 0

<2

0

mA

I_DR

Digital Output Supply Current

Total Power Consumption

686

75

895

mW (max)

mW

Rejection of Full-Scale Error with

V_A= 3.0V vs. 3.6V

PSRR1 Power Supply Rejection Ratio

PSRR2 Power Supply Rejection Ratio

56

44

dB

Rejection of Power Supply Noise with 10

MHz, 500 mV riding on V_A

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average Outgoing

Quality Level).

(5) I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁

x

f₁₁) where V_DRis the output driver power supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at

which that pin is toggling.

(6) Excludes I_DR. See⁽⁶⁾

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V_REF= +1.0V, f_CLK= 66 MHz, f_IN= 10 MHz, t_r= t_f= 2 ns, C_L= 15 pF/pin.

Boldface limits apply for T_J= T_MINto T_MAX: all other limits T_J= 25ºC^(1)(2)(3)(4)

=

Typical

Limits

Units

Symbol

Parameter

Conditions

(5)

(Limits)

MHz (min)

MHz

1

f_CLK

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

66

2

f_CLK

15

t_CH

6.6

6

ns (min)

Clock Cycles

ns (max)

ns

t_CL

Clock Low Time

t_CONV

Conversion Latency

rising

falling

rising

falling

6.6

6.0

6.4

6.5

2

9.0

8.5

9.0

V_DR= 2.5V

V_DR= 3.3V

t_OD

Data Output Delay after Rising CLK Edge

t_AD

Aperture Delay

t_AJ

Aperture Jitter

1.2

8

ps rms

ns

t_HOLD

t_DIS

t_EN

Clock Edge to Data Transition

Data outputs into Hi-Z Mode

Data Outputs Active after Hi-Z Mode

10

ns

0.1 µF on pins 4, 14; series 1.5 Ω & 1 µF

between pins 5, 6 and between pins 12, 13

t_PD

Power Down Mode Exit Cycle

500

µs

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above V_Aor below GND by more than 100 mV. As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure

accurate conversions (see Figure 2).

(2) To guarantee accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) Timing specifications are tested at TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge.

(5) Typical figures are at T_J= 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average Outgoing

Quality Level).

Figure 2.

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Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the common d.c. voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

CROSSTALK is coupling of energy from one channel into the other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR (G.E.) is the deviation from the ideal slope of the transfer function. It can be calculated as:

G.E. = Pos. Full-Scale Error − Neg. Full-Scale Error

(1)

Gain Error can also be separated into Positive Gain Error (PGE) and Negative Gain Error (NGE), which are.

PGE = Pos. Full-Scale Error − Offset Error

(2)

(3)

NGE = Offset Error − Neg. Full-Scale Error

GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average

gain of the converters.

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is V_REF/2ⁿ,

where “n” is the ADC resolution in bits, which is 12 in the case of the ADC12DL066.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12DL066 is

guaranteed not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages [(V_IN+) – (V_IN−)] required to cause a transition

from code 2047 to 2048.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

OVER RANGE RECOVERY TIME is the time required after V_INgoes from a specified voltage out of the normal

input range to a specified voltage within the normal input range and the converter makes a conversion with its

rated accuracy.

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PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC12DL066, PSRR1 is the ratio of the change in Full-Scale Error that results from a

change in the d.c. power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding

upon the power supply is rejected at the output.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the irms values of the

input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum

that is not present at the input and may or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

where

•

F₁is the RMS power of the fundamental (output) frequency and f₂through f₁₀are the RMS power of the first 9

harmonic frequencies in the output spectrum. (4)

– Second Harmonic Distortion (2ND HARM) is the difference expressed in dB, between the RMS power in the

input frequency at the output and the power in its 2nd harmonic level at the output.

– Third Harmonic Distortion (3RD HARM) is the difference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic level at the output.

Timing Diagram

Figure 3. Output Timing

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Transfer Characteristic

Figure 4. Transfer Characteristic

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Typical Performance Characteristics

V_A= V_D= +3.3V, V_DR= +2.5V, f_CLK= 66 MHz, f_IN= 10 MHz unless otherwise stated

DNL

INL

Figure 5.

Figure 6.

DNL

vs.

V_DR

INL

vs.

V_DR

Figure 7.

Figure 8.

DNL

vs.

f_CLK

INL

vs.

f_CLK

Figure 9.

Figure 10.

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Typical Performance Characteristics (continued)

V_A= V_D= +3.3V, V_DR= +2.5V, f_CLK= 66 MHz, f_IN= 10 MHz unless otherwise stated

DNL

INL

vs.

Clock Duty Cycle

Figure 11.

Figure 12.

DNL

vs.

Temperature

INL

vs.

Temperature

Figure 13.

Figure 14.

SNR, SINAD, SFDR

vs.

V_DR

f_CLK

Figure 15.

Figure 16.

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Typical Performance Characteristics (continued)

V_A= V_D= +3.3V, V_DR= +2.5V, f_CLK= 66 MHz, f_IN= 10 MHz unless otherwise stated

SNR, SINAD, SFDR

vs.

CLOCK DUTY CYCLE

V_CM

Figure 17.

Figure 18.

SNR, SINAD, SFDR

vs.

V_REF

Temperature

Figure 19.

Figure 20.

Distortion

vs.

Distortion

vs.

V_DR

F_CLK

Figure 21.

Figure 22.

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Typical Performance Characteristics (continued)

V_A= V_D= +3.3V, V_DR= +2.5V, f_CLK= 66 MHz, f_IN= 10 MHz unless otherwise stated

Distortion

vs.

Clock Duty Cycle

V_CM

Figure 23.

Figure 24.

Distortion

vs.

Distortion

vs.

Temperature

V_REF

Figure 25.

Figure 26.

t_OD

vs.

V_DR

SPECTRAL PLOT, F_IN= 10 MHz

Figure 27.

Figure 28.

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Typical Performance Characteristics (continued)

V_A= V_D= +3.3V, V_DR= +2.5V, f_CLK= 66 MHz, f_IN= 10 MHz unless otherwise stated

SPECTRAL PLOT, F_IN= 33 MHz

IMD PERFORMANCE, F_IN1 = 9.6 MHz, F_IN2 = 10.2 MHz

Figure 29.

Figure 30.

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FUNCTIONAL DESCRIPTION

Operating on a single +3.3V supply, the ADC12DL066 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.0 Volt stable reference or using an external reference. Any external

reference is buffered on-chip to ease the task of driving that pin.

The output word rate is the same as the clock frequency, which can be between 15 Msps (typical) and 66 Msps

with fully specified performance at 66 Msps. The analog input voltage for both channels is acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 6 clock cycles. A choice of

Offset Binary or Two's Complement output format is selected with the OF pin.

A logic high on the power down (PD) pin reduces the converter power consumption to 75 mW.

APPLICATION INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12DL066:

3.0V ≤ V_A≤ 3.6V

V_D= V_A

2.4V ≤ V_DR≤ V_D

15 MHz ≤ f_CLK≤ 66 MHz

0.8V ≤ V_REF≤ 1.5V

V_REF/2 ≤ V_CM≤ 1.2V

Analog Inputs

The ADC12DL066 has two analog signal input pairs, V_INA+ and V_INA- for one converter and V_INB+ and V_INB-

for the other converter. Each pair of pins forms a differential input pair. There is one reference input pin, V_REF, for

use of an optional external reference.

The analog input circuitry contains an input boost circuit that provides improved linearity over a wide range of

analog input voltages. To prevent an on-chip over voltage condition that could impair device reliability, the input

signal should never exceed the voltage described as

Peak V_IN≤ V_A− 1.0V.

(5)

Reference Pins

The ADC12DL066 is designed to operate with a 1.0V reference, but performs well with reference voltages in the

range of 0.8V to 1.5V. Lower reference voltages will decrease the signal-to-noise ratio (SNR) of the

ADC12DL066. Increasing the reference voltage (and the input signal swing) beyond 1.5V may degrade THD and

SFDR for a full-scale input, especially at higher input frequencies.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The ADC12DL066 will perform well with reference voltages up to 1.5V for full-scale input frequencies up to 10

MHz. However, more headroom is needed as the input frequency increases, so the maximum reference voltage

(and input swing) will decrease for higher full-scale input frequencies.

The six Reference Bypass Pins (V_RPA, V_RMA, V_RNA, V_RPB, V_RMB and V_RNB) are made available for bypass

purposes. The V_RMA and V_RMB pins should each be bypassed to ground with a 0.1 µF capacitor. A series 1.5Ω

resistor (5%) and 1.0 µF capacitor (±20%) should be placed between the V_RPA and V_RNA pins and between the

V_RPB and V_RNB pins, as shown in Figure 33. This configuration is necessary to avoid reference oscillation, which

could result in reduced SFDR and/or SNR.

Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may

result in degraded noise performance. DO NOT LOAD these pins. Loading any of these pins may result in

performance degradation. The ADC12DL066 does not have a reference output pin.

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The nominal voltages for the reference bypass pins are as follows:

V_RMA = V_RMB = V_A/ 2

V_RPA = V_RPB = V_RM+ V_REF/ 2

V_RNA = V_RNB = V_RM− V_REF/ 2

The V_RMpins may be used as common mode voltage (V_CM) sources for the analog input pins as long as no d.c.

current is drawn from them. However, because the voltages at the V_RMpins are half that of the V_Asupply pin,

using these pins for common mode voltage sources will result in reduced input headroom (the difference

between the V_Asupply voltage and the peak signal voltage at either analog input) and the possibility of reduced

THD and SFDR performance. For this reason, it is recommended that V_Aalways exceed V_REFby at least 2 Volts

when using the V_RMpins as V_CMsources. For high input frequencies it may be necessary to increase this

headroom to maintain THD and SFDR performance.

User choice of an on-chip or external reference voltage is provided. The internal 1.0 Volt reference is in use

when the the INT/EXT REF pin is at a logic low, regardless of any voltage applied to the V_REFpin. When the

INT/EXT REF pin is at a logic high, the voltage at the V_REFpin is used for the voltage reference. Optimum ADC

dynamic performance is obtained when the reference voltage is in the range of 0.8V to 1.5V. When an external

reference is used, the V_REFpin should be bypassed to ground with a 0.1 µF capacitor close to the reference input

pin. There is no need to bypass the V_REFpin when the internal reference is used.

There is no direct access to the internal reference voltage. However the nominal value of the reference voltage,

whether the internal or an external reference is used, is approximately equal to V_RP− V_RN

.

Signal Inputs

The signal inputs are V_INA+ and V_INA− for one ADC and V_INB+ and V_INB− for the other ADC. The input signal,

V_IN, is defined as

V_INA = (V_INA+) – (V_INA−)

(6)

for the "A" converter and

V_INB = (V_INB+) – (V_INB−)

(7)

for the "B" converter. Figure 31 shows the expected input signal range. Note that the common mode input

voltage, V_CM, should be in the range of 0.5V to 1.5V with a nominal value of 1.0V.

The ADC12DL066 performs best with a differential input signal with each input centered around a common mode

voltage, V_CM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the

reference voltage or the output data will be clipped.

The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single

frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms,

however, angular errors will result in distortion.

Figure 31. Expected Input Signal Range

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For single frequency sine waves with angular errors of less than 45° (π/4) between the two inputs, the full scale

error in LSB can be described as approximately

E_FS= 2^(n-1)* ( 1 - cos (dev) ) = 2048 * ( 1 - cos (dev) )

where

•

dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to

each other (see Figure 32). Drive the analog inputs with a source impedance less than 100Ω. (8)

Figure 32. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

Single-Ended Operation

Single-ended performance is inferior to performance obtained when differential input signals are used. For this

reason, single-ended operation is not recommended. However, if single ended-operation is required and the

resulting performance degradation is acceptable, one of the analog inputs should be connected to the d.c. mid

point voltage of the driven input. The peak-to-peak differential input signal at the driven input pin should be twice

the reference voltage to maximize SNR and SINAD performance (Figure 31b). For example, set V_REFto 0.5V,

bias V_IN− to 1.0V and drive V_IN+ with a signal range of 0.5V to 1.5V.

Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and

Table 2 indicate the input to output relationship of the ADC12DL066. Note again that single-ended operation of

the ADC12D040 is not recommended because of the degraded performance that results. A single-ended to

differential conversion circuit is shown in Figure 34.

Table 1. Input to Output Relationship – Differential Input

+

−

V_IN

_CM− V_REF/ 2

V_IN

Binary Output

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

2’s Complement Output

1000 0000 0000

1100 0000 0000

0000 0000 0000

0100 0000 0000

0111 1111 1111

V

V_CM+ V_{REF / 2}

V_CM+ V_REF/ 4

V_CM

V

_CM− V_{REF / 4}

V_CM

V_CM+ V_REF/ 4

V_CM+ V_REF/ 2

V

_CM− V_REF/ 4

_CM− V_REF/ 2

V

Table 2. Input to Output Relationship – Single-Ended Input

+

−

V_IN

Binary Output

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

2’s Complement Output

1000 0000 0000

1100 0000 0000

0000 0000 0000

0100 0000 0000

0111 1111 1111

V

_CM− V_REF

V_CM

V

_CM− V_REF/ 2

V_CM

V_CM+ V_REF/ 2

V_CM+ V_REF

Driving the Analog Inputs

The V_IN+ and the V_IN− inputs of the ADC12DL066 consist of an analog switch followed by a switched-capacitor

amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when

the clock is low, and 7 pF when the clock is high.

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As the internal sampling switch opens and closes, current pulses occur at the analog input pins, resulting in

voltage spikes at these pins. As a driving amplifier attempts to counteract these voltage spikes, a damped

oscillation may appear at the ADC analog inputs. Do not attempt to filter out these pulses. Rather, use amplifiers

to drive the ADC12DL066 input pins that are able to react to these pulses and settle before the switch opens and

another sample is taken. The LMH6550, LMH6702, LMH6628, LMH6622 and the LMH6655 are good amplifiers

for driving the ADC12DL066.

To help isolate the pulses at the ADC input from the amplifier output, use RCs at the inputs, as can be seen in

Figure 33 and Figure 34. These components should be placed close to the ADC inputs because the input pins of

the ADC is the most sensitive part of the system and this is the last opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the

sample mode should be considered when setting the RC pole. Setting the pole in this manner will provide best

SNR performance.

To obtain best SINAD and ENOB performance, reduce the RC time constant until SNR and THD are numerically

equal to each other. To obtain best distortion and SFDR performance, eliminate the RC altogether.

+5

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D1

D2

D3

D4

D5

D6

D7

D8

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

CHOKE

3x 0.1 PF

2x 0.1 PF

+

10 PF

470

1k

POT

470

LM4040-2.5

0.1 PF

11

1

CLK

OE

7

57

ChB

V

DB11

REF

56

55

54

53

52

47

46

45

44

43

42

Output Word

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

74ACT574

330

4

5

6

V

B

RM

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

1.5:

D1

D2

D3

D4

D5

D6

D7

D8

Q1

0.1 PF

B

RP

Q2

Q3

Q4

Q5

Q6

Q7

Q8

V

B

RN

1.0 PF

1.5:

14

13

12

V

A

RM

**

0.1 PF

RP

51

11

1

V

IN_B

0.1 PF

CLK

OE

V

RN

12x100:

1

6

4

T2

1.0 PF

39 pF

0.1 PF

200

51

2

3

1

2

74ACT574

V

B-

IN

39 pF

B+

IN

T4-6T

ADC12DL066

**

51

V

IN_A

0.1 PF

1

6

4

T2

39 pF

0.1 PF

200

51

2

16

15

V

A-

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

IN

D1

D2

D3

D4

D5

D6

D7

D8

Q1

39 pF

A+

3

IN

39

38

37

36

35

34

29

28

27

26

25

24

Q2

Q3

Q4

Q5

Q6

Q7

Q8

DA11

DA10

DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

T4-6T

47

60

21

11

22

41

59

Crystal Oscillator

Input OF

CLK

OF

11

1

CLK

OE

Input INT/EXT REF

Input OEA

INT/EXT REF

OEA

ChA

Output Word

74ACT574

Input OEB

OEB

Input PD

PD

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

12x100:

D1

D2

D3

D4

D5

D6

D7

D8

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

See

Text

11

1

CLK

OE

74ACT574

Figure 33. Application Circuit using Transformer or Differential Op-Amp Drive Circuit

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511, 1%

51

To ADC

V

IN

-

255, 1%

50W

SIGNAL

INPUT

47 pF

+

-

Amplifier:

LMH6550

49.9,

1%

280, 1%

330

47 pF

To ADC

0.1 mF

V

+

IN

511, 1%

51

ADC V_REF

Figure 34. Differential Drive Circuit using a fully differential amplifier.

For undersampling applications, the RC pole should be set at about 1.5 to 2 times the maximum input frequency

to maintain a linear delay response.

Note that the ADC12DL066 is not designed to operate with single-ended inputs. However, doing so is possible if

the degraded performance is acceptable. See Single-Ended Operation.

Figure 33 shows a narrow band application with a transformer used to convert single-ended input signals to

differential. Figure 34 shows the use of a fully differential amplifier for single-ended to differential conversion. The

LMH6550 is recommended for single-ended to differential conversion when d.c. or very low frequencies must be

accommodated. Of course, the LMH6550 may also be used to amplify differential signals.

Input Common Mode Voltage

The input common mode voltage, V_CM, should be of a value such that the peak excursions of the analog signal

does not go more negative than ground or more positive than 1.0 Volt below the V_Asupply voltage. The nominal

V_CMshould generally be about V_REF/2, but V_RBA and V_RBB can be used as a V_CMsource as long as no d.c.

current is drawn from either of these pins.

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, OEA, OEB, OF, INT/EXT REF and PD.

The CLK Pin

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 15 MHz to 75 MHz with rise and fall times of 2 ns or less. The trace carrying the clock

signal should be as short as possible and should not cross any other signal line, analog or digital, not even at

90°.

If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point

where the accuracy of the output data will degrade. This is what limits the lowest sample.

The ADC clock line should be considered to be a transmission line and be series terminated at the source end to

match the source impedance with the characteristic impedance of the clock line. It generally is not necessary to

terminate the far (ADC) end of the clock line, but if a single clock source is driving more than one device (a

condition that is generally not recommended), far end termination may be needed. The far end termination

should be near but beyond the ADC clock pin as seen from the clock source.

It is highly desirable that the the source driving the ADC CLK pin only drive that pin. However, if that source is

used to drive other things, each driven pin should be a.c. terminated with a series RC to ground, as shown in

Figure 33, such that the resistor value is equal to the characteristic impedance of the clock line and the capacitor

value is

where

•

t_PDis the signal propagation time in ns/unit length, "L" is the line length and Z_Ois the characteristic impedance

of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it as seen

from the clock source. Typical t_PDis about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and

t_PDshould be the same (inches or centimeters).

(9)

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The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise

duty cycle is difficult, the ADC12DL066 is designed to maintain performance over a range of duty cycles. While it

is specified and performance is guaranteed with a 50% clock duty cycle, performance is typically maintained over

a clock duty cycle range of 43% to 57% at 66 Msps.

Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application

Note AN-905 for information on setting characteristic impedance.

The OEA, OEB Pins

The OEA and OEB pins, when high, put the output pins of their respective converters into a high impedance

state. When either of these pins is low, the corresponding outputs are in the active state. The ADC12DL066 will

continue to convert whether these pins are high or low, but the output can not be read while the pin is high.

Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-

STATE outputs of the ADC12DL066 to drive a bus. Rather, each output pin should be located close to and drive

a single digital input pin. To further reduce ADC noise, a 100 Ω resistor in series with each ADC digital output

pin, located close to their respective pins, should be added to the circuit.

The PD Pin

The PD pin, when high, holds the ADC12DL066 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 75 mW with a 66 MHz clock and 40mW if the clock is

stopped when PD is high. The output data pins are undefined and the data in the pipeline is corrupted while in

the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on pins 4, 5, 6, 12, 13 and

14 and is about 500 µs with the recommended components on the V_RP, V_RMand V_RNreference bypass pins.

These capacitors loose their charge in the Power Down mode and must be recharged by on-chip circuitry before

conversions can be accurate. Smaller capacitor values allow slightly faster recovery from the power down mode,

but can result in a reduction in SNR, SINAD and ENOB performance.

The OF Pin

The output data format is offset binary when the OF pin is at a logic low or 2’s complement when the OF pin is at

a logic high. While the sense of this pin may be changed "on the fly," doing this is not recommended as the

output data could be erroneous for a few clock cycles after this change is made.

The INT/EXT REF Pin

The INT/EXT REF pin determines whether the internal reference or an external reference voltage is used. With

this pin at a logic low, the internal 1.0V reference is in use. With this pin at a logic high an external reference

must be applied to the V_REFpin, which should then be bypassed to ground. There is no need to bypass the V_REF

pin when the internal reference is used. There is no access to the internal reference voltage, but its value is

approximately equal to V_RP− V_RN

.

DATA OUTPUT PINS

The ADC12DL066 has 24 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while

the OE and PD pins are low. While the t_ODtime provides information about output timing, t_ODwill change with a

change of clock frequency. At the rated 66 MHz clock rate, the data transition can be coincident with the rise of

the clock and about 7 ns before the fall of the clock (depending upon V_DR), so the falling edge of the clock should

be used to capture the output data. At lower clock frequencies the data transition occurs a little after the rising

edge of the clock, but the fall of the clock still appears to be the best edge for data capture. However, circuit

board layout will affect relative delays of the clock and data, so it is important to consider these relative delays

when designing the digital interface.

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large charging

current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic

performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will

reduce this problem. Additionally, bus capacitance beyond the specified 15 pF/pin will cause t_ODto increase,

making it difficult to properly latch the ADC output data. The result could be an apparent reduction in dynamic

performance.

24

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To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series resistors of about 100Ω at the digital

outputs, close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the

output currents, which could otherwise result in performance degradation. See Figure 33.

Note that, although the ADC12DL066 has Tri-State outputs, these outputs should not be used to drive a bus and

the charging and discharging of large capacitances can degrade SNR performance. Each output pin should drive

only one pin of a receiving device and the interconnecting lines should be as short as practical.

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series

inductance.

As is the case with all high-speed converters, the ADC12DL066 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mV_P-P

.

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

The V_DRpin provides power for the output drivers and may be operated from a supply in the range of 2.4V to V_D

(nominal 5V). This can simplify interfacing to lower voltage devices and systems. Note, however, that t_OD

increases with reduced V_DR. DO NOT operate the V_DRpin at a voltage higher than V_D.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12DL066 between these areas, is required to

achieve specified performance.

The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the

ADC12DL066's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

The effects of the noise generated from the ADC output switching can be minimized through the use of 100Ω

resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.

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COMMON

GROUND

PLANE

OSC

Clock line should be short

and cross no other lines.

LATCH

All Digital components

mounted over Digital area

of Ground Plane

All Analog Components mounted

over Analog are of Ground Plane

6 x 100W

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

Xfmr/Amplifier

1

V

2

V

3

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

6 x 100W

V

B-

IN

D

DB5

DB4

B+

AGND

4

5

V

B

DB3

RM

LATCH

V

B

DB2

RP

6

V

DB1

Driving source

located close to

converter

RN

7

V

DB0

REF

Single Ground entry for all

Reference Components

8

AGND

OEB

DR GND

DA11

DA10

DA9

9

ADC12DL066

V

A

10

11

12

13

14

15

16

AGND

INT/EXT REF

V

A

RN

V

DA8

RP

V

DA7

RM

DA6

A+

A-

IN

V

D

Analog power line should be routed

away from Digital power trace.

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Digital power line should be routed

away from analog power trace.

Ground entry points

close to ground pins.

Figure 35. Example of a Suitable Layout

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies

beside each other.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

Figure 35 gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference

components, etc.) should be placed in the analog area of the board. All digital circuitry and I/O lines should be

placed in the digital area of the board. The ADC12DL066 should be between these two areas. Furthermore, all

components in the reference circuitry and the input signal chain that are connected to ground should be

connected together with short traces and enter the ground plane at a single, quiet point. All ground connections

should have a low inductance path to ground.

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DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate

the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 36. The gates used in

the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be

prevented.

Figure 36. Isolating the ADC Clock from other Circuitry with a Clock Tree

Best performance will be obtained with a differential input drive, compared with a single-ended drive, as

discussed in Single-Ended Operation and Driving the Analog Inputs.

As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible

and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can

lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°

crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above

the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not

uncommon for high speed digital components (e.g., 74F devices) to exhibit overshoot or undershoot that goes

above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending digital

input, close to the signal source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12DL066 with a device that is powered from supplies outside

the range of the ADC12DL066 supply. Such practice may lead to conversion inaccuracies and even to device

damage.

Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must

charge for each conversion, the more instantaneous digital current flows through V_DRand DR GND. These large

charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate

bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.

Additionally, bus capacitance beyond the specified 15 pF/pin will cause t_ODto increase, making it difficult to

properly latch the ADC output data. The result could, again, be an apparent reduction in dynamic performance.

The digital data outputs should be buffered (with 74AC541, for example). Dynamic performance can also be

improved by adding series resistors at each digital output, close to the ADC12DL066, which reduces the energy

coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors

is 100Ω.

Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen

at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is

more difficult to drive than is a fixed capacitance.

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If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in

Figure 32 and Figure 34) will improve performance. The LMH6702 and the LMH6628 have been successfully

used to drive the analog inputs of the ADC12DL066.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, V_REF

should be in the range of

0.8V ≤ V_REF≤ 1.5V

(10)

Operating outside of these limits could lead to performance degradation.

Inadequate network on Reference Bypass pins (V_RPA, V_RNA, V_RMA, V_RPB, V_RNB and V_RMB). As mentioned in

Reference Pins, these pins should be bypassed with 0.1 µF capacitors to ground at V_RMA and V_RMB and with a

series RC of 1.5 Ω and 1.0 µF between pins V_RPA and V_RNA and between V_RPB and V_RNB for best performance.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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REVISION HISTORY

Changes from Revision F (February 2013) to Revision G

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 28

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MECHANICAL DATA

MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996

PAG (S-PQFP-G64)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

48

M

0,08

33

49

32

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

0,25

12,20

SQ

0,05 MIN

11,80

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4040282/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	ADC12DL066CIVS/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	双通道、12 位、66MSPS、450MHz 输入带宽模数转换器 (ADC) \| PAG \| 64 \| -40 to 85 转换器模数转换器
文件：	总33页 (文件大小：912K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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