ADC12DL3200ALJ_技术文档

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

ADC12DL3200 具有LVDS 接口的6.4GSPS 单通道或3.2GSPS 双通道

12 位模数转换器(ADC)

1 特性

3 说明

• ADC 内核：

ADC12DL3200 是一款射频采样千兆采样模数转换器

(ADC)，可对从直流到 10GHz 以上的输入频率进行直

接采样。ADC12DL3200 在双通道模式下的最大采样速

率为 3200MSPS，在单通道模式下的最大采样速率为

6400MSPS。该器件可通过编程方式针对通道数（双

通道模式）和奈奎斯特带宽（单通道模式）进行权衡，

方便用户开发灵活的硬件，从而满足高通道数或宽瞬时

信号带宽应用的需求。它具有8.0GHz 的全功率输入带

宽 (-3dB) 和实用的频率范围，可对频率捷变系统的

L、S、C 和X 频带进行直接射频采样。

– 12 位分辨率

– 单通道模式下采样速率高达6.4GSPS

– 双通道模式下采样速率高达3.2GSPS

• 内部抖动技术，可产生低幅高位谐波

• 低延迟LVDS 接口：

– 总延迟：< 10ns

– 多达48 个速率为1.6Gbps 的数据对

– 四个DDR 数据时钟

– 选通信号会简化同步

• 本底噪声（无输入，V_FS= 1.0V_PP-DIFF）：

ADC12DL3200 针对延迟敏感型应用采用低延迟的低电

压差分信号 (LVDS) 接口，或在需要 LVDS 的简易性时

使用该接口。该接口使用多达 48 个数据对、四个双倍

数据速率 (DDR) 时钟和四个选通信号（安排在四条 12

位数据总线中）。该接口支持高达 1.6Gbps 的信号速

率。选通信号可简化总线间和多个器件间的同步工作。

选通信号是在内部产生的，并且 SYSREF 输入可在确

定的时间将其复位。无噪声孔径延迟 (T_AD) 调节和

SYSREF 窗口化等创新的同步特性进一步简化了多器

件同步。

– 双通道模式：-151.1dBFS/Hz

– 单通道模式：-154.3dBFS/Hz

• V_CMI为0V 的缓冲模拟输入：

– 模拟输入带宽(–3dB)：8.0 GHz

– 可用输入频率范围：> 10 GHz

– 满量程输入电压（V_FS，默认值）：0.8 V_PP

• 无噪声孔径延迟(T_AD) 调节：

– 精确采样控制：19 fs 步长

– 简化同步和交错

– 温度和电压不变延迟

• 简便易用的同步特性：

封装信息

封装⁽¹⁾

封装尺寸⁽²⁾

器件型号

– 自动SYSREF 计时校准

– 样片标记时间戳

ADC12DL3200

FCBGA (256)

17 mm x 17 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• 功耗：3.15W

(2) 封装尺寸（长x 宽）为标称值，并包括引脚（如适用）。

2 应用

3

0

• 示波器和宽带数字转换器

• 电子战（信号情报、电子情报）

• 飞行时间和激光雷达测距

• 微波回程

• 汽车雷达测试器

• 光谱测量

-3

-6

-9

Dual-Channel Mode

Single-Channel Mode

-12

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D_BW

ADC12DL3200 频率响应

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSDR3

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

6.10 Switching Characteristics........................................26

6.11 Typical Characteristics............................................ 38

7 Detailed Description......................................................53

7.1 Overview...................................................................53

7.2 Functional Block Diagram.........................................53

7.3 Feature Description...................................................54

7.4 Device Functional Modes..........................................65

7.5 Programming............................................................ 74

7.6 Register Maps...........................................................76

8 Device and Documentation Support..........................150

8.1 Device Support....................................................... 150

8.2 接收文档更新通知................................................... 150

8.3 支持资源..................................................................150

8.4 商标.........................................................................150

8.5 静电放电警告.......................................................... 150

8.6 术语表..................................................................... 150

9 Mechanical, Packaging, and Orderable Information150

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications................................................................ 12

6.1 Absolute Maximum Ratings...................................... 12

6.2 ESD Ratings............................................................. 12

6.3 Recommended Operating Conditions.......................13

6.4 Thermal Information..................................................14

6.5 Electrical Characteristics: DC Specifications............ 14

6.6 Electrical Characteristics: Power Consumption........ 17

6.7 Electrical Characteristics: AC Specifications

(Dual-Channel Mode)..................................................18

6.8 Electrical Characteristics: AC Specifications

(Single-Channel Mode)............................................... 22

6.9 Timing Requirements................................................26

4 Revision History

Changes from June 15, 2020 to May 22, 2023 (from Revision B (June 2020) to Revision C (May

2023))

Page

• 更改了封装信息表，添加了注释 2.....................................................................................................................1

• Changed SYNC_RECV_EN to TMSTP_RECV_EN, the correct name for register 0x03B bit 0.......................76

Changes from Revision A (September 2018) to Revision B (June 2020)

Page

• Corrected mislabeled LVDS buses in 图6-7. LVDS buses B and C were swapped.........................................26

Changes from Revision * (May 2018) to Revision A (September 2018)

Page

• 已投入量产..........................................................................................................................................................1

English Data Sheet: SLVSDR3

2

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ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

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5 Pin Configuration and Functions

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

F

AGND

INA+

INAœ

AGND

ORA1

DA0+

DA0œ

DA6+

DA6œ

DC0+

DC0œ

DGND

CALSTAT CALTRIG AGND

AGND

VA11

VA19

VA11

AGND

INB+

AGND

VA11

VA19

VA11

AGND

INBœ

AGND

VA11

VA19

VA11

AGND

DGND

AGND

ORA0

ORB1

ORB0

VD11

DA1+

DA2+

DA3+

DA4+

DA5+

DA1œ

DA2œ

DA3œ

DA4œ

DA5œ

DA7+

DA8+

DA7œ

DA8œ

DC1+

DC2+

DC3+

DC4+

DC5+

DC6+

VLVDS

DD6+

DD5+

DD4+

DD3+

DD2+

DD1+

DD0+

DC1œ

DC2œ

DC3œ

DC4œ

DC5œ

DC6œ

DC7+

DC8+

DC7œ

DC8œ

AGND

BG

AGND

TMSTP+

DA9+

DA9œ

DC9+

DC9œ

TMSTPœ SYNCSE AGND

DA10+

DA11+

DA10œ

DA11œ

VLVDS

DB11œ

DB10œ

DB9œ

DC10+

DC11+

DC10œ

DC11œ

AGND

CLK+

CLKœ

AGND

VA11

VA19

VA11

G

H

J

DACLK+ DACLKœ VLVDS

DCCLK+ DCCLKœ

DGND DASTR+ DASTRœ VLVDS

DGND DBSTR+ DBSTRœ VLVDS

DGND DCSTR+ DCSTRœ

DGND DDSTR+ DDSTRœ

K

L

AGND

VD11

SDO

SDI

DBCLK+ DBCLKœ VLVDS

DD6œ

DD5œ

DD4œ

DD3œ

DD2œ

DD1œ

DD0œ

DDCLK+ DDCLKœ

DB5+

DB4+

DB3+

DB2+

DB1+

DB0+

DB5œ

DB4œ

DB3œ

DB2œ

DB1œ

DB0œ

DB11+

DB10+

DB9+

DB8+

DB7+

DB6+

DD11+

DD10+

DD9+

DD8+

DD7+

DGND

DD11œ

DD10œ

DD9œ

DD8œ

DD7œ

M

N

P

R

T

SYSREF+ TDIODE+ AGND

SYSREFœ TDIODEœ AGND

AGND

PD

AGND

DB8œ

SCS

DB7œ

AGND

SCLK

DB6œ

DGND

Not to scale

图5-1. ACF Package, 256-Ball Flip Chip BGA

(Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NO.

A1

NAME

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

A2

A3

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Product Folder Links: ADC12DL3200

English Data Sheet: SLVSDR3

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Channel A analog input positive connection. The differential full-scale input range is determined by the

FS_RANGE_A register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to

AGND through a 50-Ωtermination resistor. The input common-mode voltage must typically be set to 0 V

(GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin

can be left disconnected if not used.

A4

INA+

I

Channel A analog input negative connection. See INA+ (pin A4) for detailed description. This input is

terminated to ground through a 50-Ωtermination resistor. This pin can be left disconnected if not used.

A5

INA–

A6

A7

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input

exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse

duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this

pin disconnected if not used.

A8

ORA1

O

A9

DA0+

DA0–

DA6+

O

LVDS output for bit 0 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

A10

A11

A12

A13

A14

A15

A16

DA6–

DC0+

DC0–

DGND

—

Foreground calibration status output or device alarm output. Functionality is programmed through

CAL_STATUS_SEL. This pin can be left disconnected if not used.

B1

B2

CALSTAT

CALTRIG

O

I

Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in

CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND

if not used.

B3

B4

B5

B6

B7

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input

exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse

duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this

pin disconnected if not used.

B8

ORA0

O

B9

DA1+

DA1–

DA7+

O

LVDS output for bit 1 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

B10

B11

B12

B13

B14

B15

B16

C1

DA7–

DC1+

DC1–

DC7+

DC7–

AGND

—

C2

C3

C4

C5

4

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Product Folder Links: ADC12DL3200

English Data Sheet: SLVSDR3

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

C6

NAME

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

C7

Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input

exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse

duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this

pin disconnected if not used.

C8

ORB1

O

C9

DA2+

DA2–

DA8+

O

LVDS output for bit 2 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

C10

C11

C12

C13

C14

C15

C16

DA8–

DC2+

DC2–

DC8+

DC8–

Timestamp input positive connection or differential LVDS SYNC positive connection. This input is used

as the timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set 1. This differential

input is used as the SYNC signal input when SYNC_SEL is set to 1. This input can be used as both a

timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the

timestamp mechanism. TMSTP± uses active low signaling when used as the LVDS SYNC signal. For

additional usage information, see the Timestamp section.

TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has

an internal untrimmed 100-Ωdifferential termination and can be AC-coupled when

D1

TMSTP+

I

TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ωto ground on each input pin

(TMSTP+ and TMSTP–) and can be DC-coupled when TMSTP_LVPECL_EN is set to 1. This pin is not

self-biased and therefore must be externally biased for both AC-coupled and DC-coupled configurations.

The common-mode voltage must be within the range provided in the Recommended Operating

Conditions table when both AC-coupled and DC-coupled. This pin can be left disconnected and disabled

(TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal and timestamp is not required.

Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited

capacitive loads, as specified in the Recommended Operating Conditions table. See the Analog

Reference Voltage section for more details. This pin can be left disconnected if not used.

D2

BG

O

D3

D4

D5

D6

D7

AGND

DGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input

exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse

duration is set by OVR_N. See the ADC Overrange Detection section for more information. Leave this

pin disconnected if not used.

D8

ORB0

O

D9

DA3+

DA3–

DA9+

O

LVDS output for bit 3 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

D10

D11

D12

D13

D14

D15

D16

DA9–

DC3+

DC3–

DC9+

DC9–

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English Data Sheet: SLVSDR3

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

E1

NAME

Timestamp input negative connection or differential LVDS SYNC negative connection. This pin can be

left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for the LVDS SYNC signal

and timestamp is not required.

I

TMSTP–

LVDS interface SYNC signal, single-ended active low input used to control sending strobe signals for

synchronization or digital interface test patterns. The Digital Interface Test Patterns section describes

using the SYNC signal in more detail. The choice of single-ended or differential SYNC (using the

TMSTP+ and TMSTP–pins) is selected by programming SYNC_SEL. Tie this pin to ground if

differential SYNC (TMSTP±) is used as the SYNC signal.

E2

SYNCSE

E3

E4

E5

E6

E7

E8

E9

E10

E11

AGND

VA11

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V analog supply

—

I

VA11

1.1-V analog supply

VA11

1.1-V analog supply

DGND

VD11

DA4+

DA4–

DA10+

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

O

LVDS output for bit 4 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 4 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

O

LVDS output for bit 10 of LVDS bus A. Negative connection. This pin can be left disconnected if not

used.

E12

O

DA10–

E13

E14

E15

DC4+

DC4–

DC10+

O

LVDS output for bit 4 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 4 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus C. Negative connection. This pin can be left disconnected if not

used.

E16

O

DC10–

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

AGND

VA11

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V analog supply

—

I

VA11

1.1-V analog supply

VA11

1.1-V analog supply

VA11

1.1-V analog supply

DGND

VD11

DA5+

DA5–

DA11+

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

O

LVDS output for bit 5 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 5 of LVDS bus A. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 11 of LVDS bus A. Positive connection. This pin can be left disconnected if not used.

O

LVDS output for bit 11 of LVDS bus A. Negative connection. This pin can be left disconnected if not

used.

F12

O

DA11–

F13

F14

F15

DC5+

DC5–

DC11+

O

LVDS output for bit 5 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 5 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 11 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 11 of LVDS bus C. Negative connection. This pin can be left disconnected if not

used.

F16

O

DC11–

G1

G2

G3

G4

G5

AGND

VA19

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

I

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.9-V analog supply

I

6

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English Data Sheet: SLVSDR3

ADC12DL3200

ZHCSI83C –MAY 2018 –REVISED MAY 2023

www.ti.com.cn

表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

G6

NAME

VA19

DGND

VD11

I

1.9-V analog supply

G7

G8

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

LVDS output for data clock of LVDS bus A. Positive connection. This pin can be left disconnected if not

used.

G9

DACLK+

O

LVDS output for data clock of LVDS bus A. Negative connection. This pin can be left disconnected if not

used.

G10

DACLK–

G11

G12

G13

G14

VLVDS

DC6+

I

1.1-V to 1.9-V LVDS digital interface supply

I

1.1-V to 1.9-V LVDS digital interface supply

O

LVDS output for bit 6 of LVDS bus C. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus C. Negative connection. This pin can be left disconnected if not used.

DC6–

LVDS output for data clock of LVDS bus C. Positive connection. This pin can be left disconnected if not

used.

G15

G16

DCCLK+

O

LVDS output for data clock of LVDS bus C. Negative connection. This pin can be left disconnected if not

used.

DCCLK–

Device (sampling) clock positive input. TI strongly recommends that the clock signal be AC-coupled to

this input for best performance. In single-channel mode, the analog input signal is sampled on both

rising and falling edges. In-dual channel mode, the analog signal is sampled on the rising edge. This

differential input has an internal untrimmed 100-Ωdifferential termination and is self-biased to the

optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0.

H1

CLK+

I

H2

H3

H4

H5

H6

H7

H8

AGND

VA19

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

I

1.9-V analog supply

VA19

1.9-V analog supply

VA19

1.9-V analog supply

VA19

1.9-V analog supply

DGND

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

LVDS output for data strobe of LVDS bus A. Positive connection. This pin can be left disconnected if not

used.

H9

DASTR+

O

LVDS output for data strobe of LVDS bus A. Negative connection. This pin can be left disconnected if

not used.

H10

DASTR–

H11

H12

H13

H14

VLVDS

DGND

I

1.1-V to 1.9-V LVDS digital interface supply

I

1.1-V to 1.9-V LVDS digital interface supply

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

LVDS output for data strobe of LVDS bus C. Positive connection. This pin can be left disconnected if not

used.

H15

H16

J1

DCSTR+

DCSTR–

CLK–

O

I

LVDS output for data strobe of LVDS bus C. Negative connection. This pin can be left disconnected if

not used.

Device (sampling) clock negative input. TI strongly recommends that the clock signal be AC-coupled to

this input for best performance.

J2

J3

J4

J5

J6

J7

J8

AGND

VA19

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

I

1.9-V analog supply

VA19

1.9-V analog supply

VA19

1.9-V analog supply

VA19

1.9-V analog supply

DGND

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

J9

NAME

LVDS output for data strobe of LVDS bus B. Positive connection. This pin can be left disconnected if not

used.

DBSTR+

O

LVDS output for data strobe of LVDS bus B. Negative connection. This pin can be left disconnected if

not used.

J10

DBSTR–

J11

J12

J13

J14

VLVDS

DGND

I

1.1-V to 1.9-V LVDS digital interface supply

I

1.1-V to 1.9-V LVDS digital interface supply

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

LVDS output for data strobe of LVDS bus D. Positive connection. This pin can be left disconnected if not

used.

J15

J16

DDSTR+

O

LVDS output for data strobe of LVDS bus D. Negative connection. This pin can be left disconnected if

not used.

DDSTR–

K1

K2

K3

K4

K5

K6

K7

K8

AGND

VA19

DGND

VD11

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

I

1.9-V analog supply

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

LVDS output for data clock of LVDS bus B. Positive connection. This pin can be left disconnected if not

used.

K9

DBCLK+

O

LVDS output for data clock of LVDS bus B. Negative connection. This pin can be left disconnected if not

used.

K10

DBCLK–

K11

K12

K13

K14

VLVDS

DD6+

I

1.1-V to 1.9-V LVDS digital interface supply

I

1.1-V to 1.9-V LVDS digital interface supply

O

LVDS output for bit 6 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

DD6–

LVDS output for data clock of LVDS bus D. Positive connection. This pin can be left disconnected if not

used.

K15

K16

DDCLK+

O

LVDS output for data clock of LVDS bus D. Negative connection. This pin can be left disconnected if not

used.

DDCLK–

L1

L2

L3

L4

L5

L6

L7

L8

L9

L10

L11

AGND

VA11

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V analog supply

—

I

VA11

1.1-V analog supply

VA11

1.1-V analog supply

VA11

1.1-V analog supply

DGND

VD11

DB5+

DB5–

DB11+

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

O

LVDS output for bit 5 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 5 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 11 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

O

LVDS output for bit 11 of LVDS bus B. Negative connection. This pin can be left disconnected if not

used.

L12

O

DB11–

L13

L14

DD5+

O

LVDS output for bit 5 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 5 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

DD5–

8

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

L15

NAME

DD11+

O

LVDS output for bit 11 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 11 of LVDS bus D. Negative connection. This pin can be left disconnected if not

used.

L16

M1

DD11–

SYSREF input positive connection. The SYSREF input is used to achieve synchronization between

multiple ADC12DL3200 devices and deterministic latency across the LVDS data interface. This

differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ωdifferential termination and

can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when

SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ωto ground on each input pin

(SYSREF+ and SYSREF–) and can be DC-coupled when SYSERF_LVPECL_EN is set to 1. This input

is not self-biased when SYSERF_LVPECL is set to 1 and must be biased externally to the input

common-mode voltage range provided in the Recommended Operating Conditions table.

SYSREF+

TDIODE+

I

Temperature diode positive (anode) connection. An external temperature sensor can be connected to

TDIODE+ and TDIODE–to monitor the junction temperature of the device. This pin can be left

disconnected if not used.

M2

I

M3

M4

M5

M6

M7

M8

M9

M10

M11

AGND

VA11

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V analog supply

—

I

VA11

1.1-V analog supply

VA11

1.1-V analog supply

DGND

VD11

DB4+

DB4–

DB10+

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

1.1-V digital supply

—

I

O

LVDS output for bit 4 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 4 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

O

LVDS output for bit 10 of LVDS bus B. Negative connection. This pin can be left disconnected if not

used.

M12

O

DB10–

M13

M14

M15

DD4+

DD4–

DD10+

O

LVDS output for bit 4 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 4 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 10 of LVDS bus D. Negative connection. This pin can be left disconnected if not

used.

M16

O

DD10–

N1

N2

N3

N4

N5

N6

N7

I

SYSREF input negative connection. See SYSREF+ (pin M1) for detailed description.

SYSREF–

TDIODE–

AGND

Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

AGND

DGND

Serial programming interface (SPI) data output. The Using the Serial Interface section describes the

serial interface in more detail. This pin is high impedance during normal device operation. This pin

outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if

not used.

N8

SDO

O

N9

DB3+

DB3–

DB9+

DB9–

DD3+

DD3–

DD9+

O

LVDS output for bit 3 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 3 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 9 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

N10

N11

N12

N13

N14

N15

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

N16

NAME

DD9–

AGND

O

LVDS output for bit 9 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

P1

P2

P3

P4

P5

P6

P7

—

Serial programming interface (SPI) data input. The Using the Serial Interface section describes the serial

interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.

P8

SDI

I

P9

DB2+

DB2–

DB8+

O

LVDS output for bit 2 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 2 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 8 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

P10

P11

P12

P13

P14

P15

P16

DB8–

DD2+

DD2–

DD8+

DD8–

This pin disables all analog circuits and LVDS outputs when set high to save power or for temperature

diode calibration. Tie this pin to ground during normal operation.

R1

PD

I

R2

R3

R4

R5

R6

R7

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Serial programming interface (SPI) chip-select active low input. The Using the Serial Interface section

describes the serial interface in more detail. Supports 1.1-V and 1.8-V CMOS levels. This pin has an 82-

kΩpullup resistor to VD11.

R8

SCS

I

R9

DB1+

DB1–

DB7+

O

LVDS output for bit 1 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 1 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 7 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

R10

R11

R12

R13

R14

R15

R16

T1

DB7–

DD1+

DD1–

DD7+

DD7–

AGND

—

T2

T3

Channel B analog input positive connection. The differential full-scale input range is determined by the

FS_RANGE_B register; see the Full-Scale Voltage (VFS) Adjustment section. This input is terminated to

AGND through a 50-Ωtermination resistor. The input common-mode voltage must typically be set to 0 V

(GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin

can be left disconnected if not used.

T4

INB+

I

10

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表5-1. Pin Functions (continued)

TYPE

DESCRIPTION

NO.

NAME

Channel B analog input negative connection. See INB+ (pin T4) for detailed description. This input is

terminated to ground through a 50-Ωtermination resistor. This pin can be left disconnected if not used.

T5

I

INB–

T6

T7

AGND

Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

—

Serial programming interface (SPI) clock. This pin functions as the serial-interface clock input that clocks

the serial programming data in and out. The Using the Serial Interface section describes the serial

interface in more detail. Supports 1.1-V and 1.8-V CMOS levels.

T8

SCLK

I

T9

DB0+

DB0–

DB6+

O

LVDS output for bit 0 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus B. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 6 of LVDS bus B. Negative connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus D. Positive connection. This pin can be left disconnected if not used.

LVDS output for bit 0 of LVDS bus D. Negative connection. This pin can be left disconnected if not used.

Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.

T10

T11

T12

T13

T14

T15

T16

DB6–

DD0+

DD0–

DGND

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–1.32

–0.1

MAX

2.35

1.32

2.35

1.32

0.1

UNIT

V

VA19⁽²⁾

VA11⁽²⁾

Supply voltage range

VD11⁽³⁾

VLVDS⁽³⁾

Voltage between VD11 and VA11

Voltage between AGND and DGND

V

DACLK+, DACLK–, DASTR+, DASTR–,

DA[11:0]+, DA[11:0]–, DBCLK+, DBCLK–,

DBSTR+, DBSTR–, DB[11:0]+, DB[11:0]–,

DCCLK+, DCCLK–, DCSTR+, DCSTR–,

DC[11:0]+, DC[11:0]–, DDCLK+, DDCLK–,

DDSTR+, DDSTR–, DD[11:0]+, DD[11:0]–⁽³⁾

VLVDS +

0.5⁽⁷⁾

–0.5

VA11 +

0.5⁽⁵⁾

CLK+, CLK–, SYSREF+, SYSREF–⁽²⁾

TMSTP+, TMSTP–⁽³⁾

–0.5

Pin voltage range

V

VD11 +

0.5⁽⁶⁾

VA19 +

0.5⁽⁴⁾

BG, TDIODE+, TDIODE–⁽²⁾

–0.5

–1

INA+, INA–, INB+, INB–⁽²⁾

1

CALSTAT, CALTRIG, ORA0, ORA1, ORB0,

VA19 +

0.5⁽⁴⁾

ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE

–0.5

(2)

25

50

mA

Peak input current (any input except INA+, INA–, INB+, INB–)

Peak input current (INA+, INA–, INB+, INB–)

–25

–50

Peak RF input power (INA+, INA–, INB+,

INB–)

Single-ended with Z_S-SE= 50 Ωor differential

with Z_S-DIFF= 100 Ω

16.4

100

dBm

mA

Peak total input current (sum of absolute value of all currents forced in or out, not including

power supply current)

Operating junction temperature, T_j

Storage temperature, T_stg

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Measured to AGND.

(3) Measured to DGND.

(4) Maximum voltage not to exceed VA19 absolute maximum rating.

(5) Maximum voltage not to exceed VA11 absolute maximum rating.

(6) Maximum voltage not to exceed VD11 absolute maximum rating.

(7) Maximum voltage not to exceed VLVDS absolute maximum rating.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

NOM

1.9

1.1

1.9

0

MAX

2.0

UNIT

VA19, analog 1.9-V supply⁽²⁾

VA11, analog 1.1-V supply⁽²⁾

1.05

-50

1.15

2.0

V_DD

Supply voltage range

V

VD11, digital 1.1-V supply⁽³⁾

VLVDS, LVDS interface supply⁽³⁾

INA+, INA–, INB+, INB–⁽²⁾

110

mV

V

CLK+, CLK–, SYSREF+, SYSREF–⁽²⁾

V_CMI

Input common-mode voltage

0

0.3

1.0

0.55

2.0

(4)

TMSTP+, TMSTP–^{(3) (5)}

CLK+ to CLK–, SYSREF+ to

SYSREF–, TMSTP+ to TMSTP–

0.4

Input voltage, peak-to-peak

differential

V_ID

V_PP-DIFF

1.0⁽⁶⁾

INA+ to INA–, INB+ to INB–

CALTRIG, PD, SCLK, SCS, SDI,

SYNCSE ⁽²⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

0.7

V

CALTRIG, PD, SCLK, SCS, SDI,

SYNCSE ⁽²⁾

0.45

I_{C_TD}

C_L

Temperature diode input current

BG maximum load capacitance

BG maximum output current

Input clock duty cycle

100

µA

pF

µA

TDIODE+ to TDIODE–

100

I_O

DC

T_A

30%

-40

50%

70%

85

Operating free-air temperature

Operating junction temperature

°C

T_j

105⁽¹⁾

(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

(2) Measured to AGND.

(3) Measured to DGND.

(4) It is strongly recommended that CLK± be AC coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self bias to the optimal

input common mode voltage for best performance. TI recommends AC coupling for SYSREF± unless DC coupling is required, in which

case LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).

(5) TMSTP± does not have internal biasing which requires TMSTP± to be biased externally whether AC coupled with

TMSTP_LVPECL_EN = 0 or DC coupled with TMSTP_LVPECL_EN = 1.

(6) ADC output code will saturate when VID for INA+/–or INB+/–exceeds the programmed full-scale voltage (V_FS) set by

FS_RANGE_A for INA± or FS_RANGE_B for INB±.

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6.4 Thermal Information

ADC12DL3200

THERMAL METRIC⁽¹⁾

ACF (FCBGA)

UNIT

256 PINS

16.5

0.94

5.4

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

ψ_JT

5.1

ψ_JB

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics: DC Specifications

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

DC ACCURACY

Resolution

TEST CONDITIONS

MIN

TYP

MAX UNIT

Resolution with no missing codes

12

0.3

Bits

Maximum positive excursion from ideal step size

Maximum negative excursion from ideal step size

DNL

Differential nonlinearity

LSB

–0.3

Maximum positive excursion from ideal transfer

function

1.6

INL

Integral nonlinearity

LSB

Maximum negative excursion from ideal transfer

function

–2.0

ANALOG INPUTS (INA±, INB±)

CAL_OS = 0

CAL_OS = 1

±2.0

±0.3

mV

V_OFF

Offset Error

Available offset correction range (see CAL_OS bit in

the CAL_CFGO register or the OADJ_A_FG0_VINA

register)

Input offset voltage

adjustment range

V_{OFF_ADJ}

±55

mV

Foreground calibration at nominal temperature only

Foreground calibration at each temperature

14

4

V_{OFF_}

Offset drift

µV/°C

DRIFT

Default full-scale voltage (FS_RANGE_A

= FS_RANGE_B = 0xA000)

750

800

1040

480

850

Analog differential input full-

scale range

Maximum full-scale voltage (FS_RANGE_A

= FS_RANGE_B = 0xFFFF)

V_{IN_FSR}

1000

mV_PP

Minimum full-scale voltage (FS_RANGE_A

= FS_RANGE_B = 0x2000)

525

Default FS_RANGE_A and FS_RANGE_B setting,

foreground calibration at nominal temperature only,

inputs driven by 50-Ωsource, includes effect of R_IN

drift

0.037

V_{IN_FSR_}Analog differential input full-

%/°C

scale range drift

DRIFT

Default FS_RANGE_A and FS_RANGE_B setting,

foreground calibration at each temperature, inputs

driven by 50-Ωsource, includes effect of R_INdrift

0.006

V_{IN_FSR_}Analog differential input full-

Matching between INA± and INB±, default setting,

dual channel mode

0.53%

scale range matching

MATCH

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6.5 Electrical Characteristics: DC Specifications (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Single-ended input resistance Each input terminal is terminated to AGND, measured

R_IN

48

50

52

Ω

to AGND

at T_A= 25°C

R_{IN_}

Input termination linear

temperature coefficient

13.7

mΩ/°C

TEMPCO

Single-channel mode measured at DC

Dual-channel mode measured at DC

0.45

Single-ended input

capacitance

C_IN

pF

TEMPERATURE DIODE CHARACTERISTICS (TDIODE±)

Forced forward current of 100 µA. Offset voltage

(approximately 0.792 V at 0°C) varies with process

and must be measured for each part. Perform offset

measurements with the device unpowered or with the

PD pin asserted to minimize device self-heating.

Temperature diode voltage

slope

-1.33

mV/°C

ΔV_BE

BANDGAP VOLTAGE OUTPUT (BG)

V_BG

Reference output voltage

1.1

V

I_L≤100 µA

V_{BG_}

Reference output temperature

drift

µV/°C

–85

DRIFT

CLOCK INPUTS (CLK±, SYSREF±, TMSTP±)

Differential termination with DEVCLK_LVPECL_EN =

0, SYSREF_LVPECL_EN = 0 and

TMSTP_LVPECL_EN = 0

100

Z_T

Internal termination

Ω

Single ended termination to GND (per pin) with

DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN =

0 and TMSTP_LVPECL_EN = 0

50

Self-biasing common-mode voltage for CLK± when

AC coupled (DEVCLK_LVPECL_EN must be set to 0)

0.3

Self-biasing common-mode voltage for SYSREF±

when AC coupled (SYSREF_LVPECL_EN must be

Input common-mode voltage, set to 0) and with receiver enabled

0.3

V_CM

V

self-biased

(SYSREF_RECV_EN = 1).

Self-biasing common-mode voltage for SYSREF±

when AC coupled (SYSREF_LVPECL_EN must be

set to 0) and with receiver disabled

VA11

(SYSREF_RECV_EN = 0).

C_{L_DIFF}Differential input capacitance Between positive and negative differential input pins

Single-ended input

0.1

0.5

pF

C_{L_SE}

Each input to ground

capacitance

LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±,

DD[11:0]±)

400

720

350

380

1.3

900

Default swing (HSM), 100-Ωload

Low swing (LSM), 100-Ωload

Low swing high-Z mode (HZM), high-impedance load

VLVDS = 1.9 V

Differential output peak-to-

peak voltage, DC

measurement

mV_PP-

V_DIFF

DIFF

Output common-mode

V_CM

V

voltage, tracks with VLVDS

VLVDS = 1.1 V

0.5

Differential short-circuit

current

I_{OS_DIFF}

Positive and negative outputs shorted together

5

mA

I_{OS_GND}Short-circuit current to ground Either positive or negative output tied to ground

Z_DIFFDifferential output impedance Measured at DC

20

mA

300

Ω

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6.5 Electrical Characteristics: DC Specifications (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE

I_IH

High-level input current

Low-level input current

Input capacitance

40

µA

pF

V

I_IL

–40

C_I

2

V_OH

V_OL

High-level output voltage

Low-level output voltage

1.65

I_LOAD= –400 µA

I_LOAD= 400 µA

150

mV

English Data Sheet: SLVSDR3

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6.6 Electrical Characteristics: Power Consumption

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

846

508

229

382

3.15

1116

611

271

385

3.82

1195

612

266

386

3.97

1195

612

266

327

3.60

35

MAX

UNIT

mA

W

I_VA19

I_VA11

I_VD11

I_VLVDS

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

LVDS interface supply current

Power dissipation

Power mode 1: single-channel

mode, demux-by-2, foreground

calibration, V_LVDS= 1.9 V

I_VA19

I_VA11

I_VD11

I_VLVDS

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

LVDS interface supply current

Power dissipation

mA

W

Power mode 2: single-channel

mode, demux-by-2, background

calibration, V_LVDS= 1.9 V

I_VA19

I_VA11

I_VD11

I_VLVDS

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

LVDS interface supply current

Power dissipation

1300

700

350

450

4.5

mA

W

Power mode 3: dual-channel mode,

demux-by-2, background calibration,

V_LVDS= 1.9 V

I_VA19

I_VA11

I_VD11

I_VLVDS

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

LVDS interface supply current

Power dissipation

mA

W

Power mode 4: dual-channel mode,

demux-by-2, background calibration,

V_LVDS= 1.1 V

I_VA19

I_VA11

I_VD11

I_VLVDS

P_DIS

1.9-V analog supply current

1.1-V analog supply current

1.1-V digital supply current

LVDS interface supply current

Power dissipation

mA

W

23

Power mode 5: PD pin held high, no

clock, V_LVDS= 1.9 V

4

0

0.1

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Foreground calibration

8.0

Full-power input bandwidth

(–3 dB)⁽¹⁾

FPBW

GHz

Background calibration

8.0

Aggressor = 400 MHz, –1 dBFS

Aggressor = 3000 MHz, –1 dBFS

Aggressor = 6000 MHz, –1 dBFS

–91

–59

XTALK

CER

Channel-to-channel crosstalk

Code error rate

dB

errors/

sample

Maximum CER

10^-18

Maximum full-scale voltage

(FS_RANGE_A = FS_RANGE_B =

0xFFFF) setting, foreground

calibration

–151.1

Noise spectral density, no input

signal

NSD

dBFS/Hz

Default full-scale voltage

(FS_RANGE_A = FS_RANGE_B =

0xA000) setting, foreground

calibration

–149.8

21.9

Maximum full-scale voltage

(FS_RANGE_A = FS_RANGE_B =

0xFFFF) setting, foreground

calibration, no input, Z_S= 100 Ω

NF

Noise figure

dB

Default full-scale voltage

(FS_RANGE_A = FS_RANGE_B =

0xA000) setting, foreground

calibration, no input, Z_S= 100 Ω

23.2

No input, foreground calibration,

excludes DC offset, includes fixed

interleaving spur (F_S/2 spur)

NOISE_DCDC input noise standard deviation

2.9

LSB

57.1

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

57.8

56.9

55.6

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

Signal-to-noise ratio, large signal,

excluding DC, HD2 to HD9 and

interleaving spurs

52

SNR

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

56.3

52.8

51.2

49.7

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

English Data Sheet: SLVSDR3

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

57.7

57.4

57.1

57.0

56.2

55.1

53.7

50.0

47.9

46.5

9.0

MAX

UNIT

f_IN= 347 MHz, AIN = –16 dBFS

f_IN= 997 MHz, A_IN= –16 dBFS

f_IN= 2482 MHz, A_IN= –16 dBFS

f_IN= 4997 MHz, A_IN= –16 dBFS

f_IN= 6397 MHz, A_IN= –16 dBFS

f_IN= 8197 MHz, A_IN= –16 dBFS

f_IN= 347 MHz, AIN = –1 dBFS

f_IN= 997 MHz, AIN = –1 dBFS

f_IN= 2482 MHz, AIN = –1 dBFS

f_IN= 4997 MHz, AIN = –1 dBFS

f_IN= 6397 MHz, AIN = –1 dBFS

f_IN= 8197 MHz, AIN = –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

Signal-to-noise ratio, small signal,

excluding DC, HD2 to HD9 and

interleaving spurs

SNR

dBFS

Signal-to-noise and distortion ratio,

large signal, excluding DC and F_S/2

fixed spurs

50

SINAD

dBFS

8.9

8.0

8.6

Effective number of bits, large signal,

excluding DC and F_S/2 fixed spurs

ENOB

bits

8.0

7.7

7.4

70

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

69

66

64

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

Spurious-free dynamic range, large

signal, excluding DC and F_S/2 fixed

spurs

56

SFDR

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

61

57

56

53

78

77

75

78

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –16 dBFS

f_IN= 997 MHz, A_IN= –16 dBFS

f_IN= 2482 MHz, A_IN= –16 dBFS

f_IN= 4997 MHz, A_IN= –16 dBFS

f_IN= 6397 MHz, A_IN= –16 dBFS

f_IN= 8197 MHz, A_IN= –16 dBFS

Spurious-free dynamic range, small

signal, excluding DC and F_S/2 fixed

spurs

SFDR

F_S/2

dBFS

F_S/2 fixed interleaving spur,

independent of input signal

No input

–76

–55

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN= 347 MHz, A_IN= –1 dBFS

–72

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

–73

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

–68

–65

–56

HD2

2^nd-order harmonic

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

–63

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

–65

–59

–65

–74

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

–71

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

–69

–65

–56

HD3

3^rd-order harmonic

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A and

FS_RANGE_B setting, foreground

calibration

–61

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

–57

–56

–53

–73

–74

–73

–72

–66

–74

–72

–74

–73

–72

–70

–56

F_S/2-F_INinterleaving spur, signal

dependent

F_S/2-F_IN

dBFS

–60

SPUR

Worst harmonic 4^th-order or higher

dBFS

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6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN= 347 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

–81

f_IN= 997 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

–87

–72

–61

–53

–45

f_IN= 2482 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

IMD3

3^rd-order intermodulation

dBFS

f_IN= 4997 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

f_IN= 6397 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

f_IN= 8197 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB

below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input

bandwidth.

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Foreground calibration

7.5

Full-power input bandwidth

FPBW

CER

GHz

(–3 dB)⁽¹⁾

Background calibration

Maximum CER

7.5

errors/

sample

Code error rate

10^–18

Maximum full-scale voltage

(FS_RANGE_A = 0xFFFF) setting,

foreground calibration

–154.3

Noise spectral density, no input

signal, excludes fixed interleaving

spurs (F_S/2 and F_S/4 spurs)

NSD

dBFS/Hz

Default full-scale voltage

(FS_RANGE_A = 0xA000) setting,

foreground calibration

–152.5

Maximum full-scale voltage

(FS_RANGE_A = 0xFFFF) setting,

foreground calibration, no input, Z_S

100 Ω

18.7

=

NF

Noise figure

dB

Default full-scale voltage

(FS_RANGE_A = 0xA000) setting,

foreground calibration, no input, Z_S

100 Ω

20.5

3.1

No input, foreground calibration,

excludes DC offset, includes fixed

interleaving spurs (F_S/2 and F_S/4

spurs)

NOISE_DCDC input noise standard deviation

LSB

57.0

57.9

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

56.8

55.8

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

Signal-to-noise ratio, large signal,

excluding DC, HD2 to HD9 and

interleaving spurs

52

SNR

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

56.5

53.2

51.4

50.1

57.8

57.7

57.8

57.5

57.1

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –16 dBFS

f_IN= 997 MHz, A_IN= –16 dBFS

f_IN= 2482 MHz, A_IN= –16 dBFS

f_IN= 4997 MHz, A_IN= –16 dBFS

f_IN= 6397 MHz, A_IN= –16 dBFS

f_IN= 8197 MHz, A_IN= –16 dBFS

Signal-to-noise ratio, small signal,

excluding DC, HD2 to HD9 and

interleaving spurs

SNR

dBFS

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

MIN

TYP

55.9

54.0

53.3

50.5

48.5

44.0

9.0

MAX

UNIT

Signal-to-noise and distortion ratio,

large signal, excluding DC and F_S/2

fixed spurs

48

SINAD

dBFS

8.7

7.7

8.6

Effective number of bits, large signal,

excluding DC and F_S/2 fixed spurs

ENOB

Bits

8.1

7.8

7.0

67

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

66

62

61

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

Spurious-free dynamic range, large

signal, excluding DC, F_S/4 and F_S/2

fixed spurs

50

SFDR

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

58

56

47

78

76

73

76

70

62

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –16 dBFS

f_IN= 997 MHz, A_IN= –16 dBFS

f_IN= 2482 MHz, A_IN= –16 dBFS

f_IN= 4997 MHz, A_IN= –16 dBFS

f_IN= 6397 MHz, A_IN= –16 dBFS

f_IN= 8197 MHz, A_IN= –16 dBFS

Spurious-free dynamic range, small

signal, excluding DC, F_S/4 and F_S/2

fixed spurs

SFDR

dBFS

F_S/2 fixed interleaving spur,

independent of input signal

F_S/2

F_S/4

No input

dBFS

–62

–69

F_S/4 fixed interleaving spur,

independent of input signal

–55

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN= 347 MHz, A_IN= –1 dBFS

–75

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

–73

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

–68

–66

–56

HD2

2^nd-order harmonic

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

–64

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

–69

–64

–68

–74

f_IN= 347 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

–72

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

–66

–56

HD3

3^rd-order harmonic

dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS,

maximum FS_RANGE_A setting,

foreground calibration

–61

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

–59

–56

–68

–63

–62

–56

–47

–75

–71

–77

–74

–70

–68

–50

F_S/2-F_INinterleaving spur, signal

dependent

F_S/2-F_IN

dBFS

–60

F_S/4±F_INinterleaving spurs, signal

dependent

F_S/4±F_IN

dBFS

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6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode) (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

f_IN= 347 MHz, A_IN= –1 dBFS

f_IN= 997 MHz, A_IN= –1 dBFS

f_IN= 2482 MHz, A_IN= –1 dBFS

f_IN= 4997 MHz, A_IN= –1 dBFS

f_IN= 6397 MHz, A_IN= –1 dBFS

f_IN= 8197 MHz, A_IN= –1 dBFS

MIN

TYP

–73

–75

–74

–69

–68

MAX

UNIT

–60

SPUR

Worst harmonic 4^th-order or higher

dBFS

f_IN= 347 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

–81

–80

–72

–62

–56

–49

f_IN= 997 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

f_IN= 2482 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

IMD3

3^rd-order intermodulation

dBFS

f_IN= 4997 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

f_IN= 6397 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

f_IN= 8197 MHz ± 5 MHz,

A_IN= –7 dBFS per tone

(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB

below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB full-power input

bandwidth.

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MAX UNIT

6.9 Timing Requirements

MIN

NOM

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

Input clock frequency (CLK+, CLK–), both single-channel and dual-channel

f_CLK

t_CLK

800

3200

1250

MHz

ps

modes⁽¹⁾

Input clock period (CLK+, CLK–), both single-channel and dual-channel modes⁽¹⁾

312.5

SYSREF (SYSREF+, SYSREF–)

t_INV(SYSRWidth of invalid SYSREF capture region of CLK± period, indicating setup or hold

49

0

ps

time violation, as measured by SYSREF_POS status register⁽²⁾

EF)

Drift of invalid SYSREF capture region over temperature, positive number indicates

a shift toward MSB of SYSREF_POS register

t_INV(TEMP)

ps/°C

ps/mV

Drift of invalid SYSREF capture region over VA11 supply voltage, positive number

indicates a shift toward MSB of SYSREF_POS register

t_INV(VA11)

0.36

SYSREF_ZOOM = 0

t_STEP(SP)Delay of SYSREF_POS LSB

77

24

4

ps

SYSREF_ZOOM = 1

t_{(PH_SYS)}Minimum SYSREF± assertion duration after SYSREF± rising edge event

t_{(PL_SYS)}Minimum SYSREF± deassertion duration after SYSREF± falling edge event

SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)

ns

4

f_CLK(SCLK)Serial clock frequency

0

32

25

3

15.625

MHz

ns

t_(PH)

t_(PL)

Serial clock high value pulse width

Serial clock low value pulse width

ns

t_{SU( SCS)}Setup time from SCS to rising edge of SCLK

ns

t_{H( SCS)}

t_SU(SDI)

t_H(SDI)

Hold time from rising edge of SCLK to SCS

Setup time from SDI to rising edge of SCLK

Hold time from rising edge of SCLK to SDI

ns

25

3

ns

(1) Unless functionally limited to a smaller range than described in the LVDS Output Modes table based on programmed LVDS output

mode.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for SYSREF capture, see the SYSREF Position Detector and Sampling

Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by

t_INV(SYSREF), indicates the portion of the CLK± period (t_CLK), as measured by SYSREF_SEL, that may result in a setup and hold

violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that

were used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in

SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and

SYSREF±.

6.10 Switching Characteristics

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEVICE (SAMPLING) CLOCK (CLK+, CLK–)

Sampling (aperture) delay from CLK±

rising edge (dual channel mode) or

TAD_COARSE = 0x00, TAD_FINE =

t_AD

360

289

ps

rising and falling edge (single channel 0x00 and TAD_INV = 0

mode) to sampling instant⁽⁴⁾

Coarse adjustment (TAD_COARSE =

0xFF)

Maximum t_ADAdjust programmable

delay, not including clock inversion

(TAD_INV = 0)

t_AD(MAX)

Fine adjustment (TAD_FINE = 0xFF)

Coarse adjustment (TAD_COARSE)

Fine adjustment (TAD_FINE)

4.9

1.13

19

ps

fs

t_AD(STEP)

Aperture delay step size

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6.10 Switching Characteristics (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum t_ADAdjust coarse setting

(TAD_COARSE = 0x00, TAD_INV =

0), dither disabled (ADC_DITH_EN =

0)

55

Minimum t_ADAdjust coarse setting

(TAD_COARSE = 0xFF, TAD_INV =

0), dither enabled (ADC_DITH_EN =

1)

70

70⁽¹⁾

80⁽¹⁾

t_AJ

Aperture jitter, rms

fs

Maximum t_ADAdjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither

disabled (ADC_DITH_EN = 0)

Maximum t_ADAdjust coarse setting

(TAD_COARSE = 0xFF) excluding

TAD_INV (TAD_INV = 0), dither

enabled (ADC_DITH_EN = 1)

LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±,

DD[11:0]±)

f_BIT

Output bit rate per output data pair

DDR data clock frequency

1.6

Gbps

MHz

f_DCLK

800

DDR data clock total jitter, peak-to-

peak, with random jitter portion defined

with respect to a BER=1e–15

(Q=7.94)

t_DJ

UPAT_CTRL = 0x10

36

75

ps

Maximum timing skew between any

two LVDS output pairs (DxCLK±,

Dx[11:0]±, DxSTR±) within the same

LVDS bank over operating conditions

t_SKEW(SAME)

Maximum timing skew between any

two LVDS output pairs (DxCLK±,

Dx[11:0]±, DxSTR±) in all LVDS banks

t_SKEW(ALL)

125

ps

over operating conditions with t_OSAB

t_OSACand t_OSBDskew excluded

,

DES_EN = 0, LDEMUX = 0,

LALIGNED = 0

0

DES_EN = 0, LDEMUX = 0,

LALIGNED = 1

DES_EN = 0, LDEMUX = 1,

LALIGNED = 0

0

DES_EN = 0, LDEMUX = 1,

LALIGNED = 1

Functional timing offset between

DACLK± rising edge and DBCLK±

rising edge, positive number indicates

that DACLK± leads DBCLK±

0

t_OSAB

t_CLK

DES_EN = 1, LDEMUX = 0,

LALIGNED = 0

0.5

0

DES_EN = 1, LDEMUX = 0,

LALIGNED = 1

DES_EN = 1, LDEMUX = 1,

LALIGNED = 0

0.5

0

DES_EN = 1, LDEMUX = 1,

LALIGNED = 1

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6.10 Switching Characteristics (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DES_EN = 0, LDEMUX = 1,

LALIGNED = 0

1

DES_EN = 0, LDEMUX = 1,

LALIGNED = 1

Functional timing offset between

DACLK± rising edge and DCCLK±

rising edge, positive number indicates

that DACLK± leads DCCLK±

0

1

t_OSAC

t_CLK

DES_EN = 1, LDEMUX = 1,

LALIGNED = 0

DES_EN = 1, LDEMUX = 1,

LALIGNED = 1

0

DES_EN = 0, LDEMUX = 1,

LALIGNED = 0

1

DES_EN = 0, LDEMUX = 1,

LALIGNED = 1

Functional timing offset between

DBCLK± rising edge and DDCLK±

rising edge, positive number indicates

that DBCLK± leads DDCLK±

0

t_OSBD

t_CLK

DES_EN = 1, LDEMUX = 1,

LALIGNED = 0

1

DES_EN = 1, LDEMUX = 1,

LALIGNED = 1

0

20% to 80%, 1.6 Gbps, V_LVDS= 1.9 V,

UPAT_CTRL = 0x10

125

200

125

200

Low-to-high transition time

(differential)

t_TLH

ps

20% to 80%, 1.6 Gbps, V_LVDS= 1.1 V,

UPAT_CTRL = 0x10

80% to 20%, 1.6 Gbps, V_LVDS= 1.9 V,

UPAT_CTRL = 0x10

t_THL

High-to-low transition time (differential)

80% to 20%, 1.6 Gbps, V_LVDS= 1.1 V,

UPAT_CTRL = 0x10

LATENCY

Output delay from CLK± rising edge

(dual-channel mode) or falling edge

(single-channel mode) to DACLK±

output⁽⁴⁾

TAD_COARSE = 0x00, TAD_FINE =

0x00 and TAD_INV = 0

t_OD

1.5

ns

DES_EN = 0, LDEMUX = 0,

LALIGNED = 0

26

DES_EN = 0, LDEMUX = 0,

LALIGNED = 1

DES_EN = 0, LDEMUX = 1,

LALIGNED = 0

26

DES_EN = 0, LDEMUX = 1,

LALIGNED = 1

27

CLK± edge that samples input signal

to CLK± edge that launches data,

digital latency only^{(2) (4)}

t_LAT(DIG)

t_CLK

DES_EN = 1, LDEMUX = 0,

LALIGNED = 0

26

DES_EN = 1, LDEMUX = 0,

LALIGNED = 1

26.5

26

DES_EN = 1, LDEMUX = 1,

LALIGNED = 0

DES_EN = 1, LDEMUX = 1,

LALIGNED = 1

27.5

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6.10 Switching Characteristics (continued)

typical values at T_A= +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000),

f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PP-DIFFsine-wave clock, DES_EN = 1,

LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless

otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature

range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DES_EN = 0, LDEMUX = 0,

LALIGNED = 0

47

DES_EN = 0, LDEMUX = 0,

LALIGNED = 1

47

DES_EN = 0, LDEMUX = 1,

LALIGNED = 0

DES_EN = 0, LDEMUX = 1,

LALIGNED = 1

Latency from SYSREF± being

sampled by rising edge of CLK± to the

start of the corresponding data

frame⁽³⁾

48

t_LAT(STB)

t_CLK

DES_EN = 1, LDEMUX = 0,

LALIGNED = 0

46.5

47

DES_EN = 1, LDEMUX = 0,

LALIGNED = 1

DES_EN = 1, LDEMUX = 1,

LALIGNED = 0

46.5

48

DES_EN = 1, LDEMUX = 1,

LALIGNED = 1

Latency from SYNCSE assertion or

deassertion to DB0± (LSB) changing

from normal data to strobe output or

strobe output to normal data, digital

latency only

36+1*LF

RAME

LDEMUX = 0

LDEMUX = 1

26

t_{LAT( SYNCSE)}

t_CLK

36+2*LF

RAME

SERIAL PROGRAMMING INTERFACE (SDO)

Delay from falling edge of 16th SCLK

t_(OZD)

cycle during read operation for SDO

transition from tri-state to valid data

1

ns

Delay from SCS rising edge for SDO

to transition from valid data to tri-state

t_(ODZ)

t_(OD)

10

ns

Delay from falling edge of SCLK

during read operation to SDO valid

(1) t_AJincreases because of additional attenuation on internal clock path.

(2) When LDEMUX = 1 the output buses are aligned in time requiring the earlier sample(s) to be delayed before outputting on the LVDS

buses to align with the later samples. The latency for the buses will be slightly different due to added delays. The number shown is for

the worst case bus.

(3) When LDEMUX = 0 the output buses are staggered in time and therefore the start of data frames occur at staggered times. The

number shown is for the earliest output frame. The strobe signals are output at the end of a frame so the start of a data frame

corresponds to the data output immediately after a strobe output.

(4) Both t_ADand t_ODincrease by the delay introduced by TAD_COARSE, TAD_FINE and TAD_INV when t_ADAdjust is used to delay the

sampling instant. The total latency through the device does not include the aperture delay. Total latency through device is t_LAT

_LAT(DIG)+ t_OD- t_AD

=

t

.

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A₁/B₁

A₀/B₀

INA+/t

or

INB+/t

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_SU(SYSREF)t_H(SYSREF)

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

A₀

DA[11:0]+/t

A₁

A₂

DBCLK+/t

DBSTR+/t

LVDS Bus

B

B₀

DB[11:0]+/t

B₁

B₂

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-1. Dual-Channel, 2-Bus Mode Timing (LDEMUX = 0, DES_EN = 0, LALIGNED = 0 or 1)

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A₁/B₁

A₂/B₂

A₀/B₀

INA+/t

or

INB+/t

A₃/B₃

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_OSAC

t_OSBD

t_SU(SYSREF)t_H(SYSREF)

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

DA[11:0]+/t

A₀

A₂

A₄

DCCLK+/t

DCSTR+/t

LVDS Bus

C

DC[11:0]+/t

A₁

A₃

DBCLK+/t

DBSTR+/t

LVDS Bus

B

DB[11:0]+/t

B₀

B₂

B₄

DDCLK+/t

DDSTR+/t

LVDS Bus

D

DD[11:0]+/t

B₁

B₃

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-2. Dual-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 0)

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A₁/B₁

A₂/B₂

A₀/B₀

INA+/t

or

INB+/t

A₃/B₃

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_SU(SYSREF)t_H(SYSREF)

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

DA[11:0]+/t

A₀

A₁

B₀

B₁

A₂

A₄

A₅

B₄

B₅

DCCLK+/t

DCSTR+/t

LVDS Bus

C

DC[11:0]+/t

A₃

B₂

B₃

DBCLK+/t

DBSTR+/t

LVDS Bus

B

DB[11:0]+/t

DDCLK+/t

DDSTR+/t

LVDS Bus

D

DD[11:0]+/t

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-3. Dual-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 1)

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S₁

S₂

S₀

INA+/t

or

INB+/t

S₃

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_SU(SYSREF)

t_H(SYSREF)

t_SKEW(ALL)

t_LAT(STB)

t_OSAB

t_SKEW(SAME)

DACLK+/t

DASTR+/t

LVDS Bus

A

DA[11:0]+/t

S₀

S₂

S₄

DBCLK+/t

DBSTR+/t

LVDS Bus

B

DB[11:0]+/t

S₁

S₃

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-4. Single-Channel, 2-Bus, Staggered-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 0)

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S₁

S₂

S₀

INA+/t

or

INB+/t

S₃

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_SU(SYSREF)t_H(SYSREF)

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

S₀

DA[11:0]+/t

S₂

S₄

DBCLK+/t

DBSTR+/t

LVDS Bus

B

S₁

DB[11:0]+/t

S₃

S₅

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-5. Single-Channel, 2-Bus, Aligned-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 1)

English Data Sheet: SLVSDR3

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S₂

S₃

S₁

S₄

S₀

S₅

INA+/t

S₆

or

S₇

INB+/t

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_OSBD

t_SU(SYSREF)t_H(SYSREF)

t_OSAC

t_OSAB

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

DA[11:0]+/t

S₀

S₄

S₈

DBCLK+/t

DBSTR+/t

LVDS Bus

B

DB[11:0]+/t

S₁

S₅

DCCLK+/t

DCSTR+/t

LVDS Bus

C

DC[11:0]+/t

S₂

S₆

DDCLK+/t

DDSTR+/t

LVDS Bus

D

DD[11:0]+/t

S₃

S₇

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-6. Single-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 0)

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S₂

S₁

S₃

S₄

S₀

S₅

INA+/t

S₆

or

S₇

INB+/t

t_AD

t_LAT(DIG)

t_OD

t_CLK

CLK+

CLKt

SYSREF+

SYSREFt

t_SU(SYSREF)t_H(SYSREF)

t_LAT(STB)

t_SKEW

DACLK+/t

DASTR+/t

LVDS Bus

A

DA[11:0]+/t

S₀

S₁

S₂

S₃

S₄

S₈

DBCLK+/t

DBSTR+/t

LVDS Bus

B

DB[11:0]+/t

S₅

S₆

S₇

S₉

DCCLK+/t

DCSTR+/t

LVDS Bus

C

DC[11:0]+/t

S₁₀

DDCLK+/t

DDSTR+/t

LVDS Bus

D

DD[11:0]+/t

S₁₁

t_SU(SYSREF)and t_H(SYSREF)are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet

SYSREF timing.

图6-7. Single-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 1)

English Data Sheet: SLVSDR3

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SYNCSE

t_LAT(SYNCSE)

DxCLK+

DxCLKœ

Dx0+/œ

(LSB)

X

Frame N

Frame 0

Output Determined by SYNC_PAT[3:0]

Shown: SYNC_PAT[3:0] = 0x2 (Strobe over LSB)

Normal Data

图6-8. SYNCSE Timing Diagram

1^stclock

16^thclock

24^thclock

SCLK

SCS

t_H(SCS)

t_SU(SCS)

t_(PH)

t_(PL)

t_H(SCS)

t_SU(SCS)

t_(PH)+ t_(PL)= t_(P)= 1 / ƒ_CLK(SCLK)

t_SU(SDI)t_H(SDI)

SDI

D7

D1

D0

Write Command

COMMAND FIELD

Hi-Z

t_(OD)

Hi-Z

SDO

D1

D0

t_(OZD)

t_(ODZ)

Read Command

图6-9. Serial Interface Timing

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6.11 Typical Characteristics

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

60

58

56

54

52

50

48

46

44

42

40

60

58

56

54

52

50

48

46

44

42

40

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D001

D002

DES_EN = 0, f_S= 3200 MHz, foreground (FG) and

background (BG) calibration

DES_EN = 1, f_S= 6400 MHz, FG and BG calibration

图6-11. SNR vs Input Frequency

图6-10. SNR vs Input Frequency

60

58

56

54

52

50

48

46

44

42

40

60

58

56

54

52

50

48

46

44

42

40

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D003

D004

DES_EN = 0, f_S= 3200 MHz, FG and BG calibration

DES_EN = 1, f_S= 6400 MHz, FG and BG calibration

图6-12. SINAD vs Input Frequency

图6-13. SINAD vs Input Frequency

9.5

9

8.5

8

9

8.5

8

7.5

7

7.5

7

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

6.5

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D005

D006

DES_EN = 0, f_S= 3200 MHz, FG and BG calibration

DES_EN = 1, f_S= 6400 MHz, FG and BG calibration

图6-14. ENOB vs Input Frequency

图6-15. ENOB vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

80

75

70

65

60

55

50

45

40

80

75

70

65

60

55

50

45

40

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

-1 dBFS, FG Cal

-1 dBFS, BG Cal

-7 dBFS, FG Cal

-7 dBFS, BG Cal

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D007

D008

DES_EN = 0, f_S= 3200 MHz, FG and BG calibration

DES_EN = 1, f_S= 6400 MHz, FG and BG calibration

图6-16. SFDR vs Input Frequency

图6-17. SFDR vs Input Frequency

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

HD2, -1 dBFS

HD2, -7 dBFS

HD3, -1 dBFS

HD3, -7 dBFS

HD2, -1 dBFS

HD2, -7 dBFS

HD3, -1 dBFS

HD3, -7 dBFS

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D009

D010

DES_EN = 0, f_S= 3200 MHz, FG calibration

图6-18. HD2 and HD3 vs Input Frequency

DES_EN = 1, f_S= 6400 MHz, FG calibration

图6-19. HD2 and HD3 vs Input Frequency

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-1 dBFS

-7 dBFS

-1 dBFS

-7 dBFS

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

D011

D012

DES_EN = 0, f_S= 3200 MHz, FG calibration, includes f_S/ 2 –

DES_EN = 1, f_S= 6400 MHz, FG calibration, includes f_S/ 2 –

f_INspur only

f_INand f_S/4 ± f_INspurs only

图6-20. Worst Interleaving Spur vs Input Frequency

图6-21. Worst Interleaving Spur vs Input Frequency

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

60

55

50

45

40

35

60

55

50

45

40

35

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

800

1200

1600

2000

f_S(MSPS)

2400

2800

3200

1600

2400

3200

4000

f_S(MSPS)

4800

5600

6400

D020

D021

DES_EN = 0, FG calibration, A_IN= –1 dBFS

图6-22. SNR vs Sampling Rate

DES_EN = 1, FG calibration, A_IN= –1 dBFS

图6-23. SNR vs Sampling Rate

60

55

50

45

40

35

30

25

20

60

55

50

45

40

35

30

25

20

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

800

1200

1600

2000

f_S(MSPS)

2400

2800

3200

1600

2400

3200

4000

f_S(MSPS)

4800

5600

6400

D022

D023

DES_EN = 0, FG calibration, A_IN= –1 dBFS

图6-24. SINAD vs Sampling Rate

DES_EN = 1, FG calibration, A_IN= –1 dBFS

图6-25. SINAD vs Sampling Rate

9.5

9

9.5

9

8.5

8

8.5

8

7.5

7

7.5

7

6.5

6

6.5

6

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

5.5

5

5.5

5

4.5

4

4.5

4

3.5

800

1200

1600

2000

f_S(MSPS)

2400

2800

3200

1600

2400

3200

4000

f_S(MSPS)

4800

5600

6400

D024

D025

DES_EN = 0, FG calibration, A_IN= –1 dBFS

图6-26. ENOB vs Sampling Rate

DES_EN = 1, FG calibration, A_IN= –1 dBFS

图6-27. ENOB vs Sampling Rate

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

75

70

65

60

55

50

45

40

35

30

25

20

15

10

5

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

800

1200

1600

2000

f_S(MSPS)

2400

2800

3200

1600

2400

3200

4000

f_S(MSPS)

4800

5600

6400

D026

D027

DES_EN = 0, FG calibration, A_IN= –1 dBFS

图6-28. SFDR vs Sampling Rate

DES_EN = 1, FG calibration, A_IN= –1 dBFS

图6-29. SFDR vs Sampling Rate

65

60

55

50

45

40

35

30

25

65

60

55

50

45

40

35

30

25

347 MHz, dBFS

347 MHz, dBc

2488 MHz, dBFS

2488 MHz, dBc

5997 MHz, dBFS

5997 MHz, dBc

347 MHz, dBFS

347 MHz, dBc

2488 MHz, dBFS

2488 MHz, dBc

5997 MHz, dBFS

5997 MHz, dBc

-24

-20

-16

-12

Input Power (dBFS)

-8

-4

0

-24

-20

-16

-12

Input Power (dBFS)

-8

-4

0

D030

D031

DES_EN = 0, FG calibration, f_S= 3200 MSPS

DES_EN = 1, FG calibration, f_S= 6400 MSPS

图6-30. SNR vs Input Power

图6-31. SNR vs Input Power

85

80

75

70

65

60

55

50

45

40

35

30

25

20

85

80

75

70

65

60

55

50

45

40

35

30

25

20

347 MHz, dBFS

347 MHz, dBc

2488 MHz, dBFS

2488 MHz, dBc

5997 MHz, dBFS

5997 MHz, dBc

347 MHz, dBFS

347 MHz, dBc

2488 MHz, dBFS

2488 MHz, dBc

5997 MHz, dBFS

5997 MHz, dBc

-24

-20

-16

-12

Input Power (dBFS)

-8

-4

0

-24

-20

-16

-12

Input Power (dBFS)

-8

-4

0

D032

D033

DES_EN = 0, FG calibration, f_S= 3200 MSPS

DES_EN = 1, FG calibration, f_S= 6400 MSPS

图6-32. SFDR vs Input Power

图6-33. SFDR vs Input Power

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

60

55

50

45

40

70

65

60

55

50

45

40

35

30

25

20

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

347 MHz

997 MHz

2488 MHz

4997 MHz

5997 MHz

8197 MHz

0

0.2 0.4 0.6 0.8

1

Clock Differential Input Voltage (V_PP-DIFF

1.2 1.4 1.6 1.8

)

2

0

0.2 0.4 0.6 0.8

1

Clock Differential Input Voltage (V_PP-DIFF

1.2 1.4 1.6 1.8

)

2

D038

D039

DES_EN = 1, FG calibration, f_S= 6400 MSPS, A_IN= –1

dBFS

图6-34. SNR vs Clock Amplitude

图6-35. SFDR vs Clock Amplitude

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Freqency (MHz)

1200

1600

0

800

1600

Freqency (MHz)

2400

3200

D040

D041

DES_EN = 0, FG calibration, f_S= 3200 MSPS, SNR = 57.2

dBFS, SFDR = 74 dBFS, ENOB = 9.1 bits

DES_EN = 1, FG calibration, f_S= 6400 MSPS, SNR = 57.2

dBFS, SFDR = 69 dBFS, ENOB = 9.1 bits

图6-36. Single-Tone FFT at f_IN= 347 MHz, A_IN= –1 dBFS

图6-37. Single-Tone FFT at f_IN= 347 MHz, A_IN= –1 dBFS

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Freqency (MHz)

1200

1600

0

800

1600

Freqency (MHz)

2400

3200

D042

D043

DES_EN = 0, FG calibration, f_S= 3200 MSPS, SNR = 55.6

dBFS, SFDR = 64 dBFS, ENOB = 8.6 bits

DES_EN = 1, FG calibration, f_S= 6400 MSPS, SNR = 55.8

dBFS, SFDR = 58 dBFS, ENOB = 8.5 bits

图6-38. Single-Tone FFT at f_IN= 2488 MHz, A_IN= –1 dBFS

图6-39. Single-Tone FFT at f_IN= 2488 MHz, A_IN= –1 dBFS

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Freqency (MHz)

1200

1600

0

800

1600

Freqency (MHz)

2400

3200

D044

D045

DES_EN = 0, FG calibration, f_S= 3200 MSPS, SNR = 56.9

dBFS, SFDR = 71 dBFS, ENOB = 9.1 bits

DES_EN = 1, FG calibration, f_S= 6400 MSPS, SNR = 57.5

dBFS, SFDR = 65 dBFS, ENOB = 9.0 bits

图6-40. Single-Tone FFT at f_IN= 2488 MHz, A_IN= –7 dBFS

图6-41. Single-Tone FFT at f_IN= 2488 MHz, A_IN= –7 dBFS

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Freqency (MHz)

1200

1600

0

800

1600

Freqency (MHz)

2400

3200

D046

D047

DES_EN = 0, FG calibration, f_S= 3200 MSPS, SNR = 53.4

dBFS, SFDR = 57 dBFS, ENOB = 8.1 bits

DES_EN = 1, FG calibration, f_S= 6400 MSPS, SNR = 53.7

dBFS, SFDR = 58 dBFS, ENOB = 8.2 bits

图6-42. Single-Tone FFT at f_IN= 4997 MHz, A_IN= –1 dBFS

图6-43. Single-Tone FFT at f_IN= 4997 MHz, A_IN= –1 dBFS

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Freqency (MHz)

1200

1600

0

800

1600

Freqency (MHz)

2400

3200

D048

D049

DES_EN = 0, FG calibration, f_S= 3200 MSPS, SNR = 50.6

dBFS, SFDR = 53 dBFS, ENOB = 7.5 bits

DES_EN = 1, FG calibration, f_S= 6400 MSPS, SNR = 50.8

dBFS, SFDR = 45 dBFS, ENOB = 6.9 bits

图6-44. Single-Tone FFT at f_IN= 8197 MHz, A_IN= –1 dBFS

图6-45. Single-Tone FFT at f_IN= 8197 MHz, A_IN= –1 dBFS

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Frequency (MHz)

1200

1600

0

800

1600

Frequency (MHz)

2400

3200

D050

D051

DES_EN = 0, FG calibration, f_S= 3200 MSPS, f₁= 342 MHz,

f₂= 352 MHz, A_IN= –7 dBFS per tone, SFDR = –77 dBFS,

IMD3 = –87 dBFS, IMD2 = –77 dBFS

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f₁= 342 MHz,

f₂= 352 MHz, A_IN= –7 dBFS per tone, SFDR = –73 dBFS,

IMD3 = –81 dBFS, IMD2 = –88 dBFS

图6-46. Two-Tone FFT at f_IN= 347 MHz, A_IN= –1 dBFS

图6-47. Two-Tone FFT at f_IN= 347 MHz, A_IN= –1 dBFS

0

-20

-40

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Frequency (MHz)

1200

1600

0

800

1600

Frequency (MHz)

2400

3200

D052

D053

DES_EN = 0, FG calibration, f_S= 3200 MSPS, f₁= 2483 MHz,

f₂= 2493 MHz, A_IN= –7 dBFS per tone, SFDR = –71 dBFS,

IMD3 = –71 dBFS, IMD2 = –75 dBFS

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f₁= 2483 MHz,

f₂= 2493 MHz, A_IN= –7 dBFS per tone, SFDR = –60 dBFS,

IMD3 = –72 dBFS, IMD2 = –78 dBFS

图6-48. Two-Tone FFT at f_IN= 2488 MHz, A_IN= –1 dBFS

图6-49. Two-Tone FFT at f_IN= 2488 MHz, A_IN= –1 dBFS

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

0

-20

-40

-60

-80

-100

-120

-100

-120

0

400

800

Frequency (MHz)

1200

1600

0

800

1600

Frequency (MHz)

2400

3200

D054

D055

DES_EN = 0, FG calibration, f_S= 3200 MSPS, f₁= 4992 MHz,

f₂= 5002 MHz, A_IN= –7 dBFS per tone, SFDR = –61 dBFS,

IMD3 = –61 dBFS, IMD2 = –77 dBFS

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f₁= 4992 MHz,

f₂= 5002 MHz, A_IN= –7 dBFS per tone, SFDR = –60 dBFS,

IMD3 = –62 dBFS, IMD2 = –78 dBFS

图6-50. Two-Tone FFT at f_IN= 4997 MHz, A_IN= –1 dBFS

图6-51. Two-Tone FFT at f_IN= 4997 MHz, A_IN= –1 dBFS

0.4

0.3

0.2

0.1

0

3

2

1

0

-0.1

-0.2

-0.3

-0.4

-1

-2

-3

0

1024

2048

Code

3072

4095

0

1024

2048

Code

3072

4095

D060

D061

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f_IN= 247 MHz

图6-52. DNL vs Code

图6-53. INL vs Code

46

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

66

64

62

60

58

56

54

52

50

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

SNR

SINAD

SFDR

HD2

HD3

f_S/4+f_IN

f_S/4-f_IN

f_S/2-f_IN

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

D070

D071

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f_IN= 2488

MHz, A_IN= –1 dBFS

图6-54. Performance vs Temperature

图6-55. Performance vs Temperature

60

58

56

54

52

50

48

46

60

58

56

54

52

50

48

46

44

BG Calibration

FG Calibration at Each Temperature

BG Calibration

FG Calibration at Each Temperature

42

FG Calibration at 25°C

40

FG Calibration at 25°C

40

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

D080

D081

DES_EN = 0, f_S= 3200 MSPS, f_IN= 347 MHz, A_IN= –1

DES_EN = 1, f_S= 6400 MSPS, f_IN= 347 MHz, A_IN= –1

dBFS

图6-56. SNR vs Temperature and Calibration Mode

图6-57. SNR vs Temperature and Calibration Mode

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

60

58

56

54

52

50

48

46

44

42

40

60

58

56

54

52

50

48

46

44

42

40

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

D082

D083

DES_EN = 0, f_S= 3200 MSPS, f_IN= 347 MHz, A_IN= –1

DES_EN = 1, f_S= 6400 MSPS, f_IN= 347 MHz, A_IN= –1

dBFS

图6-58. SINAD vs Temperature and Calibration Mode

图6-59. SINAD vs Temperature and Calibration Mode

9.5

9

8.5

8

9

8.5

8

7.5

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

7

6.5

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

D084

D085

DES_EN = 0, f_S= 3200 MSPS, f_IN= 347 MHz, A_IN= –1

DES_EN = 1, f_S= 6400 MSPS, f_IN= 347 MHz, A_IN= –1

dBFS

图6-60. ENOB vs Temperature and Calibration Mode

图6-61. ENOB vs Temperature and Calibration Mode

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

80

75

70

65

60

55

50

45

40

80

75

70

65

60

55

50

45

40

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

BG Calibration

FG Calibration at Each Temperature

FG Calibration at 25°C

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

-75

-50

-25

0

Ambient Temperature (°C)

25

50

75

100

125

D086

D087

DES_EN = 0, f_S= 3200 MSPS, f_IN= 347 MHz, A_IN= –1

DES_EN = 1, f_S= 6400 MSPS, f_IN= 347 MHz, A_IN= –1

dBFS

图6-62. SFDR vs Temperature and Calibration Mode

图6-63. SFDR vs Temperature and Calibration Mode

66

-35

SNR

SINAD

SFDR

HD2

HD3

f_S/4+f_IN

f_S/4-f_IN

f_S/2-f_IN

64

-40

62

-45

60

58

56

54

52

50

48

46

-50

-55

-60

-65

-70

-75

-80

-85

-5

-4

-3

-2

Supply Voltage Variation from Nominal (%)

-1

0

1

2

3

4

5

-5

-4

-3

-2

Supply Voltage Variation from Nominal (%)

-1

0

1

2

3

4

5

D100

D101

DES_EN = 1, FG calibration, f_S= 6400 MSPS, f_IN= 2488

MHz, A_IN= –1 dBFS

图6-64. Performance vs Supply Voltage

图6-65. Performance vs Supply Voltage

1.2

0.8

0.7

0.6

0.5

0.4

0.3

1.1

1

0.9

0.8

0.2

BG Calibration

FG Calibration

LPBG Calibration

BG Calibration

FG Calibration

LPBG Calibration

0.7

0.1

0

0.6

800

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

800

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

D110

D111

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS

图6-66. VA19 Supply Current vs Clock Rate

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS

图6-67. VA11 Supply Current vs Clock Rate

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

0.5

0.4

0.3

0.2

0.1

0

0.5

0.4

0.3

0.2

0.1

0

BG Calibration

FG Calibration

LPBG Calibration

BG Calibration

FG Calibration

LPBG Calibration

800

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

800

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

D112

D113

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS

图6-68. VD11 Supply Current vs Clock Rate

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS, VLVDS = 1.9

V

图6-69. VLVDS Supply Current vs Clock Rate

0.5

4

0.4

0.3

0.2

0.1

0

3.5

3

2.5

BG Calibration

FG Calibration

LPBG Calibration

BG Calibration

FG Calibration

LPBG Calibration

2

800

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

1200

1600

2000

f_CLK(MHz)

2400

2800

3200

D114

D115

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS, VLVDS = 1.1

DES_EN = 1, f_IN= 2488 MHz, A_IN= –1 dBFS, VLVDS = 1.9

V

图6-70. VLVDS Supply Current vs Clock Rate

图6-71. Power Consumption vs Clock Rate

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

4.5

3

0

4

-3

3.5

3

-6

-9

BG Calibration

FG Calibration

LPBG Calibration

Dual-Channel Mode

Single-Channel Mode

-12

2.5

0

2000

4000 6000

Input Frequency (MHz)

8000

10000

-75

-50

-25

0

25

50

Ambient Temperature (°C)

75

100

125

D_BW

D116

图6-73. Gain Response vs Input Frequency

DES_EN = 1, f_S= 6400 MSPS, f_IN= 2488 MHz, A_IN= –1

dBFS, VLVDS = 1.9 V

图6-72. Power Consumption vs Temperature

4000

3500

3000

2200

2000

1800

1600

1400

2500

2000

1500

1000

500

Zoomed Area

in Following Plot

0

5000 10000 15000 20000 25000 30000 35000

Sample Number

14800

15200

15600

Sample Number

16000

16400

D125

D126

DES_EN = 1, f_S= 6400 MSPS, f_IN= 3199.9 MHz

图6-74. Background Calibration Core Transition (AC Signal)

图6-75. Background Calibration Core Transition (AC Signal

Zoomed)

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6.11 Typical Characteristics (continued)

typical values are at T_A= 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B =

0xA000), f_IN= 248 MHz, A_IN= –1 dBFS, f_CLK= maximum rated clock frequency, filtered 1-V_PPsine-wave clock, DES_EN =

1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), and background calibration

(unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results

exclude DC and signal-independent interleaving spurs (f_S/ 4 and f_S/ 2 spurs)

4096

3584

3072

2560

2048

1536

1024

512

500

400

300

200

100

0

-0.35V Differential

+0.35 V Differential

-0.35 V Differential

0 V Differential

Zoomed Area

in Following Plot

0

1000 2000 3000 4000 5000 6000 7000 8000

Sample Number

1600 1700 1800 1900 2000 2100 2200 2300 2400

Sample Number

D127

D128

DES_EN = 1, f_S= 6400 MSPS, DC input

图6-76. Background Calibration Core Transition (DC Signal)

图6-77. Background Calibration Core Transition (DC Signal

Zoomed)

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7 Detailed Description

7.1 Overview

The ADC12DL3200 is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample

input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DL3200 can sample up to 3200-

MSPS and in single-channel mode up to 6400-MSPS. Programmable tradeoffs in channel count (dual-channel

mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the

needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input

bandwidth (–3 dB) of 8 GHz and a useable frequency range that allows direct RF sampling of L-band, S-band,

C-band, and X-band for frequency agile systems.

The ADC12DL3200 uses a low latency, low-voltage differential signaling (LVDS) interface for latency sensitive

applications or when the simplicity of LVDS is preferred. The interface uses up to 48 data pairs, 4 double data

rate (DDR) clocks and 4 strobe signals arranged in four 12-bit data buses. The interface supports signaling rates

of up to 1.6 Gbps. Strobe signals simplify synchronization across buses and between multiple devices. The

strobe is generated internally and can be reset at a deterministic time by the SYSREF input. Multi-device

synchronization is further eased by innovative synchronization features such as noiseless aperture delay (T_AD

)

adjustment and SYSREF windowing.

7.2 Functional Block Diagram

CALTRG

PD

ORA0 ORA1 ORB0 ORB1 CALSTAT

TDIODE+

TDIODEœ

DACLK+

DACLKœ

SCLK

SPI Registers and

Device Control

SDI

Status Indicators

DA11+

DA11œ

SDO

SCS

LVDS

Bus A

DA0+

DA0œ

DASTR+

DASTRœ

TMSTP+

De-

mux

TMSTPœ

DCCLK+

DCCLKœ

DC11+

DC11œ

Input

MUX

Sample

Marking

LVDS

Bus C

ADC A

INA+

DC0+

DC0œ

INAœ

DCSTR+

DCSTRœ

Strobe

Over-

range

Strobe

Source

Generation and

LSB

Replacement

SYNCSE

DBCLK+

DBCLKœ

INB+

DB11+

DB11œ

LVDS

Bus B

Input

MUX

Sample

Marking

INBœ

ADC B

DB0+

DB0œ

DBSTR+

DBSTRœ

Aperture

Delay Adjust

De-

mux

CLK+

DDCLK+

DDCLKœ

Clock Distribution

and Synchronization

CLKœ

DD11+

DD11œ

LVDS

Bus D

SYSREF+

DD0+

DD0œ

SYSREF

Windowing

SYSREFœ

DDSTR+

DDSTRœ

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7.3 Feature Description

7.3.1 Analog Inputs

The analog inputs of the ADC12DL3200 have internal buffers to enable high input bandwidth and isolate

sampling capacitor glitch noise from the input circuit. The analog inputs must be driven differentially as operation

with a single-ended signal is not recommended because of performance degradation. AC-coupling or DC-

coupling can be used with the analog inputs. The common-mode voltage of the analog inputs is 0 V and is

biased internally through single-ended, 50-Ω resistors to AGND on each input pin. When DC-coupled input

signals are used the applied differential signal must have a common-mode voltage that meets the device Input

common-mode requirements. See V_CMIin the 节 6.3 table. The 0-V input common-mode voltage simplifies the

interface to split-supply differential amplifiers and to a variety of transformers and baluns.

In single-channel mode, either analog input (AIN+ and AIN–or BIN+ and BIN–) can be used as the input to the

ADC core. There is no degradation in analog input bandwidth when using single-channel mode versus dual-

channel mode. The input can be chosen using SINGLE_INPUT in the INPUT_MUX register. In dual-channel

mode, the analog inputs can be swapped using DUAL_INPUT in the INPUT_MUX register.

7.3.1.1 Analog Input Protection

The analog inputs are protected against overdrive conditions by internal clamping diodes that are capable of

sourcing or sinking input currents during overrange conditions; see the voltage and current limits in the 节 6.1

table. The overrange protection is also defined for a peak RF input power in the 节 6.1 table, which is frequency

independent. Operation above the maximum conditions listed in the 节 6.3 table results in an increase in failure-

in-time (FIT) rate, so the system must correct the overdrive condition as quickly as possible. 图 7-1 shows the

analog input protection diodes.

AGND

Analog input

protection

diodes.

50 ꢀ

INA+, INB+

ADC

INAœ, INBœ

50 ꢀ

Input Buffer

图7-1. ADC12DL3200 Analog Input Internal Termination

7.3.1.2 Full-Scale Voltage (V_FS) Adjustment

Input full-scale voltage (V_FS) adjustment is available, in fine increments, for each analog input through the

FS_RANGE_A (see the INA full-scale range adjust register) and FS_RANGE_B register settings (see the INB

full-scale range adjust register) for INA± and INB±, respectively. The available adjustment range is specified in

the 节 6.5 table. Larger full-scale voltages improve SNR performance, but can degrade harmonic distortion. The

full-scale voltage adjustment is useful for matching the full-scale range of multiple ADCs when developing a

multi-converter system or for external interleaving of multiple ADC12DL3200s to achieve higher sampling rates.

7.3.1.3 Analog Input Offset Adjust

The input offset voltage for each input can be adjusted through the OADJ_x_FG0_VINy and

OADJ_x_FG90_VINy registers (registers 0x330 to 0x34F), where x represents the ADC core (A or B) and y

represents the analog input (INA± or INB±). The adjustment range is approximately 28 mV to –28 mV

differential. See the 节7.4.7 section for more information.

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7.3.2 ADC Core

The ADC12DL3200 consists of a total of six ADC cores. The cores are interleaved for higher sampling rates and

swapped on-the-fly for calibration as required by the operating mode. In dual-channel mode each ADC channel

is two-way interleaved. In single-channel mode the ADC is four-way interleaved. This section highlights the

theory of operation and key features of the ADC cores.

7.3.2.1 ADC Theory of Operation

The differential voltages at the analog inputs are captured by the rising edge of CLK± in dual-channel mode or

by the rising and falling edges of CLK± in single-channel mode. After capturing the input signal, the ADC

converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the

voltage on INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output is a

negative 2's complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–,

respectively, then the digital output is a positive 2's complement value. 方程式 1 can calculate the differential

voltage at the input pins from the digital output.

Code

2

^N

V_IN

=

V_FS

(1)

where

• Code is the signed decimation output code (for example, –2048 to +2047)

• N is the ADC resolution

• V_FSis the full-scale input voltage of the ADC as specified in the 节6.3 table, including any adjustment

performed by programming FS_RANGE_A or FS_RANGE_B

7.3.2.2 ADC Core Calibration

ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be

repeated when operating conditions change significantly, namely temperature, in order to maintain optimal

performance. The ADC12DL3200 has a built-in calibration routine that can be run as a foreground operation or a

background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the

input signal, to complete the process. Background calibration can be used to overcome this limitation and allow

constant operation of the ADC. See the 节7.4.7 section for detailed information on each mode.

7.3.2.3 ADC Overrange Detection

To ensure that system gain management has the quickest possible response time, a low-latency configurable

overrange function is included. The overrange function works by monitoring the converted 12-bit samples at the

ADC to quickly detect if the ADC is near saturation or already in an overrange condition. The absolute value of

the upper eight bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1.

These thresholds apply to both channel A and channel B in dual-channel mode. 表7-1 lists how an ADC sample

is converted to an absolute value for a comparison of the thresholds.

表7-1. Conversion of ADC Sample for Overrange Comparison

ADC SAMPLE

(Offset Binary)

ADC SAMPLE

(2's Complement)

UPPER 8 BITS USED FOR

COMPARISON

ABSOLUTE VALUE

1111 1111 1111 (4095)

1111 1111 0000 (4080)

1000 0000 0000 (2048)

0000 0001 0000 (16)

0000 0000 0000 (0)

0111 1111 1111 (2047)

0111 1111 0000 (2032)

0000 0000 0000 (0)

111 1111 1111 (2047)

111 1111 0000 (2032)

000 0000 0000 (0)

1111 1111 (255)

1111 1110 (254)

0000 0000 (0)

1111 1110 (254)

1111 1111 (255)

111 1111 0000 (2032)

111 1111 1111 (2047)

1000 0001 0000 (–2032)

1000 0000 0000 (–2048)

If the upper eight bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the

monitoring period, then the overrange bit associated with the threshold is set to 1, otherwise the overrange bit is

0. In dual-channel mode, the overrange status can be monitored on the ORA0 and ORA1 pins for channel A and

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the ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and ORx1

corresponds to the OVR_T1 threshold. In single-channel mode, the overrange status for the OVR_T0 threshold

is determined by monitoring both the ORA0 and ORB0 outputs and the OVR_T1 threshold is determined by

monitoring both ORA1 and ORB1 outputs. In single-channel mode, the two outputs for each threshold must be

OR'd together to determine whether an over-range condition occurred. OVR_N can be used to set the output

pulse duration from the last overrange event. 表 7-2 lists the overrange pulse durations for the various OVR_N

settings (see the overrange configuration register).

表7-2. Overrange Monitoring Period for the ORA0, ORA1, ORB0, and ORB1 Outputs

OVERRANGE PULSE DURATION FROM LAST OVERRANGE

OVR_N

EVENT (DEVCLK Cycles)

0

1

2

3

4

5

6

7

8

16

32

64

128

256

512

1024

Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is

triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set

much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input

signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never

tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of

time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of

the signal is above −12 dBFS).

7.3.2.4 Code Error Rate (CER)

ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle

codes, resulting from metastability caused by non-ideal comparator limitations. The ADC12DL3200 uses a

unique ADC architecture that inherently allows significant code error rate improvements from traditional pipelined

flash or successive approximation register (SAR) ADCs. The code error rate of the ADC12DL3200 is multiple

orders of magnitude better than what can be achieved in alternative architectures at equivalent sampling rates,

providing significant signal reliability improvements.

7.3.2.5 Internal Dither

The ADC12DL3200 includes internal dither to smooth out the integral nonlinearity (INL) curve. Dither improves

the high-order harmonic performance of the ADC cores that results in a reduction of spurs in the frequency

spectrum for single-tone and narrow-band signals. The dither signal is subtracted out of converted data so that

dither does not show up in the output signal and thus reduce the signal-to-noise signal.

7.3.3 Timestamp

The TMSTP+ and TMSTP– differential inputs can be used as a timestamp input to mark a specific sample

based on the timing of an external trigger event relative to the sampled signal. TIME_STAMP_EN (see the LSB

control bit output register) must be set in order to use the timestamp feature and output the timestamp data.

When enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP± input. In effect, the 12-

bit output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the 12-bit output sample is

the output of a parallel 1-bit converter (TMSTP±) with the same latency as the ADC core. The trigger must be

applied to the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to the ADC sampling

clock and is sampled at approximately the same time as the analog input. Alternatively, the SYSREF± inputs can

be used as the timestamp input when SYSREF_TIME_STAMP_EN is set to 1 in the CLK_CTRL1 register.

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7.3.4 Clocking

The clocking subsystem of the ADC12DL3200 has two input signals: the device clock (CLK+, CLK–) and

SYSREF (SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment

(t_ADadjust), a clock duty cycle corrector, and a SYSREF capture block. 图7-2 shows the clocking subsystem.

Duty Cycle

Correction

t_ADAdjust

CLK+

Clock Distribution

and Synchronization

(ADC cores, digital,

interface, etc.)

CLKœ

S

E

AR

N

O

I

V

F

C

N

I

_

E

AD

T

SYSREF Capture

SYSREF+

Automatic

SYSREF

Calibration

SYSREF

Windowing

SYSREFœ

SYSREF_POS SYSREF_SEL

SRC_EN

图7-2. ADC12DL3200 Clocking Subsystem

The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing

and LVDS outputs. Use a low-noise (low jitter) device clock to maintain high signal-to-noise ratio (SNR) within

the ADC. In dual-channel mode, the analog input signal for each input is sampled on the rising edge of the

device clock. In single-channel mode, both the rising and falling edges of the device clock are used to capture

the analog signal to reduce the maximum clock rate required by the ADC. A noiseless aperture delay adjustment

(t_ADadjust) allows the sampling instance of the ADC to be shifted in fine steps in order to synchronize multiple

ADC12DL3200 devices or to fine-tune system latency. Duty cycle correction is implemented in the

ADC12DL3200 to ease the requirements on the external device clock while maintaining high performance. 表

7-3 summarizes the device clock interface in dual-channel mode and single-channel mode.

表7-3. Device Clock versus Mode of Operation

MODE OF OPERATION

Dual-channel mode

SAMPLING RATE VS f_CLK

SAMPLING INSTANT

Rising edge

1 × f_CLK

Single-channel mode

2 × f_CLK

Rising and falling edge

SYSREF is a system timing reference used to reset clock dividers and strobe generation within the

ADC12DL3200 that is similar to the SYSREF signal used by JESD204B interface devices. SYSREF is used to

synchronize multiple ADC12DL3200 devices. SYSREF must be captured by the correct device clock edge in

order to achieve repeatable latency and synchronization. The ADC12DL3200 includes SYSREF windowing and

automatic SYSREF calibration to ease the requirements on the external clocking circuits and to simplify the

synchronization process. SYSREF can be implemented as a single pulse or as a periodic clock. In periodic

implementations, SYSREF must be equal to, or an integer division of, the frame clock frequency. 方程式 2 can

be used to calculate valid SYSREF frequencies.

f_CLK

f_SYSREF

=

LDEMUX + 1 ì LFRAME ì n

(

)

(2)

where

• LDEMUX and LFRAME are register settings

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• f_CLKis the device clock frequency (CLK±)

• n is any positive integer

7.3.4.1 Noiseless Aperture Delay Adjustment (t_ADAdjust)

The ADC12DL3200 contains a delay adjustment on the device clock (sampling clock) input path, called t_AD

adjust, that can be used to shift the sampling instance within the device in order to align sampling instances

among multiple devices or for external interleaving of multiple ADC12DL3200 devices. Further, t_ADadjust can be

used for automatic SYSREF calibration to simplify synchronization; see the 节 7.3.4.3.2 section. Aperture delay

adjustment is implemented in a way that adds no additional noise to the clock path, however a slight degradation

in aperture jitter (t_AJ) is possible at large values of TAD_COARSE because of internal clock path attenuation.

The degradation in aperture jitter can result in minor SNR degradations at high input frequencies (see t_AJin the

节 6.10 table). This feature is programmed using TAD_INV, TAD_COARSE, and TAD_FINE in the DEVCLK

timing adjust ramp control register. Setting TAD_INV inverts the input clock resulting in a delay equal to half the

clock period. 表7-4 summarizes the step sizes and ranges of the TAD_COARSE and TAD_FINE variable analog

delays. All three delay options are independent and can be used in conjunction. All clocks within the device are

shifted by the programmed t_ADadjust amount, which results in a shift of the timing of the LVDS data interface

and affects the capture of SYSREF.

表7-4. t_ADAdjust Adjustment Ranges

ADJUSTMENT PARAMETER

TAD_INV

ADJUSTMENT STEP

DELAY SETTINGS

MAXIMUM DELAY

1 / (f_CLK× 2)

1

TAD_COARSE

TAD_FINE

256

See t_TAD(STEP)in the 节6.10 table

See t_TAD(MAX)in the 节6.10 table

In order to maintain timing alignment between converters, stable and matched power-supply voltages and device

temperatures must be provided.

Aperture delay adjustment can be changed on-the-fly during normal operation, however changing the aperture

delay also shifts the clock for the LVDS data interface (DxCLK±, DxSTR±, and Dx[11:0]±). The receiving circuit

must be tolerant of shifts in the LVDS data timing. Use of the TAD_RAMP feature may help the receiver avoid

loss of synchronization; see the 节7.3.4.2 section.

7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)

The ADC12DL3200 contains a function to gradually adjust the t_ADadjust setting towards the newly written

TAD_COARSE value. This functionality allows the t_ADadjust setting to be adjusted with minimal internal clock

circuitry glitches. The TAD_RAMP_RATE parameter allows either a slower (one TAD_COARSE LSB per 256

t_CLKcycles) or faster ramp (four TAD_COARSE LSBs per 256 t_CLKcycles) to be selected. The TAD_RAMP_EN

parameter enables the ramp feature and any subsequent writes to TAD_COARSE to initiate a new ramp.

7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency

The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic

latency. The SYSREF signal must be captured by a deterministic device clock (CLK±) edge at each system

power-on and at each device in the system. This requirement imposes setup and hold constraints on SYSREF

relative to CLK±, which can be difficult to meet at giga-sample clock rates over all system operating conditions.

The ADC12DL3200 includes a number of features to simplify this synchronization process and to relax system

timing constraints:

• The ADC12DL3200 uses dual-edge sampling (DES) in single-channel mode to reduce the CLK± input

frequency by half and double the timing window for SYSREF (see 表7-3)

• A SYSREF position detector (relative to CLK±) and selectable SYSREF sampling position aid in meeting

setup and hold times over all conditions; see the 节7.3.4.3.1 section

• Easy-to-use automatic SYSREF calibration uses the aperture timing adjust block (t_ADadjust) to shift the ADC

sampling instance based on the phase of SYSREF (rather than adjusting SYSREF based on the phase of the

ADC sampling instance); see the 节7.3.4.3.2 section

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7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF windowing block is used to first detect the position of SYSREF relative to the CLK± rising edge

and then to select a desired SYSREF sampling instance, which is a delay version of CLK±, to maximize setup

and hold timing margins. In many cases a single SYSREF sampling position (SYSREF_SEL) is sufficient to meet

timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However,

this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF

as operating conditions change or to remove system-to-system variation at production test by finding a unique

optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF windowing block. First, apply the device clock and SYSREF

to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the

SYSREF_POS bits of the SYSREF capture position register. Each bit of SYSREF_POS represents a potential

SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling

position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the

positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting

SYSREF_SEL in clock control register 0 to the value corresponding to that SYSREF_POS position. In general,

the middle sampling position between two setup and hold instances is chosen. Ideally, SYSREF_POS and

SYSREF_SEL are performed at the nominal operating conditions of the system (temperature and supply

voltage) to provide maximum margin for operating condition variations. This process can be performed at final

test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further,

SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions

for a system by sweeping the system temperature and supply voltages. For systems that have large variations in

CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as

system operating conditions change. In general, a single value can be found that meets timing over all

conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking

device.

备注

SYSREF_SEL must be set to 0 when using automatic SYSREF calibration; see the 节 7.3.4.3.2

section.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When

SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are

finer. See the 节 6.10 table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general,

SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition region (defined

by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 23 of

SYSREF_POS are always be set to 1 because there is insufficient information to determine if these settings are

close to a timing violation, although the actual valid window can extend beyond these sampling positions. The

value programmed into SYSREF_SEL is the decimal number representing the desired bit location in

SYSREF_POS. 表 7-5 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings.

Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows

selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional

SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In

general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage; however, in

the fourth example a value of 15 provides additional margin and can be selected instead.

表7-5. Examples of SYSREF_POS Readings and SYSREF_SEL Selections

SYSREF_POS[23:0]

OPTIMAL SYSREF_SEL

0x02E[7:0]

(Largest Delay)

0x02C[7:0]⁽¹⁾

(Smallest Delay)

0x02D[7:0]⁽¹⁾

SETTING

b10000000

b10011000

b10000000

b0110000 0

b00000000

b01100000

b00011001

b00110001

b0 0000001

8 or 9

12

6 or 7

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表7-5. Examples of SYSREF_POS Readings and SYSREF_SEL Selections (continued)

SYSREF_POS[23:0]

OPTIMAL SYSREF_SEL

SETTING

0x02E[7:0]

(Largest Delay)

0x02C[7:0]⁽¹⁾

(Smallest Delay)

0x02D[7:0]⁽¹⁾

b10000000

b10001100

b00000011

b01100011

b00000001

b00011001

4 or 15

6

(1) Red coloration indicates the bits that are selected, as given in the last column of this table.

7.3.4.3.2 Automatic SYSREF Calibration

The ADC12DL3200 has an automatic SYSREF calibration feature to alleviate the often challenging setup and

hold times associated with capturing SYSREF for giga-sample data converters. Automatic SYSREF calibration

uses the t_ADadjust feature to shift the device clock to maximize the SYSREF setup and hold times or to align the

sampling instance based on the SYSREF rising edge.

The ADC12DL3200 must have a proper device clock applied and be programmed for normal operation before

starting the automatic SYSREF calibration. When ready to initiate automatic SYSREF calibration, a continuous

SYSREF signal must be applied. SYSREF must be a continuous (periodic) signal when using the automatic

SYSREF calibration. Start the calibration process by setting SRC_EN high in the SYSREF calibration enable

register after configuring the automatic SYSREF calibration using the SRC_CFG register. Upon setting SRC_EN

high, the ADC12DL3200 searches for the optimal t_ADadjust setting until the device clock falling edge is internally

aligned to the SYSREF rising edge. SRC_DONE in the SYSREF calibration status register can be monitored to

ensure that the SYSREF calibration has finished. By aligning the device clock falling edge with the SYSREF

rising edge, automatic SYSREF calibration maximizes the internal SYSREF setup and hold times relative to the

device clock and also sets the sampling instant based on the SYSREF rising edge. After the automatic SYSREF

calibration finishes, the rest of the startup procedure can be performed to finish bringing up the system.

For multi-device synchronization, the SYSREF rising edge timing must be matched at all devices and therefore

trace lengths must be matched from a common SYSREF source to each ADC12DL3200. Any skew between the

SYSREF rising edge at each device results in additional error in the sampling instance between devices,

however repeatable deterministic latency from system startup to startup through each device must still be

achieved.

图 7-3 provides a timing diagram of the SYSREF calibration procedure. The optimized setup and hold times are

shown as t_SU(OPT)and t_H(OPT), respectively. The device clock and SYSREF are referred to as internal in this

diagram because the phase of the internal signals are aligned within the device and not to the external (applied)

phase of the device clock or SYSREF.

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Sampled Input Signal

Internal Unadjusted

Device Clock

Internal Calibrated

Device Clock

t_TAD(SRC)

Internal SYSREF

t_CAL(SRC)

t_H(OPT)

t_SU(OPT)

Before calibration, device clock falling edge does

not align with SYSREF rising edge

SRC_EN

(SPI register bit)

Calibration

enabled

After calibration, device clock falling edge

aligns with SYSREF rising edge

TAD_DONE

(SPI register bit)

Calibration

finished

图7-3. SYSREF Calibration Timing Diagram

When finished, the t_ADadjust setting found by the automatic SYSREF calibration can be read from SRC_TAD in

the SYSREF calibration status register. After calibration, the system continues to use the calibrated t_ADadjust

setting for operation until the system is powered down. However, if desired, the SYSREF calibration can then be

disabled and the t_ADadjust setting can be fine-tuned according to the systems needs. Alternatively, the use of

the automatic SYSREF calibration can be done at product test (or periodic recalibration) of the optimal t_ADadjust

setting for each system. This value can be stored and written to the TAD register (TAD_INV, TAD_COARSE, and

TAD_FINE) upon system startup.

Do not run the SYSREF calibration when the ADC calibration (foreground or background) is running. If

background calibration is the desired use case, disable the background calibration when the SYSREF calibration

is used, then reenable the background calibration after TAD_DONE goes high. SYSREF_SEL in the clock

control register 0 must be set to 0 when using SYSREF calibration.

SYSREF calibration searches the TAD_COARSE delays using both noninverted (TAD_INV = 0) and inverted

clock polarity (TAD_INV = 1) to minimize the required TAD_COARSE setting in order to minimize loss on the

clock path to reduce aperture jitter (t_AJ).

7.3.5 LVDS Digital Interface

The ADC12DL3200 uses a low-voltage differential signaling (LVDS) interface to output the digital samples. This

interface offers simplicity in its implementation compared to serialized interfaces and provides low latency for

latency-sensitive applications. The interface uses up to 48 data pairs, four DDR clocks, and four strobe signals

arranged in four 12-bit data buses. Strobe signals simplify synchronization across buses and synchronization

between multiple devices. The strobe can be generated internally or mirrored from the TMSTP± or SYSREF±

inputs. Flexible strobe configurations allow tradeoffs in reliability or number of LVDS pairs and the on-the-fly use

of strobe is SPI or pin selectable.

Digital interface scrambling is available to avoid spurious noise generated by the digital interface from leaking

into the ADC samples. The receiver must undo the scrambling operation to extract the proper digital samples

(see the 节7.4.5.5 section) when used. Scrambling is optional.

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7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes

The ADC12DL3200 is able to achieve multi-device synchronization through deterministic latency across the

LVDS interface. First, SYSREF is issued to all devices as a known timing reference for synchronization.

SYSREF resets internal clock dividers and the strobe generation block within the ADC12DL3200. The

ADC12DL3200 issues strobe signals across each bus of the interface to provide timing information to the

receiver. The receiver uses this timing information to achieve fixed latency and for alignment among multiple

ADC12DL3200 devices. The strobe generator block provides internal generation of a repeating strobe signal to

reflect the end of a data frame. The generated strobe can be sent across the interface using a dedicated LVDS

pair (DxSTR±) or as a replacement of the sample LSB with the strobe. Strobe generation can be controlled by

the SYNC signal through the SPI or by using the SYNCSE or TMSTP± inputs (see SYNC_SEL in the LCTRL

register). In all modes, the strobe output can be treated as a data pair with the same timing as the data outputs

(Dx[11:0]±) that is source-synchronous with the associated data clock (DxCLK±).

The strobe generator sets the last unit interval (UI) of a frame high to signal the end of a frame. Frame length is

programmable through the LFRAME register. The SYSREF input marks the start of a frame and, if run

periodically, then the SYSREF period must be an integer number of frames long.

7.3.5.1.1 Dedicated Strobe Pins

Dedicated strobe pins are recommended for applications with robust requirements. Each LVDS bus has a

dedicated strobe (DxSTR±), up to four total, which is source synchronous to its associated data clock (DxCLK±).

The strobe can run continuously or can be enabled and disabled as needed. When enabled, this mode allows

the data bus to still send all 12 bits of the digital samples for highest performance. The tradeoff is that more pins

are needed, two per LVDS bus, for up to eight total pins when operating in DMUX-by-2 mode. 表 7-6 describes

the strobe output. The SYNC signal is not required to output the dedicated strobe signal.

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表7-6. Strobe Output for Dedicated Strobe Pins

1 FRAME (LFRAME = 0x08)

FRAME SAMPLE

NUMBER (UI)

0

S0[11:0]

0

1

S1[11:0]

0

2

S2[11:0]

0

3

S3[11:0]

0

4

S4[11:0]

0

5

S5[11:0]

0

6

S6[11:0]

0

7

S7[11:0]

1

Dx[11:0]

DxSTR

7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins

In four LVDS output modes (see 表 7-11), the data clock (DxCLK±) and strobe (DxSTR±) for LVDS buses C and

D can be disabled to reduce the total number of LVDS pins by eight. In this mode, the LVDS bus A data clock

(DACLK±) and strobe (DASTR±) can be used with the data from bus C and the same signals for bus B can be

used for LVDS bus D. The tradeoff is that digital interface timing may become more difficult. See the 节 7.4.5.3

and 节7.4.5.4 sections.

7.3.5.1.3 LSB Replacement With a Strobe

The strobe signals can also be output over the LSB of the digital sample for each LVDS bus. During transmission

of the strobe the LSB of the sample is replaced by the strobe signal and, therefore, the digital sample is only 11

bits wide resulting in a small loss in ENOB. When the strobe is disabled, all 12 bits of the digital sample are sent

across the interface for full performance. The strobe can be enabled periodically, allowing a tradeoff in ENOB

and robustness and reducing the interface width. Enable this mode by setting SYNC_PAT in the PAT_SEL

register to 0x2. Transmission of the strobe is controlled by the source selected by SYNC_SEL in the LCTRL

register. The SYNCSE pin controls transmission of the strobe by default. 表 7-7 describes the strobe output

when the LSB is replaced with the strobe signal data when SYNC is asserted. 表7-8 describes the strobe output

when the active pattern is used ( SYNC de-asserted).

表7-7. Sync Pattern Output for LSB Replacement With Strobe ( SYNC Asserted)

1 FRAME (LFRAME = 0x08)

FRAME SAMPLE

NUMBER (UI)

0

S0[11:1]

0

1

S1[11:1]

0

2

S2[11:1]

0

3

S3[11:1]

0

4

S4[11:1]

0

5

S5[11:1]

0

6

S6[11:1]

0

7

S7[11:1]

1

Dx[11:1]

Dx0 (LSB)

表7-8. Active Pattern Output for LSB Replacement With Strobe ( SYNC De-Asserted)

1 FRAME (LFRAME = 0x08)

FRAME SAMPLE

NUMBER (UI)

0

1

2

3

4

5

6

7

Dx[11:1]

S0[11:1]

S0[0]

S1[11:1]

S1[0]

S2[11:1]

S2[0]

S3[11:1]

S3[0]

S4[11:1]

S4[0]

S5[11:1]

S5[0]

S6[11:1]

S6[0]

S7[11:1]

S7[0]

Dx0 (LSB)

7.3.5.1.4 Strobe Over All Data Pairs

The strobe signal can also be output over all LVDS lanes. During transmission of the strobe, the entire sample is

replaced by the strobe signal and therefore the sampled data are lost. When the strobe is disabled, all 12 bits of

the digital sample are sent across the interface for full performance. The strobe can be enabled periodically to

ensure synchronization is maintained only if loss of digital samples is allowed by the application. Enable this

mode by setting SYNC_PAT in the PAT_SEL register to 0x3. Transmission of the strobe pattern is controlled by

the source selected by SYNC_SEL in the LCTRL register. The SYNCSE pin controls transmission of the strobe

pattern by default. 表 7-9 describes the strobe output when the strobe signal is output over all data pairs when

SYNC is asserted. 表7-10 describes the strobe output when the active pattern is used ( SYNC de-asserted).

表7-9. Sync Pattern Output for Strobe Over All Data Pairs ( SYNC Asserted)

1 FRAME (LFRAME = 0x08)

FRAME SAMPLE

NUMBER (UI)

0

0x000

0

1

0x000

0

2

0x000

0

3

0x000

0

4

0x000

0

5

0x000

0

6

0x000

0

7

0xFFF

1

Dx[11:0]

DxSTR (if enabled)

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表7-10. Active Pattern Output for Strobe Over All Data Pairs ( SYNC De-Asserted)

1 FRAME (LFRAME = 0x08)

FRAME SAMPLE

NUMBER (UI)

0

S0[11:0]

0

1

S1[11:0]

0

2

S2[11:0]

0

3

S3[11:0]

0

4

S4[11:0]

0

5

S5[11:0]

0

6

S6[11:0]

0

7

S7[11:0]

1

Dx[11:0]

DxSTR (if enabled)

7.3.6 Alarm Monitoring

Built-in alarms are available to monitor internal events. Two types of alarms and upsets are detected by this

feature:

1. SYSREF caused internal clocks to be realigned

2. An upset that affects the internal clocks

When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the

host system writes a 1 to clear it. If the alarm type is not masked (see the ALM_MASK register), then the alarm

is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output that

goes high when an alarm occurs. See CAL_STATUS_SEL in the CAL_PIN_CFG register.

7.3.6.1 Clock Upset Detection

The CLK_ALM register bit indicates if the internal clocks may have been upset. The clocks in channel A are

continuously compared to channel B. If these clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM

register bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to

function properly, follow this usage model:

1. Program LVDS_EN = 0

2. Ensure the device is configured to use both channels (PD_ACH = 0, PD_BCH = 0)

3. Program LVDS_EN = 1

4. Write CLK_ALM = 1 to clear CLK_ALM

5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured

6. When exiting global power-down (via MODE in the DEVICE_CONFIG register or via the PD pin), the

CLK_ALM status bit can be set and must be cleared by writing a 1 to CLK_ALM

7.3.7 Temperature Monitoring Diode

A built-in thermal monitoring diode is available on the TDIODE+ and TDIODE– pins. This diode facilitates

temperature monitoring and characterization of the device in higher ambient temperature environments.

Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a

baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with the

diode voltage slope provided in the 节 6.5 table. Perform offset measurement with the device unpowered or with

the PD pin asserted to minimize device self-heating. Recommended monitoring devices include the LM95233

device and similar remote-diode temperature monitoring products from Texas Instruments.

7.3.8 Analog Reference Voltage

The reference voltage for the ADC12DL3200 is derived from an internal band-gap reference. A buffered version

of the reference voltage is available at the BG pin for convenience. This output has an output-current capability

of ±100 µA. The BG output must be buffered if more current is required. No provision exists for the use of an

external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register

settings. In unique cases, the VA11 supply voltage can act as the reference voltage by setting BG_BYPASS (see

the internal reference bypass register).

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7.4 Device Functional Modes

The ADC12DL3200 can be configured to operate in a number of functional modes. These modes are described

in this section.

7.4.1 Dual-Channel Mode (Non-DES Mode)

The ADC12DL3200 can be used as a dual-channel ADC where the sampling rate is equal to the clock frequency

(f_S= f_CLK) provided at the CLK+ and CLK– pins. The two inputs, AIN± and BIN±, serve as the respective inputs

for each channel in this mode. This mode is chosen simply by setting DES_EN to 0. The analog inputs can be

swapped by setting DUAL_INPUT (see the input mux control register).

7.4.2 Internal Dither Modes

Dither can be disabled by setting ADC_DITH_EN to 0 in the ADC_DITH register, which can result in a slight

improvement in SNR. The amount of dither can be increased by setting ADC_DITH_AMP to 1. The increased

dither can result in further spurious improvements, but can also result in a reduction in SNR. Certain dither

values, caused by device-to-device variations, can result in rounding errors that can either reduce SNR or

reduce fixed spur performance (DC, f_S/ 4, and f_S/ 2 spurs). The choice of tradeoff can be made by setting

ADC_DITH_ERR to 0 to degrade SNR and 1 to degrade the DC, f_S/ 4 (single-channel mode only), and f_S/ 2

spurs.

7.4.3 Single-Channel Mode (DES Mode)

The ADC12DL3200 can also be used as a single-channel ADC where the sampling rate is equal to two times the

clock frequency (f_S= 2 × f_CLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two

ADC channels together to form a single-channel ADC at twice the sampling rate. This mode is chosen simply by

setting DES_EN to 1. Either analog input, INA± or INB±, can serve as the input to the ADC. ADC trim settings

are automatically adjusted based on the chosen input. The analog input can be selected using SINGLE_INPUT

(see the input mux control register).

7.4.4 LVDS Output Driver Modes

The LVDS output drivers can be configured for various swings, terminations and output common-mode levels to

meet the needs of different receivers. The swing can be adjusted between high swing (default) and low swing

mode to save power by setting LVDS_SWING to 0x1. Further power savings can be gained by choosing the

high-Z termination mode by setting LVDS_SWING to 0x3. Only use high-Z termination mode with short

transmission lines and for receivers with high-Z termination. The common-mode voltage is adjusted by adjusting

the VLVDS supply voltage. The output common-mode voltage roughly tracks the VLVDS supply voltage by V_OCM

= V_LVDS–0.6 V.

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7.4.5 LVDS Output Modes

The LVDS output buses can be configured to demux the output data from each ADC channel by one or two by

setting the LDEMUX parameter. When a demux-by-2 option is selected (LDEMUX = 1), the number of output

strobes and data clocks can be reduced by using LCS_EN. The two channels of the ADC12DL3200 can be

interleaved together to achieve double the sample rate (that is, single-channel mode) by setting DES_EN to 1. 表

7-11 lists the available interface and configuration modes. When the LSB replacement with strobe option is used

(SYNC_PAT = 0x2), the strobe column of 表 7-11 can be ignored and replaced with 0 because all dedicated

strobe outputs can be disabled.

表7-11. LVDS Output Modes

USER-PROGRAMMED VALUES

ALLOWED f_S

RANGE

(MSPS)

DATA

PAIRS CLOCKS

DATA

ALLOWED f_CLK

RANGE (MHz)

TIMING

DIAGRAM

LVDS OUTPUT MODE

STROBES

DES_EN

LDEMUX

LALIGNED

Single channel, 2 LVDS

buses, staggered data

1

0

24

48

2

4

2

4

1600–3200

1600–6400

800–1600

800–3200

图6-4

图6-5

图6-6

Single channel, 2 LVDS

buses, aligned data

1

0

1

0

Single channel, 4 LVDS

buses, staggered data

Single channel, 4 LVDS

buses, aligned data

1

0

1

0

1

0 or 1

0

48

24

48

4

2

4

2

4

1600–6400

800–1600

800–3200

800–1600

800–3200

图6-7

图6-1

图6-2

Dual channel, 2 LVDS buses

Dual channel, 4 LVDS buses,

staggered data

Dual channel, 4 LVDS buses,

aligned data

0

1

48

4

800–3200

图6-3

7.4.5.1 Staggered Output Mode

Setting LALIGNED to 0 results in the LVDS output buses being staggered in time. Staggering the output buses

causes an LVDS output switching event to occur at each sampling instance and may result in better spurious

performance than what is described in the 节 7.4.5.2 section. 表 7-11 provides links to the timing diagrams for

staggered output mode.

7.4.5.2 Aligned Output Mode

Setting LALIGNED to 1 results in the LVDS outputs buses being aligned in time, meaning that all buses switch at

the same time. The switching instance is a sub-harmonic of the sampling clock and may result in additional

spurs in the output spectrum as compared to the 节7.4.5.1 section. 表7-11 provides links to the timing diagrams

for aligned output mode.

7.4.5.3 Reducing the Number of Strobes

One strobe is provided for each LVDS bus; however, the number of output strobes can either be reduced or the

strobes can be disabled altogether. Typical use cases for reduced strobes include sharing a single strobe among

multiple buses or implementing a receiver that does not have a FIFO that needs to be synchronized by the

strobes. STBx_EN in the LCS_EN register can be used to disable any unused strobe outputs.

7.4.5.4 Reducing the Number of Data Clocks

One data clock is provided for each LVDS bus; however, the number of data clocks used in the system can be

reduced. The number of data clocks can be reduced if a data clock is shared among multiple buses, which can

be applicable at lower data rates. DCLKx_EN in the LCS_EN register can be used to disable any unused data

clock outputs.

7.4.5.5 Scrambling

The LVDS outputs can be scrambled in order to reduce spectral peaks in the output data, especially for

repeating patterns. Spectral peaks can couple back to the ADC analog input and result in degraded noise or

spurious performance in the ADC output data. Enable scrambling by setting SCR in the LCTRL register. The

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scrambler does not require any memory (only uses the current sample) and uses simple XOR operations in

order to minimize latency. Scrambling does require the two LSBs of each sample to be random (as is the case

for ADC input thermal noise), but also works when the LSB is used as a strobe or timestamp. The scrambler is

enabled by setting SCR in the LCTRL register to 1. The scrambling operation changes slightly depending on the

LWIDTH parameter, as 表 7-12 to 表 7-15 describes. Each table also describes the descrambling operation that

the receiving device must implement in order to recover the original samples. In 表 7-12 to 表 7-15, d[x]

corresponds to bit x of the unscrambled digitized ADC sample at LVDS bus q (q = A, B, C, or D) before

scrambling and y[k] corresponds to the scrambled bit k output from the interface over data pair Dqk±. Likewise,

strobe is the unscrambled strobe signal at the LVDS bus q (q = A, B, C, or D) and strobe_y is the scrambled

strobe output on data pair DqSTR±. The ⊕symbol denotes the bitwise XOR operation.

表7-12. Scrambling and Descrambling Operations (12-Bit Mode, LWIDTH = 0x0)

SCRAMBLER

y[11] = d[11] ⊕d[1] ⊕d[0]

y[10] = d[10] ⊕d[1] ⊕d[0]

y[9] = d[9] ⊕d[1] ⊕d[0]

y[8] = d[8] ⊕d[1] ⊕d[0]

y[7] = d[7] ⊕d[1] ⊕d[0]

y[6] = d[6] ⊕d[1] ⊕d[0]

y[5] = d[5] ⊕d[1] ⊕d[0]

y[4] = d[4] ⊕d[1] ⊕d[0]

y[3] = d[3] ⊕d[1] ⊕d[0]

y[2] = d[2] ⊕d[1] ⊕d[0]

y[1] = d[1]

DESCRAMBLER

d[11] = y[11] ⊕y[0]

d[10] = y[10] ⊕y[0]

d[9] = y[9] ⊕y[0]

d[8] = y[8] ⊕y[0]

d[7] = y[7] ⊕y[0]

d[6] = y[6] ⊕y[0]

d[5] = y[5] ⊕y[0]

d[4] = y[4] ⊕y[0]

d[3] = y[3] ⊕y[0]

d[2] = y[2] ⊕y[0]

d[1] = y[1]

y[0] = d[0] ⊕d[1]

d[0] = y[0] ⊕y[1]

strobe = strobe_y ⊕y[0]

strobe_y = strobe ⊕d[1] ⊕d[0]

表7-13. Scrambling and Descrambling Operations (11-Bit Mode, LWIDTH = 0x1)

SCRAMBLER

y[11] = d[11] ⊕d[2] ⊕d[1]

y[10] = d[10] ⊕d[2] ⊕d[1]

y[9] = d[9] ⊕d[2] ⊕d[1]

y[8] = d[8] ⊕d[2] ⊕d[1]

y[7] = d[7] ⊕d[2] ⊕d[1]

y[6] = d[6] ⊕d[2] ⊕d[1]

y[5] = d[5] ⊕d[2] ⊕d[1]

y[4] = d[4] ⊕d[2] ⊕d[1]

y[3] = d[3] ⊕d[2] ⊕d[1]

y[2] = d[2]

DESCRAMBLER

d[11] = y[11] ⊕y[1]

d[10] = y[10] ⊕y[1]

d[9] = y[9] ⊕y[1]

d[8] = y[8] ⊕y[1]

d[7] = y[7] ⊕y[1]

d[6] = y[6] ⊕y[1]

d[5] = y[5] ⊕y[1]

d[4] = y[4] ⊕y[1]

d[3] = y[3] ⊕y[1]

d[2] = y[2]

y[1] = d[2] ⊕d[1]

d[1] = y[2] ⊕y[1]

d[0] = y[1] ⊕y[0]⁽¹⁾

strobe = strobe_y ⊕y[1]

y[0] = d[2] ⊕d[1] ⊕d[0]⁽¹⁾

strobe_y = strobe ⊕d[1] ⊕d[0]

(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.

表7-14. Scrambling and Descrambling Operations (10-Bit Mode, LWIDTH = 0x2)

SCRAMBLER

DESCRAMBLER

d[11] = y[11] ⊕y[2]

d[10] = y[10] ⊕y[2]

y[11] = d[11] ⊕d[3] ⊕d[2]

y[10] = d[10] ⊕d[3] ⊕d[2]

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表7-14. Scrambling and Descrambling Operations (10-Bit Mode, LWIDTH = 0x2) (continued)

SCRAMBLER

y[9] = d[9] ⊕d[3] ⊕d[2]

y[8] = d[8] ⊕d[3] ⊕d[2]

y[7] = d[7] ⊕d[3] ⊕d[2]

y[6] = d[6] ⊕d[3] ⊕d[2]

y[5] = d[5] ⊕d[3] ⊕d[2]

y[4] = d[4] ⊕d[3] ⊕d[2]

y[3] = d[3]

DESCRAMBLER

d[9] = y[9] ⊕y[2]

d[8] = y[8] ⊕y[2]

d[7] = y[7] ⊕y[2]

d[6] = y[6] ⊕y[2]

d[5] = y[5] ⊕y[2]

d[4] = y[4] ⊕y[2]

d[3] = y[3]

y[2] = d[2] ⊕d[3]

d[2] = y[2] ⊕y[3]

d[1] = 0 (not used)

d[0] = y[0] ⊕y[2]⁽¹⁾

strobe = strobe_y ⊕y[2]

y[1] = 0 (not used)

y[0] = d[0] ⊕d[3] ⊕d[2]⁽¹⁾

strobe_y = strobe ⊕d[3] ⊕d[2]

(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.

表7-15. Scrambling and Descrambling Operations (8-Bit Mode, LWIDTH = 0x3)

SCRAMBLER

y[11] = d[11] ⊕d[5] ⊕d[4]

y[10] = d[10] ⊕d[5] ⊕d[4]

y[9] = d[9] ⊕d[5] ⊕d[4]

y[8] = d[8] ⊕d[5] ⊕d[4]

y[7] = d[7] ⊕d[5] ⊕d[4]

y[6] = d[6] ⊕d[5] ⊕d[4]

y[5] = d[5]

DESCRAMBLER

d[11] = y[11] ⊕y[4]

d[10] = y[10] ⊕y[4]

d[9] = y[9] ⊕y[4]

d[8] = y[8] ⊕y[4]

d[7] = y[7] ⊕y[4]

d[6] = y[6] ⊕y[4]

d[5] = y[5]

y[4] = d[4] ⊕d[5]

d[4] = y[4] ⊕y[5]

d[3] = 0 (not used)

d[2] = 0 (not used)

d[1] = 0 (not used)

d[0] = y[0] ⊕y[4]⁽¹⁾

strobe = strobe_y ⊕y[4]

y[3] = 0 (not used)

y[2] = 0 (not used)

y[1] = 0 (not used)

y[0] = d[0] ⊕d[5] ⊕d[4]⁽¹⁾

strobe_y = strobe ⊕d[5] ⊕d[4]

(1) Only used if LSB_SEL in the LSB_SEL register is set to 0 and TIME_STAMP_EN is set to 1.

7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality

A number of device test patterns are available. These modes insert known patterns into the device data path for

assistance with system debug, development, or characterization. The test patterns can also be used during

system power-up to synchronize the digital interface logic in the receiving device. Two patterns are available at

any time, and are referred to as the active pattern and the sychronization pattern. Toggling between the two

patterns is controlled by the source selected by SYNC_SEL in the LCTRL register. Selecting the active pattern or

synchronization pattern is controlled by the SYNCSE pin by default. The pattern always changes state on a

frame boundary (falling edge of the strobe).

7.4.5.6.1 Active Pattern

The active pattern is chosen by setting ACT_PAT in the PAT_SEL register. The available active patterns are

given below:

• Digitized samples from the ADC (normal operation)

• All LVDS lanes output the user-defined pattern (see the 节7.4.5.6.3 section)

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7.4.5.6.2 Synchronization Pattern

The synchronization pattern is chosen by setting SYNC_PAT in the PAT_SEL register. The available

synchronization patterns are given below:

• All LVDS lanes transmit the user-defined pattern (see the 节7.4.5.6.3 section)

• Frame strobe is transmitted on the LSB of the digital samples of each active LVDS bus. The digitized

samples (ADC output data) are still output on the other LVDS lanes.

• Frame strobe is transmitted on all active LVDS data lanes

7.4.5.6.3 User-Defined Test Pattern

A user-defined test pattern mode allows the user to define a pattern to meet various system needs. Example

patterns included strobe patterns to look for inter-symbol interference issues, single-bit patterns to verify TX to

RX lane connections, and multi-bit patterns to verify time alignment. The pattern is up to eight samples long and

is programmed using the UPAT0 through UPAT7 registers. The user pattern repeats at the beginning of each

frame. If the frame length is less than eight samples than the user pattern is truncated. If the frame length is

greater than eight samples then the user pattern repeats until the end of the frame.

Additionally, there are controls to invert specific bits of the user-defined pattern for each of the LVDS buses in

order to allow a unique pattern on each bus. UPAT_INV_x (x = A, B, C, or D) in the UPAT_CTRL register, as

shown in 表 7-16, inverts the specified bit in each LVDS bus when set to 1. The inversion is independent of the

other buses.

表7-16. UPAT_INV_x Control Definition

REGISTER CONTROL

UPAT_INV_A

LVDS BUS AFFECTED

LVDS BUS BIT INVERTED

BUS INVERSION MASK

0001 0000 0000

A

B

C

D

8

9

UPAT_INV_B

0010 0000 0000

UPAT_INV_C

10

11

0100 0000 0000

UPAT_INV_D

1000 0000 0000

A predefined pattern can also be selected by setting LANE_PAT in the UPAT_CTRL register to 1. LANE_PAT

automatically overrides the programmed user pattern. LANE_PAT is a fixed eight sample sequence output on

each LVDS bus. The pattern is 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF, and 0xFFF. The repetition

rules regarding frame length defined for the user pattern apply to the lane pattern as well.

7.4.6 Power-Down Modes

The PD input pin allows ADC12DL3200 devices to be entirely powered down. Power-down can also be

controlled by MODE (see the device configuration register). The LVDS data output drivers are disabled when PD

is high. When the device returns to normal operation, the LVDS interface must be re-established, which results in

the ADC data pipeline containing meaningless information so the system must wait a sufficient time for the data

to be flushed.

7.4.7 Calibration Modes and Trimming

The ADC12DL3200 has two calibration modes available: foreground calibration and background calibration.

When foreground calibration is initiated the ADCs are automatically taken offline and the output data become

mid-code (0x000 in 2's complement) while a calibration is occurring. Background calibration allows the ADC to

continue normal operation while the ADC cores are calibrated in the background by swapping in a different ADC

core to take its place. Additional offset calibration features are available in both foreground and background

calibration modes. Further, a number of ADC parameters can be trimmed to optimize performance in a user

system.

The ADC12DL3200 consists of a total of six sub-ADCs, each referred to as a bank, with two banks forming an

ADC core. The banks sample out-of-phase so that each ADC core is two-way interleaved. The six banks form

three ADC cores, referred to as ADC A, ADC B, and ADC C. In foreground calibration mode, ADC A samples

INA± and ADC B samples INB± in dual-channel mode and both ADC A and ADC B sample INA± (or INB±) in

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single-channel mode. In the background calibration modes, the third ADC core, ADC C, is swapped in

periodically for ADC A and ADC B so that they can be calibrated without disrupting operation.

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图 7-4 shows a diagram of the calibration system including labeling of the banks that make up each ADC core.

When calibration is performed the linearity, gain, and offset voltage for each bank are calibrated to an internally

generated calibration signal. The analog inputs can be driven during calibration, both foreground and

background, except that when offset calibration (see CAL_OS and CAL_BGOS in the CAL_CFG0 register) is

used there must be no signals (or aliased signals) near DC for proper estimation of the offset (see the 节 7.4.8

section).

ADC A

Bank 0

MUX

Calibration

INA+

Signal

Bank 1

ADC A

Output

INAœ

MUX

Calibration

Engine

ADC C

Bank 2

Bank 3

Calibration

Engine

MUX

Calibration

Signal

Calibration

Engine

ADC B

Output

ADC B

MUX

INB+

Bank 4

Bank 5

INBœ

MUX

Calibration

Engine

Calibration

Signal

Calibration

Engine

图7-4. ADC12DL3200 Calibration System Block Diagram

In addition to calibration, a number of ADC parameters are user-controllable to provide trimming for optimal

performance. These parameters include input offset voltage, ADC gain, interleaving timing, and input termination

resistance. The default trim values are programmed at the factory to unique values for each device that are

determined to be optimal at the test system operating conditions. The factory-programmed values can be read

from the trim registers and adjusted as desired. The register fields that control the trimming are labeled

according to the input that is being sampled (INA± or INB±), the bank that is being trimmed, or the ADC core that

is being trimmed. Trim values are not expected to change as operating conditions change, however optimal

performance can be obtained by doing so. Any custom trimming must be done on a per device basis because of

process variations, meaning that there is no global optimal setting for all parts. See the 节 7.4.9 section for

information about the available trim parameters and associated registers.

7.4.7.1 Foreground Calibration Mode

Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.

Foreground calibration always runs on power-up and a sufficient period of time must elapse before programming

the device to ensure that the calibration is finished. Foreground calibration can be initiated by triggering the

calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (see the calibration

software trigger register) and is chosen by setting CAL_TRIG_EN (see the calibration pin configuration register).

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7.4.7.2 Background Calibration Mode

Background calibration mode allows the ADC to continuously operate, with no interruption of data. This

continuous operation is accomplished by activating an extra ADC core that is calibrated and then takes over

operation for one of the other previously active ADC cores. When that ADC core is taken off-line, that ADC is

calibrated and can in turn take over to allow the next ADC to be calibrated. This process operates continuously,

ensuring the ADC cores always provide the optimum performance regardless of system operating condition

changes. Because of the additional active ADC core, background calibration mode has increased power

consumption in comparison to foreground calibration mode. The low-power background calibration (LPBG) mode

discussed in the 节 7.4.7.3 section provides reduced average power consumption in comparison with the

standard background calibration mode. Background calibration can be enabled by setting CAL_BG (see the

calibration configuration 0 register). CAL_TRIG_EN must be set to 0 and CAL_SOFT_TRIG must be set to 1.

Great care has been taken to minimize effects on converted data while the core switching process occurs;

however, small brief glitches can still occur on the converter data when the cores are swapped.

7.4.7.3 Low-Power Background Calibration (LPBG) Mode

Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores.

Off-line cores are powered down until ready to be calibrated and put on-line. Set LP_EN = 1 to enable the low-

power background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps

before waking up for calibration (if LP_EN = 1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is

allowed to stabilize before calibration and being put on-line. LP_TRIG is used to select between an automatic

switching process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG. In this mode there is

an increase in power consumption during the ADC core calibration. The power consumption roughly alternates

between the power consumption in foreground calibration when the spare ADC core is sleeping to the power

consumption in background calibration when the spare ADC is being calibrated. Design the power-supply

network to handle the transient power requirements for this mode.

7.4.8 Offset Calibration

Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;

however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the

standard calibration process. In both dual-channel mode and single-channel mode, uncalibrated input buffer

offsets result in a shift in the mid-code output (DC offset) with no input. Further, in single-channel mode

uncalibrated input buffer offsets can result in a fixed spur at f_S/ 2. A separate calibration is provided to correct

the input buffer offsets.

There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration

the offsets, requiring the system to ensure this condition during normal operation or have the ability to mute the

input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the

calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled via

CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for

operating condition changes. When CAL_BGOS is set, the system must ensure that there are no DC or near DC

signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed as

a foreground operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN, but

does not correct for variations as operating conditions change.

The offset calibration correction uses the input offset voltage trim registers (see the 节 7.4.9 section) to correct

the offset and therefore must not be written by the user when offset calibration is used. The calibrated values

can be read by reading the OADJ_x_FG0_VINy and OADJ_x_FG90_VINy registers, where x is the ADC core (A

or B) and y is the input (INA± or INB±), after calibration is completed. Only read the values when FG_DONE is

read as 1 when using foreground offset calibration (CAL_OS = 1) and do not read the values when using

background offset calibration (CAL_BGOS = 1).

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7.4.9 Trimming

表 7-17 lists the parameters that can be trimmed and the associated registers. Manual trimming is only allowed

in foreground calibration mode.

表7-17. Trim Register Descriptions

TRIM PARAMETER

Band-gap reference

TRIM REGISTER

NOTES

BG_TRIM

Measurement on the BG output pin.

RTRIM_x,

where x = A for INA± or B for INB±)

The device must be powered on with a clock

applied.

Input termination resistance

A different trim value is allowed for each ADC

core (A or B) to allow trimming of the offsets

as operating conditions change.

OADJ_A_FG90_VINy is used to trim the

offsets of ADC A in single-channel mode.

OADJ_x_FG0_VINy and

OADJ_A_FG90_VINy,

where x = ADC core (A or B) and

y = A for INA± or B for INB±

Input offset voltage

Set FS_RANGE_A and FS_RANGE_B to

default values before trimming the input. Use

FS_RANGE_A and FS_RANGE_B to adjust

the full-scale input voltage.

GAIN_TRIM_x,

where x = A for INA± or B for INB±

INA± and INB± gain

Bank gain trim

GAIN_Bx,

where x = 0, 1, 2, or 3

Trims the gain of the individual ADC banks to

improve gain matching between ADC cores.

Full-scale input voltage adjustment for each

input. The default value is effected by

GAIN_TRIM_x (x = A or B). Trim

GAIN_TRIM_x with FS_RANGE_x set to the

default value. FS_RANGE_x can then be

used to trim the full-scale input voltage.

FS_RANGE_x,

where x = A for INA± or B for INB±

INA± and INB± full-scale input voltage

Trims the timing between the two banks of an

ADC core (ADC A or B) for two clock phases,

either 0° or –90°. The –90° clock phase is

used by ADC A in single-channel mode only.

Bx_TIME_y,

where x = bank number (0–5) and

y = 0° or –90° clock phase

Intra-ADC core timing (bank timing)

The suffix letter (A or B) indicates the ADC

core that is being trimmed.

Inter-ADC core timing (dual-channel mode)

TADJ_A, TADJ_B

The middle letter (A or B) indicates the ADC

core that is being trimmed. The suffix of 0 or

90 indicates the clock phase applied to the

ADC core. 0 indicates a 0° clock and is

sampling in-phase with the clock input

(applies to ADC B). 90 indicates a –90°

clock and therefore is sampling out-of-phase

with the clock input (applies to ADC A).

Inter-ADC core timing (single-channel mode)

TADJ_A_FG90, TADJ_B_FG0

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7.5 Programming

7.5.1 Using the Serial Interface

The serial interface is accessed using the following four pins: serial clock (SCLK), serial data input (SDI), serial

data output (SDO), and serial-interface chip-select ( SCS). Register access is enabled through the SCS pin.

7.5.1.1 SCS

This signal must be asserted low to access a register through the serial interface. Setup and hold times with

respect to the SCLK must be followed.

7.5.1.2 SCLK

Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.

7.5.1.3 SDI

Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write

(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are

always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with

respect to the SCLK must be followed (see the 节6.9 table).

7.5.1.4 SDO

The SDO signal provides the output data requested by a read command. This output is high impedance during

write bus cycles and during the read bit and register address portion of read bus cycles.

7.5.1.5

图7-5 shows that each register access consists of 24 bits. The first bit is high for a read and low for a write.

The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits

are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored, and,

during this time, the SDO outputs the data from the addressed register. 图7-5 shows the serial protocol details.

Single Register Access

SCS

1

8

16

17

24

SCLK

SDI

Command Field

Data Field

R/W A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1 A0

D7

D6

D5

D4

D3

D2

D1 D0

Data Field

High Z

SDO

(read mode)

D7

D6

D5

D4

D3 D2

D1

D0

图7-5. Serial Interface Protocol: Single Read/Write Operation

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7.5.1.6 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction

specifics the access type, register address, and data value as normal. Additional clock cycles of write or read

data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The

register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming

transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends

(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit in the

USR0 register. 图7-6 shows the streaming mode transaction details.

Multiple Register Access

S

1

8

16

17

24

25

32

K

Command Field

Data Field (write mode)

D4 D3 D2 D1

Data Field (write mode)

D5 D4 D3 D2

A1

1

DI

R/W A14 A13 A12

A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D0

D7

D6

D1

D0

Data Field

D4 D3 D2

Data Field

D3 D2

High Z

O

D7

D6

D5

D4

D1

D0

D7

D6

D5

D1

D0

e)

图7-6. Serial Interface Protocol: Streaming Read/Write Operation

7.5.1.7

See the 节7.6 section for detailed information regarding the registers.

备注

The serial interface must not be accessed during calibration of the ADC. Accessing the serial interface

during this time impairs the performance of the device until the device is calibrated correctly. Writing or

reading the serial registers also reduces dynamic performance of the ADC for the duration of the

register access time.

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7.6 Register Maps

7.6.1 SPI_REGISTER_MAP Registers

表 7-18 lists the memory-mapped registers for the SPI_REGISTER_MAP. All register offset addresses not listed

in 表7-18 are considered reserved locations and the register contents are not to be modified.

表7-18. SPI_REGISTER_MAP Registers

Address

0x000

Acronym

Register Name

Section

Go

CONFIG_A

DEVICE_CONFIG

CHIP_TYPE

CHIP_ID

Configuration A (Default: 0x30)

0x002

Device Configuration (Default: 0x00)

0x003

Chip Type (Default: 0x03)

0x004-0x005

0x00C-0x00D

0x010

Chip Identification

VENDOR_ID

USR0

Vendor Identification (Default: 0x0451)

User SPI Configuration (Default: 0x00)

0x029

CLK_CTRL0

CLK_CTRL1

SYSREF_POS

FS_RANGE_A

FS_RANGE_B

BG_BYPASS

SYNC_CTRL

LVDS_SWING

INPUT_MUX

CAL_EN

Clock Control 0 (Default: 0x00)

0x02A

Clock Control 1 (Default: 0x00)

0x02C-0x02E

0x030-0x031

0x032-0x033

0x038

SYSREF Capture Position (Read-only status)

Full-Scale Voltage for INA± (Default: 0xA000)

Full-Scale Voltage for INB± (Default: 0xA000)

Band-Gap Bypass (Default: 0x00)

0x03B

SYNC_SE/TIMESTAMP Control (Default: 0x00)

LVDS Swing Mode (Default: 0x00)

0x048

0x060

Input Mux Control (Default: 0x01)

0x061

Calibration Enable (Default: 0x01)

0x062

CAL_CFG0

CAL_STATUS

CAL_PIN_CFG

CAL_SOFT_TRIG

CAL_LP

Calibration Configuration 0 (Default: 0x01)

Calibration Status (Default: undefined; read-only)

Calibration Pin Configuration (Default: 0x00)

Calibration Software Trigger (Default: 0x01)

Low-Power Background Calibration (Default: 0x88)

Calibration Data Enable (Default: 0x00)

0x06A

0x06B

0x06C

0x06E

0x070

CAL_DATA_EN

CAL_DATA

GAIN_TRIM_A

GAIN_TRIM_B

BG_TRIM

0x071

Calibration Data (Default: undefined)

0x07A

Gain DAC Trim A (Default from fuse ROM)

Gain DAC Trim B (Default from fuse ROM)

Band-Gap Trim (Default from fuse ROM)

Resistor TRIM for INA± (Default from fuse ROM)

Resistor TRIM for INB± (Default from fuse ROM)

ADC Dither register (Default: 0x01)

0x07B

0x07C

0x07E

RTRIM_A

0x07F

RTRIM_B

0x09D

ADC_DITH

B0_TIME_0

B0_TIME_90

B1_TIME_0

B1_TIME_90

B4_TIME_0

B5_TIME_0

LSB_CTRL

LSB_SEL

0x102

Time Adjustment for Bank 0 (0° clock) (Default from fuse ROM)

Time Adjustment for Bank 0 (–90° clock) (Default from fuse ROM)

Time Adjustment for Bank 1 (0° clock) (Default from fuse ROM)

Time Adjustment for Bank 1 (–90° clock) (Default from fuse ROM)

Time Adjustment for Bank 4 (0° clock) (Default from fuse ROM)

Time Adjustment for Bank 5 (0° clock) (Default from fuse ROM)

LSB Control Bit Output (Default: 0x00)

0x103

0x112

0x113

0x142

0x152

0x160

0x161

LSB Control Bit Position (Default: 0x00)

0x180-0x181

0x182-0x183

0x184-0x185

UPAT0

User-Defined Pattern (Sample 0; default: 0x0000)

User-Defined Pattern (Sample 1; default: 0x0FFF; same format as UPAT0)

User-Defined Pattern (Sample 2; default: 0x0000; same format as UPAT0)

UPAT1

UPAT2

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表7-18. SPI_REGISTER_MAP Registers (continued)

Address

0x186-0x187

0x188-0x189

0x18A-0x18B

0x18C-0x18D

0x18E-0x18F

0x190

Acronym

UPAT3

Register Name

Section

Go

User-Defined Pattern (Sample 3; default: 0x0FFF; same format as UPAT0)

User-Defined Pattern (Sample 4; default: 0x0000; same format as UPAT0)

User-Defined Pattern (Sample 5; default: 0x0FFF; same format as UPAT0)

User-Defined Pattern (Sample 6; default: 0x0000; same format as UPAT0)

User-Defined Pattern (Sample 7; default: 0x0FFF; same format as UPAT0)

User-Defined Pattern Control (Default: 0x1E)

LVDS Subsystem Enable (Default: 0x01)

UPAT4

UPAT5

UPAT6

UPAT7

UPAT_CTRL

LVDS_EN

LMODE

0x200

0x201

LVDS Mode (Default: 0x01)

0x202

LFRAME

LSYNC_N

LCTRL

LVDS Frame Length (Default: 0x80; 128 decimal)

LVDS Manual Sync Request (Default: 0x01)

LVDS Control (Default: 0x02)

0x203

0x204

0x205

PAT_SEL

LCS_EN

LVDS Pattern Control (Default: 0x02)

0x206

LVDS Clock and Strobe Enables (Default: 0xFF)

System Status Register

0x208

LVDS_STATUS

PD_CH

0x209

ADC Channel Power-Down (Default: 0x00)

0x211

OVR_T0

Overrange Threshold 0 (Default: 0xF2)

0x212

OVR_T1

Overrange Threshold 1 (Default: 0xAB)

0x213

OVR_CFG

SPIN_ID

Overrange Enable/Hold Off (Default: 0x07)

0x297

Chip Spin Identifier (Default from fuse ROM; read-only)

SYSREF Calibration Enable (Default: 0x00)

SYSREF Calibration Configuration (Default: 0x05)

SYSREF Calibration Status (Default: undefined; read-only)

CLK± Timing Adjust (Default: 0x00)

0x2B0

SRC_EN

SRC_CFG

SRC_STATUS

TAD

0x2B1

0x2B2-0x2B4

0x2B5-0x2B7

0x2B8

TAD_RAMP

ALARM

CLK± Timing Adjust Ramp Control (Default: 0x00)

Alarm Interrupt (Read-only)

0x2C0

0x2C1

ALM_STATUS

ALM_MASK

TADJ_A

Alarm Status (Default: 0x05; write to clear)

0x2C2

Alarm Mask Register (Default: 0x05)

0x310

Timing Adjust for A-ADC, Dual Mode (Default from fuse ROM)

Timing Adjust for B-ADC, Dual Mode (Default from fuse ROM)

0x313

TADJ_B

0x314

TADJ_A_FG90_VINA

Timing Adjust for A-ADC, DES, Foreground Calibration, INA± (Default from

fuse ROM)

0x315

TADJ_B_FG0_VINA

TADJ_A_FG90_VINB

TADJ_B_FG0_VINB

OADJ_A_FG0_VINA

OADJ_A_FG0_VINB

OADJ_A_FG90_VINA

OADJ_A_FG90_VINB

OADJ_B_FG0_VINA

Timing Adjust for B-ADC, DES, Foreground Calibration, INA± (Default from

fuse ROM)

Go

0x31A

Timing Adjust for A-ADC, DES, Foreground Calibration, INB± (Default from

fuse ROM)

0x31B

Timing Adjust for B-ADC, DES, Foreground Calibration, INB± (Default from

fuse ROM)

0x344-0x345

0x346-0x347

0x348-0x349

0x34A-0x34B

0x34C-0x34D

Offset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INA±

(Default from fuse ROM)

Offset Adjustment for A-ADC, Foreground Calibration, 0° Clock, INB±

(Default from fuse ROM)

Offset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INA±

(Default from fuse ROM)

Offset Adjustment for A-ADC, Foreground Calibration, 90° Clock, INB±

(Default from fuse ROM)

Offset Adjustment for B-ADC, Foreground Calibration, INA± (Default from

fuse ROM)

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表7-18. SPI_REGISTER_MAP Registers (continued)

Address

Acronym

Register Name

Section

0x34E-0x34F

OADJ_B_FG0_VINB

Offset Adjustment for B-ADC, Foreground Calibration, INB± (Default from

fuse ROM)

Go

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表7-18. SPI_REGISTER_MAP Registers (continued)

Address

0x360

0x361

0x364

0x365

Acronym

GAIN_B0

GAIN_B1

GAIN_B4

GAIN_B5

Register Name

Section

Go

Fine Gain Adjust for Bank 0 (Default from fuse ROM)

Fine Gain Adjust for Bank 1 (Default from fuse ROM)

Fine Gain Adjust for Bank 4 (Default from fuse ROM)

Fine Gain Adjust for Bank 5 (Default from fuse ROM)

Go

Complex bit access types are encoded to fit into small table cells. 表 7-19 shows the codes that are used for

access types in this section.

表7-19. SPI_REGISTER_MAP Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

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7.6.1.1 CONFIG_A Register (Address = 0x000) [reset = 0x30]

CONFIG_A is shown in 图7-7 and described in 表7-20.

Return to Summary Table.

Configuration A register (default: 0x30). This register controls device reset and SPI interface parameters.

图7-7. CONFIG_A Register

7

6

5

4

3

2

1

0

SOFT_RESET

R/W-0x0

RESERVED

R/W-0x0

ASCEND

R/W-0x1

SDO_ACTIVE

R-0x1

RESERVED

R/W-0x0

表7-20. CONFIG_A Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SOFT_RESET

R/W

0x0

Setting this bit causes a full reset of the device and all SPI registers

(including CONFIG_A). This bit is self-clearing. After writing this bit,

the device may take up to 750 ns to reset. During this time, do not

perform any SPI transactions.

6

5

RESERVED

ASCEND

R/W

0x0

0x1

Reserved

0 : Address is decremented during streaming reads or writes

1 : Address is incremented during streaming reads or writes (default)

4

SDO_ACTIVE

RESERVED

R

0x1

0x0

Always returns 1. Always use SDO for SPI reads.

No SDIO mode is supported.

3-0

R/W

Reserved

7.6.1.2 DEVICE_CONFIG Register (Address = 0x002) [reset = 0x00]

DEVICE_CONFIG is shown in 图7-8 and described in 表7-21.

Return to Summary Table.

Device Configuration register (default: 0x00). This device controls the power-down of the device.

图7-8. DEVICE_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MODE

R/W-0x0

表7-21. DEVICE_CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1-0

RESERVED

MODE

R/W

0x0

Reserved

R/W

0x0

0 : Normal operation (default)

1 : Reserved

2 : Reserved

3 : Power-down

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7.6.1.3 CHIP_TYPE Register (Address = 0x003) [reset = 0x03]

CHIP_TYPE is shown in 图7-9 and described in 表7-22.

Return to Summary Table.

Chip Type register (default: 0x03). This register returns the chip type.

图7-9. CHIP_TYPE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CHIP_TYPE

R-0x3

表7-22. CHIP_TYPE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3-0

RESERVED

CHIP_TYPE

R/W

0x0

Reserved

R

0x3

Always returns 0x3, indicating that the device is a high-speed ADC.

7.6.1.4 CHIP_ID Register (Address = 0x004) [reset = 0x0022]

CHIP_ID is shown in 图7-10 and described in 表7-23.

Return to Summary Table.

Chip Identification register (default: 0x0022). This register returns the chip identification number.

图7-10. CHIP_ID Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CHIP_ID

R-0x0022

表7-23. CHIP_ID Register Field Descriptions

Bit

15-0

Field

CHIP_ID

Type

Reset

Description

R

0x0022

Returns 0x0022, indicating the device is an ADC12DL3200.

7.6.1.5 VENDOR_ID Register (Address = 0xC) [reset = 0x0451]

VENDOR_ID is shown in 图7-11 and described in 表7-24.

Return to Summary Table.

Vendor Identification register (default = 0x0451). This register returns the vendor identification number.

图7-11. VENDOR_ID Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

VENDOR_ID

R-0x0451

表7-24. VENDOR_ID Register Field Descriptions

Bit

15-0

Field

VENDOR_ID

Type

Reset

Description

R

0x0451

Always returns 0x0451 (vendor ID for Texas Instruments).

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7.6.1.6 USR0 Register (Address = 0x010) [reset = 0x00]

USR0 is shown in 图7-12 and described in 表7-25.

Return to Summary Table.

User SPI Configuration register (default: 0x00). This register enables holding of the current address during

streaming SPI transactions.

图7-12. USR0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ADDR_HOLD

R/W-0x0

表7-25. USR0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

R/W

0x0

Reserved

ADDR_HOLD

R/W

0x0

0 : Use the ASCEND register to select address ascend or descend

mode (default)

1 : Address stays constant throughout streaming operation; useful for

reading and writing calibration vector information at the CAL_DATA

register

7.6.1.7 CLK_CTRL0 Register (Address = 0x029) [reset = 0x00]

CLK_CTRL0 is shown in 图7-13 and described in 表7-26.

Return to Summary Table.

Clock Control 0 register (default: 0x00). This register is used to control the SYSREF receiver (SYSREF±),

processing of the SYSREF signal and the SYSREF windowing zoom and delay settings.

图7-13. CLK_CTRL0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SYSREF_PROC_EN SYSREF_RECV_EN

R/W-0x0 R/W-0x0

SYSREF_ZOOM

R/W-0x0

SYSREF_SEL

R/W-0x0

表7-26. CLK_CTRL0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0x0

Reserved

6

SYSREF_PROC_EN

R/W

0x0

This bit enables the SYSREF processor, which allows the device to

process SYSREF events (default: disabled). SYSREF_RECV_EN

must be set before setting SYSREF_PROC_EN.

5

4

SYSREF_RECV_EN

SYSREF_ZOOM

R/W

0x0

Set this bit to enable the SYSREF receiver circuit (default: disabled).

Set this bit to zoom in the SYSREF windowing status and delays

(impacts SYSERF_POS and SYSREF_SEL). When set, the delays

used in the SYSREF windowing feature (reported in the

SYSREF_POS register) become smaller. Use SYSREF_ZOOM for

high clock rates, specifically when multiple SYSREF valid windows

are encountered in the SYSREF_POS register; see the 节7.3.4.3.1

section.

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表7-26. CLK_CTRL0 Register Field Descriptions (continued)

Bit

Field

SYSREF_SEL

Type

Reset

Description

3-0

R/W

0x0

Set this field to select which SYSREF delay to use. Set this field

based on the results returned by SYSREF_POS; see the 节7.3.4.3.1

section. These bits must be set to 0 to use SYSREF calibration; see

the 节7.3.4.3.2 section.

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7.6.1.8 CLK_CTRL1 Register (Address = 0x02A) [reset = 0x00]

CLK_CTRL1 is shown in 图7-14 and described in 表7-27.

Return to Summary Table.

Clock Control 1 register (default: 0x00). This register allows SYSREF to be used as the timestamp input, allows

inversion of the SYSREF signal, and enables the DC-coupled receiver mode for the CLK± and SYSREF± inputs.

图7-14. CLK_CTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

SYSREF_TIME_STAMP_

EN

DEVCLK_LVPECL_EN

SYSREF_LVPECL_EN

SYSREF_INVERTED

R/W-0x0

表7-27. CLK_CTRL1 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7-4

3

R/W

0x0

Reserved

SYSREF_TIME_STAMP_ R/W

EN

0x0

The SYSREF signal is output on the LSB of the LVDS output

samples when SYSREF_TIMESTAMP_EN and TIME_STAMP_EN

are both set. This bit allows SYSREF± to be used as the timestamp

input.

2

1

0

DEVCLK_LVPECL_EN

SYSREF_LVPECL_EN

SYSREF_INVERTED

R/W

0x0

Activate DC-coupled, low-voltage PECL mode for CLK±; see the Pin

Functions table.

Activate DC-coupled, low-voltage PECL mode for SYSREF±; see the

Pin Functions table.

This bit inverts the SYSREF signal used for alignment.

7.6.1.9 SYSREF_POS Register (Address = 0x02C-0x02E) [reset = Undefined]

SYSREF_POS is shown in 图7-15 and described in 表7-28.

Return to Summary Table.

SYSREF Capture Position register (read-only status). This register is used by the SYSREF windowing feature to

report back the valid SYSREF capture windows; see the 节7.3.4.3.1 section.

图7-15. SYSREF_POS Register

23

15

7

22

14

6

21

13

5

20

19

18

10

2

17

9

16

8

SYSREF_POS[23:16]

R-Undefined

12

11

SYSREF_POS[15:8]

R-Undefined

4

3

1

0

SYSREF_POS[7:0]

R-Undefined

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表7-28. SYSREF_POS Register Field Descriptions

Bit

Field

SYSREF_POS

Type

Reset

Description

23-0

R/W

Undefined

Returns a 24-bit status value that indicates the position of the

SYSREF edge with respect to CLK±. Use this field to program

SYSREF_SEL.

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7.6.1.10 INA Full-Scale Range Adjust Register (Address = 0x030-0x031) [reset = 0xA000]

FS_RANGE_A is shown in 图7-16 and described in 表7-29.

Return to Summary Table.

INA± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input

voltage of the INA± input. Calibration must be performed after changing this register; see the 节7.3.1.2 section.

图7-16. FS_RANGE_A Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FS_RANGE_A

R/W-0xA000

表7-29. FS_RANGE_A Register Field Descriptions

Bit

15-0

Field

FS_RANGE_A

Type

Reset

Description

R/W

0xA000

These bits enable adjustment of the analog full-scale range for INA±.

0x0000: Settings below 0x2000 result in degraded performance

0x2000: 500 mV_PP- Recommended minimum setting

0xA000: 800 mV_PP(default)

0xFFFF: 1000 mV_PP- Maximum setting

7.6.1.11 INB Full-Scale Range Adjust Register (Address = 0x032-0x033) [reset = 0xA000]

FS_RANGE_B is shown in 图7-17 and described in 表7-30.

Return to Summary Table.

INB± Full-Scale Range Adjust register (default: 0xA000). This register is used to change the full-scale input

voltage of the INB± input. Calibration must be performed after changing this register; see the 节7.3.1.2 section.

图7-17. FS_RANGE_B Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FS_RANGE_B

R/W-0xA000

表7-30. FS_RANGE_B Register Field Descriptions

Bit

15-0

Field

FS_RANGE_B

Type

Reset

Description

R/W

0xA000

These bits enable adjustment of the analog full-scale range for INB±.

0x0000: Settings below 0x2000 result in degraded performance

0x2000: 500 mV_PP- Recommended minimum setting

0xA000: 800 mV_PP(default)

0xFFFF: 1000 mV_PP- Maximum setting

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7.6.1.12 BG_BYPASS Register (Address = 0x038) [reset = 0x00]

BG_BYPASS is shown in 图7-18 and described in 表7-31.

Return to Summary Table.

Band-Gap Bypass register (default: 0x00). This register can be used to bypass the internal reference and use

the VA11 supply voltage instead.

图7-18. BG_BYPASS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BG_BYPASS

R/W-0x0

表7-31. BG_BYPASS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

BG_BYPASS

R/W

0x0

Reserved

R/W

0x0

When set, VA11 is used as the voltage reference instead of the

band-gap voltage.

7.6.1.13 TMSTP_CTRL Register (Address = 0x03B) [reset = 0x00]

TMSTP_CTRL is shown in 图7-19 and described in 表7-32.

Return to Summary Table.

TMSTP± and Differential SYNC Control register (default: 0x00). This register enables or disables the TMSTP±

input and determines the termination scheme for this input.

图7-19. TMSTP_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TMSTP_LVPECL_EN

R/W-0x0

TMSTP_RECV_EN

R/W-0x0

表7-32. SYNC_CTRL Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7-2

R/W

0x0

Reserved

1

TMSTP_LVPECL_EN

R/W

0x0

When set, this bit activates the DC-coupled, low-voltage PECL mode

for the differential TMSTP± receiver; see the Pin Functions table.

0

TMSTP_RECV_EN

R/W

0x0

This bit enables the differential TMSTP± receiver.

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7.6.1.14 LVDS_SWING Register (Address = 0x048) [reset = 0x00]

LVDS_SWING is shown in 图7-20 and described in 表7-33.

Return to Summary Table.

LVDS Swing Mode register (default: 0x00). This register determines the operating mode of the LVDS output

drivers.

图7-20. LVDS_SWING Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LVDS_SWING

R/W-0x0

表7-33. LVDS_SWING Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1-0

RESERVED

R/W

0x0

Reserved

LVDS_SWING

R/W

0x0

These bits set the swing mode of the LVDS output buffers:

0 : High-swing mode (HSM) (default)

1 : Low-swing mode (LSM)

2 : Reserved (do not use)

3 : Low-swing mode for use with receivers that have a high-Z load

termination (HZM). Only use with short transmission lines to avoid

reflections caused by a high-Z receiver.

7.6.1.15 INPUT_MUX Register (Address = 0x060) [reset = 0x01]

INPUT_MUX is shown in 图7-21 and described in 表7-34.

Return to Summary Table.

Input Mux Control register (default: 0x01). This register controls the input used in single-channel mode and the

swapping of inputs in dual-channel mode; see the 节7.3.1 section.

图7-21. INPUT_MUX Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

DUAL_INPUT

R/W-0x0

RESERVED

R/W-0x0

SINGLE_INPUT

R/W-0x1

表7-34. INPUT_MUX Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

R/W

0x0

Reserved

DUAL_INPUT

R/W

0x0

This bit selects the input for dual-channel mode (non-DES mode).

Only applies if DES_EN = 0.

0 : Channel A samples INA±, channel B samples INB± (no swap)

(default)

1 : Channel A samples INB±, channel B samples INA± (swap)

3-2

RESERVED

R/W

0x0

Reserved

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表7-34. INPUT_MUX Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

SINGLE_INPUT

R/W

0x1

These bits define which chip input is sampled in single-channel

mode (DES mode). Only applies if DES_EN = 1.

0 : Reserved

1 : INA± is sampled (DESA mode)

2 : INB± is sampled (DESB mode)

3 : Reserved

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7.6.1.16 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in 图7-22 and described in 表7-35.

Return to Summary Table.

Calibration Enable register (default: 0x01). This register is used to enable or disable ADC core calibration.

图7-22. CAL_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_EN

R/W-0x1

表7-35. CAL_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

CAL_EN

R/W

0x0

Reserved

R/W

0x1

This bit enables calibration. Set this bit high to run calibration. Set

this bit low to hold calibration in reset to program new calibration

settings. Clearing CAL_EN also resets the clock dividers that clock

the encoders and LVDS interface.

Note 1: Many calibration SPI registers are not synchronized to the

internal clock that runs the calibration logic. Changing these registers

may corrupt the calibration state machine. Always clear CAL_EN

before making any changes to these registers. All registers with this

requirement contain a note in their descriptions. After changing the

registers, set CAL_EN to re-run calibration with the new settings.

Note 2: Always set CAL_EN before setting LVDS_EN.

Note 3: Always clear LVDS_EN before clearing CAL_EN.

7.6.1.17 CAL_CFG0 Register (Address = 0x062) [reset = 0x01]

CAL_CFG0 is shown in 图7-23 and described in 表7-36.

Return to Summary Table.

Calibration Configuration 0 register (default: 0x01). This register controls offset calibration and sets whether

foreground or background calibration is used. Only change this register when CAL_EN is 0.

图7-23. CAL_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_BGOS

R/W-0x0

CAL_OS

R/W-0x0

CAL_BG

R/W-0x0

CAL_FG

R/W-0x1

表7-36. CAL_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

RESERVED

CAL_BGOS

R/W

0x0

Reserved

R/W

0x0

0 : Disable background offset calibration (default)

1 : Enable background offset calibration (requires CAL_BG to be

set).

2

1

CAL_OS

CAL_BG

R/W

0x0

0 : Disable foreground offset calibration (default)

1 : Enable foreground offset calibration (requires CAL_FG to be set)

0 : Disable background calibration (default)

1 : Enable background calibration

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表7-36. CAL_CFG0 Register Field Descriptions (continued)

Bit

Field

CAL_FG

Type

Reset

Description

0

R/W

0x1

0 : Reset calibration values, skip foreground calibration.

1 : Reset calibration values, then run foreground calibration (default).

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7.6.1.18 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in 图7-24 and described in 表7-37.

Return to Summary Table.

Calibration Averaging register (default: 0x61). This address determines the amount of averaging used for offset

calibration.

图7-24. CAL_AVG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OS_AVG

R/W-0x6

RESERVED

R-0x1

表7-37. CAL_AVG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

OS_AVG

R/W

0x0

Reserved

6-4

R/W

R

0x6

0x1

Select the amount of averaging used for each measurement of the

offset correction search. A larger number corresponds to more

averaging.

3-0

RESERVED

Always write 0x1.

7.6.1.19 CAL_STATUS Register (Address = 0x06A) [reset = Undefined]

CAL_STATUS is shown in 图7-25 and described in 表7-38.

Return to Summary Table.

Calibration Status register (default: Undefined) (read-only). This register is used to read out the calibration status

information.

图7-25. CAL_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R-Undefined

CAL_STAT

R-Undefined

CAL_STOPPED

R-Undefined

FG_DONE

R-Undefined

表7-38. CAL_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

RESERVED

R

Undefined

Reserved

4-2

1

CAL_STAT

R

Undefined

Calibration status code

CAL_STOPPED

This bit returns a 1 when background calibration is successfully

stopped at the requested phase. This bit returns a 0 when calibration

starts operating again. If background calibration is disabled, this bit is

set when foreground calibration is completed or skipped.

0

FG_DONE

R

Undefined

This bit is high to indicate that foreground calibration has completed

(or was skipped).

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7.6.1.20 CAL_PIN_CFG Register (Address = 0x06B) [reset = 0x00]

CAL_PIN_CFG is shown in 图7-26 and described in 表7-39.

Return to Summary Table.

Calibration Pin Configuration register (default: 0x00). This register sets the function of the CALSTAT pin and

selects whether hardware or software CALTRIG is used.

图7-26. CAL_PIN_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_STATUS_SEL

R/W-0x0

CAL_TRIG_EN

R/W-0x0

表7-39. CAL_PIN_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

2-1

RESERVED

R/W

0x0

Reserved

CAL_STATUS_SEL

R/W

0x0

0 : CALSTAT output pin matches FG_DONE

1 : CALSTAT output pin matches CAL_STOPPED

2 : CALSTAT output pin matches ALARM

3 : CALSTAT output is always low

0

CAL_TRIG_EN

R/W

0x0

This bit selects the hardware or software trigger source.

0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The

CALTRIG input is disabled (ignored).

1 : Use the CALTRIG input for the calibration trigger. The

CAL_SOFT_TRIG register is ignored.

7.6.1.21 CAL_SOFT_TRIG Register (Address = 0x06C) [reset = 0x01]

CAL_SOFT_TRIG is shown in 图7-27 and described in 表7-40.

Return to Summary Table.

Calibration Software Trigger register (default: 0x01). This register is used as the software CALTRIG.

图7-27. CAL_SOFT_TRIG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_SOFT_TRIG

R/W-0x1

表7-40. CAL_SOFT_TRIG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R/W

0x0

Reserved

0

CAL_SOFT_TRIG

R/W

0x1

CAL_SOFT_TRIG is a software bit to provide the functionality of the

CALTRIG input when there are no hardware resources to drive

CALTRIG. Program CAL_TRIG_EN = 0 to use CAL_SOFT_TRIG for

the calibration trigger.

Note: If no calibration trigger is needed, leave CAL_TRIG_EN = 0

and CAL_SOFT_TRIG = 1 (trigger set high).

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7.6.1.22 Low-Power Background Calibration Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in 图7-28 and described in 表7-41.

Return to Summary Table.

Low-Power Background Calibration register (default: 0x88). This register enables low-power background

calibration and sets the parameters for low-power background calibration.

图7-28. CAL_LP Register

7

6

5

4

3

2

1

0

LP_SLEEP_DLY

R/W-0x4

LP_WAKE_DLY

R/W-0x1

RESERVED

R/W-0x0

LP_TRIG

R/W-0x0

LP_EN

R/W-0x0

表7-41. CAL_LP Register Field Descriptions

Bit

7-5

Field

LP_SLEEP_DLY

Type

Reset

Description

R/W

0x4

These bits adjust how long an ADC sleeps before waking for

calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values

below 4 are not recommended because of limited overall power

reduction benefits.

0: Sleep delay = (2³+ 1) × 256 × t_CLK

1: Sleep delay = (2¹⁵+ 1) × 256 × t_CLK

2: Sleep delay = (2¹⁸+ 1) × 256 × t_CLK

3: Sleep delay = (2²¹+ 1) × 256 × t_CLK

4: Sleep delay = (2²⁴+ 1) × 256 × t_CLK(default, approximately 1.338

seconds with a 3.2-GHz clock)

5: Sleep delay = (2²⁷+ 1) × 256 × t_CLK

6: Sleep delay = (2³⁰+ 1) × 256 × t_CLK

7: Sleep delay = (2³³+ 1) × 256 × t_CLK

4-3

LP_WAKE_DLY

R/W

0x1

These bits adjust how much time is provided for settling before

calibrating an ADC after the ADC wakes up (only applies when

LP_EN = 1). Values lower than 1 are not recommended because

there is insufficient time for the core to stabilize before calibration

begins.

0: Wake delay = (2³+ 1) × 256 × t_CLK

1: Wake delay = (2¹⁸+ 1) × 256 × t_CLK(default, approximately 21 ms

with a 3.2-GHz clock)

2: Wake delay = (2²¹+ 1) × 256 × t_CLK

3: Wake delay = (2²⁴+ 1) × 256 × t_CLK

2

1

RESERVED

LP_TRIG

Must write 0x0.

R/W

0x0

0: ADC sleep duration is set by LP_SLEEP_DLY (autonomous

mode).

1: ADCs sleep until woken by a trigger. An ADC is woken when the

calibration trigger (the CAL_SOFT_TRIG bit or CAL_TRIG input) is

low.

0

LP_EN

0: Disable low-power background calibration (default)

1: Enable low-power background calibration (only applies when

CAL_BG = 1).

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7.6.1.23 CAL_DATA_EN Register (Address = 0x70) [reset = 0x00]

CAL_DATA_EN is shown in 图7-29 and described in 表7-42.

Return to Summary Table.

Calibration Data Enable register (default: 0x00). This register enables reading calibration data.

图7-29. CAL_DATA_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_DATA_EN

R/W-0x0

表7-42. CAL_DATA_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

R/W

0x0

Reserved

CAL_DATA_EN

R/W

0x0

Set this bit to enable the CAL_DATA register to enable reading and

writing of calibration data; see the CAL_DATA register for more

information.

7.6.1.24 CAL_DATA Register (Address = 0x71) [reset = Undefined]

CAL_DATA is shown in 图7-30 and described in 表7-43.

Return to Summary Table.

Calibration Data register (default: Undefined). This register is used to read out the calibration data.

图7-30. CAL_DATA Register

7

6

5

4

3

2

1

0

CAL_DATA

R/W-0x0

表7-43. CAL_DATA Register Field Descriptions

Bit

7-0

Field

CAL_DATA

Type

Reset

Description

R/W

0x0

After setting CAL_DATA_EN, repeated reads of this register return all

calibration values for the ADCs. Repeated writes of this register input

all calibration values for the ADCs. To read the calibration data, read

the register 673 times. To write the vector, write the register 673

times with previously stored calibration data. To speed up the read or

write operation, set ADDR_HOLD = 1 and use streaming read or

write process. IMPORTANT: Accessing the CAL_DATA register when

CAL_STOPPED = 0 corrupts the calibration. Also, stopping the

process before reading or writing 673 times leaves the calibration

data in an invalid state.

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7.6.1.25 GAIN_TRIM_A Register (Address = 0x07A) [reset = Undefined]

GAIN_TRIM_A is shown in 图7-31 and described in 表7-44.

Return to Summary Table.

Gain DAC Trim A register (default from fuse ROM). This register is used for trimming the INA± gain.

图7-31. GAIN_TRIM_A Register

7

6

5

4

3

2

1

0

GAIN_TRIM_A

R/W-Undefined

表7-44. GAIN_TRIM_A Register Field Descriptions

Bit

7-0

Field

GAIN_TRIM_A

Type

Reset

Description

R/W

Undefined

This register enables gain trim of channel A. After reset, the factory

trimmed value can be read and adjusted as required. Use

FS_RANGE_A to adjust the analog full-scale voltage (V_fs) of INA±.

7.6.1.26 GAIN_TRIM_B Register (Address = 0x07B) [reset = Undefined]

GAIN_TRIM_B is shown in 图7-32 and described in 表7-45.

Return to Summary Table.

Gain DAC Trim B register (default from fuse ROM). This register is used for trimming the INB± gain.

图7-32. GAIN_TRIM_B Register

7

6

5

4

3

2

1

0

GAIN_TRIM_B

R/W-Undefined

表7-45. GAIN_TRIM_B Register Field Descriptions

Bit

7-0

Field

GAIN_TRIM_B

Type

Reset

Description

R/W

Undefined

This register enables gain trim of channel B. After reset, the factory

trimmed value can be read and adjusted as required. Use

FS_RANGE_B to adjust the analog full-scale voltage (V_fs) of INB±.

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7.6.1.27 BG_TRIM Register (Address = 0x07C) [reset = Undefined]

BG_TRIM is shown in 图7-33 and described in 表7-46.

Return to Summary Table.

Band-Gap Trim register (default from fuse ROM). Use this register to trim the internal band-gap reference. The

voltage can be measured on the BG pin.

图7-33. BG_TRIM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BG_TRIM

R/W-Undefined

表7-46. BG_TRIM Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3-0

RESERVED

BG_TRIM

R/W

0x0

Reserved

R/W

Undefined

This register enables trimming of the internal band-gap reference.

After reset, the factory trimmed value can be read and adjusted as

required.

7.6.1.28 RTRIM_A Register (Address = 0x07E) [reset = Undefined]

RTRIM_A is shown in 图7-34 and described in 表7-47.

Return to Summary Table.

Resistor TRIM for INA± register (default from fuse ROM). This register can be used to trim the input termination

resistance of INA±.

图7-34. RTRIM_A Register

7

6

5

4

3

2

1

0

RTRIM_A

R/W-Undefined

表7-47. RTRIM_A Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

RTRIM_A

R/W

Undefined

This register controls the INA± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

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7.6.1.29 RTRIM_B Register (Address = 0x7F) [reset = Undefined]

RTRIM_B is shown in 图7-35 and described in 表7-48.

Return to Summary Table.

Resistor TRIM for INB± (default from fuse ROM). This register can be used to trim the input termination

resistance of INB±.

图7-35. RTRIM_B Register

7

6

5

4

3

2

1

0

RTRIM_B

R/W-Undefined

表7-48. RTRIM_B Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

RTRIM_B

R/W

Undefined

This register controls the INB± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

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7.6.1.30 ADC_DITH Register (Address = 0x9D) [reset = 0x01]

ADC_DITH is shown in 图7-36 and described in 表7-49.

Return to Summary Table.

ADC Dither register (default: 0x01). This register can be used enable or disable ADC dither and to adjust the

amount of dither used.

图7-36. ADC_DITH Register

7

6

5

4

3

2

ADC_DITH_ERR

0x0

1

ADC_DITH_AMP

0x0

0

ADC_DITH_EN

0x1

RESERVED

R/W-0x00

表7-49. ADC_DITH Register Field Descriptions

Bit

7-3

2

Field

Type

R/W

Reset

0x00

0x0

Description

RESERVED

Reserved

ADC_DITH_ERR

Small rounding errors may occur when subtracting the dither signal.

The error can be chosen to either slightly degrade SNR or to slightly

increase the DC offset and F_S/2 spur. In addition, the F_S/4 spur will

also be increased slightly while in single channel mode.

0 : Rounding error degrades SNR

1 : Rounding error degrades DC offset, F_S/2 spur and F_S/4 spur

1

0

ADC_DITH_AMP

ADC_DITH_EN

R/W

0x0

0x1

0 : Small dither for better SNR (default)

1 : Large dither for better spurious performance

Set this bit to enable ADC dither. Dither can improve spurious

performance at the expense of slightly degraded SNR. The dither

amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR

and spurious performance.

7.6.1.31 Timing Adjustment for Bank 0 (0° Clock) Register (Address = 0x102) [reset = Undefined]

B0_TIME_0 is shown in 图7-37 and described in 表7-50.

Return to Summary Table.

Timing Adjustment for Bank 0 (0° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 0 ADC when ADC A is configured for a 0° clock phase (dual channel mode).

图7-37. B0_TIME_0 Register

7

6

5

4

3

2

1

0

B0_TIME_0

R/W-Undefined

表7-50. B0_TIME_0 Register Field Descriptions

Bit

7-0

Field

B0_TIME_0

Type

Reset

Description

R/W

Undefined

Timing adjustment for bank 0 when ADC A is configured for 0° clock

phase (dual channel mode).

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7.6.1.32 Timing Adjustment for Bank 0 (90° Clock) Register (Address = 0x103) [reset = Undefined]

B0_TIME_90 is shown in 图7-38 and described in 表7-51.

Return to Summary Table.

Timing Adjustment for Bank 0 (–90° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 0 ADC when ADC A is configured for a –90° clock phase (single channel mode).

图7-38. B0_TIME_90 Register

7

6

5

4

3

2

1

0

B0_TIME_90

R/W-Undefined

表7-51. B0_TIME_90 Register Field Descriptions

Bit

7-0

Field

B0_TIME_90

Type

Reset

Description

R/W

Undefined

Time adjustment for bank 0 applied when ADC is configured for –

90° clock phase (single channel mode).

7.6.1.33 Timing Adjustment for Bank 1 (0° Clock) Register (Address = 0x112) [reset = Undefined]

B1_TIME_0 is shown in 图7-39 and described in 表7-52.

Return to Summary Table.

Timing Adjustment for Bank 1 (0° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 1 ADC when ADC A is configured for a 0° clock phase (dual channel mode).

图7-39. B1_TIME_0 Register

7

6

5

4

3

2

1

0

B1_TIME_0

R/W-Undefined

表7-52. B1_TIME_0 Register Field Descriptions

Bit

7-0

Field

B1_TIME_0

Type

Reset

Description

R/W

Undefined

Timing adjustment for bank 1 applied when ADC is configured for 0°

clock phase (dual channel mode).

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7.6.1.34 Timing Adjustment for Bank 1 (90° Clock) Register (Address = 0x113) [reset = Undefined]

B1_TIME_90 is shown in 图7-40 and described in 表7-53.

Return to Summary Table.

Timing Adjustment for Bank 1 (–90° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 1 ADC when ADC A is configured for a –90° clock phase (single channel mode).

图7-40. B1_TIME_90 Register

7

6

5

4

3

2

1

0

B1_TIME_90

R/W-Undefined

表7-53. B1_TIME_90 Register Field Descriptions

Bit

7-0

Field

B1_TIME_90

Type

Reset

Description

R/W

Undefined

Time adjustment for bank 1 applied when ADC is configured for –

90° clock phase (single channel mode).

7.6.1.35 Timing Adjustment for Bank 4 (0° Clock) Register (Address = 0x142) [reset = Undefined]

B4_TIME_0 is shown in 图7-41 and described in 表7-54.

Return to Summary Table.

Timing Adjustment for Bank 4 (0° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 4 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single

channel mode).

图7-41. B4_TIME_0 Register

7

6

5

4

3

2

1

0

B4_TIME_0

R/W-Undefined

表7-54. B4_TIME_0 Register Field Descriptions

Bit

7-0

Field

B4_TIME_0

Type

Reset

Description

R/W

Undefined

Timing adjustment for bank 4 applied when ADC is configured for 0°

clock phase (dual channel mode and single channel mode).

7.6.1.36 Timing Adjustment for Bank 5 (0° Clock) Register (Address = 0x152) [reset = Undefined]

B5_TIME_0 is shown in 图7-42 and described in 表7-55.

Return to Summary Table.

Timing Adjustment for Bank 5 (0° clock) register (default from fuse ROM). This register is used to adjust the

timing of the Bank 5 ADC when ADC B is configured for a 0° clock phase (dual channel mode and single

channel mode).

图7-42. B5_TIME_0 Register

7

6

5

4

3

2

1

0

B5_TIME_0

R/W-Undefined

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表7-55. B5_TIME_0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

B5_TIME_0

R/W

Undefined

Timing adjustment for bank 5 applied when ADC is configured for 0°

clock phase (dual channel mode and single channel mode).

7.6.1.37 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in 图7-43 and described in 表7-56.

Return to Summary Table.

LSB Control Bit Output register (default: 0x00). This register enables output of the timestamp signal on the LSB

of the output samples.

图7-43. LSB_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TIME_STAMP_EN

R/W-0x0

表7-56. LSB_CTRL Register Field Descriptions

Bit

7-1

0

Field

Type

R/W

Reset

Description

RESERVED

0x0

Reserved

TIME_STAMP_EN

0x0

When set, the timestamp signal is transmitted on the LSB of the

output samples. The latency of the timestamp signal (through the

entire chip) matches the latency of the analog ADC inputs.

Also set TMSTP_RECV_EN when using TIME_STAMP_EN.

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7.6.1.38 LSB_SEL Register (Address = 0x161) [reset = 0x00]

LSB_SEL is shown in 图7-44 and described in 表7-57.

Return to Summary Table.

LSB Control Bit Position register (default: 0x00). This register defines the position of the timestamp signal output

on the LSB of the samples.

图7-44. LSB_SEL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LSB_SEL

R/W-0x0

表7-57. LSB_SEL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

LSB_SEL

R/W

0x0

Reserved

R/W

0x0

0 : Place timestamp on lane 0 (Dx0±) of each LVDS output bus,

independent of the LWIDTH setting. Lane 0 of each bus is enabled

regardless of LWIDTH.

1 : Place timestamp on the LSB of the effective sample size as set by

the LWIDTH parameter. The timestamp is placed on the LSB of the

output sample. The lane that carries timestamp depends on the

selected output sample width (LWIDTH).

For 12-bit samples, lane 0 carries the control data.

For 11-bit samples, lane 1 carries the control data.

For 10-bit samples, lane 2 carries the control data.

For 8-bit samples, lane 4 carries the control data.

7.6.1.39 UPAT0 Register (Address = 0x180) [reset = 0x0000]

UPAT0 is shown in 图7-45 and described in 表7-58.

Return to Summary Table.

User-Defined Pattern (sample 0) register (default: 0x0000). This register, and the UPATx registers that follow,

define the user defined test pattern that can be used to test various aspects of the LVDS interface.

图7-45. UPAT0 Register

15

14

13

12

11

10

9

8

RESERVED

R/W-0x0

UPAT0

R/W-0x0

7

6

5

4

3

2

1

0

UPAT0

R/W-0x0

表7-58. UPAT0 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT0

R/W

0x0

Reserved

R/W

0x0

Defines the value for sample 0 of the user defined pattern. See the

PAT_SEL register and the 节7.4.5.6 section.

Note: Only change this register when LVDS_EN = 0.

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7.6.1.40 UPAT1 Register (Address = 0x182) [reset = 0x0FFF]

UPAT1 is shown in 图7-46 and described in 表7-59.

Return to Summary Table.

User-Defined Pattern (sample 1) register (default: 0x0FFF).

图7-46. UPAT1 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT1

R/W-0xF

UPAT1

R/W-0xFF

表7-59. UPAT1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT1

R/W

0x0

Reserved

R/W

0xFFF

Defines the value for sample 1 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

7.6.1.41 UPAT2 Register (Address = 0x184) [reset = 0x0000]

UPAT2 is shown in 图7-47 and described in 表7-60.

Return to Summary Table.

User-Defined Pattern (sample 2) register (default: 0x0000).

图7-47. UPAT2 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT2

R/W-0x0

UPAT2

R/W-0x00

表7-60. UPAT2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT2

R/W

0x0

Reserved

R/W

0x000

Defines the value for sample 2 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

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7.6.1.42 UPAT3 Register (Address = 0x186) [reset = 0x0FFF]

UPAT3 is shown in 图7-48 and described in 表7-61.

Return to Summary Table.

User-Defined Pattern (sample 3) register (default: 0x0FFF)

图7-48. UPAT3 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT3

R/W-0xF

UPAT3

R/W-0xFF

表7-61. UPAT3 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

15-12

11-0

RESERVED

UPAT3

0x0

Reserved

0xFFF

Defines the value for sample 3 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

7.6.1.43 UPAT4 Register (Address = 0x188) [reset = 0x0000]

UPAT4 is shown in 图7-49 and described in 表7-62.

Return to Summary Table.

User-Defined Pattern (sample 4) register (default: 0x0000).

图7-49. UPAT4 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT4

R/W-0x0

UPAT4

R/W-0x00

表7-62. UPAT4 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT4

R/W

0x0

Reserved

R/W

0x000

Defines the value for sample 4 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

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7.6.1.44 UPAT5 Register (Address = 0x18A) [reset = 0x0FFF]

UPAT5 is shown in 图7-50 and described in 表7-63.

Return to Summary Table.

User-Defined Pattern (sample 5) register (default: 0x0FFF).

图7-50. UPAT5 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT5

R/W-0xF

UPAT5

R/W-0xFF

表7-63. UPAT5 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT5

R/W

0x0

Reserved

R/W

0xFFF

Defines the value for sample 5 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

7.6.1.45 UPAT6 Register (Address = 0x18C) [reset = 0x0000]

UPAT6 is shown in 图7-51 and described in 表7-64.

Return to Summary Table.

User-Defined Pattern (sample 6) register (default: 0x0000).

图7-51. UPAT6 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT6

R/W-0x0

UPAT6

R/W-0x00

表7-64. UPAT6 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT6

R/W

0x0

Reserved

R/W

0x000

Defines the value for sample 6 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

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7.6.1.46 UPAT7 Register (Address = 0x18E) [reset = 0x0FFF]

UPAT7 is shown in 图7-52 and described in 表7-65.

Return to Summary Table.

User-Defined Pattern (sample 7) register (default: 0x0FFF).

图7-52. UPAT7 Register

15

7

14

6

13

5

12

4

11

3

10

2

9

1

8

0

RESERVED

R/W-0x0

UPAT7

R/W-0xF

UPAT7

R/W-0xFF

表7-65. UPAT7 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

UPAT7

R/W

0x0

Reserved

R/W

0xFFF

Defines the value for sample 7 of the user defined pattern. See

UPAT0 register.

Note: Only change this register when LVDS_EN = 0.

7.6.1.47 UPAT_CTRL Register (Address = 0x190) [reset = 0x1E]

UPAT_CTRL is shown in 图7-53 and described in 表7-66.

Return to Summary Table.

User-Defined Pattern Control register (default: 0x1E). This register allows selection of the predefined lane

pattern instead of the user defined pattern and the inversion of specified bits for each lane during user defined

pattern transmission.

图7-53. UPAT_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LANE_PAT

R/W-0x1

UPAT_INV_D

R/W-0x1

UPAT_INV_C

R/W-0x1

UPAT_INV_B

R/W-0x1

UPAT_INV_A

R/W-0x0

表7-66. UPAT_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

LANE_PAT

R/W

0x0

Reserved

R/W

0x1

When set, the UPATn registers are ignored, and the user-defined

pattern is set to: 0x000, 0xFFF, 0x000, 0x000, 0x000, 0xFFF, 0xFFF,

0xFFF. This bit acts as a shortcut to avoid programming the UPATn

registers. PAT_SEL register must still be programmed to configure

the interface to select the user-defined pattern. The UPAT_INV_*

registers still apply when using LANE_PAT.

3

2

UPAT_INV_D

UPAT_INV_C

R/W

0x1

When set, bit [11] of the user-defined pattern is inverted on the bus D

output.

When set, bit [10] of the user-defined pattern is inverted on the bus C

output.

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表7-66. UPAT_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

UPAT_INV_B

R/W

0x1

When set, bit [9] of the user-defined pattern is inverted on the bus B

output.

0

UPAT_INV_A

R/W

0x0

When set, bit [8] of the user-defined pattern is inverted on the bus A

output.

Note: Only change this register when LVDS_EN = 0.

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7.6.1.48 LVDS_EN Register (Address = 0x200) [reset = 0x01]

LVDS_EN is shown in 图7-54 and described in 表7-67.

Return to Summary Table.

LVDS Subsystem Enable register (default: 0x01). Use this register to enable or disable the LVDS interface.

图7-54. LVDS_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LVDS_EN

R/W-0x1

表7-67. LVDS_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

LVDS_EN

R/W

0x0

Reserved

R/W

0x1

0 : Disable LVDS interface

1 : Enable LVDS interface

Note 1: Before altering other LVDS registers, you must clear

LVDS_EN. When LVDS_EN is 0, the LVDS interface block is held in

reset and the outputs are powered down. The clocks are gated off to

save power. The frame counter is also held in reset, so SYSREF will

not align the frame counter.

Note 2: Always set CAL_EN before setting LVDS_EN.

Note 3: Always clear LVDS_EN before clearing CAL_EN.

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7.6.1.49 LMODE Register (Address = 0x201) [reset = 0x01]

LMODE is shown in 图7-55 and described in 表7-68.

Return to Summary Table.

LVDS Mode register (default: 0x01). This register is used to define the configuration of the LVDS interface.

LVDS_EN must be 0 before making any changes to this register. Additionally, CAL_EN must be 0 before

changing DES_EN.

图7-55. LMODE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LWIDTH

R/W-0x0

RESERVED

R/W-0x0

DES_EN

R/W-0x0

LALIGNED

R/W-0x0

LDEMUX

R/W-0x1

表7-68. LMODE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-4

RESERVED

LWIDTH

R/W

0x0

Reserved

R/W

0x0

Specifies the sample width for the LVDS output interface.

0 : 12-bit sample width (default)

1 : 11-bit sample width

2 : 10-bit sample width

3 : 8-bit sample width

3

2

RESERVED

DES_EN

R/W

0x0

Reserved

0 : Disable DES mode (enable dual channel mode)

1 : Enable DES mode (enable single channel mode)

CAL_EN must be 0 before changing DES_EN.

1

0

LALIGNED

LDEMUX

R/W

0x0

0x1

0 : The LVDS buses are staggered for optimized switching noise and

latency.

1 : The LVDS buses are aligned for simplified timing.

0 : Demux-by-1, uses 2 LVDS buses total

1 : Demux-by-2, uses 4 LVDS buses total

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7.6.1.50 LFRAME Register (Address = 0x202) [reset = 0x80]

LFRAME is shown in 图7-56 and described in 表7-69.

Return to Summary Table.

LVDS Frame Length register (default: 0x80) (128 decimal). This register sets the length of the frame and

subsequently the period of the strobe signal. Only change this register when LVDS_EN = 0.

图7-56. LFRAME Register

7

6

5

4

3

2

1

0

LFRAME

R/W-0x80

表7-69. LFRAME Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

LFRAME

R/W

0x80

Defines the number of UIs in each LVDS frame. Any multiple of 4

from 4 to 128 is supported. All other values are unsupported.

When LDEMUX=0, one UI is one CLK± cycle.

When LDEMUX=1, one UI is two CLK± cycles.

Note: Setting LFRAME to 4 is not recommended, as it may be

difficult to achieve deterministic latency over all process, voltage, and

temperature conditions. The propagation delay variation may be

larger than the frame period.

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7.6.1.51 LSYNC_N Register (Address = 0x203) [reset = 0x01]

LSYNC_N is shown in 图7-57 and described in 表7-70.

Return to Summary Table.

LVDS Manual Sync Request register (default: 0x01). This register can be used as a software replacement for the

LVDS SYNC signal.

图7-57. LSYNC_N Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LSYNC_N

R/W-0x1

表7-70. LSYNC_N Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

LSYNC_N

R/W

0x0

Reserved

R/W

0x1

Set this bit to 0 to request LVDS synchronization (equivalent to the

hardware SYNC signal being asserted, as selected by SYNC_SEL).

For normal operation, leave this bit set to 1.

Note: The LSYNC_N register can always generate a synchronization

request, regardless of the SYNC_SEL setting in the LCTRL register.

However, if the selected sync pin is stuck low, the synchronization

request cannot be de-asserted unless SYNC_SEL=2.

7.6.1.52 LCTRL Register (Address = 0x204) [reset = 0x02]

LCTRL is shown in 图7-58 and described in 表7-71.

Return to Summary Table.

LVDS Control register (default: 0x02). This register is used to configure aspects of the LVDS interface including

scrambling, hardware SYNC input and the output format. Only change this register when LVDS_EN = 0.

图7-58. LCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SCR

SYNC_SEL

R/W-0x0

SFORMAT

R/W-0x1

RESERVED

R/W-0x0

表7-71. LCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4

RESERVED

SCR

R/W

0x0

Reserved

R/W

0x0

When set, all LVDS data and strobes are scrambled. This also

includes the part-time strobes or timestamp signals (since they are

output on the data lanes). See the 节7.4.5.5 section.

3-2

1

SYNC_SEL

SFORMAT

0 : Use the SYNC_SE input for SYNC function (default)

1 : Use the TMSTP± input for SYNC function. also set

TMSTP_RECV_EN to use the differential TMSTP± input.

2 : Do not use any SYNC input pin, set if using LSYNC_N.

R/W

0x1

Output sample format for LVDS output samples

0 : Offset binary

1 : Signed 2’s complement (default)

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表7-71. LCTRL Register Field Descriptions (continued)

Bit

Field

RESERVED

Type

Reset

Description

0

R/W

0x0

Reserved

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7.6.1.53 PAT_SEL Register (Address = 0x205) [reset = 0x02]

PAT_SEL is shown in 图7-59 and described in 表7-72.

Return to Summary Table.

LVDS Pattern Control register (default: 0x02). This register controls the output data or pattern used during active

mode ( SYNC de-asserted) and sync mode ( SYNC asserted). During normal operation, the active pattern

should be set to the ADC output data and the SYNC pattern can be set to the mode used by the receiver for

synchronizing the interface. The input used for SYNC is chosen by SYNC_SEL.

图7-59. PAT_SEL Register

7

6

5

4

3

2

1

0

ACT_PAT

R/W-0x0

SYNC_PAT

R/W-0x2

表7-72. PAT_SEL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

ACT_PAT

R/W

0x0

This selects the output pattern that is generated when the SYNC

signal is de-asserted.

0: ADC output data

1: All LVDS lanes output the user-defined pattern (see UPAT

registers)

2-15: Reserved

3-0

SYNC_PAT

R/W

0x2

This selects the output pattern that is generated when the SYNC

signal is asserted.

0: Reserved

1: All LVDS lanes output the user-defined pattern (see UPAT

registers)

2: Frame strobe is transmitted on the LSB of the output samples

only. The other bits transmit data based on ACT_PAT.

3: The frame strobe is transmitted on all active LVDS data lanes and

strobes.

4-15: Reserved

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7.6.1.54 LCS_EN Register (Address = 0x206) [reset = 0xFF]

LCS_EN is shown in 图7-60 and described in 表7-73.

Return to Summary Table.

LVDS Clock and Strobe Enables register (default: 0xFF). Use these registers to enable or disable specific LVDS

output clocks (DxCLK±) and frame strobes (DxSTB±) if the receiver will not use them. If an entire LVDS bus is

disabled (because of PD_CH or LDEMUX) then its associated clock and frame strobe are disabled automatically,

regardless of this register. Note: Only change this register when LVDS_EN = 0.

图7-60. LCS_EN Register

7

6

5

4

3

2

1

0

DDSTB_EN

R/W-0x1

DCSTB_EN

R/W-0x1

DBSTB_EN

R/W-0x1

DASTB_EN

R/W-0x1

DDCLK_EN

R/W-0x1

DCCLK_EN

R/W-0x1

DBCLK_EN

R/W-0x1

DACLK_EN

R/W-0x1

表7-73. LCS_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DDSTB_EN

DCSTB_EN

DBSTB_EN

DASTB_EN

DDCLK_EN

DCCLK_EN

DBCLK_EN

DACLK_EN

R/W

0x1

Enable DDSTB± output

Enable DCSTB± output

Enable DBSTB± output

Enable DASTB± output

Enable DDCLK± output

Enable DCCLK± output

Enable DBCLK± output

Enable DACLK± output

6

5

4

3

2

1

0

R/W

0x1

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7.6.1.55 LVDS_STATUS Register (Address = 0x208) [reset = Undefined]

LVDS_STATUS is shown in 图7-61 and described in 表7-74.

Return to Summary Table.

System Status register (default: undefined). This register returns status bits for the device including SYNC status

for the LVDS interface and internal clock status.

图7-61. LVDS_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SYNC_STATUS

R/W-Undefined

REALIGNED

R/W-Undefined

ALIGNED

RESERVED

R/W-0x0

R/W-Undefined

表7-74. LVDS_STATUS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

RESERVED

SYNC_STATUS

0x0

Reserved

Undefined

Returns the instantaneous state of the LVDS interface SYNC signal

( SYNC_SE or TMSTP±).

0 : SYNC asserted

1 : SYNC de-asserted

4

3

REALIGNED

ALIGNED

R/W

Undefined

When high, indicates that SYSREF realigned internal clocks.

REALIGNED_ALM should be used for monitoring of realignment

events instead of this bit. Writing a 1 to this bit will clear it, but will not

affect the REALIGNED_ALM bit.

When high, indicates that internal clock phases have been

established by SYSREF. Any SYSREF rising edge that is processed

after enabling the LVDS system will set this bit. This bit can be

monitored during startup to verify that SYSREF has been processed

before continuing system initialization. Writing a 1 to this bit will clear

it and the next SYSREF event will set it again.

2-0

RESERVED

R/W

0x0

Reserved

7.6.1.56 PD_CH Register (Address = 0x209) [reset = 0x00]

PD_CH is shown in 图7-62 and described in 表7-75.

Return to Summary Table.

ADC Channel Power Down (default: 0x00). This register allows individual channels to be powered down.

LVDS_EN and CAL_EN must be set to 0 before changing PD_CH.

图7-62. PD_CH Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PD_BCH

R/W-0x0

PD_ACH

R/W-0x0

表7-75. PD_CH Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

1

RESERVED

PD_BCH

R/W

0x0

Reserved

R/W

0x0

When set, the “B”ADC channel is powered down.

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表7-75. PD_CH Register Field Descriptions (continued)

Bit

Field

PD_ACH

Type

Reset

Description

0

R/W

0x0

When set, the “A”ADC channel is powered down.

Important notes:

LVDS_EN and CAL_EN must be set to 0 before changing PD_CH.

PD_CH disables the LVDS lanes (Dx[11:0], DxSTB, DxCLK) for the

powered down channel.

To power down both ADC channels, use MODE or the PD pin.

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7.6.1.57 OVR_T0 Register (Address = 0x211) [reset = 0xF2]

OVR_T0 is shown in 图7-63 and described in 表7-76.

Return to Summary Table.

Overrange Threshold 0 register (default: 0xF2). This register sets threshold 0 for ADC overrange detection.

图7-63. OVR_T0 Register

7

6

5

4

3

2

1

0

OVR_T0

R/W-0xF2

表7-76. OVR_T0 Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

OVR_T0

R/W

0xF2

This parameter defines the absolute sample level that causes OVA0

or OVB0 to be set. The detection level in dBFS (peak) is

20log10(OVR_T0/256) (default: 0xF2 = 242 –> -0.5dBFS)

7.6.1.58 OVR_T1 Register (Address = 0x212) [reset = 0xAB]

OVR_T1 is shown in 图7-64 and described in 表7-77.

Return to Summary Table.

Overrange Threshold 1 register (default: 0xAB). This register sets threshold 1 for ADC overrange detection.

图7-64. OVR_T1 Register

7

6

5

4

3

2

1

0

OVR_T1

R/W-0xAB

表7-77. OVR_T1 Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

OVR_T1

R/W

0xAB

This parameter defines the absolute sample level that causes OVA1

or OVB1 to be set. The detection level in dBFS (peak) is

20log10(OVR_T1/256) (default: 0xAB = 171 –> -3.5dBFS)

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7.6.1.59 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in 图7-65 and described in 表7-78.

Return to Summary Table.

Overrange Enable/Hold Off register (default: 0x07). This register enables overrange detection and sets the

output pulse duration for an overrange event. The maximum overrange pulse duration is recommended to avoid

excess switching noise.

图7-65. OVR_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OVR_EN

R/W-0x0

OVR_N

R/W-0x7

表7-78. OVR_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

RESERVED

OVR_EN

R/W

0x0

Reserved

R/W

0x0

0x7

ORA0, ORA1, ORB0 and ORB1 outputs pins are enabled and output

the overrange status when this bit is set high. The outputs are held

low when this bit is set low.

2-0

OVR_N

Program this register to adjust the pulse length for the ORA0, ORA1

and ORB0, ORB1 outputs.

The minimum pulse duration of the overrange outputs is 8 × 2^OVR_N

CLK± cycles.

7.6.1.60 SPIN_ID Register (Address = 0x297) [reset = 0x00]

SPIN_ID is shown in 图7-66 and described in 表7-79.

Return to Summary Table.

Chip Spin Identifier register (default from fuse ROM, read-only). This register returns the spin identification

number of the device.

图7-66. SPIN_ID Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SPIN_ID

R/W-0x0

表7-79. SPIN_ID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

SPIN_ID

R/W

0x0

Reserved

R/W

0x0

Returns 0 to indicate that this device is ADC12DL3200.

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7.6.1.61 SRC_EN Register (Address = 0x2B0) [reset = 0x00]

SRC_EN is shown in 图7-67 and described in 表7-80.

Return to Summary Table.

SYSREF Calibration Enable register (default: 0x00). This register starts the SYSREF calibration process.

图7-67. SRC_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SRC_EN

R/W-0x0

表7-80. SRC_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

SRC_EN

R/W

0x0

Reserved

R/W

0x0

0 : SYSREF calibration disabled (default). Use the TAD register to

manually control the t_ADAdjust setting and adjust the CLK± aperture

delay.

1: SYSREF calibration enabled. The CLK± delay is automatically

calibrated. The TAD register is ignored. A 0-to-1 transition on

SRC_EN starts the SYSREF calibration sequence. Program

SRC_CFG before setting SRC_EN. Ensure that ADC calibration is

not running before setting SRC_EN.

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7.6.1.62 SRC_CFG Register (Address = 0x2B1) [reset = 0x05]

SRC_CFG is shown in 图7-68 and described in 表7-81.

Return to Summary Table.

SYSREF Calibration Configuration register (default: 0x05). This register determines the amount of averaging

performed for automatic SYSREF calibration and sets the maximum supported SYSREF cycle. The total

duration of SYSREF calibration will be no longer than: TSYSREFCAL (in CLK± cycles) = 256 * 19 * 4 *

(SRC_AVG + SRC_HDUR + 2).

图7-68. SRC_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SRC_AVG

R/W-0x1

SRC_HDUR

R-0x1

表7-81. SRC_CFG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-4

3-2

RESERVED

SRC_AVG

0x0

Reserved

0x1

Specifies the amount of averaging used for SYSREF Calibration.

Larger values will increase calibration time and reduce the variance

of the calibrated value.

0: 4 high-speed accumulations for each SYSREF measurement

1: 16 high-speed accumulations for each SYSREF measurement

2: 64 high-speed accumulations for each SYSREF measurement

3: 256 high-speed accumulations for each SYSREF measurement

1-0

SRC_HDUR

R/W

0x1

Specifies the duration of each high-speed accumulation for SYSREF

Calibration. If the SYSREF period exceeds the supported value,

calibration will fail. Larger values will increase calibration time and

support longer SYSREF periods. For a given SYSREF period, larger

values will also reduce the variance of the calibrated value.

0: 4 cycles per accumulation, supporting SYSREF periods of up to

85 CLK± cycles

1: 16 cycles per accumulation, supporting SYSREF periods of up to

1100 CLK± cycles

2: 64 cycles per accumulation, supporting SYSREF periods of up to

5200 CLK± cycles

3: 256 cycles per accumulation, supporting SYSREF periods of up to

21580 CLK± cycles

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7.6.1.63 SRC_STATUS Register (Address = 0x2B2) [reset = Undefined]

SRC_STATUS is shown in 图7-69 and described in 表7-82.

Return to Summary Table.

SYSREF Calibration Status register (read-only, default: undefined). This register indicates that the SYSREF

calibration process has completed and outputs the result of the SYSREF calibration process.

图7-69. SRC_STATUS Register

23

15

7

22

14

6

21

13

5

20

19

18

10

2

17

16

SRC_TAD[16]

R-Undefined

8

RESERVED

R-Undefined

SRC_DONE

R-Undefined

9

12

11

SRC_TAD[15:8]

R-Undefined

4

3

1

0

SRC_TAD[7:0]

R-Undefined

表7-82. SRC_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

23-18

17

RESERVED

SRC_DONE

R/W

0x0

Reserved

R/W

0x0

This bit returns ‘1’when SRC_EN=1 and SYSREF Calibration

has been completed.

16-0

SRC_TAD

R/W

0x0

This field returns the value for t _ADAdjust computed by SYSREF

Calibration. It is only valid if SRC_DONE=1. SRC_TAD[16] indicates

if CLK± has been inverted. SRC_TAD[15:8] indicates the coarse

delay adjustment.

SRC_TAD[7:0] indicates the fine delay adjustment. SRC_TAD can be

read out and manually written to the TAD register during subsequent

boot cycles for repeatability.

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7.6.1.64 TAD Register (Address = 0x2B5-2B7) [reset = 0x000000]

TAD is shown in 图7-70 and described in 表7-83.

Return to Summary Table.

CLK± Timing Adjust register (default: 0x00). This register sets the t_ADAdjust delay when automatic SYRSEF

calibration is not used.

图7-70. TAD Register

23

15

7

22

14

6

21

13

5

20

19

11

3

18

10

2

17

9

16

TAD[16]

R-0x0

8

RESERVED

R-Undefined

12

TAD[15:8]

R-0x00

4

1

0

TAD[7:0]

R-0x00

表7-83. TAD Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

23-17

16-0

RESERVED

TAD

0x0

Reserved

0x0

This register controls t_ADAdjust when SRC_EN=0. Use this register

to manually control the CLK± inversion and delay when SYSREF

Calibration is disabled.

TAD[16] inverts CLK± when set. TAD[15:8] controls the coarse delay

adjustment. TAD[7:0] controls the fine delay adjustment.

If ADC calibration is enabled (CAL_EN=1), or the LVDS interface is

enabled (LVDS_EN=1), the following rules must be obeyed to avoid

clock glitches and unpredictable behavior:

Do not change TAD[16]. CAL_EN and LVDS_EN must be set to 0

before changing TAD[16].

TAD[15:8] must be increased or decreased gradually (no more than

4 codes at a time). This rule can be obeyed manually via SPI writes

or by setting TAD_RAMP_EN.

TAD[7:0] may be changed to any value at any time since its

resolution is too fine to cause clock glitches.

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7.6.1.65 TAD_RAMP Register (Address = 0x2B8) [reset = 0x00]

TAD_RAMP is shown in 图7-71 and described in 表7-84.

Return to Summary Table.

CLK± Timing Adjust Ramp Control register (default: 0x00). This register enables the t_ADadjust ramping feature

and sets the ramp rate.

图7-71. TAD_RAMP Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TAD_RAMP_RATE

R/W-0x0

TAD_RAMP_EN

R/W-0x0

表7-84. TAD_RAMP Register Field Descriptions

Bit

Field

Type

Reset

Description

7-2

RESERVED

R/W

0x0

Reserved

1

TAD_RAMP_RATE

R/W

0x0

Specify the ramp rate for t_ADadjust when the TAD[15:8] register is

written while TAD_RAMP_EN is 1.

0 : t_ADadjust ramps up or down one code per 256 CLK± cycles.

1 : t_ADadjust ramps up or down four codes per 256 CLK± cycles.

0

TAD_RAMP_EN

R/W

0x0

TAD ramp enable. Set this bit if ramping of the coarse t_ADadjust is

desired.

0 : After writing the TAD[15:8] register, t_ADadjust is updated fully

within 1024 CLK± cycles (ramp feature disabled).

1 : After writing the TAD[15:8] register, t_ADadjust ramps up or down

gradually until it matches the TAD[15:8] register.

When TAD_RAMP_EN is 1, and the user writes the TAD[15:8]

register, a digital counter will automatically ramp t_ADadjust up or

down until it matches the TAD[15:8] register value. This ensures that

the coarse delay changes gradually and does not cause glitches in

the delayed CLK± waveform.

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7.6.1.66 ALARM Register (Address = 0x2C0) [reset = Undefined]

ALARM is shown in 图7-72 and described in 表7-85.

Return to Summary Table.

Alarm Interrupt register (read-only). This register indicates if any unmasked alarm in has been triggered in the

ALM_STATUS register.

图7-72. ALARM Register

7

6

5

4

3

2

1

0

RESERVED

R-Undefined

ALARM

R-Undefined

表7-85. ALARM Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RESERVED

ALARM

R

Undefined

Reserved

R

Undefined

This bit returns a ‘1’whenever any unmasked alarm is set in the

ALM_STATUS register. Use ALM_MASK to mask (disable) individual

alarms.

CAL_STATUS_SEL can be used to drive the ALARM bit onto the

CAL_STAT pin to provide a hardware alarm interrupt signal.

7.6.1.67 ALM_STATUS Register (Address = 0x2C1) [reset = 0x05]

ALM_STATUS is shown in 图7-73 and described in 表7-86.

Return to Summary Table.

Alarm Status register (default: 0x05, write to clear). This register indicates if the individual alarms have been

triggered.

图7-73. ALM_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

REALIGNED_ALM

R/W-0x1

RESERVED

R/W-0x0

CLK_ALM

R/W-0x1

表7-86. ALM_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

RESERVED

R/W

0x0

Reserved

2

REALIGNED_ALM

R/W

0x1

Realigned Alarm: This bit is set whenever SYSREF causes the

internal clocks (including the frame counter) to be realigned to a new

phase. Write a ‘1’to clear this bit.

1

0

RESERVED

CLK_ALM

R/W

0x0

0x1

Reserved

Clock Alarm: This bit can be used to detect an upset to the internal

clocks. This bit is set whenever the internal clock dividers for the A

and B channels do not match. Write a ‘1’to clear this bit. Refer to

Alarm Monitoring for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to

‘1.’

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7.6.1.68 ALM_MASK Register (Address = 0x2C2) [reset = 0x05]

ALM_MASK is shown in 图7-74 and described in 表7-87.

Return to Summary Table.

Alarm Mask register (default: 0x05). This register is used to mask out alarms that should not trigger the ALARM

interrupt.

图7-74. ALM_MASK Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MASK_REALIGNED_ALM

R/W-0x1

RESERVED

R/W-0x0

MASK_CLK_ALM

R/W-0x1

表7-87. ALM_MASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7-3

RESERVED

R/W

0x0

Reserved

2

MASK_REALIGNED_ALM R/W

0x1

When set, REALIGNED_ALM is masked and will not impact the

ALARM register bit.

1

0

RESERVED

R/W

0x0

0x1

Reserved

MASK_CLK_ALM

When set, CLK_ALM is masked and will not impact the ALARM

register bit.

7.6.1.69 TADJ_A Register (Address = 0x310) [reset = Undefined]

TADJ_A is shown in 图7-75 and described in 表7-88.

Return to Summary Table.

Timing Adjust for A-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim.

Refer to the Trimming section for more information.

图7-75. TADJ_A Register

7

6

5

4

3

2

1

0

TADJ_A

R/W-Undefined

表7-88. TADJ_A Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_A

R/W

Undefined

This register (and other TADJ* registers that follow it) are used to

adjust the sampling instant of each ADC core. Different TADJ

registers apply to different ADCs under different modes of operation.

The default values for all TADJ* registers are loaded from the fuse

ROM. The factory trimmed values can be read out and adjusted as

required.

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7.6.1.70 TADJ_B Register (Address = 0x313) [reset = Undefined]

TADJ_B is shown in 图7-76 and described in 表7-89.

Return to Summary Table.

Timing Adjust for B-ADC, Dual Mode register (default from fuse ROM). This register is used for ADC timing trim.

Refer to the Trimming section for more information.

图7-76. TADJ_B Register

7

6

5

4

3

2

1

0

TADJ_B

R/W-Undefined

表7-89. TADJ_B Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_B

R/W

Undefined

See TADJ_A register for description.

7.6.1.71 TADJ_A_FG90_VINA Register (Address = 0x314) [reset = Undefined]

TADJ_A_FG90_VINA is shown in 图7-77 and described in 表7-90.

Return to Summary Table.

Timing Adjust for A-ADC, DES, Foreground Calibration, INA± register (default from fuse ROM). This register is

used for ADC timing trim. Refer to the Trimming section for more information.

图7-77. TADJ_A_FG90_VINA Register

7

6

5

4

3

2

1

0

TADJ_A_FG90_VINA

R/W-Undefined

表7-90. TADJ_A_FG90_VINA Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_A_FG90_VINA

R/W

Undefined

See TADJ_A register for description.

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7.6.1.72 TADJ_B_FG0_VINA Register (Address = 0x315) [reset = Undefined]

TADJ_B_FG0_VINA is shown in 图7-78 and described in 表7-91.

Return to Summary Table.

Timing Adjust for B-ADC, DES, Foreground Calibration, INA± regsiter (default from fuse ROM). This register is

used for ADC timing trim. Refer to the Trimming section for more information.

图7-78. TADJ_B_FG0_VINA Register

7

6

5

4

3

2

1

0

TADJ_B_FG0_VINA

R/W-Undefined

表7-91. TADJ_B_FG0_VINA Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_B_FG0_VINA

R/W

Undefined

See TADJ_A register for description.

7.6.1.73 TADJ_A_FG90_VINB Register (Address = 0x31A) [reset = Undefined]

TADJ_A_FG90_VINB is shown in 图7-79 and described in 表7-92.

Return to Summary Table.

Timing Adjust for A-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is

used for ADC timing trim. Refer to the Trimming section for more information.

图7-79. TADJ_A_FG90_VINB Register

7

6

5

4

3

2

1

0

TADJ_A_FG90_VINB

R/W-Undefined

表7-92. TADJ_A_FG90_VINB Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_A_FG90_VINB

R/W

Undefined

See TADJ_A register for description.

English Data Sheet: SLVSDR3

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7.6.1.74 TADJ_B_FG0_VINB Register (Address = 0x31B) [reset = 0x0]

TADJ_B_FG0_VINB is shown in 图7-80 and described in 表7-93.

Return to Summary Table.

Timing Adjust for B-ADC, DES, Foreground Calibration, INB± register (default from fuse ROM). This register is

used for ADC timing trim. Refer to the Trimming section for more information.

图7-80. TADJ_B_FG0_VINB Register

7

6

5

4

3

2

1

0

TADJ_B_FG0_VINB

R/W-Undefined

表7-93. TADJ_B_FG0_VINB Register Field Descriptions

Bit

7-0

Field

Type

Reset

Description

TADJ_B_FG0_VINB

R/W

Undefined

See TADJ_A register for description.

7.6.1.75 OADJ_A_FG0_VINA Register (Address = 0x344) [reset = Undefined]

OADJ_A_FG0_VINA is shown in 图7-81 and described in 表7-94.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INA± register (default from fuse ROM). This

register is used for ADC core offset trimming. See the Trimming section for more details.

图7-81. OADJ_A_FG0_VINA Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_A_FG0_VINA

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_A_FG0_VINA

R/W-Undefined

表7-94. OADJ_A_FG0_VINA Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_A_FG0_VINA

R/W

Undefined

Offset adjustment value applied to A-ADC when it samples INA±

using 0° clock phase and foreground calibration is enabled.

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7.6.1.76 OADJ_A_FG0_VINB Register (Address = 0x346) [reset = Undefined]

OADJ_A_FG0_VINB is shown in 图7-82 and described in 表7-95.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 0° Clock / INB± register (default from fuse ROM). This

register is used for ADC core offset trimming. See the Trimming section for more details.

图7-82. OADJ_A_FG0_VINB Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_A_FG_VINB

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_A_FG_VINB

R/W-Undefined

表7-95. OADJ_A_FG0_VINB Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_A_FG0_VINB

R/W

Undefined

Offset adjustment value applied to A-ADC when it samples INB±

using 0° clock phase and foreground calibration is enabled.

7.6.1.77 OADJ_A_FG90_VINA Register (Address = 0x348) [reset = Undefined]

OADJ_A_FG90_VINA is shown in 图7-83 and described in 表7-96.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INA± register (default from fuse ROM). This

register is used for ADC core offset trimming. See the Trimming section for more details.

图7-83. OADJ_A_FG90_VINA Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_A_FG90_VINA

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_A_FG90_VINA

R/W-Undefined

表7-96. OADJ_A_FG90_VINA Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_A_FG90_VINA

R/W

Undefined

Offset adjustment value applied to A-ADC when it samples INA±

using 90° clock phase and foreground calibration is enabled.

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7.6.1.78 OADJ_A_FG90_VINB Register (Address = 0x34A) [reset = Undefined]

OADJ_A_FG90_VINB is shown in 图7-84 and described in 表7-97.

Return to Summary Table.

Offset Adjustment for A-ADC / Foreground Calibration / 90° Clock / INB± register (default from fuse ROM). This

register is used for ADC core offset trimming. See the Trimming section for more details.

图7-84. OADJ_A_FG90_VINB Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_A_FG90_VINB

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_A_FG90_VINB

R/W-Undefined

表7-97. OADJ_A_FG90_VINB Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_A_FG90_VINB

R/W

Undefined

Offset adjustment value applied to A-ADC when it samples INB±

using 90° clock phase and foreground calibration is enabled.

7.6.1.79 OADJ_B_FG0_VINA Register (Address = 0x34C) [reset = Undefined]

OADJ_B_FG0_VINA is shown in 图7-85 and described in 表7-98.

Return to Summary Table.

Offset Adjustment for B-ADC / Foreground Calibration / INA± register (default from fuse ROM). This register is

used for ADC core offset trimming. See the Trimming section for more details.

图7-85. OADJ_B_FG0_VINA Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_B_FG0_VINA

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_B_FG0_VINA

R/W-Undefined

表7-98. OADJ_B_FG0_VINA Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_B_FG0_VINA

R/W

Undefined

Offset adjustment value applied to B-ADC when it samples INA±

using 0° clock phase and foreground calibration is enabled.

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7.6.1.80 OADJ_B_FG0_VINB Register (Address = 0x34E) [reset = Undefined]

OADJ_B_FG0_VINB is shown in 图7-86 and described in 表7-99.

Return to Summary Table.

Offset Adjustment for B-ADC / Foreground Calibration / INB± register (default from fuse ROM). This register is

used for ADC core offset trimming. See the Trimming section for more details.

图7-86. OADJ_B_FG0_VINB Register

15

14

13

12

11

10

9

8

RESERVED

R/W-Undefined

OADJ_B_FG0_VINB

R/W-Undefined

7

6

5

4

3

2

1

0

OADJ_B_FG0_VINB

R/W-Undefined

表7-99. OADJ_B_FG0_VINB Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

11-0

RESERVED

R/W

Undefined

Reserved

OADJ_B_FG0_VINB

R/W

Undefined

Offset adjustment value applied to B-ADC when it samples INB±

using 0° clock phase and foreground calibration is enabled.

7.6.1.81 GAIN_B0 Register (Address = 0x360) [reset = Undefined]

GAIN_B0 is shown in 图7-87 and described in 表7-100.

Return to Summary Table.

Fine Gain Adjust for Bank 0 register (default from fuse ROM). This register adjusts the gain of the Bank 0 ADC.

图7-87. GAIN_B0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-Undefined

GAIN_B0

R/W-Undefined

表7-100. GAIN_B0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

GAIN_B0

R/W

Undefined

Reserved

R/W

Undefined

Fine gain adjustment for bank 0.

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7.6.1.82 GAIN_B1 Register (Address = 0x361) [reset = Undefined]

GAIN_B1 is shown in 图7-88 and described in 表7-101.

Return to Summary Table.

Fine Gain Adjust for Bank 1 register (default from fuse ROM). This register adjusts the gain of the Bank 1 ADC.

图7-88. GAIN_B1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-Undefined

GAIN_B1

R/W-Undefined

表7-101. GAIN_B1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

GAIN_B1

R/W

Undefined

Reserved

R/W

Undefined

Fine gain adjustment for bank 1.

7.6.1.83 GAIN_B4 Register (Address = 0x364) [reset = Undefined]

GAIN_B4 is shown in 图7-89 and described in 表7-102.

Return to Summary Table.

Fine Gain Adjust for Bank 4 register (default from fuse ROM). This register adjusts the gain of the Bank 4 ADC.

图7-89. GAIN_B4 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-Undefined

GAIN_B4

R/W-Undefined

表7-102. GAIN_B4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

GAIN_B4

R/W

Undefined

Reserved

R/W

Undefined

Fine gain adjustment for bank 4.

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7.6.1.84 GAIN_B5 Register (Address = 0x365) [reset = Undefined]

GAIN_B5 is shown in 图7-90 and described in 表7-103.

Return to Summary Table.

Fine Gain Adjust for Bank 5 register (default from fuse ROM). This register adjusts the gain of the Bank 5 ADC.

图7-90. GAIN_B5 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-Undefined

GAIN_B5

R/W-Undefined

表7-103. GAIN_B5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RESERVED

GAIN_B5

R/W

Undefined

Reserved

R/W

Undefined

Fine gain adjustment for bank 5.

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Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

8.1 Application Information

The ADC12DL3200 can be used in a wide range of applications including radar, electronic warfare, satellite

communications, test equipment (communications testers and oscilloscopes) and software-defined radios

(SDRs). The wide input bandwidth enables direct RF sampling to at least 10 GHz and the high sampling rate

allows signal bandwidths of greater than 3 GHz. The ADC12DL3200 can also be DC-coupled to meet the needs

of oscilloscopes or wideband digitizers. The 节8.2 section describes two configurations that meet the needs of a

number of these applications.

8.2 Typical Applications

8.2.1 Wideband RF Sampling Receiver

This section demonstrates the use of the ADC12DL3200 as a wideband RF sampling receiver. The solution is

flexible and can be used as either a 2-channel receiver (such as a diversity receiver) or as a single channel

allowing double the signal bandwidth. The ADC is driven by single-ended RF amplifiers and the conversion to

differential signaling is achieved by a transformer (balun). The ADC12DL3200 uses a low-latency LVDS interface

in order to achieve quick event detection for latency-sensitive applications.

Up to 56 LVDS

pairs

LNA

Anti-Alias BPF

ADC A

LVDS

SYNC~

LNA

Anti-Alias BPF

ADC B

LVDS

FPGA or ASIC

Clocking

Subsystem

User Control

Logic

SPI

LMK04832

Device Clock

÷

SYSREF

10 MHz

Reference

N÷

R÷

Device Clock

SYSREF

图8-1. Typical Configuration for Wideband RF Sampling

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8.2.1.1 Design Requirements

8.2.1.1.1 Input Signal Path

Use appropriate band-limiting filters to reject unwanted frequencies in the input signal path.

A 1:2 balun transformer is needed to convert the 50-Ω, single-ended signal to 100-Ω differential for input to the

ADC. The balun outputs can be either AC-coupled, or directly connected to the ADC differential inputs, which are

terminated internally to GND.

Drivers must be selected to provide any needed signal gain and that have the necessary bandwidth capabilities.

In general, baluns must be selected to cover the needed frequency range, have a 1:2 impedance ratio, and have

acceptable gain and phase balance over the frequency range of interest. Mount baluns with poor differential

output return loss as close to the ADC inputs as possible to avoid ripples in the frequency response at high input

frequencies. Resistive attenuators (Pi- or T-type) can also help dampen ripples caused by poor return loss. 表

8-1 lists a number of recommended baluns for different frequency ranges.

表8-1. Recommended Baluns

PART NUMBER

BAL-0009SMG

BAL-0208SMG

TCM2-43X+

MANUFACTURER⁽¹⁾

Marki Microwave

Mini-Circuits

MINIMUM FREQUENCY (MHz) MAXIMUM FREQUENCY (MHz)

0.5

2000

10

9000

8000

4000

3000

TCM2-33WX+

B0430J50100AHF

Mini-Circuits

10

Anaren

400

(1) See the 节8 section.

8.2.1.1.2 Clocking

The ADC12DL3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock

source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended

clock synthesizers include the LMX2594, LMX2592, and LMX2582.

For multi-device synchronization the data converter system (ADC plus FPGA) requires a SYSREF signal in

addition to the device (sampling) clock, which is similar to that used for JESD204B converters. Therefore,

JESD204B-compatible clock devices are a good choice for clocking the ADC12DL3200. The LMK04832,

LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending on the ADC

clock frequency and jitter requirements, this device can also be used as the system clock synthesizer or as a

device clock and SYSREF distribution device when multiple ADC12DL3200 devices are used in a system.

8.2.1.2 Detailed Design Procedure

Certain component values used in conjunction with the ADC12DL3200 must be calculated based on system

parameters. Those items are covered in this section.

8.2.1.2.1 Calculating Values of AC-Coupling Capacitors

AC-coupling capacitors are used in the input CLK± pair. The capacitor values must be large enough to address

the lowest frequency signals of interest, but not so large as to cause excessively long startup biasing times, or

unwanted parasitic inductance.

The minimum capacitor value can be calculated based on the lowest frequency signal that is transferred through

the capacitor. Given a 50-Ω, single-ended clock or data path impedance, good practice is to set the capacitor

impedance to be less than 1 Ωat the lowest frequency of interest. This setting ensures minimal impact on signal

level at that frequency. For the CLK± path, the minimum-rated clock frequency is 800 MHz. Therefore, the

minimum capacitor value can be calculated from:

Z_C= 1/ 2 ´ p ´ ¦

(

´ C

)

CLK

(3)

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Setting Z_c= 1 Ωand rearranging gives:

C = 1/ 2 ´ p ´ 800 MHz ´ 1 W = 199 pF

)

(

(4)

Therefore, a capacitance value of at least 199 pF is needed to provide the low-frequency response for the CLK±

path. If the minimum clock frequency is higher than 800 MHz, this calculation can be revisited for that frequency.

Capacitors must also be selected for good response at high frequencies, usually identified by low inductance or

high self-resonance frequency, and with dimensions that match the high-frequency signal traces they are

connected to. Capacitors of the 0201 size are frequently well-suited to these applications.

8.2.1.3 Application Curves

The ADC12DL3200 can be used in either dual-channel mode or single-channel mode to suit different

applications and system architectures. 图8-2 and show operation with a 497.77-MHz input signal in the following

configurations:

• 6.4 GSPS, single-channel mode (DES_EN = 1), four LVDS buses (LDEMUX = 1), and staggered output data

(LALIGNED = 0)

• 3.2 GSPS, dual-channel mode (DES_EN = 0), four LVDS buses (LDEMUX = 1), and staggered output data

(LALIGNED = 0)

图8-2. FFT for 497.77-MHz Input Signal in Single-

图8-3. FFT for 497.77-MHz Input Signal in Dual-

Channel Mode at 6.4 GSPS

Channel Mode at 3.2 GSPS

8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope

This section demonstrates the use of the ADC12DL3200 in a reconfigurable oscilloscope. The oscilloscope can

operate as a dual-channel oscilloscope running at 2.5 GSPS or can be reconfigured through SPI programming

as a single-channel, 5-GSPS oscilloscope. This reconfigurable setup allows tradeoffs between the number of

channels and the sampling rate of the oscilloscope as needed without changing the hardware. Set the input

bandwidth to the desired maximum signal bandwidth through the use of an antialiasing, low-pass filter. Digital

filtering can then be used to reconfigure the analog bandwidth as required. For instance, the maximum

bandwidth can be set to 1 GHz for use during pulsed transient detection and then reconfigured to 100 MHz

through digital filtering for low-noise, power-supply ripple observation. 图 8-4 shows the application block

diagram for a reconfigurable oscilloscope.

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Up to 56 LVDS

pairs

LMH5401

LMH6401

Anti-Alias LPF

Front Panel

Channel A

Programmable

Termination

ADC A

LVDS

DC Offset

Adjustment

DAC

SYNC~

LMH6559

OPA703

DAC8560

LMH6401

LMH5401

Anti-Alias LPF

Front Panel

Channel B

Programmable

Termination

ADC B

LVDS

FPGA or ASIC

DC Offset

Adjustment

DAC

Clocking

Subsystem

User Control

Logic

LMH6559

OPA703

DAC8560

SPI

LMK04832

Device Clock

÷

SYSREF

10 MHz

Reference

N÷

R÷

Device Clock

SYSREF

图8-4. Typical Configuration for a Reconfigurable Oscilloscope

8.2.2.1 Design Requirements

8.2.2.1.1 Input Signal Path

Most oscilloscopes are required to be DC-coupled in order to monitor DC or low-frequency signals. This

requirement forces the design to use DC-coupled, fully differential amplifiers to convert from single-ended

signaling at the front panel to differential signaling at the ADC. This design uses two differential amplifiers. The

first amplifier shown in 图 8-4 is the LMH5401 that converts from single-ended to differential signaling. The

LMH5401 interfaces with the front panel through a programmable termination network and has an offset

adjustment input. The amplifier has an 8-GHz, gain-bandwidth product that is sufficient to support a 1-GHz

bandwidth oscilloscope. A second amplifier, the LMH6401, comes after the LMH5401 to provide a digitally

programmable gain control for the oscilloscope. The LMH6401 supports a gain range from –6 dB to 26 dB in 1-

dB steps. If gain control is not necessary or is performed in a different location in the signal chain, then this

amplifier can be replaced with a second LMH5401 for additional fixed gain or omitted altogether.

The input of the oscilloscope contains a programmable termination block that is not covered in detail here. This

block enables the front-panel input termination to be programmed. For instance, many oscilloscopes allow the

termination to be programmed as either 50-Ω or 1-MΩ to meet the needs of various applications. A 75-Ω

termination can also be desired to support cable infrastructure use cases. This block can also contain an option

for DC blocking to remove the DC component of the external signal and therefore pass only AC signals.

A precision digital-to-analog converter (DAC) is used to configure the offset of the oscilloscope front-end to

prevent saturation of the analog signal chain for input signals containing large DC offsets. The DAC8560 is

shown in 图 8-4 along with signal-conditioning amplifiers OPA703 and LMH6559. The first differential amplifier,

LMH5401, is driven by the front panel input circuitry on one input, and the DC offset bias on the second input.

The impedance of these driving signals must be matched at DC and over frequency to ensure good even-order

harmonic performance in the single-ended to differential conversion operation. The high bandwidth of the

LMH6559 allows the device to maintain low impedance over a wide frequency range.

An antialiasing, low-pass filter is positioned at the input of the ADC to limit the bandwidth of the input signal into

the ADC. This amplifier also band-limits the front-end noise to prevent aliased noise from degrading the signal-

to-noise ratio of the overall system. Design this filter for the maximum input signal bandwidth specified by the

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oscilloscope. The input bandwidth can then be reconfigured through the use of digital filters in the FPGA or ASIC

to limit the oscilloscope input bandwidth to a bandwidth less than the maximum.

8.2.2.1.2 Clocking

The ADC12DL3200 clock inputs must be AC-coupled to the device to ensure rated performance. The clock

source must have extremely low jitter (integrated phase noise) to enable rated performance. Recommended

clock synthesizers include the LMX2594, LMX2592, and LMX2582.

For multi-device synchronization or deterministic latency the data converter system (ADC plus FPGA) requires a

SYSREF signal in addition to the device (sampling) clock, which is similar to that used for JESD204B converters.

Therefore, JESD204B compatible clock devices are a good choice for clocking the ADC12DL3200. The

LMK04832, LMK04828, LMK04826, and LMK04821 devices are suitable to generate these clocks. Depending

on the ADC clock frequency and jitter requirements, this device can also be used as the system clock

synthesizer or as a device clock and SYSREF distribution device when multiple ADC12DL3200 devices are used

in a system.

8.2.2.1.3 The ADC12DL3200

The ADC12DL3200 is ideally suited for oscilloscope applications. The ability to tradeoff channel count and

sampling speed allows designers to build flexible hardware to meet multiple needs. This flexibility saves

development time and cost, allows hardware reuse for various projects, and enables software upgrade paths for

additional functionality. The low code-error rate eliminates concerns about undesired time-domain glitches or

sparkle codes. This rate makes the ADC12DL3200 a perfect fit for long-duration transient detection

measurements and reduces the probability of false triggers. The input common-mode voltage of 0 V allows the

driving amplifiers to use equal split power supplies that center the amplifier output common-mode voltage at 0 V

and eliminates the need for common-mode voltage shifting before the ADC inputs. The high input bandwidth of

the ADC12DL3200 simplifies the design of the driving amplifier circuit and antialiasing, low-pass filter. The use of

dual-edge sampling (DES) in single-channel mode eliminates the need to change the clock frequency when

switching between dual- and single-channel modes and simplifies synchronization by relaxing the setup and hold

timing requirements of SYSREF. The t_ADadjust circuit allows the user to time-align the sampling instances of

multiple ADC12DL3200 devices.

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8.2.2.2 Application Curves

The following application curves demonstrate performance and results only of the ADC. The amplifier front-end

is not included in these measurements. 图 8-5 to 图 8-11 illustrate the following configurations and

measurements:

• 12-bit, 5-GSPS, single-channel oscilloscope

– Idle-channel noise (no input)

– 40-MHz, square-wave time domain

– 200-MHz, sine-wave time domain

– 200-MHz, sine-wave frequency domain (FFT)

• 12-bit, 2.5-GSPS, dual-channel oscilloscope

– Idle-channel noise (no input)

– 40-MHz, square-wave (channel B) and 200-MHz, sine-wave (channel A) time domain

– 40-MHz, square-wave (channel B) time domain and 200-MHz, sine-wave (channel A) frequency domain

(FFT)

图8-5. Idle-Channel Noise (No Input) for 5-GSPS,

图8-6. 40-MHz, Square-Wave Time Domain for 5-

Single-Channel Oscilloscope

GSPS, Single-Channel Oscilloscope

图8-7. 200-MHz, Sine-Wave Time Domain for 5-

图8-8. 200-MHz, Sine-Wave Frequency Domain

GSPS, Single-Channel Oscilloscope

(FFT) for 5-GSPS, Single-Channel Oscilloscope

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图8-9. Idle-Channel Noise (No Input) for 2.5-GSPS, 图8-10. 200-MHz, Sine-Wave (Channel A) and 40-

Dual-Channel Oscilloscope

MHz, Square-Wave (Channel B) Time Domain for 5-

GSPS, Single-Channel Oscilloscope

图8-11. 200-MHz, Sine-Wave (Channel A) Frequency Domain (FFT) and 40-MHz, Square-Wave (Channel

B) Time Domain for 5-GSPS, Single-Channel Oscilloscope

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8.3 Initialization Set Up

The device requires a specific startup and alignment sequence. The general order of that sequence is listed in

the following steps.

1. Power-up or reset the device.

2. Apply a stable device CLK signal at the desired frequency.

3. Program LVDS_EN = 0 to stop the LVDS state machine and allow setting changes.

4. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.

5. Program the LMODE register to the desired LVDS output mode.

6. Program SYNC_SEL as needed. Choose SYNCSE or the TMSTP± differential inputs.

7. Configure device calibration settings as desired. Select foreground or background calibration modes and

offset calibration as needed.

8. Program CAL_EN = 1 to enable the calibration state machine.

9. Enable overrange via OVR_EN and adjust settings if desired.

10. Program LVDS_EN = 1 to enable the LVDS interface and allow the receiver to initialize.

11. Assert the SYNC signal (set by SYNC_SEL) if required to send the strobe signal or user-defined pattern.

12. Program CAL_SOFT_TRIG = 0.

13. Program CAL_SOFT_TRIG = 1 to initiate a calibration.

8.4 Power Supply Recommendations

The device requires two different power-supply voltages. 1.9 V DC is required for the VA19 power bus and 1.1 V

DC is required for the VA11 and VD11 power buses. VLVDS can be set to any voltage between 1.9 V and 1.1 V.

The LVDS output driver common-mode voltage tracks the VLVDS supply voltage. In general, a 1.9-V supply

voltage for VLVDS can be used for standard LVDS receivers.

The power-supply voltages must be low noise and provide the needed current to achieve rated device

performance.

There are two recommended power-supply architectures:

1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide

switching noise reduction and improved voltage accuracy.

2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach

provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent

degraded ADC performance.

TI WEBENCH^®Power Designer can be used to select and design the individual power-supply elements needed:

see the WEBENCH® Power Designer

Recommended switching regulators for the first stage include the TPS62085, TPS82130, TPS62130A, and

similar devices.

Recommended low dropout (LDO) linear regulators include the TPS7A7200, TPS74401, and similar devices.

For the switcher only approach, the ripple filter must be designed with a notch frequency that aligns with the

switching ripple frequency of the DC/DC converter. Make a note of the switching frequency reported from

WEBENCH® and design the EMI filter and capacitor combination to have the notch frequency centered as

needed. 图8-12 and 图8-13 illustrate the two approaches. Do not share VLVDS with the analog supply voltages

in order to prevent digital switching noise from coupling into the analog signal chain. If VLVDS must be shared

with either VA11 or VA19, apply careful power supply filtering to limit digital noise at the analog supply pins.

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5V-12V

2.2V

1.4V

1.9V

VA19

Buck

LDO

47 …F

10 …F 0.1 …F 0.1 …F

FB

+

œ

Power

Good

GND

1.1V

VA11

Buck

LDO

47 …F

10 …F 0.1 …F 0.1 …F

FB

GND

VD11

10 …F 0.1 …F 0.1 …F

FB

GND

VLVDS

1.1V to 1.9V

Buck

47 …F

10 …F 0.1 …F 0.1 …F

FB

GND

FB = Ferrite Bead Filter

FB = ferrite bead filter.

图8-12. LDO Linear Regulator Approach Example

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1.9V

Ripple Filter

VA19

5V-12V

Buck

10 …F 10 …F 10 …F

10 …F 0.1 …F 0.1 …F

FB

+

œ

Power

Good

GND

1.1V

Ripple Filter

VA11

Buck

10 …F 10 …F 10 …F

10 …F 0.1 …F 0.1 …F

FB

GND

VD11

10 …F 0.1 …F 0.1 …F

GND

1.1V to 1.9V

FB

VLVDS

Buck

47 …F

10 …F 0.1 …F 0.1 …F

FB

GND

Ripple Filter Notch Frequency to Match Fs of Buck Converter

FB = Ferrite Bead Filter

Ripple filter notch frequency to match the fs of the buck converter.

FB = ferrite bead filter.

图8-13. Switcher-Only Approach Example

8.4.1 Power Sequencing

The voltage regulators must be sequenced using the power-good outputs and enable inputs to ensure that the

Vx11 regulator is enabled after the VA19 supply is good. Similarly, as soon as the VA19 supply drops out of

regulation on power-down, the Vx11 regulator is disabled.

The general requirement for the ADC is that VA19 ≥Vx11 during power-up, operation, and power-down.

TI also recommends that VA11 and VD11 are derived from a common 1.1-V regulator. This recommendation

ensures that all 1.1-V blocks are at the same voltage, and no sequencing problems exist between these

supplies. Also use ferrite bead filters to isolate any noise on the VA11 and VD11 buses from affecting each other.

If VA11 and VD11 are powered from separate regulators, then the device is sensitive to voltage drops that affect

the VA11 input. In this case, if the VA11 voltage is brought down below 0.6 V, the device must be reset through

the SOFT_RESET bit in the CONFIG_A register.

VLVDS can be powered up independently of the other supplies.

8.5 Layout

8.5.1 Layout Guidelines

There are many critical signals that require specific care during board design:

1. Analog input signals

2. CLK and SYSREF

3. LVDS data outputs at up to 1.6 Gbps

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a.

4. Power connections

5. Ground connections

Items 1 and 2 must be routed for excellent signal quality at high frequencies. Use the following general practices

for these signals:

1. Route using loosely coupled 100-Ωdifferential traces. This routing minimizes impact of corners and length-

matching serpentines on pair impedance.

2. Provide adequate pair-to-pair spacing to minimize crosstalk.

3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces.

4. Use smoothly radiused corners. Avoid 45- or 90-degree bends.

5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these

locations. Cutout below the landing pads on one or multiple ground planes to achieve a pad size or stackup

height that achieves the needed 50-Ω, single-ended impedance.

6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane

clearances associated with power and signal vias and through-hole component leads.

7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.

8. When high-speed signals must transition to another layer using vias, transition as far through the board as

possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is

not flexible, use back-drilled or buried, blind vias to eliminate stubs.

The LVDS data outputs must be routed with sufficient signal quality using the following general practices:

1. Route using tightly coupled 100-Ωdifferential traces to minimize the routing area and decrease crosstalk

between adjacent data pairs.

2. Use smoothly radiused corners or 45-degree bends. Avoid 90-degree bends.

3. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane

clearances associated with power and signal vias and through-hole component leads.

4. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.

5. Data, clock, and strobe pairs must be sufficiently delay matched to provide adequate timing margin at the

receiver. If routing on multiple layers, trace lengths must be compensated for the delay mismatch introduced

by the effective dielectric constant of each layer.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to

fabrication. Perform insertion loss, return loss, and time domain reflectometry (TDR) evaluations.

The power and ground connections for the device are also very important. These rules must be followed:

1. Provide low-resistance connection paths to all power and ground pins.

2. Use multiple power layers if necessary to access all pins.

3. Avoid narrow isolated paths that increase connection resistance.

4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power

planes.

8.5.2 Layout Example

图8-14 to 图8-16 provide examples of the critical traces routed on the device evaluation module (EVM). 图8-17

provides an example printed circuit board (PCB) layer stackup.

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图8-14. Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3

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图8-15. GND1 Cutouts to Optimize Impedance of Component Pads

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图8-16. Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7

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L1 - SIG

0.0056"

Panasonic R-5670K

Panasonic R-5775K

L2 - GND

L3 - SIG

0.0030"

0.0042"

0.0030"

0.0040"

0.0026"

0.0039"

0.0026"

0.0040"

0.0030"

0.0042"

0.0030"

0.0056"

Panasonic R-5670K

Panasonic R-5775K

L4 - GND

L5 - SIG

Panasonic R-5670K

Panasonic R-5775K

L6 - GND

L7 - POW

L8 - POW

L9 - GND

L10 - SIG

L11 - GND

L12 - SIG

L13 - GND

L14 - SIG

0.0576"

Panasonic R-5670K

Panasonic R-5775K

Panasonic R-5670K

Panasonic R-5775K

Panasonic R-5670K

Panasonic R-5775K

Panasonic R-5670K

1/4 oz Copper on L1 and L14

1/2 oz Copper on L2, L3, L4, L5, L10, L11, L12 and L13

1 oz Copper on L6, L7, L8 and L9

100-O differential signaling on SIG layers

Finished thickness is 0.0620" including plating and solder mask

图8-17. Example PCB Stackup

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8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

WEBENCH® Power Designer

8.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

8.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

8.4 商标

TI E2E^™is a trademark of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

8.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

8.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLVSDR3

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PACKAGE OUTLINE

ALJ0256A

FCBGA - 3.31 mm max height

SCALE 0.900

BALL GRID ARRAY

17.2

16.8

A

B

BALL A1 CORNER

PIN 1 ID

(OPTIONAL)

17.2

16.8

(

13)

(

11)

3.31

2.85

C

SEATING PLANE

0.2 C

0.7

0.3

BALL TYP

TYP

15 TYP

SYMM

1

TYP

(1) TYP

T

R

P

N

M

L

K

J

H

G

F

SYMM

15

TYP

E

D

C

B

A

0.74

0.54

C A B

256X

0.25

0.1

C

1

2 3 4

5

6 7 8 9 10 12 14 16

11 13 15

1

TYP

4225401/B 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

ALJ0256A

FCBGA - 3.31 mm max height

BALL GRID ARRAY

(1) TYP

256X ( 0.5)

3

5

6

7

10

11

12 13

15

14

1

2

4

8

9

16

A

(1) TYP

B

C

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SNOWN

SCALE:6X

0.07 MAX

0.07 MIN

METAL UNDER

SOLDER MASK

(

0.5)

METAL

EXPOSED METAL

(

0.5)

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4225401/B 05/2022

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

ALJ0256A

FCBGA - 3.31 mm max height

BALL GRID ARRAY

(1) TYP

256X 0.5

11

3

5

6

7

10

12 13

15

14

1

2

4

8

9

16

A

(1) TYP

B

C

METAL

TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE: 6X

4225401/B 05/2022

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

PACKAGE OUTLINE

ACF0256A

FCBGA - 3.31 mm max height

SCALE 0.900

BALL GRID ARRAY

17.2

16.8

A

B

BALL A1 CORNER

PIN 1 ID

(OPTIONAL)

17.2

16.8

(

13)

(

11)

3.31

2.85

C

SEATING PLANE

0.2 C

0.7

0.3

BALL TYP

TYP

15 TYP

SYMM

1

TYP

(1) TYP

T

R

P

N

M

L

K

J

H

G

F

SYMM

15

TYP

E

D

C

B

A

0.74

0.54

C A B

C

256X

0.25

0.1

1

2 3 4

5

6 7 8 9 10 12 14 16

11 13 15

1

TYP

4223888/C 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Pb-Free die bump and solder ball.

www.ti.com

EXAMPLE BOARD LAYOUT

ACF0256A

FCBGA - 3.31 mm max height

BALL GRID ARRAY

(1) TYP

256X ( 0.5)

3

5

6

7

10

11

12 13

15

14

1

2

4

8

9

16

A

(1) TYP

B

C

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SNOWN

SCALE:6X

0.07 MAX

0.07 MIN

METAL UNDER

SOLDER MASK

(

0.5)

METAL

EXPOSED METAL

(

0.5)

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223888/C 05/2022

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com

EXAMPLE STENCIL DESIGN

ACF0256A

FCBGA - 3.31 mm max height

BALL GRID ARRAY

(1) TYP

256X ( 0.5)

11

3

5

6

7

10

12 13

15

14

1

2

4

8

9

16

A

(1) TYP

B

C

METAL

TYP

D

E

F

G

H

J

SYMM

K

L

M

N

P

R

T

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE: 6X

4223888/C 05/2022

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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型号：	ADC12DL3200ALJ
厂家：	TEXAS INSTRUMENTS
描述：	12 位双通道 3.2GSPS 或单通道 6.4GSPS 射频采样数模转换器（LVDS 接口） \| ALJ \| 256 \| -40 to 85 射频转换器数模转换器
文件：	总160页 (文件大小：4079K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12DL3200ALJ [TI]

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