ADC12QS065 [TI]

四通道、12 位、65MSPS 模数转换器 (ADC);


型号：	ADC12QS065
厂家：	TEXAS INSTRUMENTS
描述：	四通道、12 位、65MSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总33页 (文件大小：863K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12QS065

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SNOSAD6I –JULY 2005–REVISED APRIL 2013

ADC12QS065 Quad 12-Bit 65 MSPS A/D Converter with

LVDS Serialized Outputs

Check for Samples: ADC12QS065

FEATURES

DESCRIPTION

The ADC12QS065 is a low power, high performance

CMOS 4-channel analog-to-digital converter with

LVDS serialized outputs. The ADC12QS065 digitizes

signals to 12 bits resolution at sampling rates up to

65 MSPS while consuming a typical 200 mW/ADC

•

Single +3.3V Supply Operation

Internal Sample-and-Hold and Internal

Reference

•

Low Power Consumption

Power Down Mode

from

a single 3.3V supply. Sampled data is

transformed into high speed serial LVDS output data

streams. Clock and frame LVDS pairs aid in data

capture. The ADC12QS065’s six differential pairs

transmit data over backplanes or cable and also

make PCB design easier. In addition, the reduced

cable, PCB trace count, and connector size

tremendously reduce cost.

Clock and Data Frame Timing

780 Mbps Serial LVDS Data Rate (at 65 MHz

Clock)

•

LVDS Serial Output Rated for 100 Ohm Load

KEY SPECIFICATIONS

No missing codes performance is ensured over the

full operating temperature range. The pipeline ADC

architecture achieves 11 Effective Bits over the entire

Nyquist band at 65 MSPS.

•

Resolution: 12 Bits

DNL: ±0.3 LSB (Typ)

SNR (f_IN= 5 MHz): 69 dB (Typ)

SFDR (f_IN= 5 MHz): 83 dB (Typ)

ENOB (at Nyquist): 11 Bits (Typ)

Power Consumption

When not converting, power consumption can be

reduced by pulling the PD (Power Down) pin high,

placing the converter into a low power state where it

typically consumes less than 3 mW total, and from

–

Operating, 65 MSPS, per ADC: 200 mW

(Typ)

which recovery is less than

ms. The

ADC12QS065's speed, resolution and single supply

operation makes it well suited for a variety of

applications in ultrasound, imaging, video and

communications. Operating over the industrial (-40°C

to +85°C) temperature range, the ADC12QS065 is

available in a 60-pin WQFN package with exposed

pad (9x9x0.8mm, 0.5mm pin pitch).

–

Power Down Mode: < 3 mW (Typ)

APPLICATIONS

•

Ultrasound

Medical Imaging

Communications

Portable Instrumentation

Digital Video

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC12QS065

SNOSAD6I –JULY 2005–REVISED APRIL 2013

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Connection Diagram

V_A

DRGND

DO1-

AGND

DO1+

V_IN1+

V_IN1-

AGND

DO2-

DO2+

DRGND

FRAME-

FRAME+

OUTCLK-

OUTCLK+

DRGND

DO3-

V_IN2-

V_IN2+

AGND

ADC12QS065

V_IN3+

V_IN3-

AGND

V_IN4-

V_IN4+

AGND

V_A

* Exposed pad must be soldered to ground

plane to ensure rated performance.

DO3+

DO4-

DO4+

Figure 1. 60-Lead WQFN

See NKA0060A Package

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Block Diagram

DO1+

DO1-

ADC - Channel 1

Serializer

V_REFT12

V_COM12

V_REFB12

DO2+

DO2-

ADC - Channel 2

Serializer

CLK

CLKB

PLL

FRAME+

FRAME-

Reference Select and Internal

Reference

Framing &

Serial Clock

Generator

V_REF

OUTCLK+

OUTCLK-

DO3+

DO3-

ADC - Channel 3

Serializer

V_REFT34

V_COM34

V_REFB34

DO4+

DO4-

ADC - Channel 4

Serializer

ADC Channel Detail

2.5 bit

S/H

2.5 bit

Converter

2.5 bit

Converter

To Serializer

Digital Error Correction and Decode

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PIN DESCRIPTIONS

Pin No.

ANALOG I/O

Symbol

Description

V_IN1+

V_IN2+

V_IN3+

V_IN4+

Differential analog input pins. With a 1.0V reference voltage the differential full-scale

input signal level is 2.0 V_P-Pwith each input pin voltage centered on a common mode

voltage, V_COM. The negative input pins may be connected to V_COMfor single-ended

operation, but a differential input signal is required for best performance.

V_IN1-

V_IN2-

V_IN3-

V_IN4-

This pin is the reference select pin and the external reference input, used in conjunction

with the INTREF pin.

If the INTREF pin is set to V_A, this pin is used as an internal reference select. With V_REF

= V_A, the internal 1.0V reference is selected. With V_REF=AGND, the internal 0.5V

reference is selected.

V_REF

If the INTREF pin is set to AGND, then this pin is the input for an external reference. A

voltage in the range of 0.8 to 1V may be applied to this pin. V_REFshould be bypassed to

AGND with a 1.0 µF capacitor when an external reference is used.

Top ADC Reference. This pin has to be driven to 1.9V if REFPD is high.

If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and a 10 µF

low ESR capacitor to VREFB. These pins should not be loaded.

VREFT12

VREFT34

This is an analog output which can be used as a common mode voltage for the inputs. It

should be bypassed to AGND with a minimum of a 1.0 µF low ESR capacitor in parallel

with a 0.1 µF capacitor. These pins may also be used as a 1.5V temperature stable

reference voltage with a maximum load of 1mA.

VCOM12

VCOM34

Bottom ADC Reference. This pin has to be driven to 0.9V if REFPD is high.

If REFPD is low, bypass this pin with a 0.1 µF low ESR capacitor to AGND and a 10 µF

low ESR capacitor to VREFT. These pins should not be loaded.

VREFB12

VREFB34

This is the bypass pin for the internal 1.8V regulator. This pin should be bypassed to

AGND with a 1.0 µF capacitor

VREG

DIGITAL I/O

This pin acts as either a Non-Inverting Differential Clock input or a CMOS clock input. If

CLKB is used as the Inverting Clock input, CLK will act as the Non-Inverting Clock input.

If CLKB is tied to AGND, CLK will act as a CMOS clock input. ADC power consumption

will increase by about 40mW if a Differential Clock is used.

CLK

CLKB

INTREF

Inverting Differential Clock input. If tied to AGND, CLK acts as a CMOS clock input.

Internal reference enable input. When this pin is high, two internal reference choices are

selectable through the V_REFpin. When this pin is low, an external reference must be

applied to V_REF(pin 23).

Power Down pin that, when high, puts the converter into the Power Down mode.

With REFPD high, user must drive VREFT12, VREFT34 and VREFB12 & VREFB34

externally. With REFPD low, VREFT12, VREFT34 and VREFB12 & VREFB34 are driven

internally.

REFPD

DO1+

DO2+

DO3+

DO4+

+ Serial Data Output. Non-inverting LVDS differential output.

- Serial Data Output. Inverting LVDS differential output.

DO1-

DO2-

DO3-

DO4-

FRAME+

FRAME-

LVDS output, it’s rising edge corresponds to the first serial bit of the output streams.

FRAME clock frequency is the same as the CLK frequency.

OUTCLK+

OUTCLK-

LVDS output clock. The data is valid on an output transition. Successive data bits are

captured on both edges of this clock. OUTCLK frequency is 6X the CLK frequency.

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PIN DESCRIPTIONS (continued)

Pin No.

Symbol

Description

ANALOG POWER

Positive analog supply pins. These pins should be connected to a quiet +3.3V source

and bypassed to AGND with 0.1 µF capacitors located near these power pins, and with

a 10 µF capacitor.

1,15,17,19,

58,59

V_A

2,5,8,11,

14,16,18,

46,49,60

The ground return for the analog supply.

NOTE: The exposed pad on the WQFN package must be soldered to AGND.

AGND

DIGITAL POWER

Positive digital supply pin. This pin should be connected to the same quiet +3.3V source

as is V_Aand be bypassed to DGND with a 0.1 µF capacitor located near the power pin

and with a 10 µF capacitor.

26,53

V_D

27, 52

DGND

The ground return for the digital supply.

Positive driver supply pin for the ADC12QS065's output drivers. This pin should be

connected to a voltage source of +2.5V to V_Dand be bypassed to DR GND with a 0.1

µF capacitor. If the supply for this pin is different from the supply used for V_Aand V_D, it

should also be bypassed with a 10 µF capacitor. V_DRshould never exceed the voltage

on V_D. All bypass capacitors should be located near the supply pin.

28, 51

V_DR

30,35,40, 45,50

DRGND

The ground return for the ADC12QS065's output drivers.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings^(1)(2)(3)(4)

V_A, V_D, V_DR

3.8V

≤ 100 mV

|V_A–V_D|

Voltage on any pin (excludes pins 29 to 45)

Voltage on any pin (pins 29 to 45)

Input Current at Any Pin⁽⁵⁾

Package Input Current⁽⁵⁾

Package Dissipation at T_A= 25°C

−0.3V to (V_Aor V_D+0.3V)

-0.3V to 2V

±25 mA

±50 mA

See⁽⁶⁾

Human Body Model⁽⁷⁾

Machine Model⁽⁷⁾

2500V

ESD Susceptibility

250V

Soldering Temperature

Storage Temperature

Infrared (10 sec.)⁽⁸⁾

235°C

−65°C to +150°C

(1) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(3) Soldering process must comply with Texas Instruments' Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.

(4) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(5) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(6) The absolute maximum junction temperature (T_Jmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

T_Jmax, the junction-to-ambient thermal resistance (θ_JA), and the ambient temperature, (T_A), and can be calculated using the formula

P_DMAX = (T_Jmax - T_A)/θ_JA. In the 60-pin WQFN, θ_JAis 20°C/W with the exposed pad soldered to a ground plane, so P_DMAX = 2 W at

the maximum operating ambient temperature of 85°C. Note that the power consumption of this device under normal operation will

typically be about 900 mW. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(7) Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

(8) Reflow Reflow temperature profiles are different for lead-free and non-lead-free packages.

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Operating Ratings⁽¹⁾⁽²⁾

Operating Temperature

−40°C ≤ T_A≤ +85°C

+3.0V to +3.6V

+2.4V to V_D

Supply Voltage (V_A, V_D)

Output Driver Supply (V_DR

)

V_INDifferential Input Range

±V_REF

V_CMInput Common Mode Range (Differential Input)

External V_REFVoltage Range

V_REF/2 to (V_A- V_REF/2 )

0.8V to 1V

Digital Input Pins Voltage Range (excludes pins 31 to 50)

|AGND–DGND|

−0.3V to (V_A+ 0.3V)

≤100mV

Clock Duty Cycle

30% to 70%

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, Internal V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 KHz, C_L= 15 pF/pin. Boldface limits apply for T_J= T_MINto T_MAX: all

other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁵⁾

Limits⁽⁵⁾

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Bits (min)

LSB (max)

%FS (max)

ppm/°C

INL

Integral Non Linearity

Differential Non Linearity

Positive Gain Error

±0.7

±0.3

±1.5

±1.1

7.5

±1.4

±0.7

±3.5

DNL

PGE

NGE

TC GE

V_OFF

Negative Gain Error

Gain Error Tempco

−40°C ≤ T_A≤ +85°C

Offset Error (V_IN+ = V_IN−)

±0.06

4.4

±0.75

%FS (max)

ppm/°C

TC V_OFFOffset Error Tempco

Under Range Output Code

Over Range Output Code

−40°C ≤ T_A≤ +85°C

4095

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, Internal V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 KHz, C_L= 15 pF/pin. Boldface limits apply for T_J= T_MINto T_MAX: all

other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁵⁾

Limits⁽⁵⁾

REFERENCE AND ANALOG INPUT CHARACTERISTICS

0.5

2.0

V (min)

V (max)

V_P-P

V_CM

V_IN

Common Mode Input Voltage

Analog Differential Input Range

1.5

(CLK LOW)

(CLK HIGH)

C_IN

V_INInput Capacitance (each pin to GND) V_IN= 2.5 Vdc + 0.7 V_rms

0.8

V (min)

V (max)

MΩ (min)

V_REF

External Reference Voltage⁽⁶⁾

Reference Input Resistance

1.00

DYNAMIC CONVERTER CHARACTERISTICS

FPBW

Full Power Bandwidth

Signal-to-Noise Ratio⁽⁷⁾

0 dBFS Input, Output at −3 dB

300

69.3

68.5

MHz

dBFS (min)

dBFS

dBFS (min)

dBFS

Bits (min)

Bits

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

f_IN= 5 MHz, V_IN= −1 dBFS

f_IN= 33 MHz, V_IN= −1 dBFS

68.4

SNR

SINAD

ENOB

THD

Signal-to-Noise and Distortion⁽⁷⁾

Effective Number of Bits⁽⁷⁾

Total Harmonic Distortion

11.2

−82

−78

−92.5

−83

−83.3

−80

83.3

-74.5

-79

dBc (min)

dBc

Second Harmonic Distortion

Third Harmonic Distortion

Spurious Free Dynamic Range

dBc

-75.5

75.5

dBc

SFDR

dBc

f_IN= 19.6 MHz and 20.2 MHz,

each = −7 dBFS

IMD

Intermodulation Distortion

Full Power Bandwidth

−78

dBFS

MHz

FPBW

300

INTER-CHANNEL CHARACTERISTICS

Channel—Channel Offset Match

Channel—Channel Gain Match

±0.3

±4

%FS

10 MHz Tested, Channel;

20 MHz Other Channel

Crosstalk (between any two channels)

dBc

(6) Optimum performance will be obtained by keeping the reference input in the 0.8V to 1V range. The LM4051CIM3-ADJ (SOT-23

package) is recommended for external reference applications.

(7) This parameter is specified in dBFS - indicating the value that would be attained with a full-scale input signal.

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Boldface limits apply for T_J= T_MINto T_MAX: all

other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁵⁾Limits⁽⁵⁾

DIGITAL INPUT CHARACTERISTICS

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

V_D= 3.6V

V_D= 3.0V

V_IN= 3.3V

V_IN= 0V

2.0

V (min)

V (max)

µA

0.5

−1

µA

POWER SUPPLY CHARACTERISTICS

PD Pin = DGND

PD Pin = V_D

168

0.5

200

mA (max)

I_A

I_D

Analog Supply Current

PD Pin = DGND

PD Pin = V_D

0.2

mA (max)

Digital Supply Current

I_DR

LVDS Output Supply Current

PD Pin = DGND, f_IN= 33 MHz

mA (max)

PWR

Total Power Consumption

(includes driver supply)

PD Pin = DGND, C_L= 5 pF

PD Pin = V_D

828

990

mW (max)

PSRR

Rejection of Full-Scale Error with

V_A= 3.0V vs. 3.6V

Power Supply Rejection Ratio

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Boldface limits apply for T_J= T_MINto T_MAX: all

other limits T_J= 25°C^(1)(2)(3)(4)

Units

Symbol

Parameter

Conditions

Typical⁽⁵⁾Limits⁽⁵⁾

(Limits)

MHz (min)

MHz

f_CLK

Maximum Clock Frequency

Minimum Clock Frequency

f_CLK

% min

% max

Clock Duty Cycle

Input Sample(N) to LSB of Sample(N)

Data valid

t_CONV

Conversion Latency

Clock Cycles

t_AD

t_AJ

t_PD

Aperture Delay

ps rms

Aperture Jitter

Power Down Mode Exit Cycle

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

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LVDS Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Boldface limits apply for T_J= T_MINto T_MAX: all

other limits T_J= 25°C^(1)(2)(3)(4)

Units

(Limits)

Symbol

Parameter

Conditions

Typical⁽⁵⁾Limits⁽⁵⁾

LVDS DC CHARACTERISTICS

Output Differential Voltage

(DO+) - (DO-)

230

mV (min)

mV (max)

V_OD

R_L= 100Ω

290

450

delta

V_OD

Output Differential Voltage Unbalance

Offset Voltage

±1

±15

mV (max)

1.125

1.375

V (min)

V (max)

V_OS

R_L= 100Ω

1.25

delta V_OSOffset Voltage Unbalance

IOS Output Short Circuit Current

LVDS OUTPUT TIMING AND SWITCHING CHARACTERISTICS

±7

±25

mV (max)

mA (max)

DO = 0V, V_IN= 1.1V

-10

t_OCP

Output Clock Period

50% to 50%

See⁽⁶⁾

2.56

% (min)

% (max)

t_OCDC

Output Clock Duty Cycle

Data Edge to Output Clock Edge Hold

Time

t_H

50% to 50%⁽⁶⁾

625

300

Data Edge to Output Clock Edge Set-Up

Time

t_S

50% to 50%⁽⁶⁾

50% to 50%

See⁽⁶⁾

600

15.38

t_FP

t_FDC

Frame Period

% (min)

% (max)

Frame Clock Duty Cycle

t_DFS

t_R, t_F

t_PLD

t_SD

Data Edge to Frame Edge Skew

LVDS Rise/Fall Time

50% to 50%

360

160

700

ps (max)

µs

C_L=5pF to GND, R_OUT=100Ω

Serializer PLL Lock Time

Serializer Delay

R_L=100Ω

2.76

(1) The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided

current is limited per. However, errors in the A/D conversion can occur if the input goes above V_Aor below GND by more than 100 mV.

As an example, if V_Ais +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions.

I/O

To Internal Circuitry

AGND

(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3) With the test condition for V_REF= +1.0V (2V_P-Pdifferential input), the 12-bit LSB is 488 µV.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 25 mA to two.

(5) Typical figures are at T_A= 25°C, and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(6) This parameter is ensured by design and/or qualification and is not tested in production.

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Specification Definitions

APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the common d.c. voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is

presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay

plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the

conversion by the pipeline delay.

CROSSTALK is coupling of energy from one channel into the other channel.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale Error

(1)

Gain Error can also be separated into Positive Gain Error and Negative Gain Error, which are:

PGE = Positive Full Scale Error − Offset Error

(2)

(3)

NGE = Offset Error − Negative Full Scale Error

GAIN ERROR MATCHING is the difference in gain errors between the two converters divided by the average

gain of the converters.

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is V_REF/2ⁿ,

where “n” is the ADC resolution in bits, which is 12 in the case of the ADC12QS065.

LVDS Differential Output Voltage (V_OD) is the absolute value of the difference between the differential output

pair voltages (V_D+ and V_D-), each measured with respect to ground.

V_D+

V_D-

V_OD

V_OS

GND

V_OD= | V_D+ - V_D- |

(4)

LVDS Output Offset Voltage (V_OS) is the midpoint between the differential output pair voltages.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12QS065 is

ensured not to have any missing codes.

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MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages [(V_IN+) – (V_IN−)] required to cause a transition

from code 2047 to 2048.

OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the

output pins.

OVER RANGE RECOVERY TIME is the time required after V_INgoes from a specified voltage out of the normal

input range to a specified voltage within the normal input range and the converter makes a conversion with its

rated accuracy.

PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power

supply voltage. For the ADC12QS065, PSRR is the ratio of the change in Full-Scale Error that results from a

change in the d.c. power supply voltage, expressed in dB.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is

any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic

levels at the output to the level of the fundamental at the output. THD is calculated as

f10

+ . . . + A

THD = 20 x log

(5)

where f₁is the RMS power of the fundamental (output) frequency and f₂through f₁₀are the RMS power of the

first 9 harmonic frequencies in the output spectrum.

SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in

the input frequency at the output and the power in its 2nd harmonic level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in

the input frequency at the output and the power in its 3rd harmonic level at the output.

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Timing Diagram

CLK

FRAME +/-

OUTCLK+/-

OCHL

80%

20%

80%

20%

OCP

OCHL

DATA+/-

B11 B10

(MSB)

B11 B10

(LSB) (MSB)

+1 Sample

Sample

Figure 2. LVDS Output Timing

Transfer Characteristic

Figure 3. Transfer Characteristic

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Typical Performance Characteristics DNL, INL

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, Internal V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 KHz, C_L= 15 pF/pin.

DNL

INL

Figure 4.

Figure 5.

DNL vs. f_CLK

INL vs. f_CLK

Figure 6.

Figure 7.

DNL vs. Clock Duty Cycle

INL vs. Clock Duty Cycle

Figure 8.

Figure 9.

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Typical Performance Characteristics DNL, INL (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DRGND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, Internal V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 KHz, C_L= 15 pF/pin.

DNL vs. Temperature

INL vs. Temperature

Figure 10.

Figure 11.

DNL vs. V_DR, V_A= V_D= 3.6V

INL vs. V_DR, V_A= V_D= 3.6V

Figure 12.

Figure 13.

INL vs. V_A

DNL vs. V_A

Figure 14.

Figure 15.

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Typical Performance Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Units for SNR and SINAD are dBFS.

Units for SFDR and Distortion are dBc.

SNR, SINAD, SFDR vs. V_A

Distortion vs. V_A

Figure 16.

Figure 17.

SNR, SINAD, SFDR vs. V_CM

Distortion vs. V_CM

Figure 18.

Figure 19.

SNR, SINAD, SFDR vs. f_CLK

Distortion vs. f_CLK

Figure 20.

Figure 21.

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Typical Performance Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Units for SNR and SINAD are dBFS.

Units for SFDR and Distortion are dBc.

SNR, SINAD, SFDR vs. Clock Duty Cycle

Distortion vs. Clock Duty Cycle

Figure 22.

Figure 23.

SNR, SINAD, SFDR vs. V_REF

Distortion vs. V_REF

Figure 24.

Figure 25.

SNR, SINAD, SFDR vs. f_IN

Distortion vs. f_IN

Figure 26.

Figure 27.

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Typical Performance Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V_A= V_D= +3.3V, V_DR

+2.5V, PD = 0V, External V_REF= +1.0V, f_CLK= 65 MHz, f_IN= 5 MHz, C_L= 15 pF/pin. Units for SNR and SINAD are dBFS.

Units for SFDR and Distortion are dBc.

SNR, SINAD, SFDR vs. Temperature

Distortion vs. Temperature

Figure 28.

Figure 29.

Spectral Response @ 5 MHz Input

Spectral Response @ 33 MHz Input

Figure 30.

Figure 31.

Spectral Response @ 70 MHz Input

Intermodulation Distortion, f_IN1= 19.6 MHz, f_IN2 = 20.2 MHz

Figure 32.

Figure 33.

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FUNCTIONAL DESCRIPTION

Operating on a single +3.3V supply, the ADC12QS065 uses a pipeline architecture and has error correction

circuitry to help ensure maximum performance. The differential analog input signal is digitized to 12 bits. The

user has the choice of using an internal 1.0 Volt or 0.5 Volt stable reference, or using an external reference. Any

external reference is buffered on-chip to ease the task of driving that pin.

Sampled data is transformed into high speed serial output LVDS data streams. Clock and frame LVDS pairs aid

in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make

PCB design easier.

The output word rate is the same as the clock frequency, which can be between 20 MSPS and 65 MSPS

(typical) with fully specified performance at 65 MSPS. The analog input for all channels are acquired at the rising

edge of the clock and the digital data for a given sample is delayed by the pipeline for 9 clock cycles.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC12QS065:

3.0V ≤ V_A≤ 3.6V

V_D= V_A

V_{DR = 2.5V}

20 MHz ≤ f_CLK≤ 65 MHz

0.8V ≤ V_REF≤ 1V (for an external reference)

0.5V ≤ V_CM≤ 2.0V

ANALOG INPUTS

There is one reference input pin, V_REF, which is used to select an internal reference, or to supply an external

reference. The ADC12QS065 has four analog signal input pairs, V_IN1+ and V_IN1-, V_IN2+ and V_IN2- , V_IN3+ and

V_IN3-, V_IN4+ and V_IN4- . Each pair of pins forms a differential input pair. There is a VREG pin for decoupling the

internal 1.8V regulator.

Reference Pins

The ADC12QS065 is designed to operate with an internal 1.0V or 0.5V reference, or an external 1.0V reference,

but performs well with external reference voltages in the range of 0.8V to 1V. Lower reference voltages will

decrease the signal-to-noise ratio (SNR) of the ADC12QS065. Increasing the reference voltage (and the input

signal swing) beyond 1V may degrade THD for a full-scale input, especially at higher input frequencies.

It is important that all grounds associated with the reference voltage and the analog input signal make connection

to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.

The six Reference Bypass Pins (VREFT12, VREFB12, VCOM12, VREFT34, VREFB34 and VCOM34) are made

available for bypass purposes. All these pins should each be bypassed to ground with a 0.1 µF capacitor. A 10

µF capacitor should be placed between the VREFT12 and VREFB12 pins and between the VREFT34 and

VREFB34 pins, as shown in Figure 36. This configuration is necessary to avoid reference oscillation, which could

result in reduced SFDR and/or SNR.

Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may

result in degraded noise performance.

The VCOM pins may be loaded to 1 mA. The remaining reference bypass pins should not be loaded.

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The nominal voltages for the reference bypass pins are as follows:

VCOM = 1.5 V

VREFT = VCOM + V_REF/ 2

VREFB = VCOM − V_REF/ 2

User choice of an on-chip or external reference voltage is provided. When INTREF is high, the V_REFpin selects

the internal reference voltage. The internal 1.0 Volt reference is in use when the the V_REFpin is connected to V_A.

When the V_REFpin is connected to AGND, the internal 0.5 Volt reference is in use. When INTREF is low, a

voltage in the range of 0.8V to 1V is applied to the V_REFpin and that is used for the voltage reference. When an

external reference is used, the V_REFpin should be bypassed to ground with a 0.1 µF capacitor close to the

reference input pin. There is no need to bypass the V_REFpin when the internal reference is used.

Signal Inputs

The ADC12QS065 has 4 input channels. They are labelled V_IN1+ and V_IN1− , V_IN2+ and V_IN2− , V_IN3+ and

V_IN3− , V_IN4+ and V_IN4− . The input signal, V_IN, is defined as

V_IN= (V_IN+) – (V_IN−)

(6)

Figure 34 shows the expected input signal range. Note that the common mode input voltage, V_CM, should be in

the range of 0.5V to 2.0V with a typical value of 1.5V.

The peaks of the individual input signals should each never exceed 2.6V to maintain THD and SINAD

performance.

The ADC12QS065 performs best with a differential input signal with each input centered around a common

mode voltage, V_CM. The peak-to-peak voltage swing at each analog input pin should not exceed the value of the

reference voltage or the output data will be clipped.

The two input signals should be exactly 180° out of phase from each other and of the same amplitude. For single

frequency inputs, angular errors result in a reduction of the effective full scale input. For complex waveforms,

however, angular errors will result in distortion.

REF

(a) Differential Input

REF

(b) Single-Ended Input

Figure 34. Expected Input Signal Range

For single frequency sine waves the full scale error in LSB can be described as approximately

E_FS= 4096 ( 1 - sin (90° + dev))

where

•

dev is the angular difference in degrees between the two signals having a 180° relative phase relationship to

each other (see Figure 35). (7)

Drive the analog inputs with a source impedance less than 100Ω.

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Figure 35. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause

Distortion

For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage just

below the reference voltage, V_REF, be 180 degrees out of phase with each other and be centered around V_CM

Single-Ended Operation

Performance with differential input signals is better than with single-ended signals. For this reason, single-ended

operation is not recommended. However, if single ended-operation is required and the resulting performance

degradation is acceptable, one of the analog inputs should be connected to the d.c. mid point voltage of the

driven input. The peak-to-peak differential input signal at the driven input pin should be twice the reference

voltage to maximize SNR and SINAD performance (Figure 34). For example, set V_REFto 0.5V, bias V_IN− to 1.0V

and drive V_IN+ with a signal range of 0.5V to 1.5V.

Because very large input signal swings can degrade distortion performance, better performance with a single-

ended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and

Table 2 indicate the input to output relationship of the ADC12QS065.

Table 1. Input to Output Relationship – Differential Input

−

V_IN

_CM− V_REF/ 2

V_IN

Binary Output

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

V_CM+ V_{REF / 2}

V_CM+ V_REF/ 4

V_CM

_CM− V_{REF / 4}

V_CM

V_CM+ V_REF/ 4

V_CM+ V_REF/ 2

_CM− V_REF/ 4

_CM− V_REF/ 2

Table 2. Input to Output Relationship – Single-Ended Input

−

V_IN

Binary Output

_CM− V_REF

V_CM

0000 0000 0000

0100 0000 0000

1000 0000 0000

1100 0000 0000

1111 1111 1111

_CM− V_REF/ 2

V_CM

V_CM+ V_REF/ 2

V_CM+ V_REF

Driving the Analog Inputs

The V_IN+ and the V_IN− inputs of the ADC12QS065 consist of an analog switch followed by a switched-capacitor

amplifier. As the internal sampling switch opens and closes, current pulses occur at the analog input pins,

resulting in voltage spikes at the signal input pins. As a driving source attempts to counteract these voltage

spikes, it may add noise to the signal at the ADC analog input. To help isolate the pulses at the ADC input from

the amplifier output, use RCs at the inputs, as can be seen in Figure 36 and Figure 37. These components

should be placed close to the ADC inputs because the input pins of the ADC is the most sensitive part of the

system and this is the last opportunity to filter that input.

For Nyquist applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the

sample mode should be considered when setting the RC pole. For wideband undersampling applications, the RC

pole should be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response.

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Input Common Mode Voltage

The input common mode voltage, V_CM, should be in the range of 0.5V to 2.0V and be a value such that the peak

excursions of the analog signal does not go more negative than ground or more positive than 2.6V. The nominal

V_CMshould generally be about 1.5V. VCOM12 or VCOM34 can be used as a V_CMsource.

Internal Regulator

The ADC12QS065 has an internal 1.8V regulator. The VREG pin (pin 29) should be bypassed to AGND with a

1.0 µF capacitor.

DIGITAL INPUTS

Digital TTL/CMOS compatible inputs consist of CLK, PD, REFPD, and INTREF.

CLK

The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock

signal in the range of 20 MHz to 65 MHz. The trace carrying the clock signal should be as short as possible and

should not cross any other signal line, analog or digital, not even at 90°.

The CLK signal also drives an internal state machine. If the CLK is interrupted, or its frequency too low, the

charge on internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This

is what limits the minimum sample rate.

The ADC12QS065 can operate with a CMOS or LVDS clock signal.

For a CMOS clock, connect CLKB (pin 48) to AGND and apply the clock signal to CLK (pin 47.) The clock line

should be terminated at its source in the characteristic impedance of that line. Take care to maintain a constant

clock line impedance throughout the length of the line. Refer to Application Note AN-905 (SNLA035) for

information on setting characteristic impedance. It is highly desirable that the the source driving the ADC CLK pin

only drive that pin. However, if that source is used to drive other things, each driven pin should be a.c.

terminated with a series RC to ground, such that the resistor value is equal to the characteristic impedance of the

clock line and the capacitor value is

where

•

t_PDis the signal propagation rate down the clock line

"L" is the line length

Z_Ois the characteristic impedance of the clock line

(8)

This termination should be as close as possible to the ADC clock pin but beyond it as seen from the clock

source. Typical t_PDis about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of "L" and t_PDshould be

the same (inches or centimeters).

For an LVDS clock, drive the CLK and CLKB pins with an ac-coupled differential clock signal. The pair should be

terminated with a 100Ω resistor near the pins.

The PD pin, when high, holds the ADC12QS065 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 3 mW with a 65MHz clock.. The output data pins are

undefined and the data in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the components on the reference bypass

pins 55-57, and 20-22, and is as listed in the Electrical Tables with the recommended components on the

VREFT, VREFB and VCOM reference bypass pins. These capacitors loose their charge in the Power Down

mode and must be recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values

allow slightly faster recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB

performance.

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REFPD

When high, the REFPD pin will power down the internal reference. With REFPD high, user must drive VREFT12,

VREFT34 and VREFB12 & VREFB34 externally. With REFPD low, VREFT12, VREFT34, VREFB12 and

VREFB34 are driven internally.

INTREF

When INTREF is connected to V_D, two internal reference choices are selectable through the V_REFpin (pin 23).

When INTREF is connected to DGND, an external reference must be applied to V_REF. (See Reference Pins).

OUTPUTS

The ADC12QS065 has four Low Voltage Differential Signaling (LVDS) Data Output pairs. Valid data is present at

these outputs while the PD pin is low. The OUTCLK and FRAME pins aid in data capture.

LVDS signals provide a high level of immunity to common mode noise. The differential data signals consist of

two 350mVpp (typical) signals that are 180 degrees out of phase. The PCB traces for these signals should be

treated as transmission lines. Each signal pair should have closely coupled traces designed with 100Ω

differential impedance and should be terminated with a 100Ω resistor near the receiver.

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10 mF

0.1 mF

x 6

NOTE: Decouple each V , V , and

0.1 mF

x 2

0.1 mF

x 2

pin with a 0.1 mF capacitor. See

pin description table for list of pins.

ADT1-6T

0.1 mF

20W

DO1+

DO1-

LVDS

Output 1

100W

0.1 mF

20W

47 pF

10 mF

50W

VREFT12

VREFB12

DO2+

DO2-

VCOM12

LVDS

Output 2

1 mF

ADT1-6T

0.1 mF

20W

0.1 mF

(3 places)

0.1 mF

20W

47 pF

OUTCLK+

OUTCLK-

50W

LVDS

OUTCLK

100W

ADT1-6T

0.1 mF

20W

FRAME+

FRAME-

LVDS

FRAME

0.1 mF

20W

47 pF

10 mF

50W

VREFT34

20 VREFB34

VCOM34

1 mF

ADC12QS065

ADT1-6T

0.1 mF

20W

0.1 mF

(3 places)

DO3+

DO3-

LVDS

Output 3

100W

0.1 mF

20W

47 pF

50W

DO4+

DO4-

LVDS

Output 4

INTREF

REF

ADC CLOCK

CLK

CLKB

VREG

1 mF

REFPD

Figure 36. Application Circuit using Transformer Drive Circuit

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511, 1%

from

ADC

COM

To ADC

255, 1%

280, 1%

50W

SIGNAL

INPUT

Amplifier:

LMH6650

47 pF

49.9,

To ADC

511, 1%

Figure 37. Differential Op-Amp Drive Circuit of Figure 36

POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor

close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.

As is the case with all high-speed converters, the ADC12QS065 is sensitive to power supply noise. Accordingly,

the noise on the analog supply pin should be kept below 100 mV_P-P

No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be

especially careful of this during power turn on and turn off.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC12QS065 between these areas, is required to

achieve specified performance.

The package of the ADC12QS065 has an exposed pad on its back that provides the primary heat removal path

as well as electrical grounding to the printed circuit board. The exposed pad must be attached to the board to

remove the maximum amount of heat from the package, as well as to ensure best product parametric

performance.

To maximize the removal of heat from the package, a thermal land pattern must be incorporated on the PC

board within the footprint of the package. The land pattern for this exposed pad should be at least as large as the

exposed pad of the package and be located such that the exposed pad of the device is entirely over that thermal

land pattern. This thermal land pattern should be electrically connected to ground.

To minimize junction temperature, it is recommended that a simple heat sink be built into the PCB. This is done

by including a copper area on the opposite side of the PCB. This copper area may be plated or solder coated to

prevent corrosion, but should not have a conformal coating, which could provide some thermal insulation.

Thermal vias should be used to connect these top and bottom copper areas. These thermal vias act as "heat

pipes" to carry the thermal energy from the device side of the board to the opposite side of the board where it

can be more effectively dissipated. The use of 9 to 16 thermal vias is recommended. The thermal vias should be

placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to

avoid solder wicking into the vias during the soldering process.

The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output

current can exhibit high transients that could add noise to the conversion process. To prevent this from

happening, the DRGND pins should NOT be connected to system ground in close proximity to any of the

ADC12QS065's other ground pins.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

The LVDS output pairs should be routed with a 100Ω differential impedance trace, and should be terminated at

the receiver with a 100Ω resistor.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than is total ground plane volume.

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Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in

high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to

keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the

generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause

problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to

degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.

Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the

signal path through all components should form a straight line wherever possible.

Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit

in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies

beside each other.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane. Traces for the

input channels should be routed away from each other as much as possible, with Ground plane between

channels, to help minimize crosstalk.

DYNAMIC PERFORMANCE

To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate

the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 38. The gates used in

the clock tree must be capable of operating at frequencies much higher than those used if added jitter is to be

prevented.

Best performance will be obtained with a differential input drive, compared with a single-ended drive, as

discussed in Single-Ended Operation and Driving the Analog Inputs.

As mentioned in the CLK section, it is good practice to keep the ADC clock line as short as possible and to keep

it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to

reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings

have capacitive coupling, so try to avoid even these 90° crossings of the clock line.

Figure 38. Isolating the ADC Clock from other Circuitry with a Clock Tree

COMMON APPLICATION PITFALLS

Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should

not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above

the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not

uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot

that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending

digital input, close to the signal source, will eliminate the problem.

Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or

power down.

Be careful not to overdrive the inputs of the ADC12QS065 with a device that is powered from supplies outside

the range of the ADC12QS065 supply. Such practice may lead to conversion inaccuracies and even to device

damage.

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Using an inadequate amplifier to drive the analog input. As explained, the capacitance seen at the input

alternates between two values depending upon the phase of the clock. This dynamic load is more difficult to

drive than is a fixed capacitance.

If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade

performance. A small series resistor at each amplifier output and a capacitor at the analog inputs (as shown in

Figure 36 and Figure 37) will improve performance. The LMH6550 is an example of an amplifier that may be

used to drive the analog inputs of the ADC12QS065.

Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of

phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will

affect the effective phase between these two signals. Remember that an operational amplifier operated in the

non-inverting configuration will exhibit more time delay than will the same device operating in the inverting

configuration.

Operating with the reference pins outside of the specified range. As mentioned, V_REFshould be in the range

0.8V ≤ V_REF≤ 1V

(9)

Operating outside of these limits could lead to performance degradation.

Inadequate network on Reference Bypass pins (VREFT12, VREFB12, VCOM12, VREFT34, VREFB34 and

VCOM34). These pins should be bypassed as mentioned in Reference Pins for best performance.

Using a clock source with excessive jitter, using excessively long clock signal trace, or having other

signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive

output noise and a reduction in SNR and SINAD performance.

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REVISION HISTORY

Changes from Revision H (April 2013) to Revision I

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 27

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC12QS065CISQ/NOPB

ACTIVE

WQFN

NKA

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

12QS065

CISQ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC12QS065CISQ/NOPB WQFN

NKA

250

178.0

16.4

9.3

1.3

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WQFN NKA 60

SPQ

Length (mm) Width (mm) Height (mm)

208.0 191.0 35.0

ADC12QS065CISQ/NOPB

250

Pack Materials-Page 2

MECHANICAL DATA

NKA0060A

SQA60A (Rev A)

www.ti.com

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ADC12QS065 [TI]

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