ADC12SJ800-Q1_技术文档

ADC12QJ800, ADC12DJ800, ADC12SJ800

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ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit,

Analog-to-Digital Converter (ADC) with JESD204C Interface

1 Features

2 Applications

•

ADC Core:

– Resolution: 12 Bit

– Maximum sampling rate: 800 MSPS

– Non-interleaved architecture

– Internal dither reduces high-order harmonics

Performance specifications (–1 dBFS):

– SNR (97 MHz): 57.6 dBFS

•

Light detection and ranging (LiDAR)

Handheld test equipment

Multi-channel oscilloscopes and digitizers

Wireless communications test equipment

Optical coherent tomography (OCT)

Electronic warfare (SIGINT, ELINT)

Satellite communications (SATCOM)

•

– ENOB (97 MHz): 9.0 Bits

– SFDR (97 MHz): 62 dBFS

– Noise floor (–20 dBFS): –146.1 dBFS/Hz

Full-scale input voltage: 800 mV_PP-DIFF

Full-power input bandwidth: 6 GHz

JESD204C Serial data interface:

– Support for 2 to 8 (Quad/Dual channel) or 1 to 4

(Single channel) total SerDes lanes

– Maximum baud-rate: 17.16 Gbps

– 64B/66B and 8B/10B encoding modes

– Subclass-1 support for deterministic latency

– Compatible with JESD204B receivers

Optional internal sampling clock generation

– Internal PLL and VCO (7.2–8.2 GHz)

SYSREF Windowing eases synchronization

Four clock outputs simplify system clocking

– Reference clocks for FPGA or adjacent ADC

– Reference clock for SerDes transceivers

Timestamp input and output for pulsed systems

Power consumption (800 MSPS):

3 Description

ADC12xJ800 is

a

family of quad, dual and

single channel, 12-bit, 800 MSPS analog-to-digital

converters (ADC). Low power consumption, high

sampling rate and 12-bit resolution makes the

ADC12xJ800 ideally suited for a variety of multi-

channel communications and test systems.

•

Full-power input bandwidth (-3 dB) of 6 GHz enables

direct RF sampling of of L-band and S-band.

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

•

ADC12QJ800

ADC12DJ800

ADC12SJ800

FCBGA (144) 10.0 mm × 10.0 mm

•

(1) For all available packages, see the package option

addendum at the end of the data sheet.

•

– Quad Channel: 415 mW / channel

– Dual channel: 555 mW / channel

– Single channel: 830 mW

•

Power supplies: 1.1 V, 1.9 V

Quad Channel Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC12QJ800, ADC12DJ800, ADC12SJ800

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Description (continued).................................................. 3

5 Revision History.............................................................. 3

6 Pin Configuration and Functions...................................4

7 Specifications................................................................ 11

7.1 Absolute Maximum Ratings...................................... 11

7.2 ESD Ratings............................................................. 12

7.3 Recommended Operating Conditions.......................12

7.4 Thermal Information..................................................13

7.5 Electrical Characteristics: DC Specifications............ 14

7.6 Electrical Characteristics: Power Consumption........ 16

7.7 Electrical Characteristics: AC Specifications............ 19

7.8 Timing Requirements................................................24

7.9 Switching Characteristics..........................................25

7.10 Typical Characteristics............................................27

8 Detailed Description......................................................47

8.1 Overview...................................................................47

8.2 Functional Block Diagram.........................................48

8.3 Feature Description...................................................51

8.4 Device Functional Modes..........................................71

8.5 Programming............................................................ 92

9 Application and Implementation................................132

9.1 Application Information........................................... 132

9.2 Typical Applications................................................ 132

9.3 Initialization Set Up................................................. 137

10 Power Supply Recommendations............................138

10.1 Power Sequencing................................................140

11 Layout.........................................................................141

11.1 Layout Guidelines................................................. 141

11.2 Layout Example.................................................... 142

12 Device and Documentation Support........................145

12.1 Device Support..................................................... 145

12.2 Receiving Notification of Documentation Updates145

12.3 Support Resources............................................... 145

12.4 Trademarks...........................................................145

12.5 Electrostatic Discharge Caution............................145

12.6 Glossary................................................................145

13 Mechanical, Packaging, and Orderable

Information.................................................................. 145

2

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4 Description (continued)

A number of clocking features are included to relax system hardware requirements, such as an internal phase-

locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock

outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is

provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB)

routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the

single channel device), with SerDes baud-rates up to 17.16 Gbps, to allow the optimal configuration for each

application.

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

October 2021

*

Initial release.

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6 Pin Configuration and Functions

1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

AGND

INA+

INAœ

AGND

INB+

INBœ

AGND

CALTRIG

VD11

DGND

AGND

TMSTP+

TMSTPœ

AGND

SE_CLK

SE_GND

AGND

IND+

AGND

SYNCSE

VA19

AGND

VA19

AGND

VA11

VA19

VA11

VREFO

AGND

INC+

AGND

CLKCFG0

CLKCFG1

AGND

PLLREF_SE

PLL_EN

SCS

CALSTAT

VD11

DGND

VD11

DGND

VD11

DGND

VD11

DGND

BG

ORA

D7+

D3+

AGND

VA11

ORB

D7œ

D3œ

AGND

VA11

ORC

D6+

D2+

CLK+

VA11

AGND

VA11

AGND

SCLK

ORD

D6œ

D2œ

G

H

J

CLKœ

VA11

AGND

VA11

AGND

SDI

SDO

D5+

D1+

AGND

VA11

AGND

VA11

AGND

VD11

D5œ

D1œ

SYSREF+

SYSREFœ

AGND

PGND

TDIODE+

AGND

INDœ

VPLL19

TDIODEœ

AGND

VPLL19

PGND

AGND

PLLREFO+

PLLREFOœ

AGND

VTRIG

AGND

TRIGOUT+

TRIGOUTœ

DGND

PD

D4+

D0+

K

L

D4œ

D0œ

DGND

M

AGND

INCœ

DGND

Not to scale

Figure 6-1. Quad Channel AAV Package, 144-Ball Flip Chip BGA (Top View)

4

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1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

AGND

INA+

INAœ

AGND

INB+

INBœ

AGND

CALTRIG

VD11

DGND

AGND

TMSTP+

TMSTPœ

AGND

SE_CLK

SE_GND

AGND

DNC

AGND

SYNCSE

VA19

AGND

VA19

AGND

VA11

VA19

VA11

VREFO

AGND

DNC

AGND

CLKCFG0

CLKCFG1

AGND

PLLREF_SE

PLL_EN

SCS

CALSTAT

VD11

DGND

VD11

DGND

VD11

DGND

VD11

DGND

BG

ORA

D7+

D3+

AGND

VA11

ORB

D7œ

D3œ

AGND

VA11

ORC

D6+

D2+

CLK+

VA11

AGND

VA11

AGND

SCLK

ORD

D6œ

D2œ

G

H

J

CLKœ

VA11

AGND

VA11

AGND

SDI

SDO

D5+

D1+

AGND

VA11

AGND

VA11

AGND

VD11

D5œ

D1œ

SYSREF+

SYSREFœ

AGND

PGND

TDIODE+

AGND

DNC

VPLL19

TDIODEœ

AGND

VPLL19

PGND

AGND

PLLREFO+

PLLREFOœ

AGND

VTRIG

AGND

TRIGOUT+

TRIGOUTœ

DGND

PD

D4+

D0+

K

L

D4œ

D0œ

DGND

M

AGND

DNC

DGND

Not to scale

Figure 6-2. Dual Channel AAV Package, 144-Ball Flip Chip BGA (Top View)

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1

2

3

4

5

6

7

8

9

10

11

12

A

B

C

D

E

F

AGND

INA+

INAœ

AGND

DNC

AGND

CALTRIG

VD11

DGND

D3+

AGND

TMSTP+

TMSTPœ

AGND

SE_CLK

SE_GND

AGND

DNC

AGND

SYNCSE

VA19

AGND

VA19

AGND

VA11

VA19

VA11

VREFO

AGND

DNC

AGND

CLKCFG0

CLKCFG1

AGND

PLLREF_SE

PLL_EN

SCS

CALSTAT

VD11

DGND

VD11

DGND

VD11

DGND

VD11

DGND

DNC

DGND

BG

ORA

AGND

VA11

ORB

D3œ

AGND

VA11

ORC

D2+

CLK+

VA11

AGND

VA11

AGND

SCLK

ORD

D2œ

G

H

J

CLKœ

VA11

AGND

VA11

AGND

SDI

SDO

D1+

AGND

VA11

AGND

VA11

AGND

VD11

D1œ

SYSREF+

SYSREFœ

AGND

PGND

TDIODE+

AGND

DNC

VPLL19

TDIODEœ

AGND

VPLL19

PGND

AGND

PLLREFO+

PLLREFOœ

AGND

VTRIG

AGND

TRIGOUT+

TRIGOUTœ

DGND

PD

D0+

K

L

D0œ

DGND

M

AGND

DNC

DGND

Not to scale

Figure 6-3. Single Channel AAV Package, 144-Ball Flip Chip BGA (Top View)

Table 6-1. Pin Functions

I/O

DESCRIPTION

NO.

NAME

A1, A4, A5, A8,

B1, B2, B3, B4,

B5, B6, B7, B8,

C2, C5, C6, D2,

D3, E1, E2, E4,

E7, F4, F7, G4,

G7, H1, H2, H4,

H7, J2, K2, L1,

L2, L3, L4, L5,

L6, L7, L8, M1,

M4, M5, M8

Analog supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit

board.

AGND

—

6

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Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads,

as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used.

C3

BG

O

Foreground calibration status output or device alarm output. Functionality is programmed through

CAL_STATUS_SEL. This pin can be left disconnected if not used.

B9

A9

CALSTAT

CALTRIG

Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in

CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not

used.

I

Device (sampling) clock negative input or differential PLL reference clock negative input. TI strongly

recommends using AC-coupling for best performance. This pin can be left disconnected if SE_CLK is used

to apply the reference clock.

G1

CLK–

Device (sampling) clock positive input or differential PLL reference clock negative input. The clock signal is

strongly recommended to be AC-coupled to this input for best performance. This differential input has an

internal 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as

DEVCLK_LVPECL_EN is set to 0. This pin can be left disconnected if SE_CLK is used to apply the reference

clock when the PLL is used.

F1

C7

CLK+

I

CLKCFG0 and CLKCFG1 can be used enable additional clock outputs on ORC and ORD when the C-PLL is

used (PLL_EN is set high). Tie this pin to ground if not used.

CLKCFG0

CLKCFG0 and CLKCFG1 can be used enable additional clock outputs on ORC and ORD when the C-PLL is

used (PLL_EN is set high). Tie this pin to ground if not used.

D7

CLKCFG1

D0–

I

K12

O

High-speed serialized data output for lane 0, negative connection. This pin can be left disconnected if not used.

High-speed serialized data output for lane 0, positive connection. This differential output must be AC-coupled

and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left

disconnected if not used.

J12

D0+

D1–

D1+

D2–

D2+

D3–

D3+

O

H12

G12

F12

E12

D12

C12

High-speed serialized data output for lane 1, negative connection. This pin can be left disconnected if not used.

High-speed serialized data output for lane 1, positive connection. This differential output must be AC-coupled

and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left

disconnected if not used.

High-speed serialized data output for lane 2, negative connection. This pin can be left disconnected if not used.

High-speed serialized data output for lane 2, positive connection. This differential output must be AC-coupled

and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left

disconnected if not used.

High-speed serialized data output for lane 3, negative connection. This pin can be left disconnected if not used.

High-speed serialized data output for lane 3, positive connection. This differential output must be AC-coupled

and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left

disconnected if not used.

High-speed serialized data output for lane 4, negative connection. Not used for single channel devices. This pin

can be left disconnected if not used.

K11

J11

D4-

D4+

D5-

D5+

D6-

D6+

D7-

D7+

O

High-speed serialized data output for lane 4, positive connection. Not used for single channel devices. This

differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for lane 5, negative connection. Not used for single channel devices. This pin

can be left disconnected if not used.

H11

G11

F11

E11

D11

C11

High-speed serialized data output for lane 5, positive connection. Not used for single channel devices. This

differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for lane 6, negative connection. Not used for single channel devices. This pin

can be left disconnected if not used.

High-speed serialized data output for lane 6, positive connection. Not used for single channel devices. This

differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

High-speed serialized data output for lane 7, negative connection. Not used for single channel devices. This pin

can be left disconnected if not used.

High-speed serialized data output for lane 7, positive connection. Not used for single channel devices. This

differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at

the receiver. This pin can be left disconnected if not used.

A11, A12, B11,

B12, C10, F10,

G10, K10, L9,

L11, L12, M11,

M12

Digital supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit

board.

DGND

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Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Channel A analog input negative connection for quad, dual and single channel devices. See INA+ for

detailed description. This input is terminated to VA11 through a 50-Ω termination resistor. This pin can be

left disconnected if not used.

A3

INA–

I

Channel A analog input positive connection for quad, dual and single channel devices. The differential full-scale

input voltage is determined by the FS_RANGE register (see the Full-Scale Voltage (VFS) Adjustment section).

This input is terminated to VA11 through a 50-Ω termination resistor. The input common-mode voltage is

internally self-biased to VA11 (1.1 V nominally) and must follow the recommendations in the Recommended

Operating Conditions table. This input can be AC coupled to the source if DC signals are not required. If

DC signals are required then a DC-coupled fully differential driving amplifier must be used with its output

common-mode voltage set to the VA11 supply voltage. This pin can be left disconnected if not used.

A2

A7

INA+

INB–

I

Channel B analog input negative connection for quad and dual channel devices. Do not connect for single

channel device. See INB+ for detailed description. This input is terminated to VA11 through a 50-Ω termination

resistor. This pin can be left disconnected if not used.

Channel B analog input positive connection for quad and dual channel devices. Do not connect for single

channel device. The differential full-scale input voltage is determined by the FS_RANGE register (see the

Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50-Ω termination

resistor. The input common-mode voltage is internally self-biased to VA11 (1.1 V nominally) and must follow

the recommendations in the Recommended Operating Conditions table. This input can be AC coupled to the

source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving

amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left

disconnected if not used.

A6

INB+

INC–

INC+

IND–

IND+

I

Channel C analog input negative connection for quad channel device. Do not connect for single and dual

channel devices. See INC+ for detailed description. This input is terminated to VA11 through a 50-Ω termination

resistor. This pin can be left disconnected if not used.

M7

M6

M3

M2

Channel C analog input positive connection for quad channel device. Do not connect for single and dual

channel devices. The differential full-scale input voltage is determined by the FS_RANGE register (see the

Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50-Ω termination

resistor. The input common-mode voltage is internally self-biased to VA11 (1.1 V nominally) and must follow

the recommendations in the Recommended Operating Conditions table. This input can be AC coupled to the

source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving

amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left

disconnected if not used.

Channel D analog input negative connection for quad channel device. Do not connect for single and dual

channel devices. See IND+ for detailed description. This input is terminated to VA11 through a 50-Ω termination

resistor. This pin can be left disconnected if not used.

Channel D analog input positive connection for quad channel device. Do not connect for single and dual

channel devices. The differential full-scale input voltage is determined by the FS_RANGE register (see the

Full-Scale Voltage (VFS) Adjustment section). This input is terminated to VA11 through a 50-Ω termination

resistor. The input common-mode voltage is internally self-biased to VA11 (1.1 V nominally) and must follow

the recommendations in the Recommended Operating Conditions table. This input can be AC coupled to the

source if DC signals are not required. If DC signals are required then a DC-coupled fully differential driving

amplifier must be used with its output common-mode voltage set to the VA11 supply voltage. This pin can be left

disconnected if not used.

Fast over-range detection status output for channel A. When the analog input for channel A exceeds the

threshold programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by

OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not

used.

C9

D9

ORA

ORB

O

Fast over-range detection status output for channel B. Only used for quad and dual channel devices. Do not

connect for single channel device. When the analog input for channel B exceeds the threshold programmed into

OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange

Detection section for more information. This pin can be left disconnected if not used.

Fast over-range detection status output for channel C or additional clock output. The fast over-range detection

function is only available for quad channel device. When the analog input for channel C exceeds the threshold

programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See

the ADC Overrange Detection section for more information. This pin can alternatively be used as an additional

clock output (DIVREF_C) when enabled by CLKCFG[1:0] or through the SPI register configuration and when

PLL_EN is high. When CLKCFG0 and CLKCFG1 are both set low (or disabled through SPI) the ORC output

is used to output the over-range signal for ADC channel C.ORC can be programmed as a copy of PLLREFO

(CLKCFG[1:0] = 0x1) or as a divide-by-2 (CLKCFG[1:0] = 0x2) or divide-by-4 (CLKCFG[1:0] = 0x3) copy

of PLLREFO. The clock at ORC is available at device power up if PLL_EN is set high, PD is set low and

CLKCFG[1:0] are configured appropriately. This pin can be left disconnected if not used.

E9

ORC

O

8

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Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

Fast over-range detection status output for channel D or additional clock output. The fast over-range detection

function is only available for quad channel device. When the analog input for channel D exceeds the threshold

programmed into OVR_T, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the

ADC Overrange Detection section for more information. This pin can alternatively be used as an additional clock

output (DIVREF_D) when enabled by CLKCFG[1:0] or through the SPI register configuration and when PLL_EN

is high. When CLKCFG0 and CLKCFG1 are both set low (or disabled through SPI) the ORD output is used to

output the over-range signal for ADC channel D.ORD can be programmed as a copy of PLLREFO when any or

both of CLKCFG[1:0] are set which will be available at startup if PLL_EN is set high and PD is held low. ORD

can be set as a divide-by-2 or divide-by-4 copy of PLLREFO when overridden through the SPI register. A clock

out of ORD is only available if a clock is also output from ORC. If only one clock is required then use ORC. This

pin can be left disconnected if not used.

F9

ORD

O

CMOS input to power down the device for power savings or temperature diode calibration. Setting PD high

disables PLLREFO and the ORC and ORD clock outputs and therefore this pin should not be used if these

clocks are critical for system operation. Tie this pin to GND if not used.

M9

PD

I

PLL supply ground. Tie AGND, PGND, SE_GND and DGND to a common ground plane (GND) on the circuit

board.

J3, K5

D8

PGND

—

I

CMOS input to enable the internal PLL for sampling clock generation if set high or to disable and bypass the

PLL if set low. Tie this pin to GND if PLL is not used.

PLL_EN

CMOS input to select the single-ended PLL reference clock input (SE_CLK) if set high or the differential clock

input (CLK±) if set low. Only CLK± can be used for the sampling clock if the PLL is disabled. Tie this pin to GND

if the PLL is not used or if CLK± is used as the reference clock input.

C8

K7

J7

PLLREF_SE

PLLREFO–

PLLREFO+

SCLK

I

Negative LVDS PLL reference clock output. The clock is repeated from the selected PLL reference clock input

(CLK± or SE_CLK). It is available at device power up to clock other devices when PLL_EN is set high and PD is

held low. This pin can be left disconnected if not used.

O

I

Positive LVDS PLL reference clock output. The clock is repeated from the selected PLL reference clock input

(CLK± or SE_CLK). It is available at device power up to clock other devices when PLL_EN is set high and PD is

held low. This pin can be left disconnected if not used.

Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming

data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports

1.1-V to 1.9-V CMOS levels.

F8

Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface

in more detail. Supports 1.1-V to 1.9-V CMOS levels. This pin has a 82-kΩ pull-up resistor to VD11.

E8

G8

SCS

SDI

I

Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail.

Supports 1.1-V to 1.9-V CMOS levels.

Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail.

This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial

interface read operations. This pin can be left disconnected if not used.

G9

SDO

O

Single-ended PLL reference clock input. This input is selected when PLL_EN is held high and PLLREF_SE is

held high. When PLLREF_SE is set low, CLK± is used as the differential PLL reference input. This pin should be

tied to GND if not used.

F2

SE_CLK

SE_GND

I

Ground reference for single-ended PLL reference clock input. Tie AGND, PGND, SE_GND and DGND to a

common ground plane (GND) on the circuit board.

G2

—

Single-ended JESD204C SYNC signal. This input is an active low input that is used to initialize the JESD204C

serial link in 8B/10B modes when SYNC_SEL is set to 0. The 64B/66B modes do not use the SYNC signal.

When toggled low in 8B/10B modes this input initiates code group synchronization (see the Code Group

Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the

initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). Tie this pin to ground

if TMSTP± or JSYNC_N is used as the JESD204C SYNC signal or for 64B/66B encoded JESD204C modes.

C4

K1

SYNCSE

I

SYSREF negative input. Leave this pin disconnected if not used and power down the SYSREF± receiver using

SYSREF_RECV_EN.

SYSREF–

The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204C

interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential

termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when

SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+

and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased

when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range

provided in the Recommended Operating Conditions table. Leave this pin disconnected if not used and power

down the SYSREF± receiver using SYSREF_RECV_EN.

J1

SYSREF+

I

K4

K3

TDIODE–

TDIODE+

I

Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.

Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+

and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.

Timestamp input negative connection. This pin can be left disconnected and the TMSTP receiver powered down

(TMSTP_RECV_EN = 0) if timestamp is not required.

D1

TMSTP–

I

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Table 6-1. Pin Functions (continued)

I/O

DESCRIPTION

NO.

NAME

Timestamp input positive connection. This input is a timestamp input, used to mark a specific sample, when

TIME_STAMP_EN is set to 1. For additional usage information, see the Timestamp section.

TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an

internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0.

The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled

when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for

both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the

Recommended Operating Conditions table when both AC and DC coupled. Can also be used as a differential

SYNC input for the JESD204C interface with 8b/10b encoding. This pin can be left disconnected and the

TMSTP receiver powered down (TMSTP_RECV_EN = 0) if timestamp is not required.

C1

TMSTP+

I

Negative LVDS output for trigger repeated from TMSTP± or clock output generated from the SerDes PLL. This

output can be enabled by setting TRIGOUT_EN to 1 and configured by TRIGOUT_MODE. Setting the PD pin

high disables this output. This pin can be left disconnected if not used.

K9

J9

TRIGOUT–

TRIGOUT+

O

Positive LVDS output for trigger repeated from TMSTP± or clock output generated from the SerDes PLL. This

output can be enabled by setting TRIGOUT_EN to 1 and configured by TRIGOUT_MODE. Setting the PD pin

high disables this output. This pin can be left disconnected if not used.

D6, E3, E5, F3,

F5, G3, G5, H3,

H5, J6

VA11

VA19

—

1.1-V analog supply

1.9-V analog supply

D4, D5, E6, F6,

G6, H6

A10, B10, D10,

E10, H8, H9,

H10, J10, L10,

M10

VD11

—

1.1-V digital supply

J4, J5

K6

VPLL19

VREFO

VTRIG

—

1.9-V supply for internal PLL and VCO

1.9-V supply for PLLREFO± output driver and PLL charge pump

1.1-V to 1.9-V supply for TRIGOUT± output driver

J8, K8

10

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

2.35

UNIT

VA19⁽²⁾

VPLL19⁽³⁾

VREFO⁽²⁾

2.35

VTRIG⁽⁵⁾

2.35

Supply voltage range

V

VA11⁽²⁾

VD11⁽⁵⁾

1.32⁽¹¹⁾

Voltage difference between any 1.9 V supply (VA19,

VPLL19 or VREFO)

–0.5

–0.1

0.5

0.1

Voltage between AGND, DGND, PGND and SE_GND

V

D[7:0]+, D[7:0]–, TMSTP+, TMSTP–⁽⁵⁾

CLK+, CLK–, SYSREF+, SYSREF–⁽²⁾

SE_CLK⁽⁴⁾

–0.5 VD11 + 0.5⁽⁷⁾

–0.5 VA11 + 0.5⁽⁶⁾

–0.5 VA19 + 0.5⁽⁸⁾

VREFO +

PLLREFO+, PLLREFO–⁽²⁾

–0.5

0.5⁽⁹⁾

VTRIG +

TRIGOUT+,TRIGOUT–⁽⁵⁾

–0.5

0.5⁽¹⁰⁾

Pin voltage range

V

BG, TDIODE+, TDIODE–⁽²⁾

–0.5 VA19 + 0.5⁽⁸⁾

VA11

– 1.0

VA11

+ 1.0

INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–⁽²⁾

CALSTAT, CALTRIG, CLKCFG0, CLKCFG1,

PLL_EN, PLLREF_SE, ORA, ORB, ORC, ORD, PD,

SCLK, SCS, SDI, SDO, SYNCSE ⁽²⁾

–0.5 VA19 + 0.5⁽⁸⁾

Peak input current (any input except INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–)

Peak input current (INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–)

–25

–50

25

50

mA

Peak RF input power (INA+, INA–, INB+, INB–, INC+,

Single-ended with Z_S-SE= 50 Ω

16.4

100

dBm

mA

INC–, IND+, IND–)

Peak total input current (sum of absolute value of all currents forced in or out, not including power-supply

current)

Operating junction temperature, T_j

Storage temperature, T_stg

–40

–65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Measured to AGND.

(3) Measured to PGND.

(4) Measured to SE_GND.

(5) Measured to DGND.

(6) Maximum voltage not to exceed VA11 absolute maximum rating.

(7) Maximum voltage not to exceed VD11 absolute maximum rating.

(8) Maximum voltage not to exceed VA19 absolute maximum rating.

(9) Maximum voltage not to exceed VREFO absolute maximum rating.

(10) Maximum voltage not to exceed VTRIG absolute maximum rating.

(11) The 1.1-V supplies (VA11, VD11) must not be more than 0.5 V above any of the 1.9-V supplies (VA19, VPLL19, VREFO) or VTRIG

(1.1 V or 1.9 V) during power up, normal operation or power down. See Power Sequencing section.

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7.2 ESD Ratings

VALUE

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_(ESD)

Electrostatic discharge

V

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

NOM

1.9

MAX

2.0

UNIT

VA19, analog 1.9-V supply⁽²⁾

VPLL19, PLL supply⁽³⁾

1.8

1.9

2.0

VREFO, PLLREFO± and PLL charge pump

supply⁽²⁾

1.8

1.9

2.0

V_DD

Supply voltage range

V

VTRIG, TRIGOUT± supply⁽⁴⁾

VA11, analog 1.1-V supply⁽²⁾

VD11, digital 1.1-V supply⁽⁴⁾

1.05 1.1 or 1.9

2.0

1.15

1.05

1.1

INA+, INA–, INB+, INB–, INC+, INC–, IND+,

IND–⁽²⁾

1.05

1.1

1.15

V_CMI

Input common-mode voltage

V

CLK+, CLK–, SYSREF+, SYSREF–^{(2) (5)}

TMSTP+, TMSTP–^{(4) (6)}

0

0.3

0.55

CLK+ to CLK–, SYSREF+ to SYSREF–,

TMSTP+ to TMSTP–

0.4

1.0

2.0

V_ID(DIFF)

Input voltage, peak-to-peak differential

V_PP-DIFF

INA+, INA–, INB+, INB–, INC+, INC–, IND+,

IND–

1.0⁽⁷⁾

V_IH

V_IL

I_{C_TD}

C_L

High-level input voltage

SE_CLK

0.9

1.8

0

V

Low-level input voltage

SE_CLK

0.3

50

V

Temperature diode input current

BG maximum load capacitance

BG maximum output current

Operating free-air temperature

Operating junction temperature

TDIODE+ to TDIODE–

100

µA

pF

µA

°C

I_O

Current at -2% drop from nominal voltage

140

T_A

–40

85

Tj

125⁽¹⁾

(1) Prolonged use above a junction temperature of 105°C may increase the device failure-in-time (FIT) rate.

(2) Measured to AGND.

(3) Measured to PGND.

(4) Measured to DGND.

(5) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input

common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which

case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).

(6) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN

= 0 or DC-coupled with TMSTP_LVPECL_EN= 1.

(7) The ADC output code saturates when V_IDfor INA± or INB± exceeds the programmed full-scale voltage(V_FS) set by FS_RANGE_A for

INA± or FS_RANGE_B for INB±.

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7.4 Thermal Information

ADC12xJ800

THERMAL METRIC⁽¹⁾

AAV (FCBGA)

144 PINS

20.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

1.0

Junction-to-board thermal resistance

6.54

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance (n/a)

0.21

ψ_JB

6.52

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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7.5 Electrical Characteristics: DC Specifications

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

Resolution

Resolution with no missing codes

12

0.2

Bits

Maximum positive excursion from ideal step size

Maximum negative excursion from ideal step size

DNL

Differential nonlinearity

LSB

–0.19

Maximum positive excursion from ideal transfer

function

1.9

INL

Integral nonlinearity

LSB

Maximum negative excursion from ideal transfer

function

–1.6

ANALOG INPUTS (INA+, INA–, INB+, INB–, INC+, INC–, IND+, IND–)

CAL_OS = 0

±0.4

mV

V_OFF

Offset error

CAL_OS = 1

Input offset voltage adjustment

range

Available offset correction range (see OFSx or

OFSxCh registers)

V_{OFF_ADJ}

±33

-1.2

mV

Foreground calibration at nominal temperature only,

CAL_OS = 1

V_{OFF_DRIFT}

Offset drift

µV/°C

Foreground calibration at each temperature,

CAL_OS = 1

0.25

800

Default full-scale voltage (FS_RANGE = 0xA000),

measured at DC

750

980

850

500

Analog differential input full-scale

range

Maximum full-scale voltage (FS_RANGE =

0xFFFF), measured at DC

V_FS

1040

480

mV_PPDIFF

%/°C

Ω

Minimum full-scale voltage (FS_RANGE = 0x2000),

measured at DC

Default FS_RANGE setting, foreground calibration

at nominal temperature only, inputs driven by a 50-Ω

source, includes effect of R_INdrift

–0.0015

-.000018

Analog differential input full-scale

range drift

V_{FS_DRIFT}

Default FS_RANGE setting, foreground calibration

at each temperature, inputs driven by a 50-Ω

source, includes effect of R_INdrift

Analog differential input full-scale

range matching

Matching between any two channels (e.g. INA± and

INB±), default full-scale voltage, measured at DC

V_{FS_MATCH}

R_IN

1%

Center of differential resistance is terminated to

V_CM, measured at T_A= 25°C

Differential input resistance

92

100

108

R_{IN_TEMPCO}

C_IN

TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)

Forced forward current of 100 µA. Offset voltage

Input termination linear temperature coefficient

38

mΩ/°C

pF

Single-ended input capacitance Measured at DC

0.6

(approximately 0.792 V at 0°C) varies with process

and must be measured for each part. Offset

measurement must be done with the device

unpowered or with the PD pin asserted to minimize

device self-heating.

ΔV_BE

Temperature diode voltage slope

–1.6

mV/°C

BAND-GAP VOLTAGE OUTPUT (BG)

Internal band-gap reference and

V_CMreference output voltage

V_BG

I_L≤ 100 µA

1.1

V

V_{BG_DRIFT}

V_BGoutput temperature drift

–117

µV/°C

DIFFERENTIAL CLOCK AND TIMESTAMP INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)

Differential termination with DEVCLK_LVPECL_EN

= 0, SYSREF_LVPECL_EN = 0, and

TMSTP_LVPECL_EN = 0

100

50

Z_T

Internal termination

Ω

Single-ended termination to GND (per pin) with

DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN

= 0, and TMSTP_LVPECL_EN = 0

14

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7.5 Electrical Characteristics: DC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Self-biasing common-mode voltage for CLK± when

AC-coupled (DEVCLK_LVPECL_EN must be set to

0)

0.3

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must

be set to 0) and with receiver enabled

(SYSREF_RECV_EN = 1)

Input common-mode voltage, self-

biased

0.3

V_CM

V

Self-biasing common-mode voltage for SYSREF±

when AC-coupled (SYSREF_LVPECL_EN must

be set to 0) and with receiver disabled

(SYSREF_RECV_EN = 0)

VA11

C_{L_DIFF}

C_{L_SE}

Differential input capacitance

Single-ended input capacitance

Between positive and negative differential input pins

Each input to ground

0.1

0.5

pF

CLOCK AND TRIGGER OUTPUTS (PLLREFO+, PLLREFO–, TRIGOUT+, TRIGOUT–)

Differential output voltage, peak-to-

peak, DC measurement

V_DIFF

100Ω load

400

720

900 mV_PP-DIFF

V

V_CM(PLLREFO)

PLLREFO± output common-mode voltage

1.31⁽¹⁾

1.31⁽²⁾

0.5⁽²⁾

300

VTRIG = 1.9

TRIGOUT± output common-mode

voltage, tracks with VTRIG

V_CM(TRIGOUT)

V

VTRIG = 1.1

Z_DIFF

Differential output impedance

Measured at DC

Ω

SERDES OUTPUTS (D[7:0]+, D[7:0]–)

Differential output voltage, peak-to-

peak

V_OD

100-Ω load

AC coupled

600

mV_PP-DIFF

V_CM

Output common-mode voltage

Differential output impedance

0.54

100

V

Z_DIFF

Ω

CMOS INTERFACE (SCLK, SDI, SDO, SCS, PD, CALSTAT, CALTRIG, CLKCFG0, CLKCFG1, PLL_EN, PLLREF_SE, ORA, ORB, ORC, ORD, SYNCSE)

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

0.7

V

0.45

40

µA

pF

V

I_IL

–40

C_I

2

V_OH

V_OL

High-level output voltage

Low-level output voltage

I_LOAD= –400 µA

I_LOAD= 400 µA

1.65

150

mV

(1) TI recommends AC-coupling PLLREFO± to the load device when PLLREFO± is enabled.

(2) TI recommends AC-couping TRIGOUT± to the load device when TRIGOUT± is enabled and used as a clock output (from S-PLL).

TRIGOUT± can be DC-coupled to the load device when TRIGOUT± is used as a trigger output (from TMSTP±).

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7.6 Electrical Characteristics: Power Consumption

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

655

0

MAX

UNIT

mA

W

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 1a: Quad channel, JMODE

0 (12-bit, 8 lanes, 8B/10B encoding), FG

calibration, PLL_EN = 0, f_S= 0.8 GSPS,

High Performance Mode

0

465

395

2.18

390

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 1b: Dual channel, JMODE

0 (12-bit, 4 lanes, 8B/10B encoding), FG

calibration, PLL_EN = 0,0.8 GSPS, High

Performance Mode

0

350

250

1.41

253

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 1c: Single channel, JMODE

0 (12-bit, 2 lanes, 8B/10B encoding), FG

calibration, PLL_EN = 0, f_S= 0.8 GSPS,

High Performance Mode

0

316

160

1.01

565

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 2a: Quad channel, JMODE

8 (12-bit, 4 lanes, 64B/66B encoding),

LPBG calibration, PLL_EN = 0, f_S= 0.8

GSPS, Low Power Mode

0

355

330

1.83⁽¹⁾

345

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 2b: Dual channel, JMODE

8 (12-bit, 2 lanes, 64B/66B encoding),

LPBG calibration, PLL_EN = 0, f_S= 0.8

GSPS, Low Power Mode

0

306

198

1.19⁽¹⁾

235

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 2c: Single channel, JMODE

8 (12-bit, 1 lanes, 64B/66B encoding),

LPBG calibration, PLL_EN = 0, f_S= 0.8

GSPS, Low Power Mode

0

283

146

0.92⁽¹⁾

I_VD11

P_DIS

16

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7.6 Electrical Characteristics: Power Consumption (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

565

60

MAX

UNIT

mA

W

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 3a: Quad channel,

JMODE 8 (12-bit, 4 lanes, 64B/66B

encoding), LPBG calibration, PLL_EN =

1, PLLREF_SE = 1, f_REF= 50 MHz,

TRIGOUT± enabled, f_S= 0.8 GSPS, Low

Power Mode

13

5.5

340

328

1.96⁽¹⁾

345

59

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 3b: Dual channel,

JMODE 8 (12-bit, 2 lanes, 64B/66B

encoding), LPBG calibration, PLL_EN =

1, PLLREF_SE = 1, f_REF= 50 MHz,

TRIGOUT± enabled, f_S= 0.8 GSPS, Low

Power Mode

13

5.5

290

198

1.34⁽¹⁾

236

60

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 3c: Single channel,

JMODE 8 (12-bit, 1 lanes, 64B/66B

encoding), LPBG calibration, PLL_EN =

1, PLLREF_SE = 1, f_REF= 50 MHz,

TRIGOUT± enabled, f_S= 0.8 GSPS, Low

Power Mode

13

5.5

270

146

1.05⁽¹⁾

543

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 4a: Quad channel, JMODE

7 (8-bit, 4 lanes, 64B/66B encoding), FG

calibration, PLL_EN = 0, f_S= 0.8 GSPS,

Low Power Mode

0

333

247

1.66

333

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 4b: Dual channel, JMODE

7 (8-bit, 2 lanes, 64B/66B encoding), FG

calibration, PLL_EN = 0, f_S= 0.8 GSPS,

Low Power Mode

0

285

149

1.11

225

0

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 4c: Single channel, JMODE

7 (8-bit, 1 lanes, 64B/66B encoding), FG

calibration, PLL_EN = 0, f_S= 0.8 GSPS,

Low Power Mode

0

260

110

0.83

I_VD11

P_DIS

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7.6 Electrical Characteristics: Power Consumption (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

804

60

MAX

UNIT

mA

W

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 5a: Quad channel, JMODE

0 (12-bit, 8 lanes, 8B/10B encoding), BG

calibration, PLL_EN = 1, PLLREF_SE = 0,

f_REF= 50 MHz, TRIGOUT± enabled, f_S

0.8 GSPS, High Performance Mode

13

5.5

527

389

2.67

526

59

=

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 5b: Dual channel, JMODE

0 (12-bit, 4 lanes, 8B/10B encoding), BG

calibration, PLL_EN = 1, PLLREF_SE =

0, f_REF= 50 MHz, TRIGOUT± enabled, 0.8

GSPS, High Performance Mode

13

5.5

395

248

1.86

386

59

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

Power mode 5c: Single channel, JMODE

0 (12-bit, 2 lanes, 8B/10B encoding), BG

calibration, PLL_EN = 1, PLLREF_SE = 0,

f_REF= 50 MHz, TRIGOUT± enabled, f_S

0.8 GSPS, High Performance Mode

13

5.5

370

158

1.46

47

=

I_VD11

P_DIS

I_VA19

1.9-V analog supply current

PLL analog supply current

PLLREFO± analog supply current

TRIGOUT± analog supply current

1.1-V analog supply current

1.1-V digital supply current

Power dissipation

mA

W

I_VPLL19

I_VREFO

I_VTRIG

I_VA11

0

Power mode 6: Power-down enabled (PD

= 1)

0

35

I_VD11

33

P_DIS

0.155

(1) Low-power background (LPBG) calibration supply current and power dissipation numbers are in the calibration sleep state. The power

dissipation in this mode increases to the background (BG) calibration power consumption during the calibration state. The sleep period

can be controlled by the user and long sleep periods will average out the calibration state power dissipation contribution.

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7.7 Electrical Characteristics: AC Specifications

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Foreground calibration

6

Full-power input bandwidth

(–3 dB)⁽¹⁾

FPBW

XTALK

GHz

Background calibration

6

Channel-to-channel

crosstalk

(Quad and dual channel

only)

Aggressor = 400 MHz, –1 dBFS

Aggressor = 1 GHz, –1 dBFS

Aggressor = 3 GHz, –1 dBFS

–81

–68

–59

dB

Maximum CER, does not include JESD204C interface

BER

Errors/

sample

CER

Code error rate

10^–18

Time from an overdriven input to accurate conversion

after a step from a ±1.2 V_PP-DIFFoverdriven input

t_ORR

Overrange recovery time

1

t_CLKcycles

LSB

stepped to 0 V_PP-DIFF

.

DC input noise standard

deviation

NOISE_DC

No input, foreground calibration, excludes DC offset

1.8

–146.1

–144.7

29.3

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20

dBFS

NSD

NF

Noise spectral density

dBFS/Hz

dB

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20

dBFS

Maximum full-scale voltage (V_FS= 1.0 V_PP), A_IN= –20

dBFS

Noise figure, Z_S= 100 Ω

Default full-scale voltage (V_FS= 0.8 V_PP), A_IN= –20

dBFS

27.9

A_IN= –1 dBFS

57.6

57.8

58.2

58.8

57.6

57.8

58.1

57.3

57.7

57.4

57.7

57.0

57.3

58.0

56.1

56.9

57.9

55.6

56.3

57.8

A_IN= –3 dBFS

f_IN= 97 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

54

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

Signal-to-noise ratio,

excluding DC, HD2 to HD9

SNR

dBFS

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

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7.7 Electrical Characteristics: AC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

55.7

56.8

58.1

57.7

56.4

57.1

58.0

56.0

56.7

58.1

57.7

55.3

56.3

57.9

51.9

55.0

57.8

48.5

52.9

57.7

9.0

MAX

UNIT

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 97 MHz

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

53

A_IN= –3 dBFS

Signal-to-noise and

distortion ratio, excluding

DC offset

A_IN= –12 dBFS

SINAD

dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

A_IN= –3 dBFS

f_IN= 97 MHz

9.1

A_IN= –12 dBFS

9.4

A_IN= –3 dBFS, V_FS= 1.0 V_PP

9.3

A_IN= –1 dBFS

9.1

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –3 dBFS

9.2

A_IN= -12 dBFS

A_IN= –1 dBFS

9.3

8.5

9

A_IN= –3 dBFS

9.1

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

9.4

Effective number of bits,

excluding DC offset

ENOB

bits

9.3

8.9

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

9.1

9.3

A_IN= –1 dBFS

8.3

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

8.8

9.3

A_IN= –1 dBFS

7.8

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

8.5

9.3

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7.7 Electrical Characteristics: AC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

A_IN= –1 dBFS

62

A_IN= –3 dBFS

66

f_IN= 97 MHz

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –12 dBFS

79

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

67

64

A_IN= –3 dBFS

68

A_IN= –12 dBFS

77

A_IN= –1 dBFS

58

65

A_IN= –3 dBFS

66

A_IN= –12 dBFS

79

Spurious-free dynamic

range

SFDR

dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

68

63

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

66

77

A_IN= –1 dBFS

55

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

61

77

A_IN= –1 dBFS

50

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

57

77

AIN = –1 dBFS

–63

–67

–80

–72

–66

–65

–81

–65

–69

–81

–70

–64

–66

–77

–60

–64

–78

–59

–64

–79

A_IN= –3 dBFS

f_IN= 97 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

–58

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

2nd-order harmonic

distortion

HD2

dBFS

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

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7.7 Electrical Characteristics: AC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–65

–73

–89

–68

–69

–75

–85

–68

–72

–86

–70

–64

–71

–86

–55

–62

–89

–50

–57

–83

–73

–77

–84

–73

–77

–80

–83

–76

–80

–84

–78

–76

–77

–83

–75

–78

–84

–74

–76

–83

MAX

UNIT

AIN = –1 dBFS

A_IN= –3 dBFS

f_IN= 97 MHz

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

–58

A_IN= –3 dBFS

A_IN= –12 dBFS

3rd-order harmonic

distortion

HD3

dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

AIN = –1 dBFS

A_IN= –3 dBFS

f_IN= 97 MHz

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

f_IN= 497 MHz

f_IN= 997 MHz

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

–65

A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –3 dBFS, V_FS= 1.0 V_PP

A_IN= –1 dBFS

Worst spur, excluding DC,

HD2, HD3

SPUR

dBFS

f_IN= 1797 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 2697 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

A_IN= –1 dBFS

f_IN= 3497 MHz A_IN= –3 dBFS

A_IN= –12 dBFS

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7.7 Electrical Characteristics: AC Specifications (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1

V, default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK= 800 MHz, filtered 1 V_PPsine-wave clock

applied to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration (unless otherwise noted);

minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in

the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–83

–87

–88

–83

–89

–77

–82

–87

–80

–66

–73

–91

–57

–63

–89

–50

–57

–84

MAX

UNIT

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –9 dBFS per tone, V_FS= 1.0 V_PP

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

A_IN= –7 dBFS per tone

A_IN= –9 dBFS per tone

A_IN= –18 dBFS per tone

f₁= 93 MHz,

f₂= 103 MHz

f₁= 493 MHz,

f₂= 503 MHz

f₁= 993 MHz,

f₂= 1003 MHz

3rd-order intermodulation

distortion

IMD3

dBFS

f₁= 1793 MHz,

f₂= 1803 MHz

f₁= 2693 MHz,

f₂= 2703 MHz

f₁= 3493 MHz,

f₂= 3503 MHz

(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB

below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input

bandwidth.

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7.8 Timing Requirements

MIN

NOM

MAX

UNIT

ADC SAMPLING CLOCK

High Performance Mode

Low Power Mode

500⁽¹⁾

800⁽¹⁾

f_S

ADC core sampling clock frequency

MHz

f_S

ADC core minimum sampling clock frequency

Low Power Mode

500⁽¹⁾

CLOCK INPUTS (CLK+, CLK–, SE_CLK)

PLL Disabled

500

50

800

500

f_CLK

CLK± input frequency

MHz

PLL Enabled, PLLREF_SE

= 0

PLL Enabled, PLLREF_SE

= 1

f_{SE_CLK}

SE_CLK input frequency

50

500

DC_(CLKMIN)

DC_(CLKMAX)

Minimum Input clock duty cycle (CLK± and SE_CLK)

Maximum Input clock duty cycle (CLK± and SE_CLK)

40%

60%

Input clock duty cycle

(CLK± and SE_CLK)

PHASE-LOCKED LOOP (PLL) AND VOLTAGE-CONTROLLED OSCILLATOR (VCO)

f_PLLPFDPLL phase-frequency detector (PFD) frequency PLL Enabled

f_VCOClosed-loop voltage-controlled oscillator (VCO) frequency PLL Enabled

SYSREF (SYSREF+, SYSREF–)

50

500

MHz

7200

8200

Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time

t_INV(SYSREF)

t_INV(TEMP)

t_INV(VA11)

238

0.05

ps

violation, as measured by SYSREF_POS status register⁽²⁾

Drift of invalid SYSREF capture region over temperature, positive number indicates a

shift toward MSB of SYSREF_POS register

ps/°C

ps/mV

Drift of invalid SYSREF capture region over VA11 supply voltage, positive number

indicates a shift toward MSB of SYSREF_POS register

-0.14

SYSREF_ZOOM = 0

Delay of SYSREF_POS LSB

119

69

t_STEP(SP)

ps

ns

SYSREF_ZOOM = 1

DC_(SYSREF)

t_{(PH_SYS)}

SYSREF duty cycle (asserted) when using a periodic SYSREF signal

Minimum SYSREF± assertion duration after SYSREF± rising edge event

50%

4

55%

JESD204C SYNC TIMING (SYNCSE)

SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)

f_CLK(SCLK)

t_(PH)

Serial clock frequency

0

15.625

MHz

ns

Serial clock high value pulse duration

Serial clock low value pulse duration

Setup time from SCS to rising edge of SCLK

Hold time from rising edge of SCLK to SCS

Setup time from SDI to rising edge of SCLK

Hold time from rising edge of SCLK to SDI

32

25

3

t_(PL)

ns

t_SU(SCS)

t_H(SCS)

t_SU(SDI)

t_H(SDI)

ns

25

3

ns

(1) Unless functionally limited to a smaller range in the tables Operating Modes for Quad Channel Device through Operating Modes for

Single Channel Device based on programmed JMODE.

(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the section SYSREF Windowing for

more information on SYSREF windowing. The invalid region, specified by t_INV(SYSREF), indicates the portion of the CLK± period(t_CLK),

as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and

CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the

invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL

selection may be needed to track the skew between CLK± and SYSREF±.

24

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7.9 Switching Characteristics

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V,

default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK=800MHz, filtered 1 V_PPsine-wave clock applied

to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration, SER_PE = 4 (unless otherwise

noted), VA11Q and VCLK11 noise suppression on when CPLL on; minimum and maximum values are at nominal supply

voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC SAMPLING CLOCK

PLL disabled, CLK±

305

314

332

60

ps

fs

Sampling (aperture) delay from the clock

falling edge to sampling instant

t_AD

PLL enabled, CLK±

PLL enabled, SE_CLK

Dither disabled (ADC_DITH_EN = 0)

Dither enabled (ADC_DITH_EN = 1)

PLL enabled (PLL_EN = 1), f_PLLREF= 50 MHz

PLL enabled (PLL_EN = 1), f_PLLREF= 200 MHz

t_AJ

Aperture jitter, rms

52

fs

t_J(PLL)

PLL additive jitter, rms

370

380

fs

CLOCK AND TRIGGER OUTPUTS (PLLREFO±, TRIGOUT±, ORC, ORD)

f_PLLREFO

PLLREFO± frequency range

PLL Enabled, PLLREFO± enabled

50

500

100

MHz

ORC and ORD frequency range when

programmed to output divided PLL reference

clock

PLL Enabled, DIVREF_C_MODE > 0,

DIVREF_D_MODE > 0

f_DIVREFO

12.5

t_PW(TRIGOUT)Minimum TRIGOUT± pulse width

TRIGOUT_SRC = 0 (TMSTP±)

TRIGOUT_SRC = 1 (S-PLL)

1

t_CLK

f_TRIGOUT

TRIGOUT± frequency range

800

440

MHz

PLLREF_SE = 0 (CLK± used), nominal supply

voltage, T_A= 25°C

280

380

250

280

359

469

330

365

t_PD(REF)

Input clock to PLLREFO± propagation delay

ps

PLLREF_SE = 1 (SE_CLK used), nominal supply

voltage, T_A= 25°C

560

420

450

PLLREF_SE = 0 (CLK± used), nominal supply

voltage

Input clock to PLLREFO± propagation delay

temperature coefficient

t_PD-TEMPCO

fs/°C

PLLREF_SE = 1 (SE_CLK used), nominal supply

voltage

PLLREF_SE = 0 (CLK± used), T_A= 25°C

PLLREF_SE = 1 (SE_CLK used), T_A= 25°C

–533

–480

–397

–372

–186

–180

Input clock to PLLREFO± propagation delay

supply voltage coefficient

t_PD-VOLTCO

fs/mV

SERIAL DATA OUTPUTS (D[7:0]+, D[7:0]–)

f_SERDES

UI

Serialized output bit rate

2.5

17.16

400

Gbps

ps

Serialized output unit interval

58.3

t_TLH

Low-to-high transition time (differential)

High-to-low transition time (differential)

20% to 80%, 8H8L test pattern, 16.5 Gbps

PRBS-7 test pattern, JMODE = 0, 6.4 Gbps

PRBS-9 test pattern, JMODE = 4, 13.2 Gbps

PRBS-9 test pattern, JMODE = 8, 9.9 Gbps

PRBS-7 test pattern, JMODE = 0, 6.4 Gbps

PRBS-9 test pattern, JMODE = 4, 13.2 Gbps

PRBS-9 test pattern, JMODE = 8, 9.9 Gbps

PRBS-7 test pattern, JMODE = 0, 6.4 Gbps

PRBS-9 test pattern, JMODE = 4, 13.2 Gbps

PRBS-9 test pattern, JMODE = 8, 9.9 Gbps

8H8L test pattern, JMODE = 0, 6.4 Gbps

8H8L test pattern, JMODE = 4, 13.2 Gbps

8H8L test pattern, JMODE = 8, 9.9 Gbps

PRBS-7 test pattern, JMODE = 0, 6.4 Gbps

PRBS-9 test pattern, JMODE = 4, 13.2 Gbps

PRBS-9 test pattern, JMODE = 8, 9.9 Gbps

27.1

27.2

7.0

ps

t_THL

ps

DDJ

DCD

EBUJ

RJ

Data dependent jitter, peak-to-peak

Even-odd jitter, peak-to-peak

8.5

ps

8.8

0.2

0.01

0.24

4.02

1.07

2.61

0.72

0.77

1.33

22.48

20.22

31.17

Effective bounded uncorrelated jitter, peak-to-

peak

Unbounded random jitter, RMS

Total jitter, peak-to-peak, with unbounded

random jitter portion defined with respect to

a BER = 1e-15 (Q = 7.94)

TJ

ADC CORE LATENCY

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7.9 Switching Characteristics (continued)

typical values at T_A= 25°C, VA19 = 1.9 V, VPLL19 = 1.9 V, VREFO = 1.9 V, VTRIG = 1.1V, VA11 = 1.1 V, VD11 = 1.1 V,

default full-scale voltage (V_FS= 0.8 V_PP), f_IN= 97 MHz, A_IN= –1 dBFS, f_CLK=800MHz, filtered 1 V_PPsine-wave clock applied

to CLK±, PLL disabled, JMODE = 0, High Performance Mode and foreground calibration, SER_PE = 4 (unless otherwise

noted), VA11Q and VCLK11 noise suppression on when CPLL on; minimum and maximum values are at nominal supply

voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table

PARAMETER

TEST CONDITIONS

MIN

TYP

–2

1

MAX

UNIT

JMODE = 0

JMODE = 1

JMODE = 2

JMODE = 3

JMODE = 4

JMODE = 5

JMODE = 6

JMODE = 7

JMODE = 8

JMODE = 9

JMODE = 10

JMODE = 11

JMODE = 12

JMODE = 13

JMODE = 14

JMODE = 15

–1

1

Deterministic delay from the CLK± edge that

samples the reference sample to the CLK±

edge that samples SYSREF going high⁽¹⁾

–1

–2

–1

2

t_CLK

cycles

t_ADC

–2

JESD204C AND SERIALIZER LATENCY

JMODE = 0

JMODE = 1

JMODE = 2

JMODE = 3

JMODE = 4

JMODE = 5

JMODE = 6

JMODE = 7

JMODE = 8

JMODE = 9

JMODE = 10

JMODE = 11

JMODE = 12

JMODE = 13

JMODE = 14

JMODE = 15

49.8

45.5

44.3

42.1

53.3

47.1

58.4

56.2

66.3

87.2

72.9

61.7

94

56.6

52.8

50.5

48

Delay from the CLK± rising edge that samples

60.2

54.2

65

SYSREF high to the first bit of the multiframe

(8B/10B encoding) or extended multiblock

(64B/66B encoding) on the JESD204C serial

output lane corresponding to the reference

t_CLK

cycles

t_TX

(2)

sample of t_ADC

63.1

74.5

94.8

83.9

68.1

103.3

SERIAL PROGRAMMING INTERFACE (SDO)

Delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from

tri-state to valid data

t_(OZD)

1

ns

t_(ODZ)

t_(OD)

Delay from the SCS rising edge for SDO transition from valid data to tri-state

Delay from the falling edge of SCLK during read operation to SDO valid

10

ns

1

(1) t_ADCis an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high

capture point, in which case the total latency is smaller than the delay given by t_TX

.

(2) The values given for t_TXinclude deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will

vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper

receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local

multiframe clock (LMFC) cycle.

26

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7.10 Typical Characteristics

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0.2

0.15

0.1

2

1.5

1

0.05

0

0.5

0

-0.05

-0.1

-0.15

-0.2

-0.5

-1

-1.5

-2

0

4096

0

4096

Output Code

Figure 7-1. DNL vs Code

Figure 7-2. INL vs Code

2

1

-40

-50

ch B aggressor

ch C aggressor

ch D aggressor

ch A

ch B

ch C

ch D

-60

0

-70

-80

-1

-90

-2

0

-100

1000

2000

3000

4000

Input Frequency (MHz)

5000

6000

0

500 1000 1500 2000 2500 3000 3500 4000

Input Frequency (MHz)

Figure 7-3. Input Fullscale vs Input Frequency

Figure 7-4. Crosstalk vs Input Frequency, Channel A victim

-40

-50

0

-10

ch A aggressor

ch C aggressor

ch D aggressor

-20

-30

-60

-40

-50

-70

-60

-70

-80

-90

-100

-110

-120

-100

0

500 1000 1500 2000 2500 3000 3500 4000

Input Frequency (MHz)

0

50

100

150

200

250

Output Frequency (MHz)

300

350

400

D801

Figure 7-5. Crosstalk vs Input Frequency, Channel B victim

Figure 7-6. Single Tone FFT at 347 MHz and -1dBFS

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

D803

D805

Figure 7-7. Single Tone FFT at 897 MHz and -1dBFS

Figure 7-8. Single Tone FFT at 2097 MHz and -1dBFS

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-110

-120

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

D807

D802

Figure 7-9. Single Tone FFT at 3247 MHz and -1dBFS

Low Power Mode

Figure 7-10. Single Tone FFT at 347 MHz and -1dBFS

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

D804

D806

Low Power Mode

Figure 7-11. Single Tone FFT at 897 MHz and -1dBFS

Figure 7-12. Single Tone FFT at 2097 MHz and -1dBFS

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50

100

150

200

250

Output Frequency (MHz)

300

350

400

D801

Low Power Mode

PLL on, suppression off

Figure 7-13. Single Tone FFT at 3247 MHz and -1dBFS

Figure 7-14. Single Tone FFT at 347 MHz and -1dBFS

PLL on, suppression on

PLL on, suppression off

Figure 7-15. Single Tone FFT at 347 MHz and -1dBFS

Figure 7-16. Single Tone FFT at 997 MHz and -1dBFS

PLL on, suppression on

Low Lower Mode, PLL on, suppression off

Figure 7-17. Single Tone FFT at 997 MHz and -1dBFS

Figure 7-18. Single Tone FFT at 347 MHz and -1dBFS

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

Low Lower Mode, PLL on, suppression on

Low Lower Mode, PLL on, suppression off

Figure 7-19. Single Tone FFT at 347 MHz and -1dBFS

Figure 7-20. Single Tone FFT at 997 MHz and -1dBFS

60

55

50

45

40

35

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

Low Lower Mode, PLL on, suppression on

Figure 7-22. SNR vs Input Frequency

Figure 7-21. Single Tone FFT at 997 MHz and -1dBFS

100

95

90

85

80

75

70

65

60

55

50

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

0

500

1000

1500

2000

2500

3000

3500

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

Figure 7-23. SFDR vs Input Frequency

Figure 7-24. HD2 vs Input Frequency

30

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

-50

-60

60

55

50

45

40

35

-70

-80

-90

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

-100

-110

0

500

1000

1500

2000

2500

3000

3500

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

Figure 7-25. HD3 vs Input Frequency

Figure 7-26. SINAD vs Input Frequency

10

9.5

9

60

59

58

57

56

55

54

53

52

51

50

8.5

8

7.5

7

6.5

6

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

5.5

5

0

500

1000

1500

2000

2500

3000

3500

500

550

600

650

700

750

800

Input Frequency (MHz)

Sample Rate (MSPS)

Figure 7-27. ENOB vs Input Frequency

Figure 7-28. SNR vs Sample Rate

70

65

60

55

50

45

40

60

58

56

54

52

50

48

46

44

42

40

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-29. SFDR vs Sample Rate

Figure 7-30. SINAD vs Sample Rate

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

60

55

50

45

40

35

30

25

20

15

10

9.75

9.5

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

9.25

9

8.75

8.5

F_IN= 99.997MHz, dBFS

F_IN= 997MHz, dBFS

F_IN= 2697MHz, dBFS

F_IN= 99.997MHz, dBc

F_IN= 997MHz, dBc

8.25

8

7.75

7.5

F_IN= 2697MHz, dBc

-40

-35

-30

-25

-20

-15

Input Amplitude (dBFS)

-10

-5

0

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-32. SNR vs Input Amplitude

Figure 7-31. ENOB vs Sample Rate

100

90

80

70

60

50

40

30

20

10

0

60

Suppression Off

Suppression On

55

50

45

40

35

F_IN= 99.997MHz, dBFS

F_IN= 997MHz, dBFS

F_IN= 2697MHz, dBFS

F_IN= 99.997MHz, dBc

F_IN= 997MHz, dBc

F_IN= 2697MHz, dBc

-40

-35

-30

-25

-20

-15

Input Amplitude (dBFS)

-10

-5

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

Figure 7-33. SFDR vs Input Amplitude

CPLL on

Figure 7-34. SNR vs Input Frequency and Suppression

70

65

60

55

50

45

40

60

Suppression Off

Suppression On

Suppression Off

Suppression On

55

50

45

40

35

0

500

1000

1500

2000

2500

3000

3500

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

CPLL on

Figure 7-35. SFDR vs Input Frequency and Suppression

Figure 7-36. SINAD vs Input Frequency and Suppression

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

10

9.5

9

70

68

66

64

62

60

58

56

54

52

50

Suppression Off

Suppression On

8.5

8

7.5

7

6.5

6

SFDR

SINAD

SNR

5.5

5

0

500

1000

1500

2000

2500

3000

3500

-5

-4

-3

-2

-1

0

1

2

3

4

5

Input Frequency (MHz)

Supply Voltage (% from nominal)

CPLL on

All supplies moved together

Figure 7-37. ENOB vs Input Frequency and Suppression

Figure 7-38. SNR, SFDR and SINAD vs Supply Voltage

-60

62

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

-65

-70

-75

-80

-85

60

58

56

54

52

50

-90

HD2

HD3

Worst Spur

-95

-100

-5

-4

-3

-2

-1

0

1

2

3

4

5

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

Supply Voltage (% from nominal)

Clock Amplitude (V_PP-DIFF

)

Figure 7-40. SNR vs Clock Amplitude

All supplies moved together

Figure 7-39. HD2, HD3 and worst non-HD vs Supply Voltage

70

80

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

F_IN= 1797 MHz

F_IN= 3497 MHz

68

66

64

62

60

58

56

54

52

50

75

70

65

60

55

50

SFDR

SINAD

SNR

0

50

100

150

200

250

300

350

400

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

PLL Reference Frequency (MHz)

Clock Amplitude (V_PP-DIFF

)

Figure 7-41. SFDR vs Clock Amplitude

Figure 7-42. SNR, SFDR and SINAD vs Reference Frequency

with PLL on

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

60

59

58

57

56

55

54

53

52

51

50

75

70

65

60

55

50

BG cal

FG cal at each temperature

FG at 25C

BG cal

FG cal at each temperature

FG at 25C

-60 -40 -20

0

20

40

60

80 100 120 140

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (C)

F_IN= 347 MHz

Figure 7-43. SNR vs Temperature

Figure 7-44. SFDR vs Temperature

-60

-62

-64

-66

-68

-70

-72

-74

-76

-78

-80

-40

-45

-50

-55

-60

-65

-70

-75

-80

BG cal

FG cal at each temperature

FG at 25C

BG cal

FG cal at each temperature

FG at 25C

-60 -40 -20

0

20

40

60

80 100 120 140

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (C)

F_IN= 347 MHz

Figure 7-45. HD2 vs Temperature

Figure 7-46. HD3 vs Temperature

-60

-65

-70

-75

-80

-85

-90

60

59

58

57

56

55

54

53

52

51

50

BG cal

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

FG cal at each temperature

FG at 25C

-60 -40 -20

0

20

40

60

80 100 120 140

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

Temperature (C)

F_IN= 347 MHz

Low Power Mode

Figure 7-47. worst non-HD spur vs Temperature

Figure 7-48. SNR vs Input Frequency in Low Power Mode

34

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

100

95

90

85

80

75

70

65

60

55

50

-60

-65

-70

-75

-80

-85

-90

-95

-100

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

Low Power Mode

Figure 7-49. SFDR vs Input Frequency in Low Power Mode

Figure 7-50. HD2 vs Input Frequency in Low Power Mode

60

59

58

57

56

55

54

53

52

-60

-65

-70

-75

-80

-85

-90

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

-95

51

50

-100

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

Low Power Mode

Figure 7-51. HD3 vs Input Frequency in Low Power Mode

Figure 7-52. SINAD vs Input Frequency in Low Power Mode

10

9.8

9.6

9.4

9.2

9

58

57.8

57.6

57.4

57.2

57

8.8

8.6

8.4

56.8

56.6

56.4

PLL off, A_IN= -12dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -6dBFS

PLL on, A_IN= -12dBFS

PLL off, A_IN= -1dBFS

PLL on, A_IN= -12dBFS

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

8.2

8

56.2

56

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

500

550

600

650

700

750

800

Sample Rate (MSPS)

Low Power Mode

Figure 7-53. ENOB vs Input Frequency in Low Power Mode

Figure 7-54. SNR vs Sample Rate in Low Power Mode

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

75

70

65

60

55

50

58

57

56

55

54

53

52

51

50

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Low Power Mode

Figure 7-55. SFDR vs Sample Rate in Low Power Mode

Figure 7-56. SINAD vs Sample Rate in Low Power Mode

9.5

60

55

50

45

40

35

F_IN= 97 MHz

F_IN= 347 MHz

F_IN= 497 MHz

F_IN= 997 MHz

9.4

9.3

9.2

9.1

9

8.9

8.8

8.7

8.6

8.5

F_IN= 99.997MHz, dBFS

30

F_IN= 997MHz, dBFS

F_IN= 2697MHz, dBFS

F_IN= 99.997MHz, dBc

F_IN= 997MHz, dBc

F_IN= 2697MHz, dBc

25

20

15

500

550

600

650

700

750

800

-40

-35

-30

-25

-20

-15

Input Amplitude (dBFS)

-10

-5

0

Sample Rate (MSPS)

Low Power Mode

Figure 7-57. ENOB vs Sample Rate in Low Power Mode

Figure 7-58. SNR vs Input Amplitude in Low Power Mode

100

90

80

70

60

50

40

30

20

60

Suppression Off

Suppression On

59

58

57

56

55

54

53

52

51

50

F_IN= 99.997MHz, dBFS

F_IN= 997MHz, dBFS

F_IN= 2697MHz, dBFS

F_IN= 99.997MHz, dBc

F_IN= 997MHz, dBc

F_IN= 2697MHz, dBc

10

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

-40

-35

-30

-25

-20

-15

Input Amplitude (dBFS)

-10

-5

0

CPLL On, Low Power Mode

Low Power Mode

Figure 7-60. SNR vs Input Frequency

Figure 7-59. SFDR vs Input Amplitude in Low Power Mode

36

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

70

68

66

64

62

60

58

56

54

52

50

60

59

58

57

56

55

54

53

52

51

50

Suppression Off

Suppression On

Suppression Off

Suppression On

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

CPLL On, Low Power Mode

Figure 7-61. SFDR vs Input Frequency

Figure 7-62. SINAD vs Input Frequency

10

9.5

9

80

SFDR

SINAD

SNR

75

70

65

60

55

50

8.5

8

7.5

7

6.5

6

Suppression Off

Suppression On

0

50 100 150 200 250 300 350 400 450 500

Input Frequency (MHz)

-5

-4

-3

-2

-1

0

1

2

3

4

5

Supply Voltage (% from nominal)

CPLL On, Low Power Mode

Low Power Mode, all supplies moved together

Figure 7-63. ENOB vs Input Frequency

Figure 7-64. SNR, SFDR and SINAD vs Supply Voltage

-60

0

-10

HD2

HD3

Worst Spur

-62

-64

-66

-68

-70

-72

-74

-76

-78

-80

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-5

-4

-3

-2

-1

0

1

2

3

4

5

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

Supply Voltage (% from nominal)

D809

Low Power Mode, all supplies moved together

-7 dBFS each tone

Figure 7-65. HD2, HD3 and worst non-HD vs Supply Voltage

Figure 7-66. Two Tone FFT at 347 MHz

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

D811

D813

-7 dBFS each tone

Figure 7-67. Two Tone FFT at 1798 MHz

Figure 7-68. Two Tone FFT at 3498 MHz

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

0

50

100

150

Output Frequency (MHz)

200

250

300

350

400

D810

D812

-7 dBFS each tone

Figure 7-69. Two Tone FFT at 347 MHz in Low Power Mode

Figure 7-70. Two Tone FFT at 1798 MHz in Low Power Mode

0

-10

-50

A_IN= -18dBFS/tone

-55

-60

-65

-70

-75

-80

-85

-90

-95

A_IN= -16dBFS/tone

A_IN= -9dBFS/tone

A_IN= -7dBFS/tone

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50

100

150

200

250

Output Frequency (MHz)

300

350

400

0

500

1000

1500

2000

Input Frequency (MHz)

2500

3000

3500

D814

-7 dBFS each tone

Figure 7-72. IMD3 vs Input Frequency

Figure 7-71. Two Tone FFT at 3498 MHz in Low Power Mode

38

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

2.5

2.25

2

A_IN= -18dBFS/tone

A_IN= -16dBFS/tone

A_IN= -9dBFS/tone

A_IN= -7dBFS/tone

1.75

1.5

1.25

1

HP mode, JMODE 0

HP mode, JMODE 1

HP mode, JMODE 2

HP mode, JMODE 3

LP mode, JMODE 0

LP mode, JMODE 1

LP mode, JMODE 2

LP mode, JMODE 3

500

550

600

650

700

750

800

0

500

1000

1500

2000

Input Frequency (MHz)

2500

3000

3500

Sample Rate (MSPS)

Figure 7-74. Quad Channel, Power Dissipation vs F_Sfor

JMODES 0 - 3

Low Power Mode

Figure 7-73. IMD3 vs Input Frequency in Low Power Mode

2.5

2.25

2

2.25

2

1.75

1.5

1.75

1.5

HP mode, JMODE 4

HP mode, JMODE 5

HP mode, JMODE 6

HP mode, JMODE 7

LP mode, JMODE 4

LP mode, JMODE 5

LP mode, JMODE 6

LP mode, JMODE 7

HP mode, JMODE 8

HP mode, JMODE 9

HP mode, JMODE 10

HP mode, JMODE 11

LP mode, JMODE 8

LP mode, JMODE 9

LP mode, JMODE 10

LP mode, JMODE 11

1.25

1

1.25

1

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-75. Quad Channel, Power Dissipation vs F_Sfor

JMODES 4 - 7

Figure 7-76. Quad Channel, Power Dissipation vs F_Sfor

JMODES 8 - 11

2.5

2.25

2

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1.75

1.5

HP mode, JMODE 12

HP mode, JMODE 13

HP mode, JMODE 14

HP mode, JMODE 15

LP mode, JMODE 12

LP mode, JMODE 13

LP mode, JMODE 14

LP mode, JMODE 15

1.25

1

HP mode

LP mode

0.1

0

500

550

600

650

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

Sample Rate (MSPS)

D839

Figure 7-77. Quad Channel, Power Dissipation vs F_Sfor

JMODES 12 - 15

Independent of JMODE

Figure 7-78. Quad Channel, I_VA19vs F_S

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.5

0.45

0.4

JMODE 0

JMODE 1

JMODE 2

JMODE 3

0.35

0.3

0.25

0.2

0.15

0.1

HP mode

LP mode

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D840

D841

Independent of JMODE

Independent of Power Mode

Figure 7-79. Quad Channel, I_VA11vs F_S

Figure 7-80. Quad Channel, I_VD11vs F_Sfor JMODES 0 - 3

0.5

0.45

0.4

0.5

JMODE 4

JMODE 5

JMODE 6

JMODE 7

JMODE 8

JMODE 10

JMODE 11

0.45

0.4

JMODE 12

0.35

0.3

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

0.05

0

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D842

D843

Independent of Power Mode

Figure 7-81. Quad Channel, I_VD11vs F_Sfor JMODES 4 - 7

Figure 7-82. Quad Channel, I_VD11vs F_Sfor JMODES 8-12

0.5

0.4

0.3

0.2

0.1

0

JMODE 13

JMODE 14

JMODE 15

0.45

0.4

0.35

0.3

0.25

0.2

-0.1

0.15

0.1

-0.2

BG cal mode, HP mode

FG cal mode, HP mode

-0.3

BG cal mode, LP mode

FG cal mode, LP mode

700 750 800

0.05

0

-0.4

-0.5

500

550

600

650

Sample Rate (MSPS)

700

750

800

550

600

650

Sample Rate (MSPS)

D844

D865

Independent of Power Mode

Difference to LPBG mode

Figure 7-83. Quad Channel, I_VD11vs F_Sfor JMODES 13-15

Figure 7-84. Quad Channel, Power Dissipation vs F_Sover

Modes

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

200

150

100

50

100

80

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

60

40

20

0

-20

-40

-60

-80

-100

-50

-100

-150

-200

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D868

D871

Difference to LPBG mode

Figure 7-85. Quad Channel, I_VA19vs F_Sover Modes

Figure 7-86. Quad Channel, I_VA11vs F_Sover Modes

1.5

50

BG cal mode, HP mode

FG cal mode, HP mode

40

30

1.4

1.3

1.2

1.1

1

20

10

0

-10

-20

-30

-40

-50

0.9

0.8

0.7

0.6

0.5

HP mode, JMODE 0

HP mode, JMODE 1

HP mode, JMODE 2

HP mode, JMODE 3

LP mode, JMODE 0

LP mode, JMODE 1

LP mode, JMODE 2

LP mode, JMODE 3

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

D874

Figure 7-88. Dual Channel, Power Dissipation vs F_Sfor

JMODES 0 - 3

Difference to LPBG mode

Figure 7-87. Quad Channel, I_VD11vs F_Sover Modes

1.5

1.4

1.3

1.2

1.1

1

1.4

1.3

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.9

0.8

HP mode, JMODE 4

HP mode, JMODE 5

HP mode, JMODE 6

HP mode, JMODE 7

LP mode, JMODE 4

LP mode, JMODE 5

LP mode, JMODE 6

LP mode, JMODE 7

HP mode, JMODE 8

HP mode, JMODE 9

HP mode, JMODE 10

HP mode, JMODE 11

LP mode, JMODE 8

LP mode, JMODE 9

LP mode, JMODE 10

LP mode, JMODE 11

0.7

0.6

0.5

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-89. Dual Channel, Power Dissipation vs F_Sfor

JMODES 4 - 7

Figure 7-90. Dual Channel, Power Dissipation vs F_Sfor

JMODES 8 - 11

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

1.5

1.4

1.3

1.2

1.1

1

0.5

0.45

0.4

0.35

0.3

0.25

0.2

0.9

0.8

0.7

0.6

0.5

0.15

0.1

HP mode, JMODE 12

HP mode, JMODE 13

HP mode, JMODE 14

HP mode, JMODE 15

LP mode, JMODE 12

LP mode, JMODE 13

LP mode, JMODE 14

LP mode, JMODE 15

HP mode

LP mode

0.05

0

500

550

600

650

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

Sample Rate (MSPS)

D849

Figure 7-91. Dual Channel, Power Dissipation vs F_Sfor

JMODES 12 - 15

Independent of JMODE

Figure 7-92. Dual Channel, I_VA19vs F_S

0.6

0.5

0.4

0.3

0.2

0.3

0.25

0.2

JMODE 0

JMODE 1

JMODE 2

JMODE 3

0.15

0.1

0.05

0

HP mode

LP mode

0

500

550

600

650

Sample Rate (MSPS)

700

750 800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D850

D851

Figure 7-94. Dual Channel, I_VD11vs F_Sfor JMODES 0 - 3

Independent of JMODE

Figure 7-93. Dual Channel, I_VA11vs F_S

0.3

JMODE 4

JMODE 5

JMODE 6

JMODE 7

JMODE 8

JMODE 10

JMODE 11

JMODE 12

0.25

0.2

0.25

0.2

0.15

0.1

0.15

0.1

0.05

0

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D852

D853

Figure 7-95. Dual Channel, I_VD11vs F_Sfor JMODES 4 - 7

Figure 7-96. Dual Channel, I_VD11vs F_Sfor JMODES 8 - 12

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0.3

0.25

0.2

0.5

0.4

0.3

0.2

0.1

0

JMODE 13

JMODE 14

JMODE 15

0.15

0.1

-0.1

-0.2

-0.3

-0.4

-0.5

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D854

D866

Figure 7-97. Dual Channel, I_VD11vs F_Sfor JMODES 13 - 15

Difference to LPBG mode

Figure 7-98. Dual Channel, Power Dissipation vs F_Sover Modes

200

150

100

50

100

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

80

60

40

20

0

-20

-40

-60

-80

-100

-50

-100

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

-150

-200

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D869

D872

Difference to LPBG mode

Figure 7-99. Dual Channel, I_VA19vs F_Sover Modes

1.2

Figure 7-100. Dual Channel, I_VA11vs F_Sover Modes

1.2

1.1

1

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.9

0.8

0.7

0.6

0.5

0.4

HP mode, JMODE 0

HP mode, JMODE 1

HP mode, JMODE 2

HP mode, JMODE 3

LP mode, JMODE 0

HP mode, JMODE 4

HP mode, JMODE 5

HP mode, JMODE 6

HP mode, JMODE 7

LP mode, JMODE 4

LP mode, JMODE 1

LP mode, JMODE 2

LP mode, JMODE 3

LP mode, JMODE 5

LP mode, JMODE 6

LP mode, JMODE 7

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-101. Dual Channel, Power Dissipation vs F_Sfor

JMODES 0 - 3

Figure 7-102. Single Channel, Power Dissipation vs F_Sfor

JMODES 4 - 7

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

1.2

1.1

1

1.2

1.1

1

0.9

0.8

0.7

0.6

0.5

0.4

0.9

0.8

0.7

0.6

0.5

0.4

HP mode, JMODE 8

HP mode, JMODE 9

HP mode, JMODE 10

HP mode, JMODE 11

LP mode, JMODE 8

LP mode, JMODE 9

LP mode, JMODE 10

LP mode, JMODE 11

HP mode, JMODE 12

HP mode, JMODE 13

HP mode, JMODE 14

HP mode, JMODE 15

LP mode, JMODE 12

LP mode, JMODE 13

LP mode, JMODE 14

LP mode, JMODE 15

500

550

600

650

700

750

800

500

550

600

650

700

750

800

Sample Rate (MSPS)

Figure 7-103. Single Channel, Power Dissipation vs F_Sfor

JMODES 8 - 11

Figure 7-104. Single Channel, Power Dissipation vs F_Sfor

JMODES 12 - 15

0.5

0.45

0.4

0.5

0.4

0.3

0.2

0.1

0.35

0.3

0.25

0.2

0.15

0.1

HP mode

LP mode

HP mode

LP mode

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

550

600

650

Sample Rate (MSPS)

700

750 800

D859

D860

Independent of JMODE

Figure 7-105. Single Channel, I_VA19vs F_S

Figure 7-106. Single Channel, I_VA11vs F_S

0.25

JMODE 0

JMODE 1

JMODE 2

JMODE 3

JMODE 4

JMODE 5

JMODE 6

JMODE 7

0.225

0.2

0.15

0.1

0.175

0.15

0.125

0.1

0.075

0.05

0.025

0

0.05

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D861

D862

Figure 7-107. Single Channel, I_VD11vs F_Sfor JMODES 0 - 3

Figure 7-108. Single Channel, I_VD11vs F_Sfor JMODES 4 - 7

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

0.25

0.225

0.2

0.25

0.225

0.2

JMODE 8

JMODE 10

JMODE 11

JMODE 12

JMODE 13

JMODE 14

JMODE 15

0.175

0.15

0.125

0.1

0.175

0.15

0.125

0.1

0.075

0.05

0.025

0

0.075

0.05

0.025

0

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D863

D864

Figure 7-109. Single Channel, I_VD11vs F_Sfor JMODES 8 - 12

Figure 7-110. Single Channel, I_VD11vs F_Sfor JMODES 13 - 15

0.5

0.4

0.3

0.2

0.1

0

200

150

100

50

0

-0.1

-50

-0.2

-100

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, HP mode

FG cal mode, HP mode

-0.3

-150

-200

BG cal mode, LP mode

FG cal mode, LP mode

700 750 800

BG cal mode, LP mode

FG cal mode, LP mode

-0.4

-0.5

500

550

600

650

Sample Rate (MSPS)

500

550

600

650

Sample Rate (MSPS)

700

750

800

D867

D870

Difference to LPBG mode

Figure 7-111. Single Channel, Power Dissipation vs F_Sover

Modes

Figure 7-112. Single Channel, I_VA19vs F_Sover Modes

100

50

BG cal mode, HP mode

FG cal mode, HP mode

BG cal mode, LP mode

FG cal mode, LP mode

BG cal mode, HP mode

FG cal mode, HP mode

80

40

30

60

40

20

0

10

0

-20

-40

-60

-80

-100

-10

-20

-30

-40

-50

500

550

600

650

Sample Rate (MSPS)

700

750

800

500

550

600

650

Sample Rate (MSPS)

700

750

800

D873

D876

Difference to LPBG mode

Figure 7-113. Single Channel, I_VA11vs F_Sover Modes

Figure 7-114. Single Channel, I_VD11vs F_Sover Modes

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7.10 Typical Characteristics (continued)

Typical values at 25°C, A_IN= -1 dBFS, F_IN= 347 MHz, F_S= 800 MSPS, High power mode, FG calibration, JMODE 0, CPLL

off, CPLL_REF= 50 MHz and VA11Q and VCLK11 noise suppression on when CPLL on, nominal supply voltages, unless

otherwise noted. SNR results exclude DC, HD2 to HD9; SINAD, ENOB, and SFDR results exclude DC.

2070

2065

2060

2055

2050

2045

2040

2035

2030

2025

2020

3570

3565

3560

3555

3550

3545

3540

3535

3530

3525

3520

0

50

100

150

200

Sample #

250

300

350

400

0

50

100

150

200

Sample #

250

300

350

400

BG Calibration, midscale input voltage, ADC_SRC_DLY=31,

MUX_DLY=30

BG Calibration, midscale input voltage, ADC_SRC_DLY=31,

MUX_DLY=30

Figure 7-115. Background Calibration Core Transition

(midscale)

Figure 7-116. Background Calibration Core Transition (voltage

offset)

BG Calibration, midscale input voltage, ADC_SRC_DLY=31,

MUX_DLY=30

BG Calibration, midscale input voltage, ADC_SRC_DLY=31,

MUX_DLY=30

Figure 7-117. Background Calibration Core Transition (AC

signal)

Figure 7-118. Background Calibration Core Transition (AC

signal zoomed)

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8 Detailed Description

8.1 Overview

The ADC12xJ800 is a family of quad, dual and single channel 12-bit, 800-MSPS analog-to-digital converters

(ADC). The devices have been optimized for low power consumption while maintaining high sampling rate and

performance. The combination of power consumption, sampling rate and 12-bit resolution makes the device is

ideally suited for light detection and ranging (LiDAR) systems. High channel density and wide input bandwidth

also makes device an ideal fit for multi-channel oscilloscopes and digitizers and small form factor electronic

warfare systems.

The device has a buffered input with full-power input bandwidth (-3 dB) of 6 GHz. The wide input bandwidth

provides flat frequency response for frequency domain applications, such as frequency modulated continuous

wave (FMCW) LiDAR systems, and provides a narrow impulse response for time domain applications, such as

and pulse-based LiDAR to achieve increased spatial resolution. The device is capable of direct RF sampling of

L-band (1-2 GHz) and S-band (2-4 GHz) for electronic warfare systems and satellite communication equipment

up to 4 GHz.

A number of clocking features are included to relax system timing requirements and simplify system

architectures. The device has an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator

(VCO) to generate the sampling clock from a low frequency reference eliminating the need for an external

high frequency clock generator. The low frequency PLL reference also relaxes timing of the SYSREF timing

reference to achieve deterministic latency and multi-device synchronization. The internal PLL can be bypassed

in favor of sending the high frequency sampling clock directly to the device for highest performance. A SYSREF

Windowing feature relaxes the setup and hold requirement of SYSREF by directly measuring and adjusting the

SYSREF delay inside of the device without the need to meet external timing requirements. The PLL reference

clock can be output from the device to clock the digital logic FPGA or ASIC or an adjacent device to eliminate

external clock buffer and distribution devices. Two additional CMOS outputs can send copies or divided copies

of the PLL reference clock to clock additional devices in the system. A fourth clock output can output a SerDes

reference clock for the transceiver block in the FPGA or ASIC to provide a complete system clocking solution.

A timestamp input can be used to mark a specific sample using an external trigger. The timestamp is output

over the JESD204C interface to mark the sample in the FPGA or ASIC. The timestamp signal can optionally be

output from the device instead of the SerDes reference clock to replicate the retimed trigger to other devices,

such as the pulse driver for a laser diode.

The JESD204C serialized interface decreases system size by reducing the amount of printed circuit board

(PCB) routing by increasing the SerDes bitrate per lane and therefore decreasing the number of lanes required.

JESD204C interface modes support from one to four lanes (single channel device) or two to eight lanes (dual

and quad channel devices) and SerDes baud-rates up to 17.16 Gbps to allow each application to choose the

optimal configuration. Both 8B/10B and 64B/66B data encoding options are available. The 8B/10B encoding

modes are backwards compatible with JESD204B receivers while the 64B/66B encoding modes provide higher

efficiency by reducing link overhead.

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8.2 Functional Block Diagram

Figure 8-1. Quad Channel Functional Block Diagram

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Figure 8-2. Dual Channel Functional Block Diagram

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Figure 8-3. Single Channel Functional Block Diagram

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8.3 Feature Description

8.3.1 Device Comparison

The devices listed in Table 8-1 are pin-to-pin compatible, providing a scalable family of devices for varying levels

of performance, speed, and signal bandwidth.

Table 8-1. Device Family Comparison

MAXIMUM

SAMPLING RATE

PART NUMBER (x= Q, D, S)

ADC12xJ1600

RESOLUTION

1.6 GSPS

12-bit

9-bit

ADC09xJ1300

ADC12xJ800

ADC09xJ800

1.3 GSPS

800 MSPS

12-bit

9-bit

800 MSPS

8.3.2 Analog Input

The analog input of the device has an internal buffer to enable high input bandwidth and to isolate sampling

capacitor glitch noise from the input circuit. The analog input must be driven differentially because operation with

a single-ended signal results in degraded performance. Both AC-coupling and DC-coupling of the analog input is

supported. The analog input is designed for an input common-mode voltage (V_CMI) of 1.1 V, which is terminated

internally through single-ended, 50-Ω resistors to the VA11 supply on each input pin. DC-coupled input signals

must have a common-mode voltage that meets the device input common-mode requirements specified as V_CMI

in the Recommended Operating Conditions table. The device includes internal analog input protection to protect

the ADC input during over-range input conditions; see the Analog Input Protection section. Figure 8-4 provides a

simplified analog input model.

VA11 (1.1 V)

Analog input

protection

diodes

INx+

ADC Core

INxt

Input buffer

Input

Termination

Figure 8-4. Analog Input Internal Termination and Protection Diagram

8.3.2.1 Analog Input Protection

The analog input is protected against overdrive conditions by internal clamping diodes that are capable of

sourcing or sinking input currents during over-range conditions, see the voltage and current limits in the Absolute

Maximum Ratings table. The over-range protection is also defined for a peak RF input power in the Absolute

Maximum Ratings table, which is frequency independent. Operation above the maximum conditions listed in the

Recommended Operating Conditions table results in an increase in failure-in-time (FIT) rate, so the system must

correct the overdrive condition as quickly as possible. Figure 8-4 shows the analog input protection diodes.

8.3.2.2 Full-Scale Voltage (V_FS) Adjustment

Input full-scale voltage (V_FS) adjustment is available, in fine increments, through FS_RANGE. All inputs are

set to the same full-scale voltage setting. The available adjustment range is specified in the Recommended

Operating Conditions table. Larger full-scale voltages improve SNR and noise floor (in dBFS/Hz) performance.

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8.3.2.3 Analog Input Offset Adjust

The input offset voltage for each analog input of the quad channel device can be adjusted through the OFSxy

registers, where x represents the ADC core (0, 1, 2, 3, 4 or 5) and y represents the analog input for ADC core

2 (A or B) and core 3 (C or D). The y parameter is omitted for ADC core 0, 1, 4 and 5 since these cores

always sample the same analog input. For the dual channel device, x represents the ADC core (0, 1, or 2) and

y represents the analog input for ADC core 2 (A or B). The y parameter is omitted for ADC core 0 and 1 since

these cores always sample the same analog input. For the single channel device, x represents the ADC core

(0 or 2) and the y parameter is omitted for ADC core 0 since this core always samples the same analog input.

The adjustment range is approximately 33 mV to –33 mV differential. See the Calibration Modes and Trimming

section for more information.

8.3.2.4 ADC Core

The device consists of a total of six ADC cores for the quad channel device, three ADC cores for the dual

channel device and two ADC cores for the single channel device. The cores are swapped on-the-fly for

calibration as required by the operating mode. This section highlights the theory and key features of the ADC

cores.

8.3.2.4.1 ADC Theory of Operation

The differential voltages at the analog inputs are captured by the rising edge of CLK±. After capturing the input

signal the ADC converts the analog voltage to a digital value by comparing the voltage to the internal reference

voltage. If the voltage on the negative input (that is, INA–) is higher than the voltage on the positive input (that

is, INA+) then the digital output is a negative 2's complement value. If the voltage on the positive input is higher

than the voltage on the negative input then the digital output is a positive 2's complement value. Equation 1 can

calculate the differential voltage at the input pins from the digital output.

Code

2

^N

V_IN

=

V_FS

(1)

where

•

Code is the signed decimal output code (for example, –2048 to +2047)

N is the ADC resolution

and V_FSis the full-scale input voltage of the ADC as specified in the DC Specifications table, including any

adjustment performed by programming FS_RANGE

8.3.2.4.2 ADC Core Calibration

ADC core calibration is required to optimize the analog performance of the ADC cores. Calibration must be

repeated when operating conditions change significantly, namely temperature, in order to maintain optimal

performance. The device has a built-in calibration routine that can be run as a foreground operation or a

background operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the

input signal, to complete the process. Background calibration can be used to overcome this limitation and allow

constant operation of the ADC. See the Calibration Modes and Trimming section for detailed information on each

mode.

8.3.2.4.3 Analog Reference Voltage

The reference voltage for the device is derived from an internal band-gap reference. A buffered version of the

reference voltage is available at the BG pin for user convenience. This output has an output-current capability

of ±100 µA. The BG output must be buffered if more current is required. No provision exists for the use of an

external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register

settings. Note that the VA11 supply voltage should be used to set the output common-mode voltage of a

front-end fully-differential amplifier and the BG output should not be used for this purpose.

8.3.2.4.4 ADC Over-range Detection

For the system gain management to have the best possible response time, a low-latency configurable over-

range function is included. The over-range function works by monitoring the converted 12-bit samples at the

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ADC to quickly detect if the ADC is near saturation or already in an over-range condition. The absolute value

of the upper 8 bits of the ADC data are checked against a programmable threshold, OVR_TH. The threshold

programmed into OVR_TH is used for all analog inputs.Table 8-2 lists how an ADC sample is converted to an

absolute value for a comparison of the thresholds.

Table 8-2. Conversion of ADC Sample for Over-range Comparison

ADC SAMPLE

(Offset Binary)

ADC SAMPLE

(2's Complement)

UPPER 8 BITS USED FOR

COMPARISON

ABSOLUTE VALUE

1111 1111 1111 (4095)

1111 1111 0000 (4080)

1000 0000 0000 (2048)

0000 0001 0000 (16)

0000 0000 0000 (0)

0111 1111 1111 (+2047)

0111 1111 0000 (+2032)

0000 0000 0000 (0)

111 1111 1111 (2047)

111 1111 0000 (2032)

000 0000 0000 (0)

1111 1111 (255)

1111 1110 (254)

0000 0000 (0)

1111 1110 (254)

1111 1111 (255)

1000 0001 0000 (–2032)

1000 0000 0000 (–2048)

111 1111 0000 (2032)

111 1111 1111 (2047)

Over-range detection is enabled by setting OVR_EN to 1. If the upper 8 bits of the absolute value equal

or exceed the OVR_TH threshold during the monitoring period, then the over-range bit associated with the

over-ranged ADC channel is set to 1, otherwise the over-range bit is 0. For the Quad channel device, the

over-range status can be monitored on the ORA, ORB, ORC or ORD output pins for ADC channels A, B, C

and D, respectively. For the dual channel device, the over-range status can be monitored on the ORA or ORB

output pins for ADC channels A and B, respectively. For the single channel device, the over-range status can be

monitored on the ORA output pins. OVR_N can be used to set the output pulse duration from the last over-range

event. Table 8-3 lists the over-range pulse lengths for the various OVR_N settings.

Table 8-3. Over-range Monitoring Period

over-range PULSE LENGTH SINCE LAST over-range EVENT

OVR_N

(DEVCLK Cycles)

0

1

2

3

4

5

6

7

8

16

32

64

128

256

512

1024

Typically, the OVR_TH threshold is set near the 8-bit full-scale value (228 for example). When the threshold

is triggered, a typical system turns down the system gain to avoid clipping. The downstream logic device then

monitors the output samples to determine when the over-range condition no longer exists and then increases the

system gain as desired.

8.3.2.4.5 Code Error Rate (CER)

ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle

codes, resulting from meta-stability caused by non-ideal comparator limitations. The device uses a unique

ADC architecture that inherently allows significant code error rate improvements from traditional pipelined flash

or successive approximation register (SAR) ADCs. The code error rate of the device is multiple orders of

magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing

significant signal reliability improvements.

8.3.3 Temperature Monitoring Diode

A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE– pins. This diode facilitates

temperature monitoring and characterization of the device in higher ambient temperature environments.

Although the on-chip diode is not highly characterized, the diode can be used effectively by performing a

baseline measurement (offset) at a known ambient or board temperature and creating a linear equation with

the diode voltage slope provided in the DC Specifications table. Perform offset measurement with the device

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unpowered or with the PD pin asserted to minimize device self-heating. Only assert the PD pin long enough

to take the offset measurement. Recommended monitoring devices include the LM95233 device and similar

remote-diode temperature monitoring products from Texas Instruments.

8.3.4 Timestamp

The TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample

based on the timing of an external trigger event relative to the sampled signal. The TMSTP± input is retimed

to the internal sampling clock and can be repeated out of the TRIGOUT± output to trigger external devices,

such as a laser driver, when TRIGOUT_EN is set to 1 to enable the TRIGOUT± output and TRIGOUT_MODE

is set to 3. The TMSTP± input can also be sent over the JESD204C interface to mark a specific ADC sample.

TIME_STAMP_EN must be set in order to output the timestamp data. When enabled, the timestamp signal

is sent over the JESD204C interface in place of the LSB of the JESD204C mode sample size (based on N'

parameter in Table 8-16, Table 8-17 and Table 8-18). For example, in JMODE 0 the JESD204C sample size (N')

is 12 and therefore the timestamp information is sent at LSB ([0]) bit location and the 12-bit sample (truncated to

11-bits) is sent in the [11:1] bit location. The input applied to TMSTP± can be asynchronous to the ADC sampling

clock and is sampled at approximately the same time as the analog input. Effectively, the TMSTP± input acts

as a 1-bit ADC sampled in parallel with the ADC cores and both have matched latency through the device. The

TMSTP± input must be enabled (TMSTP_RECV_EN) to use the timestamp feature.

8.3.5 Clocking

The input to the clocking subsystem of the device includes two clock inputs (CLK± and SE_CLK) and a

synchronization signal (SYSREF±). An internal phase-locked loop (PLL) and voltage-controlled oscillator (VCO)

can optionally be used to generate the ADC sampling clock from a low frequency reference by setting the

PLL_EN pin high. The sampling clock PLL is called the converter PLL (C-PLL). The C-PLL reference can

be provided to either the CLK± differential input or the SE_CLK single-ended input. The single-ended C-PLL

reference input is selected by setting the PLLREF_SE pin high. For highest performance, the internal C-PLL can

be bypassed and the sampling clock provided directly to the CLK± input when PLL_EN and PLLREF_SE are

held low. Note that SE_CLK cannot be used if the C-PLL is disabled. The C-PLL reference clock can be sent to

either an FPGA or ASIC or to an adjacent device through the PLLREFO± LVDS output when the PLL is enabled.

Two additional copies or divided copies of PLLREFO can be output on ORC and ORD when enabled through the

CLKCFG[1:0] pins or through SPI. PLLREFO and the ORC and ORD clock outputs are available at device power

up when the CMOS control pins (PLL_EN, CLKCFG0 and CLKCFG1) are set appropriately and if PD is held low.

Toggling PD high to power down the device also powers down the clock outputs.

In addition, the SerDes block contains a PLL, called S-PLL, that generates the SerDes output clock from the

ADC sampling clock. The S-PLL generated clock can be divided and output from the TRIGOUT± LVDS output

and sent to an FPGA or ASIC to clock the SerDes receivers. The SYSREF signal is captured by the chosen

clock input (CLK± or SE_CLK). A SYSREF Windowing block is used to measure and optimize the setup and

hold timing of the SYSREF signal relative to the selected clock input. SYSREF Windowing relaxes the timing

requirement of the external signals. Figure 8-5 shows the clocking subsystem.

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JESD204C

Block

INx+

Dx+

Timestamp

Insertion

ADC Cores

INxt

Dxt

SerDes PLL

clock

÷RX_

DIV

S-PLL

TRIGOUT+

TRIGOUTt

TMSTP+

TMSTPt

TRIGOUT_SEL

TMSTP±

Capture

ADC core

sampling

clock (f_S)

PLL Bypass

DIVREF_D

÷1/2/4

Internal PLL+VCO (C-PLL)

CLK+

ORD

ORC

VCO

CLKt

PFD

& CP

÷V

÷P

DIVREF_C

÷1/2/4

PLL_EN

÷N

PLLREF_SE

SE_CLK

PLLREFO+

PLL reference

)

PLLREFOt

clock (f_PLLREF

SYSREF+

SYSREF Windowing

SYSREFt

Relatch

SYSREF

SYSREF_POS SYSREF_SEL

Figure 8-5. Clocking Subsystem

The clock generated by the C-PLL when the PLL is enabled or the clock provided to CLK± when the PLL is

disabled is used as the sampling clock for the ADC core as well as the clocking for the digital processing and

serializer S-PLL. Use a low-noise (low jitter) clock input, whether the PLL is enabled or disabled, to maintain high

signal-to-noise ratio (SNR) within the ADC.

8.3.5.1 Converter PLL (C-PLL) for Sampling Clock Generation

An internal PLL with integrated VCO, called the converter PLL (C-PLL), is available for the high-speed sampling

clock generation from a low-frequency reference signal to simplify system clocking architectures and to avoid

routing of high speed clocks around the circuit board. The C-PLL architecture is shown in Figure 8-6. The PLL is

enabled by setting the PLL_EN pin high.

PLL Bypass

Internal PLL+VCO (C-PLL)

To ADC cores, digital

logic, JESD204C,

SerDes core, S-PLL

CLK+

VCO

CLKt

PFD

& CP

÷V

÷P

PLL_EN

÷N

PLLREF_SE

SE_CLK

Figure 8-6. Converter PLL (C-PLL) Architecture

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The PLL takes a low-frequency reference clock from the CLK± pins if the PLLREF_SE pin is set low or the

SE_CLK pin if the PLLREF_SE pin is set high. The reference clock is applied directly to the phase-frequency

detector (PFD). The PFD compares the reference clock phase to the phase of the clock divided-down from the

VCO. Therefore, the VCO frequency (f_VCO) divided by all of the dividers in the path (V, P, N) must be equal to the

reference clock frequency (f_REF). The sampling frequency (f_S) is then the reference frequency times the N divider

or the VCO frequency divided by the V and P dividers. The equations governing the PLL operation are given by

Equation 2 and Equation 3.

f_S= f_VCO÷ (V × P)

(2)

where

•

f_Sis the ADC core sampling rate

f_VCOis the VCO frequency

V is the VCO divider

P is the VCO prescalar

f_REF× N = f_S

(3)

where

•

f_REFis the PLL reference frequency

N is the PLL feedback divider

Equation 4 can be used to calculate the product of the V and P dividers (V × P). Simply choose V and P such

that their product equals the calculated product. Equation 5 can be used to calculate the N divider based on the

desired sampling rate and reference frequency.

V × P = f_VCO÷ f_S

N = f_S÷ f_REF

(4)

(5)

The VCO in the device has a limited tuning range which limits the ADC sampling rates that can be generated by

the PLL. The available VCO divisors (product of P and V) and resulting sampling rates are provided in Table 8-4.

Only the sampling rates in Table 8-4 are available in the device when the PLL is enabled. If the desired sampling

rate is not supported by the PLL then the PLL must be disabled and the desired sampling clock provided to the

CLK± pins.

Table 8-4. Available VCO Divisors and Achievable ADC Sampling Rates

VCO Divisor (P × V)

Minimum ADC Core Sampling Rate

Maximum ADC Core Sampling Rate

10

12

16

720 MSPS

600 MSPS

500 MSPS

800 MSPS

683 MSPS

513 MSPS

The C-PLL should be held in reset before changing any of the C-PLL settings by setting register CPLL_RESET

to 1 (address = 0x5C CPLL_RESET). The C-PLL dividers can be programmed using registers PLL_P_DIV

(address = 0x3D CPLL_FBDIV1), PLL_V_DIV (address = 0x03D CPLL_FBDIV1) and PLL_N_DIV (address

= 0x3E CPLL_FBDIV2). After programming the dividers the VCO calibration should be run by first setting

register VCO_CAL_EN to 1 (address = 0x5D VCO_CAL_CNTL). The VCO calibration is run when register

CPLL_RESET (address = 0x5C CPLL_RESET) is set to 0 to take the C-PLL out of reset. Calibration is finished

and the C-PLL is locked when register VCO_CAL_DONE (address = 0x5E VCO_CAL_STATUS) returns 1 and

register CPLL_LOCKED (address = 0x208 JESD_STATUS) is 1.

The C-PLL includes noise suppression options for the VA11Q and VCLK11 that reduce the sampling jitter and

reference clock input spur at the expense of approximately 20mA of current each. The control bits are found in

the CLK_CTRL2 register (address = 0x2B CLK_CTRL2).

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8.3.5.2 LVDS Clock Outputs (PLLREFO±, TRIGOUT±)

Two LVDS clock outputs are provided to simplify system clocking architectures. These outputs are shown in

Figure 8-5. The first LVDS clock output is PLLREFO±. PLLREFO± repeats the PLL reference clock directly from

the selected reference clock input (CLK± or SE_CLK) as determined by PLLREF_SE. The PLLREFO± output

is automatically enabled when the C-PLL is enabled, but can be disabled by setting PLLREFO_EN to 0. This

output is only available when the PLL_EN pin is set high and when PD is set low. Setting PD high disables

this output; and therefore, PD should not be used if PLLREFO± is necessary for system operation. Example

use cases for PLLREFO± include driving the digital core fabric of an FPGA or ASIC or it can be daisy chained

to the CLK± input pins of an additional device to provide the PLL reference clock for the second device. The

PLLREFO± outputs can be daisy chained to the CLK± inputs of as many ADC12xJ800 devices as required by

the system. Note that SYSREF must be provided from a separate clock source (clock chip, FPGA, ASIC, etc)

and setup and hold times must be met at each device relative to the reference clock input in order to achieve

deterministic latency and synchronization.

The second LVDS clock output is TRIGOUT±. This output can come from either the TMSTP± input (as a

timestamp or trigger output) or from the JESD204C SerDes PLL (S-PLL). This clock output is not available

at device startup and must be enabled through the SPI interface. The S-PLL can be divided by the RX_DIV

divider and output from the TRIGOUT± pins as a reference clock for FPGA or ASIC transceiver block.

Enable the TRIGOUT± output and set the TRIGOUT± operating mode (including RX_DIV divider) through the

TRIGOUT_CTRL register. The TRIGOUT± clock output frequency can be calculated by Equation 6 when the

S-PLL is chosen as the TRIGOUT± source.

f_TRIGOUT= f_LINERATE÷ RX_DIV

(6)

where

•

f_TRIGOUTis the TRIGOUT± output clock frequency (MHz)

f_LINERATEis the SerDes linerate (Mbps)

RX_DIV is the S-PLL output divider

8.3.5.3 Optional CMOS Clock Outputs (ORC, ORD)

Additional CMOS PLL reference clock outputs are available on ORC and ORD when configured through

CLKCFG[1:0] or through SPI. The clock outputs are available at device power up when CLKCFG[1:0] are

used to enable the clock outputs and when PD is held low. Setting the PD pin high disables these outputs; and

therefore, the PD pin should not be used when these clocks are necessary for system operation. SPI register

overrides are available for the CLKCFG[1:0] pins through the DIVREF_C_MODE and DIVREF_D_MODE SPI

register settings. Note that CLKCFG[1:0] can be used to enable or disable ORC and ORD and set the output

divider for ORC, but cannot set the output divider for ORD (enable or disable only). The DIVREF_C and

DIVREF_D functionality has higher priority than over-range as reflected in Table 8-5 and Table 8-6. Using these

outputs as clock outputs results in spurs in the ADC output spectrum at the output frequency and harmonics of

the output frequency. Limit the capacitive loading on these outputs to less than 10 pF to limit the noise impact.

Note

The DIVREF_D function is only available if DIVREF_C is also enabled (DIVREF_C_MODE > 0). If

only one clock output is required connect the external device to ORC and enable the DIVREF_C

function.

Table 8-5. Setting ORC Functionality

CPLL_OVR_EN

CLKCFG1

CLKCFG0

DIVREF_C_MODE

OVR_EN

ORC Function

0

X

0

Disabled

Quad channel: Over-

range for channel C

Dual/single channel:

Disabled

0

1

X

1

X

PLL Reference

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Table 8-5. Setting ORC Functionality (continued)

CPLL_OVR_EN

CLKCFG1

CLKCFG0

DIVREF_C_MODE

OVR_EN

ORC Function

0

1

X

0

1

X

0

PLL Reference / 2

PLL Reference / 4

Disabled

0x0

Quad channel: Over-

range for channel C

Dual/single channel:

Disabled

1

X

0x0

1

X

0x1

0x2

0x3

X

PLL Reference

PLL Reference / 2

PLL Reference / 4

Table 8-6. Setting ORD Functionality

CPLL_OVR_EN

CLKCFG1

CLKCFG0

DIVREF_D_MODE

OVR_EN

ORD Function

0

X

0

Disabled

Quad channel: Over-

range for channel C

Dual/single channel:

Disabled

0

X

1

0

1

0

1

0

1

0

X

0

PLL Reference

Disabled

X

0x0

Quad channel: Over-

range for channel C

Dual/single channel:

Disabled

1

X

0x0

1

X

0x1

0x2

0x3

X

PLL Reference

PLL Reference / 2

PLL Reference / 4

8.3.5.4 SYSREF for JESD204C Subclass-1 Deterministic Latency

SYSREF is a system timing reference used for JESD204C subclass-1 implementations of deterministic latency.

SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be

captured by the correct device clock edge in order to achieve repeatable latency and synchronization. The

device includes a SYSREF Windowing feature to ease the requirements on the external clocking circuits and

to simplify the synchronization process. SYSREF Windowing replaces the traditional setup and hold times as

these are no longer required when SYSREF Windowing is used. SYSREF can be implemented as a single pulse

or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the

local multiframe clock frequency in 8B/10B encoding modes or the local extended multiblock clock frequency

in 64B/66B encoding modes. Equation 7 is used to calculate valid SYSREF frequencies in 8B/10B encoding

modes. In 64B/66B modes, the denominator changes to 66 × 32 × E × n, where E is the number of multiblocks in

an extended multiblock.

R ì f_CLK

f_SYSREF

=

10

ì

F

ì

K

ì

n

(7)

where

•

R and F are set by the JMODE setting (see Table 8-16, Table 8-17 and Table 8-18)

f_CLKis the device clock frequency (CLK±)

K is the programmed multiframe length (see Table 8-16, Table 8-17 and Table 8-18 for valid K settings)

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•

and n is any positive integer

8.3.5.4.1 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency

The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic

latency. The device uses the JESD204C subclass-1 method to achieve deterministic latency and

synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic clock (CLK± or

SE_CLK) edge at each system power-on and at each device in the system. This requirement imposes setup and

hold constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all

system operating conditions. The device includes a number of features to simplify this synchronization process

and to relax system timing constraints:

•

The ADC12xJ800 includes an integrated PLL and VCO to generate the high frequency sampling clock,

relaxing the timing requirement by requiring timing to only be met relative to a low frequency reference clock.

A SYSREF position detector (relative to CLK± or SE_CLK) and selectable SYSREF sampling position aid the

user in meeting setup and hold times over all conditions; see the SYSREF Windowing section

•

8.3.5.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF Windowing block is used to first detect the position of SYSREF relative to the input clock (CLK±

or SE_CLK) rising edge and then to select a desired SYSREF sampling instance, which is a delayed version

of the input clock, to maximize setup and hold timing margins. In many cases a single SYSREF sampling

position (SYSREF_SEL) is sufficient to meet timing for all systems (device-to-device variation) and conditions

(temperature and voltage variations). However, this feature can also be used by the system to expand the timing

window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system

variation at production test by finding a unique optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF Windowing block. First, apply the device clock and

SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored

in the SYSREF_POS field. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a

bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or

hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are

set to 0) the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to

that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances

is chosen. Ideally, SYSREF_POS and SYSREF_SEL are performed at the nominal operating conditions of the

system (temperature and supply voltage) to provide maximum margin for operating condition variations. This

process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every

system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF±

over operating conditions for a system by sweeping the system temperature and supply voltages. For systems

that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal

SYSREF sampling position as system operating conditions change. In general, a single value can be found that

meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from

a single clocking device.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When

SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are

finer. See the Timing Requirements table for delay step sizes when SYSREF_ZOOM is enabled and disabled.

In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition

region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0

and 23 of SYSREF_POS are always be set to 1 because there is insufficient information to determine if these

settings are close to a timing violation, although the actual valid window can extend beyond these sampling

positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit

location in SYSREF_POS. Table 8-7 lists some example SYSREF_POS readings and the optimal SYSREF_SEL

settings. Although 24 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only

allows selection of the first 16 sampling positions, corresponding to SYSREF_POS bits 0 to 15. The additional

SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In

general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in

the fourth example a value of 15 provides additional margin and can be selected instead.

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Table 8-7. Examples of SYSREF_POS Readings and SYSREF_SEL Selections

SYSREF_POS[23:0]

OPTIMAL SYSREF_SEL

0x02E[7:0]

(Largest Delay)

0x02C[7:0]⁽¹⁾

(Smallest Delay)

0x02D[7:0]⁽¹⁾

SETTING

b10000000

b10011000

b10000000

b10001100

b01100000

b00000000

b01100000

b00000011

b01100011

b00011001

b00110001

b00000001

b00011001

8 or 9

12

6 or 7

4 or 15

6

(1) Red coloration indicates the bits that are selected, as given in the last column of this table.

8.3.6 JESD204C Interface

The device uses a JESD204C high-speed serial interface for data converters to transfer data from the ADC

to the receiving logic device. The device serialized lanes are capable of operating with both 8B/10B encoding

and 64B/66B encoding. The JESD204C output formats using 8B/10B encoding are backwards compatible with

existing JESD204B receivers. A maximum of 8 lanes can be used to lower lane rates for interfacing with

speed-limited logic devices. There are a few differences between 8B/10B and 64B/66B encoded JESD204C,

which is highlighted throughout this section. Figure 8-7 shows a simplified block diagram of the 8B/10B encoded

JESD204C interface and Figure 8-8 shows a simplified block diagram of the 64B/66B encoded JESD204C

interface.

ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Optional)

8B/10B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204B or JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Optional)

8B/10B

LINK LAYER

SERDES

RX PHY

Figure 8-7. Simplified 8B/10B Encoded JESD204C Interface Diagram

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ADC

JESD204C Block

TRANSPORT

LAYER

SCRAMBLER

(Required)

64B/66B

LINK LAYER

SERDES

TX PHY

ADC

ANALOG

CHANNEL

Logic Device

JESD204C Block

APPLICATION

LAYER

TRANSPORT

LAYER

DESCRAMBLE

(Required)

64B/66B

LINK LAYER

SERDES

RX PHY

Figure 8-8. Simplified 64B/66B Encoded JESD204C Interface Diagram

The various signals used in the JESD204C interface and the associated ADC12xJ800 pin names are

summarized briefly in Table 8-8 for reference. Most of the signals are common between 8B/10B and 64B/66B

encoded JESD204C, except for SYNC which is not needed to achieve block synchronization for 64B/66B

encoding. The sync header encoded into the data stream is used for block synchronization instead of the SYNC

signal.

Table 8-8. Summary of JESD204C Signals

SIGNAL NAME

PIN NAMES

8B/10B

64B/66B

DESCRIPTION

High-speed serialized data

after 8B/10B or 64B/66B

encoding

Quad/dual channel: D[7:0]+, D[7:0]–

Single channel: D[3:0]+, D[3:0]–

Data

Yes

Link initialization signal

(handshake), toggles low

to start code group

synchronization (CGS)

process. Not used for

64B/66B encoding modes,

unless it is used for NCO

synchronization purposes.

SYNC

SYNCSE

Yes

No

ADC sampling clock or PLL

reference clock, also used

for clocking digital logic and

output serializers

Device clock

SYSREF

CLK+, CLK– or SE_CLK

SYSREF+, SYSREF–

Yes

System timing reference used

to deterministically reset the

internal local multiframe clock

(LMFC) or local extended

multiblock clock (LEMC)

counters in each JESD204C

device

Not all optional features of JESD204C are supported by ADC12xJ800. The list of features that are supported

and the features that are not supported is provided in Table 8-9.

Table 8-9. Declaration of Supported JESD204C Features

REFERENCE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12xJ800

CLAUSE

clause 8

clause 7

a

b

8B/10B link layer

64B/66B link layer

Supported

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Table 8-9. Declaration of Supported JESD204C Features (continued)

REFERENCE

CLAUSE

LETTER IDENTIFIER

FEATURE

SUPPORT IN ADC12xJ800

c

clause 7

64B/80B link layer

Not supported

The command channel when using the

64B/66B or 64B/80B link layer

d

Forward error correction (FEC) when using

the 64B/66B or 64B/80B link layer

e

f

clause 7

Supported

Not supported

Supported

CRC3 when using the 64B/66B or 64B/80B

link layer

A physical SYNC pin when using the 8B/10B

link layer

g

h

clause 8

Not supported, but subclass 1 transmitter is

compatible with subclass 0 receiver

clause 7, clause 8

Subclass 0

i

j

clause 7, clause 8

clause 8

Subclass 1

Subclass 2

Supported

Not supported

Supported

k

clause 7, clause 8

Lane alignment within a single link

Subclass 1 with support for a lane alignment

on a multipoint link by means of the

MULTIREF signal

l

clause 7, clause 8

Not supported

SYNC interface timing is compatible with

JESD204A

m

n

clause 8

Supported

SYNC interface timing is compatible with

JESD204B

8.3.6.1 Transport Layer

The transport layer takes samples from the ADC output and maps the samples into octets inside of frames.

These frames are then mapped onto the available lanes. The mapping of octets into frames and frames onto

lanes is defined by the transport layer settings such as L, M, F, S, N and N'. An octet is 8 bits (before 8B/10B or

64B/66B encoding), a frame consists of F octets and the frames are mapped onto L lanes. Samples are N bits,

but sent as N' bits across the link. The samples come from M converters and there are S samples per converter

per frame cycle. M is sometimes artificially increased in order to obtain a more desirable mapping, for instance

lower latency may be achieved with a larger M value for long frames.

There are a number of predefined transport layer modes in the device that are defined in Table 8-16, Table 8-17

and Table 8-18. The high level configuration parameters for the transport layer in the device are described in

Table 8-14. The transport layer mode is chosen by simply setting the JMODE register setting. For reference, the

various configuration parameters for JESD204C are defined in Table 8-15.

The link layer further maps the frames into multiframes when using 8B/10B encoding or blocks, multiblocks and

extended multiblocks when using 64B/66B encoding.

8.3.6.2 Scrambler

A data scrambler is available to scramble the data before transmission across the channel. Scrambling is

used to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The

scrambler is optional for 8B/10B encoded modes, however it is mandatory for 64B/66B encoded modes in order

to have sufficient spectral content for clock recovery and adaptive equalization. The scrambler operates on

the data before encoding, such that the 8B/10B scrambler scrambles the 8-bit octets before 10-bit encoding

and the 64B/66B scrambler scrambles the 64-bit block before the sync header insertion (66-bit encoding). The

JESD204C receiver automatically synchronizes its descrambler to the incoming scrambled data stream. For

8B/10B encoding, the initial lane alignment sequence (ILA) is never scrambled. Scrambling can be enabled by

setting SCR for 8B/10B encoding modes, but it is automatically enabled in 64B/66B modes. The scrambling

polynomial is different for 8B/10B encoding and 64B/66B encoding schemes as defined by the JESD204C

standard.

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8.3.6.3 Link Layer

The link layer serves multiple purposes in JESD204C for both 8B/10B and 64B/66B encoding schemes,

however there are some differences in implementation for each encoding scheme. In general, the link layer

responsibilities include scrambling of the data (see Scrambler), establishing the code (8B/10B) or block (64B/

66B) boundaries and the multiframe (8B/10B) or multiblock (64B/66B) boundaries, initializing the link, encoding

the data, and monitoring the health of the link. This section is split into an 8B/10B section (8B/10B Link Layer)

and a 64B/66B section (64B/66B Link Layer) in order to cover the specific implementation for each encoding

scheme.

8.3.6.4 8B/10B Link Layer

This section covers the link layer for the 8B/10B encoding operating modes including initialization of the

character, frame and multiframe boundaries, alignment of the lanes, 8B/10B encoding and monitoring of the

frame and multiframe alignment during operation.

8.3.6.4.1 Data Encoding (8B/10B)

The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across

the link using 8B/10B encoding. 8B/10B encoding ensures DC balance to allow use of AC-coupling between

the SerDes transmitter and receiver and specify a sufficient number of edge transitions for the receiver to

reliably recover the data clock. 8B/10B encoding also provides some error detection since a single bit error in a

character likely results in either not being able to find the 10-bit character in the 8B/10B decoder lookup table or

an incorrect character disparity.

8.3.6.4.2 Multiframes and the Local Multiframe Clock (LMFC)

The frames from the transport layer are combined into multiframes which are used in the process of achieving

deterministic latency in subclass 1 implementations. The length of a multiframe is set by the K parameter which

defines the number of frames in a multiframe. JESD204C increases the maximum allowed number of frames

per multiframe (K) from 32 in JESD204B to 256 in JESD204C to allow a longer multiframe to ease deterministic

latency requirements. The total allowed range of K is defined by the inequality ceil(17/F) ≤ K ≤ min(256,

floor(1024/F)) where ceil() and floor() are the ceiling and floor function, respectively. The local multiframe clock

(LMFC) keeps track of the start and end of a multiframe for deterministic latency and data synchronization

purposes. The LMFC is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver

in order to act as a timing reference for deterministic latency. The LMFC clock frequency is given in Equation

8 where f_BITis the serialized bit rate (line rate) of the SerDes interface and F and K are as defined above.

The frequency of SYSREF must equal to or an integer division of f_LMFCwhen using 8B/10B encoding modes if

SYSREF is a continuous signal.

f_LMFC= f_BIT/ (10 × F × K)

(8)

8.3.6.4.3 Code Group Synchronization (CGS)

The first step in initializing the JESD204C link, after the LMFC is deterministically reset by SYSREF, is for the

receiver to find the boundaries of the encoded 10-bit characters sent across each SerDes lane. This process is

called code group synchronization (CGS). The receiver first asserts the SYNC signal (set to logic '0') when ready

to initialize the link. The transmitter responds to the request by sending a stream of K28.5 comma characters.

The receiver aligns its character clock to the K28.5 character sequence and CGS is achieved after successfully

receiving four consecutive K28.5 characters. The receiver deasserts SYNC (set to logic '1') on the next LMFC

edge after CGS is achieved and waits for the transmitter to start the initial lane alignment sequence (ILAS).

8.3.6.4.4 Initial Lane Alignment Sequence (ILAS)

After the transmitter detects the SYNC signal deassert (logic '0' to logic '1' transition), the transmitter waits

until its next LMFC edge to start sending the initial lane alignment sequence (ILAS). The ILAS consists of

four multiframes each containing a predetermined sequence. The receiver searches for the start of the ILAS to

determine the frame and multiframe boundaries. Each multiframe of the ILAS starts with a /R/ character (K28.0)

and ends with a /A/ character (K28.3) and either can be used to detect the boundary of a multiframe. Each lane

starts buffering its data in the elastic buffer once the ILAS reaches the receiver, starting with the /R/ character,

until all receivers have received the ILAS and subsequently release the ILAS from all lanes at the same time in

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order to align the lanes. The elastic buffer release point is chosen to avoid ambiguity in the release of the data

caused by variation in the data delay (arrival of the ILAS at the receiver for each lane). The second multiframe of

the ILAS contains configuration parameters for the JESD204C link configuration that can be used by the receiver

to verify that the transmitter and receiver configurations match.

8.3.6.4.5 Frame and Multiframe Monitoring

The device supports frame and multiframe monitoring for verifying the health of the JESD204C link when

using 8B/10B encoding. The scheme changes depending on the use of scrambling. The implementation when

scrambling is disabled is covered first. If the last octet of the current frame matches the last octet of the previous

frame, then the last octet of the current frame is encoded as an /F/ (K28.7) character. If the current frame is

also the last frame of a multiframe, then an /A/ (K28.3) character is used instead. Neither an /F/ or /A/ character

should occur in a normal data stream, except when replaced by the transmitter for alignment monitoring. When

the receiver detects an /F/ or /A/ character in the normal data stream the receiver checks to see if the character

occurs at the location expected to be the end of a frame or multiframe. If the character occurs at a location

other than the end of a frame or multiframe then either the transmitter or receiver has become misaligned.

The receiver replaces the alignment character with the appropriate data character upon reception of a properly

aligned /F/ or /A/ character. The appropriate data character is the last octet of the previously received frame. This

scheme increases the probability of an alignment character for non-scrambled data streams.

The implementation when scrambling is enabled is slightly different since the octets are randomized. If the last

octet of a frame is 0xFC (before 8B/10B encoding) then the transmitter encodes the octet as an /F/ (/K28.7/)

character. If the last octet of a multiframe is 0x7C (before 8B/10B encoding) then the transmitter encodes the

octet as an /A/ (/K28.3/) character. The location of the /A/ and /F/ characters is monitored to verify proper frame

and multiframe alignment. The receiver replaces the alignment characters by simply replacing an /F/ character

with the 0xFC octet and an /A/ character with the 0x7C octet.

The receiver can report an error if multiple alignment characters occur in the incorrect location or do not

occur when expected. Upon detection of a frame or multiframe misalignment, the receiver should trigger a link

realignment by asserting SYNC. SYSREF should also be reissued to verify that the LMFC in the transmitter and

receiver have proper alignment before restarting the link.

8.3.6.5 64B/66B Link Layer

This section covers the link layer for the 64B/66B encoding operating modes which includes scrambling of the

data, addition of the sync headers (64B/66B encoding), the structure of the block and multiblock, the sync

header, cyclic redundancy checking (CRC), forward error correction (FEC) and link alignment.

8.3.6.5.1 64B/66B Encoding

The frames formed by the transport layer are packed into 8-octet long blocks (64 bits). This 64-bit block is

scrambled and then a 2-bit sync header (SH) is appended to form a 66-bit transmission block. The sync header

is used for block synchronization by marking the end of a block as well as allowing for cyclic redundancy

checking (CRC), forward error correction (FEC) or a command channel. The structure of a block is given in Table

8-10 where SH represents the appended 2-bit sync header.

Table 8-10. Structure of 64B/66B Block with Sync Header

SH

OCTET0

OCTET1

OCTET2

OCTET3

OCTET4

OCTET5

OCTET6

OCTET7

[0:1]

[2:9]

[10:17]

[18:25]

[26:33]

[34:41]

[42:49]

[50:57]

[58:65]

8.3.6.5.2 Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)

A multiblock is a 32 block container which consists of a concatenation of 32 blocks. An extended multiblock is

a concatenation of multiple multiblocks, where E defines the number of multiblocks in an extended multiblock.

A frame can be split between blocks and multiblocks, but there must be an integer number of frames in an

extended multiblock. An extended multiblock is only necessary when a multiblock does not have an integer

number of frames. If an extended multiblock is not used, because a multiblock contains an integer number of

frames, then the E parameter is equal to 1 to indicate that there is one multiblock in an extended multiblock.

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An extended multiblock is analogous to a multiframe in the 8B/10B transport layer. The local extended mutiblock

clock (LEMC) keeps track of the start and end of a multiblock for deterministic latency and data synchronization

purposes in the same way the LMFC tracks the start and end of a multiframe in 8B/10B encoding. The LEMC

is reset by the SYSREF signal to a deterministic phase in both the transmitter and receiver in order to act as

a timing reference for deterministic latency. The LEMC clock frequency is defined by Equation 9 where f_BITis

the serialized bit rate (line rate) of the SerDes interface. The frequency of SYSREF must equal to or an integer

division of f_LMFCwhen using 64B/66B encoding modes if SYSREF is a continuous signal.

f_LEMC= f_BIT/ (66 × 32 × E)

(9)

8.3.6.5.2.1 Block, Multiblock and Extended Multiblock Alignment using Sync Header

The sync header contains two bits that are always opposite of each other (either 01 or 10). The JESD204C

receiver can find the block boundaries by looking for a 66-bit boundary that always contains a 0 to 1 or 1 to

0 transition. Although 0 to 1 and 1 to 0 transitions occur at other locations in a block, it is impossible for the

sequence to appear at a fixed location, other than the proper sync header location, in successive blocks for

a long period of time. The sync header indicates the start of a block and can be used for block alignment

monitoring. If a 00 or a 11 bit sequence is seen at the assumed sync header location of a block, then block

alignment may have been lost. Multiple occurrences of incorrect sync header bits should trigger a search for the

sync header after sending SYSREF to all devices to reset LEMC alignment.

A sync header ([0:1]) of 01 corresponds to transmission of a 1 while a sync header of 10 corresponds to a

transmission of a 0. The transmitted bit from the sync header of each block of a multiblock are combined into

a 32-bit word called the sync header stream. The sync header stream is used to transmit data in parallel with

the user data in order to synchronize the link by marking the borders of multiblocks and extended multiblocks.

In addition, the sync header stream provides one of either CRC, FEC or a command channel. ADC12xJ800

supports CRC-12 and FEC and does not support CRC-3 or the command channel.

The 32-bit sync header stream always ends with a 00001 bit sequence, called the end-of-multiblock (EoMB)

signal, that indicates the end of a multiblock. For CRC and command channel modes, a 00001 sequence never

occur in any other location in the sync header stream. For FEC mode, it is possible for a 00001 sequence to

appear in another location within the sync header stream, however it is improbable to see the 00001 sequence in

the same location within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one

multiblock to find the end of a multiblock. The end of an extended multiblock is found for all modes by monitoring

bit 22 of the sync header stream, the EoEMB bit, which indicates the end of an extended multiblock when set

to a 1. The EoMB (00001) and EoEMB signals, as well as fixed 1s in the sync header stream for CRC and

command channel modes, form the pilot signal of the sync header stream.

The defined format for each form of the sync header stream are defined in the following sections.

8.3.6.5.2.1.1 Cyclic Redundancy Check (CRC) Mode

The cyclic redundancy check (CRC) mode is available to allow detection of potential bit errors during

transmission. Support for the 12-bit word CRC-12 mode is required by JESD204C, while a 3-bit word CRC-3

mode is optional. The device does not support the CRC-3 mode and therefore this section is specific to the

CRC-12 mode only. The transmitter computes the CRC-12 parity bits from the scrambled data bits of the 32

blocks of a multiblock. The 12-bit CRC parity word is then transmitted in the sync header stream of the next

multiblock. The receiver computes the 12-bit parity word of the received multiblock and compares it against the

received 12-bit parity word of the next multiblock. A difference indicates that there is at least one error in the

received data bits or in the received 12-bit parity word. The minimum latency to the detection of a bit error in the

first data bit of a multiblock is 46 blocks. Enable CRC-12 mode by setting SHMODE to 0.

The mapping of the sync header stream when using the CRC-12 mode is shown in Table 8-11. CRC[x]

corresponds to bit x of the 12-bit CRC word. Cmd[x] corresponds to bit x of the 7 bit command word, which

are always set to 0s in the device. The 00001 bit sequence at the end of the sync header stream is the pilot

signal that is used to identify the end of a multiblock. The 1s that occur throughout the sync header ensure

that the pilot signal can only be seen at the end of the sync header, allowing multiblock alignment after only a

single multiblock has been received. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last

multiblock of an extended multiblock.

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Table 8-11. Sync Header Stream Bit Mapping for CRC-12 Mode

Bit

0

Function

CRC[11]

CRC[10]

CRC[9]

1

Bit

Function

CRC[5]

CRC[4]

CRC[3]

1

Bit

16

17

18

19

20

21

22

23

Function

Cmd[6]

Cmd[5]

Cmd[4]

1

Bit

24

25

26

27

28

29

30

31

Function

8

Cmd[2]

1

9

Cmd[1]

2

10

11

12

13

14

15

Cmd[0]

3

0

1

4

CRC[8]

CRC[7]

CRC[6]

1

CRC[2]

CRC[1]

CRC[0]

1

Cmd[3]

1

5

6

EoEMB

1

7

The CRC-12 encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 12-bit parity

word using the generator polynomial given by Equation 10. The polynomial is sufficient to detect all 2-bit errors in

a multiblock, spanning any distance, and burst error sequences of up to 12-bits in length. The probability of not

detecting a 3-bit error spanning any distance in a multiblock is approximately 0.004%.

0x987 == x¹²+x⁹+x⁸+x³+x²+x+1

(10)

The full parity bit generation for CRC-12 is shown in Figure 8-9. The input is a 2048 bit sequence, built from the

32 scrambled blocks of a multiblock (sync header is not included). The 12-bit parity word, CRC[11:0], is taken

from the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0s before

processing each multiblock. For more information on the CRC-12 parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x

x²

x³

x⁸

x⁹

x¹²

S₁₁

S₀

S₁

S₂

S₃

S₄

S₅

S₆

S₇

S₈

S₉

S₁₀

CRC[0]

CRC[1]

CRC[2]

CRC[3] CRC[4] CRC[5] CRC[6] CRC[7]

CRC[8]

CRC[9] CRC[10] CRC[11]

Figure 8-9. CRC-12 Parity Bit Generator

8.3.6.5.2.1.2 Forward Error Correction (FEC) Mode

Forward error correction (FEC) is an optional feature in JESD204C and is supported by ADC12xJ800. Whereas

CRC-12 mode can only detect errors on the link, FEC is able to detect and correct errors in order to improve the

bit error rate (BER) for error-sensitive applications. Many applications can tolerate random bit errors, however

some applications, such as an oscilloscope, rely on long error-free measurements in order to detect a certain

response from the device under test (DUT). An error in these applications may result in a false-positive detection

of the response. Enable FEC mode by setting SHMODE to 2.

A scrambled multiblock of 32 blocks (2048 bits) is input into the FEC parity bit generator to generate the

26-bit parity word. The parity word is sent in the sync header stream of the next multiblock. The receiver then

calculates its own 26-bit parity word and calculates the difference between the locally generated and received

parity word, called the syndrome of the received bits. If the syndrome is 0, then all bits are assumed to have

been received correctly, while any value other than 0 indicates at least one error in either the data bits or the

parity word. If the syndrome is non-zero, then it can be used to determine the most likely error and then correct

the error. The minimum latency from a bit error to detection and correct of a bit error in the first bit of a multiblock

is 58 blocks.

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The mapping of the sync header stream when using FEC mode is shown in Table 8-12. FEC[x] corresponds to

bit x of the 26-bit FEC word. The 00001 bit sequence at the end of the sync header stream is the pilot signal that

is used to identify the end of a multiblock. It is possible for a 00001 sequence to appear in another location within

the sync header stream in FEC mode, however it is improbable to see the 00001 sequence in the same location

within a sequence of multiple multiblocks. Therefore, in FEC mode it may take more than one multiblock to find

the end of a multiblock. EoEMB is the end-of-extended-multiblock bit, which is set to 1 for the last multiblock of

an extended multiblock.

Table 8-12. Sync Header Stream Bit Mapping for FEC Mode

Bit

0

Function

FEC[25]

FEC[24]

FEC[23]

FEC[22]

FEC[21]

FEC[20]

FEC[19]

FEC[18]

Bit

Function

FEC[17]

FEC[16]

FEC[15]

FEC[14]

FEC[13]

FEC[12]

FEC[11]

FEC[10]

Bit

16

17

18

19

20

21

22

23

Function

FEC[9]

FEC[8]

FEC[7]

FEC[6]

FEC[5]

FEC[4]

EoEMB

FEC[3]

Bit

24

25

26

27

28

29

30

31

Function

8

FEC[2]

1

9

FEC[1]

2

10

11

12

13

14

15

FEC[0]

3

0

1

4

5

6

7

The FEC encoder takes in a multiblock of 32 scrambled blocks (2048 bits) and computes the 26-bit parity word

using the generator polynomial given by Equation 11. The 2048 scrambled input bits plus 26 parity bits forms a

shortened (2074, 2048) binary cyclic code. The (2074, 2048) binary cyclic code is shortened from the cyclic Fire

code (8687, 8661). This polynomial can correct up to a 9-bit burst error per multiblock.

g(x) = (x¹⁷+1)(x⁹+x⁴+1) == x²⁶+x²¹+x¹⁷+x⁹+x⁴+1

(11)

The full 26-bit FEC parity word generation is shown in Figure 8-10. The input is a 2048 bit sequence, built from

the 32 scrambled blocks of a multiblock (sync header is not included). The 26-bit parity word, FEC[25:0], is taken

from the S_xblocks after the full 2048 bit sequence is processed. The S_xblocks are initialized with 0s before

processing each multiblock. For more information on the FEC parity word generation, refer to the JESD204C

standard.

32-block input

(2048 bits)

1

x⁴

x⁹

x¹⁷

x²¹

S₀

S₁

S₂

S₃

S₄

S₈

S₉

S₁₆

S₁₇

S₂₀

S₂₁

S₂₄

S₂₅

...

FEC[21] FEC[24] FEC[25]

FEC[0] FEC[1] FEC[2] FEC[3]

FEC[4]

FEC[8]

FEC[9]

FEC[16]

FEC[17]

FEC[20]

Figure 8-10. FEC Parity Bit Generator

FEC decoding and error correction are not covered here. For full details on FEC decoding and error correction,

refer to the JESD204C standard.

8.3.6.5.3 Initial Lane Alignment

The 64B/66B link layer does not use an initial lane alignment sequence (ILAS) like the 8B/10B link layer.

Therefore, the receiver must use a different scheme to align lanes using the elastic buffer. In 8B/10B mode, the

ILAS triggers the elastic buffer to start buffering the data for each lane. After all lanes have started buffering the

data, the elastic buffers for each lane are released at a release point determined by the release buffer delay

(RBD) parameter and the phase of the LMFC. In 64B/66B mode, the process starts by having all lanes achieve

block, multiblock and extended multiblock alignment. Once all lanes have achieved alignment, the receiver can

begin buffering data in the elastic buffers at the start of the next extended multiblock on each lane. The data is

released at the next release point after all lanes have seen the start of an extended multiblock and have started

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buffering the data. The release point is defined relative to the LEMC edge and the programmed RBD value, the

most intuitive of which is to release on the LEMC edge itself. The release point must be chosen to avoid the

region of the LEMC containing variation in the data delay on each lane from startup to startup.

8.3.6.5.4 Block, Multiblock and Extended Multiblock Alignment Monitoring

Synchronization of blocks, multiblocks and extended multiblocks by monitoring the sync header of each block

and EoMB and EoEMB bit of the sync header stream. A block always begins with a 0 to 1 or 1 to 0 transition

(sync header). A single missed sync header can occur due to a bit error, however if there are a number of sync

header errors within a set number of blocks, then block synchronization has been lost and block synchronization

should be reinitialized. It is possible to still have block synchronization, but to lose multiblock or extended

multiblock synchronization. Multiblock synchronization is monitored by looking for the EoMB signal, 00001, at

the end of the sync header stream for each multiblock. If multiple EoMB signals are erroneous within a number

of blocks, multiblock synchronization has been lost and multiblock synchronization should be reinitialized. If an

erroneous EoEMB bit is received for multiple extended multiblocks within a number of extended multiblocks,

such as a 1 for a multiblock that is not the end of an extended multiblock or a 0 for a multiblock that is the end of

an extended multiblock, then multiblock synchronization is lost and extended multiblock synchronization should

be reinitialized. If multiblock or extended multiblock synchronizaton is lost, SYSREF should be applied to the

erroneous devices in order to reestablish the LEMC before the synchronization process begins.

8.3.6.6 Physical Layer

The JESD204C physical layer consists of a current mode logic (CML) output driver and receiver. The receiver

consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data

stream and can contain a continuous time linear equalizer (CTLE) and/or discrete feedback equalizer (DFE)

to correct for the low-pass response of the physical transmission channel. Likewise, the transmitter can contain

pre-equalization to account for frequency dependent losses across the channel. The total reach of the SerDes

links depends on the data rate, board material, connectors, equalization, noise and jitter, and required bit-error

performance. The SerDes lanes do not have to be matched in length because the receiver aligns the lanes

during the initial lane alignment sequence.

8.3.6.6.1 SerDes Pre-Emphasis

The ADC12xJ800 high-speed output drivers can pre-equalize the transmitted data stream by using pre-

emphasis in order to compensate for the low-pass response of the transmission channel. Configurable pre-

emphasis settings allow the output drive waveform to be optimized for different PCB materials and signal

transmission distances. The pre-emphasis setting is adjusted through the serializer pre-emphasis setting

SER_PE. Higher values increase the pre-emphasis to compensate for more lossy PCB materials. This

adjustment is best used in conjunction with an eye-diagram analysis capability in the receiver. Adjust the

pre-emphasis setting to optimize the eye-opening for the specific hardware configuration and line rates needed.

8.3.6.7 JESD204C Enable

The JESD204C interface must be disabled through JESD_EN while any of the other JESD204C parameters are

being changed. When JESD_EN is set to 0 the block is held in reset and the serializers are powered down. The

clocks for this section are also gated off to further save power. When the parameters are set as desired, the

JESD204C block can be enabled (JESD_EN is set to 1).

8.3.6.8 Multi-Device Synchronization and Deterministic Latency

JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices

achieve the same deterministic latency then they can be considered synchronized. This latency must be

achieved from system startup to startup to be deterministic. There are two key requirements to achieve

deterministic latency. The first is proper capture of SYSREF for which the device provides a number of features

to simplify this requirement at giga-sample clock rates (see the SYSREF Capture section for more information).

SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC

and LEMC are analogous between the two modes and is now referred to as LMFC/LEMC.

The second requirement is to choose a proper elastic buffer release point in the receiver. Because the device

is an ADC, the device is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX).

The elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the

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propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release

point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency

variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time

of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all

devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined,

which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must ensure that the

data for all lanes arrives at all devices after the previous release point occurs and before the next release point

occurs.

Figure 8-11 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is

shown. The second ADC has a longer routing distance (t_PCB) and results in a longer link delay. First, the invalid

region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the

release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate

number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the

LMFC/LEMC cycle. In the case of Figure 8-11, the LMFC/LEMC edge (RBD = 0) is a good choice for the release

point because there is sufficient margin on each side of the valid region.

Nominal Link Delay

Link Delay

(Arrival at Elastic Buffer)

Variation

ADC 1 Data

t_TX

t_PCB

t_RX-DESER

Propagation

Choose LMFC/LEMC

edge as release point

(RBD = 0)

ADC 2 Data

Propagation

t_TX

t_PCB

t_RX-DESER

Release point

margin

TX LMFC/LEMC

RX LMFC/LEMC

Time

Invalid Region

of LMFC/LEMC

Valid Region of

LMFC/LEMC

Figure 8-11. LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection

The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is

important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within

every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link

delay can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the

requirements for more information.

8.3.6.9 Operation in Subclass 0 Systems

The device can operate with subclass 0 compatibility provided that multi-ADC synchronization and deterministic

latency are not required. With these limitations, the device can operate without the application of SYSREF. The

internal LMFC/LEMC is automatically self-generated with unknown timing. SYNC is used as normal to initiate the

CGS and ILAS in 8B/10B mode.

8.3.6.10 Alarm Monitoring

A number of built-in alarms are available to monitor internal events. Several types of alarms and upsets are

detected by this feature:

1. C-PLL is not locked

2. S-PLL is not locked

3. JESD204C link is not transmitting data (not in the data transmission state)

4. SYSREF causes internal clocks to be realigned

5. An upset that impacts the internal clocks

6. A read or write error generated by the digital to serializer synchronizing FIFO

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When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the

host system writes a 1 to clear the alarm. If the alarm type is not masked (see the ALM_MASK register), then the

alarm is also indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output

that goes high when an alarm occurs; see CAL_STATUS_SEL.

8.3.6.10.1 Clock Upset Detection

The CLK_ALM register bit indicates if the internal clocks have been upset. The clocks in channel A are

continuously compared to channel B. If the clocks differ for even one DEVCLK / 2 cycle, the CLK_ALM register

bit is set and remains set until cleared by the host system by writing a 1. For the CLK_ALM register bit to

function properly, follow these steps:

1. Program JESD_EN = 0

2. Ensure the part is configured to use both channels (PD_ACH = 0, PD_BCH = 0)

3. Program JESD_EN = 1

4. Write CLK_ALM = 1 to clear CLK_ALM

5. Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured

6. When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and must be

cleared by writing a 1 to CLK_ALM

8.3.6.10.2 FIFO Upset Detection

The FIFO_LANE_ALM register bits indicate if an error has occurred in the synchronizing FIFO between the

digital logic block and serializer outputs. If the FIFO pointers are upset due to an undesired clock shift or

other single event or incorrect clocking frequencies the FIFO_LANE_ALM bit for the erroneous lane is set to 1.

Toggling JESD_EN to 0 and then 1 resets the FIFO logic.

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8.4 Device Functional Modes

The device can be configured to operate in a number of functional modes. These modes are described in this

section.

8.4.1 Low Power Mode and High Performance Mode

Device power consumption can be reduced at the tradeoff of performance by programming the device into the

Low Power Mode. This mode is recommended to only be used for 1^stNyquist zone applications. The default

operating mode is High Performance Mode which is enabled by the default register values. Table 8-13 shows

the register writes to switch between the lowest power configuration of Low Power Mode and High Performance

Mode. These writes should only be performed when CAL_EN is set to 0 and JESD_EN is set to 0.

Table 8-13. Low Power Mode Register Writes

High Performance Mode Value (Default

Register Name (Address)

Low Power Mode Value

Mode)

0x4B

0x0F

0x04

0x1B

LOW_POWER1 (0x037)

LOW_POWER2 (0x29A)

LOW_POWER3 (0x29B)

LOW_POWER4 (0x29C)

0x46

0x06

0x00

0x14

The magnitude of the glitch during the transition between ADC cores during background calibration and low

power background calibration is affected by the setting of the LOW_POWER3 register setting (Address =

0x29B). A lower power can be traded off vs larger glitch magnitude. The ADC output during the transition

between ADC cores for low power mode is shown in Figure 8-12 and the power dissipation change vs

LOW_POWER3 setting is shown in Figure 8-13. A setting of 4 reduces the glitch to the same magnitude as

high performance mode.

50

2500

LOW_POWER3 = 0

LOW_POWER3 = 1

LOW_POWER3 = 2

LOW_POWER3 = 4

2450

40

2400

2350

30

2300

2250

2200

2150

2100

2050

2000

20

10

0

1

2

LOW_POWER3 Setting

3

4

D128

Figure 8-13. Power Dissipation Change vs

LOW_POWER3 register setting

0

100 200 300 400 500 600 700 800 900 1000

Sample#

Figure 8-12. Background Calibration Core

Transition In Low Power Mode

In low power background calibration mode, the timing of the ADC transition can be controlled by setting register

LP_TRIG = 1. The ADC transition will occur in the ADC output data between 500 and 1000 ADC sample clocks

after triggering by the CALTRIG ball or SPI write to CAL_SOFT_TRIG register (Address = 0x6C).

Foreground calibration mode has no ADC core transitions and no glitch.

8.4.2 JESD204C Modes

The device can be programmed for a number JESD204C output formats. Table 8-14 summarizes the basic

operating mode configuration parameters and whether they are user configured or derived.

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Table 8-14. ADC12xJ800 Operating Mode Configuration Parameters

USER CONFIGURED

OR DERIVED

PARAMETER

JMODE

DESCRIPTION

VALUE

JESD204C operating mode, automatically

derives the rest of the JESD204C parameters

User configured

Set by JMODE

Number of bits transmitted per lane per ADC

core sampling clock cycle. The JESD204C

R

line rate is the sampling clock frequency (f_S) Derived

times R. This parameter sets the SerDes PLL

multiplication factor.

See Table 8-16, Table 8-17 and Table 8-18

Set by KM1, see the allowed values in

Table 8-16, Table 8-17 and Table 8-18. This

parameter is ignored in 64B/66B modes.

Number of frames per multiframe (8B/10B

mode)

K

E

User configured

Number of multiblocks per extended

multiblock (64B/66B mode)

Always set to '1' in ADC12xJ800. This

parameter is ignored in 8B/10B modes.

Derived

There are a number of parameters required to define the JESD204C transport layer format, all of which are sent

across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the

ILAS, however the transport layer uses the same parameters. In the device, most parameters are automatically

derived based on the selected JMODE; however, a few are configured by the user. Table 8-15 describes these

parameters.

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Table 8-15. JESD204C Initial Lane Alignment Sequence Parameters

USER CONFIGURED

OR DERIVED

PARAMETER

DESCRIPTION

VALUE

ADJCNT

ADJDIR

BID

LMFC adjustment amount (not applicable)

LMFC adjustment direction (not applicable)

Bank ID

Derived

Always 0

CF

Number of control words per frame

Always set to 0 in ILAS, see Table 8-16,

Table 8-17 and Table 8-18 for actual usage

CS

Control bits per sample

Derived

DID

F

Device identifier, used to identify the link

User configured

Set by DID, see Table 8-19

Number of octets (bytes) per frame (per lane) Derived

See Table 8-16, Table 8-17 and Table 8-18

High-density format (samples split between

lanes)

HD

Derived

Always 0

JESDV

JESD204 standard revision

Derived

Always 1

K

Number of frames per multiframe

Number of serial output lanes per link

Lane identifier for each lane

User configured

Derived

Set by the KM1 register

See Table 8-16, Table 8-17 and Table 8-18

See Table 8-19

L

LID

Derived

Number of converters used to determine lane

bit packing; may not match number of ADC

channels in the device

M

Derived

See Table 8-16, Table 8-17 and Table 8-18

Sample resolution (before adding control and

tail bits)

N

N'

S

Derived

See Table 8-16, Table 8-17 and Table 8-18

Bits per sample after adding control and tail

bits

Number of samples per converter (M) per

frame

SCR

Scrambler enabled

Device subclass version

Reserved field 1

User configured

Derived

Set by SCR

Always 1

Always 0

SUBCLASSV

RES1

Derived

RES2

Reserved field 2

Derived

Checksum for ILAS checking (sum of all

above parameters modulo 256)

CHKSUM

Derived

Computed based on parameters in this table

Configuring the device is made easy by using a single configuration parameter called JMODE. Using Table 8-16

for the quad channel device, Table 8-17 for the dual channel device or Table 8-18 for the single channel device,

the correct JMODE value can be found for the desired operating mode. The modes listed are the only available

operating modes. This tables also gives a range and allowable step size for the K parameter (set by KM1), which

sets the multiframe length in number of frames.

Table 8-16. Operating Modes for Quad Channel Device

USER-SPECIFIED

PARAMETER

DERIVED PARAMETERS

INPUT

CLOCK

RANGE

(MHz)

OPERATING MODE

R

(Fbit /

Fclk)

JMOD

K

Encoding

N

CS N’ CF

L

M

F

S

HD

E

[Min:Step:Max]

12-Bit, 8B/10B, 8 Lanes

12-Bit, 8B/10B, 6 Lanes

8-Bit, 8B/10B, 4 Lanes

10-Bit, 8B/10B, 4 Lanes

0

1

2

3

4:4:256

8B/10B

12

8

0

12

8

0

8

6

4

8⁽¹⁾

4

8

2

1

5

2

1

4

0

1

0

—

8

10

500-800

16:16:256

32:32:256

4

10

4

12.5

12-Bit, 64B/66B, 3

Lanes

4

5

128⁽²⁾

64B/66B

12

8

0

12

8

0

3

2

4

2

1

0

3

1

16.5

500-800

8-Bit, 64B/66B, 2 Lanes

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Table 8-16. Operating Modes for Quad Channel Device (continued)

USER-SPECIFIED

PARAMETER

DERIVED PARAMETERS

INPUT

CLOCK

RANGE

(MHz)

OPERATING MODE

R

(Fbit /

Fclk)

JMOD

K

Encoding

N

CS N’ CF

L

M

F

S

HD

E

[Min:Step:Max]

12-Bit, 64B/66B, 6

Lanes

6

7

8

128⁽²⁾

256⁽²⁾

64B/66B

12

8

0

12

8

0

6

4

2

1

3

2

1

2

1

0

3

1

3

8.25

500-800

8-Bit, 64B/66B, 4 Lanes

12-Bit, 64B/66B, 4

Lanes

12

12.375

8-Bit, 8B/10B, 8 Lanes

10-Bit, 8B/10B, 8 Lanes

9

32:32:256

8B/10B

8

0

8

0

8

4

1

5

2

4

0

—

5

500-800

10

8⁽¹⁾

6.25

12-Bit, 64B/66B, 8

Lanes

14

256⁽²⁾

64B/66B

12

0

12

0

8

8⁽¹⁾

3

2

0

3

6.1875

500-800

(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter

does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the

correct sample data; see mode diagrams for more details.

(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x

E/F. K is not an actual parameter of the 64B/66B link layer.

Table 8-17. Operating Modes for Dual Channel Device

USER-SPECIFIED

PARAMETER

DERIVED PARAMETERS

INPUT

CLOCK

RANGE

(MHz)

OPERATING MODE

R

(Fbit /

Fclk)

JMOD

K

Encoding

N

CS N’ CF

L

M

F

S

HD

E

[Min:Step:Max]

12-Bit, 8B/10B, 4 Lanes

12-Bit, 8B/10B, 3 Lanes

8-Bit, 8B/10B, 2 Lanes

10-Bit, 8B/10B, 2 Lanes

0

1

2

3

4:4:256

8B/10B

12

8

0

12

8

0

4

3

2

4⁽¹⁾

2

8

2

1

5

2

1

4

0

1

0

—

8

10

500-800

16:16:256

32:32:256

2

10

2

12.5

12-Bit, 64B/66B, 2

Lanes

4

5

6

7

8

128⁽²⁾

256⁽²⁾

64B/66B

12

8

0

12

8

0

2

1

3

2

1

3

1

2

1

2

1

0

1

0

3

1

3

1

3

16.5

500-800

8-Bit, 64B/66B, 1 Lane

12-Bit, 64B/66B, 3

Lanes

12

8

12

8

8.25

8-Bit, 64B/66B, 2 Lanes

8.25

12-Bit, 64B/66B, 2

Lanes

12

12.375

8-Bit, 8B/10B, 4 Lanes

10-Bit, 8B/10B, 4 Lanes

12-Bit, 8B/10B, 8 Lanes

8-Bit, 8B/10B, 8 Lanes

10-Bit, 8B/10B, 8 Lanes

9

32:32:256

4:4:256

8B/10B

8

0

8

0

3

4

8

2

1

5

8

1

5

2

4

5

4

0

—

5

6.25

4

500-800

10

11

12

13

10

12

8

10

12

8

4⁽¹⁾

8⁽¹⁾

2

32:32:256

2.5

10

8⁽¹⁾

3.125

12-Bit, 64B/66B, 4

Lanes

14

15

256⁽²⁾

64B/66B

12

0

12

0

4

8

4⁽¹⁾

8⁽¹⁾

3

2

0

2

3

2

6.1875

500-800

12-Bit, 64B/66B, 8

Lanes

3.09375

(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter

does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the

correct sample data; see mode diagrams for more details.

(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x

E/F. K is not an actual parameter of the 64B/66B link layer.

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Table 8-18. Operating Modes for Single Channel Device

USER-SPECIFIED

PARAMETER

DERIVED PARAMETERS

INPUT

CLOCK

RANGE

(MHz)

OPERATING MODE

R

(Fbit /

Fclk)

JMOD

K

Encoding

N

CS N’ CF

L

M

F

S

HD

E

[Min:Step:Max]

12-Bit, 8B/10B, 2 Lanes

8-Bit, 8B/10B, 2 Lanes

10-Bit, 8B/10B, 1 Lane

12-Bit, 64B/66B, 1 Lane

8-Bit, 64B/66B, 1 Lanes

0

1

2

3

4

5

4:4:256

16:16:256

32:32:256

128⁽²⁾

8B/10B

64B/66B

12

8

0

12

8

0

2

1

2⁽¹⁾

1

8

2

1

5

2

5

2

1

4

1

0

1

0

1

0

—

3

8

500-800

10

4

10

12

8

10

12

8

4

12.5

16.5

4

128⁽²⁾

4

1

12-Bit, 64B/66B, 2

Lanes

6

128⁽²⁾

64B/66B

12

0

12

0

2

4

2

1

3

8.25

500-800

8-Bit, 64B/66B, 1 Lane

12-Bit, 64B/66B, 1 Lane

8-Bit, 8B/10B, 2 Lanes

10-Bit, 8B/10B, 2 Lanes

12-Bit, 8B/10B, 4 Lanes

8-Bit, 8B/10B, 4 Lanes

10-Bit, 8B/10B, 4 Lanes

7

8

256⁽²⁾

64B/66B

8B/10B

8

12

8

0

8

12

8

0

1

2

4

1

3

1

5

8

1

5

1

2

4

5

4

0

1

8.25

12.375

5

500-800

256⁽²⁾

3

9

32:32:256

4:4:256

4

—

10

11

12

13

10

12

8

10

12

8

2⁽¹⁾

4⁽¹⁾

1

6.25

4

32:32:256

2.5

10

4⁽¹⁾

3.125

12-Bit, 64B/66B, 2

Lanes

14

15

256⁽²⁾

64B/66B

12

0

12

0

2

4

2⁽¹⁾

4⁽¹⁾

3

2

0

2

3

2

6.1875

500-800

12-Bit, 64B/66B, 4

Lanes

3.09375

(1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter

does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the

correct sample data; see mode diagrams for more details.

(2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x

E/F. K is not an actual parameter of the 64B/66B link layer.

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The quad and dual channel devices have a total of 8 high-speed output drivers and the single channel device a

total of 4 high-speed output drivers. The lanes and their derived configuration parameters are described in Table

8-19. For a specified JMODE, the lowest indexed lanes are used and the higher indexed lanes are automatically

powered down. Always route the lowest indexed lanes to the logic device.

Table 8-19. ADC12xJ800 Lane Assignment and Parameters

DEVICE PIN

DESIGNATION

Devices

DID (User Configured)

LID (Derived)

D0±

D1±

D2±

D3±

D4±

D5±

D6±

D7±

All

Set by DID

0

1

2

3

4

5

6

7

All

Quad/Dual only

8.4.2.1 JESD204C Transport Layer Data Formats

The ADC core output samples are formatted in a specific fashion for each JMODE setting based on the transport

layer settings for that JMODE. The following tables show the specific mapping formats for a single frame for

each JMODE. The symbol definitions used in the JMODE tables is provided in Table 8-20. In all mappings the

tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.

Table 8-20. JMODE Table Symbol Definitions

NOTATION

DESCRIPTION

A_n

B_n

C_n

D_n

T

Sample n from channel A

Sample n from channel B

Sample n from channel C

Sample n from channel D

Tail bits, always set to 0

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Table 8-21. JMODE 0 (12-bit, 8/4/2 lanes, 8B/10B)

OCTET

NIBBLE

D0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

A₆

A₇

B₆

B₇

11

12

13

A₈

A₉

B₈

B₉

14

15

T

A₀

A₁

B₀

B₁

A₂

A₃

B₂

B₃

A₄

A₅

B₄

B₅

D1

T

D2

T

D3

T

D4 (Quad

only)

C₀

C₁

D₀

D₁

C₂

C₃

D₂

D₃

C₄

C₅

D₄

D₅

C₆

C₇

D₆

D₇

C₈

C₉

D₈

D₉

T

D5 (Quad

only)

D6 (Quad

only)

D7 (Quad

only)

Table 8-22. JMODE 1 (12-bit, 6/3/2 lanes, 8B/10B)

OCTET

NIBBLE

D0

0

1

0

1

2

3

A₁[11:8]

A₀[11:0]

Dual or Quad: B₀[11:4]

Single: 0x00

D1

A₁[7:0]

C₁[7:0]

D2 (Quad or Dual only)

D3 (Quad only)

B₀[3:0]

D₀[3:0]

B₁[11:0]

C₀[11:0]

C₁[11:8]

D4 (Quad only)

D₀[11:4]

D5 (Quad only)

D₁[11:0]

Table 8-23. JMODE 2 (8-bit, 4/2/1 lanes, 8B/10B)

OCTET

0

NIBBLE

D0

0

1

A₀

B₀

C₀

D₀

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

Table 8-24. JMODE 3 (10-bit, 4/2/1 lanes, 8B/10B)

OCTET

NIBBLE

D0

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

A₀

B₀

A₁

B₁

A₂

B₂

A₃

B₃

D1 (Dual or Quad

only)

D2 (Quad only)

D3 (Quad only)

C₀

D₀

C₁

D₁

C₂

D₂

C₃

D₃

Table 8-25. JMODE 4 (12-bit, 3/2/1lanes, 64B/66B)

OCTET

0

1

NIBBLE

0

1

2

3

Quad or Dual:

B₀[11:8]

D0

A₀[11:0]

Single: 0x0

Quad: C₀[11:4]

Dual: 0x00

D1 (Dual or Quad only)

B₀[7:0]

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Table 8-25. JMODE 4 (12-bit, 3/2/1lanes, 64B/66B) (continued)

OCTET

NIBBLE

0

1

0

1

2

3

D2 (Quad only)

C₀[3:0]

D₀[11:0]

Table 8-26. JMODE 5 (8-bit, 2/1/1 lanes, 64B/66B)

OCTET

NIBBLE

0

1

2

3

Quad or Dual: B₀

Single: 0x00

D0

A₀

C₀

D1 (Quad Only)

D₀

Table 8-27. JMODE 6 (12-bit, 6/3/2 lanes, 64B/66B)

OCTET

NIBBLE

D0

0

1

0

1

2

3

A₁[11:8]

Dual or Quad: B₀[11:4]

A₀[11:0]

D1

A₁[7:0]

C₁[7:0]

Single: 0x00

D2 (Dual or Quad only)

D3 (Quad only)

B₀[3:0]

D₀[3:0]

B₁[11:0]

C₀[11:0]

C₁[11:8]

D4 (Quad only)

D₀[11:4]

D5 (Quad only)

D₁[11:0]

Table 8-28. JMODE 7 (8-bit, 4/2/1 lanes, 64B/66B)

OCTET

0

NIBBLE

0

1

D0

A₀

B₀

C₀

D₀

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

Table 8-29. JMODE 8 (12-bit, 4/2/1 lanes, 64B/66B)

OCTET

NIBBLE

0

1

2

0

1

2

3

4

5

D0

A₀

B₀

C₀

D₀

A₁

B₁

C₁

D₁

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

Table 8-30. JMODE 9 (8-bit, 8/4/2lanes, 8B/10B)

OCTET

NIBBLE

D0

0

1

A₀

A₁

B₀

B₁

C₀

C₁

D₀

D₁

D1

D2 (Dual or Quad only)

D3 (Dual or Quad only)

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

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Table 8-31. JMODE 10 (10-bit, 8/4/2 lanes, 8B/10B)

OCTET

0

1

2

3

4

NIBBLE

D0

0

1

2

3

4

5

6

7

8

9

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

D1

D2 (Dual or Quad

only)

B₀

B₁

B₂

B₃

B₄

B₅

B₆

B₇

D3 (Dual or Quad

only)

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

C₀

C₁

D₀

D₁

C₂

C₃

D₂

D₃

C₄

C₅

D₄

D₅

C₆

C₇

D₆

D₇

Table 8-32. JMODE 11 (12-bit, Dual/Single channel only, 8/4 lanes, 8B/10B)

OCTET

0

1

2

3

4

5

6

7

NIBBLE

D0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

A₀

A₁

A₂

A₃

A₄

A₅

A₆

A₇

A₈

A₁₂

A₁₃

A₁₄

A₁₅

A₁₆

A₁₇

A₁₈

A₁₉

D1

A₉

T

D2

A₁₀

A₁₁

T

D3

T

D4 (Dual

only)

B₀

B₁

B₂

B₃

B₄

B₅

B₆

B₇

B₈

B₉

B₁₂

B₁₃

B₁₄

B₁₅

B₁₆

B₁₇

B₁₈

B₁₉

T

D5 (Dual

only)

D6 (Dual

only)

B₁₀

B₁₁

D7 (Dual

only)

Table 8-33. JMODE 12 (8-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)

OCTET

NIBBLE

D0

0

1

A₀

A₁

A₂

A₃

B₀

B₁

B₂

B₃

D1

D2

D3

D4 (Dual only)

D5 (Dual only)

D6 (Dual only)

D7 (Dual only)

Table 8-34. JMODE 13 (10-bit, Dual/Single channel only, 8/4lanes, 8B/10B)

OCTET

0

1

2

3

4

NIBBLE

0

1

2

3

4

5

6

7

8

9

D0

A₀

A₁

A₂

A₃

B₀

B₁

A₄

A₅

A₆

A₇

B₄

B₅

A₈

A₉

A₁₂

A₁₃

A₁₄

A₁₅

B₁₂

B₁₃

D1

D2

A₁₀

A₁₁

B₈

D3

D4 (Dual only)

D5 (Dual only)

B₉

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Table 8-34. JMODE 13 (10-bit, Dual/Single channel only, 8/4lanes, 8B/10B) (continued)

OCTET

0

1

2

3

4

NIBBLE

0

1

2

3

4

5

6

7

8

9

D6 (Dual only)

D7 (Dual only)

B₂

B₃

B₆

B₇

B₁₀

B₁₁

B₁₄

B₁₅

Table 8-35. JMODE 14 (12-bit, 8/4/2 lanes, 64B/66B)

OCTET

0

1

2

NIBBLE

D0

0

1

2

3

4

5

A₀

A₁

B₀

B₁

C₀

C₁

D₀

D₁

A₂

A₃

B₂

B₃

C₂

C₃

D₂

D₃

D1

D2 (Dual or Quad only)

D3 (Dual or Quad only)

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

Table 8-36. JMODE 15 (12-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)

OCTET

NIBBLE

D0

0

1

2

0

1

2

3

4

5

A₀

A₁

A₂

A₃

B₀

B₁

B₂

B₃

A₄

A₅

A₆

A₇

B₄

B₅

B₆

B₇

D1

D2

D3

D4 (Dual only)

D5 (Dual only)

D6 (Dual only)

D7 (Dual only)

8.4.2.2 64B/66B Sync Header Stream Configuration

The sync header stream can be used to identify bit errors on the link or to correct bit errors. Two modes of

operation are available in ADC12xJ800. Cyclic redundancy checking (CRC) can be used to identify bit errors.

ADC12xJ800 only supports 12-bit CRC (CRC-12) and does not support the optional 3-bit CRC-3 described by

JESD204C. Alternatively, forward error correction (FEC) can be used to identify bit errors and then correct bit

errors. For information on CRC-12, see Cyclic Redundancy Check (CRC Mode). For information on FEC, see

Forward Error Correction (FEC) Mode.

8.4.2.3 Redundant Data Mode (Alternate Lanes)

JMODEs that use four or less lanes allow the use of redundancy on the JESD204C output. For instance, a

system may have two FPGAs or ASICs connected to a single device, if the FPGA or ASIC is deemed the weak

point in system reliability. In this example system, only one FPGA or ASIC operates at a time with the redundant

FPGA or ASIC only being enabled if a fault is detected in the default FPGA or ASIC. To use this mode, the lower

four SerDes lanes (D3-D0) must be routed to a single FPGA or ASIC and the upper four SerDes lanes (D7-D4)

routed to the redundant FPGA or ASIC. The lower four lanes are the "default" lanes and the upper four lanes are

the "alternate" lanes. The desired lanes are chosen by setting ALT_LANES parameter to 0 for the default lanes

or 1 for the alternate lanes. Only one set of SerDes outputs can be operated at a time.

8.4.3 Power-Down Modes

The PD input pin allows the device devices to be entirely powered down. Power-down can also be controlled

by MODE. The serial data output drivers are disabled when PD is high. When the device returns to normal

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operation, the JESD204 link must be re-established and the ADC pipelines contain meaningless information so

the system must wait a sufficient time for the data to be flushed. The register configuration and calibration data

is maintained during power down. A calibration cycle (foreground or background calibration) may be needed to

return to optimal performance if the temperature changes drastically during the duration of power down.

8.4.4 Test Modes

A number of device test modes are available. These modes insert known patterns of information into the device

data path for assistance with system debug, development, or characterization.

8.4.4.1 Serializer Test-Mode Details

Test modes are enabled by setting JTEST to the desired test mode. Each test mode is described in detail in

the following sections. Regardless of the test mode, the serializer outputs (number of lanes, rate) are powered

up based on JMODE. Only enable the test modes when the JESD204C link is disabled. Figure 8-14 provides a

diagram showing the various test mode insertion points.

ADC

JESD204C Block

Active Lanes and

Serial Rates

Set by JMODE

8B/10B or

TRANSPORT

LAYER

SERDES

TX

SCRAMBLER

LINK LAYER

64B/66B

Encoder

ADC

Short Transport Test

Long Transport Test

Octet Ramp

Repeated ILA*

Modified RPAT*

K28.5*

PRBS

Clock Pattern

Serial Outputs High/Low

D21.5

* Applies only to JMODEs using 8B/10B encoding

Figure 8-14. Test Mode Insertion Points

8.4.4.2 PRBS Test Modes

The PRBS test modes bypass the JESD204C transport layer and link layer and are therefore neither scrambled

nor encoded. These test modes produce pseudo-random bit streams that comply with the ITU-T O.150

specification. These bit streams are used with lab test equipment or logic devices that can self-synchronize

to the bit pattern. The initial phase of the pattern is not defined since the receiver self synchronizes.

The sequences are defined by a recursive equation. For example, Equation 12 defines the PRBS7 sequence.

y[n] = y[n – 6]⊕y[n – 7]

(12)

where

bit n is the XOR of bit [n – 6] and bit [n – 7], which are previously transmitted bits

•

Table 8-37 lists equations and sequence lengths for the available PRBS test modes where ⊕ is the XOR

operation and y[n] represents bit n in the PRBS sequence. The initial phase of the pattern is unique for each

lane.

Table 8-37. PBRS Mode Equations

PRBS TEST MODE

PRBS7

SEQUENCE

y[n] = y[n – 6]⊕y[n – 7]

y[n] = y[n – 5]⊕y[n – 9]

y[n] = y[n – 14]⊕y[n – 15]

y[n] = y[n – 18]⊕y[n – 23]

y[n] = y[n – 28]⊕y[n – 31]

SEQUENCE LENGTH (bits)

127

PRBS9

511

PRBS15

PRBS23

PRBS31

32,767

8,388,607

2,147,483,647

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8.4.4.3 Clock Pattern Mode

In the clock pattern mode, the JESD204C transport layer and link layer are bypassed, so the test sequence is

neither scrambled nor encoded. The pattern consists of a 16-bit long sequence of 8 ones and 8 zeros (1111 1111

0000 0000) that repeats indefinitely.

8.4.4.4 Ramp Test Mode

In the ramp test mode, the JESD204C link layer operates normally, but the transport layer is disabled and the

input from the formatter is ignored. In 8B/10B modes, the pattern begins after the ILA sequence finishes. In

64B/66B mode, the pattern begins after the serializers are initialized. Each lane transmits an identical octet

stream that is encoded and scrambled by the link layer. The octet stream increments from 0x00 to 0xFF and

repeats. This mode is available for both 8B/10B and 64B/66B modes.

8.4.4.5 Short and Long Transport Test Mode

JESD204C defines both short and long transport test modes to verify that the transport layers in the transmitter

and receiver are operating correctly. The short transport test pattern used by device is dependent on the JMODE

and are provided in Short Transport Test Pattern. The device does not support long transport test modes.

8.4.4.5.1 Short Transport Test Pattern

Short transport test patterns send a predefined octet format that repeats every frame. The short transport test

patterns for each JMODE are defined in this section.

Table 8-38. Short Transport Test Pattern for JMODE 0

OCTET

NIBBLE

D0

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

0xF01

0xE11

0xF02

0xE12

0xF03

0xE13

0xF04

0xE14

0xF05

0xE15

D1

T

D2 (Dual or

Quad only)

0xD21

0xC31

0xB41

0xA51

0x961

0x871

0xD22

0xC32

0xB42

0xA52

0x962

0x872

0xD23

0xC33

0xB43

0xA53

0x963

0x873

0xD24

0xC34

0xB44

0xA54

0x964

0x874

0xD25

0xC35

0xB45

0xA55

0x965

0x875

T

D3 (Dual or

Quad only)

D4 (Quad

only)

D5 (Quad

only)

D6 (Quad

only)

D7 (Quad

only)

Table 8-39. Short Transport Test Pattern for JMODE 1

OCTET

NIBBLE

D0

0

1

0

1

2

3

0xF01

0xF

D1

0x02

0x22

0xE1

0xC3

D2 (Dual or Quad only)

D3 (Quad only)

0x1

0xE12

0xC32

0xD21

0xD

D4 (Quad only)

D5 (Quad only)

Table 8-40. Short Transport Test Pattern for JMODE 2

OCTET

NIBBLE

D0

0

1

0x01

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Table 8-40. Short Transport Test Pattern for JMODE 2 (continued)

OCTET

0

NIBBLE

0

1

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

0x11

0x21

0x31

Table 8-41. Short Transport Test Pattern for JMODE 3

OCTET

0

1

2

3

4

NIBBLE

0

1

2

3

4

5

6

7

8

0x304

9

D0

0x301

0x302

0x303

D1 (Dual or Quad

only)

0x211

0x212

0x213

0x214

D2 (Quad only)

D3 (Quad only)

0x121

0x031

0x122

0x032

0x123

0x033

0x124

0x034

Table 8-42. Short Transport Test Pattern for JMODE 4

OCTET

0

1

NIBBLE

0

1

2

3

D0

0xF01

0xE

D1 (Dual or Quad only)

D2 (Quad only)

0x11

0xD2

0x1

0xC31

Table 8-43. Short Transport Test Pattern for JMODE 5

OCTET

NIBBLE

0

1

0

1

2

3

D0

0x01

0x21

0x11

0x31

D1 (Quad only)

Table 8-44. Short Transport Test Pattern for JMODE 6

OCTET

NIBBLE

0

1

0

1

2

3

D0

0xF01

0xF

D1

0x02

0x22

0xE1

0xC3

D2 (Dual or Quad only)

D3 (Quad only)

D4 (Quad only)

D5 (Quad only)

0x1

0xE12

0xC32

0xD21

0xD

Table 8-45. Short Transport Test Pattern for JMODE 7

OCTET

0

NIBBLE

0

1

D0

0x01

0x11

0x21

0x31

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

Table 8-46. Short Transport Test Pattern for JMODE 8

OCTET

NIBBLE

D0

0

1

2

0

1

2

3

4

5

0xF01

0xF02

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Table 8-46. Short Transport Test Pattern for JMODE 8 (continued)

OCTET

NIBBLE

0

1

2

0

1

2

3

4

5

D1 (Dual or Quad only)

D2 (Quad only)

D3 (Quad only)

0xE11

0xD21

0xC31

0xE12

0xD22

0xC32

Table 8-47. Short Transport Test Pattern for JMODE 9

OCTET

0

NIBBLE

D0

0

1

0x01

0x02

0x11

0x12

0x21

0x22

0x31

0x32

D1

D2 (Dual or Quad only)

D3 (Dual or Quad only)

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

Table 8-48. Short Transport Test Pattern for JMODE 10

OCTET

NIBBLE

D0

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

0x301

0x302

0x303

0x304

D1

0x211

0x121

0x212

0x122

0x213

0x123

0x214

0x124

D2 (Dual or Quad

only)

D3 (Dual or Quad

only)

0x031

0x032

0x033

0x034

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

0x341

0x251

0x161

0x071

0x342

0x252

0x162

0x072

0x343

0x253

0x163

0x073

0x344

0x254

0x164

0x074

Table 8-49. Short Transport Test Pattern for JMODE 11

OCTET

0

1

2

3

4

5

6

7

NIBBLE

D0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

0xF01

0xE11

0xD21

0xC31

0xF02

0xE12

0xD22

0xC32

0xF03

0xE13

0xD23

0xC33

0xF04

0xE14

0xD24

0xC34

0xF05

0xE15

0xD25

0xC35

D1

T

D2

T

D3

T

D4 (Dual

only)

0xB41

0xA51

0x961

0x871

0xB42

0xA52

0x962

0x872

0xB43

0xA53

0x963

0x873

0xB44

0xA54

0x964

0x874

0xB45

0xA55

0x965

0x875

T

D5 (Dual

only)

D6 (Dual

only)

D7 (Dual

only)

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Table 8-50. Short Transport Test Pattern for JMODE 12

OCTET

NIBBLE

D0

0

1

0x01

0x02

0x03

0x04

0x11

0x12

0x13

0x14

D1

D2

D3

D4 (Dual only)

D5 (Dual only)

D6 (Dual only)

D7 (Dual only)

Table 8-51. Short Transport Test Pattern for JMODE 13

OCTET

0

1

2

3

4

NIBBLE

D0

0

1

2

3

4

5

6

7

8

0x304

9

0x301

0x302

0x303

D1

0x211

0x121

0x031

0x341

0x251

0x161

0x071

0x212

0x122

0x032

0x342

0x252

0x162

0x072

0x213

0x123

0x033

0x343

0x253

0x163

0x073

0x214

0x124

0x034

0x344

0x254

0x164

0x074

D2

D3

D4 (Dual only)

D5 (Dual only)

D6 (Dual only)

D7 (Dual only)

Table 8-52. Short Transport Test Pattern for JMODE 14

OCTET

0

1

2

NIBBLE

D0

0

1

2

3

4

5

0xF01

0xE11

0xD21

0xC31

0xB41

0xA51

0x961

0x871

0xF02

0xE12

0xD22

0xC32

0xB42

0xA52

0x962

0x872

D1

D2 (Dual or Quad only)

D3 (Dual or Quad only)

D4 (Quad only)

D5 (Quad only)

D6 (Quad only)

D7 (Quad only)

Table 8-53. Short Transport Test Pattern for JMODE 15

OCTET

NIBBLE

D0

0

1

2

0

1

2

3

4

5

0xF01

0xE11

0xD21

0xC31

0xB41

0xA51

0x961

0x871

0xF02

0xE12

0xD22

0xC32

0xB42

0xA52

0x962

0x872

D1

D2

D3

D4 (Dual only)

D5 (Dual only)

D6 (Dual only)

D7 (Dual only)

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8.4.4.6 D21.5 Test Mode

In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s). This

mode applies to 8B/10B and 64B/66B modes.

8.4.4.7 K28.5 Test Mode

In this test mode, the controller transmits a continuous stream of K28.5 characters. This mode only applies to

8B/10B modes.

8.4.4.8 Repeated ILA Test Mode

In this test mode, the JESD204C link layer operates normally, except that the ILA sequence (ILAS) repeats

indefinitely instead of starting the data phase. Whenever the receiver issues a synchronization request, the

transmitter initiates code group synchronization. Upon completion of code group synchronization, the transmitter

repeatedly transmits the ILA sequence. This mode only applies to 8B/10B modes.

8.4.4.9 Modified RPAT Test Mode

A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white

spectral content for JESD204C compliance and jitter testing. Table 8-54 lists the pattern before and after 8B/10B

encoding. This mode only applies to 8B/10B modes.

Table 8-54. Modified RPAT Pattern Values

20b OUTPUT OF 8B/10B ENCODER

OCTET NUMBER

Dx.y NOTATION

8-BIT INPUT TO 8B/10B ENCODER

(Two Characters)

0

1

D30.5

D23.6

D3.1

0xBE

0xD7

0x23

0x47

0x6B

0x8F

0xB3

0x14

0x5E

0xFB

0x35

0x59

0x86BA6

2

0xC6475

0xD0E8D

0xCA8B4

0x7949E

0xAA665

3

D7.2

4

D11.3

D15.4

D19.5

D20.0

D30.2

D27.7

D21.1

D25.2

5

6

7

8

9

10

11

8.4.5 Calibration Modes and Trimming

The device has two calibration modes available: foreground calibration and background calibration. When

foreground calibration is initiated the ADCs are taken offline to calibrate and the output data becomes mid-code

(0x000 in 2's complement) until calibration is finished. Background calibration allows the ADC to continue normal

operation while the ADC cores are calibrated in the background by swapping in a different ADC core to take its

place. Additional offset calibration features are available in both foreground and background calibration modes.

Further, a number of ADC parameters can be trimmed to optimize performance in a user system.

The device consists of a total of six ADC cores. In foreground calibration mode ADC 0 samples INA±, ADC 1

samples INB±, ADC 4 samples INC± and ADC 5 samples IND±. In the background calibration modes, ADC core

2 is swapped in periodically for ADC 0 and ADC 1 and ADC core 3 is swapped in periodically for ADC 4 and 5

so that they can be calibrated without disrupting operation. Figure 8-15 through Figure 8-17 provide a diagrams

of the calibration system including labeling of the ADC cores. When calibration is performed the linearity, gain,

and offset voltage for each bank are calibrated to an internally generated calibration signal. The analog inputs

can be driven during calibration, both foreground and background, except that when offset calibration (OS_CAL

or BGOS_CAL) is used there must be no signals (or aliased signals) near DC for proper estimation of the offset

(see the Offset Calibration section).

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INA+

ADC 0

ADC 2

ADC 1

MUX

Channel A Output

INAt

Calibration

Signal

Input

MUX

Calibration

Engine

INB+

MUX

Channel B Output

INBt

Calibration

Engine

Calibration

Engine

INC+

ADC 4

ADC 3

ADC 5

MUX

Channel C Output

INCt

Calibration

Signal

Input

MUX

Calibration

Engine

IND+

MUX

Channel D Output

INDt

Calibration

Engine

Calibration

Engine

Figure 8-15. Quad Channel Calibration System Block Diagram

INA+

ADC 0

MUX

Channel A Output

INAt

Calibration

Signal

Input

MUX

Calibration

Engine

ADC 2

ADC 1

INB+

MUX

Channel B Output

INBt

Calibration

Engine

Calibration

Engine

Figure 8-16. DualChannel Calibration System Block Diagram

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INA+

ADC 0

ADC 2

MUX

Channel A Output

INAt

Calibration

Signal

Input

MUX

Calibration

Engine

Calibration

Engine

Figure 8-17. Single Channel Calibration System Block Diagram

In addition to calibration, a number of ADC parameters are user controllable to provide trimming for optimal

performance. These parameters include input offset voltage, ADC gain and input termination resistance. The

default trim values are programmed at the factory to unique values for each device that are determined to be

optimal at the test system operating conditions. The user can read the factory-programmed values from the trim

registers and adjust as desired. The register fields that control the trimming are labeled according to the input

that is being sampled (INA±, INB±, INC± or IND±) and the ADC core that is being trimmed. The user is not

expected to change the trim values as operating conditions change, however the user can change values as

needed. Any custom trimming must be done on a per device basis because of process variations, meaning that

there is no global optimal setting for all parts. See the Trimming section for information about the available trim

parameters and associated registers.

8.4.5.1 Foreground Calibration Mode

Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.

Foreground calibration always runs on power-up and the user must wait a sufficient time before programming

the device to make sure that the calibration is finished. Foreground calibration can be initiated by triggering the

calibration engine. The trigger source can be either the CALTRIG pin or CAL_SOFT_TRIG and is chosen by

setting CAL_TRIG_EN.

8.4.5.2 Background Calibration Mode

Background calibration mode allows the ADC to continuously operate, with no interruption of data. This

continuous operation is accomplished by activating extra ADC cores that are calibrated to take over operation

for one of the other previously active ADC cores. For the quad channel device, ADC cores 0 and 1 share

one extra ADC core (ADC core 2) and ADC cores 4 and 5 share the other extra ADC core (ADC core 3).

For the dual channel device, ADC cores 0 and 1 share one extra ADC core (ADC core 2). For the single

channel device, ADC core 0 has one extra ADC core (ADC core 2). When an ADC core is taken off-line the

ADC is then calibrated and then can in turn take over to allow the next ADC to be calibrated. This process

operates continuously, ensuring the ADC cores always provide the optimum performance regardless of system

operating condition changes. Only one of the cores is calibrated at a time to reduce power consumption,

however the additional active ADC core does increase the power consumption in comparison to foreground

calibration mode. The low-power background calibration (LPBG) mode discussed in the Low-Power Background

Calibration (LPBG) Mode section provides reduced average power consumption in comparison with the standard

background calibration mode. Background calibration can be enabled by setting CAL_BG. CAL_TRIG_EN must

be set to 0 and CAL_SOFT_TRIG must be set to 1.

Great care has been taken to minimize effects on converted data as the core switching process occurs, however,

small brief glitches may still occur on the converter data as the cores are swapped. It is recommended to set

register ADC_SRC_DLY (address = 0x9A) to 0x1F and MUX_SEL_DLY (address = 0x9B) to 0x1E.

See the Typical Characteristics section for examples of possible glitches in sine-wave and DC signals.

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8.4.5.3 Low-Power Background Calibration (LPBG) Mode

Low-power background calibration (LPBG) mode reduces the power-overhead of enabling additional ADC cores

while still allowing background calibration of the ADC cores to maintain optimal performance as operating

conditions change. LPBG calibration modifies the background calibration procedure by powering down the spare

ADC cores until they are ready to be calibrated. Set LP_EN = 1 to enable the low-power background calibration

feature. Calibration and swapping of ADC cores can be controlled either automatically by the device or manually

by the system by setting LP_TRIG appropriately. Manual control (LP_TRIG=1) allows the system to trigger

calibration in order to limit the number of calibration cycles that occur to avoid unnecessary core swaps or

to keep power consumption at a minimum. For instance, the user may decide to run calibration only when

the system temperature changes by some fixed temperature. If manual control is not necessary the automatic

calibration control can be enabled (LP_TRIG=0) to calibrate at fixed time intervals.

In automatic calibration mode (LP_TRIG=0) the spare ADC core sleep time can be controlled by the

LP_SLEEP_DLY register setting. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before

waking up for calibration (when LP_EN=1 and LP_TRIG = 0). LP_WAKE_DLY sets how long the core is allowed

to stabilize after being awoken before calibration begins. In automatic calibration control mode the freshly

calibrated core is swapped in for an active core as soon as calibration finishes and the new spare core is

powered down for the sleep duration before waking up and calibrating.

Manual calibration control is enabled by setting LP_TRIG high in order to use the calibration trigger

(CAL_SOFT_TRIG or CALTRIG) to trigger calibrations and core swaps. When manual control is enabled

(LP_TRIG=1) the spare ADC is held in sleep mode while the calibration trigger is high. Setting the calibration

trigger low then wakes up the spare ADC core and starts the calibration routine after waiting for the specified

wake delay (LP_WAKE_DLY). The spare ADC core is swapped in for an active core once calibration is complete

and the calibration trigger is set high again. If the calibration trigger is held low, then the spare ADC core

calibrates and powers until the calibration trigger goes high; therefore consuming power. ADC12xJ800 can

report when the spare ADC finishes calibration on the CALSTAT output pin by setting the CALSTAT pin to output

the CAL_STOPPED signal (CAL_STATUS_SEL = 1). For lowest power consumption, set the calibration trigger

high before calibration finishes to allow the spare ADC to swap in for an active ADC core as soon as calibration

finishes. Otherwise, the ADC core swap can be timed manually by setting the calibration trigger high at the

desired time to minimize system impact of potential glitches caused by the swapping procedure.

In LPBG mode there is an increase in power consumption during the ADC core calibration. The longer the

spare ADC is held asleep the lower the average power consumption, however large shifts in operating conditions

during the sleep cycle may cause degraded ADC performance due to non-optimized calibration data for the

active ADC core. The power consumption roughly alternates between the power consumption in foreground

calibration when the spare ADC core is sleeping to the power consumption in background calibration when the

spare ADC is being calibrated. Design the power-supply network to handle the transient power requirements for

this mode, including bulk capacitance after any power supply filtering network to help regulate the supply voltage

during the supply transient.

8.4.6 Offset Calibration

Foreground calibration and background calibration modes inherently calibrate the offsets of the ADC cores;

however, the input buffers sit outside of the calibration loop and therefore their offsets are not calibrated by the

standard calibration process. A separate calibration is provided to correct the input buffer offsets.

There must be no signals at or near DC or aliased signals that fall at or near DC in order to properly calibration

the offsets, requiring the system to specify this condition during normal operation or have the ability to mute

the input signal during calibration. Foreground offset calibration is enabled via CAL_OS and only performs the

calibration one time as part of the foreground calibration procedure. Background offset calibration is enabled

via CAL_BGOS and continues to correct the offset as part of the background calibration routine to account for

operating condition changes. When CAL_BGOS is set, the system must make sure that there are no DC or near

DC signals or aliased signals that fall at or near DC during normal operation. Offset calibration can be performed

as a foreground operation when using background calibration by setting CAL_OS to 1 before setting CAL_EN,

but does not correct for variations as operating conditions change.

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The offset calibration correction uses the input offset voltage trim registers (see OFS0 to OFS5) to correct the

offset and therefore must not be written by the user when offset calibration is used. The user can read the

calibrated values by reading the offset trim registers after calibration is completed and then use these values in

the future to overwrite the factory trim values. Only read the values when FG_DONE is read as 1 when using

foreground offset calibration (CAL_OS = 1) and do not read the values when using background offset calibration

(CAL_BGOS = 1). Setting CAL_OS to 1 and CAL_BG to 1 performs an offset calibration of all six cores during

the foreground calibration process.

Some systems, such as pulsed input systems, may purposefully apply a large external DC offset to the analog

inputs to maximize the dynamic range for uni-polar signals. Standard offset calibration does not work for these

systems because of the applied DC offset. These systems can instead set OSREF to use the spare ADC as the

offset reference and then calibrate the main ADC cores to match the spare offset. This allows seamless offset

transitions during background calibration swapping.

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8.4.7 Trimming

Table 8-55 lists the parameters that can be trimmed and the associated registers.

Table 8-55. Trim Register Descriptions

TRIM PARAMETER

Band-gap reference

TRIM REGISTER

NOTES

BG_TRIM

Measurement on BG output pin.

The device must be powered on with a clock

applied. The registers corresponding to the

unused inputs for dual and single channel

devices the have no affect.

RTRIM_x,

where x = A for INA±, B for INB±, etc.

Input termination resistance

A different trim value is allowed for each

ADC core (0, 1, 2, 3, 4 or 5) to allow more

consistent offset performance in background

calibration mode. Use CAL_OS with CAL_BG

= 1 to get the trim values from these

registers. The registers corresponding to the

unused inputs for dual and single channel

devices the have no affect.

OFSxy,

where x = ADC core (0, 1, 2, 3, 4, or 5)

and y = A for INA±, B for INB±, etc. or

omitted (for ADC cores 0, 1, 4 and 5)

Input offset voltage

Use this trim to match the gain for each

ADC core. These registers are not affected

by the calibration process. The registers

corresponding to the unused inputs for dual

and single channel devices the have no

affect.

GAINxy,

where x = ADC core (0, 1, 2, 3, 4, or 5)

and y = A for INA±, B for INB±, etc. or

omitted (for ADC cores 0, 1, 4 and 5)

Analog input gain

Full-scale input voltage adjustment that

applies to all inputs. Use GAINxy to match

the gain for each input.

Full-scale input voltage

FS_RANGE

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8.5 Programming

8.5.1 Using the Serial Interface

The serial interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data

out (SDO), and serial interface chip-select (SCS). Register access is enabled through the SCS pin.

8.5.2 SCS

This signal must be asserted low to access a register through the serial interface. Setup and hold times with

respect to the SCLK must be observed.

8.5.3 SCLK

Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.

8.5.4 SDI

Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write

(R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are

always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with

respect to the SCLK must be observed (see the Timing Requirements table).

8.5.5 SDO

The SDO signal provides the output data requested by a read command. This output is high impedance during

write bus cycles and during the read bit and register address portion of read bus cycles.

As shown in Serial Interface Protocol: Single Read/Write, each register access consists of 24 bits. The first bit is

high for a read and low for a write.

The next 15 bits are the address of the register that is to be written to. During write operations, the last eight

bits are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored

and, during this time, the SDO outputs the data from the addressed register. Serial Interface Protocol: Single

Read/Write shows the serial protocol details.

Single Register Access

SCS

1

8

16

17

24

SCLK

SDI

Command Field

Data Field

R/W A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1 A0

D7

D6

D5

D4

D3

D2

D1 D0

Data Field

High Z

SDO

(read mode)

D7

D6

D5

D4

D3 D2

D1

D0

Figure 8-18. Serial Interface Protocol: Single Read/Write

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8.5.6 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction

specifics the access type, register address, and data value as normal. Additional clock cycles of write or read

data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The

register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming

transaction. ASCEND controls whether the address value ascends (increments) or descends (decrements).

Streaming mode can be disabled by setting the ADDR_HOLD bit. Figure 8-19 shows the streaming mode

transaction details.

Multiple Register Access

SCS

1

8

16

17

24

25

32

SCLK

SDI

Command Field

Data Field (write mode)

D4 D3 D2 D1

Data Field (write mode)

D5 D4 D3 D2

A1

1

R/W A14 A13 A12

A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D0

D7

D6

D1

D0

Data Field

D4 D3 D2

Data Field

D3 D2

High Z

SDO

(read mode)

D7

D6

D5

D4

D1

D0

D7

D6

D5

D1

D0

Figure 8-19. Serial Interface Protocol: Streaming Read/Write

See the SPI_Register_Map Registers section for detailed information regarding the registers

Note

The serial interface must not be accessed during ADC calibration. Accessing the serial interface

during this time impairs the performance of the device until the device is calibrated correctly. Writing

or reading the serial registers also reduces dynamic ADC performance for the duration of the register

access times.

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8.5.7 SPI_Register_Map Registers

Table 8-56 lists the SPI_Register_Map registers. All register offset addresses not listed in Table 8-56 should be

considered as reserved locations and the register contents should not be modified.

Table 8-56. SPI_REGISTER_MAP Registers

Address

0x0

Acronym

Register Name

Section

CONFIG_A

Configuration A (default: 0x30)

Section 8.5.7.1

Section 8.5.7.2

Section 8.5.7.3

Section 8.5.7.4

Section 8.5.7.5

Section 8.5.7.6

Section 8.5.7.7

Section 8.5.7.8

Section 8.5.7.9

Section 8.5.7.10

Section 8.5.7.11

Section 8.5.7.12

Section 8.5.7.13

Section 8.5.7.14

Section 8.5.7.15

Section 8.5.7.16

Section 8.5.7.17

Section 8.5.7.18

Section 8.5.7.19

Section 8.5.7.20

Section 8.5.7.21

Section 8.5.7.22

Section 8.5.7.23

Section 8.5.7.24

Section 8.5.7.25

Section 8.5.7.26

Section 8.5.7.27

Section 8.5.7.28

Section 8.5.7.29

Section 8.5.7.30

Section 8.5.7.31

Section 8.5.7.32

Section 8.5.7.33

Section 8.5.7.34

Section 8.5.7.35

Section 8.5.7.36

Section 8.5.7.37

Section 8.5.7.38

Section 8.5.7.39

Section 8.5.7.40

Section 8.5.7.41

Section 8.5.7.42

0x2

DEVICE_CONFIG

VENDOR_ID

USR0

Device Configuration (default: 0x00)

0xC

Vendor Identification (Default = 0x0451)

User SPI Configuration (Default: 0x00)

Clock Control 0 (default: 0x80)

0x10

0x29

0x2A

0x2B

0x2C

0x30

0x37

0x3B

0x3C

0x3D

0x3E

0x3F

0x48

0x57

0x58

0x59

0x5C

0x5D

0x5E

0x61

0x62

0x65

0x68

0x6A

0x6B

0x6C

0x6E

0x7A

0x7C

0x7E

0x7F

0x80

0x81

0x9A

0x9B

0x9D

0x160

0x200

0x201

CLK_CTRL0

CLK_CTRL1

CLK_CTRL2

SYSREF_POS

FS_RANGE

LOW_POWER1

TMSTP_CTRL

PLLREFO_CTRL

CPLL_FBDIV1

CPLL_FBDIV2

CPLL_VCOCTRL1

SER_PE

Clock Control 1 (default: 0x00)

Clock Control 2 (default: 0x10)

SYSREF Capture Position (read-only status)

FS_RANGE (default: 0xA000)

Low Power Mode 1 (default: 0x4B)

TIMESTAMP (TMSTP) Control (default: 0x00)

PLL Reference Output Control (default: 0x01)

C-PLL Feedback Divider V and P (default: 0x00)

C-PLL Feedback Divider N (default: 0x20)

C-PLL Feedback Divider N (default: 0x4F)

Serializer Pre-Emphasis Control (default: 0x00)

TRIGOUT Output Control (default: 0x00)

C-PLL Pin Override (default: 0x00)

TRIGOUT_CTRL

CPLL_OVR

VCO_FREQ_TRIM

CPLL_RESET

VCO_CAL_CTRL

VCO_CAL_STATUS

CAL_EN

C-PLL VCO Frequency Trim (default: undefined)

C-PLL / VCO Calibration Reset (default: 0x00)

VCO Calibration Control (default: 0x40)

VCO Calibration Status (read-only) (default: undefined)

Calibration Enable (Default: 0x01)

CAL_CFG0

Calibration Configuration 0 (Default: 0x01)

Calibration Configuration 1 (Default: 0x01)

Calibration Averaging (default: 0x61)

CAL_CFG1

CAL_AVG

CAL_STATUS

CAL_PIN_CFG

CAL_SOFT_TRIG

CAL_LP

Calibration Status (default: undefined) (read-only)

Calibration Pin Configuration (default: 0x00)

Calibration Software Trigger (default: 0x01)

Low-Power Background Calibration (default: 0x88)

Gain DAC Trim (default from Fuse ROM)

Band-Gap Trim (default from Fuse ROM)

Resistor Trim for INA (default from Fuse ROM)

Resistor Trim for INB (default from Fuse ROM)

Resistor Trim for INC (default from Fuse ROM)

Resistor Trim for IND (default from Fuse ROM)

ADC Source Delay for Calibration

GAIN_TRIM

BG_TRIM

RTRIM_A

RTRIM_B

RTRIM_C

RTRIM_D

ADC_SRC_DLY

MUX_SEL_DLY

ADC_DITH

MUX selection Delay for Calibration

ADC Dither Control (default from Fuse ROM)

LSB Control Bit Output (default: 0x00)

JESD204C Subsystem Enable (default: 0x01)

JESD204C Mode (default: 0x00)

LSB_CTRL

JESD_EN

JMODE

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Table 8-56. SPI_REGISTER_MAP Registers (continued)

Address

0x202

0x203

0x204

0x205

0x206

0x207

0x208

0x209

0x20F

0x210

0x211

0x213

0x270

0x29A

0x29B

0x29C

0x2C0

0x2C1

0x2C2

0x2C4

0x330

0x332

0x334

0x336

0x338

0x33A

0x33C

0x33E

0x360

0x361

0x362

0x363

0x364

0x365

0x366

0x367

Acronym

KM1

Register Name

Section

JESD204C K Parameter (minus 1) (default: 0x1F)

JESD204C Manual Sync Request (default: 0x01)

JESD204C Control (default: 0x03)

Section 8.5.7.43

Section 8.5.7.44

Section 8.5.7.45

Section 8.5.7.46

Section 8.5.7.47

Section 8.5.7.48

Section 8.5.7.49

Section 8.5.7.50

Section 8.5.7.51

Section 8.5.7.52

Section 8.5.7.53

Section 8.5.7.54

Section 8.5.7.55

Section 8.5.7.56

Section 8.5.7.57

Section 8.5.7.58

Section 8.5.7.59

Section 8.5.7.60

Section 8.5.7.61

Section 8.5.7.62

Section 8.5.7.63

Section 8.5.7.64

Section 8.5.7.65

Section 8.5.7.66

Section 8.5.7.67

Section 8.5.7.68

Section 8.5.7.69

Section 8.5.7.70

Section 8.5.7.71

Section 8.5.7.72

Section 8.5.7.73

Section 8.5.7.74

Section 8.5.7.75

Section 8.5.7.76

Section 8.5.7.77

Section 8.5.7.78

JSYNC_N

JCTRL

JTEST

JESD204C Test Control (default: 0x00)

DID

JESD204C DID Parameter (default: 0x00)

FCHAR

JESD204C Frame Character (default: 0x00)

JESD204C / System Status Register

JESD_STATUS

CH_EN

JESD204C Channel Enable (default: 0x03)

JESD204C Sync Word Mode (default: 0x00)

JESD204C SYNC~ Threshold (default: 0x03)

Over-range Threshold (default: 0xF2)

SHMODE

SYNC_THRESH

OVR_TH

OVR_CFG

INIT_STATUS

LOW_POWER2

LOW_POWER3

LOW_POWER4

ALARM

Over-range Enable / Hold Off (default: 0x07)

Initialization Status (read-only)

Low Power Mode 2 (default: 0x0F)

Low Power Mode 3 (default: 0x04)

Low Power Mode 4 (default: 0x1B)

Alarm Interrupt (read-only)

ALM_STATUS

ALM_MASK

FIFO_LANE_ALM

OFS0

Alarm Status (default: 0x3F, write to clear)

Alarm Mask Register (default: 0x3F)

FIFO Overflow/Underflow Alarm (default: 0xFF)

Offset Adjustment for ADC0 (default from Fuse ROM)

Offset Adjustment for ADC1 (default from Fuse ROM)

Offset Adjustment for ADC2 (INA±) (default from Fuse ROM)

Offset Adjustment for ADC2 (INB±) (default from Fuse ROM)

Offset Adjustment for ADC3 (INC±) (default from Fuse ROM)

Offset Adjustment for ADC3 (IND±) (default from Fuse ROM)

Offset Adjustment for ADC4 (default from Fuse ROM)

Offset Adjustment for ADC5 (default from Fuse ROM)

Fine Gain Adjust for ADC0 (default from Fuse ROM)

Fine Gain Adjust for ADC1 (default from Fuse ROM)

Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM)

Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM)

Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM)

Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM)

Fine Gain Adjust for ADC4 (default from Fuse ROM)

Fine Gain Adjust for ADC5 (default from Fuse ROM)

OFS1

OFS2A

OFS2B

OFS3C

OFS3D

OFS4

OFS5

GAIN0

GAIN1

GAIN2A

GAIN2B

GAIN3C

GAIN3D

GAIN4

GAIN5

Complex bit access types are encoded to fit into small table cells. Table 8-57 shows the codes that are used for

access types in this section.

Table 8-57. SPI_Register_Map Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

Write

W

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Table 8-57. SPI_Register_Map Access Type Codes

(continued)

Access Type

Code

Reset or Default Value

Value after reset or the default

Description

-n

value

Register Array Variables

i,j,k,l,m,n

When these variables are used in

a register name, an offset, or an

address, they refer to the value of

a register array where the register

is part of a group of repeating

registers. The register groups

form a hierarchical structure and

the array is represented with a

formula.

y

When this variable is used in a

register name, an offset, or an

address it refers to the value of

a register array.

8.5.7.1 CONFIG_A Register (Address = 0x0) [reset = 0x30]

CONFIG_A is shown in Figure 8-20 and described in Table 8-58.

Return to the Table 8-56.

Configuration A (default: 0x30)

Figure 8-20. CONFIG_A Register

7

6

5

4

3

2

1

0

SOFT_RESET

R/W-0x0

RESERVED

R/W-0x0

ASCEND

R/W-0x1

SDO_ACTIVE

R-0x1

RESERVED

R/W-0x0

Table 8-58. CONFIG_A Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SOFT_RESET

R/W

0x0

Setting this bit causes a full reset of the chip and all SPI registers

(including CONFIG_A). This bit is self-clearing. After writing this bit,

the part may take up to 750ns to reset. During this time, do not

perform any SPI transactions.

6

5

RESERVED

ASCEND

R/W

0x0

0x1

Must write default value.

0 : Address is decremented during streaming reads/writes

1 : Address is incremented during streaming reads/writes (default)

4

SDO_ACTIVE

RESERVED

R

0x1

0x0

Always returns 1. Always use SDO for SPI reads.

No SDIO mode supported.

3:0

R/W

8.5.7.2 DEVICE_CONFIG Register (Address = 0x2) [reset = 0x00]

DEVICE_CONFIG is shown in Figure 8-21 and described in Table 8-59.

Return to the Table 8-56.

Device Configuration (default: 0x00)

Figure 8-21. DEVICE_CONFIG Register

7

6

5

4

3

2

1

0

RESERVED

MODE

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Figure 8-21. DEVICE_CONFIG Register (continued)

R/W-0x0

Table 8-59. DEVICE_CONFIG Register Field Descriptions

Bit

7:2

1:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

MODE

Must write default value.

0 : Normal operation (default)

1 : Reserved

2 : Reserved

3 : Power down (full device)

8.5.7.3 VENDOR_ID Register (Address = 0xC) [reset = 0x0]

VENDOR_ID is shown in Figure 8-22 and described in Table 8-60.

Return to the Table 8-56.

Vendor Identification (Default = 0x0451)

Figure 8-22. VENDOR_ID Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

VENDOR_ID

R-0x0

4

3

VENDOR_ID

R-0x0

Table 8-60. VENDOR_ID Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

VENDOR_ID

R

0x0

Always returns 0x0451 (Vendor ID for Texas Instruments)

8.5.7.4 USR0 Register (Address = 0x10) [reset = 0x00]

USR0 is shown in Figure 8-23 and described in Table 8-61.

Return to the Table 8-56.

User SPI Configuration (Default: 0x00)

Figure 8-23. USR0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ADDR_HOLD

R/W-0x0

Table 8-61. USR0 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:1

0

RESERVED

Must write default value.

ADDR_HOLD

0 : Use ASCEND register to select address ascend/descend mode

(default)

1 : Address stays constant throughout streaming operation; useful for

reading and writing calibration vector information at the CAL_DATA

register

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8.5.7.5 CLK_CTRL0 Register (Address = 0x29) [reset = 0x80]

CLK_CTRL0 is shown in Figure 8-24 and described in Table 8-62.

Return to the Table 8-56.

Clock Control 0 (default: 0x80)

Figure 8-24. CLK_CTRL0 Register

7

6

5

4

3

2

1

0

RESERVED

SYSREF_PRO SYSREF_REC SYSREF_ZOO

SYSREF_SEL

R/W-0x0

C_EN

V_EN

M

R/W-0x1

R/W-0x0

Table 8-62. CLK_CTRL0 Register Field Descriptions

Bit

7

Field

Type

Reset

Description

RESERVED

R/W

0x1

Must write default value.

6

SYSREF_PROC_EN

R/W

0x0

This bit enables the SYSREF processor, which allows the device

to process SYSREF events (default: disabled). SYSREF_RECV_EN

must be set before setting SYSREF_PROC_EN.

5

4

SYSREF_RECV_EN

SYSREF_ZOOM

R/W

0x0

Set this bit to enable the SYSREF receiver circuit (default: disabled)

Set this bit to zoom in the SYSREF windowing status and

delays (impacts SYSERF_POS and SYSREF_SEL). When set,

the delays used in the SYSREF windowing feature (reported in

the SYSREF_POS register) become smaller. Use SYSREF_ZOOM

for high clock rates, specifically when multiple SYSREF valid

windows are encountered in the SYSREF_POS register; see

the SYSREF Position Detector and Sampling Position Selection

(SYSREF Windowing) section.

3:0

SYSREF_SEL

R/W

0x0

Set this field to select which SYSREF delay to use. Set this field

based on the results returned by SYSREF_POS; see the SYSREF

Position Detector and Sampling Position Selection (SYSREF

Windowing) section.

8.5.7.6 CLK_CTRL1 Register (Address = 0x2A) [reset = 0x00]

CLK_CTRL1 is shown in Figure 8-25 and described in Table 8-63.

Return to the Table 8-56.

Clock Control 1 (default: 0x00)

Figure 8-25. CLK_CTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

DEVCLK_LVPE SYSREF_LVPE SYSREF_INVE

CL_EN

RTED

R/W-0x0

Table 8-63. CLK_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

2

RESERVED

R/W

0x0

Must write default value.

DEVCLK_LVPECL_EN

R/W

0x0

Activate low voltage PECL mode for DEVCLK. The internal

termination for each input pin (CLK+ and CLK–) becomes a 50-Ω

resistor to ground. There is no input common-mode self-biasing for

CLK± when DEVCLK_LVPECL_EN is set to 1.

1

SYSREF_LVPECL_EN

Activate low voltage PECL mode for SYSREF. The internal

termination for each input pin (SYSREF+ and SYSREF–) becomes a

50-Ω resistor to ground. There is no input common-mode self-biasing

for SYSREF± when SYSREF_LVPECL_EN is set to 1.

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Table 8-63. CLK_CTRL1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

SYSREF_INVERTED

R/W

0x0

This bit inverts the SYSREF signal used for alignment.

8.5.7.7 CLK_CTRL2 Register (Address = 0x2B) [reset = 0x10]

CLK_CTRL2 is shown in Figure 8-26 and described in Table 8-64.

Return to the Table 8-56.

Clock Control 1 (default: 0x10)

Figure 8-26. CLK_CTRL2 Register

7

6

5

4

3

2

1

0

RESERVED

VA11Q_NOISE

SUPPR_EN

RESERVED

VCLK11_NOIS

ESUPPR_EN

R/W-0x1

R/W-0x0

Table 8-64. CLK_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

2

RESERVED

R/W

0x0

Must write default value.

VA11Q_NOISESUPPR_E

N

R/W

0x0

When set, noise on VA11Q is suppressed while drawing ~ 20mA

of current. This will reduce sampling jitter and reduce the reference

clock spur in C-PLL modes and SYSREF spurs.

1

0

RESERVED

R/W

0x0

Must write default value.

VCLK11_NOISESUPPR_

EN

When set, noise on VCLK11 is suppressed while drawing ~ 20mA

of current. This will reduce sampling jitter and reduce the reference

clock spur in C-PLL modes and SYSREF spurs.

8.5.7.8 SYSREF_POS Register (Address = 0x2C) [reset = 0x0]

SYSREF_POS is shown in Figure 8-27 and described in Table 8-65.

Return to the Table 8-56.

SYSREF Capture Position (read-only status)

Figure 8-27. SYSREF_POS Register

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

9

16

8

SYSREF_POS

R-0x0

SYSREF_POS

R-0x0

1

0

SYSREF_POS

R-0x0

Table 8-65. SYSREF_POS Register Field Descriptions

Bit

23:0

Field

Type

Reset

Description

SYSREF_POS

R

0x0

Returns a 24-bit status value that indicates the position of

the SYSREF edge with respect to CLK±. Use this to program

SYSREF_SEL.

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8.5.7.9 FS_RANGE Register (Address = 0x30) [reset = 0xA000]

FS_RANGE is shown in Figure 8-28 and described in Table 8-66.

Return to the Table 8-56.

FS_RANGE (default: 0xA000)

Figure 8-28. FS_RANGE Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

FS_RANGE

R/W-0xA000

4

3

FS_RANGE

R/W-0xA000

Table 8-66. FS_RANGE Register Field Descriptions

Bit

15:0

Field

Type

Reset

Description

FS_RANGE

R/W

0xA000

These bits enable adjustment of the analog full-scale range for all

channels.

0x0000: Settings below 0x2000 result in degraded performance

0x2000: 500 mVPP - Recommended minimum setting

0xA000: 800 mVPP (default)

0xFFFF: 1000 mVPP - Maximum setting, highest SNR

8.5.7.10 LOW_POWER1 Register (Address = 0x37) [reset = 0x4B]

LOW_POWER1 is shown in Figure 8-29 and described in Table 8-67.

Return to the Table 8-56.

Low Power Mode 1 (default: 0x4B)

Figure 8-29. LOW_POWER1 Register

7

6

5

4

3

2

1

0

LOW_POW_MODE1

R/W-0x4B

Table 8-67. LOW_POWER1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

LOW_POW_MODE1

R/W

0x4B

Set this register along with LOW_POWER2, LOW_POWER3 and

LOW_POWER4 to enable Low Power Mode. All registers must

be set together. Calibration must be performed after changing the

operating mode:

0x46 : Low Power Mode

0x4B : High Performance Mode (default)

All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this

register.

8.5.7.11 TMSTP_CTRL Register (Address = 0x3B) [reset = 0x00]

TMSTP_CTRL is shown in Figure 8-30 and described in Table 8-68.

Return to the Table 8-56.

TIMESTAMP (TMSTP) Control (default: 0x00)

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Figure 8-30. TMSTP_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

TMSTP_LVPEC TMSTP_RECV

L_EN

_EN

R/W-0x0

Table 8-68. TMSTP_CTRL Register Field Descriptions

Bit

7:2

1

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

TMSTP_LVPECL_EN

R/W

0x0

When set, activates the low voltage PECL mode for the differential

TMSTP± input. The internal termination for each input pin (TMSTP+

and TMSTP–) becomes a 50-Ω resistor to ground. There is no input

common-mode self-biasing for TMSTP± when TMSTP_LVPECL_EN

is set to 1.

0

TMSTP_RECV_EN

Enables the differential differential TMSTP± input.

8.5.7.12 PLLREFO_CTRL Register (Address = 0x3C) [reset = 0x01]

PLLREFO_CTRL is shown in Figure 8-31 and described in Table 8-69.

Return to the Table 8-56.

PLL Reference Output Control (default: 0x01)

Figure 8-31. PLLREFO_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PLLREFO_EN

R/W-0x1

Table 8-69. PLLREFO_CTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x1

Description

7:1

0

RESERVED

Must write default value.

PLLREFO_EN

When set the reference clock output (PLLREFO±) is enabled

whenever the PLL is enabled (PLL_EN=1). This bit defaults to 1 to

cause PLLREFO± to enable automatically without SPI writes since

PLLREFO± may be used to derive the SPI clock.

8.5.7.13 CPLL_FBDIV1 Register (Address = 0x3D) [reset = 0x00]

CPLL_FBDIV1 is shown in Figure 8-32 and described in Table 8-70.

Return to the Table 8-56.

C-PLL Feedback Divider V and P (default: 0x00)

Figure 8-32. CPLL_FBDIV1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PLL_P_DIV

R/W-0x0

PLL_V_DIV

R/W-0x0

Table 8-70. CPLL_FBDIV1 Register Field Descriptions

Bit

7:4

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

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Table 8-70. CPLL_FBDIV1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3:2

PLL_P_DIV

PLL_V_DIV

R/W

0x0

Controls the second feedback divider of C-PLL. The output of this

divider is the sampling clock. Set CPLL_RESET=1 before changing

PLL_P_DIV.

0 : divide-by-1 (default)

1 : divide-by-2

2 : divide-by-4

3 : RESERVED

1:0

R/W

0x0

Controls the first feedback divider of C-PLL. The output of this

divider feeds the P divider. Set CPLL_RESET=1 before changing

PLL_V_DIV.

0 : divide-by-5 (default)

1 : divide-by-4

2 : divide-by-3

3 : RESERVED

8.5.7.14 CPLL_FBDIV2 Register (Address = 0x3E) [reset = 0x20]

CPLL_FBDIV2 is shown in Figure 8-33 and described in Table 8-71.

Return to the Table 8-56.

C-PLL Feedback Divider N (default: 0x20)

Figure 8-33. CPLL_FBDIV2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

PLL_N_DIV

R/W-0x20

Table 8-71. CPLL_FBDIV2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x20

Description

7:6

5:0

RESERVED

PLL_N_DIV

Must write default value.

Controls the third feedback divider of C-PLL (default is divide-

by-32). This divider divides the sampling clock to generate the PFD

feedback clock. The value of PLL_N_DIV is the divider value. Values

from 1 to 63 are supported. Set CPLL_RESET=1 before changing

PLL_N_DIV.

8.5.7.15 CPLL_VCOCTRL1 Register (Address = 0x3F) [reset = 0x4F, recommended 0x4A]

CPLL_VCOCTRL1 is shown in Figure 8-34 and described in Table 8-72.

Return to the Table 8-56.

C-PLL Feedback Divider N (default: 0x4F)

Figure 8-34. CPLL_VCOCTRL1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

VCO_BIAS

R/W-0x4F

Table 8-72. CPLL_VCOCTRL1 Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

0x0

0x4F

Description

RESERVED

VCO_BIAS

Must write default value.

6:0

Sets the bias levels for the C-PLL VCO. Write 0x4A to this field when

using the C-PLL. Do not use the default value of 0x4F.

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8.5.7.16 SER_PE Register (Address = 0x48) [reset = 0x00]

SER_PE is shown in Figure 8-35 and described in Table 8-73.

Return to the Table 8-56.

Serializer Pre-Emphasis Control (default: 0x00)

Figure 8-35. SER_PE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SER_PE

R/W-0x0

Table 8-73. SER_PE Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:4

3:0

RESERVED

SER_PE

Must write default value.

Sets the pre-emphasis for the SerDes output lanes. Pre-emphasis

can be used to compensate for the high-frequency loss of the PCB

trace. This is a global setting that affects all lanes (D[7:0]±).

8.5.7.17 TRIGOUT_CTRL Register (Address = 0x57) [reset = 0x00]

TRIGOUT_CTRL is shown in Figure 8-36 and described in Table 8-74.

Return to the Table 8-56.

TRIGOUT Output Control (default: 0x00)

Figure 8-36. TRIGOUT_CTRL Register

7

6

5

4

3

2

1

0

TRIGOUT_EN

R/W-0x0

RESERVED

R/W-0x0

TRIGOUT

R/W-0x0

Table 8-74. TRIGOUT_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

TRIGOUT_EN

R/W

0x0

0 : TRIGOUT± output buffer/divider is disabled.

1 : TRIGOUT± output buffer/divider is enabled.

The RXCLK output can be used to provide a reference clock for the

JESD204C receiver. Use the TRIGOUT_MODE field to adjust the

output mode.

6:3

2:0

RESERVED

TRIGOUT

R/W

0x0

Must write default value.

Set the mode for the TRIGOUT± output.

0 : 16 UI clock (RX_DIV = 16)

1 : 32 UI clock (RX_DIV = 32)

2 : 64 UI clock (RX_DIV = 64)

3 : Resampled timestamp from TMSTP±

4-7 : RESERVED

Note 1: Only change TRIGOUT_MODE when TRIGOUT_EN=0.

Note 2: When TRIGOUT_MODE is 2 or less, TRIGOUT± is derived

from the SerDes block. As a result, the TRIGOUT± output is briefly

disrupted any time the serializer is re-initialized.

8.5.7.18 CPLL_OVR Register (Address = 0x58) [reset = 0x00]

CPLL_OVR is shown in Figure 8-37 and described in Table 8-75.

Return to the Table 8-56.

C-PLL Pin Override (default: 0x00)

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Figure 8-37. CPLL_OVR Register

7

6

5

4

3

2

1

0

CPLL_OVR_EN RESERVED

DIVREF_D_MODE

R/W-0x0

DIVREF_C_MODE

R/W-0x0

CPLLREF_SE_ CPLL_EN_OVR

OVR_VALUE

_VALUE

R/W-0x0

Table 8-75. CPLL_OVR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

CPLL_OVR_EN

R/W

0x0

Set this bit to ignore the C-PLL configuration pins and use SPI

registers instead.

0 : Pin Mode : The C-PLL is controlled by chip pins (PLL_EN,

PLLREF_SE, CLKCFG0, CLKCFG1)

1 : SPI Mode : The C-PLL is controlled by SPI

registers (CPLLREF_SE_OVR_VALUE, CPLL_EN_OVR_VALUE,

DIVREF_C_MODE, DIVREF_D_MODE)

6

RESERVED

R/W

0x0

Must write default value.

5:4

DIVREF_D_MODE

When CPLL_OVR_EN=1, this field sets the ORD output function.

When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and

CLKCFG1 controls ORD functionality).

0 : Divided reference output is disabled.

1 : Output C-PLL reference clock divided by 1 on ORD.

2 : Output C-PLL reference clock divided by 2 on ORD.

3 : Output C-PLL reference clock divided by 4 on ORD.

**Important Note: ORD cannot produce a clock unless ORC is also

producing a clock).

3:2

DIVREF_C_MODE

R/W

0x0

When CPLL_OVR_EN=1, this field sets the ORC output function.

When CPLL_OVR_EN=0, this field has no effect (CLKCFG0 and

CLKCFG1 controls ORC functionality).

0 : Divided reference output is disabled.

1 : Output C-PLL reference clock divided by 1 on ORC.

2 : Output C-PLL reference clock divided by 2 on ORC.

3 : Output C-PLL reference clock divided by 4 on ORC.

1

0

CPLLREF_SE_OVR_VAL

UE

R/W

0x0

When CPLL_OVR_EN=1, this bit enables the single-ended C-PLL

reference clock input (SE_CLK) when set to 1 instead of the

PLLREF_SE pin.

CPLL_EN_OVR_VALUE

When CPLL_OVR_EN=1, this bit enables the C-PLL when set to 1

instead of the PLL_EN pin.

8.5.7.19 VCO_FREQ_TRIM Register (Address = 0x59) [reset = 0x0]

VCO_FREQ_TRIM is shown in Figure 8-38 and described in Table 8-76.

Return to the Table 8-56.

C-PLL VCO Frequency Trim (default: undefined)

Figure 8-38. VCO_FREQ_TRIM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

VCO_FREQ_TRIM

R/W-0x0

Table 8-76. VCO_FREQ_TRIM Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0x0

Must write default value.

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Table 8-76. VCO_FREQ_TRIM Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6:0

VCO_FREQ_TRIM

R/W

0x0

Trims C-PLL VCO frequency. This field can be automatically set

by the VCO calibration routine (see VCO_CAL_EN). After VCO

calibration has been run the value can be read from this field and

reprogrammed after future power-up cycles.

If VCO calibration is running (VCO_CAL_EN=1 and

VCO_CAL_DONE=0), you should not read or write this register since

it will interfere with the calibration process.

8.5.7.20 CPLL_RESET Register (Address = 0x5C) [reset = 0x00]

CPLL_RESET is shown in Figure 8-39 and described in Table 8-77.

Return to the Table 8-56.

C-PLL / VCO Calibration Reset (default: 0x00)

Figure 8-39. CPLL_RESET Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CPLL_RESET

R/W-0x0

Table 8-77. CPLL_RESET Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:1

0

RESERVED

Must write default value.

CPLL_RESET

C-PLL / VCO calibration reset. Program CPLL_RESET=1 before

programming the C-PLL (PLL_P_DIV, PLL_V_DIV, PLL_N_DIV,

VCO_BIAS or VCO_CAL_CTRL). Program CPLL_RESET=0 after

programming is completed.

8.5.7.21 VCO_CAL_CTRL Register (Address = 0x5D) [reset = 0x40]

VCO_CAL_CTRL is shown in Figure 8-40 and described in Table 8-78.

Return to the Table 8-56.

VCO Calibration Control (default: 0x40)

Figure 8-40. VCO_CAL_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

VCO_CAL_STL

R/W-0x4

RESERVED

R/W-0x0

VCO_CAL_EN

R/W-0x0

Table 8-78. VCO_CAL_CTRL Register Field Descriptions

Bit

7

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

6:4

VCO_CAL_STL

R/W

0x4

0x0

Program this field to adjust the settling time that the VCO calibration

engine gives to the C-PLL each time it changes the VCO frequency

trim (VCO_FREQ_TRIM). Larger numbers result in longer settling

times.

3:1

RESERVED

Must write default value.

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Table 8-78. VCO_CAL_CTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

VCO_CAL_EN

R/W

0x0

Set this bit to enable the VCO calibration engine. The calibration

commences once CPLL_RESET is programmed to 0. The calibration

will automatically tune VCO_FREQ_TRIM to center the VCO

frequency based on the reference frequency and PLL configuration.

Note: The VCO_CAL_CTRL register should only be changed when

CPLL_RESET=1.

8.5.7.22 VCO_CAL_STATUS Register (Address = 0x5E) [reset = 0x0]

VCO_CAL_STATUS is shown in Figure 8-41 and described in Table 8-79.

Return to the Table 8-56.

VCO Calibration Status (read-only) (default: undefined)

Figure 8-41. VCO_CAL_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

VCO_CAL_DO

NE

R-0x0

Table 8-79. VCO_CAL_STATUS Register Field Descriptions

Bit

Field

Type

Reset

0x0

Description

7:1

0

RESERVED

R

VCO_CAL_DONE

This bit returns ‘1’ once the VCO calibration engine has completed

calibration (or calibration was skipped because VCO_CAL_EN=0).

Once the calibration is completed, you can safely read or write the

VCO_FREQ_TRIM register (never write VCO_FREQ_TRIM during

calibration).

8.5.7.23 CAL_EN Register (Address = 0x61) [reset = 0x01]

CAL_EN is shown in Figure 8-42 and described in Table 8-80.

Return to the Table 8-56.

Calibration Enable (Default: 0x01)

Figure 8-42. CAL_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_EN

R/W-0x1

Table 8-80. CAL_EN Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x1

Description

7:1

0

RESERVED

CAL_EN

Must write default value.

Calibration Enable. Set high to run calibration. Set low to hold

calibration in reset to program new calibration settings. Clearing

CAL_EN also resets the clock dividers that clock the digital block

and JESD204C interface.

Some calibration registers require clearing CAL_EN before making

any changes. All registers with this requirement contain a note in

their descriptions. After changing the registers, set CAL_EN to re-run

calibration with the new settings. Always set CAL_EN before setting

JESD_EN. Always clear JESD_EN before clearing CAL_EN.

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8.5.7.24 CAL_CFG0 Register (Address = 0x62) [reset = 0x01]

CAL_CFG0 is shown in Figure 8-43 and described in Table 8-81.

Return to the Table 8-56.

Calibration Configuration 0 (Default: 0x01)

Figure 8-43. CAL_CFG0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_BGOS

R/W-0x0

CAL_OS

R/W-0x0

CAL_BG

R/W-0x0

CAL_FG

R/W-0x1

Table 8-81. CAL_CFG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

CAL_BGOS

R/W

0x0

Must write default value.

R/W

0x0

0 : Disable background offset calibration (default)

1 : Enable background offset calibration (requires CAL_BG to be

set).

2

1

0

CAL_OS

CAL_BG

CAL_FG

R/W

0x0

0x1

0 : Disable foreground offset calibration (default)

1 : Enable foreground offset calibration (requires CAL_FG to be set).

0 : Disable background calibration (default)

1 : Enable background calibration

0 : Reset calibration values, skip foreground calibration.

1 : Reset calibration values, then run foreground calibration (default).

8.5.7.25 CAL_CFG1 Register (Address = 0x65) [reset = 0x01]

CAL_CFG1 is shown in Figure 8-44 and described in Table 8-82.

Return to the Table 8-56.

Calibration Configuration 1 (Default: 0x01)

Figure 8-44. CAL_CFG1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OSREF

R/W-0x0

RESERVED

R/W-0x1

Table 8-82. CAL_CFG1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:3

2

RESERVED

OSREF

Must write default value.

Defines which reference is used for offset calibration:

0 : Use mid-code as the reference (calibrate to zero-offset). The

analog input signal must have no offset during offset calibration

(typically true if AC-coupled).

1 : Use the spare ADC output samples as the reference (calibrates

primary ADC offsets to match the spare ADC that stands in for

them). The analog input signal can have an offset (e.g. DC-coupled).

Only use this mode when CAL_BG=1. Setting OSREF=1 while

CAL_BG=0 will produce undefined results.

1:0

RESERVED

R/W

0x1

Must write default value.

8.5.7.26 CAL_AVG Register (Address = 0x68) [reset = 0x61]

CAL_AVG is shown in Figure 8-45 and described in Table 8-83.

Return to the Table 8-56.

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Calibration Averaging (default: 0x61)

Figure 8-45. CAL_AVG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OS_AVG

R/W-0x6

RESERVED

R/W-0x0

CAL_AVG

R/W-0x1

Table 8-83. CAL_AVG Register Field Descriptions

Bit

7

Field

Type

Reset

Description

RESERVED

OS_AVG

R/W

0x0

Must write default value.

6:4

R/W

0x6

Select the amount of averaging used for the offset correction routine.

A larger number corresponds to more averaging.

3

RESERVED

CAL_AVG

R/W

0x0

0x1

Must write default value.

2:0

Select the amount of averaging used for the linearity calibration

routine. A larger number corresponds to more averaging.

8.5.7.27 CAL_STATUS Register (Address = 0x6A) [reset = 0x0]

CAL_STATUS is shown in Figure 8-46 and described in Table 8-84.

Return to the Table 8-56.

Calibration Status (default: undefined) (read-only)

Figure 8-46. CAL_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

CAL_STAT

CAL_STOPPE

D

FG_DONE

R-0x0

Table 8-84. CAL_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4:2

1

RESERVED

CAL_STAT

R

0x0

Calibration status code

CAL_STOPPED

This bit returns a 1 when background calibration is successfully

stopped at the requested phase. This bit returns a 0 when calibration

starts operating again. If background calibration is disabled, this bit is

set when foreground calibration is completed or skipped.

0

FG_DONE

R

0x0

This bit is high to indicate that foreground calibration has completed

(or was skipped).

8.5.7.28 CAL_PIN_CFG Register (Address = 0x6B) [reset = 0x00]

CAL_PIN_CFG is shown in Figure 8-47 and described in Table 8-85.

Return to the Table 8-56.

Calibration Pin Configuration (default: 0x00)

Figure 8-47. CAL_PIN_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

CAL_STATUS_SEL

R/W-0x0

CAL_TRIG_EN

R/W-0x0

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Table 8-85. CAL_PIN_CFG Register Field Descriptions

Bit

7:3

2:1

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

CAL_STATUS_SEL

R/W

0x0

0 : CALSTAT output matches FG_DONE.

1 : CALSTAT output matches CAL_STOPPED.

2 : CALSTAT output matches ALARM.

3 : CALSTAT output is always low.

0

CAL_TRIG_EN

This bit selects the hardware or software trigger source.

0 : Use the CAL_SOFT_TRIG register for the calibration trigger. The

CALTRIG input is disabled (ignored).

1 : Use the CALTRIG input for the calibration trigger. The

CAL_SOFT_TRIG register is ignored.

8.5.7.29 CAL_SOFT_TRIG Register (Address = 0x6C) [reset = 0x01]

CAL_SOFT_TRIG is shown in Figure 8-48 and described in Table 8-86.

Return to the Table 8-56.

Calibration Software Trigger (default: 0x01)

Figure 8-48. CAL_SOFT_TRIG Register

7

6

5

4

3

2

1

0

RESERVED

CAL_SOFT_TR

IG

R/W-0x0

R/W-0x1

Table 8-86. CAL_SOFT_TRIG Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x1

Description

7:1

0

RESERVED

Must write default value.

CAL_SOFT_TRIG

CAL_SOFT_TRIG is a software bit to provide the functionality of the

CALTRIG input pin when there are no hardware resources to drive

CALTRIG. Program CAL_TRIG_EN=0 to use CAL_SOFT_TRIG for

the calibration trigger.

Note: If no calibration trigger is needed, leave CAL_TRIG_EN=0 and

CAL_SOFT_TRIG=1 (trigger set high).

8.5.7.30 CAL_LP Register (Address = 0x6E) [reset = 0x88]

CAL_LP is shown in Figure 8-49 and described in Table 8-87.

Return to the Table 8-56.

Low-Power Background Calibration (default: 0x88)

Figure 8-49. CAL_LP Register

7

6

5

4

3

2

1

0

LP_SLEEP_DLY

R/W-0x4

LP_WAKE_DLY

R/W-0x1

RESERVED

R/W-0x0

LP_TRIG

R/W-0x0

LP_EN

R/W-0x0

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Table 8-87. CAL_LP Register Field Descriptions

Bit

Field

LP_SLEEP_DLY

Type

Reset

Description

7:5

R/W

0x4

These bits adjust how long an ADC sleeps before waking for

calibration (only applies when LP_EN = 1 and LP_TRIG = 0). Values

below 4 are not recommended because of limited overall power

reduction benefits.

0: Sleep delay = 1,152 × tCLK

1: Sleep delay = 4,194,432 × tCLK

2: Sleep delay = 33,554,560 × tCLK

3: Sleep delay = 268,435,584 × tCLK

4: Sleep delay = 2,147,483,776 × tCLK (default, approximately 2.15

seconds with a 1.0-GHz clock)

5: Sleep delay = 17,179,869,312× tCLK

6: Sleep delay = 137,438,953,600 × tCLK

7: Sleep delay = 1,099,511,627,904 × tCLK

4:3

LP_WAKE_DLY

R/W

0x1

These bits adjust how much time is provided for settling before

calibrating an ADC after the ADC wakes up (only applies when

LP_EN = 1). Values lower than 1 are not recommended because

there is insufficient time for the core to stabilize before calibration

begins.

0: Wake delay = 1,152 × tCLK

1: Wake delay = 33,554,560 × tCLK (default, approximately 34 ms

with a 1.0-GHz clock)

2: Wake delay = 268,435,584 × tCLK

3: Wake delay = 2,147,483,776 × tCLK

2

1

RESERVED

LP_TRIG

R/W

0x0

Must write default value.

0 : ADC sleep duration is set by LP_SLEEP_DLY (autonomous

mode).

1 : ADCs sleep until awoken by a trigger. An ADC is awoken when

the calibration trigger is low. The offline ADC is sleeping when the

calibration trigger is high.

0

LP_EN

R/W

0x0

0 : Disable low-power background calibration (default)

1 : Enable low-power background calibration (only applies when

CAL_BG=1).

8.5.7.31 GAIN_TRIM Register (Address = 0x7A) [reset = 0x0]

GAIN_TRIM is shown in Figure 8-50 and described in Table 8-88.

Return to the Table 8-56.

Gain DAC Trim (default from Fuse ROM)

Figure 8-50. GAIN_TRIM Register

7

6

5

4

3

2

1

0

GAIN_TRIM

R/W-0x0

Table 8-88. GAIN_TRIM Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

GAIN_TRIM

R/W

0x0

This register trims the gain of all ADC cores. FS_RANGE should be

used for full-scale range adjustment instead of GAIN_TRIM.

8.5.7.32 BG_TRIM Register (Address = 0x7C) [reset = 0x0]

BG_TRIM is shown in Figure 8-51 and described in Table 8-89.

Return to the Table 8-56.

Band-Gap Trim (default from Fuse ROM)

110

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Figure 8-51. BG_TRIM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

BG_TRIM

R/W-0x0

Table 8-89. BG_TRIM Register Field Descriptions

Bit

7:4

3:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

BG_TRIM

Must write default value.

This register enables trimming of the internal band-gap reference.

After reset, the factory trimmed value can be read and adjusted as

required.

8.5.7.33 RTRIM_A Register (Address = 0x7E) [reset = 0x0]

RTRIM_A is shown in Figure 8-52 and described in Table 8-90.

Return to the Table 8-56.

Resistor Trim for INA (default from Fuse ROM)

Figure 8-52. RTRIM_A Register

7

6

5

4

3

2

1

0

RTRIM_A

R/W-0x0

Table 8-90. RTRIM_A Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

RTRIM_A

R/W

0x0

This register controls the INA± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

8.5.7.34 RTRIM_B Register (Address = 0x7F) [reset = 0x0]

RTRIM_B is shown in Figure 8-53 and described in Table 8-91.

Return to the Table 8-56.

Resistor Trim for INB (default from Fuse ROM)

Figure 8-53. RTRIM_B Register

7

6

5

4

3

2

1

0

RTRIM_B

R/W-0x0

Table 8-91. RTRIM_B Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

RTRIM_B

R/W

0x0

This register controls the INB± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

8.5.7.35 RTRIM_C Register (Address = 0x80) [reset = 0x0]

RTRIM_C is shown in Figure 8-54 and described in Table 8-92.

Return to the Table 8-56.

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Resistor Trim for INC (default from Fuse ROM)

Figure 8-54. RTRIM_C Register

7

6

5

4

3

2

1

0

RTRIM_C

R/W-0x0

Table 8-92. RTRIM_C Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

RTRIM_C

R/W

0x0

This register controls the INC± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

8.5.7.36 RTRIM_D Register (Address = 0x81) [reset = 0x0]

RTRIM_D is shown in Figure 8-55 and described in Table 8-93.

Return to the Table 8-56.

Resistor Trim for IND (default from Fuse ROM)

Figure 8-55. RTRIM_D Register

7

6

5

4

3

2

1

0

RTRIM_D

R/W-0x0

Table 8-93. RTRIM_D Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

RTRIM_D

R/W

0x0

This register controls the IND± ADC input termination trim. After

reset, the factory trimmed value can be read and adjusted as

required.

8.5.7.37 ADC Source Control Delay (Address = 0x9A) [reset = 0x08]

ADC_SRC_DLY is shown in AC_SRC_DLY Register and described in ADC_SRC_DLY Register Field

Descriptions. Only change this register while CAL_EN is 0.

Return to the Table 8-56.

ADC Dither Control (default from Fuse ROM)

Figure 8-56. ADC_SRC_DLY Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

R/W-0x08

Table 8-94. ADC_SRC_DLY Register Field Descriptions

Bit

7:5

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

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Table 8-94. ADC_SRC_DLY Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4:0

ADC_SRC_DLY

R/W

0x08

Adjusts how long two ADCs will sample the same input at the same

clock phase during background ADC swaps.

The default value is appropriate for all ADCCLK frequencies. If using

a reduced ADCCLK frequency, ADC_SRC_DLY can be set to 7

to reduce the glitch duration during fast background ADC swaps,

however there is a greater risk of having a large glitch amplitude.

Two ADCs will sample the same input for 4+2*ADC_SRC_DLY

ADCCLK cycles.

ADC_SRC_DLY can be programmed from 0 to 31.

8.5.7.38 MUX Select Delay Register (Address = 0x9B) [reset = 0x07]

MUX_SEL_DLY is shown in MUX_SEL_DLY Register and described in MUX_SEL_DLY Register Field

Descriptions.

Return to the Table 8-56.

Figure 8-57. MUX_SEL_DLY Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MUX_SEL_DLY

R/W-0x07

Table 8-95. MUX_SEL_DLY Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x07

Description

7:5

4:0

RESERVED

Must write default value.

MUX_SEL_DLY

Adjusts the delay added to the internal mux selection signal. This

signal controls multiplexors that steer ADC core output data into the

encoders. This delay only applies during background ADC swaps.

This delay needs to be tuned to swap between sample streams

during a small window of time when both sample streams are valid.

MUX_SEL_DLY can be programmed from 0 to 31.

8.5.7.39 ADC_DITH Register (Address = 0x9D) [reset = 0x0]

ADC_DITH is shown in Figure 8-58 and described in Table 8-96.

Return to the Table 8-56.

ADC Dither Control (default from Fuse ROM)

Figure 8-58. ADC_DITH Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ADC_DITH_ER ADC_DITH_AM ADC_DITH_EN

R

P

R/W-0x0

Table 8-96. ADC_DITH Register Field Descriptions

Bit

7:3

Field

Type

Reset

Description

RESERVED

R/W

0x0

Must write default value.

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Table 8-96. ADC_DITH Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

ADC_DITH_ERR

R/W

0x0

Small rounding errors may occur when subtracting the dither signal.

The error can be chosen to either slightly degrade SNR or to slightly

increase the DC offset and FS/2 spur. In addition, the FS/4 spur will

also be increased slightly while in single channel mode.

0 : Rounding error degrades SNR

1 : Rounding error degrades DC offset, FS/2 spur and FS/4 spur

1

0

ADC_DITH_AMP

ADC_DITH_EN

R/W

0x0

0 : Small dither for better SNR (default)

1 : Large dither for better spurious performance

Set this bit to enable ADC dither. Dither can improve spurious

performance at the expense of slightly degraded SNR. The dither

amplitude (ADC_DITH_AMP) can be used to further tradeoff SNR

and spurious performance.

8.5.7.40 LSB_CTRL Register (Address = 0x160) [reset = 0x00]

LSB_CTRL is shown in Figure 8-59 and described in Table 8-97.

Return to the Table 8-56.

LSB Control Bit Output (default: 0x00)

Figure 8-59. LSB_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

TIME_STAMP_

EN

R/W-0x0

Table 8-97. LSB_CTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:1

0

RESERVED

Must write default value.

TIME_STAMP_EN

When set, the transport layer transmits the timestamp signal on

the LSB of the output samples. The latency of the timestamp

signal (through the entire chip) should match the latency of the

analog ADC inputs. Please also set TMSTP_RECV_EN when using

TIME_STAMP_EN.

Note 1: The control bit is placed on the LSB of the JESD204C

samples. In some cases, the JESD204C sample width (N) is greater

than the sample width from the ADC. In these cases, the control bit

does not replace the LSB of the ADC sample since it is placed at the

LSB of the N-bit field).

Note 2: The control bit that is enabled by this register is never

advertised in the ILA (CS is 0 in the ILA).

8.5.7.41 JESD_EN Register (Address = 0x200) [reset = 0x01]

JESD_EN is shown in Figure 8-60 and described in Table 8-98.

Return to the Table 8-56.

JESD204C Subsystem Enable (default: 0x01)

Figure 8-60. JESD_EN Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JESD_EN

R/W-0x1

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Table 8-98. JESD_EN Register Field Descriptions

Bit

7:1

0

Field

Type

R/W

Reset

0x0

0x1

Description

RESERVED

JESD_EN

Must write default value.

0 : Disable JESD204C interface

1 : Enable JESD204C interface

Note: Before altering other JESD204C registers, you must clear

JESD_EN. When JESD_EN is 0, the block is held in reset and

the serializers are powered down. The clocks are gated off to save

power. The LMFC/LEMC counter is also held in reset, so SYSREF

will not align the LMFC/LEMC.

Note: Always set CAL_EN before setting JESD_EN.

Note: Always clear JESD_EN before clearing CAL_EN.

8.5.7.42 JMODE Register (Address = 0x201) [reset = 0x00]

JMODE is shown in Figure 8-61 and described in Table 8-99.

Return to the Table 8-56.

JESD204C Mode (default: 0x00)

Figure 8-61. JMODE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JMODE

R/W-0x0

Table 8-99. JMODE Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:6

5:0

RESERVED

JMODE

Must write default value.

Specifies the JESD204C output mode. See JESD204C Mode table.

Note: This register should only be changed when JESD_EN=0 and

CAL_EN=0.

8.5.7.43 KM1 Register (Address = 0x202) [reset = 0x1F]

KM1 is shown in Figure 8-62 and described in Table 8-100.

Return to the Table 8-56.

JESD204C K Parameter (minus 1) (default: 0x1F)

Figure 8-62. KM1 Register

7

6

5

4

3

2

1

0

KM1

R/W-0x1F

Table 8-100. KM1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

KM1

R/W

0x1F

K is the number of frames per multiframe and this register must be

programmed as K-1. Depending on the JMODE setting, there are

constraints on the legal values of K (see K parameter in JESD204C

Mode table). The default value is KM1=31, which corresponds to

K=32.

Note: For modes using the 64B/66B link layer, the KM1 register is

ignored and the value of K is determined from E and F (which are

derived from JMODE). The effective value of K is 256*E/F.

Note: This register should only be changed when JESD_EN is 0.

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8.5.7.44 JSYNC_N Register (Address = 0x203) [reset = 0x01]

JSYNC_N is shown in Figure 8-63 and described in Table 8-101.

Return to the Table 8-56.

JESD204C Manual Sync Request (default: 0x01)

Figure 8-63. JSYNC_N Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JSYNC_N

R/W-0x1

Table 8-101. JSYNC_N Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x1

Description

7:1

0

RESERVED

JSYNC_N

Must write default value.

Set this bit to 0 to request JESD204C synchronization (equivalent to

the SYNC~ signal being asserted). For normal operation, leave this

bit set to 1.

Note: The JSYNC_N register can always generate a synchronization

request, regardless of the SYNC_SEL register. However, if

the selected sync pin is stuck low, you cannot de-assert the

synchronization request unless you program SYNC_SEL=2.

8.5.7.45 JCTRL Register (Address = 0x204) [reset = 0x03]

JCTRL is shown in Figure 8-64 and described in Table 8-102.

Return to the Table 8-56.

JESD204C Control (default: 0x03)

Figure 8-64. JCTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

ALT_LANES

R/W-0x0

SYNC_SEL

R/W-0x0

SFORMAT

R/W-0x1

SCR

R/W-0x1

Table 8-102. JCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4

RESERVED

ALT_LANES

R/W

0x0

Must write default value.

R/W

0x0

0 : Normal lane mapping (default) as shown in the JESD204C output

mode section.

Lanes 0 thru L-1 are used.

1 : Alternate lane mapping (use upper lanes).

Lanes 4 to 4+L-1 are used. Lanes 0 to 3 are unused. This option

is only supported when JMODE selects a mode that uses 4 or less

lanes per link (L<=4). The behavior is undefined for modes that use

more than 4 lanes.

3:2

1

SYNC_SEL

SFORMAT

R/W

0x0

0x1

0 : Use the SYNCSE input for SYNC~ function (default)

1 : Use the TMSTP± input for SYNC~ function. TMSTP_RECV_EN

must also be set.

2 : Do not use any SYNC~ input pin (use JSYNC_N as a software

SYNC~)

Output sample format for JESD204C samples

0 : Offset binary

1 : Signed 2’s complement (default)

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Table 8-102. JCTRL Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

SCR

R/W

0x1

0 : 8B/10B Scrambler disabled (applies only to 8B/10B modes)

1 : 8B/10B Scrambler enabled (default)

Note 1: The 8b/10b scrambler is recommended to improve spurious

noise and specify certain sample payloads cannot prevent the

JESD204C receiver from detecting incorrect code-group or lane

alignment. 64B/66B modes always use scrambling. This register

does not apply to 64B/66B modes.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.46 JTEST Register (Address = 0x205) [reset = 0x00]

JTEST is shown in Figure 8-65 and described in Table 8-103.

Return to the Table 8-56.

JESD204C Test Control (default: 0x00)

Figure 8-65. JTEST Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

JTEST

R/W-0x0

Table 8-103. JTEST Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

JTEST

Must write default value.

0 : Test mode disabled. Normal operation (default)

1 : PRBS7 test mode

2 : PRBS15 test mode

3 : PRBS23 test mode

4 : Ramp test mode

5 : Transport Layer test mode

6 : D21.5 test mode

7 : K28.5 test mode*

8 : Repeated ILA test mode*

9 : Modified RPAT test mode*

10: Serial outputs held low

11: Serial outputs held high

12: RESERVED

13: PRBS9 test mode

14: PRBS31 test mode

15: Clock test pattern (0x00FF)

16: K28.7 test mode*

17-31: RESERVED

* These test modes are only supported when JMODE is selecting a

mode that utilizes 8B/10B encoding.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.47 DID Register (Address = 0x206) [reset = 0x00]

DID is shown in Figure 8-66 and described in Table 8-104.

Return to the Table 8-56.

JESD204C DID Parameter (default: 0x00)

Figure 8-66. DID Register

7

6

5

4

3

2

1

0

DID

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Figure 8-66. DID Register (continued)

R/W-0x0

Table 8-104. DID Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

DID

R/W

0x0

Specifies the DID (Device ID) value that is transmitted during the

second multiframe of the JESD204B ILA.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.48 FCHAR Register (Address = 0x207) [reset = 0x00]

FCHAR is shown in Figure 8-67 and described in Table 8-105.

Return to the Table 8-56.

JESD204C Frame Character (default: 0x00)

Figure 8-67. FCHAR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

FCHAR

R/W-0x0

Table 8-105. FCHAR Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:2

1:0

RESERVED

FCHAR

Must write default value.

Specify which comma character is used to denote end-of-frame. This

character is transmitted opportunistically. This only applies to modes

that utilize 8B/10B encoding.

0 : Use K28.7 (default) (JESD204C compliant)

1 : Use K28.1 (not JESD204C compliant)

2 : Use K28.5 (not JESD204C compliant)

3 : Reserved

When using a JESD204C receiver, always use FCHAR=0. When

using a general purpose 8B/10B receiver, the K28.7 character may

cause issues. When K28.7 is combined with certain data characters,

a false, misaligned comma character can result, and some receivers

will re-align to the false comma. To avoid this, program FCHAR to 1

or 2.

Note: This register should only be changed when JESD_EN is 0.

8.5.7.49 JESD_STATUS Register (Address = 0x208) [reset = 0x0]

JESD_STATUS is shown in Figure 8-68 and described in Table 8-106.

Return to the Table 8-56.

JESD204C / System Status Register

Figure 8-68. JESD_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

LINK_UP

R/W-0x0

SYNC_STATUS REALIGNED

R/W-0x0 R/W-0x0

ALIGNED

R/W-0x0

SPLL_LOCKED RESERVED CPLL_LOCKED

R/W-0x0 R/W-0x0 R/W-0x0

Table 8-106. JESD_STATUS Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

0x0

Description

RESERVED

LINK_UP

6

When set, indicates that the JESD204C link is up.

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Table 8-106. JESD_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

SYNC_STATUS

REALIGNED

ALIGNED

R/W

0x0

Returns the state of the JESD204C SYNC~ signal.

0 : SYNC~ asserted

1 : SYNC~ de-asserted

4

3

R/W

0x0

When high, indicates that the digital block clock, frame clock, or

multiframe clock phase was realigned by SYSREF. Writing a 1 to this

bit will clear it.

When high, indicates that the multiframe (LMFC) clock phase has

been established by SYSREF. The first SYSREF event after enabling

the JESD204B encoder will set this bit. Writing a 1 to this bit will clear

it.

2

1

0

SPLL_LOCKED

RESERVED

R/W

0x0

When high, indicates that the SerDes PLL (S-PLL) is locked.

CPLL_LOCKED

When high, indicates that the converter PLL (C-PLL) is locked.

8.5.7.50 CH_EN Register (Address = 0x209) [reset = 0x03]

CH_EN is shown in Figure 8-69 and described in Table 8-107.

Return to the Table 8-56.

JESD204C Channel Enable (default: 0x03)

Figure 8-69. CH_EN Register

7

6

5

4

3

2

1

0

RESERVED

SINGLE_CH_E

N

CD_EN

AB_EN

R/W-0x0

R/W-0x1

Table 8-107. CH_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

2

RESERVED

R/W

0x0

Must write default value.

SINGLE_CH_EN

R/W

0x0

0x1

When set, single channel mode is enabled and channels B, C and D

are disabled. AB_EN must be set to 1.

1

0

CD_EN

When set, the C and D channels are enabled. Set to 0 to disable

channels C and D. Set this bit to enable dual channel operation.

AB_EN

When set, the A and B channels are enabled. Set to 0 to disable

channel A and B.

Important notes:

1. You must set CAL_EN=0 and JESD_EN=0 before changing

CH_EN.

2. Do not use this register to disable (power down) all channels since

this state is undefined. Instead use the MODE register to power

down the full device.

3. When either pair of channels is disabled, the JESD204C link will

scale down the number of lanes and converters: L = ceiling(Lx/2) and

M = Mx/2. If Lx is odd, tail bits are added to the end of the highest

lane to pad out the frame (as per the JESD204C standard).

4. When AB_EN=0, the samples for channels C & D are placed

within the JESD204C frame where the A & B samples would

normally be located.

8.5.7.51 SHMODE Register (Address = 0x20F) [reset = 0x00]

SHMODE is shown in Figure 8-70 and described in Table 8-108.

Return to the Table 8-56.

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JESD204C Sync Word Mode (default: 0x00)

Figure 8-70. SHMODE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SHMODE

R/W-0x0

Table 8-108. SHMODE Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:2

1:0

RESERVED

SHMODE

Must write default value.

Select the mode for the 64B/66B sync word (32 bits of data per

multi-block). This only applies when JMODE is selecting a 64B/66B

mode.

0 : Transmit CRC-12 signal (default setting)

1 : RESERVED

2 : Transmit FEC signal

3 : RESERVED

Note: This device does not support any JESD204C command

features. All command fields will be set to zero (idle headers).

Note: This register should only be changed when JESD_EN is 0.

8.5.7.52 SYNC_THRESH Register (Address = 0x210) [reset = 0x03]

SYNC_THRESH is shown in Figure 8-71 and described in Table 8-109.

Return to the Table 8-56.

JESD204C SYNC~ Threshold (default: 0x03)

Figure 8-71. SYNC_THRESH Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

SYNC_THRESH

R/W-0x3

Table 8-109. SYNC_THRESH Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

0x3

Description

7:5

4:0

RESERVED

Must write default value.

SYNC_THRESH

This register defines how many times the SYNC~ signal must be

sampled low before the JESD204C transmitter interprets it as a

synchronization request.

The SYNC~ signal is sampled by the link clock (fS/2). If SYNC~

is sampled low for SYNC_THRESH+1 consecutive clock cycles, it

will be interpreted as a synchronization request. Refer to JESD204C

section 8.8.2 for more details. If SYNC~ is sampled low for less than

SYNC_THRESH+1 clock cycles, it is considered to be an error report

and is ignored.

Note: This register should only be changed when JESD_EN is 0.

Note: Since this design does not do anything with an error reported

on the SYNC~ interface, it is recommended that error reporting be

disabled on the receiver and SYNC_THRESH programmed to 0.

This provides the fastest response time for synchronization requests.

8.5.7.53 OVR_TH Register (Address = 0x211) [reset = 0xF2]

OVR_TH is shown in Figure 8-72 and described in Table 8-110.

Return to the Table 8-56.

Over-range Threshold (default: 0xF2)

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Figure 8-72. OVR_TH Register

7

6

5

4

3

2

1

0

OVR_TH

R/W-0xF2

Table 8-110. OVR_TH Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

OVR_TH

R/W

0xF2

This parameter defines the absolute sample level that causes the

over-range outputs to be asserted. The detection level in dBFS

(peak) is 20log10(OVR_TH/256) (Default: 0xF2 = 242-> -0.5dBFS)

8.5.7.54 OVR_CFG Register (Address = 0x213) [reset = 0x07]

OVR_CFG is shown in Figure 8-73 and described in Table 8-111.

Return to the Table 8-56.

Over-range Enable / Hold Off (default: 0x07)

Figure 8-73. OVR_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

OVR_EN

R/W-0x0

OVR_N

R/W-0x7

Table 8-111. OVR_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

OVR_EN

R/W

0x0

Must write default value.

R/W

0x0

0x7

Enables over-range status output pins when set high. The ORA,

ORB, ORC and ORD outputs are held low when OVR_EN is set low.

2:0

OVR_N

Program this register to adjust the pulse extension for the ORA,

ORB, ORC and ORD outputs. The minimum pulse duration of the

over-range outputs is 4 * 2^OVR_Nsampling cycles. Incrementing this

field doubles the monitoring period.

8.5.7.55 INIT_STATUS Register (Address = 0x270) [reset = 0x0]

INIT_STATUS is shown in Figure 8-74 and described in Table 8-112.

Return to the Table 8-56.

Initialization Status (read-only)

Figure 8-74. INIT_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

INIT_DONE

R-0x0

Table 8-112. INIT_STATUS Register Field Descriptions

Bit

Field

Type

Reset

0x0

Description

7:1

0

RESERVED

INIT_DONE

R

Returns 1 when the initialization logic has finished initializing the

device. This indicates that it is now safe to proceed with startup. No

SPI transactions should be performed before INIT_DONE returns 1

(except SOFT_RESET).

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8.5.7.56 LOW_POWER2 Register (Address = 0x29A) [reset = 0x0F]

LOW_POWER2 is shown in Figure 8-75 and described in Table 8-113.

Return to the Table 8-56.

Low Power Mode 2 (default: 0x0F)

Figure 8-75. LOW_POWER2 Register

7

6

5

4

3

2

1

0

LOW_POW_MODE2

R/W-0xF

Table 8-113. LOW_POWER2 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

LOW_POW_MODE2

R/W

0xF

Set this register along with LOW_POWER1, LOW_POWER3 and

LOW_POWER4 to enable Low Power Mode. All registers must

be set together. Calibration must be performed after changing the

operating mode:

0x06 : Low Power Mode

0x0F : High Performance Mode (default)

All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this

register.

8.5.7.57 LOW_POWER3 Register (Address = 0x29B) [reset = 0x04]

LOW_POWER3 is shown in Figure 8-76 and described in Table 8-114.

Return to the Table 8-56.

Low Power Mode 3 (default: 0x04)

Figure 8-76. LOW_POWER3 Register

7

6

5

4

3

2

1

0

LOW_POW_MODE3

R/W-0x4

Table 8-114. LOW_POWER3 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

LOW_POW_MODE3

R/W

0x4

Set this register along with LOW_POWER1, LOW_POWER2 and

LOW_POWER4 to enable Low Power Mode. All registers must

be set together. Calibration must be performed after changing the

operating mode:

0x00 : Low Power Mode

0x04 : High Performance Mode (default)

All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this

register.

8.5.7.58 LOW_POWER4 Register (Address = 0x29C) [reset = 0x1B]

LOW_POWER4 is shown in Figure 8-77 and described in Table 8-115.

Return to the Table 8-56.

Low Power Mode 4 (default: 0x1B)

Figure 8-77. LOW_POWER4 Register

7

6

5

4

3

2

1

0

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Figure 8-77. LOW_POWER4 Register (continued)

LOW_POW_MODE4

R/W-0x1B

Table 8-115. LOW_POWER4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

LOW_POW_MODE4

R/W

0x1B

Set this register along with LOW_POWER1, LOW_POWER2 and

LOW_POWER3 to enable Low Power Mode. All registers must

be set together. Calibration must be performed after changing the

operating mode:

0x14 : Low Power Mode

0x1B : High Performance Mode (default)

All other values are RESERVED

Note: Must set CAL_EN to 0 and JESD_EN to 0 before changing this

register.

8.5.7.59 ALARM Register (Address = 0x2C0) [reset = 0x0]

ALARM is shown in Figure 8-78 and described in Table 8-116.

Return to the Table 8-56.

Alarm Interrupt (read-only)

Figure 8-78. ALARM Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

ALARM

R-0x0

Table 8-116. ALARM Register Field Descriptions

Bit

Field

Type

Reset

0x0

Description

7:1

0

RESERVED

ALARM

R

This bit returns a ‘1’ whenever any alarm occurs that is unmasked

in the ALM_STATUS register. Use ALM_MASK to mask (disable)

individual alarms. CAL_STATUS_SEL can be used to drive the

ALARM bit onto the CALSTAT output pin to provide a hardware

alarm interrupt signal.

8.5.7.60 ALM_STATUS Register (Address = 0x2C1) [reset = 0x3F]

ALM_STATUS is shown in Figure 8-79 and described in Table 8-117.

Return to the Table 8-56.

Alarm Status (default: 0x3F, write to clear)

Figure 8-79. ALM_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

FIFO_ALM

SPLL_ALM

LINK_ALM

REALIGNED_A

LM

RESERVED

CLK_ALM

R/W-0x1

Table 8-117. ALM_STATUS Register Field Descriptions

Bit

7:6

Field

Type

Reset

Description

RESERVED

R/W

0x0

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Table 8-117. ALM_STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

FIFO_ALM

R/W

0x1

FIFO overflow/underflow alarm: This bit is set whenever an

active JESD204C lane FIFO experiences an underflow or overflow

condition. Write a ‘1’ to clear this bit. To inspect which lane generated

the alarm, read FIFO_LANE_ALM.

4

3

SPLL_ALM

LINK_ALM

R/W

0x1

S-PLL Lock Lost Alarm: This bit is set whenever the SerDes S-PLL is

not locked. Write a ‘1’ to clear this bit.

Link Alarm: This bit is set whenever the JESD204C link is enabled,

but is not in the DATA_ENC state (8B/10B modes). In 64B/66B

modes, there is no DATA_ENC state, so this alarm will fire when

the link first starts up, and will also fire if any event causes a FIFO/

Serializer realignment. Write a ‘1’ to clear this bit.

2

REALIGNED_ALM

R/W

0x1

Realigned Alarm: This bit is set whenever SYSREF causes the

internal clocks (including the LMFC/LEMC) to be realigned. Write a

‘1’ to clear this bit.

1

0

RESERVED

CLK_ALM

R/W

0x1

Clock Alarm: This bit can be used to detect an upset to the internal

digital block and JESD204C clocks. This bit is set whenever the

internal clock dividers for the A and B channels do not match the

C and D channels. Write a ‘1’ to clear this bit. Refer to the alarm

section for the proper usage of this register.

Note: After power-on reset or soft-reset, all alarm bits are set to ‘1.’

Note: When JESD_EN=0, all alarms (except CLK_ALM) are

undefined. It is recommended that the user clears the alarms after

setting JESD_EN=1.

8.5.7.61 ALM_MASK Register (Address = 0x2C2) [reset = 0x3F]

ALM_MASK is shown in Figure 8-80 and described in Table 8-118.

Return to the Table 8-56.

Alarm Mask Register (default: 0x3F)

Figure 8-80. ALM_MASK Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

MASK_FIFO_A MASK_PLL_AL MASK_LINK_A MASK_REALIG

RESERVED MASK_CLK_AL

M

LM

M

LM

NED_ALM

R/W-0x1

Table 8-118. ALM_MASK Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0x0

Must write default value.

MASK_FIFO_ALM

R/W

0x1

When set, FIFO_ALM is masked and will not impact the ALARM

register bit.

4

3

2

MASK_PLL_ALM

MASK_LINK_ALM

When set, PLL_ALM is masked and will not impact the ALARM

register bit.

When set, LINK_ALM is masked and will not impact the ALARM

register bit.

MASK_REALIGNED_ALM

When set, REALIGNED_ALM is masked and will not impact the

ALARM register bit.

1

0

RESERVED

R/W

0x1

Must write default value.

MASK_CLK_ALM

When set, CLK_ALM is masked and will not impact the ALARM

register bit.

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8.5.7.62 FIFO_LANE_ALM Register (Address = 0x2C4) [reset = 0xFF]

FIFO_LANE_ALM is shown in Figure 8-81 and described in Table 8-119.

Return to the Table 8-56.

FIFO Overflow/Underflow Alarm (default: 0xFF)

Figure 8-81. FIFO_LANE_ALM Register

7

6

5

4

3

2

1

0

FIFO_LANE_ALM

R/W-0xFF

Table 8-119. FIFO_LANE_ALM Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

FIFO_LANE_ALM

R/W

0xFF

FIFO_LANE_ALM[i] is set if the FIFO for lane i experiences overflow

or underflow. Use this register to determine which lane(s) generated

an alarm. Writing a ‘1’ to any bit in this register will clear the

alarm (the alarm may immediately trip again if the overflow/underflow

condition persists). Writing a ‘1’ to the FIFO_ALM register will clear

all bits of this register.

8.5.7.63 OFS0 Register (Address = 0x330) [reset = 0x0]

OFS0 is shown in Figure 8-82 and described in Table 8-120.

Return to the Table 8-56.

Offset Adjustment for ADC0 (default from Fuse ROM)

Figure 8-82. OFS0 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS0

R/W-0x0

4

3

OFS0

R/W-0x0

Table 8-120. OFS0 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS0

Must write default value.

Offset adjustment value applied to ADC0. The format is unsigned.

Important note: Do not access any OFS* registers if the calibration

system is performing offset calibration.

Case 1: If CAL_BGOS or CAL_BG is 0 and CAL_OS is 1, you may

access OFS* registers after FG_DONE goes high.

Case 2: If CAL_BG=1 and CAL_BGOS=1, you should not access

the OFS* registers. For background calibration without continuous

offset calibration, set CAL_OS to 1 and CAL_BG to 1, but keep

CAL_BGOS set to 0. This will still calibrate the offset of the spare

ADC cores during the foreground offset calibration step.

Case 3: If none of the above conditions apply, you may access the

OFS* registers without waiting.

8.5.7.64 OFS1 Register (Address = 0x332) [reset = 0x0]

OFS1 is shown in Figure 8-83 and described in Table 8-121.

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Return to the Table 8-56.

Offset Adjustment for ADC1 (default from Fuse ROM)

Figure 8-83. OFS1 Register

15

7

14

6

13

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS1

R/W-0x0

5

4

3

OFS1

R/W-0x0

Table 8-121. OFS1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS1

Must write default value.

Offset adjustment value applied to ADC1.

8.5.7.65 OFS2A Register (Address = 0x334) [reset = 0x0]

OFS2A is shown in Figure 8-84 and described in Table 8-122.

Return to the Table 8-56.

Offset Adjustment for ADC2 (INA±) (default from Fuse ROM)

Figure 8-84. OFS2A Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS2A

R/W-0x0

4

3

OFS2A

R/W-0x0

Table 8-122. OFS2A Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS2A

Must write default value.

Offset adjustment value applied to ADC2 when sampling INA±.

8.5.7.66 OFS2B Register (Address = 0x336) [reset = 0x0]

OFS2B is shown in Figure 8-85 and described in Table 8-123.

Return to the Table 8-56.

Offset Adjustment for ADC2 (INB±) (default from Fuse ROM)

Figure 8-85. OFS2B Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS2B

R/W-0x0

4

3

OFS2B

R/W-0x0

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Figure 8-85. OFS2B Register (continued)

Table 8-123. OFS2B Register Field Descriptions

Bit

15:12

11:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

OFS2B

Must write default value.

Offset adjustment value applied to ADC2 when sampling INB±.

8.5.7.67 OFS3C Register (Address = 0x338) [reset = 0x0]

OFS3C is shown in Figure 8-86 and described in Table 8-124.

Return to the Table 8-56.

Offset Adjustment for ADC3 (INC±) (default from Fuse ROM)

Figure 8-86. OFS3C Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS3C

R/W-0x0

4

3

OFS3C

R/W-0x0

Table 8-124. OFS3C Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS3C

Must write default value.

Offset adjustment value applied to ADC3 when sampling INC±.

8.5.7.68 OFS3D Register (Address = 0x33A) [reset = 0x0]

OFS3D is shown in Figure 8-87 and described in Table 8-125.

Return to the Table 8-56.

Offset Adjustment for ADC3 (IND±) (default from Fuse ROM)

Figure 8-87. OFS3D Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS3D

R/W-0x0

4

3

OFS3D

R/W-0x0

Table 8-125. OFS3D Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS3D

Must write default value.

Offset adjustment value applied to ADC3 when sampling IND±.

8.5.7.69 OFS4 Register (Address = 0x33C) [reset = 0x0]

OFS4 is shown in Figure 8-88 and described in Table 8-126.

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Return to the Table 8-56.

Offset Adjustment for ADC4 (default from Fuse ROM)

Figure 8-88. OFS4 Register

15

7

14

6

13

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS4

R/W-0x0

5

4

3

OFS4

R/W-0x0

Table 8-126. OFS4 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS4

Must write default value.

Offset adjustment value applied to ADC4.

8.5.7.70 OFS5 Register (Address = 0x33E) [reset = 0x0]

OFS5 is shown in Figure 8-89 and described in Table 8-127.

Return to the Table 8-56.

Offset Adjustment for ADC5 (default from Fuse ROM)

Figure 8-89. OFS5 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R/W-0x0

OFS5

R/W-0x0

4

3

OFS5

R/W-0x0

Table 8-127. OFS5 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

15:12

11:0

RESERVED

OFS5

Must write default value.

Offset adjustment value applied to ADC5.

8.5.7.71 GAIN0 Register (Address = 0x360) [reset = 0x0]

GAIN0 is shown in Figure 8-90 and described in Table 8-128.

Return to the Table 8-56.

Fine Gain Adjust for ADC0 (default from Fuse ROM)

Figure 8-90. GAIN0 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN0

R/W-0x0

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Table 8-128. GAIN0 Register Field Descriptions

Bit

7:5

4:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

GAIN0

Must write default value.

Fine gain adjustment for ADC0.

8.5.7.72 GAIN1 Register (Address = 0x361) [reset = 0x0]

GAIN1 is shown in Figure 8-91 and described in Table 8-129.

Return to the Table 8-56.

Fine Gain Adjust for ADC1 (default from Fuse ROM)

Figure 8-91. GAIN1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN1

R/W-0x0

Table 8-129. GAIN1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

GAIN1

Must write default value.

Fine gain adjustment for ADC1.

8.5.7.73 GAIN2A Register (Address = 0x362) [reset = 0x0]

GAIN2A is shown in Figure 8-92 and described in Table 8-130.

Return to the Table 8-56.

Fine Gain Adjust for ADC2 (INA±) (default from Fuse ROM)

Figure 8-92. GAIN2A Register

7

6

5

4

3

2

1

RESERVED

R/W-0x0

GAIN2A

R/W-0x0

Table 8-130. GAIN2A Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

GAIN2A

Must write default value.

Fine gain adjustment for ADC2 when sampling INA±.

8.5.7.74 GAIN2B Register (Address = 0x363) [reset = 0x0]

GAIN2B is shown in Figure 8-93 and described in Table 8-131.

Return to the Table 8-56.

Fine Gain Adjust for ADC2 (INB±) (default from Fuse ROM)

Figure 8-93. GAIN2B Register

7

6

5

4

3

2

1

RESERVED

R/W-0x0

GAIN2B

R/W-0x0

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Table 8-131. GAIN2B Register Field Descriptions

Bit

7:5

4:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

GAIN2B

Must write default value.

Fine gain adjustment for ADC2 when sampling INB±.

8.5.7.75 GAIN3C Register (Address = 0x364) [reset = 0x0]

GAIN3C is shown in Figure 8-94 and described in Table 8-132.

Return to the Table 8-56.

Fine Gain Adjust for ADC3 (INC±) (default from Fuse ROM)

Figure 8-94. GAIN3C Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN3C

R/W-0x0

Table 8-132. GAIN3C Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

GAIN3C

Must write default value.

Fine gain adjustment for ADC3 when sampling INC±.

8.5.7.76 GAIN3D Register (Address = 0x365) [reset = 0x0]

GAIN3D is shown in Figure 8-95 and described in Table 8-133.

Return to the Table 8-56.

Fine Gain Adjust for ADC3 (IND±) (default from Fuse ROM)

Figure 8-95. GAIN3D Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN3D

R/W-0x0

Table 8-133. GAIN3D Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

GAIN3D

Must write default value.

Fine gain adjustment for ADC3 when sampling IND±.

8.5.7.77 GAIN4 Register (Address = 0x366) [reset = 0x0]

GAIN4 is shown in Figure 8-96 and described in Table 8-134.

Return to the Table 8-56.

Fine Gain Adjust for ADC4 (default from Fuse ROM)

Figure 8-96. GAIN4 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN4

R/W-0x0

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Table 8-134. GAIN4 Register Field Descriptions

Bit

7:5

4:0

Field

Type

R/W

Reset

0x0

Description

RESERVED

GAIN4

Must write default value.

Fine gain adjustment for ADC4.

8.5.7.78 GAIN5 Register (Address = 0x367) [reset = 0x0]

GAIN5 is shown in Figure 8-97 and described in Table 8-135.

Return to the Table 8-56.

Fine Gain Adjust for ADC5 (default from Fuse ROM)

Figure 8-97. GAIN5 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0x0

GAIN5

R/W-0x0

Table 8-135. GAIN5 Register Field Descriptions

Bit

Field

Type

R/W

Reset

0x0

Description

7:5

4:0

RESERVED

GAIN5

Must write default value.

Fine gain adjustment for ADC5.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The ADC12xJ800 can be used in a wide range of applications including light detection and ranging (LiDAR),

RADAR, satellite communications, handheld test equipment (communications testers and oscilloscopes), and

software-defined radios (SDR). The wide input bandwidth enables direct RF sampling to at least 4 GHz and the

high sampling rate allows signal bandwidths of greater than 300 MHz. The Typical Applications section describes

the use of the device in a LiDAR application using the integrated clocking features to reduce system cost,

component count and solution size.

9.2 Typical Applications

9.2.1 Light Detection and Ranging (LiDAR) Digitizer

A LiDAR system uses a laser to send a light pulse toward a target and measures reflections off of the target

using photodiodes. The photodiodes are connected to transimpedance amplifiers (TIA) to convert the current

generated by the reflected light into a voltage. An ADC converts the voltage to a digital signal and extracts the

pulse arrival time and reflected energy of the pulse. The device has a number of features that makes it ideal

as the digitizer for a LiDAR system including high sampling rate, high performance, high input bandwidth and

integrated clocking features. An example LiDAR system digitizer is shown in Figure 9-1 which uses up to four

ADC channels running at 800 MSPS and the on-chip clocking features of the device to reduce the component

count, size and cost of the system.

Figure 9-1. Typical Configuration for a LiDAR Digitizer

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9.2.1.1 Design Requirements

An example list of LiDAR system requirements and the resulting digitizer requirements is given in Table 9-1.

The example system requirements are for a mechanically rotating LiDAR system using a spinning mirror to

cover the horizontal (azimuth) field-of-view and parallel receivers (photodiodes) to cover the vertical (elevation)

field-of-view. The scan time requirement dictates that four vertical points are captured in parallel which requires

four ADC channels and therefore a 16:1 photodiode to ADC mux ratio. The long 200 meter range for a 10%

reflectivity target requires high performance and therefore a 12-bit ADC is chosen. The minimum pulse width of 5

ns, for high spatial resolution, requires a sampling rate of 800 MSPS in order to get 4 samples of each returning

pulse. Low cost and small size are important to enable high volume production and a quad channel ADC with

integrated clocking features help drive down these important metrics. Other considerations include the maximum

SerDes rate supported by the FPGA and number of lanes. Assume the FPGA has 4 SerDes lanes that support

up to 12.5 Gbps. For this reason, JMODE 8 is chosen.

Table 9-1. LiDAR System and Digitizer Requirements

System Parameter

Maximum Target Range

Minimum Laser Pulse Width

Horizontal FOV

Example System Requirement

Example Digitizer Requirement

200 meters at 10% reflectivity

12-bit ADC

5 ns

360°

800 MSPS (4 samples per pulse)

See Full Scan Time

Vertical FOV

20°

See Vertical Scanning Method

See Full Scan Time

Horizontal Resolution

Vertical Resolution

Horizontal Scanning Method

Vertical Scanning Method

Full Scan Time

0.1°

0.3125°

See Vertical Scanning Method

See Full Scan Time

Spinning mirror

Parallel photodiodes

76.8 ms

64 photodiodes

16:1 mux ratio (4 ADC channels)

Clock features integrated in ADC

Quad channel ADC with integrated clocking

System Cost

Low cost

System Form Factor

Small form factor

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9.2.1.2 Detailed Design Procedure

The details surrounding the LiDAR example design are provided in this section, including how to choose

components and how to calculated the necessary clock frequencies.

9.2.1.2.1 Analog Front-End Requirements

The ADC channels are fed from an analog front end (AFE) which contains photodiodes, TIAs, fully-differential

amplifiers (FDA) and analog muxes. The return pulse is collected by an optical lens which focuses the light to

the corresponding photodiode. The photodiode generates a current which is converted to a voltage and amplified

by a TIA. This single-ended voltage is converted to a differential voltage using a fully-differential amplifier which

then drives the differential input of the ADC. The ADC common-mode voltage of 1.1V is easily interfaced to by

unipolar supply FDAs for lowest cost. Analog muxing of parallel photodiode receivers can be done after the TIAs

or after the FDAs depending on the chosen components.

The input network must have sufficient bandwidth to support the minimum pulse width required by the system.

The required bandwidth to support a given rise time (10-90%) is given in Equation 13.

BW [MHz] = 350 / t_R[ns]

(13)

Assuming the laser has a rise and fall time of 1 ns (10-90%), then the input network bandwidth should be greater

than 400 MHz to avoid excessive degradation of the pulse shape and spatial resolution.

9.2.1.2.2 Calculating Clock and SerDes Frequencies

The example LiDAR system uses four ADC channels running at 800MSPS and the on-chip clock features of the

device to reduce the system size and cost. The device is clocked by a 50-MHz crystal through the single-ended

clock input (CLK_SE) and the integrated clock features are used to eliminate external clocking components. The

internal PLL (C-PLL) generates the 800 MHz sampling clock for the ADC cores. The 50 MHz PLL reference

is repeated through the PLLREFO output to the FPGA to generate the FPGA internal clocks including the

application layer clock. The 50 MHz reference is divided down in the FPGA to generate the SYSREF signal

which is sent to both the FPGA JESD204C core and to the device to achieve deterministic latency.

There are a number of clocking frequencies used in the example system shown in Figure 9-1. The reference

clock frequency (f_REF) is chosen by the designer and in this case is chosen as 50 MHz, which is the minimum

supported reference frequency and which multiplies easily to 800 MHz. The sampling rate is set by the system

requirements which is 800 MSPS (f_S). The V, P and N dividers of the C-PLL are chosen as described in the

Coverter PLL (C-PLL) section which, along with the reference frequency, determines the VCO frequency (f_VCO).

JMODE 8 was chosen to stay within the FPGA SerDes requirements (4 lanes, 12.5 Gbps max rate) which

is a 64B/66B mode. TRIGOUT provides the FPGA SerDes PLL reference clock to the FPGA (f_TRIGOUT) and

PLLREFO provides the reference clock for the FPGA core logic. ORC (f_ORC) and ORD (f_ORD) provide additional

clock outputs, if needed, for the FPGA or peripheral devices. SYSREF is generated within the FPGA and sent

to the ADC in order to achieve deterministic latency. This is not usually recommended due to timing constraints,

however the low reference frequency (50 MHz) significantly relaxes the SYSREF setup and hold timing and the

SYSREF Windowing feature allows verification of proper capture timing of SYSREF relative to the reference

clock. The SYSREF frequency must divide evenly into the reference clock frequency, in addition to meeting

the JESD204 protocol requirements, in order to achieve deterministic latency due to the use of the C-PLL. The

frequency and rate calculations are summarized in Table 9-2.

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Table 9-2. Clock and SerDes Frequency Calculations for Example LiDAR Digitizer

Clock

Symbol

Calculation

Frequency

Reference Clock

Sampling Rate

f_REF

Chosen by designer

System requirement

50 MHz

f_S

800 MSPS

f_VCO= f_Sx P x V

where P is 2 and V is 5

C-PLL VCO

SerDes Linerate

f_VCO

8 GHz

f_LINERATE= f_Sx R

where R is 12.375 for JMODE 8

(see Table 8-16, Table 8-17 and Table 8-18)

f_LINERATE

9.9 Gbps / Lane (4 lanes)

309.375 MHz

f_TRIGOUT= f_LINERATE/ RX_DIV

where RX_DIV is 32 (TRIGOUT_CTRL=0x81)

TRIGOUT Clock Output

f_TRIGOUT

f_SYSREF= f_LINERATE/(66 x 32 x E x n)

where E is 3 for JMODE 8 (64B or 66B mode) and n is

chosen such that f_SYSREFis an integer division of

f_REF(n = 5)

SYSREF

f_SYSREF

312.5 kHz

ORC Clock Output

ORD Clock Output

f_ORC

f_ORD

f_ORC= f_REF/2 (See Table 8-5)

25 MHz

50 MHz

f_ORD= f_REF

(See Table 8-6)

f_FPGA= f_REFx M^{(1) (2)}

where M is an integer value, chosen as 5

250 MHz (4 samples per

cycle)

FPGA Core Clock

f_FPGA

(1) In the clock configuration shown, the FPGA clock which runs the JESD204C core must be an integer multiplication of f_REFin order to

properly pass SYSREF from the reference clock domain to the core clock domain to achieve deterministic latency. In many cases the

JESD204C IP may expect a clock rate of f_LINERATE/66, which results in 150 MHz for the example. Some JESD204C IP cores may not

allow the JESD204C clock frequency to deviate from this requirement and therefore IP provider should be consulted. If the requirement

described for the FPGA core clock cannot be met than deterministic latency cannot be achieved (operation without deterministic

latency is still supported).

(2) If the application layer runs at a different clock rate than the JESD204C core, then some logic may be needed to pass data between

clock domains while maintain timing information. Further, many JESD204C IP cores output 64 bits per clock cycle which may include

fractions of a sample (such as in JMODE 8) and therefore gearbox logic may be needed to transition to the desired sample rate.

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9.2.1.3 Application Curves

An example pulse measurement using the device is shown in Figure 9-2. The setup follows the example LiDAR

system requirements with a 5-ns pulse captured at 800 MSPS. The applied pulse has a rise and fall time of

approximately 1 ns. A sub-sampling technique is used to interpolate data points to form an equivalent 25.6

GSPS capture of the pulse for more accurate details and multiple capture averaging is used to suppress noise.

A negative DC bias is applied to the ADC to enable use of the full dynamic range of the ADC for unipolar pulses.

The pulse is spanning almost the full range of ADC codes. The extracted pulse parameters are given in Table

9-3. The analog front-end is not included in this measurement.

2500

2000

1500

1000

500

0

-500

-1000

-1500

-2000

-2500

0

1

2

3

4

5

6

7

8

9

10

Time (ns)

Figure 9-2. Measured Pulse using Sub-Sampling Technique for Equivalent 25.6 GSPS Measurement

Table 9-3. Extracted Pulse Parameters for Example LiDAR System

Measured Parameter

Rise Time (10-90%)

Fall Time (90-10%)

Measured Value

Units

ns

1.49

1.53

5.12

240

4032

787.5

0

ns

Pulse Width (50%)

ns

Equivalent Bandwidth⁽¹⁾

Peak Amplitude (Codes)

Peak Amplitude (Voltage)

DC Offset (Codes)

MHz

LSB

mV

LSB

mV

DC Offset (Voltage)

0

(1) The equivalent bandwidth is calculated from the extracted rise time measurement. The bandwidth is limited by a 1-ns transition time

converter used at the output of the pulse generator.

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9.3 Initialization Set Up

The device and JESD204 interface require a specific startup and alignment sequence. The general order of that

sequence is listed in the following steps.

1. Tie PLL_EN high to enable the PLL or low to disable the PLL. Tie PLLREF_SE high to use the SE_CLK

clock input (only valid if PLL_EN is high) or low to use CLK± clock input. Configure CLKCFG0 and

CLKCFG1 pins to provide the required clocks from ORC and ORD outputs, if used.

2. Power-up the device and wait until voltages are within the recommended supply voltage range. The PD pin

must be held low during power up and at all other times when PLLREFO, ORC or ORD clock outputs are

necessary for system operation, if used.

3. Apply a stable clock signal at the desired frequency to CLK± or SE_CLK depending on the state of the

PLLREF_SE input.

4. Reset the device using SOFT_RESET.

5. Verify device initialization is completed before continuing by reading INIT_DONE until a 1 is returned.

6. Program the C-PLL if the PLL is enabled (PLL_EN is set high). Skip to step 7 if the C-PLL is disabled

(PLL_EN is set low).

a. Program CPLL_RESET to 1 to reset the C-PLL.

b. Program VCO_BIAS to 0x4A to set the C-PLL VCO bias settings.

c. Program PLL_P_DIV, PLL_V_DIV and PLL_N_DIV to set the C-PLL dividers (see Converter PLL (C-

PLL)).

d. Program VCO_CAL_EN to 1 to enable VCO trim calibration or manually write the VCO trim

to VCO_FREQ_TRIM (and set VCO_CAL_EN to 0). Skip to step 6.e. if manually loading

VCO_FREQ_TRIM.

e. Program CPLL_RESET to 0 to start VCO calibration and enable the C-PLL

7. Program JESD_EN = 0 to stop the JESD204C state machine and allow setting changes.

8. Program CAL_EN = 0 to stop the calibration state machine and allow setting changes.

9. Program Low Power Operating Mode, if desired, according to the Low Power Mode and High Performance

Mode section.

10. Program the desired JMODE.

11. Program the desired KM1 value. KM1 = K–1. KM1 is only used if a JMODE is chosen that uses 8B/10B

encoding.

12. Program SYNC_SEL as needed. Choose SYNCSE single-ended input or TMSTP± differential inputs.

13. Configure device calibration settings as desired (see the CAL_CFG0 and CAL_CFG1 registers). Select

foreground or background calibration modes and offset calibration as needed.

14. Enable the TRIGOUT± clock output and configure the TRIGOUT output mode through the TRIGOUT_CTRL

register, if desired.

15. If the C-PLL is used (PLL_EN is high) then verify that VCO calibration has finished (read VCO_CAL_DONE)

and that the C-PLL is locked to the reference clock (read CPLL_LOCKED) before proceeding.

16. Program CAL_EN = 1 to enable the calibration state machine.

17. Enable over-range via OVR_EN and adjust settings if desired.

18. Program JESD_EN = 1 to re-start the JESD204C state machine and allow the link to restart.

19. Trigger a foreground calibration (if enabled) by setting CAL_SOFT_TRIG to 0 and then setting it back to 1.

Alternatively, choose to use the CALTRIG pin by setting CAL_TRIG_EN to 1 and then toggling the CALTRIG

pin low and then high. The CALSTAT pin and the FG_DONE register bit goes high to indicate that calibration

has finished.

20. For JMODEs that use 8B/10B encoding the JESD204C interface now operates in response to the applied

SYNC signal from the receiver (64B/66B does not use SYNC).

21. Data is valid when the JESD204C receiver finishes the initialization sequence (CGS and ILAS completes

for 8B/10B modes or locks to SYNC header in 64B/66B modes) and the CALSTAT pin is high (if

CAL_STATUS_SEL = 0) or FG_DONE is set to 1 to indicate that calibration is finished.

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10 Power Supply Recommendations

The device requires two different power-supply voltages. 1.9 V DC is required for the VA19, VPLL19 and VREFO

power buses and 1.1 V DC is required for the VA11 and VD11 power buses. VTRIG can be set to either 1.1 V or

1.9 V and the TRIGOUT± common mode voltage shifts accordingly.

The power-supply voltages must be low noise and provide the needed current to achieve rated device

performance. Certain supplies should be isolated from each other to prevent noise coupling into sensitive

supplies. Isolation is best performed using separate regulators for each supply, but this is often not possible

due to size and cost constraints. At a minimum a PI-type power supply filtering scheme should be used which

includes a low-DC resistance ferrite bead (FB) with low-inductance decoupling capacitors on each side of the

ferrite bead. These are demonstrated in the example power supply architectures drawings in Figure 10-1 and

Figure 10-2.

There are two recommended power supply architectures:

1. Step down using high-efficiency switching converters, followed by a second stage of regulation to provide

switching noise reduction and improved voltage accuracy as shown in Figure 10-1.

2. Directly step down the final ADC supply voltage using high-efficiency switching converters as shown in

Figure 10-2. This approach provides the best efficiency, but care must be taken to minimize the switching

noise preventing degraded ADC performance. In general, operate the DC/DC switching regulators in fixed-

frequency mode at a high switching frequency to allow design of better power supply filtering networks and

reduce low frequency noise that may not be able to be filtered.

The WEBENCH® Power Designer can be used to select and design the individual power supply elements as

needed.

Recommended switching regulators include the TPS62913, TPS62912, TPS62085 and similar devices.

Recommended Low Drop-Out (LDO) linear regulators include the TPS7A8400, TPS7A7200, TPS7A54 and

similar devices.

For the switcher only approach, the ripple filter must be designed to provide sufficient filtering at the switching

frequency of the DC-DC converter and harmonics of the switching frequency. Make a note of the switching

frequency reported from WEBENCH® and design the EMI filter and capacitor combination to have the filter

cutoff frequency set as needed. Each application has different tolerance for noise on the supply voltage and the

impact to performance so strict ripple requirements are not provided. In general, the supply voltage must stay

within the recommended operating conditions limits during all ripple and transient events. Any supply filtering

must account for potential current transients, specifically when using low-power background calibration (see

Low-Power Background Calibration (LPBG) Mode).

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DC/DC Filter and Bulk Capacitance

Bulk Capacitance

Local Filtering

VA19

3.3 V - 12 V

2.2 V

1.9 V

Buck

LDO

Inductor

FB

47 ꢀF 10 ꢀF 10 ꢀF

47 ꢀF 10 ꢀF

10 ꢀF 0.1 ꢀF

+

œ

Power

Good

GND

Local Filtering

VPLL19

FB

10 ꢀF 0.1 ꢀF

GND

VREFO

Local Filtering

FB

10 ꢀF 0.1 ꢀF

GND

DC/DC Filter and Bulk Capacitance

Bulk Capacitance

Local Filtering

1.4 V

VA11

1.1 V

Buck

LDO

Inductor

FB

47 ꢀF 10 ꢀF 10 ꢀF

47 ꢀF 10 ꢀF

10 ꢀF 0.1 ꢀF

GND

Local Filtering

VD11

FB

10 ꢀF 0.1 ꢀF

GND

VTRIG

Local Filtering

FB

10 ꢀF 0.1 ꢀF

GND

FB = ferrite bead filter.

Figure 10-1. LDO Linear Regulator Approach Example

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DC/DC Filter and Bulk Capacitance

Local Filtering

FB

3.3 V - 12 V

1.9 V

VA19

Buck

Inductor

47 ꢀF 10 ꢀF 10 ꢀF

10 ꢀF 0.1 ꢀF

+

œ

Power

Good

GND

Local Filtering

VPLL19

FB

10 ꢀF 0.1 ꢀF

GND

VREFO

Local Filtering

FB

10 ꢀF 0.1 ꢀF

GND

DC/DC Filter and Bulk Capacitance

Local Filtering

1.1 V

VA11

Buck

Inductor

FB

47 ꢀF 10 ꢀF 10 ꢀF

10 ꢀF 0.1 ꢀF

GND

Local Filtering

VD11

FB

10 ꢀF 0.1 ꢀF

GND

VTRIG

Local Filtering

FB

10 ꢀF 0.1 ꢀF

GND

FB = ferrite bead filter.

Figure 10-2. Switcher-Only Approach Example

10.1 Power Sequencing

The 1.1-V supplies (VA11, VD11) must not be more than 0.5 V above any of the 1.9-V supplies (VA19, VPLL19,

VREFO) or VTRIG (1.1 V or 1.9 V) during power up, normal operation or power down. Further, all 1.9 V supplies

should be within 0.5 V of each other at all times. VTRIG can be ramped with either the 1.9-V supplies or 1.1-V

supplies, but must not be less than 0.5 V below VA11 or VD11 at any time. There is no sequencing requirement

between VA11 and VD11.

The general recommendation is to have all 1.9-V supplies share a regulator. VTRIG is generally either 1.1 V or

1.9 V and should share a regulator with supplies of the same voltage. The sequencing requirement can then

generally be met by tying the power good output of the 1.9-V regulator to the 1.1-V regulator(s). This specifies

that the 1.1-V supplies are enabled after the 1.9-V supplies have come up (power is good) and that the 1.9-V

supplies are always greater than the 1.1-V supplies on power up. During power down as soon as the 1.1-V

supplies drop out of regulation then the 1.9-V supplies are disabled. The ramp rates must be designed such that

the 1.9-V supplies never dip more than 0.5 V below the VA11 or VD11 supply.

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11 Layout

11.1 Layout Guidelines

There are many critical signals that require specific care during board design:

1. Analog input signals

2. CLK, SE_CLK and SYSREF

3. JESD204C data outputs

4. Power connections

5. Ground connections

The analog input signals, clock signals and JESD204C data outputs must be routed for excellent signal quality

at high frequencies, but should also be routed for maximum isolation from each other. Use the following general

practices:

1. Route using loosely coupled 100-Ω differential traces when possible. This routing minimizes impact of

corners and length-matching serpentines on pair impedance. SE_CLK should be routed as a coplanar

waveguide or as a stripline on an internal layer with sufficient via-fencing to prevent coupling.

2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential

traces. Tightly coupled differential traces may be used to reduce self-radiated noise or to improve

neighboring trace noise immunity when adequate spacing cannot be provided.

3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground

plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or

poorly connected ground pours.

4. Use smoothly radiused corners. Avoid 45- or 90-degree bends to reduce impedance mismatches.

5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these

locations. Cut-out below the landing pads on one or multiple ground planes to achieve a pad size or stackup

height that achieves the needed 50-Ω, single-ended impedance.

6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in

the ground plane or ground plane clearances associated with power and signal vias and through-hole

component leads.

7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias at an appropriate

spacing as determined by the maximum frequency the trace transports (<< λ_MIN/8).

8. When high-speed signals must transition to another layer using vias, transition as far through the board as

possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is

not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place ground vias close to the

signal vias when transitioning between layers to provide a nearby ground return path.

Pay particular attention to potential coupling between JESD204C data output routing and the analog input

routing. Switching noise from the JESD204C outputs can couple into the analog input traces and show up as

wideband noise due to the high input bandwidth of the ADC. Ideally, route the JESD204C data outputs on a

separate layer from the ADC input traces to avoid noise coupling (not shown in the Layout Example section).

Tightly coupled traces can also be used to reduce noise coupling.

Impedance mismatch between the CLK± input pins and the clock source can result in reduced amplitude of the

clock signal at the ADC CLK± pins due to signal reflections or standing waves. A reduction in the clock amplitude

may degrade ADC noise performance, especially at high input frequencies. To avoid this, keep the clock source

close to the ADC (as shown in the Layout Example section) or implement impedance matching at the ADC CLK±

input pins.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to

fabrication. Insertion loss, return loss, and time domain reflectometry (TDR) evaluations should be done.

The power and ground connections for the device are also very important. These rules must be followed:

1. Provide low-resistance connection paths to all power and ground pins.

2. Use multiple power layers if necessary to access all pins.

3. Avoid narrow isolated paths that increase connection resistance.

4. Use a signal-ground-power board stackup to maximum capacitance between the ground and power planes.

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11.2 Layout Example

Figure 11-1 to Figure 11-3 provide examples of the critical traces routed on the device evaluation module (EVM).

Figure 11-1. Top Layer Routing: Analog Inputs (INA±, INB±, INC±, IND±), TMSTP± and D[3:0]± Routing

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Figure 11-2. GND1 Cutouts to Optimize Impedance of Component Pads

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Figure 11-3. Bottom Layer Routing: CLK±, SYSREF and D[7:4]± Routing

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12 Device and Documentation Support

12.1 Device Support

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

AAV0144A

FCBGA - 1.94 mm max height

SCALE 1.400

BALL GRID ARRAY

10.15

9.85

A

B

BALL A1 CORNER

10.15

9.85

(

8)

(0.68)

1.94 MAX

(0.5)

C

SEATING PLANE

NOTE 4

BALL TYP

0.405

0.325

TYP

0.1 C

8.8 TYP

SYMM

(0.6) TYP

0.8 TYP

M

L

K

J

H

G

F

SYMM

8.8

TYP

E

D

C

B

A

0.51

0.41

C A B

NOTE 3

144X

0.15

0.08

C

1

2

3

4

5

6

7

8

9

10

11

12

0.8 TYP

4219578/B 01/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.

4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.

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EXAMPLE BOARD LAYOUT

AAV0144A

FCBGA - 1.94 mm max height

BALL GRID ARRAY

(0.8) TYP

1

3

5

6

7

8

9

10 11

4

12

2

A

B

(0.8) TYP

C

D

E

F

144X ( 0.4)

SYMM

G

H

J

K

L

M

SYMM

LAND PATTERN EXAMPLE

SCALE:8X

(

0.4)

0.05 MAX

METAL UNDER

SOLDER MASK

0.05 MIN

METAL

(

0.4)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219578/B 01/2020

NOTES: (continued)

5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

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EXAMPLE STENCIL DESIGN

AAV0144A

FCBGA - 1.94 mm max height

BALL GRID ARRAY

144X ( 0.4)

10 11

(0.8) TYP

1

3

5

6

7

8

9

4

12

2

A

B

(0.8)

TYP

C

D

E

F

SYMM

G

H

J

K

L

M

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.15 mm THICK STENCIL

SCALE:8X

4219578/B 01/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC12SJ800-Q1
厂家：	TEXAS INSTRUMENTS
描述：	ADC12xJ800 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface
文件：	总151页 (文件大小：6801K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC12SJ800-Q1 [TI]

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