ADC14155W-MPR [TI]
耐辐射加固保障 (RHA)、QMLV、300krad、陶瓷、14 位、单通道、155MSPS ADC | NBA | 48 | 25 to 25;
| 型号： | ADC14155W-MPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 耐辐射加固保障 (RHA)、QMLV、300krad、陶瓷、14 位、单通道、155MSPS ADC | NBA | 48 | 25 to 25 |
| 文件： | 总35页 (文件大小：1199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
ADC14155QML-SP 耐辐射、14 位、155MSPS、1.1GHz 带宽模数转换器
1 特性
3 说明
1
•
5962R0626201VXC
ADC14155QML-SP 是一款高性能 CMOS 模数转换
器，能够以高达 155MSPS 的速率将模拟输入信号转
换为 14 位数字字。该转换器使用具有数字纠错功能的
差分流水线架构和片上采样保持电路，以最大程度地降
低功耗并减少外部组件数，同时提供出色的动态性能。
独特的采样保持级能够产生 1.1GHz 的全功率带宽。
ADC14155 由 3.3V 和 1.8V 双电源供电，以
–
–
总电离剂量 (TID) 为 100krad(Si)
单粒子闩锁为 120MeV-cm2/mg
（请参阅辐射报告）
•
•
•
•
•
•
•
•
•
•
•
1.1GHz 全功率带宽
内部采样保持电路
低功耗
内部精密 1V 基准
155MSPS 的速率消耗 967mW 的功率。
单端或差分时钟模式
数据就绪输出时钟
用于数字输出接口的 1.8V 独立电源能够实现更低的功
耗和更低的噪声。断电功能可以在禁用时钟输入的情况
下将功耗降至 5mW，同时仍能快速唤醒至全功能运
行。差分输入可提供等于基准电压 2 倍的满标量程差
分输入摆幅。提供了稳定的 1V 内部电压基准，也可以
通过外部基准运行 ADC14155。可通过引脚选择时钟
模式（差分与单端）和输出数据格式（偏移二进制与二
进制补码）。占空比稳定器可在各种时钟占空比上维持
性能。
时钟占空比稳定器
由 3.3V 和 1.8V 双电源供电 (±10%)
断电模式
偏移二进制或二进制补码输出数据格式
48 引脚 CFP 封装（11.5mm ×
11.5mm，0.635mm 引脚间距）
•
主要规格
–
–
–
–
–
–
–
分辨率：14 位
ADC14155QML-SP 采用 48 引线热增强型多层陶瓷四
方封装，可以在 –55°C 至 +125°C 的军用温度范围内
运行。
转换速率：155MSPS
SNR (fIN = 70MHz) 70.1dBFS（典型值）
SFDR (fIN = 70MHz) 82.3dBFS（典型值）
ENOB (fIN = 70MHz) 11.3 位（典型值）
全功率带宽：1.1GHz（典型值）
功耗：967mW（典型值）
器件信息(1)
器件型号
等级
QMLV RHA（SMD 器件）
[100krad]
封装
5962R0626201VXC
CQFP (48)
2 应用
飞行 RHA（非 SMD 器件）
[100krad]
工程样片(2)
ADC14155W-MLS
CQFP (48)
•
•
•
•
•
•
高中频 (IF) 采样接收器
ADC14155W-MPR
ADC14155LCVAL
ADC14155HCVAL
CQFP (48)
功率放大器线性化
多载波、多模式接收器
测试和测量设备
通信仪器仪表
低频陶瓷评估板
高频陶瓷评估板
—
—
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
雷达系统
(2) 这些部件仅适用于工程评估。部件按照不合规的流程进行加工
处理。这些部件不适用于质检、生产、辐射测试或飞行。这些
零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围内或
运行寿命中保证其性能。
框图
INTERNAL
REFERENCE
V
REF
V
RP
V
RM
V
RN
14
D0 - D13
OVR
V
+
IN
14BIT HIGH SPEED
PIPELINE ADC
DIGITAL
CORRECTION
SHA
V
-
IN
DRDY
CLK+
CLK-
CLOCK/DUTY CYCLE
STABILIZER
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS378
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
目录
Performance............................................................. 15
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 18
7.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 24
8.3 Radiation Environments.......................................... 25
Power Supply Recommendations...................... 26
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
7
8
9
6.5 ADC14155 Converter Electrical Characteristics DC
Parameters................................................................. 7
10 Layout................................................................... 27
10.1 Layout Guidelines ................................................. 27
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 29
11.1 器件支持 ............................................................... 29
11.2 接收文档更新通知 ................................................. 30
11.3 社区资源................................................................ 30
11.4 商标....................................................................... 30
11.5 静电放电警告......................................................... 30
11.6 术语表 ................................................................... 30
12 机械、封装和可订购信息....................................... 30
6.6 ADC14155 Converter Electrical Characteristics
(Continued) DYNAMIC Parameters(1) ....................... 8
6.7 ADC14155 Converter Electrical Characteristics
(Continued) Logic and Power Supply Electrical
Characteristics(1)...................................................... 10
6.8 ADC14155 Converter Electrical Characteristics
(Continued) Timing and AC Characteristics(1)......... 11
6.9 Timing Diagram....................................................... 12
6.10 Transfer Characteristic.......................................... 12
6.11 Typical Performance Characteristics, DNL, INL ... 14
6.12 Typical Performance Characteristics, Dynamic
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision K (September 2018) to Revision L
Page
•
Added Figure 20 .................................................................................................................................................................. 17
Changes from Revision J (March 2018) to Revision K
Page
•
•
•
•
•
Deleted inconsistent footnotes ............................................................................................................................................... 6
Added standardized thermal values ....................................................................................................................................... 6
Changed formatting of temperature conditions in the spec tables......................................................................................... 7
Added subgroups to all applicable specs .............................................................................................................................. 7
Changed location of 12.1-Ω capacitor on VIN- pin in the circuit diagram of the Typical Application section......................... 24
Changes from Revision I (March 2013) to Revision J
Page
•
•
已添加 添加了器件信息 表、ESD 额定值表、特性 说明部分，器件功能模式部分，应用和实施部分，电源相关建议部
分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分 ................................................................................ 1
Deleted DYNAMIC CONVERTER CHARACTERISTICS, AIN = –1 dBFS duplicate specs.................................................... 9
2
Copyright © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
5 Pin Configuration and Functions
NBA Package
48-Pin CFP
Top View
AGND
VA
1
36
35
34
33
32
31
30
29
28
27
26
25
VDR
DRGND
DRDY
OVR
D13 (MSB)
D12
2
AGND
VINœ×
3
4
VIN+
5
AGND
PD
6
Thermal
Pad
7
D11
CLK_SEL/DF
VA
8
D10
9
D9
AGND
CLK+
10
11
12
D8
VDR
VDR
CLKœ
Not to scale
Copyright © 2008–2019, Texas Instruments Incorporated
3
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
Pin Descriptions and Equivalent Circuits
PIN NO.
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
ANALOG I/O
VA
4
5
VIN–
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, VCM
.
VIN+
AGND
42, 43
VRP
VA
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1-µF capacitor placed very close to
the pin to minimize stray inductance. A 0.1-µF capacitor should be
placed between VRP and VRN as close to the pins as possible, and a
10-µF capacitor should be placed in parallel.
VRP and VRN should not be loaded. VRM may be loaded to 1mA for
use as a temperature stable 1.5-V reference.
It is recommended to use VRM to provide the common mode voltage,
VCM, for the differential analog inputs, VIN+ and VIN–.
VRM
VA
VREF
VRN
46, 47
44, 45
VRM
VA
VRP
VRN
AGND
V
A
This pin can be used as either the 1-V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, VREF should be decoupled to AGND
with a 0.1-µF, low equivalent series inductance (ESL) capacitor. In
this mode, VREF defaults as the output for the internal 1.0-V
reference.
I
DC
48
VREF
To use an external reference, overdrive this pin with a low noise
external reference voltage. The output impedance of the internal
reference at this pin is 9kΩ. Therefore, to overdrive this pin, the
impedance of the external reference source should be << 9 kΩ.
This pin should not be used to source or sink current.
AGND
The full scale differential input voltage range is 2 * VREF
.
DIGITAL I/O
V
A
The clock input pins can be configured to accept either a single-
ended or a differential clock input signal.
When the single-ended clock mode is selected through CLK_SEL/DF
(pin 8), connect the clock input signal to the CLK+ pin and connect
the CLK– pin to AGND.
When the differential clock mode is selected through CLK_SEL/DF
(pin 8), connect the positive and negative clock inputs to the CLK+
and CLK– pins, respectively.
11
CLK+
CLK–
The analog input is sampled on the falling edge of the clock input.
12
AGND
4
Copyright © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
PIN NO.
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
Pin Descriptions and Equivalent Circuits (continued)
SYMBOL
EQUIVALENT CIRCUIT
DESCRIPTION
This is a four-state pin controlling the input clock mode and output
data format.
CLK_SEL/DF = VA, CLK+ and CLK– are configured as a differential
clock input. The output data format is 2's complement.
CLK_SEL/DF = (2 / 3) * VA, CLK+ and CLK– are configured as a
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1 / 3) * VA, CLK+ is configured as a single-ended
clock input and CLK– should be tied to AGND. The output data
format is 2's complement.
V
A
8
CLK_SEL/DF
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK– should be tied to AGND. The output data format is
offset binary.
This is a two-state input controlling Power Down.
PD = VA, Power Down is enabled. In the Power Down state only the
reference voltage circuitry remains active and power dissipation is
reduced.
AGND
7
PD
PD = AGND, Normal operation.
Digital data output pins that make up the 14-bit conversion result. D0
(pin 17) is the LSB, while D13 (pin 32) is the MSB of the output
word. Output levels are CMOS compatible.
V
V
A
DR
17-24,
27-32
D0–D13
OVR
Over-Range Indicator. This output is set HIGH when the input
amplitude exceeds the 14-bit conversion range (0 to 16383).
33
Data Ready Strobe. This pin is used to clock the output data. It has
the same frequency as the sampling clock. One word of data is
output in each cycle of this signal. The rising edge of this signal
should be used to capture the output data.
34
DRDY
DRGND
DGND
ANALOG POWER
Positive analog supply pins. These pins should be connected to a
quiet 3.3-V source and be bypassed to AGND with 100-pF and 0.1-
µF capacitors located close to the power pins.
2, 9, 37, 40,
41
VA
1, 3, 6, 10,
38, 39
AGND
The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to a quiet
3.3-V source and be bypassed to DGND with a 100-pF and 0.1-µF
capacitor located close to the power pin.
13
14
VD
DGND
The ground return for the digital supply.
Positive driver supply pin for the output drivers. This pin should be
connected to a quiet voltage source of 1.8 V and be bypassed to
DRGND with 100-pF and 0.1-µF capacitors located close to the
power pins.
16, 25, 26,
36
VDR
The ground return for the digital output driver supply. These pins
should be connected to the system digital ground. See Layout
Guidelines (Layout and Grounding) for more details.
15, 35
DRGND
Copyright © 2008–2019, Texas Instruments Incorporated
5
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
–0.3
–0.3
MAX
4.2
UNIT
V
Supply voltage (VA, VD)
Supply voltage (VDR
)
2.35
100
V
|VA–VD|
mV
V
Voltage on any input pin (not to exceed 4.2 V)
Voltage on any output pin (not to exceed 2.35 V)
Input current at any pin other than supply pins
Package input current
–0.3
–0.3
–5
VA + 0.3
VDR + 0.2
5
V
mA
mA
°C
°C
–50
50
Max junction temperature, TJ
150
Storage temperature, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0 V, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–55
3
NOM
MAX
125
UNIT
°C
V
Operating temperature
Supply voltage (VA, VD)
Output driver supply (VDR
CLK
3.6
)
1.6
2
V
–0.05
30%
0
VA + 0.05
70%
2.6
V
Clock duty cycle
Analog input pins
VCM
V
V
1.4
1.6
|AGND-DGND|(2)
100
mV
(1) All voltages are measured with respect to GND = AGND = DGND = DRGND = 0 V, unless otherwise specified.
(2) All GND voltages should be within 100mv of each other.
6.4 Thermal Information
ADC14155QML
NBA (CFP)
THERMAL METRIC
UNIT
48 PINS
27.5
11.7
11.4
4.6
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
11.1
3.0
(1)
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
6.5 ADC14155 Converter Electrical Characteristics DC Parameters(1)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
(2)(3)(4)(5)
Binary Format. Typical values are for TA = 25°C.
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
NOTES
TYP(6)
MIN
MAX
UNITS
STATIC CONVERTER CHARACTERISTICS
Resolution with no missing
codes
14
Bits
[1, 2, 3]
INL
Integral non linearity
See(7)
2.3
–5.0
–0.9
5.0
1.1
LSB
LSB
[1, 2, 3]
[1, 2, 3]
DNL
Differential non linearity
±0.5
Maximum positive gain
error
PGE
NGE
0.1
0.3
–3.3
–3.3
3.5
3.9
%FS
%FS
[1, 2, 3]
[1, 2, 3]
Maximum negative gain
error
TC GE
VOFF
Gain error tempco
–55°C ≤ TA ≤ +125°C
–55°C ≤ TA ≤ +125°C
0.007
–0.1
Δ%FS/°C
%FS
Offset error (VIN+ = VIN–
)
0.7
0
–0.9
[1, 2, 3]
TC VOFF Offset error tempco
Under range output code
Over range output code
0.0001
0
Δ%FS/°C
0
16383 16383
16383
REFERENCE AND ANALOG INPUT CHARACTERISTICS
Common mode input
voltage
VCM
1.5
1.5
9
V
V
Reference ladder midpoint
output voltage
VRM
Output load = 1 mA
VIN = 1.5 Vdc ± 0.5 V(CLK
LOW)
See(8)
pF
pF
VIN input capacitance
(each pin to GND)
CIN
VIN = 1.5 Vdc ± 0.5 V(CLK
HIGH)
See(8)
See(9)
6
VREF
Reference voltage
1.00
9
V
Reference input resistance
kΩ
(1) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-
STD-883, Test Method 1019.
(2) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described
in the Recommended Operating Conditions section.
VA
I/O
To Internal Circuitry
AGND
(3) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(4) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
(5) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50-mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(6) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(7) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through
positive and negative full-scale.
(8) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
(9) Optimum performance will be obtained by keeping the reference input in the 0.9-V to 1.1-V range. The LM4051CIM3-ADJ (SOT-23
package) is recommended for external reference applications.
Copyright © 2008–2019, Texas Instruments Incorporated
7
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
6.6 ADC14155 Converter Electrical Characteristics (Continued) DYNAMIC Parameters(1)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
(2)(3)(4)(5)
Binary Format. Typical values are for TA = 25°C.
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
NOTES
TYP(6)
MIN
MAX
UNITS
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1 dBFS
FPBW
SNR
Full power bandwidth
Signal-to-noise ratio
-1 dBFS Input, -3 dB Corner
fIN = 10 MHz
1.1
69
GHz
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
fIN = 70 MHz
70.1
68.5
68.5
66.4
82
66.7
[4, 5, 6]
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
fIN = 10 MHz
fIN = 70 MHz
82.3
80.5
77.3
63.5
11.3
11.3
11.0
11.0
10.0
–81
68.2
10.7
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
[4, 5, 6]
Spurious free dynamic
range
SFDR
ENOB
THD
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
fIN = 10 MHz
fIN = 70 MHz
Bits
Effective number of bits
Total harmonic disortion
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
fIN = 10 MHz
Bits
Bits
Bits
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
fIN = 70 MHz
–79.9
–82.4
–76.6
–63.2
–95.4
–88.5
–88.3
–77.3
–60.9
–67
–70
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
fIN = 10 MHz
fIN = 70 MHz
Second-order harmonic
distortion
HD2
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
(1) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-
STD-883, Test Method 1019.
(2) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described
in the Recommended Operating Conditions section.
VA
I/O
To Internal Circuitry
AGND
(3) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(4) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
(5) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(6) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
8
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ADC14155 Converter Electrical Characteristics (Continued) DYNAMIC Parameters(1) (continued)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
(2)(3)(4)(5)
Binary Format. Typical values are for TA = 25°C.
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
NOTES
TYP(6)
MIN
MAX
UNITS
fIN = 10 MHz
–81.6
–82.3
–86.4
–89.0
–80.5
68.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
fIN = 70 MHz
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 169 MHz
fIN = 238 MHz
fIN = 398 MHz
–68
[4, 5, 6]
Third-order harmonic
distortion
HD3
69.9
66.2
[4, 5, 6]
Signal-to-noise and
distortion ratio
SINAD
68.3
67.8
61.5
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6.7 ADC14155 Converter Electrical Characteristics (Continued) Logic and Power Supply
Electrical Characteristics(1)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
(2)(3)(4)(5)
Binary Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude.
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
NOTES
TYP(6)
MIN
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS (CLK, PD/DCS, CLK_SEL/DF)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
CIN
Logical “1” input voltage
Logical “0” input voltage
Logical “1” input current
Logical “0” input current
Digital input capacitance
VD = 3.6 V
VD = 3.0 V
VIN = 3.3 V
VIN = 0 V
See(7)
2.0
V
[1, 2, 3]
[1, 2, 3]
0.8
V
10
–10
5
µA
µA
pF
DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY, OVR)
VOH
VOL
Output logic high
Output logic low
IOUT = –0.5 mA , VDR = 1.8 V
IOUT = 1.6 mA, VDR = 1.8 V
See(7)
See(7)
1.55
0.15
1.2
V
V
[1, 2, 3]
[1, 2, 3]
0.4
Output short circuit source
current
+ISC
VOUT = 0 V
VOUT = VDR
–10
mA
Output short circuit sink
current
–ISC
10
5
mA
pF
COUT
Digital output capacitance
POWER SUPPLY CHARACTERISTICS
IA
Analog supply current
Digital supply current
Full operation
Full operation
283
10
350
11
mA
mA
mA
mW
[1, 2, 3]
[1, 2, 3]
ID
IDR
Digital output supply current Full operation
See(8)
15
Power consumption
Excludes IDR
967
1170
[1, 2, 3]
Power down power
consumption
Clock disabled
5
mW
(1) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-
STD-883, Test Method 1019.
(2) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described
in the Recommended Operating Conditions section.
VA
I/O
To Internal Circuitry
AGND
(3) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(4) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
(5) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50-mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(6) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(7) Specified by characterization.
(8) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR(C0 × f0 + C1 × f1 +....C11
× f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at
which that pin is toggling.
10
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6.8 ADC14155 Converter Electrical Characteristics (Continued) Timing and AC
Characteristics(1)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for TA = 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface
limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C(2)(3)(4)(5)
SUB-
GROUPS
PARAMETER
TEST CONDITIONS
NOTES
TYP(6)
MIN
MAX
UNITS
Maximum clock frequency
Minimum clock frequency
Clock high time
155
MHz
MHz
ns
[7, 8A, 8B]
5
3.0
3.0
Clock low time
ns
Clock
cycles
Conversion latency
See(7)
8
[4, 5, 6]
Output delay of CLK to
DATA
tOD
Relative to falling edge of CLK
2.0
ns
tSU
tH
tAD
tAJ
Data output setup time
Data output hold time
Aperture delay
Relative to DRDY
Relative to DRDY
See(8)
See(8)
2.1
2.1
1.22
1.83
ns
ns
0.5
ns
Aperture jitter
0.08
ps rms
0.1 µF to GND on pins 43, 44;
10 µF and 0.1 µF between
pins 43, 44; 0.1 µF and 10 µF
to GND on pins 47, 48
Power down recovery time
3.0
ms
(1) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-
STD-883, Test Method 1019.
(2) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described
in the Recommended Operating Conditions section.
VA
I/O
To Internal Circuitry
AGND
(3) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(4) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
(5) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
(6) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(7) Specified by design.
(8) Specified by characterization.
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6.9 Timing Diagram
Sample N + 9
Sample N + 8
Sample N + 7
Sample N
Sample N + 10
Sample N + 11
V
IN
t
AD
1
f
Clock N
Clock N + 8
CLK
90%
10%
90%
10%
CLK
t
t
CH
CL
t
f
t
r
Latency
t
OD
DRDY
t
t
H
SU
D0 - D13
Data N + 1
Data N + 2
Data N - 1
Data N
Figure 1. Output Timing
6.10 Transfer Characteristic
Figure 2. Transfer Characteristic
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Transfer Characteristic (continued)
Table 1. Quality Conformance Inspection(1)
Subgroup
Description
Static tests at
Temp (°C)
25
1
2
Static tests at
125
–55
25
3
Static tests at
4
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
5
125
–55
25
6
7
8A
8B
9
125
–55
25
10
11
125
–55
(1) MIL-STD-883, Method 5005 - Group A
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6.11 Typical Performance Characteristics, DNL, INL
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for TA = 25°C.(1)(2)(3)
Figure 3. DNL
Figure 4. INL
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per Note 5. However, errors in the A/D conversion can occur if the input goes above 2.6 V or below GND as described
in the Recommended Operating Conditions section.
VA
I/O
To Internal Circuitry
AGND
(2) To ensure accuracy, it is required that |VA – VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3) With the test condition for VREF = 1 V (2-VP-P differential input), the 14-bit LSB is 122.1 µV.
14
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6.12 Typical Performance Characteristics, Dynamic Performance
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for TA = 25°C
Figure 5. SFDR vs fIN
Figure 6. SNR vs fIN
Figure 8. Distortion vs fIN
Figure 10. Distortion vs VA
Figure 7. SNR, SINAD, SFDR vs fIN
Figure 9. SNR, SINAD, SFDR vs VA
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Typical Performance Characteristics, Dynamic Performance (continued)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for TA = 25°C
Figure 11. SNR, SINAD, SFDR vs VDR
Figure 12. Distortion vs VDR
Figure 13. SNR, SINAD, SFDR vs VREF
Figure 14. Distortion vs VREF
Figure 15. SNR, SINAD, SFDR vs Temperature
Figure 16. Distortion vs Temperature
16
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Typical Performance Characteristics, Dynamic Performance (continued)
Unless otherwise specified, the following specifications apply: AGND = DGND = DRGND = 0 V, VA = VD = 3.3 V, VDR = 1.8 V,
Internal VREF = 1 V, fCLK = 155 MHz, VCM = VRM, CL = 5 pF/pin, Differential Analog Input, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for TA = 25°C
Figure 17. Spectral Response at 70-MHz Input
Figure 18. Spectral Response at 169-MHz Input
1000
900
800
700
600
500
400
300
200
100
0
0
50
100
150
200
Fs (MHz)
P2o0w19e
Figure 19. Spectral Response at 238-MHz Input
Figure 20. Power vs Sample Rate
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7 Detailed Description
7.1 Overview
Operating on dual 3.3-V and 1.8-V supplies, the ADC14155 digitizes a differential analog input signal to 14 bits,
using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to
ensure maximum performance.
The user has the choice of using an internal 1-V stable reference, or using an external reference. The ADC14155
will accept an external reference between 0.9 V and 1.1 V (1-V recommended) which is buffered on-chip to ease
the task of driving that pin. The 1.8-V output driver supply reduces power consumption and decreases the noise
at the output of the converter.
The quad state function pin CLK_SEL/DF (pin 8) allows the user to choose between using a single-ended or a
differential clock input and between offset binary or 2's complement output data format. The digital outputs are
CMOS compatible signals that are clocked by a synchronous data ready output signal (DRDY, pin 34) at the
same rate as the clock input. For the ADC14155 the clock frequency can be between 5 MSPS and 155 MSPS
with fully specified performance at 155 MSPS. The analog input is acquired at the falling edge of the clock and
the digital data for a given sample is output on the falling edge of the DRDY signal and is delayed by the pipeline
for 8 clock cycles. The data should be captured on the rising edge of the DRDY signal.
Power-down is selectable using the PD pin (pin 7). A logic high on the PD pin disables everything except the
voltage reference circuitry and reduces the converter power consumption to 5 mW with no clock running. For
normal operation, the PD pin should be connected to the analog ground (AGND). A duty cycle stabilizer
maintains performance over a wide range of clock duty cycles.
7.2 Functional Block Diagram
INTERNAL
REFERENCE
V
REF
V
RP
V
RM
V
RN
14
D0 - D13
OVR
V
+
IN
14BIT HIGH SPEED
PIPELINE ADC
DIGITAL
CORRECTION
SHA
V
-
IN
DRDY
CLK+
CLK-
CLOCK/DUTY CYCLE
STABILIZER
7.3 Feature Description
7.3.1 Analog Inputs
7.3.1.1 Differential Analog Input Pins
The ADC14155QML-SP has one pair of analog signal input pins, VIN+ and VIN–, which form a differential input
pair. The input signal, VIN, is defined as
VIN = (VIN+) – (VIN–
)
(1)
Figure 21 shows the expected input signal range. Note that the common mode input voltage, VCM, should be 1.5
V. Using VRM (pin 46 or 47) for VCM will ensure the proper input common mode level for the analog input signal.
The peaks of the individual input signals should each never exceed 2.6 V. Each analog input pin of the
differential pair should have a peak-to-peak voltage equal to the reference voltage, VREF, be 180° out of phase
with each other and be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not
exceed the value of the reference voltage or the output data will be clipped.
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Feature Description (continued)
Figure 21. Expected Input Signal Range
For single frequency sine waves the full scale error, EFS, in LSB can be described as approximately
EFS = 16384 ( 1 – sin (90° + dev))
(2)
Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship
to each other (see Figure 22). For single frequency inputs, angular errors result in a reduction of the effective full
scale input. For complex waveforms, however, angular errors will result in distortion.
Figure 22. Angular Errors Between The Two Input Signals Will Reduce The Output Level Or Cause
Distortion
It is recommended to drive the analog inputs with a source impedance less than 100 Ω. Matching the source
impedance for the differential inputs will improve even ordered harmonic performance (particularly second
harmonic).
Table 2 indicates the input to output relationship of the ADC14155.
Table 2. Input To Output Relationship
VIN+
VIN–
Binary Output
2’s Complement Output
10 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
01 0000 0000 0000
01 1111 1111 1111
VCM – VREF / 2
VCM – VREF / 4
VCM
VCM + VREF / 2
VCM + VREF / 4
VCM
00 0000 0000 0000
01 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
11 1111 1111 1111
Negative Full-Scale
Mid-Scale
VCM + VREF / 4
VCM + VREF / 2
VCM – VREF / 4
VCM – VREF / 2
Positive Full-Scale
7.3.1.2 Driving The Analog Inputs
The VIN+ and the VIN– inputs of the ADC14155QML-SP have an internal sample-and-hold circuit which consists of
an analog switch followed by a switched-capacitor amplifier. The analog inputs are connected to the sampling
capacitors through NMOS switches, and each analog input has parasitic capacitances associated with it.
When the clock is high, the converter is in the sample phase. The analog inputs are connected to the sampling
capacitor through the NMOS switches, which causes the capacitance at the analog input pins to appear as the
pin capacitance plus the internal sample and hold circuit capacitance (approximately 9 pF). While the clock level
remains high, the sampling capacitor will track the changing analog input voltage. When the clock transitions
from high to low, the converter enters the hold phase, during which the analog inputs are disconnected from the
sampling capacitor. The last voltage that appeared at the analog input before the clock transition will be held on
the sampling capacitor and will be sent to the ADC core. The capacitance seen at the analog input during the
hold phase appears as the sum of the pin capacitance and the parasitic capacitances associated with the sample
and hold circuit of each analog input (approximately 6 pF). Once the clock signal transitions from low to high, the
analog inputs will be reconnected to the sampling capacitor to capture the next sample. Usually, there will be a
difference between the held voltage on the sampling capacitor and the new voltage at the analog input. This will
cause a charging glitch that is proportional to the voltage difference between the two samples to appear at the
analog input pin. The input circuitry must be fast enough to allow the sampling capacitor to fully charge before
the clock signal goes high again, as incomplete settling can degrade the SFDR performance.
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A single-ended to differential conversion circuit is shown in Figure 24. A transformer is preferred for high
frequency input signals. Terminating the transformer on the secondary side provides two advantages. First, it
presents a real broadband impedance to the ADC inputs and second, it provides a common path for the charging
glitches from each side of the differential sample-and-hold circuit.
One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed
to the ADC core.
The SFDR performance of the converter depends on the external signal conditioning circuity used, as this affects
how quickly the sample-and-hold charging glitch will settle. An external resistor and capacitor network as shown
in Figure 24 should be used to isolate the charging glitches at the ADC input from the external driving circuit and
to filter the wideband noise at the converter input. These filtering components should be placed close to the ADC
inputs in order to absorb the sampling glitches as close to the source of the glitches as possible. For Nyquist
applications the RC pole should be at the ADC sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should
be set at about 1.5 to 2 times the maximum input frequency to maintain a linear delay response.
7.3.1.3 Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 1.4 V to 1.6 V and be a value such that the
peak excursions of the analog signal do not go more negative than ground or more positive than 2.6 V. It is
recommended to use VRM (pin 46 or 47) as the input common mode voltage.
7.3.2 Reference Pins
The ADC14155QML-SP is designed to operate with an internal 1-V reference, or an external 1-V reference, but
performs well with external reference voltages in the range of 0.9 V to 1.1 V. The internal 1-V reference is the
default condition when no external reference input is applied to the VREF pin. If a voltage in the range of 0.9 V to
1.1 V is applied to the VREF pin, then that voltage is used for the reference. The VREF pin should always be
bypassed to ground with a 0.1-µF capacitor close to the reference input pin. Lower reference voltages will
decrease the signal-to-noise ratio (SNR) of the ADC14155. Increasing the reference voltage (and the input signal
swing) beyond 1.1-V may degrade THD for a full-scale input, especially at higher input frequencies.
It is important that all grounds associated with the reference voltage and the analog input signal make connection
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.
The Reference Bypass Pins (VRP, VRM, and VRN) are made available for bypass purposes. Each of these pins
should be bypassed to ground with a 0.1-µF capacitor. A 0.1-µF and a 10-µF capacitor should be placed
between the VRP and VRN pins, as shown in Figure 24. This configuration is necessary to avoid reference
oscillation, which could result in reduced SFDR and/or SNR. VRM may be loaded to 1 mA for use as a
temperature stable 1.5-V reference. The VRP and VRN pins should not be loaded.
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may
result in degraded noise performance. Loading any of these pins, other than VRM, may result in performance
degradation.
The nominal voltages for the reference bypass pins are as follows:
VRM = 1.5 V
VRP = VRM + VREF / 2
VRN = VRM – VREF / 2
7.3.3 Digital Inputs
Digital CMOS compatible inputs consist of CLK+, CLK–, PD and CLK_SEL/DF.
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7.3.3.1 Clock Inputs
The CLK+ and CLK– signals control the timing of the sampling process. The CLK_SEL/DF pin (pin 8) allows the
user to configure the ADC for either differential or single-ended clock mode (see Clock Mode Select/Data Format
(CLK_SEL/DF)). In differential clock mode, the two clock signals should be exactly 180° out of phase from each
other and of the same amplitude. In the single-ended clock mode, the clock signal should be routed to the CLK+
input and the CLK– input should be tied to AGND in combination with the correct setting from Table 4.
To achieve the optimum noise performance, the clock inputs should be driven with a stable, low jitter clock
signal. The clock input signal should also have a short transition region. This can be achieved by passing a low-
jitter sinusoidal clock source through a high speed buffer gate. This configuration is shown in Figure 24. The
trace carrying the clock signal should be as short as possible and should not cross any other signal line, analog
or digital, not even at 90°. Figure 24 shows the recommended clock input circuit.
The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.
This will limit the minimum sample rate.
The clock line should be terminated at its source in the characteristic impedance of that line. Care should be
taken to maintain a constant clock line impedance throughout the length of the line. Refer to Application Note
AN-905 (SNLA035) for information on setting characteristic impedance.
It is highly desirable that the source driving the ADC clock pins only drive that pin. However, if that source is
used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
(3)
where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it
as seen from the clock source. Typical tPD is about 150 ps/in (60 ps/cm) on FR-4 board material. The units of "L"
and tPD should be the same (inches or centimeters).
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC14155 has a Duty Cycle Stabilizer. It is designed to maintain performance over a
clock duty cycle range of 30% to 70%.
7.3.3.2 Power-Down (PD)
Power-down can be enabled through this two-state input pin. Table 3 shows how to power-down the ADC14155.
Table 3. Power Down Selection Table
PD Input Voltage
Power State
Power-down
On
VA
AGND
The power-down mode allows the user to conserve power when the converter is not being used. In the power-
down state all bias currents of the analog circuitry, excluding the reference are shut down which reduces the
power consumption to 5 mW with no clock running. The output data pins are undefined and the data in the
pipeline is corrupted while in the power-down mode.
The Power-down Mode Exit Cycle time is determined by the value of the capacitors on the VRP (pin 42, 43), VRM
(pin 46, 47) and VRN (pin 44, 45) reference bypass pins (pins 43, 44 and 45) and is approximately 3 ms with the
recommended component values. These capacitors lose their charge in the power-down mode and must be
recharged by on-chip circuitry before conversions can be accurate. Smaller capacitor values allow slightly faster
recovery from the power down mode, but can result in a reduction in SNR, SINAD and ENOB performance.
Copyright © 2008–2019, Texas Instruments Incorporated
21
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
7.3.3.3 Clock Mode Select/Data Format (CLK_SEL/DF)
Single-ended versus differential clock mode and output data format are selectable using this quad-state function
pin. Table 4 shows how to select between the clock modes and the output data formats.
Table 4. Clock Mode And Data Format Selection Table
CLK_SEL/DF Input Voltage
Clock Mode
Differential
Output Data Format
2's Complement
Offset Binary
VA
(2 / 3) * VA
(1 / 3) * VA
AGND
Differential
Single-Ended
Single-Ended
2's Complement
Offset Binary
7.4 Device Functional Modes
This devices has no specific functional modes.
22
Copyright © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition
region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree
shown in Figure 23. The gates used in the clock tree must be capable of operating at frequencies much higher
than those used if added jitter is to be prevented. Best performance will be obtained with a differential clock input
drive, compared with a single-ended drive.
As mentioned in Power Supply Recommendations, it is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal,
which can lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with
90° crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.
Figure 23. Isolating the ADC Clock From Other Circuitry With a Clock Tree
Copyright © 2008–2019, Texas Instruments Incorporated
23
ADC14155QML-SP
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www.ti.com.cn
8.2 Typical Application
+3.3 V from
Regulator
+3.3 V from
Regulator
+1.8 V from
Regulator
+1.8 V from
Regulator
+3.3 V from
Regulator
100 pF
x 3
100 pF
100 pF
x 4
100 pF
x 2
0.1 mF
0.1 mF
x 3
0.1 mF
x 6
100 pF
x 6
0.1 mF
x 2
0.1 mF
x 4
48
V
REF
22
34
DRDY
10 mF
0.1 mF
33
32
31
30
29
28
27
24
23
22
21
20
19
18
17
46
47
V
RM
OVR
V
(MSB) D13
D12
RM
10 mF
49.9
44
45
D11
10 mF
0.1 mF
0.1 mF
V
RN
V
0.1 mF
D10
RN
42
43
D9
V
V
RP
RP
D8
V
ADC14155
LC4032V-25TN48C
PLD
IN
Output
Word
0.1 mF
0.1 mF
0.1 mF
D7
D6
D5
1
12.1
12.1
4
5
V
IN
-
0.1 mF
V
IN
+
24.9
24.9
15 pF
D4
D3
7
8
PD
PD
CLK_SEL/DF
CLK_SEL/DF
D2
Flux XFMR: ADT1-1WT or ETC1-1T
Balun XFMR: ADT1-12 or ETC1-1-13
D1
11
12
(LSB) D0
CLK+
CLK-
V
A
CLK
IN
0.1 mF
1k
1k
24.9
1
NC7WV125K8X
High Speed Buffer
Figure 24. Application Circuit Using Transformer Drive Circuit
8.2.1 Design Requirements
We recommend that the following conditions be observed for operation of the ADC14155:
3 V ≤ VA ≤ 3.6 V
VD = VA
VDR = 1.8 V
5 MHz ≤ fCLK ≤ 155 MHz
1-V internal reference
0.9 V ≤ VREF ≤ 1.1 V (for an external reference)
VCM = 1.5 V (from VRM
)
8.2.2 Detailed Design Procedure
Digital outputs consist of the 1.8 V CMOS signals D0-D13, DRDY and OVR.
The ADC14155 has 16 CMOS compatible data output pins: 14 data output bits corresponding to the converted
input value, a data ready (DRDY) signal that should be used to capture the output data and an over-range
indicator (OVR) which is set high when the sample amplitude exceeds the 14-bit conversion range. Valid data is
present at these outputs while the PD pin is low.
Data should be captured and latched with the rising edge of the DRDY signal. Depending on the setup and hold
time requirements of the receiving circuit (ASIC), either the rising edge or the falling edge of the DRDY signal
can be used to latch the data. Generally, rising-edge capture would maximize setup time with minimal hold time;
while falling-edge-capture would maximize hold time with minimal setup time. However, actual timing for the
falling-edge case depends greatly on the CLK frequency and both cases also depend on the delays inside the
ASIC. Refer to the ADC14155 Converter Electrical Characteristics (Continued) Timing and AC Characteristics(1)
table.
(1) Pre and post irradiation limits are identical to those listed in the Electrical Characteristics tables. Radiation testing is performed per MIL-
STD-883, Test Method 1019.
24
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ADC14155QML-SP
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ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
Typical Application (continued)
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will
reduce this problem. Additionally, bus capacitance beyond the specified 5 pF/pin will cause tOD to increase,
reducing the setup and hold time of the ADC output data. The result could be an apparent reduction in dynamic
performance.
To minimize noise due to output switching, the load currents at the digital outputs should be minimized. This can
be done by using a programmable logic device (PLD) such as the LC4032V-25TN48C to level translate the ADC
output data from 1.8 V to 3.3 V for use by any other circuitry. Only one load should be connected to each output
pin. Additionally, inserting series resistors of about 22 Ω at the digital outputs, close to the ADC pins, will isolate
the outputs from trace and other circuit capacitances and limit the output currents, which could otherwise result in
performance degradation. See Figure 24.
8.2.3 Application Curve
Figure 25. SNR, SINAD, SFDR vs fIN
8.3 Radiation Environments
Careful consideration should be given to environmental conditions when using a product in a radiation
environment.
8.3.1 Total Ionizing Dose (TID)
Radiation hardness assured (RHA) products are those part numbers with a total ionizing dose (TID) level
specified in the table on the front page. Testing and qualification of these products is done according to MIL-
STD-883, Test Method 1019. Additional information on how to download lot-specific TID data can be found in
SBOA140 "QML Class V/Q and Enhanced Products Lot Documents".
8.3.2 Single Event Effects
One time single event latch-up testing (SEL) was preformed according to EIA/JEDEC Standard, EIA/JEDEC57.
The linear energy transfer threshold (LETth) shown in the Key Specifications table on the front page is the
maximum LET tested. Test reports are available on the TI estore at SNAA153 and SNAA183.
Copyright © 2008–2019, Texas Instruments Incorporated
25
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
9 Power Supply Recommendations
The power supply pins should be bypassed with a 0.1-µF capacitor and with a 100-pF ceramic chip capacitor
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC14155 is sensitive to power supply noise. Accordingly, the
noise on the analog supply pin should be kept below 100 mVP-P
.
The VDR pin provides power for the output drivers and may be operated from a supply in the range of 1.6 V to 2
V. This enables lower power operation, reduces the noise coupling effects from the digital outputs to the analog
circuitry and simplifies interfacing to lower voltage devices and systems. Note, however, that tOD increases with
reduced VDR. A level translator may be required to interface the digital output signals of the ADC14155 to non-
1.8-V CMOS devices.
Care should be taken to avoid extremely rapid power supply ramp up rate. Excessive power supply ramp up rate
may damage the device.
26
Copyright © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
10 Layout
10.1 Layout Guidelines
For best dynamic performance, the center die attach pad of the device should be connected to ground with low
inductive path.
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC14155 between these areas, is required to achieve
specified performance.
The ground return for the data outputs (DRGND) carries the ground current for the output drivers. The output
current can exhibit high transients that could add noise to the conversion process. To prevent this from
happening, it is recommended to use a single common ground plane with managed return current paths instead
of a split ground plane. The key is to make sure that the supply current in the ground plane does not return under
a sensitive node (e.g., caps to ground in the analog input network). This is done by routing a trace from the ADC
to the regulator / bulk capacitor for the supply so that it does not run under a critical node.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
The effects of the noise generated from the ADC output switching can be minimized through the use of 22-Ω
resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane area.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
Be especially careful with the layout of inductors and transformers. Mutual inductance can change the
characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by
side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog
input and the clock input at 90° to one another to avoid magnetic coupling.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the ground plane.
All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of
the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The
ADC14155 should be between these two areas. Furthermore, all components in the reference circuitry and the
input signal chain that are connected to ground should be connected together with short traces and enter the
ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.
Copyright © 2008–2019, Texas Instruments Incorporated
27
ADC14155QML-SP
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
www.ti.com.cn
10.2 Layout Example
Figure 26. ADC14155QML Layout
28
版权 © 2008–2019, Texas Instruments Incorporated
ADC14155QML-SP
www.ti.com.cn
ZHCSHX9L –NOVEMBER 2008–REVISED FEBRUARY 2019
11 器件和文档支持
11.1 器件支持
11.1.1 器件命名规则
孔径延迟是时钟下降沿之后到采集或保持输入信号以进行转换的时间。
孔径抖动（孔径不确定性）是样本之间孔径延迟的变化。孔径抖动在输出中表现为噪声。
时钟占空比一个周期内重复数字波形为高电平的时间与一个周期总时长的比值。这里的规格是指 ADC 时钟输入信
号。
共模电压 (VCM) 是施加到 ADC 的两个输入端子上的共用直流电压。
转换延迟是开始转换与数据出现在输出驱动器级中之间的时钟周期数。在获取样本之后，可以在输出引脚上获取任
何给定样本的数据（流水线延迟和输出延迟）。可以在每个时钟周期获取新数据，但数据会将转换滞后流水线延迟
的时间。
微分非线性 (DNL) 是对相对于理想步长 (1LSB) 的最大偏差的度量。
有效位数（ENOB 或有效位）是另一种用于指定信号噪声失真比或 SINAD 的方法。ENOB 定义为 (SINAD – 1.76)
/6.02，表明转换器等效于具有该位数 (ENOB) 的理想 ADC。
全功率带宽是一个频率测量值，在此频率下，重构的输出基频会降至满标量程输入的低频值以下 3dB。
增益误差是指相对于传递函数理想斜率的偏差。可按以下方式来计算它：
增益误差 = 正满标量程误差 – 负满标量程误差
(4)
(5)
它还可以表示为正增益误差和负增益误差，计算方式如下：
PGE = 正满标量程误差 – 偏移误差 NGE = 偏移误差 – 负满标量程误差
积分非线性 (INL) 表示每个单独代码相对于从负满标量程（第一个代码转换之下 ½ LSB）到正满标量程（最后一个
代码转之上 ½ LSB）画出的线的偏差。任意指定代码相对于该直线的偏差从该代码值的中心进行测量。
互调失真 (IMD) 是由于两个正弦频率同时被施加到 ADC 输入上所产生的额外频谱分量。它定义为互调产物中的功
率与原始频率中的总功率之比。IMD 通常以 dBFS 为单位。
LSB（最低有效位）是所有位中具有最小值或最低权重的位。该值为VFS/2n，其中“VFS”是满标量程输入电压，“n”是
以位为单位的 ADC 分辨率。
缺失的代码是永远不会显示在 ADC 输出中的输出代码。ADC14155QML 保证不会有任何缺失的代码。
MSB（最高有效位）是具有最大值或最高权重的位。它的值是满量程的一半。
负满标量程误差是实际第一个代码转换与它的理想值（负满标量程之上 ½ LSB）之间的差值。
偏移误差是导致从代码 8191 到 8192 的转换所需的两个输入电压之间的差值 [(VIN+) – (VIN–)]。
输出延迟是在时钟的下降沿之后、输出引脚上出现数据更新之前的时间延迟。
流水线延迟 (LATENCY) 请参阅“转换延迟”。
正满标量程误差是实际最后一个代码转换与它的理想值（正满标量程之下 1½ LSB）之间的差值。
电源抑制比 (PSRR) 是对 ADC 抑制电源电压变化的能力的度量。PSRR 是电源处于直流电源下限的 ADC 满标量
程输出与电源处于直流电源上限的 ADC 满标量程输出之比，以 dB 为单位。
信噪比 (SNR) 是输入信号的 rms 值与低于采样频率一半的所有其他频谱分量（不包括谐波或直流）之和的 rms 值
之比，以 dB 为单位。
信号噪声失真比（S/N+D 或 SINAD） 是输入信号的 rms 值与低于时钟频率一半的所有其他频谱分量（包括谐波，
但不包括直流）的 rms 值之比，以 dB 为单位。
无杂散动态范围 (SFDR) 是输入信号与杂散信号峰值的 rms 值之间的差值（以 dB 为单位），其中杂散信号是出现
在输出频谱中但未出现在输入中的任何信号。
总谐波失真 (THD) 是输出端前九个谐波电平的总 rms 与输出端基波电平之比，以 dB 为单位。THD 的计算方法为
Copyright © 2008–2019, Texas Instruments Incorporated
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ADC14155QML-SP
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www.ti.com.cn
器件支持 (continued)
(6)
其中 f1 是基波（输出）频率的 RMS 功率，f2 到 f10 是输出频谱中前 9 个谐波频率的 RMS 功率。
二次谐波失真 (2ND HARM) 是输出端的输入频率中的 RMS 功率与输出端其二次谐波电平中的功率之间的差值，以
dB 为单位。
三次谐波失真 (3RD HARM) 是输出端的输入频率中的 RMS 功率与输出端其三次谐波电平中的功率之间的差值，以
dB 为单位。
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2008–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
5962R0626201VXC
ACTIVE
CFP
NBA
48
14
RoHS & Green
Call TI
Level-1-NA-UNLIM
-55 to 125
5962
R0626201VXC
ADC14155-RHA
Samples
ADC14155W-MLS
ADC14155W-MPR
ACTIVE
ACTIVE
CFP
CFP
NBA
NBA
48
48
14
14
RoHS & Green
RoHS & Green
Call TI
Call TI
Level-1-NA-UNLIM
Level-1-NA-UNLIM
-55 to 125
25 to 25
ADC14155W
-MLS
Samples
Samples
ADC14155W
-MPR ES
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
5962R0626201VXC
ADC14155W-MLS
ADC14155W-MPR
NBA
NBA
NBA
CFP
CFP
CFP
48
48
48
14
14
14
495
495
495
33
33
33
11176
11176
11176
16.51
16.51
16.51
Pack Materials-Page 1
PACKAGE OUTLINE
NBA0048A
CFP - 2.77 mm max height
S
C
A
L
E
1
.
0
0
0
CERAMIC FLATPACK
B
11.5±0.13
37
48
A
PIN 1 ID
36
1
9.525 0.076
11.5±0.13
10.94 0.13
25
12
48X
2.25 0.26
24
13
48X 0.18 0.05
0.12 C A
44X 0.635
B
4X 6.99
2.77 MAX
C
2.64±0.05
(0.78) TYP
(0.96) TYP
(0.2) TYP
0.15 0.03
2.03±0.02
TYP
6
0.13
HEATSINK
PIN1 ID
4219845/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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