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ADC14DC080CISQE/NOPB [TI]

双通道、14 位、80MSPS、1.0GHz 输入带宽模数转换器 (ADC) | NKA | 60 | -40 to 85;
ADC14DC080CISQE/NOPB
型号： ADC14DC080CISQE/NOPB
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

双通道、14 位、80MSPS、1.0GHz 输入带宽模数转换器 (ADC) | NKA | 60 | -40 to 85

转换器 模数转换器
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ADC14DC080  
www.ti.com  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
ADC14DC080 Dual 14-Bit, 80 MSPS A/D Converter with CMOS Outputs  
Check for Samples: ADC14DC080  
1
FEATURES  
DESCRIPTION  
The ADC14DC080 is a high-performance CMOS  
analog-to-digital converter capable of converting two  
analog input signals into 14-bit digital words at rates  
up to 80 Mega Samples Per Second (MSPS). These  
converters use a differential, pipelined architecture  
with digital error correction and an on-chip sample-  
and-hold circuit to minimize power consumption and  
the external component count, while providing  
excellent dynamic performance. A unique sample-  
and-hold stage yields a full-power bandwidth of 1  
GHz. The ADC14DC080 may be operated from a  
single +3.0V power supply. A power-down feature  
reduces the power consumption to very low levels  
while still allowing fast wake-up time to full operation.  
2
•
Internal Sample-and-Hold Circuit and Precision  
Reference  
•
•
•
•
•
Low Power Consumption  
Clock Duty Cycle Stabilizer  
Single +3.0V Supply Operation  
Power-Down Mode  
Offset Binary or 2's Complement Output Data  
Format  
•
60-Pin WQFN Package, (9x9x0.8mm, 0.5mm  
Pin-Pitch)  
APPLICATIONS  
The differential inputs provide  
a 2V full scale  
differential input swing. A stable 1.2V internal voltage  
reference is provided, or the ADC14DC080 can be  
operated with an external 1.2V reference. Output  
data format (offset binary versus 2's complement)  
and duty cycle stabilizer are pin-selectable. The duty  
cycle stabilizer maintains performance over a wide  
range of clock duty cycles.  
•
•
•
•
•
High IF Sampling Receivers  
Wireless Base Station Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Portable Instrumentation  
KEY SPECIFICATIONS  
The ADC14DC080 is available in a 60-lead WQFN  
package and operates over the industrial temperature  
range of −40°C to +85°C.  
•
•
•
•
•
•
Resolution 14 Bits  
Conversion Rate 80 MSPS  
SNR (fIN = 170 MHz) 71 dBFS (typ)  
SFDR (fIN = 170 MHz) 83 dBFS (typ)  
Full Power Bandwidth 1 GHz (typ)  
Power Consumption 600 mW (typ)  
Block Diagram  
2
14  
14  
14-Bit Pipelined  
ADC Core  
Output  
Buffers  
CHANNEL A  
DA0-DA13  
V
A
IN  
3
Ref.Decoupling  
Reference  
A
V
REF  
Timing  
Generation  
CLK  
DRDY  
Reference  
B
3
2
Ref.Decoupling  
14  
14  
CHANNEL B  
DB0-DB13  
14-Bit Pipelined  
ADC Core  
Output  
Buffers  
V
B
IN  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
ADC14DC080  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
www.ti.com  
Connection Diagram  
AGND  
1
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
DA5  
V
A-  
IN  
2
DA4  
V A+  
IN  
3
DA3  
AGND  
4
DA2  
V
A
A
A
RP  
5
DA1  
V
RN  
6
DA0 (LSB)  
DRDY  
V
V
CMO  
7
ADC14DC080  
V
V
DR  
A
8
B
B
B
CMO  
9
DRGND  
DB13 (MSB)  
DB12  
(top view)  
V
RN  
10  
11  
12  
13  
14  
15  
V
RP  
AGND  
DB11  
V
B+  
IN  
DB10  
V
B-  
IN  
DB9  
* Exposed Pad  
AGND  
DB8  
Pin Descriptions and Equivalent Circuits  
Pin No.  
Symbol  
Equivalent Circuit  
Description  
ANALOG I/O  
3
13  
VINA+  
VINB+  
V
A
Differential analog input pins. The differential full-scale input signal  
level is 2VP-P with each input pin signal centered on a common mode  
2
14  
VINA-  
VINB-  
voltage, VCM  
.
AGND  
5
11  
VRP  
VRP  
A
B
V
A
V
A
7
9
VCMO  
VCMO  
A
B
These pins should each be bypassed to AGND with a low ESL  
(equivalent series inductance) 1 µF capacitor placed very close to  
the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor  
should be placed between VRP and VRN as close to the pins as  
possible, and a 1 µF capacitor should be placed in parallel.  
VRP and VRN should not be loaded. VCMO may be loaded to 1mA for  
use as a temperature stable 1.5V reference.  
V
A
6
10  
VRN  
A
V
A
VRNB  
It is recommended to use VCMO to provide the common mode  
voltage, VCM for the differential analog inputs.  
AGND  
AGND  
2
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Product Folder Links: ADC14DC080  
ADC14DC080  
www.ti.com  
Pin No.  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
Pin Descriptions and Equivalent Circuits (continued)  
Symbol  
Equivalent Circuit  
Description  
V
A
Reference Voltage. This device provides an internally developed  
1.2V reference. When using the internal reference, VREF should be  
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series  
inductance (ESL) capacitor.  
59  
VREF  
This pin may be driven with an external 1.2V reference voltage.  
This pin should not be used to source or sink current when the  
internal reference is used.  
AGND  
DIGITAL I/O  
This is a four-state pin controlling the input clock mode and output  
data format.  
V
A
OF/DCS = VA, output data format is 2's complement without duty  
cycle stabilization applied to the input clock.  
OF/DCS = AGND, output data format is offset binary, without duty  
cycle stabilization applied to the input clock.  
19  
OF/DCS  
OF/DCS = (2/3)*VA, output data is 2's complement with duty cycle  
stabilization applied to the input clock.  
OF/DCS = (1/3)*VA, output data is offset binary with duty cycle  
stabilization applied to the input clock.  
AGND  
The clock input pin.  
The analog inputs are sampled on the rising edge of the clock input.  
18  
CLK  
V
A
This is a two-state input controlling Power Down.  
PD = VA, Power Down is enabled and power dissipation is reduced.  
PD = AGND, Normal operation.  
57  
20  
PD_A  
PD_B  
AGND  
Digital data output pins that make up the 14-bit conversion result for  
Channel A. DA0 (pin 40) is the LSB, while DA13 (pin 55) is the MSB  
of the output word. Output levels are CMOS compatible.  
40-49,  
52-55  
DA0-DA9,  
DA10-DA13  
V
V
A
DR  
Digital data output pins that make up the 14-bit conversion result for  
Channel B. DB0 (pin 21) is the LSB, while DB13 (pin 36) is the MSB  
of the output word. Output levels are CMOS compatible.  
21-24,  
27-36  
DB0-DB3,  
DB4-DB13  
Data Ready Strobe. The data output transition is synchronized with  
the falling edge of this signal. This signal switches at the same  
frequency as the CLK input.  
39  
DRDY  
DRGND  
DRGND  
ANALOG POWER  
Positive analog supply pins. These pins should be connected to a  
quiet source and be bypassed to AGND with 0.1 µF capacitors  
located close to the power pins.  
8, 16, 17, 58,  
60  
VA  
The ground return for the analog supply.  
The exposed pad on back of package must be soldered to ground  
plane to ensure rated performance.  
1, 4, 12, 15,  
Exposed Pad  
AGND  
Copyright © 2008–2013, Texas Instruments Incorporated  
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ADC14DC080  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
www.ti.com  
Pin Descriptions and Equivalent Circuits (continued)  
Pin No.  
Symbol  
Equivalent Circuit  
Description  
DIGITAL POWER  
Positive driver supply pin for the output drivers. This pin should be  
connected to a quiet voltage source and be bypassed to DRGND  
with a 0.1 µF capacitor located close to the power pin.  
26, 38,50  
25, 37, 51  
VDR  
The ground return for the digital output driver supply. This pins  
should be connected to the system digital ground, but not be  
connected in close proximity to the ADC's AGND pins.  
DRGND  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
(1) (2)(3)  
Absolute Maximum Ratings  
Supply Voltage (VA, VDR  
)
−0.3V to 4.2V  
Voltage on Any Pin  
(Not to exceed 4.2V)  
−0.3V to (VA +0.3V)  
(4)  
Input Current at Any Pin other than Supply Pins  
±5 mA  
±50 mA  
(4)  
Package Input Current  
Max Junction Temp (TJ)  
+150°C  
(5)  
Thermal Resistance (θJA  
)
30°C/W  
(6)  
ESD Rating  
Human Body Model  
2500V  
(6)  
Machine Model  
250V  
Storage Temperature  
−65°C to +150°C  
Soldering process must comply with TI's Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.(7)  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test  
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance  
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the  
maximum Operating Ratings is not recommended.  
(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.  
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.  
(4) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be  
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power  
supplies with an input current of ±5 mA to 10.  
(5) The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient  
temperature, (TA), and can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed  
above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the  
power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.  
(6) Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω.  
(7) Reflow temperature profiles are different for lead-free and non-lead-free packages.  
(1)(2)  
Operating Ratings  
Operating Temperature  
Supply Voltage (VA)  
Output Driver Supply (VDR  
Clock Duty Cycle  
−40°C ≤ TA ≤ +85°C  
+2.7V to +3.6V  
2.4V to VA  
)
(DCS Enabled)  
(DCS Disabled)  
30/70 %  
45/55 %  
VCM  
1.4V to 1.6V  
≤100mV  
|AGND-DRGND|  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is specified to be functional, but do not ensure specific performance limits. For ensured specifications and test  
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance  
characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the  
maximum Operating Ratings is not recommended.  
(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.  
4
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: ADC14DC080  
 
ADC14DC080  
www.ti.com  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
Converter Electrical Characteristics  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤  
(1)(2)  
TMAX. All other limits apply for TA = 25°C  
Typical  
Units  
(Limits)  
Symbol  
Parameter  
Conditions  
Limits  
(3)  
STATIC CONVERTER CHARACTERISTICS  
Resolution with No Missing Codes  
14  
4
Bits (min)  
LSB (max)  
LSB (min)  
LSB (max)  
LSB (min)  
%FS (max)  
%FS (max)  
ppm/°C  
(4)  
INL  
Integral Non Linearity  
±1.5  
±0.4  
-4  
1
DNL  
Differential Non Linearity  
-0.9  
±1  
±1  
PGE  
NGE  
Positive Gain Error  
Negative Gain Error  
0.15  
-0.1  
-8  
TC PGE Positive Gain Error Tempco  
TC NGE Negative Gain Error Tempco  
−40°C ≤ TA ≤ +85°C  
−40°C ≤ TA ≤ +85°C  
-12  
0.1  
ppm/°C  
VOFF  
Offset Error  
±0.55  
%FS (max)  
ppm/°C  
TC VOFF Offset Error Tempco  
Under Range Output Code  
Over Range Output Code  
−40°C ≤ TA ≤ +85°C  
10  
0
0
16383  
16383  
REFERENCE AND ANALOG INPUT CHARACTERISTICS  
1.45  
1.56  
V (min)  
V (max)  
VCMO  
VCM  
Common Mode Output Voltage  
1.5  
1.5  
1.4  
1.6  
V (min)  
V (max)  
Analog Input Common Mode Voltage  
(CLK LOW)  
(CLK HIGH)  
8.5  
3.5  
pF  
pF  
VIN Input Capacitance (each pin to GND) VIN = 1.5 Vdc ± 0.5  
CIN  
(5)  
V
1.176  
1.224  
V (min)  
V (max)  
VREF  
Internal Reference Voltage  
1.20  
TC VREF Internal Reference Voltage Tempco  
−40°C ≤ TA ≤ +85°C  
18  
2
ppm/°C  
VRP  
VRN  
Internal Reference Top  
V
V
Internal Reference Bottom  
1
0.89  
1.06  
V (Min)  
V (max)  
Internal Reference Accuracy  
External Reference Voltage  
(VRP-VRN  
)
1
EXT  
VREF  
1.176  
1.224  
V (Min)  
V (max)  
(6)  
See  
1.20  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V  
or below GND as described in the Operating Ratings section.  
V
A
I/O  
To Internal Circuitry  
AGND  
(2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.  
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical  
specifications are not ensured.  
(4) Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through  
positive and negative full-scale.  
(5) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.  
(6) This parameter is specified by design and/or characterization and is not tested in production.  
Copyright © 2008–2013, Texas Instruments Incorporated  
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Product Folder Links: ADC14DC080  
 
ADC14DC080  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
www.ti.com  
Dynamic Converter Electrical Characteristics  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤  
(1) (2)  
TMAX. All other limits apply for TA = 25°C  
Typical  
Units  
(Limits)  
Symbol  
Parameter  
Conditions  
Limits  
(3)  
(4)  
DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS  
FPBW  
SNR  
Full Power Bandwidth  
Signal-to-Noise Ratio  
-1 dBFS Input, −3 dB Corner  
fIN = 10 MHz  
1.0  
74  
GHz  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
Bits  
fIN = 70 MHz  
73.5  
71  
fIN = 170 MHz  
fIN = 10 MHz  
70  
78  
90  
SFDR  
ENOB  
THD  
H2  
Spurious Free Dynamic Range  
Effective Number of Bits  
fIN = 70 MHz  
86  
fIN = 170 MHz  
fIN = 10 MHz  
83  
12  
fIN = 70 MHz  
11.9  
11.4  
−86  
−85  
−82  
−95  
−90  
−83  
−90  
−85  
−83  
73.7  
73.2  
70.7  
-84  
Bits  
fIN = 170 MHz  
fIN = 10 MHz  
11.1  
-77  
-78  
-78  
69.2  
Bits  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
Total Harmonic Disortion  
fIN = 70 MHz  
fIN = 170 MHz  
fIN = 10 MHz  
Second Harmonic Distortion  
Third Harmonic Distortion  
fIN = 70 MHz  
fIN = 170 MHz  
fIN = 10 MHz  
H3  
fIN = 70 MHz  
fIN = 170 MHz  
fIN = 10 MHz  
SINAD  
IMD  
Signal-to-Noise and Distortion Ratio  
fIN = 70 MHz  
fIN = 170 MHz  
fIN = 20 MHz and 21 MHz, each -7dBFS  
Intermodulation Distortion  
Crosstalk  
0 MHz tested channel, fIN = 10 MHz at -  
1dBFS other channel  
-100  
dBFS  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V  
or below GND as described in the Operating Ratings section.  
V
A
I/O  
To Internal Circuitry  
AGND  
(2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.  
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical  
specifications are not ensured.  
(4) This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal.  
6
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Product Folder Links: ADC14DC080  
ADC14DC080  
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SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
Logic and Power Supply Electrical Characteristics  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Boldface limits apply for TMIN ≤ TA ≤  
(1) (2)  
TMAX. All other limits apply for TA = 25°C  
Units  
(Limits)  
(3)  
Symbol  
Parameter  
Conditions  
Typical  
Limits  
DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B)  
VIN(1)  
VIN(0)  
IIN(1)  
IIN(0)  
CIN  
Logical “1” Input Voltage  
Logical “0” Input Voltage  
Logical “1” Input Current  
Logical “0” Input Current  
Digital Input Capacitance  
VA = 3.3V  
VA = 3.0V  
VIN = 3.3V  
VIN = 0V  
2.0  
0.8  
V (min)  
V (max)  
µA  
10  
−10  
5
µA  
pF  
DIGITAL OUTPUT CHARACTERISTICS (DA0-DA13,DB0-DB13,DRDY)  
VOUT(1)  
VOUT(0)  
+ISC  
Logical “1” Output Voltage  
IOUT = −0.5 mA , VDR = 2.4V  
IOUT = 1.6 mA, VDR = 2.4V  
VOUT = 0V  
2.0  
0.4  
V (min)  
V (max)  
mA  
Logical “0” Output Voltage  
Output Short Circuit Source Current  
Output Short Circuit Sink Current  
Digital Output Capacitance  
−10  
10  
5
−ISC  
VOUT = VDR  
mA  
COUT  
pF  
POWER SUPPLY CHARACTERISTICS  
IA  
Analog Supply Current  
Full Operation  
200  
26  
233  
700  
mA (max)  
mA  
(4)  
IDR  
Digital Output Supply Current  
Power Consumption  
Full Operation  
(4)  
Excludes IDR  
600  
33  
mW (max)  
mW  
Power Down Power Consumption  
PD_A=PD_B=VA  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V  
or below GND as described in the Operating Ratings section.  
V
A
I/O  
To Internal Circuitry  
AGND  
(2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.  
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical  
specifications are not ensured.  
(4) IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,  
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C13  
f13) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at  
which that pin is toggling.  
x
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SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
www.ti.com  
Timing and AC Characteristics  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 80 MHz, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C. Timing measurements are taken at 50%  
(1) (2)  
of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C  
Units  
(3)  
Symb  
Parameter  
Conditions  
Typical  
Limits  
(Limits)  
MHz (max)  
MHz (min)  
ns  
Maximum Clock Frequency  
Minimum Clock Frequency  
Clock High Time  
80  
20  
tCH  
6
6
tCL  
Clock Low Time  
ns  
tCONV  
Conversion Latency  
7
Clock Cycles  
4.7  
8.9  
ns (min)  
ns (max)  
tOD  
Output Delay of CLK to DATA  
Relative to rising edge of CLK  
6.8  
tSU  
tH  
tAD  
tAJ  
Data Output Setup Time  
Data Output Hold Time  
Aperture Delay  
Relative to DRDY  
Relative to DRDY  
5.8  
6.6  
0.6  
0.1  
4
ns (min)  
ns (min)  
ns  
4.6  
Aperture Jitter  
ps rms  
(1) The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided  
current is limited per Absolute Maximum Ratings, Note 4. However, errors in the A/D conversion can occur if the input goes above 2.6V  
or below GND as described in the Operating Ratings section.  
V
A
I/O  
To Internal Circuitry  
AGND  
(2) With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.  
(3) Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical  
specifications are not ensured.  
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Specification Definitions  
APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for  
conversion.  
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.  
Aperture jitter manifests itself as noise in the output.  
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the  
total time of one period. The specification here refers to the ADC clock input signal.  
COMMON MODE VOLTAGE (VCM) is the common DC voltage applied to both input terminals of the ADC.  
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is  
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay  
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the  
conversion by the pipeline delay.  
CROSSTALK is coupling of energy from one channel into the other channel.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise  
and Distortion Ratio or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is  
equivalent to a perfect ADC of this (ENOB) number of bits.  
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental  
drops 3 dB below its low frequency value for a full scale input.  
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:  
Gain Error = Positive Full Scale Error − Negative Full Scale Error  
(1)  
(2)  
It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:  
PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error  
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight  
line. The deviation of any given code from this straight line is measured from the center of that code value.  
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two  
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in  
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.  
LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is VFS/2n,  
where “VFS” is the full scale input voltage and “n” is the ADC resolution in bits.  
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC is ensured not to  
have any missing codes.  
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.  
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of  
½ LSB above negative full scale.  
OFFSET ERROR is the difference between the two input voltages [(VIN+) – (VIN-)] required to cause a transition  
from code 8191 to 8192.  
OUTPUT DELAY is the time delay after the falling edge of the clock before the data update is presented at the  
output pins.  
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.  
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of  
1½ LSB below positive full scale.  
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power  
supply voltage. PSRR is the ratio of the Full-Scale output of the ADC with the supply at the minimum DC supply  
limit to the Full-Scale output of the ADC with the supply at the maximum DC supply limit, expressed in dB.  
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms  
value of the sum of all other spectral components below one-half the sampling frequency, not including  
harmonics or DC.  
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the  
input signal to the rms value of all of the other spectral components below half the clock frequency, including  
harmonics but excluding d.c.  
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the  
input signal and the peak spurious signal, where a spurious signal is any signal present in the output spectrum  
that is not present at the input.  
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first six harmonic  
levels at the output to the level of the fundamental at the output. THD is calculated as:  
(3)  
where f1 is the RMS power of the fundamental (output) frequency and f2 through f7 are the RMS power of the first  
six harmonic frequencies in the output spectrum.  
SECOND HARMONIC DISTORTION (2ND HARM) is the difference expressed in dB, between the RMS power in  
the input frequency at the output and the power in its 2nd harmonic level at the output.  
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in  
the input frequency at the output and the power in its 3rd harmonic level at the output.  
Timing Diagrams  
SampleN+8  
SampleN+7  
SampleN+6  
SampleN+9  
SampleN  
SampleN+10  
V
V
A
B
IN  
IN  
t
AD  
1
F
CLK  
ClockN  
ClockN+7  
90%  
10%  
90%  
10%  
CLK  
t
CL  
t
CH  
t
f
t
r
DRDY  
Latency ( t  
)
CONV  
t
OD  
DA0 - DA13  
DB0 - DB13  
DataN-1  
Data N  
DataN+1  
DataN+2  
t
t
H
SU  
Figure 1. Output Timing  
10  
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Transfer Characteristic  
Figure 2. Transfer Characteristic  
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Typical Performance Characteristics DNL, INL  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, TA = 25°C.  
DNL  
INL  
Figure 3.  
Figure 4.  
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Typical Performance Characteristics  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 170 MHz, TA = 25°C.  
SNR, SINAD, SFDR vs. VA  
Distortion vs. VA  
Figure 5.  
Figure 6.  
SNR, SINAD, SFDR vs. Clock Duty Cycle, fIN=40 MHz  
Distortion vs. Clock Duty Cycle, fIN=40 MHz  
Figure 7.  
Figure 8.  
SNR, SINAD, SFDR vs. Clock Duty Cycle, DCS Enabled,  
fIN=40 MHz  
Distortion vs. Clock Duty Cycle, DCS Enabled, fIN=40 MHz  
Figure 9.  
Figure 10.  
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Typical Performance Characteristics (continued)  
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.3V, VDR = +2.5V, Internal VREF  
= +1.2V, fCLK = 105 MHz, 50% Duty Cycle, DCS disabled, VCM = VCMO, fIN = 170 MHz, TA = 25°C.  
SNR and SFDR vs. fIN  
POWER vs. fCLK  
Figure 11.  
Figure 12.  
Spectral Response @ 10 MHz Input  
Spectral Response @ 70 MHz Input  
Figure 13.  
Figure 14.  
Spectral Response @ 170 MHz Input  
IMD, fIN1 = 20 MHz, fIN2 = 21 MHz  
Figure 15.  
Figure 16.  
14  
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FUNCTIONAL DESCRIPTION  
Operating on a single +3.0V supply, the ADC14DC080 digitizes two differential analog input signals to 14 bits,  
using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to  
ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or using an  
external 1.2V reference. Any external reference is buffered on-chip to ease the task of driving that pin. Duty cycle  
stabilization and output data format are selectable using the quad state function OF/DCS pin (pin 19). The output  
data can be set for offset binary or two's complement.  
Applications Information  
OPERATING CONDITIONS  
We recommend that the following conditions be observed for operation of the ADC14DC080:  
2.7V ≤ VA ≤ 3.6V  
2.4V ≤ VDR ≤ VA  
20 MHz ≤ fCLK ≤ 80 MHz  
1.2V internal reference  
VREF = 1.2V (for an external reference)  
VCM = 1.5V (from VCMO  
ANALOG INPUTS  
Signal Inputs  
)
Differential Analog Input Pins  
The ADC14DC080 has a pair of analog signal input pins for each of two channels. VIN+ and VIN− form a  
differential input pair. The input signal, VIN, is defined as:  
VIN = (VIN+) – (VIN−)  
(4)  
Figure 17 shows the expected input signal range. Note that the common mode input voltage, VCM, should be  
1.5V. Using VCMO (pins 7,9) for VCM will ensure the proper input common mode level for the analog input signal.  
The positive peaks of the individual input signals should each never exceed 2.6V. Each analog input pin of the  
differential pair should have a maximum peak-to-peak voltage of 1V, be 180° out of phase with each other and  
be centered around VCM.The peak-to-peak voltage swing at each analog input pin should not exceed the 1V or  
the output data will be clipped.  
Figure 17. Expected Input Signal Range  
For single frequency sine waves the full scale error in LSB can be described as approximately:  
EFS = 16384 ( 1 - sin (90° + dev))  
(5)  
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Where dev is the angular difference in degrees between the two signals having a 180° relative phase relationship  
to each other (see Figure 18). For single frequency inputs, angular errors result in a reduction of the effective full  
scale input. For complex waveforms, however, angular errors will result in distortion.  
Figure 18. Angular Errors Between the Two Input Signals Will Reduce the Output Level or Cause  
Distortion  
It is recommended to drive the analog inputs with a source impedance less than 100Ω. Matching the source  
impedance for the differential inputs will improve even ordered harmonic performance (particularly second  
harmonic).  
Table 1 indicates the input to output relationship of the ADC14DC080.  
Table 1. Input to Output Relationship  
+
−
VIN  
VIN  
Binary Output  
2’s Complement Output  
10 0000 0000 0000  
11 0000 0000 0000  
00 0000 0000 0000  
01 0000 0000 0000  
01 1111 1111 1111  
V
CM − VREF/2  
CM − VREF/4  
VCM  
VCM + VREF/2  
VCM + VREF/4  
VCM  
00 0000 0000 0000  
01 0000 0000 0000  
10 0000 0000 0000  
11 0000 0000 0000  
11 1111 1111 1111  
Negative Full-Scale  
Mid-Scale  
V
VCM + VREF/4  
VCM + VREF/2  
V
CM − VREF/4  
CM − VREF/2  
V
Positive Full-Scale  
Driving the Analog Inputs  
The VIN+ and the VIN− inputs of the ADC14DC080 have an internal sample-and-hold circuit which consists of an  
analog switch followed by a switched-capacitor amplifier.  
Figure 19 and Figure 20 show examples of single-ended to differential conversion circuits. The circuit in  
Figure 19 works well for input frequencies up to approximately 70MHz, while the circuit inFigure 20 works well  
above 70MHz.  
V
IN  
0.1 mF  
50W  
20W  
ADT1-1WT  
ADC  
Input  
18 pF  
0.1 mF  
0.1 mF  
20W  
V
CMO  
Figure 19. Low Input Frequency Transformer Drive Circuit  
V
IN  
0.1 mF  
0.1 mF  
ETC1-1-13  
100W  
100W  
3 pF  
ADC  
Input  
ETC1-1-13  
V
CMO  
0.1 mF  
Figure 20. High Input Frequency Transformer Drive Circuit  
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One short-coming of using a transformer to achieve the single-ended to differential conversion is that most RF  
transformers have poor low frequency performance. A differential amplifier can be used to drive the analog inputs  
for low frequency applications. The amplifier must be fast enough to settle from the charging glitches on the  
analog input resulting from the sample-and-hold operation before the clock goes high and the sample is passed  
to the ADC core.  
Input Common Mode Voltage  
The input common mode voltage, VCM, should be in the range of 1.4V to 1.6V and be a value such that the peak  
excursions of the analog signal do not go more negative than ground or more positive than 2.6V. It is  
recommended to use VCMO (pins 7,9) as the input common mode voltage.  
Reference Pins  
The ADC14DC080 is designed to operate with an internal or external 1.2V reference. The internal 1.2 Volt  
reference is the default condition when no external reference input is applied to the VREF pin. If a voltage is  
applied to the VREF pin, then that voltage is used for the reference. The VREF pin should always be bypassed to  
ground with a 0.1 µF capacitor close to the reference input pin.  
It is important that all grounds associated with the reference voltage and the analog input signal make connection  
to the ground plane at a single, quiet point to minimize the effects of noise currents in the ground path.  
The Reference Bypass Pins (VRP, VCMO, and VRN) for channels A and B are made available for bypass purposes.  
These pins should each be bypassed to AGND with a low ESL (equivalent series inductance) 1 µF capacitor  
placed very close to the pin to minimize stray inductance. A 0.1 µF capacitor should be placed between VRP and  
VRN as close to the pins as possible, and a 1 µF capacitor should be placed in parallel. This configuration is  
shown in Figure 21. It is necessary to avoid reference oscillation, which could result in reduced SFDR and/or  
SNR. VCMO may be loaded to 1mA for use as a temperature stable 1.5V reference. The remaining pins should  
not be loaded.  
Smaller capacitor values than those specified will allow faster recovery from the power down mode, but may  
result in degraded noise performance. Loading any of these pins, other than VCMO may result in performance  
degradation.  
The nominal voltages for the reference bypass pins are as follows:  
VCMO = 1.5 V  
VRP = 2.0 V  
VRN = 1.0 V  
OF/DCS Pin  
Duty cycle stabilization and output data format are selectable using this quad state function pin. When enabled,  
duty cycle stabilization can compensate for clock inputs with duty cycles ranging from 30% to 70% and generate  
a stable internal clock, improving the performance of the part. With OF/DCS = VA the output data format is 2's  
complement and duty cycle stabilization is not used. With OF/DCS = AGND the output data format is offset  
binary and duty cycle stabilization is not used. With OF/DCS = (2/3)*VA the output data format is 2's complement  
and duty cycle stabilization is applied to the clock. If OF/DCS is (1/3)*VA the output data format is offset binary  
and duty cycle stabilization is applied to the clock. While the sense of this pin may be changed "on the fly," doing  
this is not recommended as the output data could be erroneous for a few clock cycles after this change is made.  
NOTE  
This signal has no effect when SPI_EN is high and the serial control interface is enabled.  
DIGITAL INPUTS  
Digital CMOS compatible inputs consist of CLK, PD_A, and PD_B.  
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Clock Input  
The CLK controls the timing of the sampling process. To achieve the optimum noise performance, the clock input  
should be driven with a stable, low jitter clock signal in the range indicated in the Electrical Table. The clock input  
signal should also have a short transition region. This can be achieved by passing a low-jitter sinusoidal clock  
source through a high speed buffer gate. The trace carrying the clock signal should be as short as possible and  
should not cross any other signal line, analog or digital, not even at 90°.  
The clock signal also drives an internal state machine. If the clock is interrupted, or its frequency is too low, the  
charge on the internal capacitors can dissipate to the point where the accuracy of the output data will degrade.  
This is what limits the minimum sample rate.  
The clock line should be terminated at its source in the characteristic impedance of that line. Take care to  
maintain a constant clock line impedance throughout the length of the line. Refer to Application Note AN-905  
(SNLA035) for information on setting characteristic impedance.  
It is highly desirable that the the source driving the ADC clock pins only drive that pin. However, if that source is  
used to drive other devices, then each driven pin should be AC terminated with a series RC to ground, such that  
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is:  
(6)  
where tPD is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic  
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it  
as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of  
"L" and tPD should be the same (inches or centimeters).  
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise  
duty cycle is difficult, the ADC14DC080 has a Duty Cycle Stabilizer.  
DIGITAL OUTPUTS  
Digital outputs consist of the CMOS signals DA0-DA13, DB0-DB13, and DRDY.  
The ADC14DC080 has 14 CMOS compatible data output pins corresponding to the converted input value for  
each channel, and a data ready (DRDY) signal that should be used to capture the output data. Valid data is  
present at these outputs while the PD pin is low. Data should be captured and latched with the rising edge of the  
DRDY signal.  
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for  
each conversion, the more instantaneous digital current flows through VDR and DRGND. These large charging  
current spikes can cause on-chip ground noise and couple into the analog circuitry, degrading dynamic  
performance. Adequate bypassing, limiting output capacitance and careful attention to the ground plane will  
reduce this problem. The result could be an apparent reduction in dynamic performance.  
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+3.3V  
+
+2.5V  
3x 0.1 mF  
5x 0.1 mF  
10 mF  
0.1 mF  
59  
7
V
REF  
22W  
V
A
CMO  
55  
0.1 mF  
(MSB) DA13  
DA12  
5
6
54  
53  
52  
49  
48  
V
V
A
A
RP  
0.1 mF  
0.1 mF  
0.1 mF  
1 mF  
DA11  
RN  
DA10  
50  
DA9  
9
11  
10  
V
V
V
B
CMO  
DA8  
0.1 mF  
0.1 mF  
47  
B
DA7  
DA6  
DA5  
Channel A  
Output Word  
RP  
46  
0.1 mF  
0.1 mF  
74LCX162244  
B
RN  
45  
44  
43  
42  
41  
40  
1 mF  
V
20  
IN_A  
0.1 mF  
DA4  
DA3  
1
0.1 mF  
18 pF  
3
2
DA2  
V
A+  
A-  
IN  
0.1 mF  
DA1  
20  
V
IN  
(LSB) DA0  
ADT1-1WT  
22W  
22W  
39  
Buffered  
DRDY  
50  
DRDY  
ADC14DC080  
V
20  
20  
IN_B  
0.1 mF  
0.1 mF  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
24  
23  
22  
21  
0.1 mF  
18 pF  
(MSB) DB13  
DB12  
13  
14  
V
V
B+  
B-  
IN  
IN  
DB11  
DB10  
ADT1-1WT  
DB9  
18  
Crystal Oscillator  
OF/DCS  
DB8  
CLK  
DB7  
DB6  
DB5  
Channel B  
Output Word  
19  
57  
20  
OF/DCS  
PD_A  
74LCX162244  
PD_A  
PD_B  
DB4  
DB3  
DB2  
DB1  
PD_B  
(LSB) DB0  
Figure 21. Application Circuit  
POWER SUPPLY CONSIDERATIONS  
The power supply pins should be bypassed with a 0.1 µF capacitor and with a 100 pF ceramic chip capacitor  
close to each power pin. Leadless chip capacitors are preferred because they have low series inductance.  
As is the case with all high-speed converters, the ADC14DC080 is sensitive to power supply noise. Accordingly,  
the noise on the analog supply pin should be kept below 100 mVP-P  
.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be  
especially careful of this during power turn on and turn off.  
LAYOUT AND GROUNDING  
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining  
separate analog and digital areas of the board, with the ADC14DC080 between these areas, is required to  
achieve specified performance.  
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor  
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the  
clock line as short as possible.  
Since digital switching transients are composed largely of high frequency components, total ground plane copper  
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area  
is more important than is total ground plane area.  
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Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in  
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to  
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the  
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause  
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to  
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.  
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the  
signal path through all components should form a straight line wherever possible.  
Be especially careful with the layout of inductors and transformers. Mutual inductance can change the  
characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by  
side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog  
input and the clock input at 90° to one another to avoid magnetic coupling.  
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.  
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to  
the reference input pin and ground should be connected to a very clean point in the ground plane.  
All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed in the analog area of  
the board. All digital circuitry and dynamic I/O lines should be placed in the digital area of the board. The  
ADC14DC080 should be between these two areas. Furthermore, all components in the reference circuitry and  
the input signal chain that are connected to ground should be connected together with short traces and enter the  
ground plane at a single, quiet point. All ground connections should have a low inductance path to ground.  
DYNAMIC PERFORMANCE  
To achieve the best dynamic performance, the clock source driving the CLK input must have a sharp transition  
region and be free of jitter. Isolate the ADC clock from any digital circuitry with buffers, as with the clock tree  
shown in Figure 22. The gates used in the clock tree must be capable of operating at frequencies much higher  
than those used if added jitter is to be prevented.  
As mentioned in Section Clock Input, it is good practice to keep the ADC clock line as short as possible and to  
keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can lead to  
reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90° crossings  
have capacitive coupling, so try to avoid even these 90° crossings of the clock line.  
Figure 22. Isolating the ADC Clock from other Circuitry with a Clock Tree  
20  
Submit Documentation Feedback  
Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: ADC14DC080  
 
 
ADC14DC080  
www.ti.com  
SNAS463B –SEPTEMBER 2008–REVISED APRIL 2013  
REVISION HISTORY  
Changes from Revision A (April 2013) to Revision B  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 20  
Copyright © 2008–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Links: ADC14DC080  
PACKAGE OPTION ADDENDUM  
www.ti.com  
10-Dec-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
ADC14DC080CISQE/NOPB  
ACTIVE  
WQFN  
NKA  
60  
250  
RoHS & Green  
SN  
Level-3-260C-168 HR  
-40 to 85  
14DC080  
CISQ  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
ADC14DC080CISQE/  
NOPB  
WQFN  
NKA  
60  
250  
178.0  
16.4  
9.3  
9.3  
1.3  
12.0  
16.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Aug-2022  
TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
WQFN NKA 60  
SPQ  
Length (mm) Width (mm) Height (mm)  
208.0 191.0 35.0  
ADC14DC080CISQE/  
NOPB  
250  
Pack Materials-Page 2  
MECHANICAL DATA  
NKA0060A  
SQA60A (Rev A)  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
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