ADC14X250 [TI]
14 位、250MSPS 模数转换器 (ADC);
| 型号： | ADC14X250 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 位、250MSPS 模数转换器 (ADC) 转换器 模数转换器 |
| 文件： | 总74页 (文件大小：3688K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC14X250
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
ADC14X250 具有 5Gb/s JESD204B 输出的单通道 14 位 250MSPS ADC
1 特性
3 说明
1
•
•
•
分辨率：14 位
ADC14X250 器件是一款单片单通道高性能模数转换
器，能够将模拟输入信号转换成 14 位数字字，采样速
率达 250MSPS。该转换器采用差分流水线架构并集成
有输入缓冲器，在 –40°C 至 105°C 的整个扩展温度范
围内（在器件的印刷电路板 (PCB) 散热焊盘处测得）
具有出色的动态性能和低功耗特性。
转换速率：250MSPS
性能：
–
输入：240MHz，-3dBFS
–
–
–
–
信噪比 (SNR)：70.1dBFS
噪声频谱密度：-151.1dBFS/Hz
无杂散动态范围 (SFDR)：87dBFS
非 HD2 和非 HD3 毛刺：-92dBFS
集成的输入缓冲器消除了来自内部开关电容采样电路的
电荷回馈噪声，并且简化了驱动放大器、抗混叠滤波器
以及阻抗匹配的系统级设计。此外，还可以对缓冲器进
行调整以校正差分输入信号路径的相位和幅值失衡，从
而改善偶数阶谐波失真。输入采样时钟分频器提供整数
分频比以简化系统时钟。该器件集成有低噪声电压基
准，无需使用外部去耦电容器，从而简化了电路板级设
计。数字输出数据通过采用 32 引脚 5mm × 5mm
WQFN 封装的 JESD204B 子类 1 单通道接口提供。
ADC14X250 可在 1.2V、1.8V 和 3.0V 电源供电下工
作。可使用 SPI 来配置与 1.2V 至 3V 逻辑电路兼容的
器件。
–
无输入 SNR：71.1dBFS
•
•
•
功耗：584mW
额定温度最高达 105°C（在散热焊盘处）
JESD204B 通道速率高达 5Gb/s 的子类 1 单通道
串行数据接口
•
•
•
经缓冲的模拟输入
差分输入相位和幅值校正
输入采样时钟分频器（1 分频、2 分频、4 分频、8
分频）
•
•
4 线制串行外设接口 (SPI)
32 引脚超薄型四方扁平无引线 (WQFN) 封装
（5mm×5mm、0.5mm 间距）
器件信息(1)
部件名称
ADC14X250
封装
WQFN (32)
封装尺寸（标称值）
2 应用范围
5.00mm × 5.00mm
•
•
高中频 (IF) 采样接收器
(1) 要了解所有可用封装，请见产品说明书末尾的可订购产品附
录。
多载波基站接收器
–
GSM/EDGE，CDMA2000，UMTS，LTE，Wi
Max
•
•
•
•
•
•
•
多样性、多模式和多波段接收器
数字预失真
软件定义无线电 (SDR)
测试和测量设备
通信仪器仪表
雷达
便携式仪表
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLASE49
ADC14X250
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
www.ti.com.cn
空白
整个温度范围内的
性能稳定性 (240MHz)
单音源频谱，输入：240MHz，–3dBFS
110
105
100
95
0
-10
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
-20
-30
-40
90
-50
85
-60
80
-70
75
-80
70
-90
-100
-110
-120
65
60
-40
-20
0
20
40
60
80
100
0
25
50
75
100
125
Temperature [èC]
Frequency [MHz]
2
版权 © 2015–2017, Texas Instruments Incorporated
ADC14X250
www.ti.com.cn
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
目录
7.1 JESD204B Interface Functional Characteristics..... 23
Detailed Description ............................................ 24
8.1 Overview ................................................................. 24
8.2 Functional Block Diagram ....................................... 24
8.3 Feature Description................................................. 24
8.4 Device Functional Modes........................................ 33
8.5 Register Map........................................................... 34
Application and Implementation ........................ 41
9.1 Application Information............................................ 41
9.2 Typical Applications ................................................ 55
1
2
3
4
5
6
特性.......................................................................... 1
8
9
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 8
10 Power Supply Recommendations ..................... 60
10.1 Power Supply Design............................................ 60
10.2 Decoupling ............................................................ 60
11 Layout................................................................... 61
11.1 Layout Guidelines ................................................. 61
12 器件和文档支持 ..................................................... 63
12.1 器件支持................................................................ 63
12.2 接收文档更新通知 ................................................. 64
12.3 社区资源................................................................ 64
12.4 商标....................................................................... 64
12.5 静电放电警告......................................................... 64
12.6 Glossary................................................................ 65
13 机械、封装和可订购信息....................................... 65
6.5 Electrical Characteristics: Static Converter
Performance ............................................................. 8
6.6 Electrical Characteristics: Dynamic Converter
Performance............................................................... 8
6.7 Electrical Characteristics: Power Supply ................ 11
6.8 Electrical Characteristics: Analog Interface ............ 11
6.9 Digital Input Characteristics .................................... 12
6.10 Electrical Characteristics: Serial Data Output
Interface ................................................................... 13
6.11 Electrical Characteristics: Digital Input.................. 13
6.12 Timing Requirements............................................ 14
6.13 Typical Characteristics.......................................... 18
Parameter Measurement Information ................ 23
7
4 修订历史记录
Changes from Revision A (March 2017) to Revision B
Page
•
Changed VOH Test Conditions From: "Default VSPI = 1.8 V" To: "Default VSPI = 3 V" in Electrical Characteristics:
Digital Input table.................................................................................................................................................................. 13
•
•
Changed text From: "output 1.8 V logic levels..." To: "output 3 V logic levels..." in section SPI ......................................... 32
Changed text From: "output 1.8 V logic levels..." To: "output 3 V logic levels..." in section SPI ......................................... 55
Changes from Original (December 2015) to Revision A
Page
•
•
Changed 0.1: 1.8 V (default) to 0.1: 3.0 V (default) in 表 13 ............................................................................................... 36
Changed 11: 3.0 V To: 11: 1.8 V in 表 13 ........................................................................................................................... 36
Copyright © 2015–2017, Texas Instruments Incorporated
3
ADC14X250
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
www.ti.com.cn
5 Pin Configuration and Functions
RHB package
32 Pin WQFN
Top View
VA3.0
AGND
VIN+
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SCLK
CSB
BP2.5
AGND
SO–
Thermal
Pad
VIN–
AGND
VCM
SO+
VA1.2
AGND
AGND
VA1.2
Exposed pad on bottom of package
Pin Functions
PIN
TYPE OR DIAGRAM
DESCRIPTION
NAME
NO.
Analog ground
Must be connected to a solid ground reference plane
under the device.
2, 5, 8, 11, 18,
21, 27, 30, 31
AGND
Analog ground
Bypass pins
Capacitive bypassing pin for internally regulated 2.5-V
supply
This pin must be decoupled to AGND with a 0.1-μF
and a 10-µF capacitor located close to the pin.
BP2.5
22
9
CLKIN+
V
A1.2
V
A3.0
Differential device clock input pins
CLKIN+
Each pin is internally terminated to a DC bias with a
50-Ω resistor for a 100-Ω total internal differential
termination. AC coupling is required for coupling the
clock input to these pins if the clock driver cannot meet
the common-mode requirements. Sampling occurs on
the rising edge of the differential signal (CLKIN+) −
(CLKIN–).
50W
10kW
CLKIN–
10
+
-
0.5V
50W
AGND
CLKIN-
AGND
4
Copyright © 2015–2017, Texas Instruments Incorporated
ADC14X250
www.ti.com.cn
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
Pin Functions (continued)
PIN
TYPE OR DIAGRAM
DESCRIPTION
NAME
NO.
23
SPI chip select pin
When this signal is asserted, SCLK is used to clock the
input serial data on the SDI pin or output serial data on
the SDO pin. When this signal is de-asserted, the SDO
pin is high impedance and the input data is ignored.
Active low. A 10 kΩ pull-up resistor to a supply
corresponding to the CSB drive logic level is
recommended to prevent undesired activation of the
SPI bus. Compatible with 1.2- to 3-V CMOS logic
levels.
V
A1.2
V
A3.0
CSB
SO+
19
V
A3.0
Differential high speed serial data lane pins
These pins must be AC coupled to the receiving
device. The differential trace routing from these pins
must maintain a 100-Ω characteristic impedance.
S+
S-
SO–
20
AGND
SPI serial clock pin
V
A1.2
V
Serial data is shifted into and out of the device
synchronous with this clock signal. Compatible with
1.2- to 3-V CMOS logic levels.
A3.0
SCLK
SDI
24
25
SPI data input pin
Serial data is shifted into the device on this pin while
the CSB signal is asserted. Compatible with 1.2- to 3-V
CMOS logic levels.
V
A3.0
+
-
SPI data output pin
Serial data is shifted out of the device on this pin
during a read command while CSB is asserted. The
output logic level is configurable as 1.2, 1.8, 2.5, or 3
V. The output level must be configured after power up
and before performing a read command. See the
Register Descriptions for configuration details.
80W
SDO
26
15
SDO
80W
SYNCb+
2.5V
Differential SYNCb signal input pins
2.5V
2kW
V
A3.0
DC coupling is required for coupling the SYNCb signal
to these pins. Each pin is internally terminated to the
DC bias with a large resistor. An internal 100-Ω
differential termination is provided therefore an external
termination is not required. Additional resistive
components in the input structure give the SYNCb
input a wide input common-mode range. The SYNCb
signal is active low and therefore asserted when the
voltage at SYNCb+ is less than at SYNCb–.
If JESD204B sync~ signals are directed via SPI (with
SYNC_SEL=1), then SYNCb+ and SYNCb- may
remain not connected.
1kW
SYNC+
50W
34kW
2kW
3pF
SYNCb–
16
50W
1kW
SYNC-
34kW
AGND
AGND
Copyright © 2015–2017, Texas Instruments Incorporated
5
ADC14X250
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE OR DIAGRAM
DESCRIPTION
NAME
SYSREF+
NO.
13
V
A1.2
V
A3.0
Differential SYSREF signal input pins
Each pin is internally terminated to a DC bias with a 1-
kΩ resistor. An external 100-Ω differential termination
must always be provided. AC coupling using capacitors
is required for coupling the SYSREF signal to these
pins if the clock driver cannot meet the common-mode
requirements. In the case of AC coupling, the external
termination must be placed on the source side of the
coupling capacitors.
SYSREF+
1kW
10kW
SYSREF–
14
+
-
0.5V
1kW
AGND
SYSREF-
AGND
1.2-V analog power supply pins
These pins must be connected to a quiet source and
decoupled to AGND with a 0.1-μF and 0.01-μF
capacitor located close to each pin.
VA1.2
VA1.8
VA3.0
7, 17, 28
12, 29, 32
1
Supply input pin
Supply input pin
Supply input pin
1.8-V analog power supply pins
These pins must be connected to a quiet source and
decoupled to AGND with a 0.1-μF and 0.01-μF
capacitor located close to each pin.
3-V analog power supply pin
This pin must be connected to a quiet source and
decoupled to AGND with a 0.1-μF and 0.01-μF
capacitor located close to the pin.
Input interface common mode voltage
This pin must be bypassed to AGND with low
V
A3.0
equivalent series inductance (ESL) 0.1-μF capacitors.
One capacitor should be placed as close to the pin as
possible and additional capacitors placed at the bias
load points. 10-μF capacitors should also be placed in
parallel. TI recommends to use VCM to provide the
common mode voltage for the differential analog
inputs. The input common mode bias is provided
internally for the ADC input; therefore, external use of
VCM is recommended, but not strictly required. The
recommended bypass capacitors are always required.
-
VCM
6
VCM
+
+
-
V
A3.0
Differential analog input pins
V
IN+
Each input pin is terminated to the internal common
mode reference with a resistor for an internal
differential termination. External resistors that terminate
to the common-mode voltage bias are recommended
but not strictly required. The total recommended
differential resistive termination (including the internal
200 Ω termination) is recommended to be between 50
Ω and 200 Ω.
100 Ω
V
CM
VIN+
3
+ -
100 Ω
V
IN-
AGND
VIN–
4
Exposed thermal pad
The exposed pad must be connected to the AGND
ground plane electrically and with good thermal
dissipation properties to achieve rated performance.
Exposed thermal pad
6
Copyright © 2015–2017, Texas Instruments Incorporated
ADC14X250
www.ti.com.cn
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
V
VA3.0
–0.3
4.2
2.35
Supply Voltage
VA1.8
–0.3
V
VA1.2
–0.3
1.55
V
VIN+, VIN–
VCM – 0.75(2)
–0.3
VCM + 0.75
V
VCM
VA3.0 + 0.3, not to exceed 4.2 V
V
SCLK, SDI, CSb
–0.3
VA3.0 + 0.3, not to exceed 4.2 V
V
SDO
–0.3
VSPI + 0.3, not to exceed 4.2 V
V
Voltage at:
CLKIN+, CLKIN–, SYSREF+, SYSREF–
–0.3
1.55
V
SYNC+, SYNC–
BP2.5
–0.3
VBP2.5 + 0.3
V
–0.3
3.2
V
SO+, SO–
–0.3
VBP2.5 + 0.3
V
Input current at any pin(3)
5
125
150
mA
°C
°C
TJ
Operating junction temperature(4)
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VCM refers to the voltage bias present at the VCM output. The Absolute Maximum Rating for the VIN+ and VIN– inputs may extend
down to –0.3V for the purpose of the initial power-up transient only. Forcing these pins to a voltage lower than VCM – 0.75 for an
extended time may reduce the operating lifetime of the device.
(3) When the input voltage at any pin exceeds the VA3.0 power supply (that is VIN > VA3.0 or VIN < AGND) the current at that pin should be
limited to ±5 mA. The ±50-mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10 pins.
(4) Prolonged use at this temperature may increase the device failure-in-time (FIT) rate.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Operation of the device beyond the recommended operating ratings is not recommended as it may degrade the device
lifetime.
MIN
MAX
UNIT
°C
TA-MIN Specified temperature minimum, ambient air.
TA-MAX Specified temperature maximum, ambient air.(1)
–40
85
°C
TP-MAX Specified temperature maximum, measured at the device's footprint thermal
pad on the printed circuit board.
105
°C
TJ
Operating junction temperature(2)
106
°C
(1) This device may be operated above the maximum ambient temperature (TA-MAX) up to the value of TP-MAX as long as the maximum
temperature at the device's footprint thermal pad on the printed circuit board remains less than TP-MAX
.
(2) The recommended maximum operating junction temperature assumes the junction to package bottom thermal resistance, RθJC(bottom)
1.1°C/W, the thermal resistance of the device thermal pad connection to the PCB footprint is negligible, and the recommended
maximum temperature at the PCB footprint thermal pad, TP-MAX, is satisfied.
=
Copyright © 2015–2017, Texas Instruments Incorporated
7
ADC14X250
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
www.ti.com.cn
UNIT
6.4 Thermal Information
THERMAL METRIC(1)
RHB (WQFN)
(32 PINS)
31.4
50.2
1.1
RθJA
Thermal resistance, junction to ambient
RθJC(top)
RθJC(bottom)
RθJB
Thermal resistance, junction to package top
Thermal resistance, junction to package bottom
Thermal resistance, junction to board
°C/W
5.1
φJT
Characterization parameter, junction to package top
Characterization parameter, junction to board
0.2
φJB
5.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: Static Converter Performance
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
external differential resistive termination at ADC input is 66 Ω. Typical values are at TA = 25°C, unless otherwise noted. Limit
values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
FSR
Bit resolution of ADC core
14
Bits
Full scale range
Differential peak-to-peak
1.7
Vpp
Gain variation
GVAR
VOFF
DNL
±0.05
±3
dB
mV
LSB
1-sigma variation of full scale range across multiple units
Input referred voltage offset
+0.27
–0.18
Differential non-linearity
Integral non-linearity
+1
–0.9
INL
LSB
6.6 Electrical Characteristics: Dynamic Converter Performance
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
external differential resistive termination at ADC input is 66 Ω. CLKIN± input is a 2 Vp-p differential sinusoid. Typical values
are at TA = 25°C, unless otherwise noted. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
3-dB bandwidth
Frequency at which the voltage input to digital output
response deviates by 3 dB compared to low frequencies for
a low impedance differential signal applied at the input pins.
Includes 0.5-nH parasitic inductance in series with each pin
of the differential analog input.
BW3dB
800
MHz
Signal-to-noise ratio, integrated across entire Nyquist
bandwidth
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 240 MHz, –40 dBFS
Input = 300 MHz, –3 dBFS
71.1
70.9
70.5
70.1
71.1
69.7
SNR
dBFS
68.3
8
Copyright © 2015–2017, Texas Instruments Incorporated
ADC14X250
www.ti.com.cn
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
Electrical Characteristics: Dynamic Converter Performance (continued)
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
external differential resistive termination at ADC input is 66 Ω. CLKIN± input is a 2 Vp-p differential sinusoid. Typical values
are at TA = 25°C, unless otherwise noted. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Signal-to-noise and distortion ratio, integrated across Nyquist
bandwidth
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 240 MHz, –40 dBFS
Input = 300 MHz, –3 dBFS
71.0
70.8
70.0
70.0
71.0
69.4
SINAD
ENOB
NSD
dBFS
Signal-to-noise and distortion ratio, integrated across Nyquist
bandwidth
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 300 MHz, –3 dBFS
11.5
11.5
11.3
11.3
11.2
Bits
Noise spectral density, average NSD across Nyquist
bandwidth
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 240 MHz, –40 dBFS
Input = 300 MHz, –3 dBFS
Spurious free dynamic range, single tone
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 300 MHz, –3 dBFS
2nd order harmonic distortion
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 300 MHz, –3 dBFS
3rd order harmonic distortion
Input = 10 MHz, –3 dBFS
Input = 70 MHz, –3 dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
Input = 300 MHz, –3 dBFS
–152.1
–151.9
–151.5
–151.1
–152.1
–150.7
dBFS/Hz
93
92
80
87
86
SFDR
dBFS
dBFS
dBFS
75
–75
–75
–95
–95
–92
–90
–90
HD2
–95
–95
–80
–87
–86
HD3
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
www.ti.com.cn
Electrical Characteristics: Dynamic Converter Performance (continued)
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
external differential resistive termination at ADC input is 66 Ω. CLKIN± input is a 2 Vp-p differential sinusoid. Typical values
are at TA = 25°C, unless otherwise noted. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Largest spurious tone, not including DC, HD2 or HD3
Input = 10 MHz, –3 dBFS
–95
–95
–92
–92
–92
Input = 70 MHz, –3 dBFS
Non HD2, HD3
dBFS
Input = 170 MHz, –3 dBFS
Input = 240 MHz, –3 dBFS
–80
Input = 300 MHz, –3 dBFS
Third-order intermodulation, dual tone
IMD3
dBFS
Tone 1 = 235 MHz, –10 dBFS
Tone 2 = 240 MHz, –10 dBFS
–94
10
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
6.7 Electrical Characteristics: Power Supply
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS.
Typical values are at TA = 25°C, unless otherwise noted. Limit values specified for the temperature range TA-MIN = –40°C to TP-
= 105°C.
MAX
PARAMETER
TEST CONDITIONS
MIN
2.85
1.7
TYP
3.0
1.8
1.2
95
MAX
3.45
1.9
UNIT
V
VA3.0
VA1.8
VA1.2
IA3.0
3.0V analog voltage supply
1.8V analog voltage supply
1.2V analog voltage supply
VA3.0 supply current consumption
VA1.8 supply current consumption
VA1.2 supply current consumption
V
1.15
1.25
V
mA
mA
mA
IA1.8
112
78
IA1.2
Total power
Normal operation(2)
584
600
consumption of the
VA3.0 , VA1.8 , VA1.2
supplies(1)
Power consumption during power-down state, external clock
active
PT
38
mW
V
Power consumption during sleep state, external clock active
Do not load the BP2.5 pin
38
VBP2.5
BP2.5 bias voltage
2.65
Supply sensitivity to noise
Power of spectral spur resulting from a 100-mV sinusoidal signal modulating a supply
at 500 kHz. Analog input is a –3 dBFS 150-MHz single tone. In all cases, the spur
appears as part of a pair symmetric about the fundamental that scales proportionally
with the fundamental amplitude.
dBFS
VA3.0
VA1.8
VA1.2
–72.5
–58.0
–37.7
(1) Power values indicate consumption during normal conversion assuming an established JESD204 link.
(2) The power limit applies to an ambient temperature and board thermal pad temperature of 25°C.
6.8 Electrical Characteristics: Analog Interface
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
external differential resistive termination at ADC input is 66 Ω. Typical values are at TA = 25°C. Limit values specified for the
temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDIONS
MIN
TYP
MAX UNIT
Input common mode voltage reference voltage at the VCM pin
Varies with temperature
VCM
IVCM
1.6
V
Input common mode voltage reference current sourcing or sinking on VCMA or
VCMB pins.(1)
1
mA
mV
Input common mode voltage offset range
Allowable difference between the common mode applied to the analog input and
the bias voltage at the VCM bias pin.
VCM-OFF
50
Input termination resistance
Differential
RIN
CIN
200
3.7
Ω
Input capacitance, differential
pF
(1) This parameter is verified by design.
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6.9 Digital Input Characteristics
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS.
Typical values are at TA = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLKIN+/-
Maximum Input differential voltage(1)(2)
Differential peak voltage
VID-MAX
1000
mV
Minimum Input differential voltage(1)
Differential peak voltage
Recommended minimum edge slew rate at the zero crossing(1)
VID-MIN
dVSS/dt
VIS-BIAS
250
1
mV
V/ns
V
(1)
Input offset voltage internal bias
0.5
Internally biased
Externally applied input offset voltage(2)(3)
Allowable common mode voltage range for DC coupled interfaces
VIS-IN
0.5 ± 0.1
V
Zrdiff
Differential termination resistance at DC(4)
Common-mode bias source impedance(4)(3)
Differential termination capacitance(3)
100
11
Ω
Ztt
kΩ
pF
CT
1.5
SYSREF+/-
Maximum Input differential voltage(1)(2)
Differential peak voltage
Minimum Input differential voltage(1)
Differential peak voltage
VID-MAX
VID-MIN
VIS-BIAS
VIS-IN
1000
mV
mV
V
250
0.5
(1)
Input offset voltage bias
Internally biased
Externally applied input offset voltage(2)(3)
Allowable common mode voltage range for DC coupled interfaces
0.5 ± 0.1
V
Zrdiff
Ztt
Differential termination resistance at DC(4)
Common-mode bias source impedance(4)(3)
Differential termination capacitance(4)(3)
2.2
11
kΩ
kΩ
pF
CT
0.8
SYNCb+/-
(1)(2)
Input differential voltage
VID
350
mV
V
Differential peak voltage
1.25 ±
0.75
VIS-IN
Externally applied input offset voltage(1)(2)
Zrdiff
CT
Differential termination resistance(4)
Differential termination capacitance(4)(3)
110
1.0
Ω
pF
(1) Specification applies to the electrical level diagram of 图 1
(2) The voltage present at the pins should not exceed Absolute Maximum limits
(3) This parameter is verified by design.
(4) Specification applies to the electrical circuit diagram of 图 2
12
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
6.10 Electrical Characteristics: Serial Data Output Interface
Unless otherwise noted, these specifications apply for VA3.0 = 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS.
Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SERIAL LANE OUTPUT CHARACTERISTICS (SO)
570
660
750
Output differential voltage(1)
Differential peak-peak values. Assumes ideal 100-Ω load. De-
emphasis disabled.
840
930
VOD
mV
Configurable via SPI.
1030
1130
1200
Short circuit current. SO+ terminal shorted to GND during logic high
output signal state.
ISC
19
mA
VOD and Rdeemp configured to default values.
Differential output impedance at DC.(2)
VOD configured to default value.
Zddiff
100
Ω
Differential output return loss magnitude
Relative to 100 Ω; For frequencies between 100 MHz and
0.75*Baud_Rate (5.5 GHz max); VOD and Rdeemp configured to
default values.
RLddiff
–11
dB
dB
0
1.4
3.4
4.9
5.9
7.4
8.9
12.1
Transmitter de-emphasis values
VOD configured to 4.
Configurable via SPI.
Rdeemp
(1) Specification applies to the electrical level diagram of 图 3
(2) Specification applies to the electrical circuit diagram of 图 4
6.11 Electrical Characteristics: Digital Input
Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS.
Typical values are at TA = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT CHARACTERISTICS (SDI, SCLK, CSB)
Logical 1 input voltage(1)
Inputs are compatible with 1.2-V up to 3-V logic.
VIH
0.9
V
VIL
IIN0
IIN1
CIN
Logical 0 input voltage(1)
Logic low input current
Logic high input current
Input capacitance(2)
0.3
V
0.04
0.04
2
uA
uA
pF
DIGITAL OUTPUT CHARACTERISTICS (SDO)
Logical 1 output voltage(1)(3)
(3)
VOH
VSPI = 1.2, 1.8, 2.5, or 3 V ; Configurable via SPI.
VSPI – 0.3
VSPI
V
V
Default VSPI = 3 V, IOH = 400 µA
Logical 0 output voltage(1)(3)
IOL = –400 µA.
VOL
0
0.3
+ISC
–ISC
Logic high short circuit current. Applies to VSPI = 1.8 V
Logic low short circuit current. Applies to VSPI = 1.8 V
18
14
mA
mA
(1) Specification applies to the electrical level diagram of 图 5.
(2) This parameter is verified by design.
(3) The SPI_CFG register must be changed to a supported output logic level after power up and before a read command is executed. Until
that time, the output voltage on SDO may be as high as the VA3.0 supply during a read command. The SDO output is high-Z at all times
except during a read command.
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6.12 Timing Requirements
Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS. VSPI
1.8 V(1). Typical values are at TA = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC SAMPLING INSTANT TIMING CHARACTERISTICS
Sampling Rate
FS
50
250
MSPS
Equal to FCLKIN / CLKDIV
Input Clock Frequency at CLKIN Inputs
CLKDIV = 1
50
100
200
400
30
250
500
1000
2000
70
FCLKIN
CLKDIV = 2
CLKDIV = 4
CLKDIV = 8
MHz
%
Input clock (CLKIN) duty
cycle
CLKDIV = 1
CLKDIV = 2, 4, 8(2)
50
50
DC
45
55
ADC core latency
Delay from a reference sampling instant to the boundary of the
internal LMFC where the reference sample is the first sample of the
next transmitted multi-frame. In this device, the frame clock period is
equal to the sampling clock period.
Frame clock
cycles
tLAT-ADC
8.5
Additive sampling aperture jitter
Depends on input CLKIN differential edge rate at the zero crossing,
dVSS/dt. Tested with 5 V/ns edge rate.
tJ
fs
CLKDIV = 1
105
140
CLKDIV = 2, 4, 8
SYSREF TIMING CHARACTERISTICS
SYSREF assertion duration
tPH-SYS
Frame clock
cycles
2
2
Required duration of SYSREF assertion after rising edge event
SYSREF de-assertion duration
Frame clock
cycles
tPL-SYS
tS-SYS
tH-SYS
Required duration of SYSREF de-assertion after falling edge event
SYSREF setup time
430
ps
ps
Relative to CLKIN rising edge
SYSREF hold time
–100
Relative to CLKIN rising edge
JESD204B INTERFACE LINK TIMING CHARACTERISTICS
SYSREF to LMFC delay
Functional delay between SYSREF assertion latched and LMFC
frame boundary. Depends on CLKDIV setting. Multiply the delay value
by the CLKDIV factor to convert to units of CLKIN clock cycles.
Frame clock
cycles
tD-LMFC
CLKDIV = 1
CLKDIV = 2
CLKDIV = 4
CLKDIV = 8
3.5
4
3.75
3.625
LMFC to K28.5 delay
Functional delay between the start of the first K28.5 frame during
Code Group Synchronization at the serial output and the preceding
LMFC frame boundary.
tD-K28
7
7.4
9
LMFC to ILA delay
Frame clock
cycles
Functional delay between the start of the first ILA frame during Initial
Lane Synchronization at the serial output and the preceding LMFC
frame boundary
tD-ILA
7
7
7.4
7.4
9
9
LMFC to valid data delay
Functional delay between the start of the first valid data frame at the
serial output and the preceding LMFC frame boundary.
tD-DATA
(1) All timing specifications for the SPI given for VSPI = 1.8-V logic levels and a 5-pF capacitive load on the SDO output. Timing specification
may require larger margins for VSPI= 1.2 V.
(2) This parameter is verified by design.
14
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
Timing Requirements (continued)
Unless otherwise noted, these specifications apply for VA3.0= 3 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS. VSPI
1.8 V(1). Typical values are at TA = 25°C. Limit values specified for the temperature range TA-MIN = –40°C to TP-MAX = 105°C.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYNCb assertion hold time
Required SYNCb hold time after assertion before de-assertion to
initiate a link re-synchronization.
Frame clock
cycles
tH-SYNCb
4
ILA duration
Duration of the ILA sequence .
Multi-frame
clock cycles
tILA
4
SERIAL OUTPUT DATA TIMING CHARACTERISTICS
FSR
Serial bit rate
1.0
5.0
Gb/s
ps
Unit Interval
5.0 Gb/s Data Rate
UI
200
tR, tF
Edge transition rise and fall times
40
ps
Deterministic jitter
0.032
p-p UI
Includes periodic jitter (PJ), data dependent jitter (DDJ), duty cycle
distortion (DCD), and inter-symbol interference (ISI); 5.0 Gb/s data
rate.
DJ
6.33
p-p ps
0.118
1.48
p-p UI
rms ps
p-p UI
Random jitter
RJ
TJ
Assumes BER of 1e-15 (Q = 15.88); 5.0 Gb/s data rate
Total jitter
0.148
Sum of DJ and RJ. Assumes BER of 1e-15 (measured Q = 15.6); 5.0
Gb/s data rate.
29.56
p-p ps
SPI BUS TIMING CHARACTERISTICS(1)
Serial clock frequency
fSCLK = 1 / tP
fSCLK
20
MHz
tPH
SCLK pulse width – high
SCLK pulse width – low
SDI input data setup time
SDI input data hold time
SDO output data driven-to-3-state time
SDO output data 3-state-to-driven time
SDO output data delay time
CSB setup time
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPL
tSSU
tSH
5
tODZ
tOZD
tOD
15
15
20
tCSS
tCSH
5
5
CSB hold time
Inter-access gap
Minimum time CSB must be de-asserted between accesses
tIAG
5
ns
VID
VSS
VI+
VI-
dVSS/dt
VI-
VI+
VIS
GND
VI+ and VI- referenced to GND
VID = |VI+ œ VI-|
VI+ referenced to VI-
VSS = 2*|VI+ œ VI-|
VIS = |VI+ + VI-| / 2
图 1. Electrical Level Diagram for Differential Input Signals
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Zrdiff / 2
VI+
VI-
Ztt
C
T
+
-
VIS
Zrdiff / 2
图 2. Simplified Electrical Circuit Diagram for Differential Input Signals
½ VOD
+
VO
-
VO
VOS
GND
VO+ and VO- referenced to GND
-
VOD = 2*|VO+ œ VO |
-
VOS = |VO+ + VO | / 2
图 3. Electrical Level Diagram for Differential Output Signals
Zrdiff / 2
+
VO
Ztt
-
VO
+
-
VOS
Zrdiff / 2
图 4. Electrical Circuit Diagram for Differential Output Signals
VOH
VIH
VIL
Input
Output
VOL
图 5. Electrical Level Diagram for Single-ended Digital Inputs and Outputs
Sample N
V
IN
t
AD
1
f
S
Clock N
CLKIN
(CLKDIV=1)
S2SO Device Latency
= t + t
t
H-SYS
LAT-ADC
D-DATA
SYSREF
t
S-SYS
t
CLK-DATA
SA0
1st
2nd
(L=1, F=2)
Octet
Octet
Digitized
Sample N
图 6. Sample to Data Timing Diagram
16
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
st
th
th
24 clock
1
clock
16 clock
SCLK
CSB
t
CSS
t
t
PH
t
t
CSS
PL
CSH
t
CSH
t
IAG
t
= 1/f
SCLK
P
t
t
SH
SS
t
t
SH
SS
SDI
D7
D7
D1
D1
D0
Write Command
D0
COMMAND FIELD
Hi-Z
t
OD
Hi-Z
SDO
t
t
OZD
ODZ
Read Command
图 7. SPI Timing Diagram
SYSREF assertion
latched
SYNCb assertion
latched
SYNCb de-assertion
latched
t
S-SYNCb-F
t
S-SYNCb
t
S-SYNCb-F
t
H-SYNCb-F
K28.5
SYNCb
t
ILA
ILA
D-ILA
XXX
XXX
K28.5
ILA
Valid Data
Serial Data
t
S-SYS
t
t
t
D-DATA
D-K28
t
H-SYS
CLKIN
SYSREF
t
PL-SYS
t
PH-SYS
Tx Frame Clk
t
Tx LMFC Boundary
D-LMFC
Code Group
Synchronization
Initial Frame and Lane
Synchronization
Data
Transmission
Frame Clock
Alignment
图 8. JESD204B Interface Link Initialization Timing Diagram
For more information, see the Functional Block Diagram.
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6.13 Typical Characteristics
Unless otherwise noted, these specifications apply for VA3.0 = 3.0 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
240-MHz input frequency; –3-dBFS input power. External termination at ADC input is 66 Ω differential. CLKIN± input is a 2
Vp-p differential sinusoid. Typical values are at TA = 25°C.
1
0.8
0.6
0.4
0.2
0
4
3
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
0
4096
8192
Code
12288
16384
0
4096
8192
Code
12288
16384
Input Frequency = 10 MHz
Input Frequency = 10 MHz
图 9. Differential Non-Linearity (DNL)
图 10. Integral Non-Linearity (INL)
1
4
0.8
0.6
0.4
0.2
0
3
2
1
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
-4
1.15
1.175
1.2
1.225
1.25
1.15
1.175
1.2
1.225
1.25
VA1.2 Supply [V]
VA1.2 Supply [V]
Input Frequency = 10 MHz
Input Frequency = 10 MHz
图 11. DNL vs VA1.2 Supply
图 12. INL vs VA1.2 Supply
110
105
100
95
110
105
100
95
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
90
90
SNR [dBFS]
85
85
SINAD [dBFS]
SFDR [dBFS]
80
80
75
75
70
70
65
65
60
60
0
50
100
150
200
250
300
350
-70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Input Amplitude [dBFS]
0
Input Frequency [MHz]
图 13. SNR, SINAD, SFDR vs Input Frequency
图 14. SNR, SINAD, SFDR vs Input Power
18
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
Typical Characteristics (接下页)
Unless otherwise noted, these specifications apply for VA3.0 = 3.0 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
240-MHz input frequency; –3-dBFS input power. External termination at ADC input is 66 Ω differential. CLKIN± input is a 2
Vp-p differential sinusoid. Typical values are at TA = 25°C.
110
105
100
95
110
105
100
95
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
90
90
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
85
85
80
80
75
75
70
70
65
65
60
60
50
100
150
Sampling Rate [MSPS]
200
250
2.85
2.95
3.05
3.15
3.25
3.35
3.45
VA3.0 Supply Voltage [V]
Input Frequency = 10 MHz
Nominal Supplies:
VA1.8 = 1.8 V
VA1.2 = 1.2 V
图 15. SNR, SINAD, SFDR vs Sampling Rate
图 16. SNR, SINAD, SFDR vs VA3.0 Supply
110
105
100
95
110
105
100
95
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
90
90
85
85
80
80
75
75
70
70
65
65
60
60
1.7
1.75
1.8
1.85
1.9
1.15
1.175
1.2
1.225
1.25
VA1.8 Supply Voltage [V]
VA1.2 Supply Voltage [V]
Nominal Supplies:
VA3.0 = 3.0 V
VA1.2 = 1.2 V
Nominal Supplies:
VA3.0 = 3.0 V
VA1.8 = 1.8 V
图 17. SNR, SINAD, SFDR vs VA1.8 Supply
图 18. SNR, SINAD, SFDR vs VA1.2 Supply
110
105
100
95
-60
-65
SNR [dBFS]
SINAD [dBFS]
SFDR [dBFS]
HD2 [dBFS]
HD3 [dBFS]
Non-HD2,HD3 [dBFS]
THD [dBFS]
-70
-75
90
-80
85
-85
80
-90
75
-95
70
-100
-105
-110
65
60
-40
-20
0
20
40
60
80
100
0
50
100
150
200
250
300
350
Temperature [èC]
Input Frequency [MHz]
图 19. SNR, SINAD, SFDR vs Temperature
图 20. HD2, HD3, Non-HD2/HD3, THD vs Input Frequency
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Typical Characteristics (接下页)
Unless otherwise noted, these specifications apply for VA3.0 = 3.0 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
240-MHz input frequency; –3-dBFS input power. External termination at ADC input is 66 Ω differential. CLKIN± input is a 2
Vp-p differential sinusoid. Typical values are at TA = 25°C.
-70
-70
HD2 [dBFS]
HD2 [dBFS]
HD3 [dBFS]
Non-HD2,HD3 [dBFS]
THD [dBFS]
HD3 [dBFS]
Non-HD2,HD3 [dBFS]
THD [dBFS]
-75
-75
-80
-80
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-110
-70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
Input Amplitude [dBFS]
0
50
100
150
200
250
Sampling Rate [MSPS]
Input Frequency = 10 MHz
图 21. HD2, HD3, Non-HD2/HD3, THD vs Input Power
图 22. HD2, HD3, Non-HD2/HD3, THD vs Sampling Rate
-60
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
HD2 [dBFS]
HD3 [dBFS]
Non-HD2,HD3 [dBFS]
THD [dBFS]
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-100
-110
-120
-40
-20
0
20
40
60
80
100
0
25
50
75
100
125
Temperature [èC]
Frequency [MHz]
SNR = 71.0 dBFS
SFDR = 92 dBFS
Capture Depth = 65536 Samples
图 23. HD2, HD3, Non-HD2/HD3, THD vs Temperature
图 24. 1-Tone Spectrum (10 MHz)
0
0
-10
-10
-20
-30
-20
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency [MHz]
Frequency [MHz]
SNR = 70.9 dBFS
SFDR = 92 dBFS
Capture Depth = 65536 Samples
SNR = 70.1 dBFS
SFDR = 86 dBFS
Capture Depth = 65536 Samples
图 25. 1-Tone Spectrum (70 MHz)
图 26. 1-Tone Spectrum (240 MHz)
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Typical Characteristics (接下页)
Unless otherwise noted, these specifications apply for VA3.0 = 3.0 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
240-MHz input frequency; –3-dBFS input power. External termination at ADC input is 66 Ω differential. CLKIN± input is a 2
Vp-p differential sinusoid. Typical values are at TA = 25°C.
0
0.7
0.65
0.6
0.24
Total Power [W]
IA1.2 [A]
IA1.8 [A]
-10
-20
0.2
IA3.0 [A]
-30
-40
0.16
0.12
0.08
0.04
0
-50
-60
0.55
0.5
-70
-80
-90
-100
-110
-120
0.45
0.4
0
25
50
75
100
125
-40
-20
0
20
40
60
80
100
Frequency [MHz]
Temperature [èC]
Input Amplitude =
–9 dBFS/tone
IMD3 = –94 dBFS
Capture Depth =
65536 Samples
图 28. Power vs Temperature
图 27. 2-Tone Spectrum (235/240 MHz)
0.7
0.65
0.6
0.32
0.28
0.24
0.2
Total Power [W]
IA1.2 [A]
IA1.8 [A]
IA3.0 [A]
0.55
0.5
0.16
0.12
0.08
0.04
0
0.45
0.4
0.35
0.3
50
100
150
200
250
Sampling Rate [MSPS]
图 29. Power vs Sampling Rate
图 30. Output Serial Lane Eye Diagram at 5.0 Gb/s
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Typical Characteristics (接下页)
Unless otherwise noted, these specifications apply for VA3.0 = 3.0 V; VA1.8 = 1.8 V; VA1.2 = 1.2 V; FCLKIN = FS = 250 MSPS;
240-MHz input frequency; –3-dBFS input power. External termination at ADC input is 66 Ω differential. CLKIN± input is a 2
Vp-p differential sinusoid. Typical values are at TA = 25°C.
图 31. Transmitted Eye at Output of 20-inch, 5-mil. FR4 Microstrip at 5.0 Gb/s With Optimized De-Emphasis and Voltage Swing
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7 Parameter Measurement Information
7.1 JESD204B Interface Functional Characteristics
Unless otherwise noted, these specifications apply for all supply and temperature conditions.
PARAMETER
DESCRIPTION AND TEST CONDITIONS
Supported Configurations
VALUE
L = Number of lanes/converter
S = Samples per frame
F = Octets per frame
LSF
L = 1, S = 1, F = 2
Number of frames per multi-frame
Configurable via SPI
K
9 (min)
32 (max, default)
L = 1, S = 1, F = 2
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8 Detailed Description
8.1 Overview
The ADC14X250 device is a single channel analog-to-digital converter (ADC) composed of pipelined stages and
followed by a back-end JESD204B interface. The ADC core is preceded by an input buffer and imbalance
correction circuit at the analog input and is provided with the necessary reference voltages with internal drivers
that require no external components. The analog input common-mode is also internally regulated.
A DC offset correction block is disabled by default, but may also be enabled at the ADC core output to remove
DC offset. Processed data is passed into the JESD204B interface where the data is framed, encoded, serialized,
and output on one lane per channel. Data is serially transmitted by configurable high-speed voltage mode
drivers.
The sampling clock is derived from the CLKIN input via a low-noise receiver and clock divider. The CLKIN,
SYSREF, and SYNCb inputs provide the device clock, sysref, and sync~ signals to the JESD204B interface,
which are used to derive the internal local frame and local multi-frame clocks and establish the serial link.
Features of the ADC14X250 device are configurable through the 4-wire SPI.
8.2 Functional Block Diagram
SYSREF+
SYSREF-
CLKIN+
CLKIN-
SYNCb+
SYNCb-
DUTY CYCLE
STABILIZER
ó N
DIVIDER
VIN+
VCM
VIN-
PHASE &
AMPLITUDE
CORRECTION
BUFFER
SO+
SO-
14-BIT ADC
CM REF.
INTERNAL
REFERENCE
SDI
INTERNAL
SUPPLY
REGULATION
SDO
SCLK
CSB
CONTROL
REGISTERS
SPI
INTERFACE
BP2.5
8.3 Feature Description
8.3.1 Amplitude and Phase Imbalance Correction of Differential Analog Input
The ADC performance can be sensitive to amplitude and phase imbalance of the input differential signal and
therefore integrates a front-end balance correction circuit to optimize the second-order distortion (HD2)
performance of the ADC in the presence of an imbalanced input signal. 4-bit control of the phase mismatch and
3-bit control of the amplitude mismatch corrects the input mismatch before the input buffer. A simplified diagram
of the amplitude and phase correction circuit at the ADC input is shown in 图 32.
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Feature Description (接下页)
3
4
V +
IN
INPUT
BUFFER
V
-
IN
+
-
V
CM
图 32. Simplified Input Differential Balance Correction Circuit
Amplitude correction is achieved by varying the single-ended termination resistance of each input while
maintaining constant total differential resistance, thereby adjusting the amplitude at each input but leaving the
differential swing constant. Phase correction, also considered capacitive balance correction, varies the capacitive
load at the ADC input, thereby correcting a phase imbalance by creating a bandwidth difference between the
analog inputs that minimally affects amplitude. This function is useful for correcting the balance of transformers
or filters that drive the ADC analog inputs. 图 33 shows the measured HD2 resulting from an example 240-MHz
imbalanced signal input into the ADC14X250 device recorded over the available amplitude and phase correction
settings, demonstrating the optimization of HD2. Performance parameters in the Electrical Characteristics:
Dynamic Converter Performance are characterized with the amplitude and phase correction settings in the
default condition.
图 33. Gain and Phase Imbalance HD2 Optimization
8.3.2 Input Clock Divider
An input clock divider allows a high frequency clock signal to be distributed throughout the system and locally
divided down at the ADC device so that coupling of signals at common intermediate frequencies into other parts
of the system can be avoided. The frequency at the CLKIN input may be divided down to the sampling rate of the
ADC by factors of 1, 2, 4, or 8. Changing the clock divider setting initiates a JESD204 link re-initialization and
requires re-calibration of the ADC if the sampling rate is changed from the rate during the previous calibration.
8.3.3 SYSREF Offset Feature and Detection Gate
When the signal at the SYSREF input is not actively toggling periodically, the SYSREF signal is considered to be
in an idle state. The idle state is recommended at any time the ADC14X250 spurious performance must be
maximized. When the SYSREF signal is in the idle state for longer than 1 µs, an undesirable offset voltage may
build up across the AC coupling capacitors between the SYSREF transmitter and the ADC14X250 device input.
This offset voltage creates a signal threshold problem, requires a long time to dissipate, and therefore prevents
quick transition of the SYSREF signal out of the idle state. Two features are provided as a solution and are
shown in 图 50, namely the SYSREF offset feature and SYSREF detection gate.
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Feature Description (接下页)
In the case that the SYSREF signal idle state has a 0-V differential value, or if the ADC14X250 device must be
insensitive to noise that may appear on the SYSREF signal, then the SYSREF detection gate may be used. The
detection gate is the AND gate shown in 图 50 that enables or disables propagation of the SYSREF signal
through to the internal device logic. If the detection gate is disabled and a false edge appears at the SYSREF
input, the signal does not disrupt the internal clock alignment. Note that the SYSREF detection gate is disabled
by default; therefore, the device does not respond to a SYSREF edge until the detection gate is enabled.
The SYSREF offset and detection gate features are both controlled through the SPI.
8.3.4 DC Offset Correction
DC offset correction is provided using a digital high-pass IIR filter at the immediate output of the ADC core. The
DC offset correction is bypassed by default, but may be enabled and configured via the SPI. The 3-dB bandwidth
of the IIR digital correction filter may be set to four different low-frequency values. When DC offset correction is
enabled, any signal in the stop-band of the high-pass filter is attenuated. The settling time of the DC offset
correction is approximately equal to the inverse of the 3-dB bandwidth setting.
8.3.5 Serial Differential Output Drivers
The differential drivers of the ADC14X250 device that output the serial JESD204B data are voltage mode drivers
with amplitude control and de-emphasis features that may be configured through the SPI for a variety of different
channel applications. Eight amplitude control (VOD) and eight de-emphasis control (DEM) settings are available.
Both VOD and DEM register fields must be configured to optimize the noise performance of the serial interface
for a particular lossy channel.
The output common-mode of the driver varies with the configuration of the output swing. Therefore, AC coupling
is strongly recommended between the ADC14X250 device and the device receiving the serial data.
8.3.5.1 De-Emphasis Equalization
De-emphasis of the differential output is provided as a form of continuous-time linear equalization that imposes a
high-pass frequency response onto the output signal to compensate for frequency-dependent attenuation as the
signal propagates through the channel to the receiver. In the time-domain, the de-emphasis appears as the bit
transition transient followed by an immediate reduction in the differential amplitude, as shown in 图 34. The
characteristic appearance of the waveform changes with differential amplitude and the magnitude of de-
emphasis applied. The serial lane rate determines the available period of time during which the de-emphasis
transient settles. However, the lane rate does not affect the settling behavior of the applied de-emphasis.
图 34. De-emphasis of the Differential Output Signal
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Feature Description (接下页)
表 1 indicates the typical measured values for the de-emphasis range, where the de-emphasis value is measured
as the ratio (in units of [dB]) between the peak voltage after the signal transition to the settled voltage value in
one bit period. The data rate for this measurement is 1.2 Gb/s to allow settling of the de-emphasis transient. 表 1
illustrates the actual de-emphasis value in terms of voltage attenuation and shows dependence on the amplitude
setting, but does not reflect the optimal amplitude setting (VOD) and de-emphasis setting (DEM) for a particular
lossy channel. 表 2 shows the amplitude of the differential signal swing during its settled state after the transition
transient. The measurement is performed at 1.2 Gb/s and the units are in differential peak-to-peak mV.
表 1. De-Emphasis Values (dB) for All VOD and DEM Configuration Settings
DEM
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
–0.2
–0.4
–0.7
–1.0
–1.4
–1.7
–2.1
–2.5
–1.1
–1.7
–2.2
–2.8
–3.4
–3.9
–4.4
–4.9
–2.2
–2.9
–3.5
–4.2
–4.9
–5.5
–6.0
–6.5
–3.0
–3.8
–4.5
–5.2
–5.9
–6.5
–7.1
–7.6
–4.3
–5.1
–5.9
–6.7
–7.4
–8.0
–8.6
–9.2
–5.6
–6.5
–7.4
–8.1
–8.9
–9.5
–10.2
–10.7
–8.5
–9.6
–10.4
–11.2
–12.1
–12.7
–13.4
–14.0
VOD
表 2. Settled Differential Voltage Swing Values, VOD (mV-peak-peak) for All VOD and DEM Configuration
Settings
DEM
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
570
660
750
840
940
1020
1110
1200
550
630
690
750
800
840
870
900
500
550
580
610
630
650
670
680
440
470
500
520
530
550
560
570
400
430
450
460
470
480
490
500
350
370
380
390
400
410
410
420
300
310
320
330
340
340
340
350
210
220
230
230
230
240
240
240
VOD
8.3.6 ADC Core Calibration
After power-up, the ADC14X250 device detects that the supplies and clock are valid, waits for a power-up delay,
and then performs a calibration of the ADC core automatically. The power-up delay is 8.4 × 106 sampling clock
cycles or 33.6 ms at a 250-MSPS sampling rate. The calibration requires approximately 1.0 × 106 sampling clock
cycles.
If the system requires that the ADC14X250 input clock divider value (CLKDIV) is set to 2, 4, or 8, then ADC
calibration must be performed manually after CLKDIV has been set to the desired value. Manual calibration is
performed by changing to power down mode, returning to normal operation, and monitoring the CAL_DONE bit
in the JESD_STATUS register until calibration is complete. As an alternative to monitoring CAL_DONE, the
system may wait 1.5 × 106 sampling clock cycles until calibration is complete.
Re-calibration is not required across the supported operating temperature range to maintain functional
performance, but it is recommended for large changes in ambient temperature to maintain optimal dynamic
performance. Changing the sampling rate always requires re-calibration of the ADC core. For more information
about device modes, see Power-Down and Sleep Modes.
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8.3.7 Data Format
Data may be output in the serial stream as 2’s complement format by default or optionally as offset binary. This
formatting is configured through the SPI and is performed in the data path prior to JESD204B data framing,
scrambling and 8b/10b encoding.
8.3.8 JESD204B Supported Features
The ADC14X250 device supports a feature set of the JESD204B standard targeted to its intended applications
but does not implement all the flexibility of the standard. 表 3 summarizes the level of feature support.
表 3. ADC14X250 Feature Support for the JESD204B Serial Interface
Feature
Subclass
Supported
Not Supported
Subclass 0(1), 2
•
Subclass 1
•
•
Device Clock
(CLKIN) and
SYSREF
•
•
•
AC coupled CLKIN and SYSREF
DC coupled CLKIN and SYSREF (special cases)
Periodic, Pulsed Periodic and One-Shot SYSREF
Latency
•
Deterministic latency supported for subclass
implementations using standard SYSREF signal
1
Deterministic latency not supported for non-
standard implementations
Electrical layer
features
•
•
LV-OIF-11G-SR interface and performance
AC coupled serial lanes
•
•
TX lane polarity inversion
DC coupled serial lanes
Transport layer
features and
configuration
•
•
•
L = 1
K configuration
Scrambling
•
F, S, and HD configuration depends on L and is
not independently configurable
M, N, N’, CS, CF configuration
Idle link mode
•
•
•
Short and Long transport layer test patterns
Data link layer
features
•
•
•
8b/10b encoding
Lane synchronization
D21.5, K28.5, ILA, PRBS7, PRBS15, PRBS23, Ramp test
sequences
•
RPAT/JSPAT test sequences
(1) The ADC14X250 supports most subclass 0 requirements, but is not strictly subclass compliant.
8.3.9 Transport Layer Configuration
The transport layer features supported by the ADC14X250 device are a subset of possible features described in
the JESD204B standard. The configuration options are intentionally simplified to provide the lowest power and
most easy-to-use solution.
8.3.9.1 Lane Configuration
The ADC14X250 outputs all digital data on a single JESD204B serial lane. The serial-data lane transmits at 20
times the sampling rate. A 250 MSPS sampling rate corresponds to a 5.0 Gb/s per lane rate.
8.3.9.2 Frame Format
The format of the data arranged in a frame is fixed. The octets per frame (F), samples per frame (S), and high-
density mode (HD) parameters are not independently configurable. The N, N’, CS, CF, M, and HD parameters
are fixed and not configurable. 图 35 shows the data format.
L=1
S=1
F=2
N=16
CS=0
N‘=16
D[13:0] = Sampled Data
0 = Zero padded bit
Octet 0
Octet 1
(MSB)
(LSB) (MSB)
(LSB)
0
D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0
Lane
图 35. Transport Layer Definitions for the Supported-Lane Configurations
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8.3.9.3 ILA Information
表 4 summarizes the information transmitted during the initial lane alignment (ILA) sequence. Mapping of these
parameters into the data stream is described in the JESD204B standard.
表 4. Configuration of the JESD204B Serial-Data Receiver
Paramet
Description
Logical Value
Encoded Value
er
ADJCNT DAC LMFC adjustment
0
0
0
0
0
0
ADJDIR DAC LMFC adjustment direction
BID
Bank ID
Number of control words per frame clock period
per link
CF
0
0
CS
DID
F
Number of control bits per sample
Device identification number
Number of octets per frame (per lane)(1)
High-density format
0
0
0
0
2
1
HD
JESDV
K
0
0
JESD204 version
1
1
Number of frames per multi-frame(1)
Number of lanes per link(1)
Lane identification number
Set by register as 9 to 32
8 to 31
L
1
0
0
0
LID
M
Number of converters per device(1)
1
1
(1)
N
Converter resolution
16
16
0
15
15
0
N’
Total number of bits per sample(1)
PHADJ
Phase adjustment request to DAC
Number of samples per converter per frame
cycle(1)
S
1
0
0 or 1
1
Set by register as 0
(disabled) or 1
SCR
Scrambling enabled
SUBCLA
SSV
Device subclass version
1
RES1
RES2
FCHK
Reserved field 1
Reserved field 2
Checksum
0
0
0
0
34 + (K-1) + SCR
(1) These parameters have a binary-value-minus-1 encoding applied before being mapped into the link configuration octets. For example, F
= 1 is encoded as 0.
Scrambling of the output serial data is supported and conforms to the JESD204B standard. Scrambling is
disabled by default, but may be enabled via the SPI. When scrambling is enabled, the ADC14X250 device
supports the early synchronization option by the receiver during the ILA sequence, although the ILA sequence
data is never scrambled.
8.3.10 Test Pattern Sequences
The SPI may enable the following test pattern sequences. Short- and long-transport layer, RPAT, and JSPAT
sequences are not supported.
表 5. Supported Test Pattern Sequences
Test Pattern
Description
Alternating 1 and 0 pattern (101010...)
Continuous K28.5 symbols
Common Purpose
Jitter or system debug
D21.5
K28.5
System debug
System debug
Repeated ILA
ILA repeats indefinitely
After ILA, a sample ramp is transmitted with programmable
step. The 16-bit output word fully spans both octets that
compose a sample.
Ramp
System debug and transport layer verification
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表 5. Supported Test Pattern Sequences (接下页)
Test Pattern
PRBS
Description
Common Purpose
PRBS 7/15/23 Complies with ITU-T O.150 specification and is
compatible with J-BERT equipment
Jitter and bit error rate testing
8.3.11 JESD204B Link Initialization
A JESD204B link is established via link initialization, which involves the following steps: frame alignment, code
group synchronization, and initial lane synchronization. These steps are shown in 图 36. Link initialization must
occur between the transmitting device (ADC14X250) and receiving device before sampled data may be
transmitted over the link. The link initialization steps described here are specifically for the ADC14X250 device,
supporting JESD204B subclass 1.
SYSREF assertion
latched
SYNCb assertion
latched
SYNCb de-assertion
latched
t
S-SYNCb-F
t
S-SYNCb
t
S-SYNCb-F
t
H-SYNCb-F
K28.5
SYNCb
t
ILA
ILA
D-ILA
XXX
XXX
K28.5
ILA
Valid Data
Serial Data
t
S-SYS
t
t
t
D-DATA
D-K28
t
H-SYS
CLKIN
SYSREF
t
PL-SYS
t
PH-SYS
Tx Frame Clk
t
Tx LMFC Boundary
D-LMFC
Code Group
Synchronization
Initial Frame and Lane
Synchronization
Data
Transmission
Frame Clock
Alignment
图 36. Link-initialization Timing and Flow Diagram
8.3.11.1 Frame Alignment
The Frame Alignment step requires alignment of the frame and local multi-frame clocks within the ADC14X250
device to an external reference. This is accomplished by providing the device clock and SYSREF clock to the
CLKIN and SYSREF inputs, respectively. The ADC14X250 device aligns its frame clock and LMFC to any
SYSREF rising edge event, offset by a SYSREF-to-LMFC propagation delay.
The SYSREF signal must be source synchronous to the device clock; therefore, the SYSREF rising edge must
meet setup and hold requirements relative to the signal at the CLKIN input. If these requirements cannot be met,
then the alignment of the internal frame and multi-frame clocks cannot be ensured. As a result, a link may still be
established, but the latency through the link cannot be deterministic. Frame alignment may occur at any time;
although, a re-alignment of the internal frame clock and LMFC will break the link. Note that frame alignment is
not required for the ADC14X250 device to establish a link because the device automatically generates the clocks
on power-up with unknown phase alignment.
8.3.11.2 Code Group Synchronization
Code Group Synchronization is initiated when the receiver sends a synchronization request by asserting the
SYNCb input of the ADC14X250 device to a logic low state (SYNCb+ < SYNCb–). After the SYNCb assertion is
detected, the ADC14X250 device outputs K28.5 symbols on all serial lanes that are used by the receiver to
synchronize and time align its clock and data recovery (CDR) block to the known symbols. The SYNCb signal
must be asserted for at least 4 frame clock cycles otherwise the event is ignored by the ADC14X250 device.
Code group synchronization is completed when the receiver de-asserts the SYNCb signal to a logic high state.
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After the ADC14X250 detects a de-assertion of its SYNCb input, the Initial Lane Synchronization step begins
on the following LMFC boundary. The ADC14X250 device outputs 4 multi-frames of information that compose
the ILA sequence. This sequence contains information about the data transmitted on the link. The initial lane
synchronization step and link initialization conclude when the ILA is finished and immediately transitions into
Data Transmission. During data transmission, valid sampled data is transmitted across the link until the link is
broken.
ADC Core Calibration Complete
(after power up or Power Down Mode Exit)
Initialize
Default
Frame Clock
and LMFC
Alignment
Sleep Mode Exit
Clock Alignment and
Synchronization Requests
SYSREF
Assertion
Detected
LMFC
Alignment
Error?
Frame
Alignment
Error?
YES
Re-align
Frame
Clock
YES
Serializer
PLL
Calibration
& LMFC
NO
NO
SYNCb
Assertion
Detected
Send K28.5
Characters
Wait for
Next LMFC
Boundary
SYNCb
De-Asserted?
NO
Send ILA
Sequence
Send Encoded
Sampled Data
YES
JESD204B Link
Initialization
Valid Data
Transfer
图 37. Device Start-Up and JESD204B Link Synchronization Flow Chart
The flowchart in 图 37 describes how the ADC14X250 device initializes the JESD204B link and reacts to
changes in the link. After the ADC core calibration is finished, the ADC14X250 device begins with PLL calibration
and link initialization using a default frame clock and LMFC alignment by sending K28.5 characters. PLL
calibration requires approximately 153×103 sampling clock cycles. If SYNCb is not asserted, then the device
immediately advances to the ILA sequence at the next LMFC boundary. Whereas, if SYNCb is asserted, then the
device continues to output K28.5 characters until SYNCb is de-asserted.
When a SYSREF rising edge event is detected, then the ADC14X250 device compares the SYSREF event to the
current alignment of the LMFC. If the SYSREF event is aligned to the current LMFC alignment, then no action is
taken and the device continues to output data. If misalignment is detected, then the SYSREF event is compared
to the frame clock. If misalignment of the frame clock is also detected, then the clocks are re-aligned and the link
is re-initialized. If the frame clock is not misaligned, then the frame clock alignment is not updated. In the cases
that a SYSREF event causes a link re-initialization, the ADC14X250 device begins sending K28.5 characters
without a SYNCb assertion and immediately transitions to the ILA sequence on the next LMFC boundary unless
the SYNCb signal is asserted. Anytime the frame clock and LMFC are re-aligned, the serializer PLL must
calibrate before code group synchronization begins. SYSREF events must not occur during ADC14X250 device
power-up, ADC calibration, or PLL calibration. The JESD_STATUS register is available to check the status of the
ADC14X250 device and the JESD204B link.
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If a SYNCb assertion is detected for at least 4 frame clock cycles, the ADC14X250 device immediately breaks
the link and sends K28.5 characters until the SYNCb signal is de-asserted.
When exiting sleep mode, the frame clock and LMFC are started with a default (unknown) phase alignment, PLL
calibration is performed, and the device immediately transitions into sending K28.5 characters.
8.3.12 Sync~ Signal Selection
The JESD204B sync~ signal can be directed to the internal JESD204B core block via two different input paths:
via the external pins or SPI. The selection MUX is controlled using the SYNC_SEL register field and sync~
control is performed using the JSYNC_N register field via SPI . By default, the signal is routed from the external
SYNCb+/- pins and writes to the JSYNC_N register field are ignored.
Optionally, the signal may be routed via SPI by setting the register field SYNC_SEL = 1. In this mode, signals at
the external SYNCb+/- pins are ignored and the sync~ signal is written to the JSYNC_N register field.
8.3.13 SPI
The SPI allows access to the internal configuration registers of the ADC through read and write commands to a
specific address. The interface protocol has a 1-bit command, 15-bit address word and 8-bit data word as shown
in 图 38. A read or write command is 24 bits in total, starting with the read or write command bit where 0
indicates a write command and 1 indicates a read command. The read or write command bit is clocked into the
device on the first rising edge of SCLK after CSb is asserted to 0. During a write command, the 15-bit address
and 8-bit data values follow the read or write bit MSB-first and are latched on the rising edge of SCLK. During a
read command, the SDO output is enabled shortly after the 16th rising edge of SCLK and outputs the read value
MSB first before the SDO output is returned to a high impedance state. The read or write command is completed
on the SCLK rising edge on which the data word’s LSB is latched. CSb may be de-asserted to 1 after the LSB is
latched into the device.
The SPI allows command streaming where multiple commands are made without de-asserting CSb in-between
commands. The commands in the stream must be of similar types, either read or write. Each subsequent
command applies to the register address adjacent to the register accessed in the previous command. The
address order can be configured as either ascending or descending. Command streaming is accomplished by
immediately following a completed command with another set of 8 rising edges of SCLK without de-asserting
CSb. During a write command, an 8-bit data word is input on the SDI input for each subsequent set of SCLK
edges. During a read command, data is output from SDO for each subsequent set of SCLK edges. Each
subsequent command is considered finished after the 8th rising edge of SCLK. De-asserting CSb aborts an
incomplete command.
The SDO output is high impedance at all times other than during the final portion of a read command. During the
time that the SDO output is active, the logic level is determined by a configuration register. The SPI output logic
level must be properly configured after power up and before making a read command to prevent damaging the
receiving device or any other device connected to the SPI bus. Until the SPI_CFG register is properly configured,
voltages on the SDO output may be as high as the VA3.0 supply during a read command. The default state of
SDO is to output 3 V logic levels during a read command. The SDI, SCLK, and CSB pins are all 1.2-V to 3-V
logic compatible.
32
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CSB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SCLK
COMMAND FIELD
DATA FIELD
R/W A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D6
D5
D4
D3
D2
D1
D1
D0
SDI
R=1
W=0
(MSB)
(LSB)
(MSB)
(LSB)
Address (15-bits)
Write DATA (8-bits)
Hi-Z
D7
D5
D4
D3
D2
D0
SDO
(MSB)
(LSB)
Read DATA (8-bits)
Single Access Cycle
图 38. Serial Interface Protocol
8.4 Device Functional Modes
8.4.1 Power-Down and Sleep Modes
Power-down and sleep modes are provided to allow the user to reduce the power consumption of the device
without disabling power supplies. Both modes reduce power consumption by the same amount but they differ in
the amount of time required to return to normal operation. Upon changing from Power Down back to Normal
operation, an ADC calibration routine is performed. Waking from sleep mode does not perform ADC calibration
(see ADC Core Calibration for more details). Neither power-down mode nor sleep mode resets configuration
registers.
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8.5 Register Map
表 6. ADC14X250 Register Map
Register
ADDRESS
DFLT
b[7]
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
CONFIG_A
0x0000
0x3C
SR
Res (0)
ASCEND
Res (1)
PAL[3:0]
Address 0x0001 Reserved
Reserved (000000)
Reserved (0000)
DEVICE _CONFIG
CHIP_TYPE
0x0002
0x0003
0x0004
0x0005
0x0006
0x00
0x03
0x01
0x00
0x00
PD_MODE[1:0]
CHIP_TYPE[3:0]
CHIP_ID[7:0]
CHIP_ID[15:8]
CHIP_VER[7:0]
CHIP_ID
CHIP _VER
Address 0x0007-0x000B Reserved
VENDOR_ID[7:0]
0x000C
0x000D
0x0010
0x51
0x04
0x01
VENDOR_ID
VENDOR_ID[15:8]
SPI_CFG
OM1
Reserved (000000)
VSPI[1:0]
Res(01)
SYS_E
N
0x0012
0x81
DF
Res (00)
IDLE[1:0]
CLKDIV
OM2
0x0013
0x0014
0x20
0x00
Reserved (001)
AMPADJ[2:0]
Res (0)
Res (0)
Res (0)
IMB_ADJ
Res (0)
PHADJ[3:0]
Address 0x0015-0x003C Reserved
Reserved (00000)
DC_MODE
SER_CFG
0x003D
0x0047
0x00
0x00
DC_TC
DC_EN
Address 0x003E-0x0046 Reserved
Res(0)
VOD[2:0]
Res (0)
DEM[2:0]
Address 0x0048-0x005F Reserved
SCR
_EN
JESD
_EN
JESD_CTRL1
JESD_CTRL2
0x0060
0x0061
0x7D
0x00
K_M1[4:0]
Reserved (00)
Res (0)
SYNC_S
EL
JSYNC_N
JESD_TEST_MODE[3:0]
0x0062
0x0063
0x01
0x00
JESD_RSTEP[7:0]
JESD_RSTEP[15:8]
JESD_RSTEP
JESD_STATUS
Address 0x0064-0x006B Reserved
REALIG
N
PLL
CAL
CLK
0x006C
N/A
Res (0)
LINK
SYNC
ALIGN
_LOCK
_DONE
_RDY
Address 0x006D- Reserved
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8.5.1 Register Descriptions
8.5.1.1 CONFIG_A, [Address: 0x0000], [Default: 0x3C]
表 7. CONFIG_A, [Address: 0x0000], [Default: 0x3C]
Bit
Field
Type
Reset
Description
7
SR
Read or write
0
Setting this soft reset bit causes all registers to be reset to their default
state. This bit is self-clearing.
6
5
Reserved
ASCEND
Read or write
Read or write
0
1
Reserved and must be written with 0.
Order of address change during streaming reads or writes.
0 : Address is decremented during streaming reads or writes.
1 : Address is incremented during streaming reads or writes (default).
4
Reserved
PAL[3:0]
Read
1
Reserved and must be written with 1.
3:0
Read or write
1100
Palindrome Bits are bit 3 = bit 4, bit 2 = bit 5, bit 1 = bit 6, and bit 0 =
bit 7.
8.5.1.2 DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]
表 8. DEVICE CONFIG, [Address: 0x0002], [Default: 0x00]
Bit
Field
Type
Reset
000000
00
Description
[7:2]
[1:0]
Reserved
Read or write
Read or write
Reserved and must be written with 000000.
PD_MODE
[1:0]
Power-down mode
00 : Normal operation (default)
01 : Reserved
10 : Sleep operation (faster resume)
11 : Power-down (slower resume)
8.5.1.3 CHIP_TYPE, [Address: 0x0003], [Default: 0x03]
表 9. CHIP_TYPE, [Address: 0x0003], [Default: 0x03]
Bit
Field
Type
Read or write
Read
Reset
0000
0011
Description
Reserved and must be written with 0000.
[7:4]
[3:0]
Reserved
CHIP_TYPE
Chip type that always returns 0x3, indicating that the part is a high-
speed ADC
8.5.1.4 CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]
表 10. CHIP_ID, [Address: 0x0005, 0x0004], [Default: 0x00, 0x01]
Bit
Field
Type
Read
Read
Reset
0x01
0x00
Description
0x0004[7:0] CHIP_ID[7:0]
0x0005[7:0] CHIP_ID[15:8]
Chip ID least significant word
Chip ID most significant word
8.5.1.5 CHIP_VERSION, [Address: 0x0006], [Default: 0x00]
表 11. CHIP_VERSION, [Address: 0x0006], [Default: 0x00]
Bit
Field
Type
Reset
Description
[7:0]
CHIP_VER
Read
0x00
Chip version
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8.5.1.6 VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]
表 12. VENDOR_ID, [Address: 0x000D, 0x000C], [Default: 0x04, 0x51]
Bit
Field
Type
Reset
Description
0x000C[7:0] VENDOR_ID
[7:0]
Read
0x51
Vendor ID. Texas Instruments vendor ID is 0x0451.
0x000D[7:0] VENDOR_ID
[15:8]
Read
0x04
8.5.1.7 SPI_CFG, [Address: 0x0010], [Default: 0x01]
表 13. SPI_CFG, [Address: 0x0010], [Default: 0x01]
Bit
Field
Reserved
VSPI
Type
Reset
000000
01
Description
[7:2]
[1:0]
Read or write
Read or write
Reserved and must be written with 000000.
SPI logic level controls the SDO output logic level.
00 : 1.2 V
01 : 3.0 V (default)
10 : 2.5 V
11 : 1.8 V
This register must be configured (written) before making a read
command on the SPI bus if the logic level is different that the VSPI
setting. The SPI inputs (SDI, SCLK, and CSb) are compatible with
logic levels ranging from 1.2 to 3 V.
8.5.1.8 OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]
表 14. OM1 (Operational Mode 1), [Address: 0x0012], [Default: 0x81]
Bit
Field
Type
Reset
Description
[7]
DF
Read or write
1
Output data format
0 : Offset binary
1 : Signed 2s complement (default)
[6:5]
[4:3]
Reserved
IDLE[1:0]
Read or write
Read or write
00
00
Reserved and must be written with 00.
SYSREF idle state offset configuration.
00 : No offset applied (default)
01 : SYSREF idles low (de-asserted) with –400-mV offset
10 : SYSREF idles high (asserted) with +400-mV offset
11 : Reserved
[2]
SYS_EN
Read or write
Read or write
0
SYSREF detection gate enable
0 : SYSREF gate is disabled; (input is ignored, default)
1 : SYSREF gate is enabled
[1:0]
Reserved[1:0]
01
Reserved. Must be written with 01.
8.5.1.9 OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]
表 15. OM2 (Operational Mode 2), [Address: 0x0013], [Default: 0x20]
Bit
Field
Type
Reset
001
00
Description
[7:5]
[4:3]
Reserved
CLKDIV[1:0]
Read or write
Read or write
Reserved and must be written with 001.
Clock divider ratio. Sets the value of the clock divide factor, CLKDIV
00 : Divide by 1, CLKDIV = 1 (default)
01 : Divide by 2, CLKDIV = 2
10 : Divide by 4, CLKDIV = 4
11 : Divide by 8, CLKDIV = 8
[2:0]
Reserved
Read or write
000
Reserved. Must be written with 000.
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8.5.1.10 IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]
表 16. IMB_ADJ (Imbalance Adjust), [Address: 0x0014], [Default: 0x00]
Bit
[7]
Field
Type
Reset
0
Description
Reserved
Read or write
Read or write
Reserved. Must be written with 0.
[6:4]
AMPADJ[2:0]
000
Analog input amplitude imbalance correction
7 = +30 Ω VIN+, –30 Ω VIN–
6 = +20 Ω VIN+, –20 Ω VIN–
5 = +10 Ω VIN+, –10 Ω VIN–
4 = Reserved
3 = –30 Ω VIN+, +30 Ω VIN–
2 = –20 Ω VIN+, +20 Ω VIN–
1 = –10 Ω VIN+, +10 Ω VIN–
0 = +0 Ω VIN+, –0 Ω VIN– (default)
Resistance changes indicate variation of the internal single-ended
termination.
[3:0]
PHADJ[3:0]
Read or write
0000
Analog input phase imbalance correction
15 = +1.68 pF VIN–
...
9 = +0.48 pF VIN–
8 = +0.24 pF VIN–
7 = +1.68 pF VIN+
...
2 = +0.48 pF VIN+
1 = +0.24 pF VIN+
0 = +0 pF VIN+, +0 pF VIN– (default)
Capacitance changes indicate the addition of internal capacitive load
on the given pin.
8.5.1.11 DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]
表 17. DC_MODE (DC Offset Correction Mode), [Address: 0x003D], [Default: 0x00]
DC_MODE (DC Offset Correction Mode)
Bit
Field
Type
Reset
00000
00
Description
Reserved and must be written as 00000.
Read or
write
[7:3]
[2:1]
Reserved
TC_DC
Read or
write
DC offset filter time constant.
The time constant determines the filter bandwidth of the DC high-pass filter.
TC_DC
Time Constant 3-dB Bandwidth
3-dB Bandwidth
(Normalized)
(FS = 250
MSPS)
(FS = 250
MSPS)
00
01
10
11
17 µs
130 µs
1.1 ms
8.4 ms
9.3 kHz
1.2 kHz
150 Hz
19 Hz
37e–6 × Fs
4.9e–6 × Fs
605e–9 × Fs
76e–9 × Fs
[0]
DC_EN
Read or
Write
0
DC offset correction enable
0 : Disable DC offset correction
1 : Enable DC offset correction
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8.5.1.12 SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]
表 18. SER_CFG (Serial Lane Transmitter Configuration), [Address: 0x0047], [Default: 0x00]
Bit
[7]
Field
Type
Reset
0
Description
Reserved
VOD[2:0]
Read or write
Read or write
Reserved. Must be written as 0.
[6:4]
000
Serial-lane transmitter driver output differential peak-peak-voltage amplitude.
000 : 0.570 V (default)
001 : 0.660 V
010 : 0.750 V
011 : 0.840 V
100 : 0.940 V
101 : 1.02 V
110 : 1.11 V
111 : 1.20 V
Reported voltage values are nominal values at low-lane rates with de-emphasis
disabled
[3]
Reserved
DEM[2:0]
Read or write
Read or write
0
Reserved and must be written as 0.
[2:0]
000
Serial lane transmitted de-emphasis.
De-emphasis value are for VOD configured to 100.
DEM
000
001
010
011
100
101
110
111
De-emphasis [dB]
0.0
1.4
3.4
4.9
5.9
7.4
8.9
12.1
8.5.1.13 JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]
表 19. JESD_CTRL1 (JESD Configuration Control 1) , [Address: 0x0060], [Default: 0x7D]
Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not
supported.
Bit
Field
Type
Reset
Description
[7]
SCR_EN
Read or write
0
Scrambler enable.
0 : Disabled (default)
1 : Enabled
Note:
•
JESD_EN must be set to 0 before altering this field.
[6:2]
K_M1[4:0]
Read or write
11111
Number of frames per multi-frame, K – 1.
The binary values of K_M1 represent the value (K – 1)
00000 : Reserved
00001 : Reserved
…
00111 : Reserved
01000 : K = 9
…
11111 : K = 32 (default)
Note:
•
K must be in the range 9 to 32. Values outside this range are
either reserved or may produce unexpected results.
•
JESD_EN must be set to 0 before altering this field.
[1]
[0]
Reserved
JESD_EN
Read or write
Read or write
0
1
Reserved and must be written as 0.
JESD204B link enable.
When enabled, the JESD204B link synchronizes and transfers data
normally. When the link is disabled, the serial transmitters output a
repeating, alternating 01010101 stream.
0 : Disabled
1 : Enabled (default)
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8.5.1.14 JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]
表 20. JESD_CTRL2 (JESD Configuration Control 2), [Address: 0x0061], [Default: 0x00]
Note: Before altering any parameters in this register, one must set JESD_EN = 0. Changing parameters while JESD_EN = 1 is not
supported.
Bit
Field
Type
Reset
Description
[7]
SYNC_SEL
Read or write
0
SYNCb Signal MUX Select
0 : The internal SYNCb signal is routed from the SYNCb+/- pins
(default)
1 : The internal SYNCb signal is routed from the JSYNC_N register
field (SYNCb over SPI)
[6]
JSYNC_N
Read or write
0
SYNCb Over SPI Control
0 : The internal SYNCb signal as asserted, indicating a JESD204 link
synchronization request (default)
1 : The internal SYNCb signal is de-asserted, indicating JESD204 link
synchronization is not being requested
Note: JSYNC_N controls the internal SYNCb signal only when
SYNC_SEL = 1. When SYNC_SEL = 0, this register field is ignored.
[7:4]
[3:0]
Reserved
Read or write
Read or write
00
Reserved. Must be written as 00.
JESD_TEST_
MODES[3:0]
0000
JESD204B test modes.
0000 : Test mode disabled. Normal operation (default)
0001 : PRBS7 test mode
0010 : PRBS15 test mode
0011 : PRBS23 test mode
0100 : RESERVED
0101 : ILA test mode
0110 : Ramp test mode
0111 : K28.5 test mode
1000 : D21.5 test mode
1001: Logic low test mode (serial outputs held low)
1010: Logic high test mode (serial outputs held high)
1011 – 1111 : Reserved
Note:
•
JESD_EN must be set to 0 before altering this field.
8.5.1.15 JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]
表 21. JESD_RSTEP (JESD Ramp Pattern Step), [Addresses: 0x0063, 0x0062], [Default: 0x00, 0x01]
Bit
Field
Type
Reset
Description
JESD204B ramp test mode step
0x0062[7:0] JESD_RSTEP
[7:0]
Read or write
0x01
0x0063[7:0] JESD_RSTEP
[15:8]
Read or write
0x00
The binary value JESD_RSTEP[15:0] corresponds to the step of the
ramp mode step. A value of 0x0000 is not allowed.
Note:
•
JESD_EN must be set to 0 before altering this field.
8.5.1.16 JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]
表 22. JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A]
Bit
[7]
[6]
Field
Reserved
LINK
Type
Read
Read
Reset
N/A
Description
Reserved.
N/A
JESD204B link status
This bit is set when synchronization is finished, transmission of the ILA
sequence is complete, and valid data is being transmitted.
0 : Link not established
1 : Link established and valid data transmitted
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表 22. JESD_STATUS (JESD Link Status), [Address: 0x006C], [Default: N/A] (接下页)
Bit
Field
Type
Reset
Description
[5]
SYNC
Read
N/A
JESD204B link synchronization request status
This bit is cleared when a synchronization request is received at the
SYNCb input.
0 : Synchronization request received at the SYNCb input and
synchronization is in progress
1 : Synchronization not requested
Note:
•
SYNCb must be asserted for at least four local frame clocks before
synchronization is initiated. The SYNC status bit reports the status
of synchronization, but does not necessarily report the current
status of the signal at the SYNCb input.
[4]
[3]
REALIGN
Read or write
N/A
N/A
SYSREF re-alignment status
This bit is set when a SYSREF event causes a shift in the phase of the
internal frame or LMFC clocks.
Note:
•
•
Write a 1 to REALIGN to clear the bit field to a 0 state.
SYSREF events that do not cause a frame or LMFC clock phase
adjustment do not set this register bit.
•
If CLK_RDY becomes low, this bit is cleared.
ALIGN
Read or write
SYSREF alignment status
This bit is set when the ADC has processed a SYSREF event and
indicates that the local frame and multi-frame clocks are now based on
a SYSREF event.
Note:
•
•
•
Write a 1 to ALIGN to clear the bit field to a 0 state.
Rising-edge SYSREF event sets ALIGN bit.
If CLK_RDY becomes low, this bit is cleared.
[2]
[1]
PLL_LOCK
CAL_DONE
Read
Read
N/A
N/A
PLL lock status. This bit is set when the PLL has achieved lock.
0 : PLL unlocked
1 : PLL locked
ADC calibration status
This bit is set when the ADC calibration is complete.
0 : Calibration currently in progress or not yet completed
1 : Calibration complete
Note:
•
Calibration must complete before SYSREF detection (SYS_EN)
can be enabled.
•
Calibration must complete before the any clock phase delay
adjustments are made.
[0]
CLK_RDY
Read
N/A
Input clock status
This bit is set when the ADC is powered-up and detects an active clock
signal at the CLKIN input.
0 : CLKIN not detected
1 : CLKIN detected
40
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Analog Input Considerations
9.1.1.1 Differential Analog Inputs and Full Scale Range
The ADC14X250 device has a single channel with a pair of analog signal input pins: VIN+, VIN−. VIN, the input
differential signal for a channel, is defined as VIN = (VIN+) – (VIN−). 表 23 shows the expected input signal
range when the differential signal swings about the input common mode, VCM. The full-scale differential peak-to-
peak input range is equal to twice the internal reference voltage, VREF. Nominally, the full scale range is 1.7
Vpp-diff, therefore the maximum peak-to-peak single-ended voltage is 0.85 Vpp at each of the VIN+ and VIN−
pins.
The single-ended signals must be opposite in polarity relative to the VCM voltage to provide a purely differential
signal, otherwise the common-mode component may be rejected by the ADC input. 表 23 indicates the input to
output relationship of the ADC14X250 device where VREF = 0.85 V. Differential signals with amplitude or phase
imbalances result in lower system performance compared to perfectly balanced signals. Imbalances in signal
path circuits lead to differential-to-common-mode signal conversion and differential signal amplitude loss as
shown in 图 39. This deviation or imbalance directly causes a reduction in the signal amplitude and may also
lead to distortion, particularly even order harmonic distortion, as the signal propagates through the signal path.
The differential imbalance correction feature of the ADC14X250 device helps to correct amplitude or phase
errors in the signal.
表 23. Mapping of the Analog Input Full Scale Range to Digital Codes
VIN+
VIN–
2s Complement Output
10 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
01 0000 0000 0000
01 1111 1111 1111
Binary Output
Note
VCM – VREF / 2
VCM – VREF / 4
VCM
VCM + VREF / 2
VCM + VREF / 4
VCM
00 0000 0000 0000
01 0000 0000 0000
10 0000 0000 0000
11 0000 0000 0000
11 1111 1111 1111
Negative full-scale
Mid-scale
VCM + VREF / 4
VCM + VREF / 2
VCM – VREF / 4
VCM – VREF / 2
Positive full-scale
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Single-Ended
Differential Mode
Common Mode
VDD
VCM
GND
VCM
0
GND
V
IN-DIFF
V
-
IN
V
IN-CM
0
V +
IN
0
图 39. Differential Signal Waveform and Signal Imbalance
9.1.1.2 Analog Input Network Model
Matching the impedance of the driving circuit to the input impedance of the ADC can be important for low
distortion performance and a flat gain response through the network across frequency. In very broadband
applications or lowpass applications, the ADC driving network must have very low impedance with a small
termination resistor at the ADC input to maximize the bandwidth and minimize the bandwidth limitation posed by
the capacitive load of the ADC input. In bandpass applications, a designer may either design the anti-aliasing
filter to match to the complex impedance of the ADC input at the desired intermediate frequency, or consider the
resistive part of the ADC input to be part of the resistive termination of the filter and the capacitive part of the
ADC input to be part of the filter itself.
The analog input circuit of the ADC14X250 device is a buffered input with an internal differential termination.
Compared to an ADC with a switched-capacitor input sampling network that has an input impedance that varies
with time, the ADC14X250 device provides a constant input impedance that simplifies the interface design joining
the ADC and ADC driver. A simplified passive model of the ADC input network is shown in 图 40 that includes
the termination resistance, input capacitance, parasitic bond-wire inductance, and routing parastics.
5W
0.47nH
+
VIN+
5.2pF
–
5W
+
VIN-
5.2pF
–
0.47nH
图 40. Simplified Analog Input Network Circuit Model
A more accurate load model is described by the measured differential SDD11 (100-Ω) parameter model. A plot of
the differential impedance derived from the model is shown on the Smith chart of 图 41. The model includes the
internal 200-Ω resistive termination, the capacitive loading of the input buffer, and stray parasitic impedances like
bond wire inductance and signal routing coupling. The SDD11 model may be used to back-calculate the
impedance of the ADC input at a frequency of interest.
42
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图 41. Measured Differential Impedance of Analog Input Network on a Smith Chart (100 Ω)
9.1.1.3 Input Bandwidth
The input bandwidth of the ADC14X250 device is defined here as the frequency at which the fundamental
amplitude of the sampled data deviates by 3 dB, compared to the amplitude at low frequencies, for a low-
impedance input sinusoidal signal with constant voltage amplitude at the VIN+ and VIN– input pins. The voltage
frequency response is shown in 图 42.
The peaking in the frequency response is caused by the resonance between the package bond wires and input
capacitance as well as a parasitic 0.5-nH series trace inductance leading to the device pins. This peaking is
typically made insignificant by the stop-band of an anti-aliasing filter that precedes the ADC input. For broadband
applications, 10-Ω resistors may be put in series with the VIN+ and VIN– input pins. This extra resistance flattens
out the frequency response at the cost of adding some attenuation in the signal path. The additional series
resistance also accordingly modifies the measured SDD11 looking into the analog input.
10
No series resistance
8
6
10 ohm series resistance
4
2
0
-2
-4
-6
-8
-10
10
100
1000
Frequency [MHz]
C001
图 42. Measured Input Voltage Frequency Response
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9.1.1.4 Driving the Analog Input
The ADC14X250 device analog input may be driven by a number of methods depending on the end application.
The most important design aspects to consider when designing the ADC voltage driver network are signal
coupling, impedance matching, differential signal balance, anti-alias filtering, and signal level.
An analog signal is AC or DC coupled to the ADC depending on whether signal frequencies near DC must be
sampled. DC coupling requires tight control of the output common-mode of the ADC driver to match the input
common-mode of the ADC input. In the case of DC coupling, the bias at pin VCM may be used as a reference to
establish the driver output common-mode, but the load cannot source or sink more current than what is specified
in the electrical parameters. AC coupling does not require strict common-mode control of the driver and is
typically achieved using AC coupling capacitors or a flux-coupled transformer. AC coupling capacitors should be
chosen to have 0.1-Ω impedance or less over the frequency band of interest. LC filter designs may be
customized to achieve either AC or DC coupling.
The internal input network of the ADC14X250 device has the common-mode voltage bias provided through
internal shunt termination resistors, as shown in the CLKIN+/- pin description figure. TI also recommends
providing the common-mode reference externally from the VCM pin, through external termination resistors.
Impedance matching in high speed signal paths using an ADC is dictated by the characteristic impedance of
interconnects and by the design of anti-aliasing filters. Matching the source to the load termination is critical to
ensure maximum power transfer to the load and to maintain gain flatness across the desired frequency band. In
applications with signal transmission lengths greater than 10% of the smallest signal wavelength (0.1 λ),
matching is also desirable to avoid signal reflections and other transmission line effects. Applications that require
high order anti-aliasing filter designs, including LC bandpass filters, require an expected source and load
termination to ensure the passband bandwidth and ripple of the filter design. The recommended range of the
total ADC load termination is from 50- to 200-Ω differential. The ADC14X250 device has an internal differential
load termination, but additional termination resistance may be added at the ADC input pins to adjust the total
termination. The load termination at the ADC input presents a system-level design tradeoff. Better 2nd order
distortion performance (HD2, IMD2) is achieved by the ADC using a lower load termination resistance, but the
ADC driver must have a higher drive strength and linearity to drive the lower impedance. Choosing a 100-Ω total
load termination is a reasonable balance between these opposing requirements.
Differential signal balance is important to achieve good distortion performance, particularly even order distortion
(HD2, HD4). Circuits such as transformers and filters in the signal path between the signal source and ADC can
disrupt the amplitude and phase balance of the differential signal before reaching the ADC input due to
component tolerances or parasitic mismatches between the two parallel paths of the differential signal. The
amplitude mismatch in the differential path should be less than ± 0.4 dB and the phase mismatch should be less
than ± 2° to achieve a high level of HD2 performance. In the case that this imbalance is exceeded, the input
balance correction may be used to re-balance the signal and improve the performance. Driving the ADC14X250
device with a single-ended signal is not supported due to the tight restriction on the ADC input common-mode to
maintain good distortion performance.
Converting a single-ended signal to a differential signal may be performed by an ADC driver or transformer. The
advantages of the ADC driver over a transformer include configurable gain, isolation from previous stages of
analog signal processing, and superior differential signal balancing. The advantages of using a transformer
include no additional power consumption and little additional noise or distortion.
图 43 is an example of driving the ADC input with a cascaded transformer configuration. The cascaded
transformer configuration provides a high degree of differential signal balancing, the series 0.1-µF capacitors
provide AC coupling, and the additional 33-Ω termination resistors provide a total differential load termination of
50 Ω. When additional termination resistors are added to change the ADC load termination, shunt terminations to
the VCM reference are recommended to reduce common-mode fluctuations or sources of common-mode
interference. A differential termination may be used if these sources of common-mode interference are minimal.
In either case, the additional termination components must be placed as close to the ADC pins as possible. The
MABA007159 transmission-line transformer from this example is widely available and results in good differential
balance. Shunt capacitors at the ADC input, used to suppress the charge kickback of an ADC with switched-
capacitor inputs, are not required for this purpose because the buffered input of the ADC14X250 device does not
kickback a significant amount of charge.
44
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The insertion loss between an ADC driver and the ADC input is important because the driver must overcome the
insertion loss of the connecting network to drive the ADC to full-scale and achieve the best SNR. Minimizing the
loss through the network reduces the output swing and distortion requirements of the driver and usually
translates to a system-level power savings in the driver. This can be accomplished by selecting transformers or
filter designs with low insertion loss. Some filter designs may employ reduced source terminations or impedance
conversions to minimize loss. Many designs require the use of high-Q inductors and capacitors to achieve an
expected passband flatness and profile.
Z0 = 50 W
MABA007159
VIN
+
33 W
33 W
0.01uF
0.01uF
ADC
VIN
-
VCM
MABA007159
10 W
0.1uF
10uF
0.1uF
10uF
图 43. Transformer Input Network
Sampling theory states that if a signal with frequency fIN is sampled at a rate less than 2 × fIN, then it experiences
aliasing, causing the signal to fall at a new frequency between 0 and FS / 2 and become indistinguishable from
other signals at that new frequency.
To prevent out-of-band interference from aliasing onto a desired signal at a particular frequency, an anti-aliasing
filter is required at the ADC input to attenuate the interference to a level below the level of the desired signal.
This is accomplished by a lowpass filter in systems with desired signals from DC to FS / 2 or with a bandpass
filter in systems with desired signals greater than FS / 2 (under-sampled signals). If an appropriate anti-aliasing
filter is not included in the system design, the system may suffer from reduced dynamic range due to additional
noise and distortion that aliases into the frequency bandwidth of interest.
An anti-aliasing filter is required in front of the ADC input in most applications to attenuate noise and distortion at
frequencies that alias into any important frequency band of interest during the sampling process. An anti-aliasing
filter is typically a LC lowpass or bandpass filter with low insertion loss. The bandwidth of the filter is typically
designed to be less than FS / 2 to allow room for the filter transition band. 图 44 is an example architecture of a 9
pole order LC bandpass anti-aliasing filter with added transmission zeros that can achieve a tight filtering profile
for second Nyquist zone under-sampling applications.
Maximizing the distortion performance of this device requires the avoidance of driving circuits that are mostly
capacitive at frequencies near and above the sampling rate. The performance is maximized by ensuring the
driving circuit is high impedance or mostly resistive (real impedance) at these out-of-band frequencies. Driving
circuits with highly capacitive source impedances (negative source reactance) at these frequencies can cause
resonance with the interface, leading to sub-optimal distortion performance. In the case of bandpass LC anti-
aliasing filters, the impedance looking into the filter output is recommended to be high impedance or real at
frequencies near and above the sampling rate such as the filter shown in Figure 42 . Capacitors placed directly
at the ADC input used as bandwidth limiters or as part of a filter's final stage LC tank are not recommended.
Applications that use lumped reactive components (capacitors, inductors) in the interface to the ADC are
recommended to have a small series resistor at the ADC input, also shown in Figure 42 . Place these resistors
close to the device pins, between the external termination resistors and the device pins. A value of 5 Ω is
sufficient for most applications, though TI recommends 10 Ω for applications where the lumped differential
capacitance at the ADC input is unavoidable and greater than 2 pF.
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LC BPF
Vcc+
Rs
5 W
VIN
+
0.1uF
RL
Driver
ADC
5 W
VIN
-
VCM
10 W
0.1uF
10uF
0.1uF
10uF
图 44. Bandpass Filter Anti-Aliasing Interface
DC coupling to the analog input is also possible but the input common-mode must be tightly controlled for
specified performance. The driver device must have an output common-mode that matches the input common-
mode of the ADC14X250 device and the driver must track the VCM output from the ADC14X250 device, as
shown in the example DC coupled interface of 图 45 because the input common-mode varies with temperature.
The common-mode path from the VCM output, through the driver device, back to the ADC14X250 device input,
and through a common-mode detector inside the ADC14X250 device forms a closed tracking loop that will
correct common-mode offset contributed by the driver device but the loop must be stable to ensure correct
performance. The loop requires the large, 10-µF capacitor at the VCM output to establish the dominant pole for
stability and the driver device must reliably track the VCM output voltage bias. The current drive strength and
voltage swing of the VCM output bias limits the correctable amount of common-mode offset.
V
CC
+
LC LPF
5W
R
S
V
IN
+
R
L
Driver
ADC
V
CMO
= V
CM
200W
V
IN
-
V
CM
V
CC
-
0.1uF
0.1uF
图 45. DC Coupled Interface
9.1.1.5 Clipping
The ADC14X250 device has two regions of signal clipping: code clipping (over-range) and ESD clipping. When
the input signal amplitude exceeds the full-scale reference range, code clipping occurs during which the digital
output codes saturate. If the signal amplitude increases beyond the absolute maximum rating of the analog
inputs, ESD clipping occurs due to the activation of ESD diodes.
TI does not recommend ESD clipping and activation of the ESD diodes at the analog input, which may damage
or shorten the life of the device. This clipping may be avoided by selecting an ADC driver with an appropriate
saturating output voltage, by placing insertion loss between the driver and ADC, by limiting the maximum
amplitude earlier in the signal path at the system level, or by using a dedicated differential signal limiting device
such as back-to-back diodes. Any signal swing limiting device must be chosen carefully to prevent added
distortion to the signal.
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9.1.2 CLKIN, SYSREF, and SYNCb Input Considerations
Clocking the ADC14X250 device shares many common concepts and system design requirements with
previously released ADC products, but the JESD204B supported architecture adds another layer of complexity to
clocking at the system level. A SYSREF signal accompanies the device clock to provide phase alignment
information for the output data serializer (as well as for the sampling instant when the clock divider is enabled) to
ensure that the latency through the JESD204B link is always known and does not vary, a concept called
deterministic latency. To ensure deterministic latency, the SYSREF signal must meet setup and hold
requirements relative to CLKIN and the design of the clocking interfaces require close attention. As with other
ADCs, the quality of the clock signal also influences the noise and spurious performance of the device.
9.1.2.1 Driving the CLKIN+ and CLKIN– Input
The CLKIN input circuit is composed of a differential receiver and an internal 100-Ω termination to a weakly
driven common-mode of 0.50 V. TI recommends AC coupling to the CLKIN input with 0.1-uF external capacitors
to maintain the optimal common-mode biasing. 图 46 shows the CLKIN receiver circuit and an example AC
coupled interface.
CLKIN
Receiver
0.1uF
100W-diff
50W
50W
CLKIN
Transmitter
PCB Channel
VIS = 0.5V
10kW
图 46. Driving the CLKIN Input With an AC Coupled Interface
DC coupling is allowed as long as the input common-mode range requirements are satisfied. The input common-
mode of the CLKIN input is not compatible with many common signaling standards like LVDS and LVPECL.
Therefore, the CLKIN signal driver common-mode must be customized at the transmitter or adjusted along the
interface. 图 47 shows an example DC coupled interface that uses a resistor divider network to reduce the
common-mode while maintaining a 100-Ω total termination at the load. Design equations are provided with
example values to determine the resistor values.
V
= 1.2V
CLKIN
Receiver
CMO
R2
R1
100W-diff
50W
50W
Transmitter
PCB Channel
VIS = 0.5V
10kW
4*R1*R2 + 200*R1 = 1002
R2 / (R1+R2) = 0.5 / V
CMO
I
(Each Side)= V
CMO
/ (R1+R2)
DC
VCMO = 1.2V: R1 = 29.1W, R2 = 20.8W, I
= 24mA
DC
图 47. Driving the CLKIN Input With an Example DC Coupled Interface
The CLKIN input supports any type of standard signaling that meets the input signal swing and common-mode
range requirements with an appropriate interface. Generic differential sinusoidal or square-wave clock signals are
also supported. TI does not recommend driving the CLKIN input single-ended. The differential lane trace on the
PCB should be designed to be a controlled 100 Ω and protected from noise sources or other signals.
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9.1.2.2 Clock Noise and Edge Rate
Noise added to the sampling clock path of the ADC degrades the SNR performance of the system. This noise
may include broadband noise added by the ADC clock receiver inside the ADC device but may also include
broadband and in-close phase noise added by the clock generator and any other devices leading to the CLKIN
input. The theoretical SNR performance limit of the ADC14X250 device as a result of clock noise for a given
input frequency is shown in 图 48 for a full scale input signal and different values of total jitter.
74
72
70
68
66
64
62
60
58
56
54
2ps
1ps
500fs
200fs
100fs
50fs
1
10
100
Frequency [MHz]
1000
C001
图 48. SNR Limit Due to Jitter of Sampling Clock With a Full-Scale Input Signal
The differential clock receiver of the ADC14X250 device has a very-low noise floor and wide bandwidth. The
wide band clock noise of the receiver, also referred to as the additive jitter, modulates the sampling instant and
adds the noise to the signal. At the sampling instant, the added broadband noise appears in the first Nyquist
zone at the ADC output to degrade the noise performance. Minimizing the additive jitter requires a sampling
clock with a steep edge rate at the zero crossing. Reduced edge rate increases the additive jitter. For clock
signals with a differential swing of 100 mV or greater, the additive clock 图 49 shows the SNR performance of the
ADC14X250 device for a range of clock transition slopes.
72
71
70
69
68
67
66
65
64
10 MHz
63
62
61
60
70 MHz
170 MHz
240 MHz
300 MHz
0.1
0.2
0.3 0.4 0.5 0.60.7
1
2
CLKIN Zero Crossing Edge Rate [V/ns]
图 49. SNR vs Input Clock Edge Rate (–3 dBFS Input)
Noise added to the sampling clock by devices leading up to the ADC clock input also directly affects the noise
performance of the system. In-close phase noise is typically dominated by the performance of the clock
reference and phase-locked loop (PLL) that generates the clock and limits the sensitivity of the sampling system
at desired frequencies offset 100 Hz to 10 MHz away from a large blocking signal. Little can be done to improve
the in-close phase noise performance without the use of an additional PLL. Broadband noise added in the clock
path limits the sensitivity of the whole spectrum and may be improved by using lower noise devices or by
inserting a band-pass filter (BPF) with a narrow pass band and low insertion loss to the clock input signal path.
Adding a BPF limits the transition rate of the clock, thereby creating a trade-off between the additive jitter added
by the ADC clock receiver and the broadband noise added by the devices that drive the clock input.
Additional noise may couple to the clock path through power supplies. Take care to provide a very-low noise
power supply and isolated supply return path to minimize noise added to the supply. Spurious noise added to the
clock path results in symmetrical, modulated spurs around large input signals. These spurs have a constant
magnitude in units of dB relative to the input signal amplitude or carrier, [dBc].
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9.1.2.3 Driving the SYSREF Input
The SYSREF input interface circuit is composed of the differential receiver, internal common-mode bias,
SYSREF offset feature, and SYSREF detection feature.
A high impedance (10-kΩ) reference biases the input common-mode through internal 1-kΩ termination resistors.
The bias voltage is similar to the CLKIN input common-mode bias, but the internal differential termination is
different. The SYSREF input requires an external 100-Ω termination. A network of resistors and switches are
included at the input interface to provide a programmable DC offset, referred to as the SYSREF offset feature.
This feature is configurable through the SPI and may be utilized to force a voltage offset at the SYSREF input in
the absence of an active SYSREF signal. Following the receiver, an AND gate provides a method for detecting
or ignoring incoming SYSREF events.
The timing relationship between the CLKIN and SYSREF signal is very important in a JESD204B system.
Therefore, the signal path network of the CLKIN and SYSREF signals must be as similar as possible to ensure
that the signal relationship is maintained from the launch of the signal, through their respective channels to the
CLKIN and SYSREF input receivers.
TI recommends AC coupling for the SYSREF interface as shown in 图 50. This network closely resembles the
AC coupled interface of the CLKIN input shown in 图 46 with the exception of the 100-Ω termination resistor on
the source side of the AC coupling capacitors. This resistor is intentionally placed on the source side of the AC
coupling capacitors, so that the termination does not interfere with the DC biasing capabilities of the SYSREF
offset feature. In the case of AC coupling, the coupling capacitors of both the CLKIN and SYSREF interfaces, as
well as the SYSREF termination resistor, must be placed as close as possible to the pins of the ADC14X250
device.
1.2V
VIS = 0.5V
2.5kW
10kW
1kW
S2a S1a
SYSREF
Receiver
0.1uF
100W
100W-diff
S2b S1b
SYSREF
Transmitter
SYSREF
Offset
Feature
PCB Channel
SYSREF
Detection
Feature
1.5kW
图 50. SYSREF Input Receiver and AC Coupled Interface
DC coupling of the SYSREF interface is possible, but not recommended. DC coupling allows all possible
SYSREF signaling types to be used without the use of the SYSREF offset feature, but it has strict common-mode
range requirements. The example DC coupled configuration of 图 51 uses the same technique for the CLKIN
example DC coupled interface and also includes the 100-Ω external termination. A drawback of the example DC
coupled interface is that the resistor divider draws a constant DC current that must be sourced by the SYSREF
transmitter.
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1.2V
VIS = 0.5V
2.5kW
10kW
1kW
V
= 1.2V
CMO
R2
SYSREF
Receiver
R1
100W-diff
100W
SYSREF
Transmitter
PCB Channel
1.5kW
4*R1*R2 + 200*R1 = 1002
R2 / (R1+R2) = 0.5 / V
CMO
I
(Each Side)= V
CMO
/ (R1+R2)
DC
VCMO = 1.2V: R1 = 29.1W, R2 = 20.8W, I
= 24mA
DC
图 51. Example DC Coupling to the SYSREF Input
9.1.2.4 SYSREF Signaling
The SYSREF input may be driven by a number of different types of signals. The supported signal types, shown
in 图 52 (in single-ended form), include periodic, gapped periodic, and one-shot signals. The rising edge of the
SYSREF signal is used as a reference to align the internal frame clock and local multi-frame clock (LMFC). To
ensure proper alignment of these system clocks, the SYSREF signal must be generated along with the CLKIN
signal such that the SYSREF rising edge meets the setup and hold requirements relative to the CLKIN at the
ADC14X250 device inputs.
For each rising clock edge that is detected at the SYSREF input, the ADC14X250 device compares the current
alignment of the internal frame and LMFC with the SYSREF edge and determines if the internal clocks must be
re-aligned. In the case that no alignment is needed, the clocks maintain their current alignment and the
JESD204B data link is not broken. In the case that re-alignment is needed, the JESD204B data link is broken
and the clocks are re-aligned.
Periodic
TSYSREF = n*K*TFRAME
(n=1,2,3...)
Gapped-Periodic
≥ 2*TFRAME
One-Shot
≥ 2*TFRAME
图 52. SYSREF Signal Types (Single-Ended Representations)
In the case of a periodic SYSREF signal, the frame and LMFC alignment is established at the first rising edge of
SYSREF, and every subsequent rising edge (that properly meets setup and hold requirements) is ignored
because the alignment has already been established. A periodic SYSREF must have a period equal to n × K / FS
where ‘FS’ is the sampling rate, ‘K’ is the JESD204B configuration parameter indicating the number of frames per
multi-frame, and ‘n’ is an integer of one or greater. The duty cycle of the SYSREF signal should be greater than
2 / K but less than (K – 2) / K.
Gapped-period signals contain bursts of pulses. The frame and LMFC alignments are established on the first
rising edge of the pulse burst. The rising edges within the pulse burst must be spaced apart by n × K / FS
seconds, similar to the periodic SYSREF signal. Any rising edge that does not abide by this rule or does not
meet the setup and hold requirements forces re-alignment of the clocks. The duty cycle requirements are the
same as the periodic signal type.
A one-shot signal contains a single rising edge that establishes the frame and LMFC alignment. The single pulse
duration must be 2 × TFRAME or greater.
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TI recommends gapped-periodic or one-shot signals for most applications so that the SYSREF signal is not
active during normal sampling operation. Periodic signals that toggle constantly introduce spurs into the signal
spectrum that degrade the sensitivity of the system.
9.1.2.5 SYSREF Timing
The SYSREF timing requirements depend on whether deterministic latency of the JESD204B link is required.
If deterministic latency is required, then the SYSREF signal must meet setup and hold requirements relative to
the CLKIN signal. In the case that the internal CLKIN divider is used and a very high-speed signal is provided to
the CLKIN input, the SYSREF signal must meet setup and hold requirements relative to the very high-speed
signal at the CLKIN input.
If deterministic latency is not required, then the SYSREF signal may be supplied as an asynchronous signal
(possibly achieving < ± 2 frame clock cycles latency variation) or not provided at all (resulting in latency variation
as large as the multi-frame period).
9.1.2.6 Effectively Using the SYSREF Offset and Detection Gate Features
Selecting the proper settings for the SYSREF offset feature depends on the condition of SYSREF in the idle
state and the type of SYSREF signal being transmitted. 表 24 describes the possible SYSREF idle cases and the
corresponding SYSREF offset to apply.
TI recommends the use of the SYSREF detection gate for most applications. The gate is enabled when SYSREF
is being transmitted and the gate is disabled before the SYSREF transmitter is put in the idle state. Although the
SYSREF offset feature does not support situations where the SYSREF transmitter is in a 0 V or Hi-Z common-
mode condition during the idle state, the SYSREF gate can be used to ignore the SYSREF input during those
conditions. In those cases, time is required to dissipate the voltage build-up on the AC coupling capacitors when
the SYSREF returns to an active state.
Enabling the SYSREF gate immediately sends a logic signal to a logic block responsible for aligning the internal
frame clock and LMFC. If the signal at the SYSREF input is logic high when the gate is enabled, then a "false"
rising edge event causes a re-alignment of the internal clocks, despite the fact that the event is not an actual
SYSREF rising edge. The SYSREF rising edge following the gate enable then causes a subsequent re-alignment
with the desired alignment.
TI highly recommends the SYSREF clocking schemes described in 表 25.
表 24. SYSREF Offset Feature Usage Cases
SYSREF
Signal Type
SYSREF Idle
VOD at TX
SYSREF Idle Common-Mode (VIS) at the
Transmitter
SYSREF
Offset Feature Setting
Periodic
N/A
N/A
0 mV
0 mV
= 0
> 0 (logic high)
< 0 (logic low)
0
VIS same during idle and non-idle states
Gapped-periodic or
One-shot
VIS same during idle and non-idle states
+400 mV
–400 mV
VIS same during idle and non-idle states
0
SYSREF offset feature does not
support these cases
Any
Hi-Z
Hi-Z
表 25. Recommended SYSREF Clocking Schemes
SYSREF at TX During Idle
State
SYSREF Rx Offset
Setting
Coupling
SYSREF Type
SYSREF Detection Gate
One-shot or gapped-
periodic(1)
VOD logic low, VIS does not
change during idle
Disabled during SYSREF idle,
enabled during LMFC alignment
AC Coupled
DC Coupled
–400 mV at all times
0 mV at all times
VOD either logic state, VIS
does not change during idle
Disabled during SYSREF idle,
enabled during LMFC alignment
One-shot or gapped-periodic
(1) A gapped-periodic signal used in this recommended clocking scheme must have a pulse train duration of less than the RC time constant
where R = 50 Ω and C is the value of the AC coupling capacitor. Using a 0.1-µF capacitor, the pulse train should be less than 5 µs.
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9.1.2.7 Driving the SYNCb Input
The SYNCb input is part of the JESD204B interface and is used to send synchronization requests from the serial
data receiver to the transmitter, the ADC14X250 device. The SYNCb signal, quantified as the (SYNCb+ –
SYNCb–), is a differential active low signal. In the case of the ADC14X250 device, a JESD204B subclass 1
device, a SYNCb assertion (logic low) indicates a request for synchronization by the receiver.
The SYNCb input is a differential receiver as shown in 图 53. Resistors provide an internal 100-Ω differential
termination as well as a voltage divider circuit that gives the SYNCb receiver a wide input common-mode range.
The SYNCb signal must be DC coupled from the driver to the SYNCb inputs; therefore, the wide common-mode
range allows the use of many different logic standards including LVDS and LVPECL. No additional external
components are needed for the SYNCb signal path as shown in the interface circuit of 图 53, but providing an
electrical probing site is recommended for system debug.
2.5V
2kW
1kW
1kW
2kW
SYNCb
Receiver
100W-diff
50W
50W
34kW
SYNCb
Transmitter
PCB Channel
34kW
3pF
图 53. SYNCb Input Receiver and Interface
The SYNCb input is an asynchronous input and does not have sub-clock-cycle setup and hold requirements
relative to the CLKIN or any other input to the ADC14X250 device. The SYNCb input also does not have setup
and hold requirements relative to the frame and LMFC system clocks.
In the case that the JESD204B sync~ signal is provided via SPI with SYNC_SEL = 1, the SYNCb+/- pin interface
may remain not connected.
9.1.3 Output Serial Interface Considerations
9.1.3.1 Output Serial-Lane Interface
The output high speed serial lanes must be AC coupled to the receiving device with 0.01-µF capacitors as shown
in 图 54. DC coupling to the receiving device is not supported. The lane channel on the PCB must be a 100-Ω
differential transmission line with dominant coupling between the differential traces instead of to adjacent layers.
The lane must terminate at a 100-Ω termination inside the receiving device. Avoid changing the direction of the
channel traces abruptly at angles larger than 45°.
0.01uF
100W-diff
100W
PCB Channel
Serial Lane
Transmitter
Serial Lane
Receiver
图 54. High-Speed Serial-Lane Interface
The recommended spacing between serial lanes is 3× the differential line spacing or greater. High speed serial
lanes should be routed on top of or below adjacent, quiet ground planes to provide shielding. TI recommends
that other high speed signal traces do not cross the serial lanes on adjacent PCB layers. If absolutely necessary,
crossing should occur at a 90° angle with the trajectory of the serial lane to minimize coupling.
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The integrity of the data transfer from the transmitter to receiver is limited by the accuracy of the differential lane
characteristic impedance and the attenuation as the signal travels down the lane. Inaccurate or varying
impedance and frequency dependent attenuation results in increased ISI (part of deterministic jitter) and reduced
signal-to-noise ratio, which limits the ability of the receiver to accurately recover the data.
Two features are provided in the ADC14X250 device serial transmitters to compensate attenuation and ISI
caused by the serial lane: voltage swing control (VOD) and de-emphasis (DEM).
9.1.3.2 Voltage Swing and De-Emphasis Optimization
Voltage swing control (VOD) compensates for attenuation across all frequencies through the channel at the
expense of power consumption. Increasing the voltage swing increases the power consumption. De-emphasis
(DEM) compensates for the frequency dependent attenuation of the channel but results in attenuation at lower
frequencies. The voltage swing control and de-emphasis feature may be used together to optimally compensate
for attenuation effects of the channel.
The frequency response of the PCB channel is typically lowpass with more attenuation occurring at higher
frequencies. The de-emphasis implemented in the ADC14X250 device is a form of linear, continuous-time
equalization that shapes the signal at the transmitter into a high-pass response to counteract the low-pass
response of the channel. The de-emphasis setting should be selected such that the equalizer’s frequency
response is the inverse of the channel’s response. Therefore, transferring data at the highest speeds over long
channel lengths requires knowledge of the channel characteristics.
Optimization of the de-emphasis and voltage swing settings is only necessary if the ISI and losses caused by the
channel are too great for reception at the desired bit rate. Many applications will perform with an adequate BER
using the default settings.
9.1.3.3 Minimizing EMI
High data-transfer rates have the potential to emit radiation. EMI may be minimized using the following
techniques:
•
Use differential stripline channels on inner layer sandwiched between ground layers instead of routing
microstrip pairs on the top layer.
•
•
•
Avoid routing lanes near the edges of boards.
Enable data scrambling to spread the frequency content of the transmitted data.
If the serial lane must travel through an interconnect, choose a connector with good differential pair channels
and shielding.
•
Ensure lanes are designed with an accurate, 100-Ω characteristic impedance and provide accurate 100-Ω
terminations inside the receiving device.
9.1.4 JESD204B System Considerations
9.1.4.1 Frame and LMFC Clock Alignment Procedure
Frame and LMFC clocks are generated inside the ADC14X250 device and are used to properly align the phase
of the serial data leaving the device. The phases of the frame and multi-frame clocks are determined by the
frame alignment step for JESD204B link initialization as shown in 图 36. These clocks are not accessible outside
the device. The frequencies of the frame and LMFC must be equal to the frame and LMFC of the device
receiving the serial data.
When the ADC14X250 device is powered-up, the internal frame and local multi-frame clocks initially assume a
default phase alignment. To ensure determinist latency through the JESD204B link, the frame and LMFC clocks
of the ADC14X250 device must be aligned in the system. Perform the following steps to align the ADC14X250
device clocks:
1. Enable the SYSREF signal driver. See SYSREF Signaling for more information.
2. Configure the SYSREF offset feature appropriately based on the SYSREF signal and channel. See
Effectively Using the SYSREF Offset and Detection Gate Features for more information.
3. Enable detection of the SYSREF signal at the ADC14X250 device by enabling the SYSREF detection gate.
4. Apply the desired SYSREF signal at the ADC14X250 device SYSREF input.
5. Disable detection of the SYSREF signal by disabling the SYSREF gate.
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6. Configure the SYSREF driver into its idle state.
9.1.4.2 Link Interruption
The internal frame and multi-frame clocks must be stable to maintain the JESD204B link. The ADC14X250 is
designed to maintain the JESD204B link in most conditions but some features interrupt the internal clocks and
break the link.
The following actions cause a break in the JESD204B link:
•
•
•
•
The ADC14X250 device is configured into power-down mode or sleep mode
The ADC14X250 device CLKIN clock divider setting is changed
The serial data receiver performs a synchronization request
The ADC14X250 device detects a SYSREF assertion that is not aligned with the internal frame or multi-frame
clocks
•
•
The CLKIN input is interrupted
Power to the device is interrupted
The following actions do not cause a change in clock alignment nor break the JESD204B link:
•
The ambient temperature or operating voltages are varied across the ranges specified in the normal operating
conditions.
•
The ADC14X250 device detects a SYSREF assertion that is aligned with the internal frame and multi-frame
clocks.
9.1.4.3 Clock Configuration Examples
The features provided in the ADC14X250 device allow for a number of clock and JESD204B link configurations.
These examples in 表 26 show some common implementations and may be used as a starting point for a more
customized implementation.
表 26. Example ADC14X250 Clock Configurations
Parameter
CLKIN Frequency
CLKIN Divider
Sampling Rate
Example 1
250 MHz
1
Example 2
1000 MHz
4
Example 3
2000 MHz
8
250 MSPS
250 MSPS
250 MSPS
K (Frames per Multi-
frame)
20
32
16
LMFC Frequency
12.5 MHz
12.5 MHz
5.0 Gb/s
7.8125 MHz
7.8125 MHz
5.0 Gb/s
15.625 MHz
15.625 MHz
5.0 Gb/s
SYSREF
Frequency(1)
Serial Bit Rate
(1) The SYSREF frequency for a continuous SYSREF signal can be the indicated frequency fLMFC or integer sub-harmonic such as fLMFC
/
2, fLMFC / 3, and so forth. Gapped-periodic SYSREF signals should have pulses spaced by the associated periods 1 / fLMFC, 2 / fLMFC, 3 /
fLMFC, and so forth.
9.1.4.4 Configuring the JESD204B Receiver
The ASIC or FPGA device that receives the JESD204B data from the ADC14X250 device must be configured
properly to interpret the serial stream. 表 4 describes the JESD204B parameter information transmitted during
the ILA sequence and may be used to dynamically configure the receiving device. Due to the various
arrangements of output data across different operational modes, some parameters (N, N’, CS, CF) do not always
reflect the data properties in all modes. Therefore, the ILA information does not completely describe the data
output from the ADC14X250 device in all modes.
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9.1.5 SPI
图 55 demonstrates a typical circuit to interface the ADC14X250 device to a SPI master using a shared SPI bus.
The 4-wire interface (SCLK, SDI, SDO, CSb) is compatible with 1.2-, 1.8-, 2.5-, or 3-V logic. The input pins
(SCLK, SDI, CSb) utilize thick-oxide devices to tolerate 3-V logic although the input threshold levels are relative
to 1.2-V logic. The SDO output logic level is programmed in the the SPI_CFG. Until this register is properly
configured, voltages on the SDO output may be as high as the VA3.0 supply during a read command. The default
state of SDO is to output 3 V logic levels during a read command. A low-capacitance protection diode may also
be added with the anode connected to the SDO output and the cathode connected to the desired voltage supply
to prevent an accidental pre-configured read command from causing damage.
Configurable bus access logic level
(Must configure BEFORE read command)
Hi-Z idle state
1.2V 1.8V 2.5V 3.0V
22 W
SDO
SPI Slave 1
(ADC14X250)
3.0V tolerant inputs
1.2V logic thresholds
VMASTER
SPI
Master
1.2V
10kW
22 W
SCLK
SDI
CSB1
22 W
SDO
SCLK
SDI
SPI Slave 2
CSB2
图 55. Typical SPI Application
9.2 Typical Applications
The ADC14X250 device is architected to fit seamlessly into most high intermediate frequency (IF) receiver
applications where low noise and low distortion are required. An example block diagram is shown in 图 56 where
the ADC14X250 device is used in the receive path as well as the transmitter observation path to accommodate
digital pre-distortion. The 250-MHz sampling rate provides a wide spectrum bandwidth and performance to
support the newest cellular standards like LTE as well as the mature multi-carrier standards like GSM and
UMTS. The device supports diversity and MIMO architectures and multi-band receivers. The back-end
JESD204B interface reduces the space required to transfer data and provides a standard interface that can
migrate to future generations of products, making it optimal for highly-channelized applications.
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Typical Applications (接下页)
De-Modulator
BPF
BPF
BPF
ADC14X250
(ADC)
LNA
DVGA
RECEIVER
JESD204
SYSTEM
CLOCK
RF PLL
SYNTH
GENERATOR
FPGA /
ASIC
BPF
BPF
BPF
BPF
BPF
PA
DVGA
DVGA
DAC
Modulator
ATT
ADC14X250
(ADC)
De-Modulator
TRANSMITTER
图 56. High IF Receiver and Transmitter With Digital Pre-Distortion Path
9.2.1 Design Requirements
The following are example design requirements expected of the ADC in a typical high-IF, 100-MHz bandwidth
receiver, and is met by the ADC14X250 device:
表 27. Example Design Requirements for a High-IF Application
Specification
Sampling Rate
Example Design Requirement(1)
ADC14X250 Capability
Up to 250-MSPS
250-MSPS
Input Bandwidth
Full Scale Range
Small Signal Noise Spectral Density
Large Signal SNR
SFDR
> 400-MHz, 1-dB flatness
500-MHz, 1dB Bandwidth
< 2-Vpp-diff
1.7-Vpp-diff
< –150-dBFS/Hz
–152.1-dBFS/Hz
> 69-dBFS for a –3 dBFS, 240-MHz Input
> 80-dBFS for a –3 dBFS, 240-MHz input
< –80-dBFS for a –3 dBFS, 240-MHz input
< –85-dBFS for a –3 dBFS, 240-MHz input
70.1-dBFS for a –3 dBFS, 240-MHz Input
87-dBFS for a –3 dBFS, 240-MHz input
–87-dBFS for a –3 dBFS, 240-MHz input
–92-dBFS for a –3 dBFS, 240-MHz input
HD2, HD3
Next Largest SPUR
JESD204B interface, 1 lane/channel, < 10-
Gb/s bit rate
JESD204B subclass 1 interface, 1 lane, 5.0-Gb/s
bit rate
Digital Interface
SPI configuration, 4-wire, 1.8-V logic, SCLK up SPI configuration, 4-Wire, 1.8-V Logic, SCLK > 20-
Configuration Interface
Package Size
to 20-MHz
MHz
< 8 × 8 × 1 mm
5 × 5 × 0.8 mm
(1) These example design requirements do not represent the capabilities of the ADC14X250, rather the requirements are satisfied by the
ADC14X250.
9.2.2 Design Procedure
The following procedure can be followed to design the ADC14X250 device into most applications:
•
Choose an appropriate ADC driver and analog input interface.
–
–
–
–
Optimize the signal chain gain leading up to the ADC to make use of the full ADC dynamic range.
Identify whether DC or AC coupling is required.
Determine the desired analog input interface, such as a bandpass filter or a transformer.
Use the provided input network models to design and verify the interface.
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–
Refer to the interface recommendations in Analog Input Considerations.
•
Determine the core sampling rate of the ADC.
–
–
Must satisfy the bandwidth requirements of the application .
Must also provide enough margin to prevent aliasing or to accommodate the transitions bands of an anti-
aliasing filter.
–
Ensure the application initialization sequence properly handles ADC core calibration as described in ADC
Core Calibration.
•
•
Determine the system latency requirements.
–
–
Total allowable latency through the ADC and JESD204B link.
Is the system tolerant of latency variation over time or conditions or between power cycles?
Determine the desired JESD204B link configuration as discussed in JESD204B Supported Features.
–
Based on the system latency requirements, determine whether deterministic latency is required across the
JESD204B link.
–
–
Choose the number of frames per multi-frame, K.
Choose whether scrambling is desired.
•
Choose an appropriate clock generator, CLKIN interface, and SYSREF interface.
–
Determine the system clock distribution scheme and the clock frequencies for the CLKIN and SYSREF
inputs.
–
Determine the allowable amount of sampling clock phase noise in the system and then select a CLKIN
edge rate that satisfies this requirement as discussed in Clock Noise and Edge Rate.
–
–
Choose an appropriate CLKIN interface as discussed in Driving the CLKIN+ and CLKIN– Input.
Based on the latency requirements, determine whether SYSREF must meet setup and hold requirements
relative to CLKIN.
–
–
–
Choose the SYSREF signal type as discussed in SYSREF Signaling.
Choose an appropriate SYSREF interface as discussed in Driving the SYSREF Input.
Choose a CLKIN and SYSREF clock generator based on the above requirements. The signals need come
from the same generator in some cases.
–
Determine what clock idle modes are supported by the SYSREF clock generator and choose the
appropriate setting for the SYSREF Offset feature as discussed in Effectively Using the SYSREF Offset
and Detection Gate Features .
•
•
Design the SYNCb interface as discussed in Driving the SYNCb Input.
Choose appropriate configurations for the output serial data interface.
–
–
–
Design the serial lane interface according to Output Serial-Lane Interface.
Choose the required PCB materials, keeping in mind the desired rate of the serial lanes.
Characterize the signal lane channels the connect the ADC serial output transmitters to the receiving
device either through simulation or bench characterization.
–
Optimize the VOD and DEM parameters to achieve the required signal integrity according to Voltage
Swing and De-Emphasis Optimization.
•
•
Design the SPI bus interface.
–
–
–
Verify the electrical and functional compatibility of the ADC SPI with the SPI controller.
Interface the ADC to the SPI bus according to SPI.
Ensure that the application initialization sequence properly configures the output SDO voltage before the
first read command.
Design the power supply architecture and de-coupling.
–
–
–
Choose appropriate power supply and supply filtering devices to provide stable, low-noise supplies as
described in Power Supply Design.
Design the capacitive de-coupling around the ADC, also described in Power Supply Design, while paying
close attention to placing the capacitors as close to the device as possible.
Time the power architecture to satisfy the power sequence requirements described in Power Supply
Design.
•
Ensure that the application initialization sequence satisfies the JESD204B link initialization requirements
described in JESD204B Link Initialization.
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9.2.3 Application Performance Plot
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
25
50
75
100
125
Frequency [MHz]
F1 = 235 MHz; F2 = 240 MHz
图 57. 2-Tone IMD3 Performance
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9.2.4 Systems Example
VDDA1.8
10 kW
VDDA1.8
VDDA1.8
0.1, 0.01 uF
VDDA1.2
0.1, 0.01 uF
SPI
Master
0.1, 0.01 uF
25 W
VDDA3.0
VA3.0
AGND
VIN+
SCLK
1
2
3
4
5
6
7
8
24
0.1, 0.01 uF
CSB
23
50 W
50 W
BP2.5
22
0.1, 10 uF
AGND
VIN-
21
100 W Differential
ADC14X250
100 W
100 W
10 W
AGND
VCM
SO-
20
0.01 uF
100 W
SO+
Driver
19
18
17
VDDA1.2
0.1 uF
10 uF
0.1 uF
VA1.2
AGND
AGND
VA1.2
10 uF
VDDA1.2
0.1, 0.01 uF
JESD204
Receiver
0.1, 0.01 uF
100 W Differential
VDDA1.8
0.1, 0.01 uF
JESD204
Clock
100 W Differential
Trace Matched
Generator
100 W
100 W
图 58. High-IF Sampling Receiver
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10 Power Supply Recommendations
10.1 Power Supply Design
The ADC14X250 device is a very-high dynamic range device and therefore requires very-low noise power
supplies. LDO-type regulators, capacitive decoupling, and series isolation devices like ferrite beads are all
recommended.
LDO-type low noise regulators should be used to generate the 1.2-, 1.8-, and 3-V supplies used by the device.
To improve power efficiency, a switching-type regulator may precede the LDO to efficiently drop a supply to an
intermediate voltage that satisfies the drop-out requirements of the LDO. TI recommends to follow a switching-
type regulator with an LDO to provide the best filtering of the switching noise. Additional ferrite beads and LC
filters may be used to further suppress noise. Supplying power to multiple devices in a system from one regulator
may result in noise coupling between the multiple devices; therefore, series isolation devices and additional
capacitive decoupling is recommended to improve the isolation.
The power supplies must be applied to the ADC14X250 device in this specific order:
1. VA3.0
2. VA1.8
3. VA1.2
First, the VA3.0 (+3.0 V) must be applied to provide the bias for the ESD diodes. The VA1.8 (+1.8-V) supply
should be applied next, followed by the VA1.2 (+1.2-V) supply. As a guideline, each supply should stabilize to
within 20% of the final value within 10 ms and before enabling the next supply in the sequence. If the
stabilization time is longer than 10 ms, then the system should perform the calibration procedure after the
supplies have stabilized. Turning power supplies off should occur in the reverse order.
In the case of a DC coupled interface with driving amplifier, the ADC supplies should be enabled and allowed to
stabilize at least 1 ms before enabling the supply of driving amplifier. The sequencing delay allows the capacitors
in the common-mode control loop to charge and avoids reliability concerns related to driving the ADC input
outside the VIN+/- absolute maximum range for an extended time.
10.2 Decoupling
Decoupling capacitors must be used at each supply pin to prevent supply or ground noise from degrading the
dynamic performance of the ADC and to provide the ADC with a well of charge to minimize voltage ripple caused
by current transients. The recommended supply decoupling scheme is to have a ceramic X7R 0201 0.1-μF
capacitor at each supply pin. The 0201 capacitor must be placed on the same layer as the device as close to the
pin as possible to minimize the AC decoupling path length from the supply pin, through the capacitor, to the
nearest adjacent ground pin. The 0402 capacitor should also be close to the pins. TI does not recommend
placing the capacitor on the opposite board side. Each voltage supply should also have a single 10-μF
decoupling capacitor near the device but the proximity to the supply pins is less critical.
The BP2.5 pin is an external bypass pin used for stabilizing an internal 2.5-V regulator and must have a ceramic
or tantalum 10-μF capacitor and a ceramic 0402 0.1-μF capacitor. The 0.1-μF capacitor should be placed as
close to the BP2.5 pin as possible.
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11 Layout
11.1 Layout Guidelines
•
The design of the PCB is critical to achieve the full performance of the ADC14X250 device. Defining the PCB
stackup should be the first step in the board design. Experience has shown that at least 6 layers are required
to adequately route all required signals to and from the device. Each signal routing layer must have an
adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve
controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground
planes to control supply return paths. Minimizing the spacing between supply and ground planes improves
performance by increasing the distributed decoupling. The recommended stack-up for a 6-layer board design
is shown in 图 59.
•
Although the ADC14X250 device consists of both analog and digital circuitry, TI highly recommends solid
ground planes that encompass the device and its input and output signal paths. TI does not recommend split
ground planes that divide the analog and digital portions of the device. Split ground planes may improve
performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path.
When split ground planes are employed, one must carefully control the supply return paths and keep the
paths on top of their respective ground reference planes.
•
•
Quality analog input signal and clock signal path layout is required for full dynamic performance. Symmetry of
the differential signal paths and discrete components in the path is mandatory and symmetrical shunt-oriented
components should have a common grounding via. The high frequency requirements of the input and clock
signal paths necessitate using differential routing with controlled impedances and minimizing signal path
stubs (including vias) when possible.
Coupling onto or between the clock and input signal paths must be avoided using any isolation techniques
available including distance isolation, orientation planning to prevent field coupling of components like
inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal
path and the input analog signal path provides a quiet ground reference for the critical signal paths and
reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power
routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces
should cross at 90° angles to minimize crosstalk.
•
•
The substrate dielectric materials of the PCB are largely influenced by the speed and length of the high speed
serial lanes. The affordable and common FR4 variety may not offer the consistency or loss to support very
high speed transmission (> 5 Gb/s) and long lengths (> 4 inch). Although the VOD and DEM features are
available to improve the signal integrity of the serial lanes, some of the highest performing applications may
still require special dielectric materials such as Rogers 4350B or Panasonic Megtron 6.
Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by
maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be
used in very noisy environments and high dynamic range applications to isolate the signal path.
L1 œ SIG
L2 œ GND
0.007''
0.004''
L3 œ PWR/SIG
0.0625''
L4 œ PWR
L5 œ GND
0.004''
0.007''
L6 œ SIG
1 oz. Copper on L2-5, 2 oz. Copper on L1, L6
100 Differential Signaling on SIG Layers
Low loss dielectric adjacent very high speed trace layers
图 59. Recommended PCB Layer Stack-Up for a Six-Layer Board
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Layout Guidelines (接下页)
11.1.1 Layout Example
图 60. Example Layout
11.1.2 Thermal Considerations
The exposed thermal pad of the ADC14X250 device draws heat from the silicon down into the PCB to prevent
overheating and must attach to the landing pad with a quality solder connection to maximize thermal conductivity.
Overly hot operating temperatures may be alleviated further by increasing the PCB size, filling surface layers with
ground planes to increase heat radiation, or using a thermally conductive connection between the package top
and a heat sink.
62
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ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
12 器件和文档支持
12.1 器件支持
12.1.1 相关文档
请参见隔离术语表 (SLLA353)
12.1.1.1 技术规格定义
3dB 带宽
是频率的测量值，在这一频率上，相对于施加在器件输入引脚上的差分电压信号，重建输出基频从其
低频值偏离 3dB。
孔径延迟
是时钟的上升边沿到获得或保持转换所需输入信号的时间延迟。
孔径抖动（孔径不确定性） 是采样与采样之间的孔径延迟变化。
时钟占空比 是一个周期内重复数字波形为高电平的时间与一个周期总时长的比。这里的技术规格是指 ADC 时钟
输入信号。
共模电压 (VCM) 是施加在 ADC 差分输入两个端子上的共直流电压。
共模抑制比 (CMRR) 是采样频谱内单音寄生信号的幅度（将 ADC 模拟输入视为峰值电压量）与同时出现在差分模
拟输入（此输入作为生成寄生信号的共模信号）正负端子上正弦波的峰值电压摆幅的比。通常情况
下，CMRR 的单位为分贝 [dB]。
微分非线性 (DNL) 是到 1 个最低有效位 (LSB) 的理想步长尺寸的最大偏差测量值。
增益变化
是转换器增益的预计标准偏差，此转换器进行部件或通道之间的施加电压到输出代码的转换。
积分非线性 (INL) 是每个独立代码到最佳拟合直线偏差的测量值。任意指定代码到这条直线的偏差是代码值中央的
测量值。
互调失真 (IMD) 是由于两个正弦频率同时被施加到 ADC 输入上所产生的额外频谱分量。它将邻近输入音的最大互
调乘积的功率量化，表示单位为 dBFS。(It quantifies the power of the largest intermodulation
product adjacent to the input tones, expressed in dBFS.)
最低有效位 (LSB) 是所有位中具有最小值或最低权重的位。这个值为 VFS / 2n，在这里，VFS 是满量程输入电压，
而 n 是单位为位的 ADC 分辨率。
丢码
最高有效位 (MSB) 是具有最大值或最高权重的位。它的值是满量程的一半。
偏移误差 是代码 8191LSB 和 8192LSB 偏移二进制数据格式转换所需的两输入电压之差 (VIN+ - VIN-)。
是那些没有出现在 ADC 输出上的输出代码。ADC14X250 器件不含丢码。
电源敏感度 是电源对噪声的敏感度的测量值。在其技术规格内，电源经 100mV，500kHz 正弦波调制，在测量频
谱中产生的寄生信号。敏感度的表示方法相对于可能的满量程正弦波的功率 [dBFS] 。
采样到串行输出 (S2SO) 延迟 是转换开始到针对此次采样的串行数据第一位出现在输出驱动器之上的帧时钟周期的
数量。这个延迟的额定值是不确定的。
采样到并行输出 (S2PO) 延迟 是转换开始到并行采样数据在接收器的弹性缓冲器输出上可用时的帧时钟周期数量。
这个延迟的额定值在满足 JESD204B 1 子类要求的情况下是确定的。
信噪比 (SNR) 是输入信号的功率与所有其他频谱分量（不包括谐波和直流分量）的功率之间的比，表示为 dB。
SNR 通常表示为相对于可能的满量程正弦波功率 [dBFS] 或相对于实际输入载波信号的功率 [dBc] 。
信噪比和失真 (SINAD) 是输入信号的功率与所有其他频谱分量（其中包括谐波分量，但不包括直流分量）的功率
之间的比，单位 dB。SINAD 通常表示为相对于可能的满量程正弦波功率 [dBFS] 或相对于实际输入
载波信号的功率 [dBc] 。
非 HD2/HD3 毛刺 是杂散信号峰值功率与输入信号功率的比值，以分贝 (dB) 为单位表示，其中杂散信号是出现在
输出频谱但未出现在输入中的所有信号，不包括二次和三次谐波失真。该参数通常表示为与可能的满
量程正弦信号功率的相对值 [dBFS] 或与实际输入载波信号功率的相对值 [dBc]。
无寄生动态范围 (SFDR) 是输入信号功率与峰值寄生信号功率的比，单位 dB，在这里，寄生信号是出现在输出频
谱中，但是未出现在输入中的任一信号。SINAD 通常表示为相对于可能的满量程正弦波功率 [dBFS]
或相对于实际输入载波信号的功率 [dBc]。
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63
ADC14X250
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www.ti.com.cn
器件支持 (接下页)
第二谐波失真（2ND HARM 或 HD2） 是输入信号的 2nd 谐波的功率与输入信号功率的比，单位 dB。HD2 通常表
示为相对于可能的满量程正弦波功率 [dBFS] 或相对于实际输入载波信号的功率 [dBc]。
第三谐波失真（3RD HARM 或 HD3） 是输入信号的 3rd 谐波的功率与输入信号功率的比，单位 dB。HD3 通常表
示为相对于可能的满量程正弦波功率 [dBFS] 或相对于实际输入载波信号的功率 [dBc]。
总谐波失真 (THD) 是头八个谐波（HD2 直到 HD9）的总功率与输入信号功率的比，单位 dB。THD 通常表示为相
对于可能的满量程正弦波功率 [dBFS]，或者相对于实际输入载波信号的功率 [dBc]。
12.1.1.2 JESD204B 定义
器件时钟
是主时钟信号，器件必须从这个时钟信号中生成其本地帧和本地多帧时钟。对于 ADC14X250 器件，
它指的是 CLKIN 输入处的信号。
帧
是一组连续的八位字节，可参考一个帧校准信号来确定每个八位字节的位置。
帧时钟
是用来对帧进行排序，并且监控它们的校准情况的信号。对于 ADC14X250 器件，此时钟在内部产生
且外部不可用。
链接（数据链接） 是一个组装部件，由两个器件和它们之间的互连数据电路组成，由长协议使能数据（从一个数
据源传输到一个数据接收端）控制。链路包括 ADC14X250 器件（发送器）、现场可编程门阵列
(FPGA) 或专用集成电路 (ASIC)（接收器）以及与其相连的硬件。
本地多帧时钟 (LMFC) 是用来对多帧进行排序，并监控它们校准情况的信号。此时钟是由 ADC14X250 器件内部的
器件时钟产生，用于实现器件内部的 JESD204B 链路。
多帧
是一组连续的帧，可参考一个多帧校准信号来确定每个帧的位置。
八位字节
换序
是一组八个邻近二进制位，作为到 8B/10B 编码器的输入，或 8B/10B 解码器的输出。
是输出数据随机选择，用来消除连续同一已发射符号的长字符串，并且在不改变信令速率的情况下，
避免在信号频谱中出现频谱线。
串行信道
是针对一个方向数据传输的差分信号对。
SYSREF
是周期性的、单次、或断续周期信号，此信号用来在 JESD204B 1 子类兼容器件中校准本地多帧时钟
的边界。SYSREF 的源必须与器件时钟同步。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每周
定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
64
版权 © 2015–2017, Texas Instruments Incorporated
ADC14X250
www.ti.com.cn
ZHCSEE8B –DECEMBER 2015–REVISED APRIL 2017
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械封装、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据发生变化时，
我们可能不会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
版权 © 2015–2017, Texas Instruments Incorporated
65
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC14X250RHBR
ADC14X250RHBT
ACTIVE
ACTIVE
VQFN
VQFN
RHB
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
14X250
14X250
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC14X250RHBR
VQFN
RHB
32
3000
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHB 32
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADC14X250RHBR
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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