ADC16V130CISQE/NOPB [TI]

16 位、130MSPS 模数转换器 (ADC) | NKD | 64 | -40 to 85;


型号：	ADC16V130CISQE/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	16 位、130MSPS 模数转换器 (ADC) \| NKD \| 64 \| -40 to 85 转换器模数转换器
文件：	总32页 (文件大小：1729K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC16V130

www.ti.com

SNAS458E –NOVEMBER 2008–REVISED MARCH 2013

ADC16V130 16-Bit, 130 MSPS A/D Converter With LVDS Outputs

Check for Samples: ADC16V130

FEATURES

APPLICATIONS

•

Dual Supplies: 1.8V and 3.0V Operation

•

High IF Sampling Receivers

On Chip Automatic Calibration During Power-

Multi-carrier Base Station Receivers

–

GSM/EDGE, CDMA2000, UMTS, LTE, and

WiMax

•

Low Power Consumption

Multi-Level Multi-Function Pins for CLK/DF and

•

Test and Measurement Equipment

Communications Instrumentation

Data Acquisition

•

Power-Down and Sleep Modes

On Chip Precision Reference and Sample-and-

Hold Circuit

Portable Instrumentation

•

On Chip Low Jitter Duty-Cycle Stabilizer

Offset Binary or 2's Complement Data Format

Full Data Rate LVDS Output Port

DESCRIPTION

The ADC16V130 is a monolithic high performance

CMOS analog-to-digital converter capable of

converting analog input signals into 16-bit digital

words at rates up to 130 Mega Samples Per Second

(MSPS). This converter uses a differential, pipelined

architecture with digital error correction and an on-

chip sample-and-hold circuit to minimize power

consumption and external component count while

providing excellent dynamic performance. Automatic

power-up calibration enables excellent dynamic

performance and reduces part-to-part variation, and

the ADC16V130 could be re-calibrated at any time by

asserting and then de-asserting power-down. An

integrated low noise and stable voltage reference and

differential reference buffer amplifier easies board

level design. On-chip duty cycle stabilizer with low

additive jitter allows wide duty cycle range of input

clock without compromising its dynamic performance.

A unique sample-and-hold stage yields a full-power

bandwidth of 1.4 GHz. The digital data is provided via

full data rate LVDS outputs – making possible the 64-

pin, 9mm x 9mm WQFN package. The ADC16V130

operates on dual power supplies +1.8V and +3.0V

with a power-down feature to reduce the power

consumption to very low levels while allowing fast

recovery to full operation.

64-pin WQFN Package (9x9x0.8, 0.5mm Pin-

Pitch)

KEY SPECIFICATIONS

•

Resolution: 16 Bits

Conversion Rate: 130 MSPS

SNR

–

(f_IN= 10MHz): 78.5 dBFS (Typ)

(f_IN= 70MHz): 77.8 dBFS (Typ)

(f_IN= 160MHz): 76.7 dBFS (Typ)

•

SFDR

–

(f_IN= 10MHz): 95.5 dBFS (Typ)

(f_IN= 70MHz): 92.0 dBFS (Typ)

(f_IN= 160MHz): 90.6 dBFS (Typ)

•

Full Power Bandwidth: 1.4 GHz (Typ)

Power Consumption

–

Core: 650 mW (Typ)

LVDS Driver: 105 mW (Typ)

Total: 755 mW (Typ)

•

Operating Temperature Range: -40°C ~ 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADC16V130

SNAS458E –NOVEMBER 2008–REVISED MARCH 2013

www.ti.com

Block Diagram

CLK+

DUTY CYCLE

STABILIZER

CLK-

DO+/-, OR+/-

OUTCLK+/-

IN+

16BIT HIGH SPEED

PIPELINE ADC

ERROR CORRECTION

LOGIC

SDR LVDS

BUFFER

SHA

IN-

CALIBRATION ENGINE

INTERNAL

REFERENCE

REF

MULTI-LEVEL

FUNCTION

Connection Diagram

CLK_SEL/DF

V_A3.0

D13+

D13-

EXPOSED PADDLE ON BOTTOM

OF PACKAGE, PIN 0

AGND

V_RN

D12+

D12-

V_RN

V_DR

V_RP

DRGND

V_RP

42 D11+

AGND

V_A1.8

CLK+

CLK-

AGND

V_AD1.8

D11-

ADC16V130

(Top View)

D10+

D10-

D9+

D9-

D8+

D8-

DO-

OUTCLK+

OUTCLK-

DO+

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SNAS458E –NOVEMBER 2008–REVISED MARCH 2013

PIN DESCRIPTIONS

Pin No.

ANALOG I/O

Symbol

Equivalent Circuit

Function and Connection

V_IN+

A3.0

Differential analog input pins. The differential full-scale input signal

level is 2.4Vpp as default. Each input pin signal centered on a

V_IN-

common mode voltage, V_CM

AGND

Upper reference voltage.

This pin should not be used to source or sink current. The decoupling

capacitor to AGND (low ESL 0.1μF) should be placed very close to

the pin to minimize stray inductance. V_RPneeds to be connected to

V_RNthrough a low ESL 0.1μF and a low ESR 10μF capacitors in

parallel.

6,7

V_RP

A3.0

Lower reference voltage.

A3.0

This pin should not be used to source or sink current. The decoupling

capacitor to AGND (low ESL 0.1μF) should be placed very close to

the pin to minimize stray inductance. V_RNneeds to be connected to

V_RPthrough a low ESL 0.1μF and a low ESR 10μF capacitors in

parallel.

4,5

V_RN

REF

A3.0

Common mode voltage

The decoupling capacitor to AGND (low ESL 0.1μF) should be placed

as close to the pin as possible to minimize stray inductance. It is

recommended to use V_RMto provide the common mode voltage for

the differential analog inputs.

V_RM

AGND

Internal reference voltage output / External reference voltage input.

By default, this pin is the output for the internal 1.2V voltage

reference. This pin should not be used to sink or source current and

should be decoupled to AGND with a 0.1μF, low ESL capacitor. The

decoupling capacitors should be placed as close to the pins as

possible to minimize inductance and optimize ADC performance. The

size of decoupling capacitor should not be larger than 0.1μF,

otherwise dynamic performance after power-up calibration can drop

due to the long V_REFsettling.

A3.0

V_REF

This pin can also be used as the input for a low noise external

reference voltage. The output impedance for the internal reference at

this pin is 9 kΩ and this can be overdriven provided the impedance of

the external source is <<9 kΩ. Careful decoupling is just as essential

when an external reference is used. The 0.1µF low ESL decoupling

capacitor should be placed as close to this pin as possible.

AGND

The Input differential voltage swing is equal to 2 * V_REF

CLK+

V_A3.0

V_A1.8

Differential clock input pins. DC biasing is provided internally. For

single-ended clock mode, drive CLK+ through AC coupling while

decoupling CLK- pin to AGND.

CLK−

AGND

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PIN DESCRIPTIONS (continued)

Pin No.

Symbol

Equivalent Circuit

Function and Connection

DIGITAL I/O

D0+/- to D3+/-

D4+/- to D7+/-

D8+/- to D11+/-

D12+/- to

LVDS Data Output. The 16-bit digital output of the data converter is

provided on these ports in a full data rate manner. A 100 Ω

termination resistor must be placed between each pair of differential

signals at the far end of the transmission line.

15 – 22

25 – 32

35 – 42

45 – 52

D15+/-

A3.0

Over-Range Indicator. Active High.

This output is set High when analog input signal exceeds full scale of

16 bit conversion range (<0,> 65535). This signal is asserted

coincidently with the over-range data word. A 100 Ω termination

resistor must be placed between the differential signals at the far end

of the transmission.

53, 54

33, 34

OR+/-

D+

D-

Output Clock. This pin is used to clock the output data. It has the

same frequency as the sampling clock. One word of data is output in

each cycle of this signal. A 100 Ω termination resistor must be placed

between the differential clock signals at the far end of the transmission

line. The rising edge of this signal should be used to capture the

output data. See the detail Section on Timing Diagrams .

AGND

DRGND

AGND

OUTCLK+/-

This is a three-state pin.

PD = V_A3.0, then Power Down is enabled. In the Power Down state,

only the reference voltage circuitry remains active and power

dissipation is reduced.

PD =V_A3.0* (2/3), then Sleep mode is enabled. In Sleep mode is

similar to Power Down mode - it consumes more power but has a

faster recovery time.

A3.0

PD = AGND, then Normal operation mode is turned on.

This is a four-state pin controlling two parameters: input clock

selection and output data format.

CLK_SEL/DF = V_A3.0, then CLK+ and CLK− are configured as a

differential clock input and the output data format is 2's complement.

CLK_SEL/DF = V_A3.0* (2/3), then CLK+ and CLK− are configured as

a differential clock input and the output data format is offset binary.

CLK_SEL/DF = V_A3.0* (1/3), then CLK+ is configured as a single-

ended clock input and CLK− should be tied to AGND. The output data

format is 2's complement.

AGND

CLK_SEL/DF

CLK_SEL/DF = AGND, then CLK+ is configured as a single-ended

clock input and CLK− should be tied to AGND. The output data format

is offset binary.

POWER SUPPLIES

3.0V Analog Power Supply. These pins should be connected to a

quiet source and should be decoupled to AGND with 0.1μF capacitors

located close to the power pins.

2, 55, 59

9, 64

V_A3.0

Analog Power

1.8V Analog Power Supply. These pins should be connected to a

quiet source and should be decoupled to AGND with 0.1μF capacitors

located close to the power pins.

V_A1.8

V_AD1.8

AGND

1.8V Analog/Digital Power Supply. These pins should be connected to

a quiet source and should be decoupled to AGND with 0.1μF

capacitors located close to the power pins.

Analog/Digital Power

Analog Ground

Analog Ground Return. The exposed pad (Pin 0) on back of the

package must be soldered to ground plane to ensure rated

performance.

0, 3, 8, 12,

56, 60, 63

Output Driver Power Supply. This pin should be connected to a quiet

voltage source and be decoupled to DRGND with a 0.1μF capacitor

close to the power pins.

24, 44

23, 43

V_DR

Power

DRGND

Ground

Output Driver Ground Return.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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SNAS458E –NOVEMBER 2008–REVISED MARCH 2013

Absolute Maximum Ratings^(1)(2)(3)

Supply Voltage (V_A3.0

)

−0.3V to 4.2V

−0.3V to 2.35V

Supply Voltage (V_A1.8, V_AD1.8, V_DR

)

Voltage at any Pin except D0-D15, OVR, OUTCLK, CLK, V_IN

−0.3V to (V_A3.0+0.3V)

(Not to exceed 4.2V)

Voltage at CLK, V_INPins

-0.3V to (V_DR+0.3V)

(Not to exceed 2.35V)

Voltage at D0-D15, OR, OUTCLK Pins

0.3V to (V_DR+ 0.3V)

(Not to exceed 2.35V)

Input Current at any pin⁽⁴⁾

Storage Temperature Range

Maximum Junction Temp (T_J)

5 mA

-65°C to +150°C

+150°C

Thermal Resistance (θ_JA

)

20.4°C/W

1.4°C/W

Thermal Resistance (θ_JC

)

ESD Rating⁽⁵⁾

Machine Model

200 V

Human Body Model

2000 V

Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.⁽⁶⁾

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be

limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of ±5 mA to 10.

(5) Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω.

(6) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Operating Ratings⁽¹⁾⁽²⁾

Specified Temperature Range:

-40°C to +85°C

+2.7V to +3.6V

+1.7V to +1.9V

30/70 %

3.0V Analog Supply Voltage Range: (V_A3.0

)

1.8V Supply Voltage Range: V_A1.8, V_AD1.8, V_DR

Clock Duty Cycle

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is ensured to be functional, but do not ensure specific performance limits. For ensured specifications and test

conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance

characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the

maximum Operating Ratings is not recommended.

(2) All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

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Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_A3.0= +3.0V, V_A1.8= V_AD1.8= V_DR= +1.8V, f_CLK= 130 MSPS,

A_IN= -1dBFS, LVDS Rterm = 100 Ω, C_L= 5 pF. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX

All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Typical

Units

(Limits)

Symbol

Parameter

Conditions

Limits

(2)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

Bits (min)

LSB

INL

Integral Non Linearity

Differential Non Linearity

Positive Gain Error

±1.5

±0.45

-4.2

3.7

DNL

PGE

NGE

V_OFF

LSB

%FS

Negative Gain Error

%FS

Offset Error (V_IN+ = V_IN−)

Under Range Output Code

Over Range Output Code

0.12

%FS

65535

REFERENCE AND ANALOG INPUT CHARACTERISTICS⁽³⁾

V_RMis the common mode reference

voltage

V_CM

Common Mode Input Voltage

V_RM±0.05

1.15

Reference Ladder Midpoint Output

Voltage

V_RM

V_REF

Internal Reference Voltage

1.20

2.4

Differential Analog Input Range

Internal Reference

V_PP

(1) The inputs are protected as shown below. Input voltage magnitudes above V_A3.0or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section see Figure 1.

(2) Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(3) The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

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Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_A3.0= +3.0V, V_A1.8= V_AD1.8= V_DR= +1.8V, f_CLK= 130 MSPS,

A_IN= -1dBFS, LVDS Rterm = 100 Ω, C_L= 5 pF. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX

All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Symbol

Parameter

Resolution with no missing codes

Dynamic Range

Conditions

Typ

Limits

Units

Bits

0V analog input is applied

78.5

78.2

77.8

76.7

75.6

95.5

dBFS

Bits

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

Fin = 10 MHz

Fin = 40 MHz

Fin = 70 MHz

Fin = 160 MHz

Fin = 240 MHz

SNR

SFDR

THD

Signal-to-Noise Ratio⁽²⁾

75.5

Single-tone Spurious Free Dynamic

Range⁽²⁾

90.6

85.3

-91.5

-88.4

-89.4

-87.1

-82.8

-95.5

-104.1

-95.6

-91.5

-85.3

-98.3

-89.4

-92

Total Harmonic Distortion⁽²⁾

Second-order Harmonic⁽²⁾

Third-order Harmonic⁽²⁾

-81

-88

-87

-90.6

-87.8

106

103.2

104.1

101.5

98.4

78.3

77.8

77.5

76.3

74.8

12.7

12.6

12.4

12.1

Worst Harmonic or Spurious Tone

excluding H2 and H3⁽²⁾

Spur-H2/3

SINAD

ENOB

Signal-to-Noise and Distortion Ratio⁽²⁾

Bits

Effective Number of Bits

Bits

(1) The inputs are protected as shown below. Input voltage magnitudes above V_A3.0or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section see Figure 1.

(2) This parameter is specified in units of dBFS – indicating the equivalent value that would be attained with a full-scale input signal.

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Dynamic Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply: V_A3.0= +3.0V, V_A1.8= V_AD1.8= V_DR= +1.8V, f_CLK= 130 MSPS,

A_IN= -1dBFS, LVDS Rterm = 100 Ω, C_L= 5 pF. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX

All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Symbol

Parameter

Full Power Bandwidth

Conditions

-3dB Compression Point

Typ

Limits

Units

1.4

GHz

Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_A3.0= +3.0V, V_A1.8= V_AD1.8= V_DR= +1.8V, f_CLK= 130 MSPS,

A_IN= -1dBFS, LVDS Rterm = 100 Ω, C_L= 5 pF. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX

All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Units

Symbol

Parameter

Conditions

Typical

Limits

(Limits)

mA (max)

I_A3.0

I_A1.8

I_AD1.8R

I_DR

Analog 3.0V Supply Current

Analog 1.8V Supply Current

Digital 1.8V Supply Current

Output Driver Supply Current

Core Power Consumption

Full Operation⁽²⁾

174.5

208

(2)

Full Operation

58.3

650

(2)

Excludes I_DR

773

mW (max)

Current drawn from the V_DRsupply; Fin =

10 MHz Rterm = 100Ω

Driver Power Consumption

105

Normal operation; Fin = 10 MHz

Power down state, with external clock

Sleep state, with external clock

755

Total Power Consumption

(1) The inputs are protected as shown below. Input voltage magnitudes above V_A3.0or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section see Figure 1.

(2) This parameter is ensured only at 25°C. For power dissipation over temperature range, refer to Core Power vs. Temperature plot in

Typical Performance Characteristics, Dynamic Performance

LVDS Electrical Characteristics

Unless otherwise specified, the following specifications apply: V_A3.0= +3.0V, V_A1.8= V_AD1.8= V_DR= +1.8V, f_CLK= 130 MSPS,

A_IN= -1dBFS, LVDS Rterm = 100 Ω, C_L= 5 pF. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤ T_MAX

All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LVDS DC SPECIFICATIONS (apply to pins DO to D15, OR)

V_OD

V_OS

I_OS

Output Differential Voltage

Output Offset Voltage

100 Ω Differential Load

0 Ω Differential Load

Termination is open

175

250

1.2

2.5

± 1

325

1.15

1.25

Output Short Circuit Current

Output Open Circuit Current

µA

I_OZ

-20

(1) The inputs are protected as shown below. Input voltage magnitudes above V_A3.0or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section see Figure 1.

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Timing Specifications

Unless otherwise specified, the following specifications apply: V_IN= -1dBFS, AGND = DRGND = 0V, V_A3.0= +3.0V, V_A1.8

V_AD1.8= V_DR= +1.8V, Internal V_REF= +1.2V, f_CLK= 130 MHz, V_CM= V_RM, C_L= 5 pF, Single-Ended Clock Mode, Offset Binary

Format. Typical values are for T_A= 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits

apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A= 25°C, unless otherwise noted.⁽¹⁾

Parameter

Input Clock Frequency

Conditions

Typ

Limits

130

Units

MHz (max)

MHz (min)

nS (min)

Minimum Clock Frequency

Data Output Setup Time (Tsu)⁽²⁾

Data Output Hold Time (Th)⁽²⁾

Pipeline Latency⁽³⁾

Measured @ Vdr/2; Fclk = 130 MHz.

3.3

2.5

Clock

Cycles

Aperture Jitter

fS rms

Power-Up Time

From assertion of Power to specified level of

performance.

0.5+ 10³*(2²²+2¹⁶)/FCLK

0.1+ 10³*(2¹⁹+2¹⁶)/FCLK

100

Power-Down Recovery Time

Sleep Recovery Time

From de-assertion of power down mode to

output data available.

From de-assertion of sleep mode to output

data available.

μS

(1) The inputs are protected as shown below. Input voltage magnitudes above V_A3.0or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section see Figure 1.

(2) This parameter is a function of the CLK frequency - increasing directly as the frequency is lowered. At frequencies less than 130 MHz,

use the following formulae to calculate the setup and hold times:

For Data and OR+/- Outputs: Tsu = ½*Tp – 0.5 ns (typical)

For Data and OR+/- Outputs: Th = ½*Tp – 0.5 ns (typical)

where Tp = CLK input period = OUTCLK period

(3) Input signal is sampled with the falling edge of the CLK input.

A3.0

To Internal

Circuitry

I/O

AGND

Figure 1.

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Specification Definitions

APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for

conversion.

APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.

Aperture jitter manifests itself as noise in the output.

CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the

total time of one period. The specification here refers to the ADC clock input signal.

COMMON MODE VOLTAGE (V_CM) is the common DC voltage applied to both input terminals of the ADC.

CONVERSION LATENCY is the number of clock cycles between initiation of conversion and the time when data

is presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline

Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data

lags the conversion by the pipeline delay.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:

Gain Error = Positive Full Scale Error − Negative Full Scale Error

(1)

(2)

It can also be expressed as Positive Gain Error and Negative Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a best fit straight

line. The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the smallest value or weight of all bits. This value is V_FS/2ⁿ,

where “V_FS” is the full scale input voltage and “n” is the ADC resolution in bits.

MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC16V130 is ensured

not to have any missing codes.

MSB (MOST SIGNIFICANT BIT) is the bit that has the largest value or weight. Its value is one half of full scale.

NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of

½ LSB above negative full scale.

OFFSET ERROR is the difference between the two input voltages (V_IN+– V_IN-) required to cause a transition from

code 32767LSB and 32768LSB with offset binary data format.

PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.

POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of

1½ LSB below positive full scale.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the power of input signal to the total power of

all other spectral components below one-half the sampling frequency, not including harmonics and DC.

SIGNAL TO NOISE AND DISTORTION (SINAD) Is the ratio, expressed in dB, of the power of the input signal to

the total power of all of the other spectral components below half the clock frequency, including harmonics but

excluding DC.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the power of input

signal and the peak spurious signal power, where a spurious signal is any signal present in the output spectrum

that is not present at the input.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total power of the first seven

harmonic to the input signal power. THD is calculated as:

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f₂²+ f₃²+ ... + f₈

THD = 20log₁₀

f₁²

where

•

f₁²is the power of the fundamental frequency and f₂²through f₈²are the powers of the first seven harmonics in

the output spectrum. (3)

SECOND HARMONIC DISTORTION (2^NDHARM or H2) is the difference expressed in dB, from the power of

its 2^ndharmonic level to the power of the input signal.

THIRD HARMONIC DISTORTION (3^RDHARM or H3) is the difference expressed in dB, from the power of

the 3^ndharmonic level to the power of the input signal.

HIGHEST SPURIOUS EXCEPT H2 and H3 (Spur-H2/3) is the difference, expressed in dB, between the

power of input signal and the peak spurious signal power except H2 and H3, where a spurious signal is any

signal present in the output spectrum that is not present at the input.

Timing Diagrams

Sample N+12

Vin

Sample N+11

Sample N

t_AD

T_P

CLK+

CLK-

Latency

T_P

OUTCLK+

OUTCLK-

T_SU

T_h

Word N-1

Word N+1

Word N

Dx+/-, OR+/-

Figure 2. Digital Output Timing

Transfer Characteristic

Figure 3. Transfer Characteristic (Offset Binary Format)

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Typical Performance Characteristics, DNL, INL

Unless otherwise noted, these specifications apply: V_A3.0= +3.0V, V_A1.8, V_AD1.8, V_DR= 1.8V, f_CLK= 130 MSPS. Differential

Clock Mode, Offset Binary Format. LVDS Rterm = 100 Ω. C_L= 5 pF. Typical values are at T_A= +25°C. Fin = 10MHz with

–1dBFS.

DNL

INL

Figure 4.

Figure 5.

DNL vs.V_A3.0

INL vs .V_A3.0

Figure 6.

Figure 7.

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Typical Performance Characteristics, Dynamic Performance

Unless otherwise noted, these specifications apply: V_A3.0= +3.0V, V_A1.8, V_AD1.8, V_DR= 1.8V, f_CLK= 130 MSPS. Differential

Clock Mode, Offset Binary Format. LVDS Rterm = 100 Ω. C_L= 5 pF. Typical values are at T_A= +25°C. Fin = 160MHz with

–1dBFS..

SNR, SINAD, SFDR vs. f_IN

DISTORTION vs. f_IN

Figure 8.

Figure 9.

SNR, SINAD, SFDR vs. V_A3.0

DISTORTION vs. V_A3.0

Figure 10.

Figure 11.

SNR, SINAD, SFDR vs. V_AD1.8

DISTORTION vs. V_AD1.8

Figure 12.

Figure 13.

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Typical Performance Characteristics, Dynamic Performance (continued)

Unless otherwise noted, these specifications apply: V_A3.0= +3.0V, V_A1.8, V_AD1.8, V_DR= 1.8V, f_CLK= 130 MSPS. Differential

Clock Mode, Offset Binary Format. LVDS Rterm = 100 Ω. C_L= 5 pF. Typical values are at T_A= +25°C. Fin = 160MHz with

–1dBFS..

Spectral Response @ 10.11 MHz

Spectral Response @ 160.11 MHz

Figure 14.

Figure 15.

Spectral Response @ 40.11 MHz

Spectral Response @ 240.11 MHz

Figure 16.

Figure 17.

Spectral Response @ 70.11 MHz

Core Power vs. Temperature (Excludes I_DR)

Figure 18.

Figure 19.

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FUNCTIONAL DESCRIPTION

Operating on dual +1.8 and +3.0V supplies, the ADC16V130 digitizes a differential analog input signals to 16

bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold

circuit to ensure maximum performance. The user has the choice of using an internal 1.2V stable reference, or

using an external 1.2V reference. Internal 1.2V reference has high output impedance of > 9 kΩ and can be easily

over-driven by external reference. Two multi-level multi-function pins can program data format, clock mode,

power down and sleep mode.

ADC Architecture

The ADC16V130 architecture consists of a highly linear and wide bandwidth sample-and-hold circuit, followed by

a switched capacitor pipeline ADC. Each stage of the pipeline ADC consists of low resolution flash sub-ADC and

an inter-stage multiplying digital-to-analog converter (MDAC), which is a switched capacitor amplifier with a fixed

stage signal gain and DC level shifting circuits. The amount of DC level shifting is dependent on sub-ADC digital

output code. 16bit final digital output is the result of the digital error correction logic, which receives digital output

of each stage including redundant bits to correct offset error of each sub-ADC.

APPLICATIONS INFORMATION

OPERATING CONDITIONS

We recommend that the following conditions be observed for operation of the ADC16V130:

2.7V ≤ V_A3.0≤ 3.6V

1.7V ≤ V_A1.8≤ 1.9V

1.7V ≤ V_AD1.8≤ 1.9V

1.7V ≤ V_DR≤ 1.9V

5 MSPS ≤ F_CLK≤ 130 MSPS

V_REF≤ 1.2V

V_CM= 1.15V (from V_RM

)

ANALOG INPUTS

Analog input circuit of the ADC16V130 is a differential switched capacitor sample-and-hold circuit (see Figure 20)

that provides optimum dynamic performance wide input frequency range with minimum power consumption. The

clock signal alternates sample mode (Q_S) and hold mode (Q_H). An integrated low jitter duty cycle stabilizer

ensures constant optimal sample and hold time over wide range of input clock duty cycle. The duty cycle

stabilizer is always turned on during normal operation.

During sample mode, analog signals (V_IN+, V_IN-) are sampled across two sampling capacitor (C_S) while the

amplifier in the sample-and-hold circuit is idle. The dynamic performance of the ADC16V130 is likely determined

during sampling mode. The sampled analog inputs (V_IN+, V_IN-) are held during hold mode by connecting input

side of the sampling capacitors to output of the amplifier in the sample-and-hold circuit while driving pipeline ADC

core.

The signal source, which drives the ADC16V130, is recommended to have source impedance less than 100 Ω

over wide frequency range for optimal dynamic performance.

A shunt capacitor can be placed across the inputs to provide high frequency dynamic charging current during

sample mode and also absorb any switching charge coming from the ADC16V130. A shunt capacitor can be

placed across each input to GND for similar purpose. Smaller physical size and low ESR and ESL shunt

capacitor is recommended.

The value of shunt capacitor should be carefully chosen to optimize the dynamic performance at certain input

frequency range. Larger value shunt capacitors can be used for low input frequency range, but the value has to

be reduced at high input frequency range.

Balancing impedance at positive and negative input pin over entire signal path must be ensured for optimal

dynamic performance.

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IN+

IN -

Figure 20. Simplified Switched-Capacitor Sample-and-hold Circuit

Input Common Mode

The analog inputs of the ADC16V130 are not internally dc biased and the range of input common mode is very

narrow. Hence it is highly recommended to use the common mode voltage (V_RM, typically 1.15V) as input

common mode for optimal dynamic performance regardless of DC and AC coupling applications. Input common

mode signal must be decoupled with low ESL 0.1μF at the far end of load point to minimize noise performance

degradation due to any coupling or switching noise between the ADC16V130 and input driving circuit.

Driving Analog Inputs

For low frequency applications, either a flux or balun transformer can convert single-ended input signal into

differential and drive the ADC16V130 without additive noise. An example is shown in Figure 21. V_RMpin is used

to bias the input common mode by connecting the center tap of the transformer’s secondary ports. Flux

transformer is used for this example, but AC coupling capacitors should be added once balun type transformer is

used.

IN+

ADC16V130

0.1 mF

Figure 21. Transformer Drive Circuit for Low Input Frequency

Transformer has a characteristic of band pass filtering. It sets lower band limit by being saturated at frequencies

below a few MHz and sets upper frequency limit due to its parasitic resistance and capacitance. The transformer

core will be saturated with excessive signal power and it causes distortion as equivalent load termination

becomes heavier at high input frequencies. This is a reason to reduce shunt capacitors for high IF sampling

application to balance the amount of distortion caused by transformer and charge kick-back noise from the

device.

As input frequency goes higher with the input network in Figure 22, amplitude and phase unbalance increase

between positive and negative inputs (V_IN+and V_IN-) due to the inherent impedance mismatch between the two

primary ports of the transformer while one is connected to the signal source and the other is connected to GND.

Distortion increases as the result.

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Cascaded transmission line transformers can be used for high frequency applications like high IF sampling base

station receiver channel. Transmission line transformer has less stray capacitance between primary and

secondary ports and so the amount of impedance at secondary ports is effectively less even with the given

inherent impedance mismatch on the primary ports. Cascading two transmission line transformers further

reduces the effective stray capacitance from the secondary of ports of the secondary transformer to primary ports

of first transformer, where impedance is mismatched. A transmission line transformer, for instance MABACT0040

from M/A-COM, with center tap on secondary port could further reduce amplitude and phase mismatch.

0.1 mF

IN+

ADC16V130

0.1 mF

Figure 22. Transformer Drive Circuit for High Input Frequency

Equivalent Input Circuit and Its S11

Input circuit of the ADC16V130 during sample mode is a differential switched capacitor as shown in Figure 23.

Bottom plate sampling switch is bootstrapped in order to reduce its turn on impedance and its variation across

input signal amplitude. Bottom plate sampling switches and top plate sampling switch are all turned off during

hold mode. The sampled analog input signal is processed throughout the following pipeline ADC core. Equivalent

impedance changes drastically between sample and hold mode while significant amount of charge injection

occurs during the transition between the two operating modes.

Distortion and SNR heavily rely on the signal integrity, impedance matching during sample mode and charge

injection while switching sampling switches.

V_IN+

V_IN-

Figure 23. Input Equivalent Circuit

A measured S11 of the input circuit of the ADC16V130 is shown in Figure 24 (Currently the figure is a simulated

one. It is subject to be changed later. Note that the simulated S11 closely matches with the measured S11). Up

to 500 MHz, it is predominantly capacitive loading with small stray resistance and inductance as shown in

Figure 24. An appropriate resistive termination at a given input frequency band has to be added to improve

signal integrity. Any shunt capacitor on analog input pin deteriorates signal integrity but it provides high frequency

charge to absorb the charge inject generated while sampling switches are toggling. A optimal shunt capacitor is

dependent on input signal frequency as well as impedance characteristic of analog input signal path including

components like transformer, termination resistor, DC coupling capacitors.

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Figure 24. S11 Curve of Input Circuit

CLOCK INPUT CONSIDERATIONS

Clock Input Modes

The ADC16V130 provides a low additive jitter differential clock receiver for optimal dynamic performance at wide

input frequency range. Input common mode of the clock receiver is internally biased at V_A1.8/2 through a 10 kΩ

each to be driven by DC coupled clock input as shown in Figure 25. However while DC coupled clock input

drives CLK+ and CLK-, it is recommend the common mode (average voltage of CLK+ and CLK-) not to be higher

than V_A1.8/2 in order to prevent substantial tail current reduction, which might cause lowered jitter performance.

Meanwhile, CLK+ and CLK- should not become lower than AGND. A high speed back-to-back diode connected

between CLK+ and CLK- could limit the maximum swing, but this could cause signal integrity concerns when the

diode turns on and reduce load impedance instantaneously.

A preferred differential clocking through a transformer coupled is shown in Figure 26. A 0.1μF decoupling

capacitor on the center tap of the secondary ports of a flux type transformer stabilizes clock input common mode.

Differential clocking increases the maximum amplitude of the clock input at the pins twice as large as that with

singled-ended mode as shown in Figure 27. Clock amplitude is recommended to be as large as possible while

CLK+ and CLK- both never exceed supply rails of V_A1.8and AGND. With a given equivalent input noise of the

differential clock receiver shown in Figure 25, larger clock amplitude at CLK+ and CLK- pins increases its slope

around zero-crossing point so that higher signal-to-noise could be obtained by reducing the noise contributed by

clock signal path.

A1.8

CLK +

CLK

10k

A1.8

Figure 25. Equivalent Clock Receiver

The differential receiver of the ADC16V130 has excellent low noise floor but its bandwidth is wide as multiple

times of clock rate. The wide band noise folds back to nyquist frequency band in frequency domain at ADC

output. Increased slope of the input clock lowers the equivalent noise contributed by the differential receiver.

A band-pass filter (BPF) with narrow pass band and low insertion loss could be added on the clock input signal

path when wide band noise of clock source is noticeably large compared to the input equivalent noise of the

differential clock receiver.

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Load termination could be a combination of R and C instead of a pure R. This RC termination could improve

noise performance of clock signal path by filtering out high frequency noise through a low pass filter. The size of

R and C is dependent on the clock rate and slope of the clock input.

A LVPECL and/or LVDS driver could also drive the ADC16V130. However the full dynamic performance of the

ADC16V130 might not be achieved due to the high noise floor of the driving circuit itself especially in high IF

sampling application.

CLOCK

INPUT

CLK +

ADC16V130

CLK

0.1 mF

Figure 26. Differential Clocking, Transformer Coupled

Singled-ended clock can drive CLK+ pin through a 0.1μF AC coupling capacitor while CLK- is decoupled to

AGND through a 0.1μF capacitor as shown in Figure 27.

0.1mF

CLOCK

CLK

INPUT

ADC 16 V 130

CLK

0.1mF

Figure 27. Singled-Ended 1.8V Clocking, Capacitive AC Coupled

Duty Cycle Stabilizer

Highest operating speed with optimal performance could be only achieved with 50% of clock duty cycle because

the switched-capacitor circuit of the ADC16V130 is designed to have equal amount of settling time between each

stage. The maximum operating frequency could be reduced accordingly while clock duty cycle departs from 50%.

The ADC16V130 contains a duty cycle stabilizer that adjusts non-sampling (rising) clock edge to make the duty

cycle of the internal clock over 30 to 70% of input clock duty cycle. The duty cycle stabilizer is always on

because the noise and distortion performance are not affected at all. It is not recommended to use the

ADC16V130 at the clock frequencies less than 5 MSPS, at which the feedback loop in the duty cycle stabilizer

becomes unstable.

Clock Jitter vs. Dynamic Performance

High speed and high resolution ADCs require low noise clock input to ensure its full dynamic performance over

wide input frequency range. SNR (SNR_Fin) at a given input frequency (Fin) can be calculated by:

A²/2

V_N²+ (2pFin x Tj)²

SNR_Fin= 10log₁₀

with a given total noise power (V_N²) of an ADC, total rms jitter (Tj), and input amplitude (A) in dBFS.

Clock signal path must be treated as an analog signal whenever aperture jitter affects the dynamic performance

of the ADC16V130. Power supplies for the clock drivers has to be separated from the ADC output drive supplies

to prevent modulated clock signal with the ADC digital output signals. Higher noise floor and/or increased

distortion/spur might result from any coupling noise from ADC digital output signals to analog input and clock

signals.

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In IF sampling applications, the signal-to-noise ratio is particularly affected by clock jitter as shown in Figure 28.

Tj is the integrated noise power of the clock signal divided by the slope of clock signal around tripping point.

Upper limit of the noise integration is independent of applications and set by the bandwidth of the clock signal

path. However lower limit of the noise integration highly relies on the applications. In base station receiver

channel applications, the lower limit is determined by channel bandwidth and space from an adjacent channel.

50fs

75fs

100fs

200fs

400fs

800fs

1.5ps

100

1000

INPUT FREQUENCY (MHz)

Figure 28. SNR with given Jitter vs. Input Frequency

CALIBRATION

Automatic calibration engine contained within the ADC16V130 improves dynamic performance and reduces its

part-to-part variation. Digital output signals including output clock (OUTCLK+/-) are all logic low while calibrating.

The ADC16V130 is automatically calibrated when the device is powered up. Optimal dynamic performance might

not be obtained if power-up time is longer than internal delay time (~32mS @ 130 MSPS clock rate). In this case,

the ADC16V130 could be re-calibrated by asserting and then de-asserting power down mode. Re-calibration is

recommended whenever operating clock rate changes.

VOLTAGE REFERENCE

A stable and low noise voltage reference and its buffer amplifier are built into the ADC16V130. The input full

scale is two times of V_REF, which is same as VBG (On-chip bandgap output having 9 kΩ output impedance) as

well as V_RP- V_RNas shown in Figure 29. The input range can be adjusted by changing V_REFeither internally or

externally. An external reference with low output impedance can easily over-drive V_REFpin. Default V_REFis 1.2V.

Input common mode voltage (V_RM) is a fixed voltage level of 1.15V. Maximum SNR can be achieved at maximum

input range of 1.2V V_REF. Although the ADC16V130 dynamic and static performance is optimized at V_REFof 1.2V,

reducing V_REFcan improve SFDR performance with sacrificing SNR of the ADC16V130.

Reference Decoupling

It is highly recommended to place external decoupling capacitors connected to V_RP, V_RN, V_RMand V_REFpins as

close to pins as possible. The external decoupling capacitor should have minimal ESL and ESR. During normal

operation, inappropriate external decoupling with large ESL and/or ESR capacitors increase settling time of ADC

core and results in lower SFDR and SNR performance. V_RMpin may be loaded up to 1mA for setting input

common mode. The remaining pins should not be loaded. Smaller capacitor values might result in degraded

noise performance. Decoupling capacitor on V_REFpin must not exceed 0.1μF, heavier decoupling on this pin will

cause improper calibration during power-up. All reference pins except V_REFhave very low output impedance.

Driving these pins via low output impedance external circuit for long time period might damage the device.

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ADC16V130

1.15V

REF

0.1

0.1 F

Figure 29. Internal References and their Decoupling

While V_RMpin is used to set input common mode level via transformer, a smaller serial resistor could be placed

on the signal path to isolate any switching noise interfering between ADC core and input signal. The serial

resistor introduces voltage error between V_RMand V_CMdue to charge injection while sampling switches toggling.

The serial resistance should not be larger than 50 Ω.

All grounds associated with each reference and analog input pins should be connected to a solid and quite

ground on PC board. Coupling noise from digital outputs and their supplies to the reference pins and their ground

can cause degraded SNR and SFDR performance.

LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining

separate analog and digital areas of the board, with the ADC16V130 between these areas, is required to achieve

specified performance.

Even though LVDS output reduces ground bounding during its transition, the positive and negative signal path

has to be well matched and their trace should be kept as short as possible. It is recommend to place LVDS

repeater between the ADC16V130 and digital data receiver block to isolate coupling noise from receiving block

while the length of the traces are long or the noise level of the receiving block is high.

Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the

clock line as short as possible.

Since digital switching transients are composed largely of high frequency components, total ground plane copper

weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area

is more important than its total ground plane area.

Generally, analog and digital lines should not be crossing each. However whenever it is inevitable, make sure

that these lines are crossing each other at 90° to minimize cross talk. Digital output and output clock signals must

be separated from analog input, references and clock signals unconditionally to ensure the maximum

performance from ADC16V130. Any coupling might result degraded SNR and SFDR performance especially at

high IF applications.

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Be especially careful with the layout of inductors and transformers. Mutual inductance can change the

characteristics of the circuit in which they are used. Inductors and transformers should not be placed side by

side, even with just a small part of their bodies beside each other. For instance, place transformers for the analog

input and the clock input at 90° to one another to avoid magnetic coupling. It is recommended to place the

transformers of input signal path on the top plate, but the transformer of clock signal path on the bottom plate.

Every critical analog signal path like analog inputs and clock inputs must be treated as a transmission line and

should have a solid ground return path with a small loop.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to

the reference pins and ground should be connected to a very clean point in the ground plane. All analog circuitry

(input amplifiers, filters, reference components, etc.) should be placed in the analog area of the board. All digital

circuitry and dynamic I/O lines should be placed in the digital area of the board. The ADC16V130 should be

between these two areas. Furthermore, all components in the reference circuitry and the input signal chain that

are connected to ground should be connected together with short traces and enter the ground plane at a single,

quiet point. All ground connections should have a low inductance path to ground.

Ground return current path can be well managed when supply current path is precisely controlled and ground

layer is continuous and placed next to the supply layer. This is because of the proximity effect. Ground return

current path with a large loop will cause electro-magnetic coupling and results in poor noise performance. Not

that even if there is a large plane for a current path, high frequency current path is not spread evenly over the

large plane, but only takes a path with lowest impedance. Instead of large plane, using thick trace for supplies

makes it easy to control return current path. It is recommended to place supply next to GND layer with thin

dielectric for smaller ground return loop. Proper location and size of decoupling capacitors provide short and

clean return current path.

SUPPLIES AND THEIR SEQUENCE

There are four supplies for the ADC16V130; one 3.0V supply V_A3.0and three 1.8V supplies V_A1.8, V_AD1.8and V_DR

It is recommended to separate V_DRfrom V_A1.8supplies, any coupling from V_DRto rest of supplies and analog

signals could cause lower SFDR and noise performance. When V_A1.8and V_DRare both from same supply source,

coupling noise can be mitigated by adding ferrite-bead on V_DRsupply path.

The user can use different decoupling capacitors to provide current over wide frequency range. The decoupling

capacitors should be located close to the point of entry and close to the supply pins with minimal trace length. A

single ground plane is recommended because separating ground under the ADC16V130 could cause

unexpected long return current path.

V_A3.0supply must turn on before V_A1.8and/or V_DRreaches single diode turn-on voltage level. If this supply

sequence is reversed, excessive amount of current will flow through V_A3.0supply. Ramp rate of V_A3.0supply must

be kept less than 60V/mS (i.e., 60μS for 3.0V supply) in order to prevent excessive surge current through ESD

protection devices.

The exposed pad (Pin #0) on the bottom of the package should be soldered to AGND in order to get optimal

noise performance. The exposed pad is a solid ground for the device and also is heat sinking path.

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REVISION HISTORY

Changes from Revision D (March 2013) to Revision E

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 22

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADC16V130CISQ/NOPB

ADC16V130CISQE/NOPB

ADC16V130CISQX/NOPB

ACTIVE

WQFN

NKD

250

RoHS & Green

Level-3-260C-168 HR

-40 to 85

ADC16V130

2000 RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC16V130CISQ/NOPB WQFN

ADC16V130CISQE/NOPB WQFN

ADC16V130CISQX/NOPB WQFN

NKD

250

178.0

330.0

16.4

9.3

1.3

12.0

16.0

2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC16V130CISQ/NOPB

ADC16V130CISQE/NOPB

ADC16V130CISQX/NOPB

WQFN

NKD

250

208.0

356.0

191.0

356.0

35.0

2000

Pack Materials-Page 2

GENERIC PACKAGE VIEW

NKD 64

9 x 9, 0.5 mm pitch

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4229637/A

www.ti.com

PACKAGE OUTLINE

NKD0064A

WQFN - 0.8 mm max height

WQFN

9.1

8.9

PIN 1 INDEX AREA

0.5

0.3

9.1

8.9

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

0.8 MAX

SEATING PLANE

(0.1)

TYP

7.2 0.1

SEE TERMINAL

DETAIL

60X 0.5

7.5

0.3

64X

PIN 1 ID

0.2

(OPTIONAL)

0.1

C A

0.5

0.3

64X

0.05

4214996/A 08/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

NKD0064A

WQFN - 0.8 mm max height

WQFN

(

7.2)

SYMM

64X (0.6)

64X (0.25)

SEE DETAILS

60X (0.5)

SYMM

(8.8)

(1.36)

TYP

8X (1.31)

(

0.2) VIA

TYP

(1.36) TYP

8X (1.31)

(8.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214996/A 08/2013

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

NKD0064A

WQFN - 0.8 mm max height

WQFN

SYMM

(1.36) TYP

64X (0.6)

64X (0.25)

(1.36)

TYP

60X (0.5)

SYMM

(8.8)

METAL

TYP

25X (1.16)

(8.8)

SOLDERPASTE EXAMPLE

BASED ON 0.125mm THICK STENCIL

EXPOSED PAD

65% PRINTED SOLDER COVERAGE BY AREA

SCALE:10X

4214996/A 08/2013

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADC16V130CISQE/NOPB [TI]

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