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ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

ADC324x 双通道、14 位、25MSPS 至 125MSPS 模数转换器

1 特性

3 说明

1

•

双通道

ADC324x 属于高线性度、超低功耗、双通道、14 位、

25MSPS 至 125MSPS 模数转换器 (ADC) 系列。此类

器件专门设计用于支持具有宽动态范围需求且要求苛刻

的高输入频率信号。当 SYSREF 输入实现整个系统同

步时，时钟输入分频器将给予系统时钟架构设计更高的

灵活性。ADC324x 系列支持串行低压差分信令

14 位分辨率

单电源：1.8V

串行 LVDS 接口 (SLVDS)

支持 1 分频，2 分频和 4 分频的灵活输入时钟缓冲

器

•

f_IN= 70MHz 时，信噪比 (SNR) = 72.4dBFS，无杂

散动态范围 (SFDR) = 87dBc

(LVDS)，从而减少接口线路的数量，实现高系统集成

度。串行 LVDS 接口为双线制，通过两个 LVDS 对串

行输出每个 ADC 数据。内部锁相环 (PLL) 会将传入的

ADC 采样时钟加倍，以获得串行输出各通道的 14 位

输出数据时所使用的位时钟。除了串行数据流之外，数

据帧和位时钟也作为 LVDS 输出进行传送。

超低功耗：

–

125MSPS 时为每通道 116mW

•

通道隔离：105dB

内部抖动和斩波

支持多芯片同步

器件信息⁽¹⁾

与 12 位版本器件引脚到引脚兼容

器件型号

ADC324x

封装

VQFN (48)

封装尺寸（标称值）

封装：超薄四方扁平无引线 (VQFN)-48 (7mm x

7mm)

7.00mm x 7.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

2 应用

空白

•

多载波、多模式蜂窝基站

雷达和智能天线阵列

炮弹制导

电机控制反馈

网络和矢量分析器

通信测试设备

无损检测

微波接收器

软件定义无线电 (SDR)

正交和分集无线电接收器

手持式无线电和仪表

f_S= 125MSPS、f_IN= 10MHz 时的性能

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D101

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS671

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

7.19 Typical Characteristics: Common ......................... 43

7.20 Typical Characteristics: Contour ........................... 44

Parameter Measurement Information ................ 45

8.1 Timing Diagrams..................................................... 45

Detailed Description ............................................ 47

9.1 Overview ................................................................. 47

9.2 Functional Block Diagram ....................................... 47

9.3 Feature Description................................................. 48

9.4 Device Functional Modes........................................ 52

9.5 Programming........................................................... 53

9.6 Register Maps......................................................... 57

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics: ADC3241, ADC3242 ....... 7

7.6 Electrical Characteristics: ADC3243, ADC3244 ....... 7

7.7 Electrical Characteristics: General............................ 8

7.8 AC Performance: ADC3241...................................... 9

7.9 AC Performance: ADC3242.................................... 11

7.10 AC Performance: ADC3243.................................. 13

7.11 AC Performance: ADC3244.................................. 15

7.12 Digital Characteristics ........................................... 17

7.13 Timing Requirements: General ............................. 17

7.14 Timing Requirements: LVDS Output..................... 18

7.15 Typical Characteristics: ADC3241 ........................ 19

7.16 Typical Characteristics: ADC3242 ........................ 25

7.17 Typical Characteristics: ADC3243 ........................ 31

7.18 Typical Characteristics: ADC3244 ........................ 37

8

9

10 Applications and Implementation...................... 69

10.1 Application Information.......................................... 69

10.2 Typical Applications .............................................. 70

11 Power-Supply Recommendations ..................... 72

12 Layout................................................................... 73

12.1 Layout Guidelines ................................................. 73

12.2 Layout Example .................................................... 73

13 器件和文档支持 ..................................................... 74

13.1 相关链接................................................................ 74

13.2 社区资源................................................................ 74

13.3 商标....................................................................... 74

13.4 静电放电警告......................................................... 74

13.5 Glossary................................................................ 74

14 机械、封装和可订购信息....................................... 74

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (March 2015) to Revision C

Page

•

Added Digital Inputs section to Digital Characteristics table ................................................................................................ 17

Changed Wake-up time parameter maximum specifications in Timing Requirements: General table ................................ 17

Updated Figure 19, Figure 20, Figure 23, Figure 24 , Figure 25, and Figure 26................................................................. 22

Updated Figure 50 , Figure 51, Figure 54, Figure 55, Figure 56, and Figure 57................................................................. 28

Updated Figure 81, Figure 82, Figure 85, Figure 86, Figure 87, and Figure 88 . ............................................................... 34

Updated Figure 112, Figure 113, Figure 116, Figure 117, Figure 118, and Figure 119...................................................... 40

Changed Figure 133. ........................................................................................................................................................... 45

Changed SNR and Clock Jitter section: changed typical thermal noise value and changed Figure 141 to reflect

updated thermal noise value ................................................................................................................................................ 49

•

Changed Table 3 .................................................................................................................................................................. 50

Changed Changed Figure 142 ............................................................................................................................................. 51

Added Improving Wake-Up Time From Global Power-Down section .................................................................................. 53

Changed Table 8: changed FLIP BITS to FLIP WIRE in register 4h, changed bit D7 in row 70A, and added register

13 row................................................................................................................................................................................... 57

•

Changed Summary of Special Mode Registers section: changed title, moved section to correct location ......................... 58

Changed register 04h description......................................................................................................................................... 59

Changed register 0Ah and 0Bh descriptions........................................................................................................................ 61

Added register 13h ............................................................................................................................................................... 63

Changed register 70Ah to include DIS CLK FILT bit ........................................................................................................... 68

2

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Changes from Revision A (December 2014) to Revision B

Page

•

已将文档状态由“混合状态”更改为“量产数据”：将 ADC3241 和 ADC3242 发布为量产数据；已对产品预览器件进行了更改 1

Changes from Original (July 2014) to Revision A

Page

•

已将文档状态更改为“混合状态”............................................................................................................................................... 1

更改了产品预览数据表............................................................................................................................................................ 1

3

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

5 Device Comparison Table

RESOLUTION

INTERFACE

(Bits)

25 MSPS

ADC3221

ADC3241

—

50 MSPS

ADC3222

ADC3242

ADC32J22

ADC32J42

80 MSPS

ADC3223

ADC3243

ADC32J23

ADC32J43

125 MSPS

ADC3224

ADC3244

ADC32J24

ADC32J44

160 MSPS

—

12

Serial LVDS

14

—

12

ADC32J25

ADC32J45

JESD204B

14

—

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

48

47

46

45

44

43

42

41

40

39

38

37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

GND

DVDD

GND

DVDD

GND

3

4

DVDD

GND

DVDD

GND

5

GND Pad

6

AVDD

INAP

PDN

(Back Side)

7

AVDD

INBP

INBM

AVDD

8

9

10

11

12

INAM

AVDD

13

14

15

16

17

18

19

20

21

22

23

24

4

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Pin Functions

I/O

DESCRIPTION

NAME

NO.

6-9, 12, 17, 20, 25,

28-30

AVDD

I

Analog 1.8-V power supply

CLKM

CLKP

18

I

Negative differential clock input for the ADC

Positive differential clock input for the ADC

Negative serial LVDS output for channel A0

Positive serial LVDS output for channel A0

Negative serial LVDS output for channel A1

Positive serial LVDS output for channel A1

Negative serial LVDS output for channel B0

Positive serial LVDS output for channel B0

Negative serial LVDS output for channel B1

Positive serial LVDS output for channel B1

Negative bit clock output

19

I

DA0M

DA0P

48

O

I

47

DA1M

DA1P

46

45

DB0M

DB0P

40

39

DB1M

DB1P

38

37

DCLKM

DCLKP

DVDD

FCLKM

FCLKP

44

43

2, 4, 33, 35

42

Positive bit clock output

Digital 1.8-V power supply

O

Negative frame clock output

41

Positive frame clock output

1, 3, 5, 32, 34, 36,

PowerPAD™

GND

I

Ground, 0 V

INAM

INAP

INBM

INBP

11

10

26

27

I

Negative differential analog input for channel A

Positive differential analog input for channel A

Negative differential analog input for channel B

Positive differential analog input for channel B

Power-down control. This pin can be configured via the SPI.

This pin has an internal 150-kΩ pull-down resistor.

PDN

31

I

RESET

SCLK

21

13

14

16

I

Hardware reset; active high. This pin has an internal 150-kΩ pull-down resistor.

Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.

Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.

Serial interface data output

SDATA

SDOUT

I

O

Serial interface enable; active low.

This pin has an internal 150-kΩ pull-up resistor to AVDD.

SEN

15

I

SYSREFM

SYSREFP

VCM

23

22

24

I

Negative external SYSREF input

Positive external SYSREF input

O

Common-mode voltage for analog inputs

5

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

UNIT

V

Analog supply voltage range, AVDD

Digital supply voltage range, DVDD

INAP, INBP, INAM, INBM

2.1

V

min (1.9, AVDD + 0.3)

CLKP, CLKM

Voltage applied to input pins

AVDD + 0.3

V

SYSREFP, SYSREFM

AVDD + 0.3

SCLK, SEN, SDATA, RESET, PDN

Operating free-air, T_A

3.9

85

Temperature

Operating junction, T_J

Storage, T_stg

125

150

ºC

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage range

Digital supply voltage range

1.7

1.8

1.9

V

DVDD

ANALOG INPUT

For input frequencies < 450 MHz

For input frequencies < 600 MHz

2

1

V_ID

Differential input voltage

V_PP

V

V_IC

Input common-mode voltage

VCM ± 0.025

CLOCK INPUT

Input clock frequency

Sampling clock frequency

Sine wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

10

125⁽²⁾

MSPS

V_PP

0.2

1.5

1.6

Input clock amplitude (differential)

0.7

Input clock duty cycle

35%

50%

0.95

65%

Input clock common-mode voltage

V

DIGITAL OUTPUTS

Maximum external load capacitance

from each output pin to GND

C_LOAD

R_LOAD

3.3

pF

Differential load resistance placed

externally

100

Ω

(1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

(2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.

6

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.4 Thermal Information

ADC324x

THERMAL METRIC⁽¹⁾

RGZ (VQFN)

UNIT

48 PINS

25.7

18.9

3.0

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

3

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics: ADC3241, ADC3242

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3241

TYP

ADC3242

TYP

PARAMETER

ADC clock frequency

MIN

MAX

125

71

MIN

MAX

125

81

UNIT

MSPS

mA

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

31

35

118

5

39

43

147

5

65

75

mA

205

17

245

17

mW

Global power-down dissipation

Standby power-down dissipation

mW

78

103

78

103

mW

7.6 Electrical Characteristics: ADC3243, ADC3244

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3243

TYP

ADC3244

TYP

PARAMETER

ADC clock frequency

MIN

MAX

80

MIN

MAX

125

106

95

UNIT

MSPS

mA

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

50

52

183

5

91

65

64

233

5

85

mA

285

17

325

17

mW

Global power-down dissipation

Standby power-down dissipation

mW

72

103

78

103

mW

7

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

7.7 Electrical Characteristics: General

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

Resolution

ANALOG INPUT

14

Bits

Differential input full-scale

Input resistance

2.0

6.6

3.7

0.95

10

V_PP

kΩ

R_IN

Differential at dc

C_IN

Input capacitance

Differential at dc

pF

V_OC(VCM)

VCM common-mode voltage output

VCM output current capability

Input common-mode current

V

mA

Per analog input pin

1.5

µA/MSPS

50-Ω differential source driving 50-Ω

termination across INP and INM

Analog input bandwidth (3 dB)

540

MHz

DC ACCURACY

E_O

Offset error

–25

–2

25

2

mV

°C

Temperature coefficient of offset

error

α_EO

±0.024

Gain error as a result of internal

reference inaccuracy alone

E_G(REF)

%FS

E_G(CHAN)

Gain error of channel alone

–2

%FS

α_(EGCHAN)Temperature coefficient of E_G(CHAN)

±0.008

Δ%FS/°C

CHANNEL-TO-CHANNEL ISOLATION

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 200 MHz

f_IN= 230 MHz

f_IN= 300 MHz

105

Crosstalk⁽¹⁾

dB

(1) Crosstalk is measured with a –1-dBFS input signal on one channel and no input on the other channel.

8

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.8 AC Performance: ADC3241

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3241 (f_S= 25 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

73.3

73.4

72.8

72.4

71.3

70.1

72.2

72.3

71.8

71.5

70.5

69.3

–143.9

73.7

73.2

72.8

71.6

70.4

72.6

72.2

71.9

70.8

69.6

–144.3

–143.8

–143.4

–142.2

–141.0

73.5

72.9

72.4

71.2

69.7

11.9

11.8

11.7

11.5

11.3

87

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

69.7

Signal-to-noise ratio

(from 1-MHz offset)

dBFS

SNR

Signal-to-noise ratio

(full Nyquist band)

dBFS

dBFS/Hz

dBFS

Bits

–144.0 –140.7

–143.4

–143.0

–141.9

–140.7

73.3

73.1

72.8

72.2

71.2

69.7

11.9

11.8

11.7

11.5

11.3

95

Noise spectral density

NSD⁽¹⁾

(averaged across Nyquist zone)

69.1

11.2

84

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

Effective number of bits

94

89

92

86

Spurious-free dynamic range

dBc

85

81

86

83

81

79

(1) Reported from a 1-MHz offset.

9

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

AC Performance: ADC3241 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3241 (f_S= 25 MSPS)

DITHER ON

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

104

100

95

MAX

TYP

96

95

93

87

81

88

92

86

82

83

80

92

85

84

82

81

76

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

84

Second-order harmonic

distortion

HD2

dBc

87

81

95

84

94

92

HD3

Non

Third-order harmonic distortion

dBc

85

87

82

100

101

100

98

87

Spurious-free dynamic range

HD2, HD3 (excluding HD2, HD3)

100

96

94

80.5

92

91

THD

Total harmonic distortion

dBc

86

84

78

f_IN1= 45 MHz,

f_IN2= 50 MHz

–94

–92

–93

–90

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

10

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.9 AC Performance: ADC3242

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3242 (f_S= 50 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

73.3

73

73.7

73.8

73.3

73.1

72.1

71.2

72.9

73.1

72.6

72.4

71.5

70.6

–147.5

–147.6

–147.1

–146.9

–145.9

–145

73.6

73.2

72.9

71.7

70.6

11.9

11.8

11.6

11.4

95

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.5

Signal-to-noise ratio

(from 1-MHz offset)

72.6

71.7

70.9

72.5

72.6

72.3

71.9

71.1

70.3

–147.1

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–147.1 –144.5

–146.8

–146.4

–145.5

–144.7

73.2

73.4

72.9

72.5

71.5

70.5

11.9

11.8

11.7

11.6

11.4

89

Noise spectral density

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

(averaged across Nyquist zone)

69.6

11.3

83

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

Effective number of bits

93

91

94

93

Spurious-free dynamic range

dBc

88

86

85

82

80

(1) Reported from a 1-MHz offset.

11

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AC Performance: ADC3242 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3242 (f_S= 50 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

103

99

96

94

88

82

89

93

94

88

85

82

99

101

100

99

97

88

92

89

83

79

MAX

TYP

97

95

94

92

89

83

97

95

93

86

82

80

96

93

94

93

90

87

88

86

81

78

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

83

87

79

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

dBc

Spurious-free dynamic range

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–95

–92

–95

–89

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

12

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7.10 AC Performance: ADC3243

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3243 (f_S= 80 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

73.1

72.9

72.7

72

73.5

73.3

73

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.7

Signal-to-noise ratio

(from 1-MHz offset)

72.4

71.7

72.8

72.6

72.3

71.7

71.2

–149.4

–149.2

–148.9

–148.3

–147.6

73.4

73.2

72.9

72.2

71.3

11.9

11.8

11.7

11.6

94

71.4

72.4

72.3

72.1

71.4

70.9

–149.0

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–148.8 –146.7

–148.6

–147.9

–147.3

73.1

Noise spectral density

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

(averaged across Nyquist zone)

69.6

11.3

82

72.9

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

72.7

71.9

71.2

11.8

Effective number of bits

11.8

11.6

11.5

89

93

Spurious-free dynamic range

93

91

dBc

87

85

83

(1) Reported from a 1-MHz offset.

13

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AC Performance: ADC3243 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC3243 (f_S= 80 MSPS)

DITHER ON

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

102

95

MAX

TYP

98

93

87

85

95

94

96

90

84

95

94

91

89

88

84

81

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

82

83

86

76

Second-order harmonic

distortion

HD2

95

dBc

87

85

89

94

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

95

dBc

92

89

93

100

99

HD2, HD3 (excluding HD2, HD3)

98

88

91

THD

Total harmonic distortion

91

dBc

85

83

f_IN1= 45 MHz,

f_IN2= 50 MHz

–93

–91

–92

–89

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

14

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7.11 AC Performance: ADC3244

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC3244 (f_S= 125 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

72.9

72.6

72.4

71.7

71

73.3

73

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

71

Signal-to-noise ratio

(from 1-MHz offset)

72.8

72.2

71.6

72.9

72.6

72.5

71.9

71.3

–151.1

–150.9

–150.7

–150.1

–149.5

73

SNR

dBFS

72.5

72.2

72.1

71.4

70.7

–150.8

Signal-to-noise ratio

(full Nyquist band)

–150.5 –148.9

–150.3

–149.6

–148.9

72.8

Noise spectral density

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

(averaged across Nyquist zone)

69.6

11.3

82

72.6

72.9

72.5

71.9

71.1

11.8

11.6

11.5

86

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

72.3

71.5

70.7

11.8

Effective number of bits

11.7

11.6

11.5

93

94

89

Spurious-free dynamic range

89

85

dBc

85

83

82

(1) Reported from a 1-MHz offset.

15

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AC Performance: ADC3244 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC3244 (f_S= 125 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

95

96

91

85

83

94

91

97

87

100

99

100

96

91

87

84

81

MAX

TYP

96

95

90

85

83

86

89

85

89

85

95

91

92

85

86

83

82

80

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

82

83

86

76

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

dBc

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–97

–91

–95

–90

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

16

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7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)

All digital inputs support 1.8-V and

3.3-V CMOS logic levels

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

V

All digital inputs support 1.8-V and

3.3-V CMOS logic levels

0.4

RESET, SDATA, SCLK,

PDN

SEN⁽¹⁾

V_HIGH= 1.8 V

V_LOW= 0 V

10

0

High-level input

current

I_IH

µA

RESET, SDATA, SCLK,

PDN

0

Low-level input

current

I_IL

SEN

V_LOW= 0 V

10

DIGITAL INPUTS (SYSREFP, SYSREFM)

V_IH

V_IL

High-level input voltage

1.3

0.5

0.9

V

Low-level input voltage

Common-mode voltage for SYSREF

DIGITAL OUTPUTS, CMOS INTERFACE (SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

DVDD – 0.1

DVDD

0

V

0.1

DIGITAL OUTPUTS, LVDS INTERFACE

V_ODH

V_ODL

V_OCM

High-level output differential voltage

Low-level output differential voltage

Output common-mode voltage

With an external 100-Ω termination

280

410

–410

1.05

460

mV

V

–460

–280

(1) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up resistor is weak, SEN can also be driven by 1.8-V or 3.3-V

CMOS buffers.

7.13 Timing Requirements: General

Typical values are at T_A= 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum

and maximum values are across the full temperature range: T_MIN= –40°C to T_MAX= 85°C.

MIN

TYP

1.44

±70

±150

130

35

MAX

UNIT

t_A

Aperture delay

1.24

1.64

ns

Aperture delay matching between two channels of the same device

Variation of aperture delay between two devices at the same temperature and supply voltage

Aperture jitter

ps

t_J

f_Srms

Time to valid data after exiting standby power-down mode

65

Wake-up time

µs

Time to valid data after exiting global power-down mode

(in this mode, both channels power down)

85

140

2-wire mode (default)

9

8

Clock

cycles

ADC latency⁽¹⁾

1-wire mode

t_{SU_SYSREF}

t_{H_SYSREF}

Setup time for SYSREF referenced to input clock rising edge

SYSREF reference time

1000

100

ps

Hold time for SYSREF referenced to input clock rising edge

(1) Overall latency = ADC latency + t_PDI

.

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7.14 Timing Requirements: LVDS Output

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 7x serialization, C_LOAD= 3.3 pF⁽¹⁾, and

R_LOAD= 100 Ω⁽²⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN= –40°C

to T_MAX= 85°C.⁽³⁾⁽⁴⁾

MIN

TYP

MAX

UNIT

Data setup time: data valid to zero-crossing of differential output clock

(CLKOUTP – CLKOUTM)⁽⁵⁾

t_SU

t_HO

0.36

0.42

ns

Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data

becoming invalid⁽⁵⁾

0.36

0.47

ns

LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM)

49%

4.5

Clock propagation delay: input clock falling edge cross-over to frame 1-wire mode

clock rising edge cross-over 10 MSPS < sampling frequency <

2.7

6.5

t_PDI

ns

2-wire mode

125 MSPS

0.44 × t_S+ t_DELAY

t_DELAY

Delay time

3

4.5

5.9

ns

t_FALL

t_RISE

,

Data fall time, data rise time: rise time measured from –100 mV to 100 mV,

10 MSPS ≤ Sampling frequency ≤ 125 MSPS

0.11

t_CLKRISE

t_CLKFALL

,

Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,

10 MSPS ≤ Sampling frequency ≤ 125 MSPS

0.11

ns

(1) C_LOADis the effective external single-ended load capacitance between each output pin and ground

(2) R_LOADis the differential load resistance between the LVDS output pair.

(3) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time

specifications take into account the effect of jitter on the output data and clock.

(4) Timing parameters are ensured by design and characterization and are not tested in production.

(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode)

SETUP TIME

(t_SU, ns)

HOLD TIME

(t_HO, ns)

SAMPLING FREQUENCY

(MSPS)

MIN

2.27

1.44

1.2

TYP

MAX

MIN

2.41

1.51

1.24

0.97

0.72

0.53

TYP

MAX

25

40

2.6

1.6

2.6

1.7

50

1.32

1.04

0.75

0.57

1.4

60

0.95

0.68

0.5

1.09

0.81

0.62

80

100

Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode)

SETUP TIME

(t_SU, ns)

HOLD TIME

(t_HO, ns)

SAMPLING FREQUENCY

(MSPS)

MIN

1.1

TYP

MAX

MIN

1.19

0.74

0.54

0.42

0.3

TYP

MAX

25

40

50

60

80

1.24

0.72

0.55

0.41

0.24

1.34

0.82

0.64

0.51

0.38

0.66

0.48

0.35

0.17

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7.15 Typical Characteristics: ADC3241

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D701

D702

SFDR = 97.9 dBc, SNR = 73.8 dBFS, SINAD = 73.8 dBFS,

THD = 96.8 dBc, HD2 = –110.0 dBc, HD3 = –97.9 dBc

SFDR = 89.8 dBc, SNR = 74.5 dBFS, SINAD = 74.3 dBFS,

THD = 88.3 dBc, HD2 = –89.8 dBc, HD3 = –100.3 dBc

Figure 1. FFT for 10-MHz Input Signal (Dither On)

Figure 2. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D703

D704

SFDR = 91.8 dBc, SNR = 73.4 dBFS, SINAD = 73.4 dBFS,

THD = 91.4 dBc, HD2 = –108.2 dBc, HD3 = –91.8 dBc

SFDR = 90.2 dBc, SNR = 74.1 dBFS, SINAD = 73.9 dBFS,

THD = 88.7 dBc, HD2 = –90.2 dBc, HD3 = –100.5 dBc

Figure 3. FFT for 70-MHz Input Signal (Dither On)

Figure 4. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D705

D706

SFDR = 86.6 dBc, SNR = 72.1 dBFS, SINAD = 71.9 dBFS,

THD = 84.7 dBc, HD2 = –89.8 dBc, HD3 = –86.6 dBc

SFDR = 87.7 dBc, SNR = 72.5 dBFS, SINAD = 72.3 dBFS,

THD = 85 dBc, HD2 = –87.7 dBc, HD3 = –91.2 dBc

Figure 5. FFT for 170-MHz Input Signal (Dither On)

Figure 6. FFT for 170-MHz Input Signal (Dither Off)

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Typical Characteristics: ADC3241 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D707

D708

SFDR = 75.6 dBc, SNR = 69.8 dBFS, SINAD = 68.8 dBFS,

THD = 74.8 dBc, HD2 = –75.6 dBc, HD3 = –82.5 dBc

SFDR = 75.3 dBc, SNR = 70.0 dBFS, SINAD = 68.8 dBFS,

THD = 73.8 dBc, HD2 = –75.3 dBc, HD3 = –79.6 dBc

Figure 7. FFT for 270-MHz Input Signal (Dither On)

Figure 8. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D709

D710

SFDR = 68.4 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS,

THD = 92.6 dBc, HD2 = –68.4 dBc, HD3 = –89.5 dBc

SFDR = 67.9 dBc, SNR = 67.2 dBFS, SINAD = 67.2 dBFS,

THD = 87.6 dBc, HD2 = –67.9 dBc, HD3 = –96.9 dBc

Figure 9. FFT for 450-MHz Input Signal (Dither On)

Figure 10. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D711

D712

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 82.4 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 90 dBFS,

each tone at –36 dBFS

Figure 11. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 12. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

20

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3241 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D713

D714

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 78 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 89 dBFS,

each tone at –36 dBFS

Figure 13. FFT for Two-Tone Input Signal

Figure 14. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

(–36 dBFS at 185 MHz and 190 MHz)

-90

-80

-85

-90

-95

-100

-105

-110

-115

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D715

D716

Figure 15. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 16. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

75

104

Dither_EN

Dither_DIS

74

73

72

71

70

69

68

67

96

88

80

72

64

56

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D717

D718

Figure 17. Signal-to-Noise Ratio vs Input Frequency

Figure 18. Spurious-Free Dynamic Range vs

Input Frequency

21

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3241 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

75

74.5

74

180

160

140

120

100

80

75.5

74.5

73.5

72.5

71.5

70.5

69.5

68.5

280

240

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

73.5

73

72.5

72

60

40

71.5

71

40

20

0

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D719

D720

.

Figure 19. Performance vs Input Amplitude (30 MHz)

Figure 20. Performance vs Input Amplitude (170 MHz)

80

78

76

74

72

70

97.5

SNR

SFDR

78

76

74

72

70

68

87.5

SNR

SFDR

95

85

92.5

90

82.5

80

87.5

77.5

85

75

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D721

D722

Figure 21. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 22. Performance vs Input Common-Mode Voltage

(170 MHz)

106

74

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

104

102

100

98

73.7

73.4

73.1

72.8

72.5

96

94

92

90

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D723

D724

Figure 23. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (30 MHz)

Figure 24. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (30 MHz)

22

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3241 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

98

97

96

95

94

93

74.5

74.1

73.7

73.3

72.9

72.5

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D725

D726

Figure 25. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (30 MHz)

Figure 26. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (30 MHz)

78

92.5

75.4

112

SNR

SFDR

SNR

SFDR

76

74

72

70

68

66

64

62

60

90

74.6

73.8

73

104

96

88

80

72

64

56

48

87.5

85

82.5

80

72.2

71.4

70.6

69.8

69

77.5

75

72.5

70

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D727

D728

Figure 27. Performance vs Clock Amplitude (40 MHz)

Figure 28. Performance vs Clock Amplitude (150 MHz)

74

99

74

73.2

72.4

71.6

70.8

70

90

88

86

84

82

80

SNR

SFDR

SNR

SFDR

73.8

73.6

73.4

73.2

73

97.5

96

94.5

93

91.5

72.8

90

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D729

D730

Figure 29. Performance vs Clock Duty Cycle (30 MHz)

Figure 30. Performance vs Clock Duty Cycle (150 MHz)

23

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3241 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

15

12.5

10

7.5

5

2.5

0

D731

Output Code (LSB)

RMS Noise = 1.33 LSBs

Figure 31. Idle Channel Histogram

24

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.16 Typical Characteristics: ADC3242

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D501

D502

SFDR = 88.9 dBc, SFDR = 99.8 dBc (non 23), SNR = 73.6 dBFS,

SINAD = 73.5 dBFS, THD = 88.8 dBc, HD2 = –111.4 dBc,

HD3 = –88.9 dBc

SFDR = 84.7 dBc, SFDR = 96.1 dBc (non 23), SNR = 74.1 dBFS,

SINAD = 73.8 dBFS, THD = 83.5 dBc, HD2 = –92.2 dBc,

HD3 = –84.7 dBc

Figure 32. FFT for 10-MHz Input Signal (Dither On)

Figure 33. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D503

D504

SFDR = 85.8 dBc, SFDR = 100.3 dBc (non 23),

SNR = 72.4 dBFS, SINAD = 72.2 dBFS, THD = 84.8 dBc,

HD2 = –92.3 dBc, HD3 = –85.8 dBc

SFDR = 90.4 dBc, SFDR = 94.7 dBc (non 23), SNR = 73.9 dBFS,

SINAD = 73.7 dBFS, THD = 87.5 dBc, HD2 = –91.9 dBc,

HD3 = –90.4 dBc

Figure 35. FFT for 70-MHz Input Signal (Dither Off)

Figure 34. FFT for 70-MHz Input Signal (Dither On)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D505

D506

SFDR = 85.8 dBc, SFDR = 99.1 dBc (non 23), SNR = 72.4 dBFS,

SINAD = 72.2 dBFS, THD = 84.8 dBc, HD2 = –92.3 dBc,

HD3 = –85.8 dBc

SFDR = 89.7 dBc, SFDR = 93 dBc (non 23), SNR = 72.9 dBFS,

SINAD = 72.8 dBFS, THD = 86.6 dBc, HD2 = –89.7 dBc,

HD3 = –107.7 dBc

Figure 36. FFT for 170-MHz Input Signal (Dither On)

Figure 37. FFT for 170-MHz Input Signal (Dither Off)

25

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3242 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D507

D508

SFDR = 74.7 dBc, SFDR = 95.2 dBc (non 23), SNR = 70.7 dBFS,

SINAD = 69.3 dBFS, THD = 73.8 dBc, HD2 = –74.7 dBc,

HD3 = –81.1 dBc

SFDR = 74.6 dBc, SFDR = 91.1 dBc (non 23), SNR = 70.9 dBFS,

SINAD = 69.2 dBFS, THD = 72.9 dBc, HD2 = –74.6 dBc,

HD3 = –78.0 dBc

Figure 38. FFT for 270-MHz Input Signal (Dither On)

Figure 39. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D509

D510

SFDR = 68.2 dBc, SNR = 69.0 dBFS, SINAD = 69.0 dBFS,

THD = –85.7 dBc, HD2 = –68.2 dBc, HD3 = –86.5 dBc

SFDR = 68.2 dBc, SNR = 69.2 dBFS, SINAD = 69.2 dBFS,

THD = –86.4 dBc, HD2 = 68.2 dBc, HD3 = –90.3 dBc

Figure 40. FFT for 450-MHz Input Signal (Dither On)

Figure 41. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D511

D5112

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 87 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 88 dBFS,

each tone at –36 dBFS

Figure 42. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 43. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

26

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3242 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D513

D514

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 83 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 85 dBFS,

each tone at –36 dBFS

Figure 44. FFT for Two-Tone Input Signal

Figure 45. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

(–36 dBFS at 185 MHz and 190 MHz)

-85

-80

-85

-90

-95

-90

-95

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D515

D516

Figure 46. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 47. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

74.5

104

Dither_EN

Dither_DIS

73.5

96

72.5

71.5

70.5

69.5

68.5

88

80

72

64

56

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D517

D518

Figure 48. Signal-to-Noise Ratio vs Input Frequency

Figure 49. Spurious-Free Dynamic Range vs

Input Frequency

27

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3242 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

74.5

180

160

140

120

100

80

75.5

74.5

73.5

72.5

71.5

70.5

69.5

68.5

280

240

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

72.5

72

71.5

71

60

40

70.5

20

0

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D519

D520

Figure 50. Performance vs Input Amplitude (30 MHz)

Figure 51. Performance vs Input Amplitude (170 MHz)

80

78

76

74

72

70

95

SNR

SFDR

78

76

74

72

70

68

90

SNR

SFDR

92.5

90

87.5

85

87.5

85

82.5

80

82.5

77.5

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D521

D522

Figure 52. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 53. Performance vs Input Common-Mode Voltage

(170 MHz)

96

74

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

94

92

90

88

86

84

82

80

73.7

73.4

73.1

72.8

72.5

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D523

D524

Figure 54. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (30 MHz)

Figure 55. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (30 MHz)

28

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3242 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

92

91

90

89

88

87

86

85

74.5

74.1

73.7

73.3

72.9

72.5

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D525

D526

Figure 56. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (30 MHz)

Figure 57. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (30 MHz)

78

90

76

96

SNR

SFDR

75

74

73

72

71

70

69

94

75

72

69

66

63

60

87

84

81

78

75

72

92

90

88

86

84

82

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D528

Figure 58. Performance vs Clock Amplitude (40 MHz)

Figure 59. Performance vs Clock Amplitude (150 MHz)

74.2

94.5

72.4

90

88

86

84

82

80

SNR

SFDR

SNR

SFDR

73.8

73.4

73

93

72.2

72

91.5

90

71.8

71.6

71.4

72.6

88.5

72.2

87

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D529

D530

Figure 60. Performance vs Clock Duty Cycle (30 MHz)

Figure 61. Performance vs Clock Duty Cycle (150 MHz)

29

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3242 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

20

16

12

8

4

0

D531

Output Code (LSB)

RMS Noise = 1.3 LSBs

Figure 62. Idle Channel Histogram

30

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.17 Typical Characteristics: ADC3243

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D301

D302

SFDR = 88.9 dBc, SNR = 73.4 dBFS, SINAD = 73.3 dBFS,

THD = 88.8 dBc, HD2 = –109.9 dBc, HD3 = –88.9 dBc

SFDR = 84.2 dBc, SNR = 73.8 dBFS, SINAD = 73.4 dBFS,

THD = 83.2 dBc, HD2 = –93.6 dBc, HD3 = –84.2 dBc

Figure 63. FFT for 10-MHz Input Signal (Dither On)

Figure 64. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D303

D304

SFDR = 91.3 dBc, SNR = 73.2 dBFS, SINAD = 73.1 dBFS,

THD = 91 dBc, HD2 = –109.5 dBc, HD3 = –91.3 dBc

SFDR = 85.4 dBc, SNR = 73.6 dBFS, SINAD = 73.3 dBFS,

THD = 83.7 dBc, HD2 = –91.2 dBc, HD3 = –85.4 dBc

Figure 65. FFT for 70-MHz Input Signal (Dither On)

Figure 66. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D305

D306

SFDR = 94.9 dBc, SNR = 72.4 dBFS, SINAD = 72.4 dBFS,

THD = 93.2 dBc, HD2 = –106.1 dBc, HD3 = –94.9 dBc

SFDR = 92.3 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,

THD = 88 dBc, HD2 = –92.3 dBc, HD3 = –95.4 dBc

Figure 67. FFT for 170-MHz Input Signal (Dither On)

Figure 68. FFT for 170-MHz Input Signal (Dither Off)

31

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3243 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D307

D308

SFDR = 75.4 dBc, SNR = 70.9 dBFS, SINAD = 69.6 dBFS,

THD = 74.3 dBc, HD2 = –75.4 dBc, HD3 = –81.0 dBc

SFDR = 75.4 dBc, SNR = 71.2 dBFS, SINAD = 69.8 dBFS,

THD = 74.2 dBc, HD2 =–75.4 dBc, HD3 = –81.2 dBc

Figure 69. FFT for 270-MHz Input Signal (Dither On)

Figure 70. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D309

D310

SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS,

THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc

SFDR = 77.8 dBc, SNR = 68.8 dBFS, SINAD = 68.3 dBFS,

THD = 77.5 dBc, HD2 = –77.8 dBc, HD3 = –91.8 dBc

Figure 71. FFT for 450-MHz Input Signal (Dither On)

Figure 72. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D311

D312

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 87 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 92.8 dBFS,

each tone at –36 dBFS

Figure 73. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 74. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

32

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3243 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D313

D314

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 78.8 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 91 dBFS,

each tone at –36 dBFS

Figure 75. FFT FOR Two-Tone Input Signal

Figure 76. FFT FOR Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

(–7 dBFS at 185 MHz and 190 MHz)

-85

-80

-85

-90

-95

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D315

D316

Figure 77. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 78. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

74.5

100

Dither_EN

Dither_DIS

73.5

95

72.5

71.5

70.5

69.5

68.5

90

85

80

75

70

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D317

D318

Figure 79. Signal-to-Noise Ratio vs Input Frequency

Figure 80. Spurious-Free Dynamic Range vs

Input Frequency

33

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3243 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

74.5

180

160

140

120

100

80

74.5

180

160

140

120

100

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

73.5

73

72.5

72

72.5

72

71.5

71

60

71.5

71

60

40

70.5

20

70.5

20

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D319

D320

Figure 81. Performance vs Input Amplitude (30 MHz)

Figure 82. Performance vs Input Amplitude (170 MHz)

78

92

90

88

86

84

82

78

92

90

88

86

84

82

SNR

SFDR

SNR

SFDR

76

74

72

70

68

76

74

72

70

68

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D321

D322

Figure 83. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 84. Performance vs Input Common-Mode Voltage

(170 MHz)

95

74

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

73.5

73

93

91

89

87

85

72.5

72

71.5

71

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D323

D324

Figure 85. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (170 MHz)

Figure 86. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (170 MHz)

34

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3243 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

95

93

91

89

87

85

74

73.5

73

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

72.5

72

71.5

71

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D325

D326

Figure 87. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (170 MHz)

Figure 88. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (170 MHz)

74.5

104

80

94

SNR

SFDR

78

76

74

72

70

68

66

64

92

74

73.5

73

102

100

98

90

88

86

84

82

80

78

72.5

72

96

94

71.5

92

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D327

D328

Figure 89. Performance vs Clock Amplitude (40 MHz)

Figure 90. Performance vs Clock Amplitude (150 MHz)

74.2

90

89

88

87

86

85

72.8

92

90

88

86

84

82

SNR

SFDR

SNR

SFDR

73.8

73.4

73

72.6

72.4

72.2

72

72.6

72.2

71.8

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D329

D330

Figure 91. Performance vs Clock Duty cycle (30 MHz)

Figure 92. Performance vs Clock Duty Cycle (150 MHz)

35

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3243 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

24

22

20

18

16

14

12

10

8

6

4

2

0

D331

Output Code (LSB)

RMS Noise = 1.28 LSBs

Figure 93. Idle Channel Histogram

36

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

7.18 Typical Characteristics: ADC3244

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D101

D102

SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,

THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc

SFDR = 91.8 dBc, SNR = 73.5 dBFS, SINAD = 73.4 dBFS,

THD = 87.3 dBc, HD2 = –93.8 dBc, HD3 = –91.8 dBc

Figure 94. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

Figure 95. FFT for 10-MHz Input Signal

(Chopper On, Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D103

D104

SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,

THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc

SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,

THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc

Figure 96. FFT for 70-MHz Input Signal (Dither On)

Figure 97. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D105

D106

SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,

THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc

SFDR = 89.9 dBc, SNR = 72.8 dBFS, SINAD = 72.6 dBFS,

THD = 87.1 dBc, HD2 = –97.2 dBc, HD3 = –89.9 dBc

Figure 98. FFT for 170-MHz Input Signal (Dither On)

Figure 99. FFT for 170-MHz Input Signal (Dither Off)

37

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3244 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D107

D108

SFDR = 76.1 dBc, SNR = 70.8 dBFS, SINAD = 69.8 dBFS,

THD = 74.8 dBc, HD2 = –76.1 dBc, HD3 = –80.9 dBc

SFDR = 76.1 dBc, SNR = 71.2 dBFS, SINAD = 70.2 dBFS,

THD = 74.9 dBc, HD2 = –76.1 dBc, HD3 = –81.6 dBc

Figure 100. FFT for 270-MHz Input Signal (Dither On)

Figure 101. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D109

D110

SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,

THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc

SFDR = 75.3 dBc, SNR = 69.1 dBFS, SINAD = 67.8 dBFS,

THD = 72.7 dBc, HD2 = –76.7 dBc, HD3 = –75.3 dBc

Figure 102. FFT for 450-MHz Input Signal (Dither On)

Figure 103. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D111

D112

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 88.3 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 90.8 dBFS,

each tone at –36 dBFS

Figure 104. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 105. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

38

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3244 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D113

D114

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 86.4 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 87.28 dBFS,

each tone at –36 dBFS

Figure 106. FFT for Two-Tone Input Signal

Figure 107. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

(–36 dBFS at 185 MHz and 190 MHz)

-85

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D115

D116

Figure 108. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 109. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

74

100

Dither_EN

Dither_DIS

73

95

72

71

70

69

68

90

85

80

75

70

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D117

D118

Figure 110. Signal-to-Noise Ratio vs Input Frequency

Figure 111. Spurious-Free Dynamic Range vs

Input Frequency

39

ADC3241, ADC3242, ADC3243, ADC3244

ZHCSD67C –JULY 2014–REVISED MARCH 2016

www.ti.com.cn

Typical Characteristics: ADC3244 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

74.5

180

160

140

120

100

80

74

73.5

73

180

160

140

120

100

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

72.5

72

72.5

72

71.5

71

71.5

71

60

40

70.5

70

40

70.5

20

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D119

D120

Figure 112. Performance vs Input Amplitude (30 MHz)

Figure 113. Performance vs Input Amplitude (170 MHz)

78

96

94

92

90

88

86

78

76

74

72

70

68

92

90

88

86

84

82

SNR

SFDR

SNR

SFDR

76

74

72

70

68

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D121

Figure 115. Performance vs Input Common-Mode Voltage

(170 MHz)

Figure 114. Performance vs Input Common-Mode Voltage

(30 MHz)

92

73

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

72.5

72

90

88

86

84

82

71.5

71

70.5

70

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D123

D124

Figure 116. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (170 MHz)

Figure 117. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (170 MHz)

40

ADC3241, ADC3242, ADC3243, ADC3244

www.ti.com.cn

ZHCSD67C –JULY 2014–REVISED MARCH 2016

Typical Characteristics: ADC3244 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

92

90

88

86

84

82

73

72.6

72.2

71.8

71.4

71

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D125

D126

Figure 118. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (170 MHz)

Figure 119. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (170 MHz)

74.5

94

77

95

SNR

SFDR

74

73.5

73

93

92

91

90

89

75

73

71

69

67

65

90

85

80

75

70

72.5

72

71.5

88

65

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D127

D128

Figure 120. Performance vs Clock Amplitude (40 MHz)

Figure 121. Performance vs Clock Amplitude (150 MHz)

74.2

95

94

93

92

91

90

72.4

90

SNR

SFDR

SNR

SFDR

73.8

73.4

73

72.2

72

87.5

85

71.8

71.6

71.4

82.5

80

72.6

72.2

77.5

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D129

D130

Figure 122. Performance vs Clock Duty Cycle (30 MHz)

Figure 123. Performance vs Clock Duty Cycle (150 MHz)

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Typical Characteristics: ADC3244 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

20

16

12

8

4

0

D131

Output Code (LSB)

RMS Noise = 1.4 LSBs

Figure 124. Idle Channel Histogram

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7.19 Typical Characteristics: Common

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when chopper is enabled, unless otherwise noted.

0

-10

0

-5

-20

-10

-15

-20

-25

-30

-35

-40

-45

-50

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12ꢀ5

25

37ꢀ5

50

62ꢀ5

0

50

100

150

200

250

300

Crequency (aIz)

Frequency of Signal on Supply (MHz)

D001

D0012

f_IN= 30 MHz, A_IN= –1 dBFS,

test signal amplitude = 50 mV_PP

f_IN= 30.1 MHz, f_PSRR= 3 MHz, A_PSRR= 50 mV_PP

SNR = 58.51 dBFS, SINAD = 58.51 dBFS, SFDR = 60.53 dBc,

THD = –90.71 dBc, SFDR = 60.53 dBc (non 23)

,

Figure 126. Power-Supply Rejection Ratio Spectrum

Figure 125. Power-Supply Rejection Ratio vs

Test Signal Frequency

0

-10

0

-5

-20

-10

-15

-20

-25

-30

-35

-40

-45

-50

-55

-60

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12ꢀ5

25

37ꢀ5

50

62ꢀ5

0

50

100

150

200

250

300

Crequency (aIz)

Frequency of Input Common-Mode Signal (MHz)

D003

D004

f_IN= 30 MHz, A_IN= –1 dBFS,

test signal amplitude = 50 mV_PP

f_IN= 170.1 MHz, f_CMRR= 5 MHz, A_CMRR= 50 mV_PP

SNR = 69.72 dBFS, SINAD = 69.66 dBFS, SFDR = 75.66 dBc,

THD = –86.98 dBc, SFDR = 75.66 dBc (non 23)

,

Figure 128. Common-Mode Rejection Ratio Spectrum

Figure 127. Common-Mode Rejection Ratio vs

Test Signal Frequency

240

Analog Power

Digital Power

Total Power

200

160

120

80

40

5

15 25 35 45 55 65 75 85 95 105 115 125

Sampling Speed (MSPS)

Figure 129. Power vs Sampling Frequency

(One-Wire Mode)

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7.20 Typical Characteristics: Contour

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc

when chopper is disabled and from f_S/ 2 when is chopper enabled, unless otherwise noted.

80

85

120

110

100

90

80

90

75

90

85

80

75

80

70

60

90

50

85

40

70

75

90

80

30

50

100

150

200

250

300

350

400

450

90

Input Frequency, MHz

70

75

80

85

Figure 130. Spurious-Free Dynamic Range (SFDR)

120

110

100

90

72.5

73

72

71.5

71

70.5

69.5

69

70

80

72.5

73

71.5

70

72

71

70.5

69.5

69

70

60

50

40

68.5

72.5

70.5

71.5

70

71

73

72

69.5

69

30

68

67.5

50

100

150

200

250

300

350

400

450

73

Input Frequency, MHz

70

67

68

69

71

72

Figure 131. Signal-to-Noise Ratio (SNR)

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8 Parameter Measurement Information

8.1 Timing Diagrams

DAn_P

DBn_P

Logic 0

_ODL= -410 mV⁽¹⁾

Logic 1

V_ODH= +410 mV⁽¹⁾

V

DAn_M

DBn_M

V_OCM

GND

(1) With an external 100-Ω termination.

Figure 132. Serial LVDS Output Voltage Levels

CLKIN

FCLK

DCLK

1-Wire (14x Serialization)

Dx0P

Dx0M

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

D

13

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

10 11 12 13

CLKIN

FCLK

DCLK

Dx0P

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

2-Wire (7x Serialization)

Dx0M

Dx1P

Dx1M

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

SAMPLE N-1

SAMPLE N

SAMPLE N+1

Figure 133. Output Timing Diagram

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Timing Diagrams (continued)

DCLK

t _HO

Dx0P

Dx0M

t _SU

Figure 134. Setup and Hold Time

N+10

N+1

N+9

Sample N

T_A

Input Signal

on INxP, INxM pins

Data Latency⁽¹⁾= 9 Input Clock Cycles

Sample N

CLKINP,

CLKINM

t_PDI

FCLKP,

FCLKM

DCLKP,

DCLKM

DCLK edges are centered within the data valid

window.

DA0P, DA0M,

DB0P, DB0M

5

6

0

7

1

8

2

9

3

4

5

6

0

7

1

8

2

9

3

4

12 13

10 11 12 13

Sample N

10 11

DA1P, DA1M,

DB1P, DB1M

Sample N+1

t_h

t_su

(1) Overall latency = data latency + t_PDI

.

Figure 135. Latency Diagram

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9 Detailed Description

9.1 Overview

The ADC324x are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-

digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency

signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock

architecture design while the SYSREF input enables complete system synchronization. The ADC324x family

supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high system

integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over

two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the

bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams,

the frame and bit clocks are also transmitted as LVDS outputs.

9.2 Functional Block Diagram

DA0P

DA0M

Digital Encoder

and Serializer

INAP

INAM

14-Bit

ADC

DA1P

DA1M

CLKP

CLKM

Divide by

1,2,4

DCLKP

DCLKM

Bit Clock

PLL

Frame Clock

FCLKP

FCLKM

SYSREFP

SYSREFM

DB0P

DB0M

INBP

INBM

14-Bit

ADC

Digital Encoder

and Serializer

DB1P

DB1M

Common

Mode

VCM

Configuration Registers

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9.3 Feature Description

9.3.1 Analog Inputs

The ADC324x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing

symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP(default) differential input swing.

The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω

termination between INP and INM).

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC324x can be driven by the transformer-

coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in

Figure 136, Figure 137, and Figure 138. See Figure 139 for details regarding the internal clock buffer.

0.1 mF

Z_o

CLKP

Differential

Sine-Wave

Clock Input

R_T

Typical LVDS

Clock Input

100 W

0.1 mF

CLKM

Device

0.1 mF

Z_o

CLKM

NOTE: R_T= termination resistor, if necessary.

Device

Figure 136. Differential Sine-Wave Clock Driving

Circuit

Figure 137. LVDS Clock Driving Circuit

0.1 mF

Z_o

CLKP

150 W

Typical LVPECL

Clock Input

100 W

0.1 mF

Z_o

CLKM

Device

150 W

Figure 138. LVPECL Clock Driving Circuit

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Clock Buffer

L_PKG

2 nH

20 W

CLKP

C_BOND

1 pF

C_EQ

5 kW

R_ESR

100 W

1.4 V

L_PKG

2 nH

5 kW

20 W

CLKM

C_BOND

1 pF

R_ESR

100 W

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 139. Internal Clock Buffer

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF

capacitor, as shown in Figure 140. However, for best performance the clock inputs must be driven differentially,

thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using

a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.

There is no change in performance with a non-50% duty cycle clock input.

0.1 mF

CMOS

Clock Input

CLKP

0.1 mF

CLKM

Device

Figure 140. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization

noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter

sets SNR for higher input frequencies.

2

SNR_Quantizatoin

SNR

Jitter

Noise

≈

’

÷

Thermal Noise

≈

’

÷

≈

’

÷

-

∆

20

∆

SNR_ADC[dBc] = -20∂log 10

+ 10

∆

«

÷

◊

∆

«

÷

∆

«

÷

◊

(1)

(2)

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.

SNR_Jitter[dBc] = -20∂log(2p ∂ f_in∂T_Jitter)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by

the noise of the clock input buffer and the external clock. T_Jittercan be calculated with Equation 3.

2

T_Jitter= (T_{Jitter,Ext.Clock _ Input})²+(T_{Aperture_ ADC}

)

(3)

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External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band pass

filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The ADC324x has a

typical thermal noise of 73.5 dBFS and internal aperture jitter of 130 fs. Figure 141 shows SNR (from 1 MHz

offset leaving the 1/f flicker noise) for different jitter of clock driver.

73.0

Ext Clock Jitter

72.5

35 fs

72.0

71.5

71.0

70.5

70.0

69.5

69.0

68.5

68.0

67.5

67.0

50 fs

100 fs

150 fs

200 fs

10

100

1000

Input Frequency (MHz)

D03061

Figure 141. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array

(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using

the serial interface, as shown in Table 3. The output interface options are:

•

One-wire, 1x frame clock, 14x serialization with the DDR bit clock and

Two-wire, 0.5x frame clock, 7x serialization with the DDR bit clock.

Table 3. Interface Rates

RECOMMENDED SAMPLING

FREQUENCY (MSPS)

BIT CLOCK

FREQUENCY

(MHz)

FRAME CLOCK

FREQUENCY

(MHz)

INTERFACE

OPTIONS

SERIAL DATA

RATE (Mbps)

SERIALIZATION

MINIMUM

15⁽¹⁾

—

MAXIMUM

—

80

105

560

15

80

210

1120

140

1-wire

14x

7x

20⁽¹⁾

—

70

10

2-wire (default

after reset)

—

125

437.5

62.5

875

(1) Use the LOW SPEED ENABLE register bits for low speed operation; see Table 22.

9.3.3.1 One-Wire Interface: 14x Serialization

In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The

data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at

the rising edge of every frame clock, starting with the MSB. The data rate is 14x sample frequency (14x

serialization).

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9.3.3.2 Two-Wire Interface: 7x Serialization

The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x

sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC

sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as

shown in Figure 142. Note that in two-wire mode, the frame clock (FCLK) frequency is half of sampling clock

(CLKIN) frequency.

CLKIN

FCLK

DCLK

1-Wire (14x Serialization)

Dx0P

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

D

13

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

10 11 12 13

Dx0M

CLKIN

FCLK

DCLK

Dx0P

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

2-Wire (7x Serialization)

Dx0M

Dx1P

Dx1M

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

SAMPLE N-1

SAMPLE N

SAMPLE N+1

Figure 142. Output Timing Diagram

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9.4 Device Functional Modes

9.4.1 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a

faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for

operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the

divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC

noise spectrum by shifting the 1/f noise from dc to f_S/ 2. Figure 143 shows the noise spectrum with the chopper

off and Figure 144 shows the noise spectrum with the chopper on. This function is especially useful in

applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper

can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper

function creates a spur at f_S/ 2 that must be filtered out digitally.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D052

D051

f_IN= 10 MHz, f_S= 125 MHz

Figure 143. Chopper Off

Figure 144. Chopper On

9.4.3 Power-Down Control

The power-down functions of the ADC324x can be controlled either through the parallel control pin (PDN) or

through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-

down or standby functionality, as shown in Table 4.

Table 4. Power-Down Modes

FUNCTION

Global power-down

Standby

POWER CONSUMPTION (mW)

WAKE-UP TIME (µs)

5

85

35

81

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9.4.3.1 Improving Wake-Up Time From Global Power-Down

The device has an internal low-pass filter in the sampling clock path. This low-pass filter helps improve the

aperture jitter of the device. However, in applications where input frequencies are < 200 MHz, noise from the

aperture jitter does not dominate the overall SNR of the device. In such applications, the wake-up time from a

global power-down can be reduced by bypassing the low-pass filter using the DIS CLK FILT register bit (write

80h to register address 70Ah). As shown in Table 5, setting the DIS CLK FILT bit improves the wake-up time

from a global power-down from 85 µs to 55 µs.

Table 5. Wake-Up Time From Global Power-Down

WAKE-UP TIME

DIS CLK FILT

REGISTER BIT

GLOBAL PDN

REGISTER BIT

TYP

85

MAX

140

81

UNIT

µs

0

1

0→1→0

55

µs

9.4.4 Internal Dither Algorithm

The ADC324x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither

algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm

can be turned off by using the DIS DITH CHx registers bits. Figure 145 and Figure 146 show the effect of using

dither algorithms.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D103

D104

SFDR = 95.9 dBc, SNR = 72.7 dBFS, SINAD = 72.7 dBFS,

THD = 93.6 dBc, HD2 = –100.6 dBc, HD3 = –95.9 dBc

SFDR = 90.9 dBc, SNR = 73.3 dBFS, SINAD = 73.1 dBFS,

THD = 87 dBc, HD2 = –90.9 dBc, HD3 = –94.9 dBc

Figure 145. FFT with Dither On

Figure 146. FFT with Dither Off

9.5 Programming

The ADC324x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at

every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th

SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are

ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can

function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%

SCLK duty cycle.

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Programming (continued)

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 147. If required,

the serial interface registers can be cleared during operation either:

1. Through a hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

1. Drive the SEN pin low,

2. Set the R/W bit to 0 (bit A15 of the 16-bit address),

3. Set bit A14 in the address field to 1,

4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be

written, and

5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 147 and Table 6 show the timing requirements for the serial register write operation.

Register Address [13:0]

A13 A12 A11 A1

Register Data [7:0]

SDATA

R/W

= 0

1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 147. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

MIN

> dc

25

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIO setup time

)

20

25

ns

25

ns

t_DH

SDIO hold time

25

ns

(1) Typical values are at 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, and AVDD = DVDD = 1.8 V, unless otherwise

noted.

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9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

This readback mode can be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. Given below is the procedure to read contents of serial registers:

1. Drive the SEN pin low.

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.

3. Set bit A14 in the address field to 1.

4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.

5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.

6. The external controller can latch the contents at the SCLK rising edge.

7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the

SDOUT pin must float. Figure 148 shows a timing diagram of the serial register read operation. Data appear on

the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 149.

Register Address [13:0]

A13 A12 A11 A1

Register Data: Don‘t Care

D5 D4 D3 D2

SDATA

R/W

= 1

A0

D7

D6

D1

D0

1

Register Read Data [7:0]

SDOUT

SCLK

D5

D4

D3

D2

SEN

Figure 148. Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

Figure 149. SDOUT Timing Diagram

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9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in Figure 150 and Table 7.

Power

Supplies

t₁

RESET

t₂

t₃

SEN

Figure 150. Initialization of Serial Registers after Power-Up

Table 7. Power-Up Timing

MIN

1

TYP

MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay: delay from power up to active high RESET pulse

Reset pulse duration: active high RESET pulse duration

Register write delay: delay from RESET disable to SEN active

10

1000

100

ns

If required, the serial interface registers can be cleared during operation either:

1. Through hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

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9.6.1 Summary of Special Mode Registers

Table 9 lists the location, value, and functions of special mode registers in the device.

Table 9. Special Modes Summary

MODE

REGISTER SETTINGS

DESCRIPTION

Special modes

Registers 439h (bit 3) and 539h (bit 3)

Always set these bits high for best performance

Registers 1h (bits 5-2), 434h (bits 5 and 3), and

534h (bits 5 and 3)

Disable dither

Disable chopper

High IF modes

Disable dither to improve SNR

Registers 422h (bit 1) and 522h (bit 1)

Disable chopper to shift 1/f noise floor at dc

Improves HD3 for IF > 100 MHz

Registers 41Dh (bit 1), 51Dh (bit 1), and

608h (bits 7-6)

9.6.2 Serial Register Description

9.6.2.1 Register 01h

Figure 151. Register 01h

7

0

6

0

5

4

3

2

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 10. Register 01h Description

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0

These bits enable or disable the on-chip dither. Control this bit

with bits 5 and 3 of register 434h.

5-4

DIS DITH CHA

R/W

0h

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

These bits enable or disable the on-chip dither. Control this bit

with bits 5 and 3 of register 434h.

3-2

1-0

DIS DITH CHB

0

R/W

W

0h

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

Must write 0

9.6.2.2 Register 03h

Figure 152. Register 03h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ODD EVEN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 11. Register 03h Description

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

This bit selects the bit sequence on the output lanes

(in 2-wire mode only).

0 = Bits 0, 1, and 2 appear on lane 0; bits 7, 8, and 9 appear on lane 1

1 = Bits 0, 2, and 4 appear on lane 0; bits 1, 3, and 5 appear on lane 1

0

ODD EVEN

R/W

0h

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9.6.2.3 Register 04h

Figure 153. Register 04h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FLIP WIRE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 12. Register 04h Description

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

This bit flips the data on the output wires. Valid only in two wire

configuration.

0

FLIP WIRE

R/W

0h

0 = Default

1 = Data on output wires is flipped. Pin D0x becomes D1x, and

vice versa.

9.6.2.4 Register 05h

Figure 154. Register 05h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1W-2W

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 13. Register 05h Description

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

This bit transmits output data on either one or two wires.

0 = Output data are transmitted on two wires (Dx0P, Dx0M and

Dx1P, Dx1M)

0

1W-2W

R/W

0h

1 = Output data are transmitted on one wire (Dx0P, Dx0M). In this

mode, the recommended f_Sis less than 62.5 MSPS.

9.6.2.5 Register 06h

Figure 155. Register 06h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TEST PATTERN EN

R/W-0h

RESET

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 14. Register 06h Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

This bit enables test pattern selection for the digital outputs.

0 = Normal output

1 = Test pattern output enabled

1

0

TEST PATTERN EN

RESET

R/W

W

0h

This bit applies a software reset.

This bit resets all internal registers to the default values and self-

clears to 0.

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9.6.2.6 Register 07h

Figure 156. Register 07h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OVR ON LSB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 15. Register 07h Description

Bit

Field

Type

Reset

Description

7-1

0

W

0h

Must write 0

This bit provides the overrange (OVR) information on the LSB bits.

0 = Output data bit 0 functions as the LSB of the 14-bit data

1 = Output data bit 0 carries the OVR information.

0

OVR ON LSB

R/W

0h

9.6.2.7 Register 09h

Figure 157. Register 09h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ALIGN TEST

PATTERN

DATA FORMAT

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 16. Register 09h Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

This bit aligns the test patterns across the outputs of both channels.

0 = Test patterns of both channels are free running

1 = Test patterns of both channels are aligned

1

0

ALIGN TEST PATTERN

DATA FORMAT

R/W

0h

This bit programs the digital output data format.

0 = Twos complement

1 = Offset binary

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9.6.2.8 Register 0Ah

Figure 158. Register 0Ah

7

0

6

0

5

0

4

0

3

2

1

0

CHA TEST PATTERN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 17. Register 0Ah Description

Bit

Field

Type

Reset

Description

7-4

0

W

0h

Must write 0

These bits control the test pattern for channel A after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010 and

01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle from

code 0 to 16383

3-0

CHA TEST PATTERN

R/W

0h

0101 = Custom pattern: output data are the same as programmed by

the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192, 13984,

16383, 13984, 8192, 2399.

Others = Do not use

9.6.2.9 Register 0Bh

Figure 159. Register 0Bh

7

6

5

4

3

0

2

0

1

0

CHB TEST PATTERN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 18. Register 0Bh Description

Bit

7-4

3-0

Field

Type

R/W

W

Reset

Description

These bits control the test pattern for channel B after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010 and

01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle from

code 0 to 16383

0101 = Custom pattern: output data are the same as programmed by

the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192, 13984,

16383, 13984, 8192, 2399.

CHB TEST PATTERN

0h

Others = Do not use

0

0h

Must write 0

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9.6.2.10 Register 0Eh

Figure 160. Register 0Eh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[13:6]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. Register 0Eh Description

Bit

Field

Type

Reset

Description

These bits set the 14-bit custom pattern (bits 13-6) for all channels.

7-0

CUSTOM PATTERN[13:6]

R/W

0h

9.6.2.11 Register 0Fh

Figure 161. Register 0Fh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[5:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 20. Register 0Fh Description

Bit

7-2

1-0

Field

Type

R/W

W

Reset

0h

Description

CUSTOM PATTERN[5:0]

0

These bits set the 14-bit custom pattern (bits 5-0) for all channels.

Must write 0

0h

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9.6.2.12 Register 13h (address = 13h)

Figure 162. Register 13h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LOW SPEED ENABLE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 21. Register 13h Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0.

LOW SPEED ENABLE

R/W

0h

Enables low speed operation in 1-wire and 2-wire mode.

Depending upon sampling frequency, write this bit as per

Table 22.

Table 22. LOW SPEED ENABLE Register Bit Settings Across f_S

f_S(MSPS)

REGISTER BIT LOW SPEED ENABLE

MIN

25

MAX

125

25

1-WIRE MODE

2-WIRE MODE

00

10

00

10

20

15

20

Not supported

9.6.2.13 Register 15h

Figure 163. Register 15h

7

0

6

5

4

0

3

2

1

0

CHA PDN

R/W-0h

CHB PDN

R/W-0h

STANDBY

R/W-0h

GLOBAL PDN

R/W-0h

CONFIG PDN PIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 23. Register 15h Description

Bit

Field

Type

Reset

Description

7

0

W

0h

Must write 0

0 = Normal operation

1 = Power-down channel A

6

CHA PDN

R/W

0h

0 = Normal operation

1 = Power-down channel B

5

4

CHB PDN

0

R/W

W

0h

Must write 0

The ADCs of both channels enter standby.

0 = Normal operation

3

STANDBY

R/W

0h

1 = Standby

0 = Normal operation

1 = Global power-down

2

1

GLOBAL PDN

0

R/W

W

0h

Must write 0

This bit configures the PDN pin as either a global power-down or

standby pin.

0

CONFIG PDN PIN

R/W

0h

0 = Logic high voltage on the PDN pin sends the device into global

power-down

1 = Logic high voltage on the PDN pin sends the device into standby

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9.6.2.14 Register 25h

Figure 164. Register 25h

7

6

5

4

3

2

1

0

LVDS SWING

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Register 25h Description

Bit

Field

Type

Reset

Description

These bits control the swing of the LVDS outputs (including the

data output, bit clock, and frame clock). For details see

Table 25.

7-0

LVDS SWING

R/W

0h

Table 25. LVDS Output Swing

BITS 7-4

0h

BITS 3-0

0h

LVDS OUTPUT SWING

Default (±425 mV)

Dh

9h

Swing reduces by 50 mV

Swing reduces by 100 mV

Swing reduces by 300 mV

Swing increases by 100 mV

Do not use

Eh

Ah

Fh

Dh

Ch

Eh

Others

9.6.2.15 Register 27h

Figure 165. Register 27h

7

6

5

0

4

0

3

0

2

0

1

0

CLK DIV

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 26. Register 27h Description

Bit

7-6

5-0

Field

CLK DIV

0

Type

R/W

W

Reset

Description

These bits set the internal clock divider for the input sampling clock.

00 = Divide-by-1

01 = Divide-by-1

10 = Divide-by-2

11 = Divide-by-4

0h

Must write 0

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9.6.2.16 Register 41Dh

Figure 166. Register 41Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE0

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 27. Register 41Dh Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

This bit improves HD3 for IF > 100 MHz.

0 = Normal operation

For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

1

0

HIGH IF MODE0

0

R/W

W

0h

Must write 0

9.6.2.17 Register 422h

Figure 167. Register 422h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 28. Register 422h Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

Disable chopper.

Set this bit to shift a 1/f noise floor at dc.

1

DIS CHOP CHA

R/W

W

0h

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered at

dc

0

Must write 0

9.6.2.18 Register 434h

Figure 168. Register 434h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 29. Register 434h Description

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

5

4

DIS DITH CHA

R/W

W

0h

0

Must write 0

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

3

DIS DITH CHA

0

R/W

W

2-0

Must write 0

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9.6.2.19 Register 439h

Figure 169. Register 439h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 30. Register 439h Description

Bit

Field

Type

Reset

Description

7-4

0

W

0h

Must write 0

Special mode for best performance on channel A.

Always write 1 after reset.

3

SP1 CHA

0

R/W

W

0h

2-0

Must write 0

9.6.2.20 Register 51Dh

Figure 170. Register 51Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE1

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 31. Register 51Dh Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

This bit improves HD3 for IF > 100 MHz.

0 = Normal operation

For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

1

0

HIGH IF MODE1

0

R/W

W

0h

Must write 0

9.6.2.21 Register 522h

Figure 171. Register 522h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 32. Register 522h Description

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0

Disable chopper.

Set this bit to shift a 1/f noise floor at dc.

1

0

DIS CHOP CHB

0

R/W

W

0h

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered

at dc

Must write 0

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9.6.2.22 Register 534h

Figure 172. Register 534h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 33. Register 534h Description

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

5

4

DIS DITH CHA

R/W

W

0h

0

Must write 0

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

3

DIS DITH CHA

0

R/W

W

2-0

Must write 0

9.6.2.23 Register 539h

Figure 173. Register 539h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 34. Register 539h Description

Bit

Field

Type

Reset

Description

7-4

0

W

0h

Must write 0

Special mode for best performance on channel B.

Always write 1 after reset.

3

0

SP1 CHB

0

R/W

W

0h

Must write 0

9.6.2.24 Register 608h

Figure 174. Register 608h

7

6

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE[3:2]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 35. Register 608h Description

Bit

7-6

5-0

Field

Type

R/W

W

Reset

Description

This bit improves HD3 for IF > 100 MHz.

0 = Normal operation

For best HD3 at IF > 100 MHz, set HIGH IF MODE[3:0] to 1111.

HIGH IF MODE[3:2]

0

0h

Must write 0

67

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ZHCSD67C –JULY 2014–REVISED MARCH 2016

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9.6.2.25 Register 70Ah

Figure 175. Register 70Ah

7

6

0

5

0

4

0

3

0

2

0

1

0

DIS CLK FILT

R/W-0h

PDN SYSREF

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 36. Register 70Ah Description

Bit

7

Field

Type

R/W

W

Reset

Description

Set this bit to improve wake-up time from global power-down

mode; see the Improving Wake-Up Time From Global Power-

Down section for details.

DIS CLK FILT

0

0h

6-1

0h

Must write 0

If the SYSREF pins are not used in the system, the SYSREF

buffer must be powered down by setting this bit.

0 = Normal operation

0

PDN SYSREF

R/W

0h

1 = Powers down the SYSREF buffer

68

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10 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical applications involving transformer coupled circuits are discussed in this section. Transformers (such as

ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC

inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 176 and

Figure 177 show the impedance (Z_in= R_in|| C_in) across the ADC input pins.

10

6

5

4

3

2

1

0.1

0.01

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D024

D00215

Figure 176. Differential Input Resistance (R_IN

)

Figure 177. Differential Input Capacitance (C_IN)

69

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10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

39 nH

0.1 mF

INP

0.1 mF

50 Ω

25 Ω

0.1 mF

22 pF

50 Ω

INM

1:1

0.1 mF

39 nH

VCM

Device

Figure 178. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in

series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may

have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and

closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched

impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is shown in Figure 178. The circuit is

optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used

with the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curve

Figure 179 shows the performance obtained by using circuit shown in Figure 178.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D101

SFDR = 102.6 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,

THD = 99.8 dBc, HD2 = –108.6 dBc, HD3 = –104.0 dBc

Figure 179. Performance FFT at 10 MHz (Low Input Frequency)

70

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Typical Applications (continued)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

0.1 mF

10 Ω

INP

0.1 mF

15 Ω

25 Ω

0.1 mF

56 nH

10 pF

25 Ω

15 Ω

INM

10 Ω

1:1

0.1 mF

VCM

Device

Figure 180. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN< 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize

performance, as shown in Figure 180.

10.2.2.3 Application Curve

Figure 181 shows the performance obtained by using circuit shown in Figure 180.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D105

SFDR = 96.4 dBc, SNR = 72.1 dBFS, SINAD = 72.0 dBFS,

THD = 92.6 dBc, HD2 = –96.4 dBc, HD3 = –98.8 dBc

Figure 181. Performance FFT at 170 MHz (Mid Input Frequency)

71

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Typical Applications (continued)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

0.1 mF

10 Ω

INP

25 Ω

0.1 mF

25 Ω

INM

1:1

10 Ω

0.1 mF

VCM

Device

Figure 182. Driving Circuit for High input Frequencies ( f_IN> 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant

improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 182.

10.2.3.3 Application Curve

Figure 183 shows the performance obtained by using circuit shown in Figure 182.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D109

SFDR = 76.2 dBc, SNR = 68.3 dBFS, SINAD = 67.5 dBFS,

THD = 74.3 dBc, HD2 = –76.2 dBc, HD3 = –79.2 dBc

Figure 183. Performance FFT at 450 MHz (High Input Frequency)

11 Power-Supply Recommendations

The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply

requirements during device power-up. AVDD and DVDD can power up in any order.

72

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ZHCSD67C –JULY 2014–REVISED MARCH 2016

12 Layout

12.1 Layout Guidelines

The ADC324x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram

of the EVM top layer is provided in Figure 184. Some important points to remember during laying out the board

are:

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,

as shown in the reference layout of Figure 184 as much as possible.

2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 184

as much as possible.

3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, do not keep the

digital output traces parallel to the analog input traces because this configuration can result in coupling from

digital outputs to analog inputs and degrade performance. All digital output traces to the receiver [such as a

field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] must be matched

in length to avoid skew among outputs.

4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A

separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

12.2 Layout Example

{ampling

/lock

!nalog

Lnput

wouting

!5/32xx

5igital

hutput

wouting

Figure 184. Typical Layout of the ADC324x Board

73

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ZHCSD67C –JULY 2014–REVISED MARCH 2016

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13 器件和文档支持

13.1 相关链接

下面的表格列出了快速访问链接。范围包括技术文档、支持和社区资源、工具和软件，以及样片或购买的快速访

问。

表 37. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

ADC3241

ADC3242

ADC3243

ADC3244

13.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 商标

E2E is a trademark of Texas Instruments.

PowerPAD is a trademark of Texas Instruments, Inc.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

74

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC3241IRGZR

ADC3242IRGZR

ADC3243IRGZR

ADC3244IRGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC3241IRGZR

ADC3242IRGZR

ADC3243IRGZR

ADC3244IRGZR

VQFN

RGZ

48

2500

350.0

43.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048D

VQFN - 1 mm max height

S

C

A

L

E

1

.

9

0

PLASTIC QUAD FLATPACK - NO LEAD

7.1

6.9

A

B

0.5

0.3

PIN 1 INDEX AREA

7.1

6.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5.6 0.1

2X 5.5

(0.2) TYP

13

24

44X 0.5

12

25

EXPOSED

THERMAL PAD

2X

49

SYMM

5.5

SEE TERMINAL

DETAIL

1

36

0.30

48X

0.18

37

48

PIN 1 ID

(OPTIONAL)

SYMM

0.1

C A B

0.5

0.3

48X

0.05

4219046/B 11/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.6)

SYMM

48

37

48X (0.6)

1

36

48X (0.24)

6X

(1.22)

44X (0.5)

SYMM

10X

(1.33)

49

(6.8)

(R0.05)

TYP

(

0.2) TYP

VIA

25

12

13

24

10X (1.33)

6X (1.22)

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219046/B 11/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.665 TYP)

(1.33) TYP

16X ( 1.13)

37

48

48X (0.6)

49

36

1

48X (0.24)

44X (0.5)

(1.33)

TYP

(0.665)

TYP

SYMM

(6.8)

(R0.05) TYP

25

12

METAL

TYP

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:15X

4219046/B 11/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC3241IRGZT
厂家：	TEXAS INSTRUMENTS
描述：	双通道、14 位、25MSPS 模数转换器 (ADC) \| RGZ \| 48 \| -40 to 85 转换器模数转换器
文件：	总83页 (文件大小：4470K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC3241IRGZT [TI]

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