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ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

ADC32J4x 具有 JESD204B 接口的双通道、14 位、50MSPS 至

160MSPS 模数转换器

1 特性

3 说明

1

•

双通道

ADC32J4x 属于高线性度、超低功耗、双通道、14

位、50MSPS 至 160MSPS 模数转换器 (ADC) 系列。

此类器件专门设计用于支持具有宽动态范围需求且要求

苛刻的高输入频率信号。时钟输入分频器可给予系统

时钟架构设计更高的灵活性，SYSREF 输入可实现整

个系统同步。 ADC32J4x 系列支持 JESD204B 接口，

减少了接口线路数，从而实现高系统集成度。

•

14 位分辨率

单电源：1.8V

支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲

器

•

f_IN= 70MHz 时，信噪比 (SNR) = 72.2dBFS，无杂

散动态范围 (SFDR) = 87dBc

JESD204B 接口是串行接口，仅通过一个差分对即可

串行输出每个 ADC 的数据。内部锁相环 (PLL) 会将

传入的 ADC 采样时钟乘以 20，以获得串行化各通道

的 14 位数据时所使用的位时钟。该器件支持子类 1，

接口速率高达 3.2Gbps。

超低功耗：

–

160MSPS 时为每通道 227mW

•

通道隔离：105dB

内部抖动

JESD204B 串口：

器件信息⁽¹⁾

–

兼容子类 0、1、2，速率最高达 3.2Gbps

支持每个 ADC 一条通道（高达 160MSPS）

器件型号

ADC32J4x

封装

VQFN (48)

封装尺寸（标称值）

7.00mm x 7.00mm

•

支持多芯片同步

(1) 要了解所有可用封装，请见数据表末尾的封装选项附录。

与 12 位版本器件 (ADC32J2X) 引脚到引脚兼容

封装：超薄四方扁平无引线 (VQFN)-48 (7mm x

7mm)

f_S= 160MSPS 且 f_IN= 10MHz 时的性能

（SNR = 72.5dBFS，SFDR = 92dBc）

2 应用

0

-10

•

多载波、多模式蜂窝基站

-20

雷达和智能天线阵列

炮弹制导

-30

-40

电机控制反馈

-50

网络和矢量分析器

通信测试设备

-60

-70

-80

无损检测

-90

微波接收器

-100

-110

-120

软件定义无线电 (SDR)

正交和分集无线电接收器

0

16

32

48

64

80

Frequency (MHz)

D101

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS663

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

www.ti.com.cn

7.19 Typical Characteristics: Contour Plots.................. 43

Parameter Measurement Information ................ 44

8.1 Timing Diagrams..................................................... 44

Detailed Description ............................................ 46

9.1 Overview ................................................................. 46

9.2 Functional Block Diagram ....................................... 46

9.3 Feature Description................................................. 46

9.4 Device Functional Modes........................................ 53

9.5 Programming........................................................... 54

9.6 Register Maps......................................................... 58

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 6

7.6 Electrical Characteristics: ADC32J44, ADC32J45.... 7

7.7 Electrical Characteristics: ADC32J42, ADC32J43.... 7

7.8 AC Performance: ADC32J45 .................................... 8

7.9 AC Performance: ADC32J44 .................................. 10

7.10 AC Performance: ADC32J43 ................................ 12

7.11 AC Performance: ADC32J42 ................................ 14

7.12 Digital Characteristics ........................................... 16

7.13 Timing Requirements............................................ 17

7.14 Typical Characteristics: ADC32J45 ...................... 18

7.15 Typical Characteristics: ADC32J44 ...................... 24

7.16 Typical Characteristics: ADC32J43 ...................... 30

7.17 Typical Characteristics: ADC32J42 ...................... 36

7.18 Typical Characteristics: Common Plots ................ 42

8

9

10 Application and Implementation........................ 72

10.1 Application Information.......................................... 72

10.2 Typical Applications .............................................. 73

11 Power-Supply Recommendations ..................... 75

12 Layout................................................................... 76

12.1 Layout Guidelines ................................................. 76

12.2 Layout Example .................................................... 76

13 器件和文档支持 ..................................................... 77

13.1 相关链接................................................................ 77

13.2 社区资源................................................................ 77

13.3 商标....................................................................... 77

13.4 静电放电警告......................................................... 77

13.5 Glossary................................................................ 77

14 机械、封装和可订购信息....................................... 77

4 修订历史记录

Changes from Original (May 2014) to Revision A

Page

•

已从产品预览更改为量产数据 ................................................................................................................................................. 1

2

ADC32J42, ADC32J43, ADC32J44, ADC32J45

www.ti.com.cn

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

5 Device Comparison Table

RESOLUTION

INTERFACE

(Bits)

25 MSPS

ADC3221

ADC3241

—

50 MSPS

ADC3222

ADC3242

ADC32J22

ADC32J42

80 MSPS

ADC3223

ADC3243

ADC32J23

ADC32J43

125 MSPS

ADC3224

ADC3244

ADC32J24

ADC32J44

160 MSPS

—

12

Serial LVDS

14

—

12

ADC32J25

ADC32J45

JESD204B

14

—

6 Pin Configuration and Functions

RGZ Package

48-Pin VQFN

Top View

48

47

46

45

44

43

42

41

40

39

38

37

1

2

OVRA

NC

OVRB

36

35

34

33

32

31

30

29

28

27

26

25

NC

3

DVDD

AVDD

NC

DVDD

PDN

AVDD

NC

4

5

6

GND Pad

(Back Side)

7

NC

8

AVDD

INAP

INAM

AVDD

INBP

INBM

AVDD

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

3

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

AVDD

NO.

4, 5, 8, 9, 12, 17, 20,

25, 28, 29, 32, 39, 46

I

Analog 1.8-V power supply

CLKM

CLKP

DAM

DAP

18

I

Negative differential clock input for the ADC

Positive differential clock input for the ADC

Negative serial JESD204B output for channel A

Positive serial JESD204B output for channel A

Negative serial JESD204B output for channel B

Positive serial JESD204B output for channel B

Digital 1.8-V power supply

19

48

O

I

47

DBM

DBP

45

44

DVDD

GND

INAM

INAP

INBM

INBP

3,34

PowerPAD™

I

Ground, 0 V

11

10

26

27

I

Negative differential analog input for channel A

Positive differential analog input for channel A

Negative differential analog input for channel B

Positive differential analog input for channel B

I

2, 6, 7, 30, 31, 35,

37, 38, 40, 41

NC

—

Do not connect

OVRA

1

O

I

Overrange indicator for channel A

OVRB

36

33

21

13

14

16

15

42

43

23

22

24

Overrange indicator for channel B

PDN

Power-down control. This pin has an internal 150-kΩ pulldown resistor.

Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.

Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.

Serial Interface data input. This pin has an internal 150-kΩ pulldown resistor.

Serial interface data output

RESET

SCLK

I

SDATA

SDOUT

SEN

I

O

I

Serial interface enable. This pin has an internal 150-kΩ pullup resistor to AVDD.

Positive JESD204B SYNC~ input

SYNCM~

SYNCP~

SYSREFM

SYSREFP

VCM

I

Negative JESD204B SYNC~ input

I

Negative external SYSREF input

I

Positive external SYSREF input

O

Common-mode voltage output for analog inputs

4

ADC32J42, ADC32J43, ADC32J44, ADC32J45

www.ti.com.cn

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

2.1

UNIT

V

Supply voltage range, AVDD

Supply voltage range, DVDD

2.1

V

Minimum

(AVDD + 0.3, 2.1)

INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM

–0.3

V

Minimum

(AVDD + 0.3, 2.1)

CLKP, CLKM⁽²⁾

Voltage applied to

input pins:

Minimum

(AVDD + 0.3, 2.1)

SYSREFP, SYSREFM, SYNCP~, SYNCM~

SCLK, SEN, SDATA, RESET, PDN

Operating free-air, T_A

–0.3

–40

3.6

85

V

°C

Temperature

Operating junction, T_J

Storage, T_stg

125

150

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|).

This configuration prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage range

Digital supply voltage range

1.7

1.8

1.9

V

DVDD

ANALOG INPUT

For input frequencies < 450 MHz

For input frequencies < 600 MHz

2

1

V_PP

V

V_ID

V_IC

Differential input voltage

Input common-mode voltage

VCM ± 0.025

CLOCK INPUT

Input clock frequency

Sampling clock frequency

Sine wave, ac-coupled

LVPECL, ac-coupled

LVDS, ac-coupled

15

160⁽²⁾

MSPS

0.2

1.5

1.6

V

Input clock amplitude (differential)

0.7

Input clock duty cycle

35%

50%

0.95

65%

Input clock common-mode voltage

V

DIGITAL OUTPUTS

C_LOAD

R_LOAD

Maximum external load capacitance from each output pin to GND

Single-ended load resistance

3.3

50

pF

Ω

(1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.

(2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.

5

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

www.ti.com.cn

7.4 Thermal Information

ADC32J4x

THERMAL METRIC⁽¹⁾

RGZ (VQFN)

UNIT

48 PINS

25.7

18.9

3.0

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

3

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Electrical Characteristics

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUT

Differential input full-scale

Input resistance

2.0

6.5

5.2

0.95

10

V_PP

kΩ

r_i

Differential at dc

c_i

Input capacitance

Differential at dc

pF

V_OC(VCM)

VCM common-mode voltage output

VCM output current capability

Input common-mode current

V

mA

Per analog input pin

1.5

µA/MSPS

50-Ω differential source driving a

50-Ω termination across INP, INM

Analog input bandwidth (3 dB)

450

MHz

DC ACCURACY

E_O

Offset error

–20

–3

20

3

mV

Gain error as a result of internal

reference inaccuracy alone

E_G(REF)

%FS

E_G(CHAN)

Gain error of channel alone

±1

%FS

α_(EGCHAN)Temperature coefficient of E_G(CHAN)

–0.017

Δ%FS/Ch

CHANNEL-TO-CHANNEL ISOLATION

f_IN= 10 MHz

f_IN= 100 MHz

f_IN= 200 MHz

f_IN= 230 MHz

f_IN= 300 MHz

105

dB

Crosstalk⁽¹⁾

(1) Crosstalk is measured with a –1-dBFS input signal on aggressor channel and no input on victim channel.

6

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

7.6 Electrical Characteristics: ADC32J44, ADC32J45

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J44

TYP

ADC32J45

TYP

PARAMETER

MIN

MAX

MIN

MAX

UNIT

MSPS

Bits

mA

ADC clock frequency

125

160

Resolution

14

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

177

46

292

65

192

56

302

80

mA

401

5

535

454

5

560

mW

us

Global power-down dissipation

Wake-up time from global power-down

Standby power-down dissipation

Wake-up time from standby power-down

85

112

35

118

35

mW

µs

7.7 Electrical Characteristics: ADC32J42, ADC32J43

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J42

TYP

ADC32J43

TYP

PARAMETER

MIN

MAX

MIN

MAX

UNIT

MSPS

Bits

mA

ADC clock frequency

50

80

Resolution

14

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

134

22

281

5

267

45

152

31

272

46

mA

435

329

5

450

mW

us

Global power-down dissipation

Wake-up time from global power-down

Standby power-down dissipation

Wake-up time from standby power-down

85

99

35

85

105

35

mW

µs

7

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

www.ti.com.cn

7.8 AC Performance: ADC32J45

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC32J45 (f_S= 160 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

72.5

71.7

71.3

70.1

68.9

151.5

72.8

72.0

71.6

70.7

69.5

151.8

151.0

150.6

149.7

148.5

72.6

71.8

71.2

70.1

68.4

11.8

11.6

11.5

11.3

11.1

88

70.2

SNR

Signal-to-noise ratio

dBFS

–149.5 150.7

150.3

Noise spectral density

(averaged across Nyquist zone)

NSD

dBFS/Hz

dBFS

Bits

149.1

147.9

72.3

68.3

11.1

81

71.5

71.0

69.6

68.3

11.7

11.6

11.5

11.3

11.0

90

SINAD

ENOB

SFDR

HD2

Signal-to-noise and distortion ratio f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

Effective number of bits

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

85

Spurious-free dynamic range

85

84

dBc

84

83

81

80

90

91

81

91

92

Second-order harmonic distortion f_IN= 100 MHz

88

86

dBc

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

84

83

81

80

91

88

81

85

84

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

85

84

dBc

91

86

87

98

95

87

99

95

97

94

dBc

HD2, HD3 (excluding HD2, HD3)

92

91

89

8

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

AC Performance: ADC32J45 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC32J45 (f_S= 160 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

87

MAX

MIN

TYP

84

MAX

UNIT

f_IN= 70 MHz

78

84

83

THD

Total harmonic distortion

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

83

82

dBc

82

80

79

77

f_IN1= 45 MHz,

f_IN2= 50 MHz

90

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

86

DNL

INL

Differential nonlinearity

Integrated nonlinearity

f_IN= 70 MHz

±0.3

±1.5

±0.3

±1.5

LSBs

9

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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7.9 AC Performance: ADC32J44

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC32J44 (f_S= 125 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

72.6

72.3

72.1

70.1

70.0

150.6

72.8

72.5

72.3

71.7

70.8

150.8

150.5

150.3

149.7

148.8

72.7

72.4

72.2

71.4

70.2

11.8

11.7

11.6

11.4

92

70.8

SNR

Signal-to-noise ratio

dBFS

–148.8 150.3

150.1

Noise spectral density

(averaged across Nyquist zone)

NSD

dBFS/Hz

dBFS

Bits

148.1

148.0

72.5

68.6

11.1

81

72.2

72.0

70.7

69.5

11.8

11.7

11.4

11.2

94

SINAD

ENOB

SFDR

HD2

Signal-to-noise and distortion ratio f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

Effective number of bits

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

93

91

Spurious-free dynamic range

93

90

dBc

85

84

82

81

95

92

81

94

Second-order harmonic distortion f_IN= 100 MHz

93

91

dBc

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

85

84

82

81

96

92

82

93

90

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

93

90

dBc

88

91

93

99

96

87

99

96

98

96

dBc

HD2, HD3 (excluding HD2, HD3)

98

95

96

91

10

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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AC Performance: ADC32J44 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,

unless otherwise noted.

ADC32J44 (f_S= 125 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

91

MAX

MIN

TYP

87

MAX

UNIT

f_IN= 70 MHz

78

90

87

THD

Total harmonic distortion

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

90

87

dBc

83

82

80

79

f_IN1= 45 MHz,

f_IN2= 50 MHz

91

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

86

DNL

INL

Differential nonlinearity

Integrated nonlinearity

f_IN= 70 MHz

±0.3

±1.5

±0.3

±1.5

LSBs

11

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7.10 AC Performance: ADC32J43

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J43 (f_S= 80 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

72.3

72.2

72.0

71.4

70.6

148.4

72.6

72.4

72.2

71.8

71.0

148.7

148.4

148.2

147.8

147.0

72.5

72.2

72.0

71.4

70.2

11.8

11.7

11.6

11.4

91

70.8

SNR

Signal-to-noise ratio

dBFS

–146.8 148.2

148.0

Noise spectral density

(averaged across Nyquist zone)

NSD

dBFS/Hz

dBFS

Bits

147.4

146.6

72.3

68.6

11.1

82

72.2

71.9

71.0

69.9

11.7

11.6

11.5

11.3

96

SINAD

ENOB

SFDR

HD2

Signal-to-noise and distortion ratio f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

Effective number of bits

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

95

90

Spurious-free dynamic range

91

88

dBc

85

84

81

80

96

95

81

98

96

Second-order harmonic distortion f_IN= 100 MHz

93

91

dBc

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

85

84

81

80

95

93

83

92

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

91

88

dBc

92

91

83

99

93

87

99

93

97

92

dBc

HD2, HD3 (excluding HD2, HD3)

97

93

95

92

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AC Performance: ADC32J43 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J43 (f_S= 80 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

93

MAX

MIN

TYP

87

MAX

UNIT

f_IN= 70 MHz

78

93

87

THD

Total harmonic distortion

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

87

85

dBc

83

82

79

77

f_IN1= 45 MHz,

f_IN2= 50 MHz

90

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

89

DNL

INL

Differential nonlinearity

Integrated nonlinearity

f_IN= 70 MHz

±0.3

±1.5

±0.3

±1.5

LSBs

13

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7.11 AC Performance: ADC32J42

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J42 (f_S= 50 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

DYNAMIC AC CHARACTERISTICS

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

71.3

72.2

71.8

71.1

69.1

146.1

145.8

145.1

143.1

72.1

71.8

71.7

70.8

68.4

11.7

11.6

11.5

11.1

95

72.5

72.1

72.0

71.5

69.4

146.5

146.1

146.0

145.5

143.4

72.3

71.9

71.8

71.1

68.7

11.7

11.6

11.5

11.1

93

SNR

Signal-to-noise ratio

dBFS

Noise spectral density

(averaged across Nyquist zone)

NSD

dBFS/Hz

dBFS

Bits

69.1

11.2

84.5

87

SINAD

ENOB

SFDR

HD2

Signal-to-noise and distortion ratio f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

Effective number of bits

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

95

90

Spurious-free dynamic range

91

89

dBc

85

84

81

80

95

94

97

96

Second-order harmonic distortion f_IN= 100 MHz

92

dBc

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

85

84

81

80

102

95

93

90

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

91

89

dBc

88

82

83

98

91

94

92

91

dBc

HD2, HD3 (excluding HD2, HD3)

96

92

93

91

14

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AC Performance: ADC32J42 (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to T_MAX

= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless

otherwise noted.

ADC32J42 (f_S= 50 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

79.5

TYP

92

MAX

MIN

TYP

90

MAX

UNIT

f_IN= 70 MHz

91

87

THD

Total harmonic distortion

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

88

85

dBc

83

82

78

f_IN1= 45 MHz,

f_IN2= 50 MHz

90

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

86

DNL

INL

Differential nonlinearity

Integrated nonlinearity

f_IN= 70 MHz

±0.3

±1.5

±0.3

±1.5

LSBs

15

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7.12 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)⁽¹⁾

V_IH

V_IL

High-level input voltage

Low-level input voltage

All digital inputs support 1.8-V and 3.3-V logic levels

1.2

V

All digital inputs support 1.8-V and 3.3-V logic levels

0.4

V

SEN

0

10

0

µA

I_IH

High-level input current

Low-level input current

RESET, SCLK, SDATA, PDN

SEN

I_IL

RESET, SCLK, SDATA, PDN

DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

0.5

V

Common-mode voltage for SYNC~

and SYSREF

V_{(CM_DIG)}

0.95

V

DIGITAL OUTPUTS (SDOUT, OVRA, OVRB)

DVDD –

0.1

V_OH

High-level output voltage

DVDD

V

V_OL

Low-level output voltage

0.1

DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)⁽²⁾

V_OH

V_OL

V_OD

V_OC

High-level output voltage

Low-level output voltage

Output differential voltage

Output common-mode voltage

AVDD

AVDD – 0.4

0.4

V

AVDD – 0.2

Transmitter pins shorted to any voltage between

–0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

–100

100

mA

Ω

z_os

50

2

Output capacitance inside the device,

from either output to ground

pF

(1) The RESET, SCLK, SDATA, and PDN pins have a 150-kΩ (typical) internal pulldown resistor to ground, and the SEN pin has a 150-kΩ

(typical) pullup resistor to AVDD.

(2) 50-Ω, single-ended external termination to 1.8 V.

16

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7.13 Timing Requirements

Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and

maximum values are across the full temperature range: T_MIN= –40°C to T_MAX= 85°C. See Figure 143.

MIN

TYP

MAX

UNITS

SAMPLE TIMING REQUIREMENTS

Aperture delay

0.85

1.25

±70

1.65

ns

ps

Between four channels on the same device

Aperture delay matching

Between two devices at the same temperature and

supply voltage

±150

ps

Aperture jitter

Wake-up time

200

35

f_Srms

µs

Time to valid data after coming out of STANDBY mode

Time to valid data after coming out of global power-down

100

300

85

µs

t_{SU_SYNC~}

t_{H_SYNC~}

t_{SU_SYSREF}

t_{H_SYSREF}

Setup time for SYNC~ referenced to input clock rising edge

Hold time for SYNC~ referenced to input clock rising edge

1

100

1

ns

ps

Setup time for SYSREF referenced to input clock rising edge

Hold time for SYSREF referenced to input clock rising edge

ns

100

ps

CML OUTPUT TIMING REQUIREMENTS

Unit interval

312.5

1667

3.2

ps

Serial output data rate

Gbps

_P-PUI

Total jitter: 3.125 Gbps (20X mode, f_S= 156.25 MSPS)

0.3

Data rise time, data fall time: rise and fall times measured from 20% to 80%,

differential output waveform, 600 Mbps ≤ bit rate ≤ 3.125 Gbps

t_R, t_F

105

ps

Table 1. Latency in Different Modes⁽¹⁾⁽²⁾

MODE

PARAMETER

LATENCY (N Cycles)

TYPICAL DATA DELAY (t_D, ns)

0.29 × t_S+ 3

0.5 × t_S+ 2

ADC latency

17

9

Normal OVR latency

20X

Fast OVR latency

7

0.5 × t_S+ 2

From SYNC~ falling edge to CGS phase⁽³⁾

From SYNC~ rising edge to ILA sequence⁽⁴⁾

ADC latency

15

17

16

9

0.3 × t_S+ 4

0.85 × t_S+ 3.9

0.5 × t_S+ 2

Normal OVR latency

40X

Fast OVR latency

7

0.5 × t_S+ 2

From SYNC~ falling edge to CGS phase⁽³⁾

From SYNC~ rising edge to ILA sequence⁽⁴⁾

14

12

0.9 × t_S+ 4

(1) Overall latency = latency + t_D.

(2) t_Sis the time period of the ADC conversion clock.

(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10X mode and 15

clock cycles in 20X mode.

(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10X mode and

11 clock cycles in 20X mode.

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7.14 Typical Characteristics: ADC32J45

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D101

D102

f_S= 160 MSPS, SNR = 72.4 dBFS, f_IN= 10 MHz,

SFDR = 92.3 dBc

f_S= 160 MSPS, SNR = 72.7 dBFS, f_IN= 10 MHz,

SFDR = 92.7 dBc

Figure 1. FFT for 10-MHz Input Signal (Dither On)

Figure 2. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D103

D104

f_S= 160 MSPS, SNR = 71.7 dBFS, f_IN= 70 MHz,

SFDR = 86 dBc

f_S= 160 MSPS, SNR = 72.1 dBFS, f_IN= 70 MHz,

SFDR = 85 dBc

Figure 3. FFT for 70-MHz Input Signal (Dither On)

Figure 4. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D105

D106

f_S= 160 MSPS, SNR = 70.6 dBFS, f_IN= 170 MHz,

SFDR = 85 dBc

f_S= 160 MSPS, SNR = 71.4 dBFS, f_IN= 170 MHz,

SFDR = 84 dBc

Figure 5. FFT for 170-MHz Input Signal (Dither On)

Figure 6. FFT for 170-MHz Input Signal (Dither Off)

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Typical Characteristics: ADC32J45 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D107

D108

f_S= 160 MSPS, SNR = 69.3 dBFS, f_IN= 270 MHz,

SFDR = 78.9 dBc

f_S= 160 MSPS, SNR = 69.9 dBFS, f_IN= 270 MHz,

SFDR = 79.3 dBc

Figure 7. FFT for 270-MHz Input Signal (Dither On)

Figure 8. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D109

D110

f_S= 160 MSPS, SNR = 63.2 dBFS, f_IN= 450 MHz,

SFDR = 65.7 dBc

f_S= 160 MSPS, SNR = 63.8 dBFS, f_IN= 450 MHz,

SFDR = 67 dBc

Figure 9. FFT for 450-MHz Input Signal (Dither On)

Figure 10. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D111

D112

f_S= 160 MSPS, IMD = 92 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

f_S= 160 MSPS, IMD = 99 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

Figure 11. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 12. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

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Typical Characteristics: ADC32J45 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D113

D114

f_S= 160 MSPS, IMD = 87 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

f_S= 160 MSPS, IMD = 100 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

Figure 13. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 14. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-80

-85

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D115

D116

f_S= 160 MSPS, f_IN1= 46 MHz, f_IN2= 50 MHz

f_S= 160 MSPS, f_IN1= 185 MHz, f_IN2= 190 MHz

Figure 15. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 16. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

100

73

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

72

92

84

76

68

60

71

70

69

68

67

66

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D117

D118

Figure 17. Signal-to-Noise Ratio vs Input Frequency

Figure 18. Spurious-Free Dynamic Range vs

Input Frequency

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Typical Characteristics: ADC32J45 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

120

110

100

90

74.5

72.5

70.5

68.5

66.5

64.5

62.5

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

80

70

60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Digital Gain (dB)

D119

D120

Figure 19. Signal-to-Noise Ratio vs

Digital Gain and Input Frequency

Figure 20. Spurious-Free Dynamic Range vs

Digital Gain and Input Frequency

76

180

76

180

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

72

70

68

66

64

150

120

90

60

30

0

74.5

73

150

120

90

60

30

0

71.5

70

68.5

67

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D121

D122

Figure 21. Performance vs Input Amplitude (30 MHz)

Figure 22. Performance vs Input Amplitude (170 MHz)

72.8

72.6

72.4

72.2

72

94

SNR

SFDR

71.1

70.9

70.7

70.5

70.3

70.1

69.9

92

SNR

SFDR

88

92

90

88

86

84

80

76

72

68

71.8

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common - Mode Voltage (V)

D123

D124

Figure 23. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 24. Performance vs Input Common-Mode Voltage

(170 MHz)

21

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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Typical Characteristics: ADC32J45 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

94

92

90

88

86

84

71.5

71.1

70.7

70.3

69.9

69.5

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D125

D126

Figure 25. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

Figure 26. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

71.6

71.2

70.8

70.4

70

91

90

89

88

87

86

85

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

69.6

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D127

D128

Figure 27. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

Figure 28. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

84

80

76

72

68

64

110

100

90

140

120

100

80

SNR

SFDR

SNR

SFDR

85

80

75

70

65

60

55

60

80

40

70

20

60

0

0.2

0.6

1

1.4

1.8

2.2

0.2

0.6

1

1.4

1.8

2.2

Differential Clock Amplitude (Vpp)

D129

D130

Figure 29. Performance vs Clock Amplitude (40 MHz)

Figure 30. Performance vs Clock Amplitude (150 MHz)

22

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J45 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, 32k-point FFT, dither enabled, and special modes written, unless otherwise noted.

71

70.75

70.5

100

95

90

85

80

75

70

72.9

72.7

72.5

72.3

72.1

71.9

100

96

92

88

84

80

SNR

SFDR

SNR

SFDR

70.25

70

69.75

69.5

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D131

D132

Figure 31. Performance vs Clock Duty Cycle (40 MHz)

Figure 32. Performance vs Clock Duty Cycle (150 MHz)

28

26

24

22

20

18

16

14

12

10

8

6

4

2

0

D133

Output Code (LSB)

RMS noise = 1.3 LSBs

Figure 33. Idle Channel Histogram

23

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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7.15 Typical Characteristics: ADC32J44

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D301

D302

f_S= 125 MSPS, SNR = 72.4 dBFS, f_IN= 10 MHz,

SFDR = 98.3 dBc

f_S= 125 MSPS, SNR = 72.7 dBFS, f_IN= 10 MHz,

SFDR = 94.7 dBc

Figure 34. FFT for 10-MHz Input Signal (Dither On)

Figure 35. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D303

D304

f_S= 125 MSPS, SNR = 71.9 dBFS, f_IN= 70 MHz,

SFDR = 91 dBc

f_S= 125 MSPS, SNR = 72.3 dBFS, f_IN= 70 MHz,

SFDR = 90 dBc

Figure 36. FFT for 70-MHz Input Signal (Dither On)

Figure 37. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D305

D306

f_S= 125 MSPS, SNR = 71 dBFS, f_IN= 170 MHz,

SFDR = 86 dBc

f_S= 125 MSPS, SNR = 71.9 dBFS, f_IN= 70 MHz,

SFDR = 85 dBc

Figure 38. FFT for 170-MHz Input Signal (Dither On)

Figure 39. FFT for 170-MHz Input Signal (Dither Off)

24

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Typical Characteristics: ADC32J44 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D307

D308

f_S= 125 MSPS, SNR = 70.4 dBFS, f_IN= 270 MHz,

SFDR = 80.1 dBc

f_S= 125 MSPS, SNR = 70.5 dBFS, f_IN= 270 MHz,

SFDR = 79.4 dBc

Figure 40. FFT for 270-MHz Input Signal (Dither On)

Figure 41. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D309

D310

f_S= 125 MSPS, SNR = 64.2 dBFS, f_IN= 450 MHz,

SFDR = 68.7 dBc

f_S= 125 MSPS, SNR = 64.6 dBFS, f_IN= 450 MHz,

SFDR = 68.9 dBc

Figure 42. FFT for 450-MHz Input Signal (Dither On)

Figure 43. FFT for 450-MHz Input Signal (Dither Off)

0

-10

-20

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D311

D312

f_S= 125 MSPS, IMD = 93 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

f_S= 125 MSPS, IMD = 101 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

Figure 44. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 45. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

25

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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Typical Characteristics: ADC32J44 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D313

D314

f_S= 125 MSPS, IMD = 88 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

f_S= 125 MSPS, IMD = 99 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

Figure 46. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 47. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-80

-85

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D315

D7175

Figure 48. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 49. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

100

73.5

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

95

72.5

71.5

70.5

69.5

68.5

90

85

80

75

70

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D717

D318

Figure 50. Signal-to-Noise Ratio vs Input Frequency

Figure 51. Spurious-Free Dynamic Range vs

Input Frequency

26

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J44 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

120

110

100

90

74.5

72.5

70.5

68.5

66.5

64.5

62.5

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

80

70

60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Digital Gain (dB)

D319

D320

Figure 52. Signal-to-Noise Ratio vs

Digital Gain and Input Frequency

Figure 53. Spurious-Free Dynamic Range vs

Digital Gain and Input Frequency

76

180

76

210

180

150

120

90

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74.5

73

150

120

90

60

30

0

74.5

73

71.5

70

71.5

70

68.5

60

67

30

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D321

D322

Figure 54. Performance vs Input Amplitude (30 MHz)

Figure 55. Performance vs Input Amplitude (170 MHz)

73.2

73

98

SNR

SFDR

71.7

71.5

71.3

71.1

70.9

70.7

70.5

86

SNR

SFDR

84

96

94

92

90

88

82

80

78

76

74

72.8

72.6

72.4

72.2

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common - Mode Voltage (V)

D723

D324

Figure 56. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 57. Performance vs Input Common-Mode Voltage

(170 MHz)

27

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Typical Characteristics: ADC32J44 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

90

88

86

84

82

80

72

71.6

71.2

70.8

70.4

70

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D325

D326

Figure 58. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

Figure 59. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

71.6

71.4

71.2

71

89

88

87

86

85

84

83

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

70.8

70.6

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D327

D328

Figure 60. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

Figure 61. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

84

80

76

72

68

64

110

100

90

140

120

100

80

SNR

SFDR

SNR

SFDR

85

80

75

70

65

60

55

60

80

40

70

20

60

0

0.2

0.6

1

1.4

1.8

2.2

0.2

0.6

1

1.4

1.8

2.2

Differential Clock Amplitude (Vpp)

D329

D330

Figure 62. Performance vs Clock Amplitude (40 MHz)

Figure 63. Performance vs Clock Amplitude (150 MHz)

28

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Typical Characteristics: ADC32J44 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

71.5

71.25

71

90

72.9

72.7

72.5

72.3

72.1

71.9

100

96

92

88

84

80

SNR

SFDR

SNR

SFDR

87.5

85

70.75

70.5

70.25

70

82.5

80

77.5

75

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D331

D332

Figure 64. Performance vs Clock Duty Cycle (40 MHz)

Figure 65. Performance vs Clock Duty Cycle (150 MHz)

28

26

24

22

20

18

16

14

12

10

8

6

4

2

0

D333

Output Code (LSB)

RMS noise = 1.4 LSBs

Figure 66. Idle Channel Histogram

29

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7.16 Typical Characteristics: ADC32J43

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D501

D502

f_S= 80 MSPS, SNR = 72.2 dBFS, f_IN= 10 MHz, SFDR = 93.1 dBc

f_S= 80 MSPS, SNR = 72.6 dBFS, f_IN= 10 MHz, SFDR = 91.4 dBc

Figure 67. FFT for 10-MHz Input Signal (Dither On)

Figure 68. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D503

D504

f_S= 80 MSPS, SNR = 72.1 dBFS, f_IN= 70 MHz, SFDR = 92 dBc

f_S= 80 MSPS, SNR = 72.5 dBFS, f_IN= 70 MHz, SFDR = 91 dBc

Figure 69. FFT for 70-MHz Input Signal (Dither On)

Figure 70. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D505

D506

f_S= 80 MSPS, SNR = 71 dBFS, f_IN= 170 MHz, SFDR = 86 dBc

f_S= 80 MSPS, SNR = 69.7 dBFS, f_IN= 10 MHz, SFDR = 85 dBc

Figure 71. FFT for 170-MHz Input Signal (Dither On)

Figure 72. FFT for 170-MHz Input Signal (Dither Off)

30

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J43 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D507

D508

f_S= 80 MSPS, SNR = 70.2 dBFS, f_IN= 270 MHz,

SFDR = 76.9 dBc

f_S= 80 MSPS, SNR = 70.5 dBFS, f_IN= 270 MHz,

SFDR = 76.7 dBc

Figure 73. FFT for 270-MHz Input Signal (Dither On)

Figure 74. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D509

D510

f_S= 80 MSPS, SNR = 64.5 dBFS, f_IN= 450 MHz,

SFDR = 67.6 dBc

f_S= 80 MSPS, SNR = 63.8 dBFS, f_IN= 450 MHz,

SFDR = 67.4 dBc

Figure 75. FFT for 450-MHz Input Signal (Dither On)

Figure 76. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D511

D512

f_S= 80 MSPS, IMD = 93 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

f_S= 80 MSPS, IMD = 101 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

Figure 77. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 78. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

31

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Typical Characteristics: ADC32J43 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D513

D514

f_S= 80 MSPS, IMD = 88 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

f_S= 80 MSPS, IMD = 99 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

Figure 79. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 80. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-80

-85

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D715

D7165

Figure 81. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 82. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

100

73.5

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

95

72.5

71.5

70.5

69.5

68.5

90

85

80

75

70

65

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D717

D718

Figure 83. Signal-to-Noise Ratio vs Input Frequency

Figure 84. Spurious-Free Dynamic Range vs Input

Frequency

32

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J43 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

120

110

100

90

74.5

72.5

70.5

68.5

66.5

64.5

62.5

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

80

70

60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Digital Gain (dB)

D719

D720

Figure 85. Signal-to-Noise Ratio vs

Digital Gain and Input Frequency

Figure 86. Spurious-Free Dynamic Range vs

Digital Gain and Input Frequency

76

180

76

210

180

150

120

90

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74.5

73

150

120

90

60

30

0

74.5

73

71.5

70

71.5

70

68.5

60

67

30

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D721

D722

Figure 87. Performance vs Input Amplitude (30 MHz)

Figure 88. Performance vs Input Amplitude (170 MHz)

73

72.8

72.6

72.4

72.2

72

110

SNR

SFDR

72.4

72.1

71.8

71.5

71.2

70.9

100

SNR

SFDR

100

90

80

70

60

90

80

70

60

50

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common - Mode Voltage (V)

D723

D724

Figure 89. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 90. Performance vs Input Common-Mode Voltage

(170 MHz)

33

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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Typical Characteristics: ADC32J43 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

90

88

86

84

82

80

72

71.6

71.2

70.8

70.4

70

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D725

D726

Figure 91. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

Figure 92. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

71.8

71.6

71.4

71.2

71

88

87

86

85

84

83

82

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

70.8

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D727

D728

Figure 93. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

Figure 94. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

80

76

72

68

64

60

110

100

90

85

140

120

100

80

SNR

SFDR

SNR

SFDR

80

75

70

65

60

55

50

60

80

40

70

20

60

0

0.2

0.6

1

1.4

1.8

2.2

0.2

0.6

1

1.4

1.8

2.2

Differential Clock Amplitude (Vpp)

D729

D730

Figure 95. Performance vs Clock Amplitude (40 MHz)

Figure 96. Performance vs Clock Amplitude (150 MHz)

34

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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Typical Characteristics: ADC32J43 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

73

72.75

72.5

104

100

96

71.8

71.3

70.8

70.3

69.8

69.3

68.8

90

88

86

84

82

80

78

SNR

SFDR

SNR

SFDR

72.25

72

92

88

71.75

84

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D731

D732

Figure 97. Performance vs Clock Duty Cycle (40 MHz)

Figure 98. Performance vs Clock Duty Cycle (150 MHz)

32.5

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

5

2.5

0

D733

Output Code (LSB)

RMS noise = 1.4 LSBs

Figure 99. Idle Channel Histogram

35

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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7.17 Typical Characteristics: ADC32J42

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D701

D702

f_S= 50 MSPS, SNR = 72.1 dBFS, f_IN= 10 MHz, SFDR = 96.2 dBc

f_S= 50 MSPS, SNR = 72.6 dBFS, f_IN= 10 MHz, SFDR = 92.1 dBc

Figure 100. FFT for 10-MHz Input Signal (Dither On)

Figure 101. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D703

D704

f_S= 50 MSPS, SNR = 71.7 dBFS, f_IN= 70 MHz, SFDR = 93.2 dBc

f_S= 50 MSPS, SNR = 72 dBFS, f_IN= 70 MHz, SFDR = 92 dBc

Figure 102. FFT for 70-MHz Input Signal (Dither On)

Figure 103. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D705

D706

f_S= 50 MSPS, SNR = 70.4 dBFS, f_IN= 170 MHz,

SFDR = 86 dBc

f_S= 50 MSPS, SNR = 70.9 dBFS, f_IN= 170 MHz,

SFDR = 85 dBc

Figure 104. FFT for 170-MHz Input Signal (Dither On)

Figure 105. FFT for 170-MHz Input Signal (Dither Off)

36

ADC32J42, ADC32J43, ADC32J44, ADC32J45

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J42 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D707

D708

f_S= 50 MSPS, SNR = 69.5 dBFS, f_IN= 270 MHz,

SFDR = 75.7 dBc

f_S= 50 MSPS, SNR = 69.5 dBFS, f_IN= 270 MHz,

SFDR = 75.7 dBc

Figure 106. FFT for 270-MHz Input Signal (Dither On)

Figure 107. FFT for 270-MHz Input Signal (Dither Off)

0

-10

-20

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D709

D710

f_S= 50 MSPS, SNR = 65.9 dBFS, f_IN= 450 MHz,

SFDR = 67.4 dBc

f_S= 50 MSPS, SNR = 66.4 dBFS, f_IN= 450 MHz, SFDR = 67 dBc

Figure 108. FFT for 450-MHz Input Signal (Dither On)

Figure 109. FFT for 450-MHz Input Signal (Dither Off)

0

-10

-20

-30

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D711

D712

f_S= 50 MSPS, IMD = 93 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

f_S= 50 MSPS, IMD = 101 dBFS, f_IN1= 46 MHz, f_IN2= 50 MHz

Figure 110. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 111. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

37

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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Typical Characteristics: ADC32J42 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D713

D714

f_S= 50 MSPS, IMD = 86 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

f_S= 50 MSPS, IMD = 99 dBFS, f_IN1= 185 MHz, f_IN2= 190 MHz

Figure 112. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 113. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-80

-85

-80

-85

-90

-95

-100

-105

-110

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D715

D7165

Figure 114. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 115. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

100

73

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

95

72

90

85

80

75

70

65

71

70

69

68

67

66

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D717

D718

Figure 116. Signal-to-Noise Ratio vs Input Frequency

Figure 117. Spurious-Free Dynamic Range vs

Input Frequency

38

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Characteristics: ADC32J42 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

120

110

100

90

74

72

70

68

66

64

62

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

10 MHz

70 MHz

100 MHz

170 MHz

230 MHz

270 MHz

400 MHz

80

70

60

0

1

2

3

4

5

6

0

1

2

3

4

5

6

Digital Gain (dB)

D719

D720

Figure 118. Signal-to-Noise Ratio vs

Digital Gain and Input Frequency

Figure 119. Spurious-Free Dynamic Range vs

Digital Gain and Input Frequency

77

75

73

71

69

67

65

175

76

175

150

125

100

75

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

150

125

100

75

74.5

73

71.5

70

50

68.5

50

25

67

25

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D721

D722

Figure 120. Performance vs Input Amplitude (30 MHz)

Figure 121. Performance vs Input Amplitude (170 MHz)

71.5

71.3

71.1

70.9

70.7

70.5

90

SNR

SFDR

72.8

72.6

72.4

72.2

72

100

SNR

SFDR

98

96

94

92

90

88

86

84

82

80

71.8

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common - Mode Voltage (V)

D723

D724

Figure 122. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 123. Performance vs Input Common-Mode Voltage

(170 MHz)

39

ADC32J42, ADC32J43, ADC32J44, ADC32J45

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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Typical Characteristics: ADC32J42 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

100

98

96

94

92

90

73.4

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

73

72.6

72.2

71.8

71.4

71

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D725

D726

Figure 124. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

Figure 125. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

100

98

96

94

92

90

73.4

73

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

72.6

72.2

71.8

71.4

71

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D727

D728

Figure 126. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

Figure 127. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

80

110

100

90

85

140

120

100

80

SNR

SFDR

SNR

SFDR

80

75

70

65

60

55

50

76

72

68

64

60

80

40

70

20

60

0

0.2

0.6

1

1.4

1.8

2.2

0.2

0.6

1

1.4

1.8

2.2

Differential Clock Amplitude (Vpp)

D729

D730

Figure 128. Performance vs Clock Amplitude (40 MHz)

Figure 129. Performance vs Clock Amplitude (150 MHz)

40

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Typical Characteristics: ADC32J42 (continued)

Typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

71.7

71.3

70.9

70.5

70.1

69.7

69.3

92

90

88

86

84

82

80

72.5

72.3

72.1

71.9

71.7

71.5

71.3

100

98

96

94

92

90

88

SNR

SFDR

SNR

SFDR

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D731

D732

Figure 130. Performance vs Clock Duty Cycle (40 MHz)

Figure 131. Performance vs Clock Duty Cycle (150 MHz)

33

30

27

24

21

18

15

12

9

6

3

0

D733

Output Code (LSB)

RMS noise = 1.3 LSBs

Figure 132. Idle Channel Histogram

41

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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7.18 Typical Characteristics: Common Plots

Typical values are at T_A= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS

differential input, 2-V_PPfull-scale, and 32k-point FFT, unless otherwise noted.

0

±20

±35

±40

±45

±50

±55

±60

±65

Input Frequency = 30MHz

50-mV_PPSignal Superimposed on VCM

±40

±60

±80

±100

±120

0

30

60

90

120 150 180 210 240 270 300

0

16

32

48

64

80

Common-Mode Test Signal Frequency (MHz))

C041

Frequency (MHz)

C040

f_S= 160 MSPS, f_CM= 10 MHz, 50 mV_PP, f_IN= 30 MHz, Amplitude

(f_IN+ f_CM) = –98 dBFS, Amplitude (f_IN– f_CM) = –91 dBFS

Figure 134. CMRR vs Test Signal Frequency

Figure 133. CMRR FFT

0

±25

±30

±35

±40

±45

±50

±55

±60

Input Frequency = 30MHz

50-mV_PPSignal Superimposed on AVDD

±20

±40

±60

±80

±100

±120

0

30

60

90

120 150 180 210 240 270 300

0

16

32

48

64

80

Test Signal Frequency On Supply (MHz)

C043

Frequency (MHz)

C042

f_S= 160 MSPS, f_PSRR= 5 MHz, 50 mV_PP, f_IN= 30 MHz, Amplitude

(f_IN+ f_PSRR) = –65 dBFS, Amplitude (f_IN– f_PSRR) = –67 dBFS

Figure 136. PSRR vs Test Signal Frequency

Figure 135. PSRR FFT for AVDD Supply

500

400

350

300

250

200

150

100

50

Analog Power

Digital Power

Analog Power

Digital Power

Total Power

450

Total Power

400

350

300

250

200

150

100

50

0

20

40

60

80

100

120

140

160

10

20

30

40

50

60

70

80

Sampling Speed (MSPS)

D005

D010

Figure 137. Power vs Sampling Frequency 20X Mode

Figure 138. Power vs Sampling Frequency 40X Mode

42

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

7.19 Typical Characteristics: Contour Plots

Typical values are at T_A= 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-V_PPfull-scale, and

32k-point FFT, unless otherwise noted.

160

140

120

100

80

160

140

120

100

80

85

76

84

80

85

80

75

90

88

92

72

65

70

95

92

88

90

92

75

70

84 80

76

80

85

72

95

65

92

88

60

90

65

92

80

84

72

75

80

76

85

70

95

50

100

150

200

250

300

350

400

450

95

50

100

150

200

250

300

350

400

450

Input Frequency, MHz

60

65

70

75

80

85

90

70

75

80

85

90

Figure 139. Spurious-Free Dynamic Range (SFDR) for

0-dB Gain

Figure 140. Spurious-Free Dynamic Range (SFDR) for

6-dB Gain

160

140

120

100

80

160

140

120

100

80

64.2

64

71.5

72

67

65.8

71

63.4

65

70.5

66.6

68

66.2

65

70

69

67

66

72.5

64.2

68

67

65

71.5

71

70.5

65.8

70

66.2

65.8

66.6

67

69

72

66

60

72

71.5

70.5

70

66.6

66.2

67

68

71

69

65

50

100

150

200

250

300

350

400

450

50

100

150

200

250

300

350

400

450

Input Frequency, MHz

64

65

66

67

68

69

70

71

72

62.5

63

63.5

64

64.5

65

65.5

66

66.5

67

Figure 141. Signal-to-Noise Ratio (SNR) for

0-dB Gain

Figure 142. Signal-to-Noise Ratio (SNR) for

6-dB Gain

43

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8 Parameter Measurement Information

8.1 Timing Diagrams

N + Latency + 2

N + 4

N + 3

N + Latency + 1

N + Latency

N + 2

Sample

N

N + 1

t_A

CLKP

CLKM

Input

Clock

ADC Latency⁽¹⁾

t_D

DxP, DxM⁽²⁾

N - Latency-1

N + Latency

N - Latency+1 N - Latency+2 N - Latency+3

N - 1

N

N + 1

(1) Overall latency = ADC latency + t_D.

(2) x = A for channel A and B for channel B.

Figure 143. ADC Latency

CLKINP

CLKINM

Input

Clock

t_{SU_SYNC~}

t_{H_SYNC~}

SYNC~

t_D

SYNC~ Asserted Latency

CGS Phase

DxP, DxM⁽¹⁾

Data

K28.5

(1) x = A for channel A and B for channel B.

Figure 144. SYNC~ Latency in CGS Phase

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Timing Diagrams (continued)

CLKINP

Input

Clock

CLKINM

t_{SU_SYNC~}

t_{H_SYNC~}

SYNC~

t_D

SYNC~ Deasserted Latency

ILA Sequence

DxP, DxM⁽¹⁾

K28.5

K28.0

(1) x = A for channel A and B for channel B.

Figure 145. SYNC~ Latency in ILAS Phase

Sample N

t_{SU_SYSREF}

t_{SU_SYNC~}

t_{H_SYSREF}

t_{H_SYNC~}

CLKIN

SYSREF

SYNC~

Figure 146. SYSREF Timing (Subclass 1)

Figure 147. SYNC~ Timing (Subclass 2)

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9 Detailed Description

9.1 Overview

The ADC32J4x are a high-linearity, ultra-low power, dual-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-

digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency

signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock

architecture design ans the SYSREF input enables complete system synchronization. The ADC32J4x family

supports JESD204B interface in order to reduce the number of interface lines, thus allowing for high system

integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and

output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling

clock by 20 to derive the bit clock, which is used to serialize the 14-bit data from each channel. The ADC32J4x

devices support subclass 0, 1, and 2 with interface data rates up to 3.2 Gbps.

9.2 Functional Block Diagram

DAP,

DAM

Digital Encoder

INAP,

INAM

14-Bit

ADC

and

JESD204B

OVRA

PLL

CLKP,

CLKM

Divide by

1,2,4

SYNCP,

SYNCM

SYSREFP,

SYSREFM

DBP,

DBM

Digital Encoder

and

JESD204B

INBP,

INBM

14-Bit

ADC

OVRD

Common

Mode

VCM

Configuration Registers

9.3 Feature Description

9.3.1 Analog Inputs

The ADC32J4x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must

swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP(default) differential input

swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving a 50-Ω

termination between INP and INM).

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Feature Description (continued)

9.3.2 Clock Input

The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V

using internal 5-kΩ resistors. The self-bias clock inputs of the ADC32J4x can be driven by the transformer-

coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in

Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.

0.1 mF

Z_o

CLKP

Differential

Sine-Wave

Clock Input

R_T

Typical LVDS

Clock Input

100 W

0.1 mF

CLKM

Device

0.1 mF

Z_o

CLKM

NOTE: R_T= termination resistor, if necessary.

Device

Figure 148. Differential Sine-Wave Clock Driving

Circuit

Figure 149. LVDS Clock Driving Circuit

0.1 mF

Z_o

CLKP

150 W

Typical LVPECL

Clock Input

100 W

0.1 mF

Z_o

CLKM

Device

150 W

Figure 150. LVPECL Clock Driving Circuit

Clock Buffer

L_PKG

2 nH

20 W

CLKP

C_BOND

1 pF

C_EQ

5 kW

R_ESR

100 W

1.4 V

L_PKG

2 nH

5 kW

20 W

CLKM

C_BOND

1 pF

R_ESR

100 W

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 151. Internal Clock Buffer

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A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF

capacitor, as shown in Figure 152. However, the clock inputs must be driven differentially for best performance,

thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using

a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.

There is no change in performance with a non-50% duty cycle clock input.

0.1 mF

CMOS

Clock Input

CLKP

0.1 mF

CLKM

Device

Figure 152. Single-Ended Clock Driving Circuit

9.3.2.1 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors: quantization noise, thermal noise, and

jitter noise, as shown in Equation 1. Quantization noise is typically not noticeable in pipeline converters and is

86 dB for a 14-bit ADC. Thermal noise limits SNR at low input frequencies and the clock jitter sets SNR for

higher input frequencies.

2

SNR_Quantizatoin

SNR

Jitter

Noise

§

·

¸

Thermal Noise

§

·

¸

§

·

¸

ꢁ

¨

20

¨

SNR_ADC[dBc] ꢁ20log 10

ꢀ 10

¨

©

¸

¹

¨

©

¸

¨

©

¸

¹

(1)

(2)

The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:

SNR_Jitter[dBc] ꢀ20log(2S f_inT_Jitter)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (200 fs for the device), is set by the

noise of the clock input buffer, and the external clock. T_Jittercan be calculated with Equation 3:

2

T_Jitter (T_{Jitter,Ext.Clock _ Input})²ꢀ(T_{Aperture_ ADC}

)

(3)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input, although a faster clock slew rate improves ADC aperture jitter. The devices have a

thermal noise of 73.5 dBFS and an internal aperture jitter of 200 fs. The SNR, depending on the amount of

external jitter for different input frequencies, is shown in Figure 153.

73

72

71

70

69

68

67

66

65

Ext Clock Jitter

35 fs

50 fs

100 fs

150 fs

200 fs

10

100

1000

Input Frequency (MHz)

D036

Figure 153. SNR vs Frequency and Jitter

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9.3.2.2 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster

input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1)

for operation with a 160-MHz clock; the divide-by-2 option supports a maximum input clock of 320 MHz and the

divide-by-4 option supports a maximum input clock frequency of 640 MHz.

9.3.3 Power-Down Control

The power-down functions of the ADC32J4x can be controlled either through the parallel control pin (PDN) or

through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-

down or standby functionality, as shown in Table 2.

Table 2. Power-Down Modes

FUNCTION

Global power-down

Standby

POWER CONSUMPTION (mW)

WAKE-UP TIME (µs)

5

85

35

118

9.3.4 Internal Dither Algorithm

The ADC32J4x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the

dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither

algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect

of using dither algorithms.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

16

32

48

64

80

0

16

32

48

64

80

Frequency (MHz)

D103

D104

f_S= 160 MSPS, SNR = 72 dBFS, f_IN= 70 MHz, SFDR = 95 dBc

f_S= 160 MSPS, SNR = 72.5 dBFS, f_IN= 70 MHz,

SFDR = 85 dBc

Figure 155. FFT with Dither Off

Figure 154. FFT with Dither On

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9.3.5 JESD204B Interface

The ADC32J4x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial

transmitter, as shown in Figure 156. The data of each ADC are serialized by 20X using an internal PLL and then

transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC~ (subclass 2) signal is

used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This

process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.

SYSREF SYNC~

JESD

204B

INA

INB

DA

DB

JESD

204B

Sample

Clock

Figure 156. JESD204B Interface

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown

in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and

determines if the ADC output data or test patterns are transmitted. The link layer performs the 8b or 10b data

encoding and the synchronization and initial lane alignment using the SYNC~ input signal. Optionally, data from

the transport layer can be scrambled.

JESD204B Block

Transport Layer

Link Layer

Frame Data

Mapping

8b, 10b

Encoding

ADC

Scrambler

1+x¹⁴+x¹⁵

DA

DB

Comma Characters

Initial Lane Alignment

Test Patterns

SYNC

Figure 157. JESD204B Block

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9.3.5.1 JESD204B Initial Lane Alignment (ILA)

The initial lane alignment process is started by the receiving device by asserting the SYNC~ signal. When a logic

high is detected on the SYNC~ input pins, the ADC32J4x starts transmitting comma (K28.5) characters to

establish code group synchronization. When synchronization is complete, the receiving device de-asserts the

SYNC~ signal and the ADC32J4x starts the initial lane alignment sequence with the next local multiframe clock

boundary. The ADC32J4x transmits four multiframes, each containing K frames (K is SPI programmable). Each

multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link

configuration data.

9.3.5.2 JESD204B Test Patterns

There are three different test patterns available in the transport layer of the JESD204B interface. The ADC32J4x

supports a clock output, an encoded, and a PRBS (2¹⁵– 1) pattern. These patterns can be enabled via SPI

register writes and are located in address 26h (bits 7-6).

9.3.5.3 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

•

L is the number of lanes per link,

M is the number of converters per device,

F is the number of octets per frame clock period, and

S is the number of samples per frame.

Table 3 lists the available JESD204B format and valid range for the ADC32J4x. The ranges are limited by the

SERDES line rate and the maximum ADC sample frequency.

Table 3. LMFS Values and Interface Rate

MINIMUM ADC

SAMPLING RATE

(MSPS)

MAXIMUM ADC

SAMPLING RATE

(Msps)

MAXIMUM

f_SERDES(Mbps)

MAXIMUM

f_SERDES(GSPS)

L

2

1

M

2

F

2

4

S

1

MODE

20X (default)

40X

15

10

300

400

160

80

3.2

2

The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration

can be changed from 20X (default) to 40X by setting the registers listed in Table 4.

LMFS = 2221

LMFS = 1241

Lane DA

Lane DB

Figure 158. JESD Frame Assembly

Table 4. Configuring 40X Mode

ADDRESS

2Bh

DATA

01h

30h

11h

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9.3.5.4 Digital Outputs

The ADC32J4x JESD204B transmitter uses differential CML output drivers. The CML output current is

programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential

100-Ω load impedance and the termination resistors must be placed as close to the receiver inputs as possible to

avoid unwanted reflections and signal distortion. Because the JESD204B employs 8b and 10b encoding, the

output data stream is dc-balanced and ac-coupling can be used to avoid the need to match up common-mode

voltages between the transmitter and receivers. Connect the termination resistors to the termination voltage, as

shown in Figure 159.

V_term

R_t= Z_O

Transmission Line, Zo

0.1 PF

DAP, DBP

DAM, DBM

Receiver

0.1 PF

Figure 159. CML Output Connections

Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B

transmitter mask at 3.125 Gbps (156.25 MSPS, 20X mode), respectively.

300

150

0

-150

-300

-200

-150

-100

-50

0

50

100

150

200

Time (ps)

Figure 160. Eye Diagram: 3.125 Gbps

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9.4 Device Functional Modes

9.4.1 Digital Gain

The input full-scale amplitude can be selected between 1 V_PPto 2 V_PP(default is 2 V_PP) by choosing the

appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for

SFDR performance. A larger input full-scale increases SNR performance (2 V_PPis recommended for maximum

SNR) and a reduced input swing typically results in better SFDR performance. Table 5 lists the available digital

gain settings.

Table 5. Digital Gain versus Full-Scale Amplitude

DIGITAL GAIN (dB)

MAX INPUT VOLTAGE (V_PP)

0

0.5

1

2

1.89

1.78

1.68

1.59

1.50

1.42

1.34

1.26

1.19

1.12

1.06

1.00

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

9.4.2 Overrange Indication

The ADC32J4x provides two different overrange indications. The normal OVR (default) is triggered if the final 14-

bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the

programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction

to an overrange event. By default, the normal overrange indication is output on the OVRA, OVRB pins. The fast

OVR indication can be presented on the overrange pins instead by using the SPI register map.

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9.5 Programming

The ADC32J4x can be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at

every SCLK rising edge when SEN is active (low). Serial data are loaded into the register at every 24th SCLK

rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored.

Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with

SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50% SCLK duty

cycle.

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial

interface registers can be cleared during operation either:

1. Through a hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register can be programmed with these steps:

1. Drive the SEN pin low,

2. Set the R/W bit to 0 (bit A15 of the 16-bit address),

3. Set bit A14 in the address field to 1,

4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be

written, and

5. Write the 8-bit data that are latched in on the SCLK rising edge.

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Programming (continued)

Figure 161 and Table 6 show the timing requirements for the serial register write operation.

Register Address [13:0]

A13 A12 A11 A1

Register Data [7:0]

SDATA

R/W

= 0

1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 161. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

MIN

> dc

25

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIO setup time

)

20

25

ns

25

ns

t_DH

SDIO hold time

25

ns

(1) Typical values are at 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, and AVDD = DVDD = 1.8 V, unless otherwise

noted.

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9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.

This readback mode can be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. To read the contents of serial registers, follow this procedure:

1. Drive the SEN pin low.

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.

3. Set bit A14 in the address field to 1.

4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.

5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.

6. The external controller can latch the contents at the SCLK rising edge.

7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the

SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on

the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 163.

Register Address [13:0]

A13 A12 A11 A1

Register Data: 'RQ¶Wꢀ&DUH

D5 D4 D3 D2

SDATA

R/W

= 1

A0

D7

D6

D1

D0

1

Register Read Data [7:0]

SDOUT

SCLK

D5

D4

D3

D2

SEN

Figure 162. Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

Figure 163. SDOUT Timing Diagram

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9.5.2 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in Figure 164 and Table 7.

Power

Supplies

t₁

RESET

t₂

t₃

SEN

Figure 164. Initialization of Serial Registers after Power-Up

Table 7. Power-Up Timing

MIN

1

TYP

MAX

UNIT

ms

ns

t₁

t₂

t₃

Power-on delay from power-up to an active high RESET pulse

Reset pulse duration: active high RESET pulse duration

Register write delay from RESET disable to SEN active

10

1000

100

ns

If required, the serial interface registers can be cleared during operation either:

1. Through hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

9.5.3 Start-Up Sequence

After power-up, the sequence described in Table 8 can be used to set up the ADC32J4x for basic operation.

Table 8. Start-Up Settings

STEP

DESCRIPTION

REGISTER ADDRESS AND DATA

Provide all supply voltages. There is no required power-supply sequence for

AVDD and DVDD.

1

2

3

4

—

Pulse a hardware reset (low to high to low) on pin 24

Optionally, configure LMFS of the JESD204B interface to LMFS = 1241

(default is LMFS = 2221)

Address 2Bh, data 01h

Address 30h, data 11h

Pulse SYNC~ from high to low to transmit data from K28.5 SYNC~ mode

—

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9.6.1 Summary of Special Mode Registers

Table 10 lists the location, value, and functions of special mode registers in the device.

Table 10. Special Modes Summary

MODE

LOCATION

VALUE AND FUNCTION

DIS DITH CHA

01h (bits 5-4), 434h (bits 5, 3)

Creates a noise floor cleaner and improves SFDR;

see the Internal Dither Algorithm section.

0000 = Dither disabled

Dither mode

DIS DITH CHB

01h (bits 3-2), 534h (bits 5, 3)

07h (bits 4-2)

1111 = Dither enabled

SPECIAL MODE 1 CHA

SPECIAL MODE 1 CHB

Use for improved HD3.

000 = Default after reset

010 = Use for frequency < 120 MHz

111 = Use for frequency > 120 MHz

Special mode 1

Special mode 2

08h (bits 4-2)

SPECIAL MODE 2 CHA

SPECIAL MODE 2 CHB

422h (bits 1-0)

522h (bits 1-0)

Helps improve HD2.

00 = Default after reset

11 = Improves HD2

9.6.2 Serial Register Descriptions

9.6.2.1 Register 01h (address = 01h)

Figure 165. Register 01h

7

0

6

0

5

4

3

2

1

0

DIS DITHER CHA

R/W-0h

DIS DITHER CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 11. Register 01h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0.

These bits enable or disable the on-chip dither. Control these

bits with bits 5 and 3 of register 434h.

00 = Dither enabled

5-4

DIS DITHER CHA

R/W

0h

11 = Dither disabled. Improves SNR by 0.4 dB for input

frequencies up to 170 MHz.

These bits enable or disable the on-chip dither. Control these

bits with bits 5 and 3 of register 534h.

00 = Dither enabled

11 = Dither disabled. Improves SNR by 0.4 dB for input

frequencies up to 170 MHz.

3-2

1-0

DIS DITHER CHB

0

R/W

W

0h

Must write 0.

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9.6.2.2 Register 03h (address = 03h)

Figure 166. Register 03h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

CHA GAINEN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 12. Register 03h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0.

Digital gain enable bit for channel A.

0 = Digital gain disabled

1 = Digital gain enabled

1

0

CHA GAINEN

0

R/W

W

0h

Must write 0.

9.6.2.3 Register 04h (address = 04h)

Figure 167. Register 04h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

CHB GAINEN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 13. Register 04h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0.

Digital gain enable bit for channel B.

0 = Digital gain disabled

1 = Digital gain enabled

1

0

CHB GAINEN

0

R/W

W

0h

Must write 0.

9.6.2.4 Register 06h (address = 06h)

Figure 168. Register 06h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TEST

PATTERN EN

RESET

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 14. Register 06h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0.

This bit enables the test pattern selection for the digital outputs.

0 = Normal operation

1 = Test pattern output enabled

1

0

TEST PATTERN EN

RESET

R/W

0h

Software reset applied.

This bit resets all internal registers to the default values and self-

clears to 0.

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9.6.2.5 Register 07h (address = 07h)

Figure 169. Register 07h

7

0

6

0

5

0

4

3

2

1

0

SPECIAL MODE1 CHA

R/W-0h

EN FOVR

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 15. Register 07h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

0

W

0h

Must write 0.

010 = For frequencies < 120 MHz

111 = For frequencies > 120 MHz

4-2

SPECIAL MODE1 CHA

R/W

0h

0 = Normal OVR on OVRx pins

1 = Enable fast OVR on OVRx pins

1

0

EN FOVR

0

R/W

W

0h

Must write 0.

9.6.2.6 Register 08h (address = 08h)

Figure 170. Register 08h

7

0

6

0

5

0

4

3

2

1

0

SPECIAL MODE1 CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 16. Register 08h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

0

W

0h

Must write 0.

010 = For frequencies < 120 MHz

111 = For frequencies > 120 MHz

4-2

1-0

SPECIAL MODE1 CHB

0

R/W

W

0h

Must write 0.

9.6.2.7 Register 09h (address = 09h)

Figure 171. Register 09h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ALIGN TEST

PATTERN

DATA

FORMAT

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 17. Register 09h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0.

This bit aligns test patterns across the outputs of the four

channels.

0 = Test patterns of four channels are free-running

1 = Test patterns of all four channels are aligned

1

0

ALIGN TEST PATTERN

DATA FORMAT

R/W

0h

This bit sets the digital output data format.

0 = Twos complement

1 = Offset binary

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9.6.2.8 Register 0Ah (address = 0Ah)

Figure 172. Register 0Ah

7

0

6

0

5

0

4

0

3

2

1

0

CHA TEST PATTERN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 18. Register 0Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-4

0

W

0h

Must write 0.

These bits control the test pattern for channel A after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101.

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383.

3-0

CHA TEST PATTERN

R/W

0h

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits.

0110 = Deskew pattern: data are 3AAAh.

1000 = PRBS pattern: data are a sequence of pseudo random

numbers.

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, and 2399.

Others = Do not use

9.6.2.9 Register 0Bh (address = 0Bh)

Figure 173. Register 0Bh

7

6

5

4

3

0

2

0

1

0

CHB TEST PATTERN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 19. Register 0Bh Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

W

Reset

Description

These bits control the test pattern for channel B after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101.

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383.

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits.

0110 = Deskew pattern: data are 3AAAh.

1000 = PRBS pattern: data are a sequence of pseudo random

numbers.

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, and 2399.

Others = Do not use

CHB TEST PATTERN

0h

0

0h

Must write 0.

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9.6.2.10 Register 0Ch (address = 0Ch)

Figure 174. Register 0Ch

7

0

6

0

5

0

4

0

3

2

1

0

CHA DIGITAL GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 20. Register 0Ch Field Descriptions

Bit

Field

Type

Reset

Description

7-4

0

W

0h

Must write 0.

These bits set the digital gain for individual channels. Register

settings are listed in Table 21.

3-0

CHA DIGITAL GAIN

R/W

0h

Table 21. Channel Digital Gain

REGISTER VALUE

0000

DIGITAL GAIN (dB)

MAXIMUM INPUT VOLTAGE (V_PP)

0

0.5

1

2.0

0001

1.89

1.78

1.68

1.59

1.50

1.42

1.34

1.26

1.19

1.12

1.06

1.00

0010

0011

1.5

2

0100

0101

2.5

3

0110

0111

3.5

4

1000

1001

4.5

5

1010

1011

5.5

6

1100

9.6.2.11 Register 0Dh (address = 0Dh)

Figure 175. Register 0Dh

7

6

5

4

3

0

2

0

1

0

CHB DIGITAL GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 22. Register 0Dh Field Descriptions

Bit

7-4

3-0

Field

Type

R/W

W

Reset

Description

These bits set the digital gain for the individual channels.

Register settings are listed in Table 21.

CHB DIGITAL GAIN

0

0h

Must write 0.

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9.6.2.12 Register 0Eh (address = 0Eh)

Figure 176. Register 0Eh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[13:6]

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 23. Register 0Eh Field Descriptions

Bit

Field

Type

Reset

Description

These bits set the custom pattern[13:6] for all channels.

7-0

CUSTOM PATTERN[13:6]

R/W

0h

9.6.2.13 Register 0Fh (address = 0Fh)

Figure 177. Register 0Fh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[5:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 24. Register 0Fh Field Descriptions

Bit

7-2

1-0

Field

Type

R/W

W

Reset

0h

Description

CUSTOM PATTERN[5:0]

0

These bits set the custom pattern[5:0] for all channels.

Must write 0.

0h

9.6.2.14 Register 13h (address = 13h)

Figure 178. Register 13h

7

6

0

5

0

4

0

3

0

2

0

1

0

LOW SPEED MODE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 25. Register 13h Field Descriptions

Bit

7

Field

Type

R/W

W

Reset

Description

Use this bit for sampling frequencies < 25 MSPS.

0 = Normal operation

1 = Low-speed mode is enabled

LOW SPEED MODE

0

0h

6-0

0h

Must write 0.

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9.6.2.15 Register 15h (address = 15h)

Figure 179. Register 15h

7

0

6

5

4

0

3

2

1

0

GLOBAL

PDN

PDN PIN

DISABLE

CHA PDN

R/W-0h

CHB PDN

R/W-0h

STANDBY

R/W-0h

W-0h

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 26. Register 15h Field Descriptions

Bit

Field

Type

Reset

Description

7

0

W

0h

Must write 0.

Power-down channel A.

0 = Normal operation

1 = Power-down channel A if the PDN PIN DISABLE register bit

is set

6

5

CHA PDN

CHB PDN

R/W

0h

Power-down channel B.

0 = Normal operation

1 = Power-down channel B if the PDN PIN DISABLE register bit

is set

4

3

0

W

0h

Must write 0.

ADCs of both channels enter standby.

0 = Normal operation

STANDBY

R/W

1 = Standby

Global power-down.

0 = Normal operation

1 = Global power-down

2

1

GLOBAL PDN

0

R/W

W

0h

Must write 0.

This bit disables the power-down control from the pin.

0 = Normal operation

1 = Power-down pin is disabled; use register settings for power-

down operations

0

PDN PINDISABLE

R/W

0h

9.6.2.16 Register 27h (address = 27h)

Figure 180. Register 27h

7

6

5

0

4

0

3

0

2

0

1

0

CLK DIV

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 27. Register 27h Field Descriptions

Bit

7-6

5-0

Field

CLK DIV

0

Type

R/W

W

Reset

Description

Internal clock divider for the input sample clock.

00 = Clock divider bypassed

01 = Divide-by-1

10 = Divide-by-2

11 = Divide-by-4

0h

Must write 0.

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9.6.2.17 Register 2Ah (address = 2Ah)

Figure 181. Register 2Ah

7

6

5

4

3

2

1

0

TRP LAYER

TESTMODE

EN

TX LINK

FRAME ALIGN CONFIG DATA

DIS

FLIP ADC

DATA

SERDES TEST PATTERN

R/W-0h

IDLE SYNC

R/W-0h

LANE ALIGN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after

Table 28. Register 2Ah Field Descriptions

Bit

Field

Type

Reset

Description

00 = Normal operation

01 = Outputs clock pattern: output is 10101010

10 = Encoded pattern: output is 1111111100000000

11 = PRBS sequence: output is 2¹⁵– 1

7-6

SERDES TEST PATTERN

R/W

0h

This bit sets the output pattern when SYNC~ is high.

0 = Sync code is K28.5 (BCBCh)

5

IDLE SYNC

R/W

0h

1 = Sync code is BC50h

This bit generates the long transport layer test pattern mode

according to section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

4

3

TRP LAYER TESTMODE EN

FLIP ADC DATA

R/W

0h

1 = Test mode enabled

0 = Normal operation

1 = Output data order is reversed: MSB – LSB

This bit inserts a lane alignment character (K28.3) for the

receiver to align to the lane boundary per section 5.3.3.5 of the

JESD204B specification.

2

LANE ALIGN

R/W

0h

0 = Normal operation

1 = Inserts lane alignment characters

This bit inserts a frame alignment character (K28.7) for the

receiver to align to the lane boundary per section 5.3.3.4 of the

JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

1

0

FRAME ALIGN

R/W

0h

This bit disables sending the initial link alignment (ILA) sequence

when SYNC~ is de-asserted.

0 = Normal operation

TX LINK CONFIG DATA DIS

1 = ILA disabled

9.6.2.18 Register 2Bh (address = 2Bh)

Figure 182. Register 2Bh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

CTRL K

R/W-0h

CTRL F

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 29. Register 2Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-2

0

W

0h

Must write 0.

Enable bit for the number of frames per multiframe.

0 = Default is 9 (20X mode) frames per multiframe

1 = Frames per multiframe can be set in register 31h

1

0

CTRL K

CTRL F

R/W

0h

Enable bit for the number of octets per frame.

0 = 20X mode using one lane per ADC (default is F = 2)

1 = Octets per frame can be specified in register 30h

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9.6.2.19 Register 2Fh (address = 2Fh)

Figure 183. Register 2Fh

7

6

0

5

0

4

0

3

0

2

0

1

0

SCRAMBLE EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 30. Register 2Fh Field Descriptions

Bit

7

Field

Type

R/W

W

Reset

Description

Scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

1 = Scrambling enabled

SCRAMBLE EN

0

0h

6-0

0h

Must write 0.

9.6.2.20 Register 30h (address = 30h)

Figure 184. Register 30h

7

6

5

4

3

2

1

0

OCTETS PER FRAME

R/W-0h

LEGEND: R/W = Read/Write; -n = value after

Table 31. Register 30h Field Descriptions

Bit

Field

Type

Reset

Description

These bits set the number of octets per frame (F).

01 = 20X serialization: two octets per frame

11 = 40X serialization: four octets per frame

7-0

OCTETS PER FRAME

R/W

0h

9.6.2.21 Register 31h (address = 31h)

Figure 185. Register 31h

7

0

6

0

5

0

4

3

2

1

0

FRAMES PER MULTI FRAME

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 32. Register 31h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

0

W

0h

Must write 0.

These bits set the number of frames per multiframe.

After reset, the default settings for frames per multiframe are:

20X mode: K = 8

4-0

FRAMES PER MULTI FRAME

R/W

0h

For each mode, K must not be set to a lower value.

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9.6.2.22 Register 34h (address = 34h)

Figure 186. Register 34h

7

6

5

4

0

3

0

2

0

1

0

SUBCLASSV

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 33. Register 34h Field Descriptions

Bit

7-5

4-0

Field

Type

R/W

W

Reset

Description

JESD204B subclass setting.

000 = Subclass 0 backward compatibility with JESD204A

001 = Subclass 1 deterministic latency using the SYSREF signal

010 = Subclass 2 deterministic latency using SYNC~ detection

SUBCLASSV

0

0h

Must write 0.

9.6.2.23 Register 3Ah (address = 3Ah)

Figure 187. Register 3Ah

7

6

5

0

4

0

3

2

1

0

SYNC REQ

R/W-0h

SYNC REQ EN

R/W-0h

OUTPUT CURRENT SEL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 34. Register 3Ah Field Descriptions

Bit

Field

Type

Reset

Description

This bit generates a synchronization request only when the

SYNC REQ EN register bit is set.

0 = Normal operation

7

SYNC REQ

R/W

0h

1 = Generates sync request

0 = Sync request is made with the SYNCP~, SYNCM~ pins

1 = Sync request is made with the SYNC REQ register bit

6

SYNC REQ EN

0

R/W

W

0h

5-4

Must write 0.

JESD output buffer current selection.

0000 = 16 mA

0001 = 15 mA

0010 = 14 mA

0011 = 13 mA

0100 = 20 mA

0101 = 19 mA

0110 = 18 mA

0111 = 17 mA

1000 = 8 mA

3-0

OUTPUT CURRENT SEL

R/W

0h

1001 = 7 mA

1010 = 6 mA

1011 = 5 mA

1100 = 12 mA

1101 = 11 mA

1110 = 10 mA

1111 = 9 mA

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9.6.2.24 Register 3Bh (address = 3Bh)

Figure 188. Register 3Bh

7

6

5

4

3

0

2

1

0

LINK LAYER

RPAT

LINK LAYER TESTMODE

R/W-0h

PULSE DET MODES

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 35. Register 3Bh Field Descriptions

Bit

Field

Type

Reset

Description

These bits generate a pattern according to section 5.3.3.8.2 of

the JESD204B specification.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and continuously repeats lane alignment sequences)

100 = 12 octet RPAT jitter pattern

7-5

LINK LAYER TESTMODE

R/W

0h

This bit changes the running disparity in the modified RPAT

pattern test mode (only when link layer test mode = 100).

0 = Normal operation

4

LINK LAYER RPAT

R/W

0h

1 = Changes disparity

3

0

W

0h

Must write 0.

These bits select different detection modes for SYSREF

(subclass 1) and SYNC~ (subclass2). Register settings are

listed in Table 36.

2-0

PULSE DET MODES

R/W

Table 36. PULSE DET MODES Register Settings

D2

0

D1

D0

0

FUNCTIONALITY

Don’t care

Allow all pulses to reset input clock dividers

1

0

Do not allow reset of analog clock dividers

Don’t care

0 to 1 transition

1

Allow one pulse immediately after the 0 to 1 transition to reset the divider

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9.6.2.25 Register 3Ch (address = 3Ch)

Figure 189. Register 3Ch

7

6

5

4

3

2

1

0

FORCE LMFC

COUNT

LMFC COUNT INIT

R/W-0h

RELEASE ILAN SEQ

R/W-0h

LEGEND: R/W = Read/Write; -n = value after

Table 37. Register 3Ch Field Descriptions

Bit

Field

Type

Reset

Description

0 = Normal operation

7

FORCE LMFC COUNT

R/W

0h

1 = Enables using a different starting value for the LMFC

counter

If SYSREF is transmitted to the digital block, the LMFC count

resets to 0 and K28.5 stops transmitting when the LMFC count

reaches 31. The initial value that the LMFC count resets to can

be set using LMFC COUNT INIT. In this manner, the Rx can be

synchronized early because the Rx receives the LANE

ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT

register bit must be enabled.

6-2

1-0

LMFC COUNT INIT

RELEASE ILAN SEQ

R/W

0h

These bits delay the lane alignment sequence generation by 0,

1, 2, or 3 multiframes after the code group synchronization.

00 = 0

01 = 1

10 = 2

11 = 3

9.6.2.26 Register 422h (address = 422h)

Figure 190. Register 422h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

SPECIAL MODE2 CHA

W-1h

W-0h

LEGEND: W = Write only; -n = value after

Table 38. Register 422h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

SPECIAL MODE2 CHA

0

W

1h

Always write 1 for improved HD2 performance.

Must write 0.

0

W

0h

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9.6.2.27 Register 434h (address = 434h)

Figure 191. Register 434h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 39. Register 434h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0.

Set this bit along with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

5

4

DIS DITH CHA

R/W

W

0h

0

Must write 0.

Set this bit along with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

3

DIS DITH CHA

0

R/W

W

2-0

Must write 0.

9.6.2.28 Register 522h (address = 522h)

Figure 192. Register 522h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

SPECIAL MODE2 CHB

W-1h

W-0h

LEGEND: W = Write only; -n = value after

Table 40. Register 522h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

SPECIAL MODE2 CHB

0

W

1h

Always write 1 for better HD2 performance.

Must write 0.

0

W

0h

71

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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9.6.2.29 Register 534h (address = 534h)

Figure 193. Register 534

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHB

R/W-0h

DIS DITH CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after

Table 41. Register 534 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

0

W

0h

Must write 0.

Set this bit along with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

5

4

DIS DITH CHB

R/W

W

0h

0

Must write 0.

Set this bit along with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

3

DIS DITH CHB

0

R/W

W

2-0

Must write 0.

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as

ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC

inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 194 and

Figure 195 show the impedance (Z_in= R_in|| C_in) across the ADC input pins.

10

6

5

4

3

2

1

0.1

0.01

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D024

D025

Figure 194. Differential Input Resistance, R_in

Figure 195. Differential Input Capacitance, C_in

72

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

39 nH

0.1 PF

INP

0.1 PF

50

25

0.1 PF

22 pF

50

INM

1:1

0.1 PF

39 nH

VCM

Device

Figure 196. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in

series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may

have to be designed to minimize the affect of kick-back noise generated by sampling switches opening and

closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched

impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application using two back-to-back coupled transformers is illustrated in Figure 196. The circuit is

optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used.

With the series inductor (39 nH), this combination helps absorb the sampling glitches.

10.2.1.3 Application Curves

Figure 197 shows the performance obtained by using the circuit illustrated in Figure 196.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

16

32

48

64

80

Frequency (MHz)

D101

f_S= 160 MSPS, SNR = 72.4 dBFS, f_IN= 10 MHz,

SFDR = 92.3 dBc

Figure 197. FFT for 10-MHz Input Signal (Dither On)

73

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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Typical Applications (continued)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

0.1 PF

10 ꢀ

INP

0.1 PF

15 ꢀ

25 ꢀ

0.1 PF

56 nH

10 pF

25 ꢀ

15 ꢀ

10 ꢀ

INM

1:1

0.1 PF

VCM

Device

Figure 198. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN< 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize

performance, as shown in Figure 198.

10.2.2.3 Application Curve

Figure 199 shows the performance obtained by using the circuit shown in Figure 198.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

16

32

48

64

80

Frequency (MHz)

D105

f_S= 160 MSPS, SNR = 70.6 dBFS, f_IN= 170 MHz,

SFDR = 94.4 dBc

Figure 199. FFT for 170-MHz Input Signal (Dither On)

74

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

Typical Applications (continued)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

0.1 PF

10

INP

25

0.1 PF

25

INM

1:1

10

0.1 PF

VCM

Device

Figure 200. Driving Circuit for High Input Frequencies (f_IN> 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant

improvement in performance. However, a series resistance of 10 Ω can be used, as shown in Figure 200.

10.2.3.3 Application Curve

Figure 201 shows the performance obtained by using the circuit shown in Figure 200.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

16

32

48

64

80

Frequency (MHz)

D109

f_S= 160 MSPS, SNR = 63.2 dBFS, f_IN= 450 MHz,

SFDR = 65.7 dBc

Figure 201. FFT for 450-MHz Input Signal (Dither On)

11 Power-Supply Recommendations

The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply

requirements during device power-up. AVDD and DVDD can power up in any order.

75

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ZHCSDU1A –MAY 2014–REVISED JUNE 2015

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12 Layout

12.1 Layout Guidelines

The ADC32J4x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram

of the EVM top layer is provided in Figure 202. Some important points to remember when laying out the board

are:

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions

as much as possible, as shown in the reference layout of Figure 202.

2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 202

as much as possible.

3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

output traces must not be kept parallel to the analog input traces because this configuration may result in

coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the

receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)]

must be matched in length to avoid skew among outputs.

4. At each power-supply pin (AVDD and DVDD), a 0.1-µF decoupling capacitor must be kept close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-

µF capacitors can be kept close to the supply source.

12.2 Layout Example

ADC3xJxx

Analog

Input

Routing

Sampling

Clock

Routing

Digital

Output

Routing

Clock

Distribution IC

Analog input

for CHB

Analog input

for CHA

Figure 202. Typical Layout of the ADC32J4x Board

76

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www.ti.com.cn

ZHCSDU1A –MAY 2014–REVISED JUNE 2015

13 器件和文档支持

13.1 相关链接

表 42 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买链

接。

表 42. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

ADC32J45

ADC32J44

ADC32J43

ADC32J42

13.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.3 商标

E2E is a trademark of Texas Instruments.

PowerPAD is a trademark of Texas Instruments, Inc.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

77

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC32J42IRGZR

ADC32J43IRGZR

ADC32J44IRGZR

ADC32J45IRGZR

VQFN

RGZ

48

2500

330.0

16.4

7.3

1.5

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC32J42IRGZR

ADC32J43IRGZR

ADC32J44IRGZR

ADC32J45IRGZR

VQFN

RGZ

48

2500

350.0

43.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048D

VQFN - 1 mm max height

S

C

A

L

E

1

.

9

0

PLASTIC QUAD FLATPACK - NO LEAD

7.1

6.9

A

B

0.5

0.3

PIN 1 INDEX AREA

7.1

6.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5.6 0.1

2X 5.5

(0.2) TYP

13

24

44X 0.5

12

25

EXPOSED

THERMAL PAD

2X

49

SYMM

5.5

SEE TERMINAL

DETAIL

1

36

0.30

48X

0.18

37

48

PIN 1 ID

(OPTIONAL)

SYMM

0.1

C A B

0.5

0.3

48X

0.05

4219046/B 11/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.6)

SYMM

48

37

48X (0.6)

1

36

48X (0.24)

6X

(1.22)

44X (0.5)

SYMM

10X

(1.33)

49

(6.8)

(R0.05)

TYP

(

0.2) TYP

VIA

25

12

13

24

10X (1.33)

6X (1.22)

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219046/B 11/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.665 TYP)

(1.33) TYP

16X ( 1.13)

37

48

48X (0.6)

49

36

1

48X (0.24)

44X (0.5)

(1.33)

TYP

(0.665)

TYP

SYMM

(6.8)

(R0.05) TYP

25

12

METAL

TYP

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:15X

4219046/B 11/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC32J44
厂家：	TEXAS INSTRUMENTS
描述：	双通道、14 位、125MSPS 模数转换器 (ADC) 转换器模数转换器
文件：	总86页 (文件大小：5262K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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