ADC32RF44 [TI]
双通道、14 位、2.6GSPS 射频采样模数转换器 (ADC);型号: | ADC32RF44 |
厂家: | TEXAS INSTRUMENTS |
描述: | 双通道、14 位、2.6GSPS 射频采样模数转换器 (ADC) 射频 转换器 模数转换器 |
文件: | 总135页 (文件大小:7544K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
ADC32RF44 双通道 14 位 2.6GSPS 模数转换器
1 特性
3 说明
1
•
•
•
•
•
•
14 位双通道 2.6GSPS ADC
ADC32RF44 器件是一款 14 位 2.6GSPS 双通道模数
转换器 (ADC),支持输入频率高达 4GHz 及以上的射
频采样。ADC32RF44 专为高信噪比 (SNR) 设计,其
噪声频谱密度为 –154.2dBFS/Hz,并可在较大输入频
率范围提供动态范围和通道隔离。经缓冲的模拟输入配
有片上端接电阻,可在较宽频率范围内提供统一输入阻
抗并最大程度地降低采样和保持毛刺脉冲能量。
本底噪声:–154.2dBFS/Hz
射频 (RF) 输入支持的频率最高可达 4.0GHz
孔径抖动:90fs
通道隔离:fIN = 1.8GHz 时为 95dB
频谱性能(fIN = 900MHz,–2dBFS):
–
–
–
SNR:61.2dBFS
SFDR:65dBc(HD2、HD3)
SFDR:79dBc(最严重毛刺)
每个 ADC 通道均可连接到一个双频带数字下变频器
(DDC),每个 DDC 最多连接三个独立的 16 位数控振
荡器 (NCO) 用于相位相干跳频。此外,ADC 还配有前
端峰值和 RMS 功率检测器及报警功能,用以支持外部
自动增益控制 (AGC) 算法。
•
•
频谱性能(fIN = 1.85GHz,–2dBFS):
–
–
–
SNR:58.3dBFS
SFDR:69dBc(HD2、HD3)
SFDR:74dBc(最严重毛刺)
ADC32RF44 支持具有基于子类 1 确定性延迟的
JESD204B 串行接口,其数据速率高达 12.5Gbps,每
个 ADC 最多具有四条信道。该器件采用 72 引脚
VQFN 封装 (10mm × 10mm),支持工业级温度范围
(-40℃ 至 +85°C)。
片上数字下变频器:
–
–
最多 4 个下变频器 (DDC)(双频带模式)
每个 DDC 最多配有 3 个独立数控振荡器
(NCO)
•
•
提供过压保护的片上输入钳位
器件信息(1)
带有报警引脚的可编程片上功率检测器,支持自动
增益控制 (AGC)
器件型号
封装
封装尺寸(标称值)
•
•
•
•
•
片上抖动
ADC32RF44
VQFN (72)
10.00mm x 10.00mm
片上输入端接电阻
输入满量程:1.35 VPP
支持多芯片同步
JESD204B 接口:
(1) 要了解所有可用封装,请参见数据表末尾的可订购产品附录。
简化框图
Digital Block
DA[1:0]P,
DA[1:0]M
–
–
基于子类 1 的确定性延迟
Buffer
N
N
ADC
65 ꢀ
Interleave
Correction
Power
INAP,
INAM
DA[3:2]P,
DA[3:2]M
12.5Gbps 时每条通道具有 4 条信道
Detection
NCO
•
•
功率耗散:2.6GSPS 时为 2.95W/通道
CM
FOVR
NCO
72 引脚超薄型四方扁平无引线 (VQFN) 封装
NCO
CTRL
GPIO[4:1]
(10mm × 10mm)
SYNCBP,
SYNCBM
CLKINP,
CLKINM
Clock
Divider
PLL
SYSREFP,
SYSREFM
2 应用
NCO
RESET
SCLK
SDATA
SEN
PDN
SDO
SPI
and
FOVR
NCO
•
•
•
•
•
•
•
•
•
多频带、多模式 2G、3G、4G 蜂窝接收器
Control
Digital Block
N
N
DB[1:0]P,
DB[1:0]M
Buffer
Interleave
Correction
Power
ADC
相控阵列雷达
电子对抗战
INBP,
INBM
DB[3:2]P,
DB[3:2]M
Detection
65 ꢀ
Copyright © 2017, Texas Instruments Incorporated
线缆基础设施
无线宽带
高速数字转换器
软件定义无线电
通信测试设备
微波和毫米波接收器
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS809
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
目录
9.1 Overview ................................................................. 22
9.2 Functional Block Diagram ....................................... 22
9.3 Feature Description................................................. 23
9.4 Device Functional Modes........................................ 50
9.5 Register Maps......................................................... 64
10 Application and Implementation...................... 115
10.1 Application Information........................................ 115
10.2 Typical Application .............................................. 122
11 Power Supply Recommendations ................... 124
12 Layout................................................................. 124
12.1 Layout Guidelines ............................................... 124
12.2 Layout Example .................................................. 125
13 器件和文档支持 ................................................... 126
13.1 文档支持.............................................................. 126
13.2 接收文档更新通知 ............................................... 126
13.3 社区资源.............................................................. 126
13.4 商标..................................................................... 126
13.5 静电放电警告....................................................... 126
13.6 Glossary.............................................................. 126
14 机械、封装和可订购信息..................................... 126
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 AC Performance Characteristics .............................. 7
7.7 Digital Requirements ................................................ 9
7.8 Timing Requirements.............................................. 10
7.9 Typical Characteristics............................................ 12
Parameter Measurement Information ................ 21
8.1 Input Clock Diagram ............................................... 21
Detailed Description ............................................ 22
8
9
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (February 2017) to Revision A
Page
•
•
Changed minimum specification of NSD parameter (fIN = 1850 MHz) from 146.6 to 146.1 .................................................. 7
Changed minimum specifications of HD3, HD4 and HD5, and IL spur parameters (fIN = 1850 MHz) from 63 to 62.5,
from 70 to 69.5, and from 68 to 66.5, respectively................................................................................................................. 8
2
Copyright © 2017, Texas Instruments Incorporated
ADC32RF44
www.ti.com.cn
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
5 Device Comparison Table
PART NUMBER
ADC32RF45
SPEED GRADE (MSPS)
RESOLUTION (Bits)
CHANNELS
3000
2600
14
14
2
2
ADC32RF44
6 Pin Configuration and Functions
RMP Package
72-Pin VQFN
Top View
DB3M
DB3P
GND
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
DA3M
DA3P
GND
2
3
DVDD
SDIN
4
DVDD
PDN
5
SCLK
SEN
6
GND
7
RESET
DVDD
AVDD
AVDD19
AVDD
AVDD
INAP
DVDD
AVDD
AVDD19
SDOUT
AVDD
INBP
8
9
Thermal
Pad
10
11
12
13
14
15
16
17
18
INBM
INAM
AVDD
AVDD19
AVDD
GND
AVDD
AVDD19
AVDD
GND
Not to scale
Copyright © 2017, Texas Instruments Incorporated
3
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
Pin Functions
NAME
NO.
I/O
DESCRIPTION
INPUT, REFERENCE
INAM
41
42
14
13
22
I
Differential analog input for channel A
Differential analog input for channel B
INAP
INBM
I
INBP
CM
O
Common-mode voltage for analog inputs, 1.2 V
CLOCK, SYNC
CLKINM
CLKINP
SYSREFM
SYSREFP
GPIO1
28
27
34
33
19
20
21
63
Differential clock input for the analog-to-digital converter (ADC).
This pin has an internal differential 100-Ω termination.
I
I
External sync input. This pin has an internal, differential 100-Ω termination and requires external
biasing.
GPIO control pin; configured through the SPI. This pin can be configured to be either a fast
overrange output for channel A and B, a fast detect alarm signal from the peak power detect, or
a numerically-controlled oscillator (NCO) control.
GPIO2
I/O
GPIO3
GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input.
GPIO4
CONTROL, SERIAL
RESET
48
6
I
I
Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.
Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor.
SCLK
Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN can be data
input in 4-wire mode, data input and output in 3-wire mode.
SDIN
5
I/O
SEN
7
I
Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD.
SDOUT
11
O
Serial interface data output in 4-wire mode
Power down; active high. This pin can be configured through an SPI register setting and can be
configured to a fast overrange output channel B through the SPI.
This pin has an internal 20-kΩ pulldown resistor.
PDN
50
I
DATA INTERFACE
DA0M
62
61
59
58
56
55
54
53
65
66
68
69
71
72
1
DA0P
DA1M
DA1P
O
JESD204B serial data output for channel A
DA2M
DA2P
DA3M
DA3P
DB0M
DB0P
DB1M
DB1P
O
JESD204B serial data output for channel B
DB2M
DB2P
DB3M
DB3P
2
SYNCBM
36
Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic input, an
optional on-chip 100-Ω termination, and is selectable through the SPI.
This pin requires external biasing.
I
SYNCBP
35
POWER SUPPLY
AVDD19
10, 16, 24, 31, 39, 45
I
I
I
I
Analog 1.9-V power supply
9, 12, 15, 17, 25, 30, 38,
40, 43, 44, 46
AVDD
DVDD
GND
Analog 1.15-V power supply
4, 8, 47, 51, 57, 64, 70
Digital 1.15 V-power supply, including the JESD204B transmitter
Ground; shorted to thermal pad inside device
3, 18, 23, 26, 29, 32, 37,
49, 52, 60, 67
4
Copyright © 2017, Texas Instruments Incorporated
ADC32RF44
www.ti.com.cn
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
2.1
UNIT
AVDD19
Supply voltage range
AVDD
1.4
V
DVDD
1.4
INAP, INAM and INBP, INBM
CLKINP, CLKINM
AVDD19 + 0.3
AVDD + 0.6
AVDD + 0.6
Voltage applied to input pins
V
SYSREFP, SYSREFM, SYNCBP, SYNCBM
SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2,
GPIO3, GPIO4
–0.2
AVDD19 + 0.2
Voltage applied to output pins
Temperature
–0.3
–40
–65
2.2
85
V
Operating free-air, TA
Storage, Tstg
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
1.9
MAX
2.0
UNIT
AVDD19
Supply voltage(1)
Temperature
AVDD
1.1
1.15
1.15
1.25
1.2
V
DVDD
1.1
Operating free-air, TA
Operating junction, TJ
–40
85
°C
105(2)
125
(1) Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
7.4 Thermal Information
ADC32RF44
THERMAL METRIC(1)
RMP (VQFN)
UNIT
72 PINS
21.8
4.4
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
2.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
2.0
RθJC(bot)
0.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017, Texas Instruments Incorporated
5
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
7.5 Electrical Characteristics
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION(1) (Dual-Channel Operation, Both Channels A and B are Active; DDC Bypass Mode(2)
)
IAVDD19
IAVDD
IDVDD
PD
1.9-V analog supply current
1.15-V analog supply current
1.15-V digital supply current
Power dissipation
12-bit, bypass mode, fS = 2.6 GSPS
12-bit, bypass mode, fS = 2.6 GSPS
12-bit, bypass mode, fS = 2.6 GSPS
12-bit, bypass mode, fS = 2.6 GSPS
1730
860
1969
1079
1846
6.95
mA
mA
mA
W
1416
5.9
Global power-down power
dissipation
360
mW
ANALOG INPUTS
Resolution
14
1.35
1.2(3)
65
Bits
VPP
V
Differential input full-scale
Input common-mode voltage
Input resistance
VIC
RIN
CIN
Differential resistance at dc
Differential capacitance at dc
Ω
Input capacitance
2
pF
V
VCM common-mode voltage output
1.2
Analog input bandwidth
(–3-dB point)
ADC driven with 50-Ω source
3200
MHz
ISOLATION
fIN = 100 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3500 MHz
100
99
95
86
85
Crosstalk isolation between channel
A and channel B(4)
dBc
CLOCK INPUT(5)
Input clock frequency
1.5
0.5
2.6
1.5
GHz
VPP
Differential (peak-to-peak) input
clock amplitude
2.5
Input clock duty cycle
Internal clock biasing
45%
50%
1.0
55%
V
Internal clock termination
(differential)
100
Ω
(1) See the Power Consumption in Different Modes section for more details.
(2) Full-scale signal is applied to the analog inputs of all active channels.
(3) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best
performance.
(4) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.
(5) See Figure 57.
6
Copyright © 2017, Texas Instruments Incorporated
ADC32RF44
www.ti.com.cn
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
7.6 AC Performance Characteristics
typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 100 MHz, AOUT = –2 dBFS
MIN(1)
NOM
62.5
61.2
58.3
57.5
56.4
54.0
153.6
152.3
149.4
148.6
147.5
145.1
63.1
24.7
61.8
60.0
58.0
56.5
54.7
53.2
10.0
9.7
MAX
UNIT
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
55.5
SNR
NSD
Signal-to-noise ratio
dBFS
fIN = 900 MHz, AOUT = –2 dBFS
Noise spectral density
averaged across the
Nyquist zone
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 1850 MHz, AOUT = –40 dBFS
fIN = 1850 MHz, AOUT = –40 dBFS
fIN = 100 MHz, AOUT = –2 dBFS
146.1
dBFS/Hz
Small-signal SNR
Input noise figure
dBFS
dB
NF(3)
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
Signal-to-noise and
distortion ratio
SINAD
dBFS
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
9.3
ENOB
SFDR
HD2(4)
Effective number of bits
Bits
9.1
8.8
8.5
68.0
65.0
69.0
62.0
59.0
57.0
68.0
74.0
69.0
62.0
62.0
57.0
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
60
60
Spurious-free dynamic
range
dBc
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
Second-order harmonic
distortion
dBc
(1) Minimum values are specified at AOUT = –3 dBFS, ADC sampling rate = 2.5 GHz.
(2) Output amplitude, AOUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, AIN, except
when the digital gain feature is used. If digital gain is G, then AOUT = G + AIN
(3) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.
(4) The minimum value of HD2 is specified by bench characterization.
.
Copyright © 2017, Texas Instruments Incorporated
7
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
AC Performance Characteristics (continued)
typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fIN = 100 MHz, AOUT = –2 dBFS
MIN(1)
NOM
84.0
65.0
74.0
67.0
59.0
72.0
92.0
82.0
86.0
87.0
90.0
87.0
93.0
88.0
80.0
85.0
81.0
75.0
83.0
82.0
80.0
75.0
77.0
77.0
79.0
79.0
74.0
72.0
72.0
69.0
MAX
UNIT
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
62.5
Third-order harmonic
distortion
HD3
dBc
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
69.5
66.5
68
HD4,
HD5
Fourth- and fifth-order
harmonic distortion
dBc
dBc
dBc
fIN = 900 MHz, AOUT = –2 dBFS
Interleaving spurs:
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
IL spur
fS / 2 – fIN
,
fS / 4 ± fIN
fIN = 900 MHz, AOUT = –2 dBFS
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
fIN = 100 MHz, AOUT = –2 dBFS
Interleaving spur for HD2:
fS / 2 – HD2
HD2 IL
fIN = 900 MHz, AOUT = –2 dBFS
Spurious-free dynamic
fIN = 1850 MHz, AOUT = –2 dBFS
fIN = 2100 MHz, AOUT = –2 dBFS
fIN = 2500 MHz, AOUT = –2 dBFS
fIN = 3500 MHz, AOUT(2) = –3 dBFS with 2-dB gain
Worst
spur
range (excluding HD2, HD3,
HD4, HD5, and interleaving
spurs IL and HD2 IL)
dBc
fIN1 = 900 MHz, fIN2 = 960 MHz,
AOUT = –8 dBFS (each tone)
82
72
69
Two-tone, third-order
intermodulation distortion
fIN1 = 1850 MHz, fIN2 = 1870 MHz,
AOUT = –8 dBFS (each tone)
IMD3
dBFS
fIN1 = 3490 MHz, fIN2 = 3510 MHz,
AOUT = –8 dBFS (each tone) with 2-dB gain
8
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
7.7 Digital Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)
VIH
VIL
IIH
IIL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
0.8
V
V
0.4
50
–50
4
µA
µA
pF
Ci
DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)
AVDD19
–0.1
VOH
VOL
High-level output voltage
Low-level output voltage
AVDD19
V
V
0.1
DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)
VID
Differential input voltage
350
450
1.2
800
mVPP
V
VCM
Input common-mode voltage
1.05
1.325
DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)
|VOD
|
Output differential voltage
700
450
mVPP
mV
|VOCM
|
Output common-mode voltage
Transmitter pins shorted to any voltage
between –0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
–100
100
mA
Ω
zos
Co
50
2
Output capacitance inside the device,
from either output to ground
pF
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7.8 Timing Requirements
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
MIN
NOM
MAX
UNIT
SAMPLE TIMING
Aperture delay
250
750
ps
ps
Aperture delay matching between two channels on the same device
±15
±150
90
Aperture delay matching between two devices at the same
temperature and supply voltage
ps
Aperture jitter, clock amplitude = 2 VPP
fS
Input
clock
cycles
12-bit bypass mode, LMFS = 82820
461
424
Latency
Data latency, ADC sample to
digital output
(1)(2)
Input
clock
14-bit bypass mode, LMFS = 8224
cycles
Fast overrange latency, ADC sample to FOVR indication on GPIO pins
70
6
Propagation delay time: logic gates and output buffer delay
(does not change with fS)
tPD
ns
SYSREF TIMING(3)
tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 2.6 GSPS
tH_SYSREF SYSREF hold time: referenced to clock rising edge, 2.6 GSPS
Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 2.6 GSPS
JESD OUTPUT INTERFACE TIMING
140
50
70
20
ps
ps
ps
194
UI
Unit interval: 12.5 Gbps
80
100
10.0
60
400
ps
Gbps
ps
Serial output data rate
2.5
12.5
Rise, fall times: 1-pF, single-ended load capacitance to ground
Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps
Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps
25
%UI
0.99
%UI, rms
%UI,
pk-pk
Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps
9.1
(1) Overall latency = latency + tPD
.
(2) Latency increases when the DDC modes are used; see Table 4.
(3) Common-mode voltage for the SYSREF input is kept at 1.2 V.
10
Copyright © 2017, Texas Instruments Incorporated
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
SYSREFP, SYNCP, DxP
VID / 4, VOD / 4
(1)
VICM, VOCM
VID / 4, VOD / 4
SYSREFM, SYNCM, DxM
SYSREF = SYSREFP-SYNCP,
SYNC = SYNCP-SYNCM,
Dx = DxP-DxM
(1)
VID or VOD
0 V
GND
(1) VOCM is not the same as VICM. Similarly, VOD is not the same as VID
.
Figure 1. Logic Levels for Digital Inputs and Outputs
Sample N
CLKP
CLKM
tSU_SYSREF
tH_SYSREF
SYSREFP
SYSREFM
Valid Transition Window
Valid Transition Window
Figure 2. SYSREF Timing Diagram
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7.9 Typical Characteristics
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
D001
0
260
520
780
1040
1300
D002
Frequency (MHz)
Frequency (MHz)
SFDR = 68 dBc, SNR = 62.7 dBFS, SINAD = 62 dBFS,
THD = 68 dBc, HD2 = –68 dBc, HD3 = –83 dBc,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 83 dBc
SFDR = 63 dBc, SNR = 61.3 dBFS, SINAD = 59.8 dBFS,
THD = 63 dBc, HD2 = –72 dBc, HD3 = –63 dBc,
SFDR (non HD2, HD3) = 79 dBc, IL spur = 76 dBc
Figure 3. FFT for 100-MHz Input Signal
Figure 4. FFT for 900-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
D003
0
260
520
780
1040
1300
D004
Frequency (MHz)
Frequency (MHz)
SFDR = 71 dBc, SNR = 58.5 dBFS, SINAD = 58.2 dBFS,
THD = 70 dBc, HD2 = –76 dBc, HD3 = –71 dBc,
SFDR (non HD2, HD3) = 74 dBc, IL spur = 77 dBc
SFDR = 63 dBc, SNR = 57.5 dBFS, SINAD = 56.5 dBFS,
THD = 61 dBc, HD2 = –65 dBc, HD3 = –63 dBc,
SFDR (non HD2, HD3) = 72 dBc, IL spur = 72 dBc
Figure 5. FFT for 1850-MHz Input Signal
Figure 6. FFT for 2100-MHz Input Signal
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
D005
0
260
520
780
1040
1300
D006
Frequency (MHz)
Frequency (MHz)
SFDR = 59 dBc, SNR = 56.3 dBFS, SINAD = 54.2 dBFS,
THD = 56 dBc, HD2 = –59 dBc, HD3 = –60 dBc,
SFDR (non HD2, HD3) = 69 dBc, IL spur = 72 dBc
SFDR = 64 dBc, SNR = 54.1 dBFS, SINAD = 53.9 dBFS,
HD2 = –64 dBc, HD3 = –88 dBc,
SFDR (non HD2, HD3) = 72 dBc, THD = 64 dBc,
IL spur = 77 dBc, AIN = –3 dBFS with 2-dB gain
Figure 8. FFT for 3500-MHz Input Signal
Figure 7. FFT for 2500-MHz Input Signal
12
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
0
260
520
780
1040
1300
Frequency (MHz)
Frequency (MHz)
D007
D008
fIN1 = 900 MHz, fIN2 = 960 MHz,
AIN = –8 dBFS, IMD = 81 dBFS
fIN1 = 900 MHz, fIN2 = 960 MHz,
AIN = –36 dBFS, IMD = 96 dBFS
Figure 9. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 10. FFT for Two-Tone Input Signal (–36 dBFS)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
0
260
520
780
1040
1300
Frequency (MHz)
Frequency (MHz)
D009
D010
fIN1 = 1850 MHz, fIN2 = 1870 MHz,
AIN = –8 dBFS, IMD = 74 dBFS
fIN1 = 1850 MHz, fIN2 = 1870 MHz,
AIN = –36 dBFS, IMD = 94 dBFS
Figure 11. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 12. FFT for Two-Tone Input Signal (–36 dBFS)
0
0
-20
-40
-60
-80
-20
-40
-60
-80
-100
-100
-120
-120
0
260
520
780
1040
1300
0
260
520
780
1040
1300
Frequency (MHz)
Frequency (MHz)
D011
D012
fIN1 = 3490 MHz, fIN2 = 3510 MHz,
AIN = –8 dBFS with 2-dB gain, IMD = 68 dBFS
fIN1 = 3490 MHz, fIN2 = 3510 MHz,
AIN = –36 dBFS with 2-dB gain, IMD = 89 dBFS
Figure 13. FFT for Two-Tone Input Signal (–8 dBFS)
Figure 14. FFT for Two-Tone Input Signal (–36 dBFS)
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
-60
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-36
-32
-28
-24
-20
-16
-12
-8
-36
-32
-28
-24
-20
-16
-12
-8
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D013
D014
fIN1 = 900 MHz, fIN2 = 960 MHz
fIN1 = 1850 MHz, fIN2 = 1870 MHz
Figure 15. Intermodulation Distortion vs Input Amplitude
(900 MHz and 960 MHz)
Figure 16. Intermodulation Distortion vs Input Amplitude
(1850 MHz and 1870 MHz)
-60
90
78
66
54
42
30
-70
-80
-90
-100
-110
-36
-32
-28
-24
-20
-16
-12
-8
0
500
1000
1500
2000
2500
3000
3500
Each Tone Amplitude (dBFS)
InputFrequency (MHz)
D015
D016
fIN1 = 3490 MHz, fIN2 = 3510 MHz
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 18. Spurious-Free Dynamic Range vs Input
Frequency
Figure 17. Intermodulation Distortion vs Input Amplitude
(3490 MHz and 3510 MHz)
105
65
63
61
59
57
55
53
fIN + fS/4 (dBc)
fIN - fS/2 (dBc)
fIN - fS/4 (dBc)
2fIN + fS/4 (dBc)
2fIN - fS/2 (dBc)
2fIN - fS/4 (dBc)
100
95
90
85
80
75
70
65
0
500
1000
1500
2000
2500
3000
3500
0
500
1000
1500
2000
2500
3000
3500
Input Frequency (MHz)
Input Frequency (MHz)
D017
D018
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
AOUT = –2 dBFS with 0-dB gain for fIN less than 3 GHz,
AOUT = –3 dBFS with 2-dB gain for fIN more than 3 GHz
Figure 19. IL Spur vs Input Frequency
Figure 20. Signal-to-Noise Ratio vs Input Frequency
14
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
63
61
59
57
55
53
72
70
68
66
64
62
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D019
D020
fIN = 1850 MHz, AIN = –2 dBFS
fIN = 1850 MHz, AIN = –2 dBFS
Figure 21. Signal-to-Noise Ratio vs AVDD Supply and
Temperature
Figure 22. Spurious-Free Dynamic Range vs AVDD Supply
and Temperature
57
65
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.1 V
AVDD = 1.15 V
AVDD = 1.2 V
AVDD = 1.25 V
AVDD = 1.2 V
AVDD = 1 .25 V
56
63
55
61
54
53
52
59
57
55
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D021
D022
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
Figure 23. Signal-to-Noise Ratio vs AVDD Supply and
Temperature
Figure 24. Spurious-Free Dynamic Range vs AVDD Supply
and Temperature
61
70
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
60
68
59
58
57
56
66
64
62
60
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D0213
D024
fIN = 1850 MHz, AIN = –2 dBFS
fIN = 1850 MHz, AIN = –2 dBFS
Figure 25. Signal-to-Noise Ratio vs DVDD Supply and
Temperature
Figure 26. Spurious-Free Dynamic Range vs DVDD Supply
and Temperature
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
57
56
55
54
53
52
64
62
60
58
56
54
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
DVDD = 1.1 V
DVDD = 1.15 V
DVDD = 1.2 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D025
D026
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
Figure 27. Signal-to-Noise Ratio vs DVDD Supply and
Temperature
Figure 28. Spurious-Free Dynamic Range vs DVDD Supply
and Temperature
61
78
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.95 V
AVDD19 = 2 V
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.95 V
AVDD19 = 2 V
60
59
58
57
56
74
70
66
62
58
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D027
D028
fIN = 1850 MHz, AIN = –2 dBFS
fIN = 1850 MHz, AIN = –2 dBFS
Figure 29. Signal-to-Noise Ratio vs AVDD19 Supply and
Temperature
Figure 30. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
57
64
62
60
58
56
54
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.95 V
AVDD19 = 2 V
AVDD19 = 1.8 V
AVDD19 = 1.85 V
AVDD19 = 1.9 V
AVDD19 = 1.95 V
AVDD19 = 2 V
56
55
54
53
52
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D029
D030
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
fIN = 3500 MHz, AIN = –3 dBFS with 2-dB digital gain
Figure 31. Signal-to-Noise Ratio vs AVDD19 Supply and
Temperature
Figure 32. Spurious-Free Dynamic Range vs
AVDD19 Supply and Temperature
16
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ADC32RF44
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
20
18
16
14
12
10
8
16
14
12
10
8
Temp = -40°C
Temp = 25°C
Temp = 85°C
Temp = -40°C
Temp = 25°C
Temp = 85°C
6
6
4
4
2
2
0
0
D031
D032
HD2 (dBFS)
HD2 (dBFS)
fIN = 1.85 GHz, AOUT = –2 dBFS, AVDD19 = 1.8 V,
ADC sampling rate = 2.5 GHz
fIN = 1.85 GHz, AOUT = –2 dBFS, AVDD19 = 1.9 V,
ADC sampling rate = 2.5 GHz
Figure 33. HD2 Histogram at AVDD19 = 1.8 V
Figure 34. HD2 Histogram at AVDD19 = 1.9 V
72
70
68
66
64
62
60
58
56
54
52
50
48
120
21
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
Temp = -40°C
Temp = 25°C
110
18
100
90
80
70
60
50
40
30
20
10
0
Temp = 85°C
15
12
9
6
3
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
D034
D033
HD2 (dBFS)
fIN = 1.85 GHz
fIN = 1.85 GHz, AOUT = –2 dBFS, AVDD19 = 2.0 V,
ADC sampling rate = 2.5 GHz
Figure 36. Performance vs Amplitude
Figure 35. HD2 Histogram at AVDD19 = 2.0 V
62
71
70
69
68
67
66
65
72
70
68
66
64
62
60
58
56
54
52
50
48
120
SNR
SFDR
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
110
61
60
59
58
57
56
100
90
80
70
60
50
40
30
20
10
0
0.5
0.9
1.3
1.7
2.1
2.5
-70
-60
-50
-40
-30
-20
-10
0
Differential Clock Amplitude (Vpp)
Amplitude (dBFS)
D036
D035
fIN = 1.85 GHz, AIN = –2 dBFS,
ADC sampling rate = 2.5 GHz
fIN = 3.5 GHz, 2-dB digital gain
Figure 38. Performance vs Clock Amplitude
Figure 37. Performance vs Amplitude
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
57
56
55
54
53
52
65
62
61
60
59
58
57
56
80
SNR
SFDR
SNR
SFDR
77.5
75
62.5
60
72.5
70
57.5
55
67.5
52.5
65
0.5
0.9
1.3
1.7
2.1
2.5
40
45
50
55
60
Differential Clock Amplitude (Vpp)
Input Clock Duty Cycle (%)
D037
D038
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain,
ADC sampling rate = 2.5 GHz
fIN = 1.85 GHz,
ADC sampling rate = 2.5 GHz
Figure 39. Performance vs Clock Amplitude
Figure 40. Performance vs Clock Duty Cycle
59
63
0
SNR
SFDR
-20
-40
-60
-80
58
62
61
60
59
58
57
56
55
54
-100
-120
40
45
50
55
60
0
250
500
750
1000
1250
D040
Input Clock Duty Cycle (%)
Frequency (MHz)
D039
fIN = 3.5 GHz, AIN = –3 dBFS with 2-dB digital gain,
ADC sampling rate = 2.5 GHz
fIN = 1.85 GHz, AIN = –2 dBFS, fPSRR = 7.5 MHz,
APSRR = 50 mVPP, AVDD = 1.9 V, PSRR = 20 dB,
ADC sampling rate = 2.5 GHz
Figure 42. Power-Supply Rejection Ratio FFT for Test Signal
on AVDD Supply
Figure 41. Performance vs Clock Duty Cycle
60
0
PSRR with 50-mVpp Signal on AVDD
PSRR with 50-mVpp Signal on AVDD19
-20
50
40
30
20
10
-40
-60
-80
-100
-120
0.02
0.1
1
10
100
500
Frequency of Signal on Supply (MHz)
0
250
500
750
1000
1250
D041
Frequency (MHz)
D042
ADC sampling rate = 2.5 GHz
fIN = 1.85 GHz, AIN = –2 dBFS, fCMRR = 10 MHz,
ACSRR = 50 mVPP, CMRR = 28 dB,
ADC sampling rate = 2.5 GHz
Figure 43. Power-Supply Rejection Ratio vs Supplies
Figure 44. Common-Mode Rejection Ratio FFT
18
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
50
40
30
20
10
0
0
-20
-40
-60
-80
-100
-120
-312.5
-187.5
-62.5
62.5
187.5
312.5
0.2
1
10
100 200
Frequency (MHz)
Frequency of Input Common-Mode Signal (MHz)
D044
D043
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 59.7 dBFS, SFDR (includes IL) = 74 dBc
ADC sampling rate = 2.5 GHz
Figure 46. FFT in 4X Decimation
Figure 45. Common-Mode Rejection Ratio vs Signal
Frequency
0
-20
-40
-60
-80
0
-20
-40
-60
-80
-100
-100
-120
-120
-208.3
-124.98
-41.66
41.66
124.98
208.3
-156.25
-93.75
-31.25
31.25
93.75
156.25
Frequency (MHz)
Frequency (MHz)
D045
D046
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 61 dBFS, SFDR (includes IL) = 72 dBc
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 61.3 dBFS, SFDR (includes IL) = 72 dBc
Figure 47. FFT in 6X Decimation
Figure 48. FFT in 8X Decimation
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-100
-120
-138.9
-83.34
-27.78
27.78
83.34
138.9
-125
-75
-25
25
75
125
Frequency (MHz)
Frequency (MHz)
D047
D048
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 61.5 dBFS, SFDR (includes IL) = 73 dBc
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 62 dBFS, SFDR (includes IL) = 79 dBc
Figure 49. FFT in 9X Decimation
Figure 50. FFT in 10X Decimation
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Typical Characteristics (continued)
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and ADC sampling rate = 2.6 GHz, 50% clock duty cycle, AVDD19 = 1.9 V, AVDD =
1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
-104.2
-62.52
-20.84
20.84
62.52
104.2
-78.12
-46.87
-15.62
15.63
46.88
78.12
Frequency (MHz)
Frequency (MHz)
D049
D050
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 62.7 dBFS, SFDR (includes IL) = 80 dBc
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 63 dBFS, SFDR (includes IL) = 81 dBc
Figure 51. FFT in 12X Decimation
Figure 52. FFT in 16X Decimation
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-100
-120
-69.4
-41.64
-13.88
13.88
41.64
69.4
-62.5
-37.5
-12.5
12.5
37.5
62.5
Frequency (MHz)
Frequency (MHz)
D051
D052
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 63.2 dBFS, SFDR (includes IL) = 79 dBc
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 63.3 dBFS, SFDR (includes IL) = 79 dBc
Figure 53. FFT in 18X Decimation
Figure 54. FFT in 20X Decimation
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-100
-120
-52.1
-31.26
-10.42
10.42
31.26
52.1
-39.1
-23.46
-7.82
7.82
23.46
39.1
Frequency (MHz)
Frequency (MHz)
D053
D054
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 63.7 dBFS, SFDR (includes IL) = 79 dBc
fS = 2500 MSPS, fIN = 1.85 GHz, AIN = –2 dBFS,
SNR = 63.8 dBFS, SFDR (includes IL) = 79 dBc
Figure 55. FFT in 24X Decimation
Figure 56. FFT in 32X Decimation
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8 Parameter Measurement Information
8.1 Input Clock Diagram
Figure 57 shows the input clock diagram.
VCLKIN_DIFF
=
VCLKIN+ - VCLKIN-
VCLKIN+
VCLKIN-
Figure 57. Input Clock Diagram
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9 Detailed Description
9.1 Overview
The ADC32RF44 is a dual, 14-bit, 2.6-GSPS, analog-to-digital converter (ADC) followed by a multi-band digital
down-converter (DDC) that can be bypassed, and a back-end JESD204B digital interface.
The ADCs are preceded by an input buffer and on-chip termination to provide a uniform input impedance over a
large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection
against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with
background, analog and digital, and interleaving correction.
The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of
interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,
16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be
controlled through the SPI or GPIO pins. The ADC32RF44 also provides three different power detectors on-chip
with alarm outputs in order to support external automatic gain control (AGC) loops.
The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized,
and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN,
SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B
interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link.
All features of the ADC32RF44 are configurable through the SPI.
9.2 Functional Block Diagram
DA[1:0]P,
DA[1:0]M
Digital Block
Buffer
N
N
ADC
65 ꢀ
Interleave
Correction
Power
INAP,
INAM
DA[3:2]P,
DA[3:2]M
Detection
NCO
CM
FOVR
NCO
NCO
CTRL
GPIO[4:1]
SYNCBP,
SYNCBM
CLKINP,
CLKINM
Clock
Divider
PLL
SYSREFP,
SYSREFM
NCO
RESET
SCLK
SDATA
SEN
SPI
and
Control
FOVR
NCO
PDN
Digital Block
N
N
DB[1:0]P,
DB[1:0]M
SDO
Buffer
Interleave
Correction
Power
ADC
INBP,
INBM
DB[3:2]P,
DB[3:2]M
Detection
65 ꢀ
Copyright © 2016, Texas Instruments Incorporated
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC32RF44 analog signal inputs are designed to be driven differentially. The analog input pins have
internal analog buffers that drive the sampling circuit. The ADC32RF44 provides on-chip, differential termination
to minimize reflections. The buffer also helps isolate the external driving circuit from the internal switching
currents of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.
The common-mode voltage of the signal inputs is internally biased to CM using the 32.5-Ω termination resistors
that allow for ac-coupling of the input drive network. Figure 58 and Figure 59 show SDD11 at the analog inputs
from dc to 5 GHz with a 100-Ω reference impedance.
TI Device
INxP
CIN
RIN
ZIN = RIN || CIN
SDD11 = (ZIN œ 100) / (ZIN + 100)
INxM
Copyright © 2016, Texas Instruments Incorporated
Figure 58. Equivalent Input Impedance
Figure 59. SDD11 Over the Input Frequency Range
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Feature Description (continued)
The input impedance of analog inputs can also be modelled as parallel combination of equivalent resistance and
capacitance. Figure 60 and Figure 61 show how equivalent impedance (CIN and RIN) vary over frequency.
3
2
0.07
0.06
0.05
0.04
0.03
0.02
0.01
1
0
-1
-2
-3
0
500
1000
1500
2000
2500
3000
0
500
1000
1500
2000
2500
3000
Input Frequency (MHz)
Input Frequency (MHz)
D063
D00614
Figure 60. Differential Input Capacitance vs
Input Frequency
Figure 61. Differential Input Resistance vs Input Frquency
Each input pin (INP, INM) must swing symmetrically between (CM + 0.3375 V) and (CM – 0.3375 V), resulting in
a 1.35-VPP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to
approximately 3.2 GHz, as shown in Figure 62.
2
1
0
-1
-2
-3
-4
-5
-6
100 Ohm Source
-7
50 Ohm Source
-8
100
200 300
500 700 1000
2000 3000 5000
Input Frequency (MHz)
D062
Figure 62. Input Bandwidth with a 100-Ω Source Resistance
24
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Feature Description (continued)
9.3.1.1 Input Clamp Circuit
The ADC32RF44 analog inputs include an internal, differential clamp for overvoltage protection. The clamp
triggers for any input signals at approximately 600 mV above the input common-mode voltage, effectively limiting
the maximum input signal to approximately 2.4 VPP, as shown in Figure 63 and Figure 64.
When the clamp circuit conducts, the maximum differential current flowing through the circuit (via input pins)
must be limited to 20 mA.
TI Device
+600 mV
INxP
To Analog Buffer
+337.5 mV
INP
675 mVPP for INP and INM
(1.35 VPP Differentially)
RDC / 2
Input Vcm
INM
Clamp
Circuit
IDIFF
œ337.5 mV
œ600 mV
VCM
RDC / 2
To Analog Buffer
INxM
Copyright © 2017, Texas Instruments Incorporated
Figure 63. Clamp Circuit in the ADC32RF44
Figure 64. Clamp Response Timing Diagram
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Feature Description (continued)
9.3.2 Clock Input
The ADC32RF44 sampling clock input includes internal 100-Ω differential termination along with on-chip biasing.
The clock input is recommended to be ac-coupled externally. The input bandwidth of the clock input is
approximately 3 GHz; the clock input impedance is shown with a 100-Ω reference impedance in the smith chart
of Figure 65.
Figure 65. SDD11 of the Clock Input
26
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Feature Description (continued)
The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. The
equivalent aperture jitter for input frequencies at a 1-GHz and a 2-GHz input (fS = 2.6 GSPS) is shown in
Figure 66. Depending on the clock frequency, a matching circuit can be designed in order to maximize the clock
amplitude.
350
fIN = 1 GHz
fIN = 2 GHz
300
250
200
150
100
50
0.2
1
2
Clock Amplitude (vPP
)
D061
Figure 66. Equivalent Aperture Jitter vs Input Clock Amplitude
9.3.3 SYSREF Input
The SYSREF signal is a periodic signal that is sampled by the ADC32RF44 device clock and is used to align the
boundary of the local multiframe clock inside the data converter. SYSREF is also used to reset critical blocks
[such as the clock divider for the interleaved ADCs, numerically-controlled oscillators (NCOs), decimation filters
and so forth].
The SYSREF input requires external biasing. Furthermore, SYSREF must be established before the SPI
registers are programmed. A programmable delay on the SYSREF input, as shown in Figure 67, is available to
help with skew adjustment when the sampling clock and SYSREF are not provided from the same source.
CLKINP
50 ꢀ
ë/a
50 ꢀ
CLKINM
Delay
SYSREFP
SYSREF
Capture
100 ꢀ
SYSREFM
Figure 67. SYSREF Internal Circuit Diagram
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Feature Description (continued)
9.3.3.1 Using SYSREF
The ADC32RF44 uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of
the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or
through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change
in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 68.
Input Clock
Divider
(Divide-by-4)
NCO,
JESD Interface
(LMFC Counter)
CLKIN
(CLKP-CLKM)
DLL
PDN SYSREF
(In Master Page)
MASK CLKDIV SYSREF
(In JESD Digital Page)
0
1
SYSREF
(SYSREFP-SYSREFM)
ASSERT SYSREF REG
(In Master Page)
SEL SYSREF REG
(In Master Page)
MASK NCO SYSREF
(In JESD Digital Page)
Figure 68. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter
The ADC32RF44 samples the SYSREF signal on the input clock rising edge. Required setup and hold time are
listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,
whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after
disregarding the first two assertions, as shown in Table 1.
Table 1. Asserting SYSREF
ACTION
SYSREF ASSERTION INDEX
INPUT CLOCK DIVIDER
Gets reset
NCO PHASE
Does not get reset
Does not get reset
Gets reset
LMFC COUNTER
Does not get reset
Does not get reset
Gets reset
1
2
Gets reset
3
Gets reset
4 and onwards
Gets reset
Gets reset
Gets reset
28
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The SESREF use-cases can be classified broadly into two categories:
1. SYSREF is applied as aperiodic multi-shot pulses.
Figure 69 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.
CLKIN
SYSREF
tDLL
(Must be Kept > 40 ms)
1st SYSREF pulse.
Only the input clock
divider is reset.
2nd SYSREF pulse. If
the MASK CLKDIV bit is
set, the clock divider
ignores this pulse and
any subsequent
3rd SYSREF pulse.
The NCO phase and
LMFC counter are reset.
4th SYSREF pulse (and
subsequent pulses).
Ignored by the input clock
divider, NCO, and the JESD
interface.
SYSREF pulses.
1 (The input clock divider ignores the SYSREF pulses.)
MASK CLKDIV SYSREF Register Bit
0
1 (The NCO and LMFC counter of the JESD interface
ignore the SYSREF pulses.)
MASK NCO SYSREF Register Bit(1)
0
Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.
Figure 69. SYSREF Used as a Periodic, Finite Number of Pulses
After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the tDLL time (>
40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider
by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase
and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going
to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted
resets.
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2. SYSREF is applied as a periodic pulse.
Figure 70 shows how SYSREF can be applied as a continuous periodic waveform.
Mask SYSREF to the NCO after
resetting the NCO phase.
The NCO phase is reset here for
the last time.
Then, the NCO mask is set high to
ignore further SYSREF pulses.
CLKIN
SYSREF(1)
Time > tDLL + 2 x tSYSREF
1st SYSREF pulse.
The input clock divider
is reset.
1 (The NCO and LMFC counter of the JESD
interface ignore the SYSREF pulses.)
MASK NCO SYSREF Register Bit(2)
0
tSYSREF is a period of the SYSREF waveform.
Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit.
Figure 70. SYSREF Used as a Periodic Waveform
After applying the SYSREF signal, DLL must be allowed to lock, and the NCO phase and LMFC counter
must be allowed to reset by waiting for at least the tDLL (40 µs) + 2 × tSYSREF time. Then, the SYSREF going
to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.
9.3.3.2 Frequency of the SYSREF Signal
When SYSREF is a periodic signal, its frequency is required to be a sub-harmonic of the internal local multi-
frame clock (LMFC) frequency, as described in Equation 1. The LMFC frequency is determined by the selected
decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.
SYSREF = LMFC / N
where
•
N is an integer value (1, 2, 3, and so forth)
(1)
In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a
multiple of fS / 64. Table 2 provides a summary of the valid LMFC clock settings.
Table 2. . SYSREF and LMFC Clock Frequency
OPERATING MODE
Bypass mode
Bypass mode
Decimation
LMFS SETTING
82820
LMFC CLOCK FREQUENCY
fS(1) / (20 × K)
SYSREF FRQUENCY
fS / (N × LCM(2) (64, 20 × K(3)))
fS / (N × LCM (64, 4 × K))
8224
fS/(4 × K)
fS / (D × S(4) × K)
Various
fS / (N × LCM (64, D(5) × S × K))
(1) fS = sampling (device) clock frequency.
(2) LCM = least-common multiple.
(3) K = number of frames per multi-frame.
(4) S = samples per frame.
(5) D = decimation ratio.
The SYSREF signal is recommended to be a low-frequency signal less than 5 MHz in order to reduce coupling to
the signal path both on the printed circuit board (PCB) as well as internal to the device.
30
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Example 1: fS = 2.6 GSPS, Bypass Mode (LMFS = 82820), K = 16
SYSREF = 2.6 GSPS / LCM (64, 20 × 16) / N = 8.125 MHz / N
Operate SYSREF at 4.0625 MHz (effectively divide-by-640, N = 2)
Example 2: fS = 2.6 GSPS, Divide-by-4 (LMFS = 8411), K = 16
SYSREF = 2.6 GSPS / LCM (4 ,64, 16) = 40.625 MHz / N
Operate SYSREF at 2.539063 MHz (effectively divide-by-1024, N = 16)
For proper device operation, disable the SYSREF signal after the JESD synchronization is established.
9.3.4 DDC Block
The ADC32RF44 provides a sophisticated on-chip, digital down converter (DDC) block that can be controlled
through SPI register settings and the general-purpose input/output (GPIO) pins. The DDC block supports two
basic operating modes: receiver (RX) mode with single- or dual-band DDC and wide-bandwidth observation
receiver mode.
Each ADC channel is followed by two DDC chains consisting of the digital filter along with a complex digital mixer
with a 16-bit numerically-controlled oscillator (NCO), as shown in Figure 71. The NCOs allow accurate frequency
tuning within the Nyquist zone prior to the digital filtering. One DDC chain is intended for supporting a dual-band
DDC configuration in receiver mode and the second DDC chain supports the wide-bandwidth output option for
the observation configuration. At any given time, either the single-band DDC, the dual-band DDC, or the
wideband DDC can be enabled. Furthermore, three different NCO frequencies can be selected on that path and
are quickly switched using the SPI or the GPIO pins to enable wide-bandwidth observation in a multi-band
application.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ Data
Wideband Real Output
Wideband IQ Output
Real[ ]
GPIO
2,3
2
2
LPF
LPF
LPF
LPF
2.6 GSPS
IQ Data, 2.6 GSPS
RX1 IQ Output
ADC
N/2
JESD204B
RX1 Real Output
Real[ ]
IQ Data
fOUT / 4
IQ 2.6 GSPS
RX2 IQ Output
2
LPF
LPF
N/2
RX2 Real Output
Real[ ]
NCO 4,
16 Bits
IQ Data
SYSREF
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 71. DDC Chains Overview (One ADC Channel Shown)
Additionally, the decimation filter block provides the option to convert the complex output back to real format at
twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.
The band is centered in the middle of the Nyquist zone (mixed with fOUT / 4) based on a final output data rate of
fOUT
.
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9.3.4.1 Operating Mode: Receiver
In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 72.
Both DDC chains use the same decimation filter setting and the available options are discussed in the
Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of
lanes of the JESD204B interface.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ Data
Wideband Real Output
Wideband IQ Output
Real[ ]
GPIO
2,3
2
2
LPF
LPF
LPF
LPF
IQ Data, 2.6 GSPS
2.6 GSPS
RX1 IQ Output
ADC
N/2
JESD204B
RX1 Real Output
Real[ ]
IQ Data
fOUT / 4
IQ 2.6 GSPS
RX2 IQ Output
2
LPF
LPF
N/2
RX2 Real Output
Real[ ]
NCO 4,
16 Bits
IQ Data
SYSREF
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 72. Decimation Filter Option for Single- or Dual-Band Operation
32
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9.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver
This mode is intended for using a DDC with a wide bandwidth output, but for multiple bands. This mode uses a
single DDC chain where up to three NCOs can be used to perform wide-bandwidth observation in a multi-band
environment, as shown in Figure 73. The three NCOs can be switched dynamically using either the GPIO pins or
an SPI command. All three NCOs operate continuously to ensure phase continuity; however, when the NCO is
switched, the output data are invalid until the decimation filters are completely flushed with data from the new
band.
fOUT / 4
NCO 1,
16 Bits
NCO 2,
16 Bits
NCO 3,
16 Bits
IQ Data
Wideband Real Output
Wideband IQ Output
Real[ ]
GPIO
2,3
2
2
LPF
LPF
LPF
LPF
2.6 GSPS
IQ Data, 2.6 GSPS
RX1 IQ Output
ADC
N/2
JESD204B
RX1 Real Output
Real[ ]
IQ Data
fOUT / 4
IQ 2.6 GSPS
RX2 IQ Output
2
LPF
LPF
N/2
RX2 Real Output
Real[ ]
NCO 4,
16 Bits
IQ Data
SYSREF
fOUT / 4
NOTE: Red traces show SYSREF going to the NCO blocks.
Figure 73. Decimation Filter Implementation for Single-Band and Wide-Bandwidth Mode
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9.3.4.3 Decimation Filters
The stop-band rejection of the decimation filters is approximately 90 dB with a pass-band bandwidth of
approximately 80%. Table 3 gives an overview of the pass-band bandwidth depending on decimation filter setting
and ADC sampling rate.
Table 3. Decimation Filter Summary and Maximum Available Output Bandwidth
ADC SAMPLE RATE =
BANDWIDTH ADC SAMPLE RATE = N MSPS
2.6 GSPS
COMPLEX OUTPUT
BANDWIDTH OUTPUT RATE BANDWIDTH
NO. OF DDCS
AVAILABLE
PER
NOMINAL
PASSBAND
GAIN
DECIMATION
SETTING
OUTPUT
OUTPUT RATE
(MSPS) PER
BAND
3 dB 1 dB
CHANNEL
(%)
(%)
(MHz) PER
BAND
(MSPS) PER
BAND
(MHz) PER
BAND
Divide-by-4
complex
1
1
2
2
2
2
2
2
2
2
2
–0.4 dB
–0.65 dB
–0.27 dB
–0.45 dB
–0.58 dB
–0.55 dB
–0.42 dB
–0.83 dB
–0.91 dB
–0.95 db
–0.78 dB
90.9
90.6
91.0
90.7
90.7
90.7
90.8
91.2
91.2
91.1
91.1
86.8
86.1
86.8
86.3
N / 4 complex
N / 6 complex
N / 8 complex
N / 9 complex
0.4 × N / 2
0.4 × N / 3
0.4 × N / 4
0.4 × N / 4.5
0.4 × N / 5
0.4 × N / 6
0.4 × N / 8
0.4 × N / 9
0.4 × N / 10
0.4 × N / 12
0.4 × N / 16
650
433.3
325
520
346.64
260
Divide-by-6
complex
Divide-by-8
complex
Divide-by-9
complex
288.9
260
231.12
208
Divide-by-10
complex
86.3 N / 10 complex
86.4 N / 12 complex
86.4 N / 16 complex
87.0 N / 18 complex
87.0 N / 20 complex
86.9 N / 24 complex
86.8 N / 32 complex
Divide-by-12
complex
216.7
162.5
144.4
130
173.36
130
Divide-by-16
complex
Divide-by-18
complex
115.52
104
Divide-by-20
complex
Divide-by-24
complex
108.3
81.3
86.64
65.04
Divide-by-32
complex
34
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A dual-band example with a divide-by-8 complex is shown in Figure 74.
NCO 1,
16 Bits
Band 1
Filter
8
IQ
650 MSPS
IQ 2.6 GSPS
IQ 2.6 GSPS
2.6 GSPS
IQ Output
Band 1
ADC
IQ
650 MSPS
IQ Output
Band 2
8
fS/16
Filter
NCO 2,
16 Bits
Band 2
Band 2
fS/4
Band 1
fS/16
fS/2
NCO 2
NCO 1
Figure 74. Dual-Band Example
The decimation filter responses normalized to the ADC sampling clock are illustrated in Figure 74 to Figure 97
and can be interpreted as follows:
Each figure contains the filter pass-band, transition bands, and alias bands, as shown in Figure 75. The x-axis in
Figure 75 shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling clock
frequency.
For example, in the divide-by-4 complex, the output data rate is an fS / 4 complex with a Nyquist zone of fS / 8 or
0.125 × fS. The transition band is centered around 0.125 × fS and the alias transition band is centered at 0.375 ×
fS. The alias bands that alias on top of the wanted signal band are centered at 0.25 × fS and 0.5 × fS (and are
colored in red).
The decimation filters of the ADC32RF44 provide greater than 90-dB attenuation for the alias bands.
.and Çhat Colds .ack ꢀn
Cilter
Çransition
.and
Çop of Çransition .and
.ands Çhat !liases ꢀn
Çop of {ignal .and
Figure 75. Interpretation of the Decimation Filter Plots
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9.3.4.3.1 Divide-by-4
Peak-to-peak pass-band ripple: approximately 0.22 dB
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Passband
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-20
-40
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency
Frequency
D023
D024
Figure 76. Divide-by-4 Filter Response
Figure 77. Divide-by-4 Filter Response (Zoomed)
9.3.4.3.2 Divide-by-6
Peak-to-peak pass-band ripple: approximately 0.38 dB
0
0
Pass Band
Transition Band
Alias Band
Attn Spec
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Frequency
D025
D026
Figure 78. Divide-by-6 Filter Response
Figure 79. Divide-by-6 Filter Response (Zoomed)
9.3.4.3.3 Divide-by-8
Peak-to-peak pass-band ripple: approximately 0.25 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
0
0.01
0.02
0.03
0.04
0.05
0.06
Frequency
Frequency
D027
D028
Figure 80. Divide-by-8 Filter Response
Figure 81. Divide-by-8 Filter Response (Zoomed)
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9.3.4.3.4 Divide-by-9
Peak-to-peak pass-band ripple: approximately 0.39 dB
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Pass Band
Transition Band
Alias Band
Attn Spec
Pass Band
Transition Band
-20
-40
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
0
0.01
0.02
0.03
0.04
0.05
Frequency
Frequency
D029
D030
Figure 82. Divide-by-9 Filter Response
Figure 83. Divide-by-9 Filter Response (Zoomed)
9.3.4.3.5 Divide-by-10
Peak-to-peak pass-band ripple: approximately 0.39 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
0
0.01
0.02
0.03
0.04
0.05
Frequency
Frequency
D029
D032
Figure 84. Divide-by-10 Filter Response
Figure 85. Divide-by-10 Filter Response (Zoomed)
9.3.4.3.6 Divide-by-12
Peak-to-peak pass-band ripple: approximately 0.36 dB
0
0
Passband
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Frequency
D033
D034
Figure 86. Divide-by-12 Filter Response
Figure 87. Divide-by-12 Filter Response (Zoomed)
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9.3.4.3.7 Divide-by-16
Peak-to-peak pass-band ripple: approximately 0.29 dB
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-20
-40
-60
-80
-100
-120
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Frequency
D035
D036
Figure 88. Divide-by-16 Filter Response
Figure 89. Divide-by-16 Filter Response (Zoomed)
9.3.4.3.8 Divide-by-18
Peak-to-peak pass-band ripple: approximately 0.33 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.005
0.01
Frequency
0.015
0.02
0.025
D038
D037
Figure 90. Divide-by-18 Filter Response
Figure 91. Divide-by-18 Filter Response (Zoomed)
9.3.4.3.9 Divide-by-20
Peak-to-peak pass-band ripple: approximately 0.32 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.2
-20
-40
-0.4
-0.6
-0.8
-1
-60
-80
-100
-120
-1.2
-1.4
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.005
0.01
Frequency
0.015
0.02
0.025
D040
D039
Figure 92. Divide-by-20 Filter Response
Figure 93. Divide-by-20 Filter Response (Zoomed)
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9.3.4.3.10 Divide-by-24
Peak-to-peak pass-band ripple: approximately 0.30 dB
0
0
-0.2
-0.4
-0.6
-0.8
-1
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-20
-40
-60
-80
-100
-120
-1.2
-1.4
0
0.1
0.2
Frequency
0.3
0.4
0.5
0
0.005
0.01
Frequency
0.015
0.02
0.025
D042
D041
Figure 94. Divide-by-24 Filter Response
Figure 95. Divide-by-24 Filter Response (Zoomed)
9.3.4.3.11 Divide-by-32
Peak-to-peak pass-band ripple: approximately 0.24 dB
0
0
Pass Band
Attn Spec
Transition Band
Alias Band
Pass Band
Transition Band
-0.1
-20
-40
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
0
0.005
0.01
0.015
0.02
Frequency
Frequency
D043
D044
Figure 96. Divide-by-32 Filter Response
Figure 97. Divide-by-32 Filter Response (Zoomed)
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9.3.4.3.12 Latency with Decimation Options
Device latency in 12-bit bypass mode (with LMFS = 8224) is 424 clock cycles. When the DDC option is used,
latency increases as a result of decimation filters, as described in Table 4.
Table 4. Latency with different Decimation options
DECIMATION OPTION
Divide-by-4
TOTAL LATENCY, DEVICE CLOCK CYCLES
516
746
Divide-by-6
Divide-by-8
621
Divide-by-9
763.5
811
Divide-by-10
Divide-by-12
Divide-by-16
Divide-by-18
Divide-by-20
Divide-by-24
Divide-by-32
897
1045
1164
1256
1443
1773
9.3.4.4 Digital Multiplexer (MUX)
The ADC32RF44 supports a mode where the output data of the ADC channel A can be routed internally to the
digital blocks of both channel A and channel B. The ADC channel B can be powered down as shown in
Figure 98. In this manner, the ADC32RF44 can be configured as a single-channel ADC with up to four
independent DDC chains or two wideband DDC chains. All decimation filters and JESD204B format
configurations are identical to the two ADC channel operation.
N
ADC A
To JESD ChA
N
NCO
NCO
N
N
ADC B
To JESD ChB
NCO
NCO
Figure 98. Digital Multiplexer Option
9.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers
The ADC32RF44 is equipped with three independent, complex NCOs per ADC channel. The oscillator generates
a complex exponential sequence, as shown in Equation 2.
x[n] = e–jωn
where
•
frequency (ω) is specified as a signed number by the 16-bit register setting
(2)
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The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down
to 0 Hz.
Each ADC channel has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first
DDC can dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth
mode (lower decimation factors, for example, 4 and 6), there can only be one DDC for each ADC channel. The
NCO frequencies can be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB
register settings.
The NCO frequency setting is set by the 16-bit register value given by Equation 3:
DDCxNCOy ì fS
fNCO
=
216
where
•
•
x = 0, 1
y = 1 to 4
(3)
(4)
For example:
If fS = 2.6 GSPS, then the NCO register setting = 38230 (decimal).
Thus, fNCO is defined by Equation 4:
2.6 GSPS
fNCO = 38230ì
= 1516.693 MHz
216
Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic
NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the
register setting.
In bypass mode (when decimation filters are not used), the NCOs are powered down in order to avoid creating
unwanted spurs.
9.3.5 NCO Switching
The first DDC (DDC0) on each ADC channel provides three different NCOs that can be used for phase-coherent
frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0.
The NCOs can be switched through an SPI control or by using the GPIO pins with the register configurations
shown in Table 5 for channel A (50xxh) and channel B (58Xxh). The assignment of which GPIO pin to use for
INSEL0 and INSEL1 is done based on Table 6, using registers 5438h and 5C38h. The NCO selection is done
based on the logic selection on the GPIO pins; see Table 7 and Figure 99.
Table 5. NCO Register Configurations
REGISTER
ADDRESS
DESCRIPTION
NCO CONTROL THROUGH GPIO PINS
NCO SEL pin
500Fh, 580Fh
5438h, 5C38h
Selects the NCO control through the SPI (default) or a GPIO pin.
Selects which two GPIO pins are used to control the NCO.
INSEL0, INSEL1
NCO CONTROL THROUGH SPI CONTROL
NCO SEL pin
NCO SEL
500Fh, 580Fh
5010h, 5810h
Selects the NCO control through the SPI (default) or a GPIO pin.
Selects which NCO to use for DDC0.
Table 6. GPIO Pin Assignment
INSELx[1:0] (Where x = 0 or 1)
GPIO PIN SELECTED
GPIO4
00
01
10
11
GPIO1
GPIO3
GPIO2
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Table 7. NCO Selection
NCO SEL[1]
NCO SEL[0]
NCO SELECTED
NCO1
0
0
1
1
0
1
0
1
NCO2
NCO3
n/a
NCO for DDC1 of
channel x
NCO1
NCO2
NCO3
N/A
0
1
2
3
GPIO4
GPIO1
DtLh3
GPIO2
0
1
2
3
NCO SEL[1:0]
0
1
INSEL1[1:0]
NCO SEL PIN
GPIO4
GPIO1
GPIO3
GPIO2
0
1
2
3
INSEL0[1:0]
Figure 99. NCO Switching from GPIO and SPI
9.3.6 SerDes Transmitter Interface
Each 12.5-Gbps serializer, deserializer (SerDes) LVDS transmitter output requires ac-coupling between the
transmitter and receiver. Terminate the differential pair with 100-Ω resistance (that is, two 50-Ω resistors) as
close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in
Figure 100.
0.1 mF
DA[3:0]P,
DB[3:0]P
Rt = ZO
Transmission Line,
VCM
Receiver
ZO
Rt = ZO
DA[3:0]M,
DB[3:0]M
0.1 mF
Figure 100. External Serial JESD204B Interface Connection
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9.3.7 Eye Diagrams
Figure 101 and Figure 102 show the serial output eye diagrams of the ADC32RF44 at 5.0 Gbps and 12 Gbps
against the JESD204B mask.
Figure 101. Data Eye at 5 Gbps
Figure 102. Data Eye at 12 Gbps
9.3.8 Alarm Outputs: Power Detectors for AGC Support
The GPIO pins can be configured as alarm outputs for channels A and B. The ADC32RF44 supports three
different power detectors (an absolute peak power detector, crossing detector, and RMS power detector) as well
as fast overrange from the ADC. The power detectors operate off the full-rate ADC output prior to the decimation
filters.
9.3.8.1 Absolute Peak Power Detector
In this detector mode, the peak is computed over eight samples of the ADC output. Next, the peak for a block of
N samples (N × S`) is computed over a programmable block length and then compared against a threshold to
either set or reset the peak detector output (Figure 103 and Figure 104). There are two sets of thresholds and
each set has two thresholds for hysteresis. The programmable DWELL-time counter is used for clearing the
block detector alarm output.
BLKTHHH,
BLKTHHL,
BLKTHLH,
BLKTHLL
BLKPKDET
N = [1..216
]
>THHigh
>THLow
Hysteresis
and DWELL
BLKPKDETH
BLKPKDETL
S`
fS / 8
Block:
Peak over N
Samples (S`)
fS / (8N)
fS
Output
of ADC
Peak over 8
Samples
>TLHigh
>TLLow
Hysteresis
and DWELL
DWELL
Figure 103. Peak Power Detector Implementation
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DWELL Time
THHH
THHL
BLKPKDET
Figure 104. Peak Power Detector Timing Diagram
Table 8 shows the register configurations required to set up the absolute peak power detector. The detector
operates in the fS / 8 clock domain; one peak sample is calculated over eight actual samples.
The automatic gain control (AGC) modes can be configured separately for channel A (54xxh) and channel B
(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).
Table 8. Registers Required for the Peak Power Detector
REGISTER
ADDRESS
DESCRIPTION
PKDET EN
5400, 5C00h
Enables peak detector
5401h, 5402h,
5403h, 5C01h,
5C02h, 5C03h
Sets the block length N of number of samples (S`). Number of actual ADC samples is 8X this
value: N is 17 bits: 1 to 216
BLKPKDET
.
BLKTHHH,
BLKTHHL,
BLKTHLH,
BLKTHLL
5407h, 5408h,
5409h, 540Ah,
5C07h, 5C08h,
5C09h, 5C0Ah
Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is
equivalent to the peak amplitude).
For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then set 5407h and
5C07h = CBh.
When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak
detector output flags are set. In order to be reset, the computed block peak must remain
continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by
the DWELL value. This threshold is 16 bits and is specified in terms of fS / 8 clock cycles.
540Bh, 540Ch,
5C0Bh, 5C0Ch
DWELL
OUTSEL
GPIO[4:1]
5432h, 5433h,
5434h, 5435h
Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register.
IODIR
5437h
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
RESET AGC
542Bh, 5C2Bh
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9.3.8.2 Crossing Detector
In this detector mode the peak is computed over eight samples of the ADC output. Next, the peak for a block of
N samples (N × S`) is computed over a programmable block length and then the peak is compared against two
sets of programmable thresholds (with hysteresis). The crossing detector counts how many fS / 8 clock cycles
that the block detector outputs are set high over a programmable time period and compares the counter value
against the programmable thresholds. The alarm outputs are updated at the end of the time period, routed to the
GPIO pins, and held in that state through the next cycle, as shown in Figure 105 and Figure 106. Alternatively, a
2-bit format can be used but (because the ADC32RF44 has four GPIO pins available) this feature uses all four
pins for a single channel.
BLKTHHH,
FILT0LP
SEL
2-Bit Mode
10: High
00: Mid
BLKTHHL,
BLKTHLH,
BLKTHLL
1 or 2-Bit
Mode
BLKPKDET
Time
N = [1..216
]
Constant
01: Low
>THHigh
>THLow
Hysteresis
and DWELL
BLKPKDETH
2-Bit Mode
S`
fS/8
>FIL0THH
>FIL0THL
IIR LPF
IIR LPF
IIR PK DET0
IIR PK DET1
fS/(8N)
Block:
Peak Over N
Samples (S`)
fS
ADC
Output
Peak Over
8 Samples
Combine
>TLHigh
>TLLow
Hysteresis
and DWELL
BLKPKDETHL
>FIL1THH
>FIL1THL
BLKPKDETL
1-Bit Mode
DWELL
With Hysteresis and Dwell
1: High
Time
Constant
1 or 2-Bit
Mode
0: Low
Figure 105. Crossing Detector Implementation
Crossing Detector Time Period
THHH
THHL
BLKPKDET
Crossing Detector Counter Threshold
Crossing Detector Counter
IIR PK DET
Figure 106. Crossing Detector Timing Diagram
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Table 9 shows the register configurations required to set up the crossing detector. The detector operates in the
fS / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B (5Cxxh),
although some registers are common in 54xxh (such as the GPIO pin selection).
Table 9. Registers Required for the Crossing Detector Operation
REGISTER
ADDRESS
DESCRIPTION
PKDET EN
5400h, 5C00h
Enables peak detector
5401h, 5402h, 5403h,
5C01h, 5C02h, 5C03h
Sets the block length N of number of samples (S`).
BLKPKDET
Number of actual ADC samples is 8X this value: N is 17 bits: 1 to 216
.
Sets the different thresholds for the hysteresis function values from 0 to 256
(where 256 is equivalent to the peak amplitude).
5407h, 5408h, 5409h,
540Ah, 5C07h, 5C08h,
5C09h, 5C0Ah
BLKTHHH, BLKTHHL,
BLKTHLH, BLKTHLL
For example: if BLKTHHH is to –2 dBFS from peak, 10(–2 / 20) × 256 = 203, then
set 5407h and 5C07h = CBh.
Select block detector output or 2-bit output mode as the input to the interrupt
identification register (IIR) filter.
FILT0LPSEL
TIMECONST
540Dh, 5C0Dh
Sets the crossing detector time period for N = 0 to 15 as 2N × fS / 8 clock cycles.
The maximum time period is 32768 × fS / 8 clock cycles (approximately 101 µs at
2.6 GSPS).
540Eh, 540Fh,
5C0Eh, 5C0Fh
540Fh-5412h, 5C0Fh-
5C12h, 5416h-5419h,
5C16h-5C19h
Comparison thresholds for the crossing detector counter. These thresholds are 16-
bit thresholds in 2.14-signed notation. A value of 1 (4000h) corresponds to 100%
crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings.
FIL0THH, FIL0THL,
FIL1THH, FIL1THL
541Dh, 541Eh, 5C1Dh,
5C1Eh
DWELLIIR
DWELL counter for the IIR filter hysteresis.
IIR0 2BIT EN,
IIR1 2BIT EN
5413h, 54114h,
5C13h, 5C114h
Enables 2-bit output format for the crossing detector.
5432h, 5433h,
5434h, 5435h
OUTSEL GPIO[4:1]
Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register.
IODIR
5437h
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
RESET AGC
542Bh, 5C2Bh
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9.3.8.3 RMS Power Detector
In this detector mode the peak power is computed for a block of N samples over a programmable block length
and then compared against two sets of programmable thresholds (with hysteresis).
The RMS power detector circuit provides configuration options, as shown in Figure 107. The RMS power value
(1 or 2 bit) can be output onto the GPIO pins. In 2-bit output mode, two different thresholds are used whereas the
1-bit output provides one threshold together with hysteresis.
M = [1..216
]
2-M
2-Bit Mode
10: High
00: Mid
01: Low
fS/8
Randomly
Pick 1 Out of
8 Samples
Accumulate
Over 2^M
Inputs
>THHigh
>THLow
Hysteresis
fS
Output
of ADC
^2
PWR DET
1-Bit Mode
With Hysteresis
1: High
0: Low
1 or 2-Bit
Mode
Figure 107. RMS Power Detector Implementation
Table 10 shows the register configurations required to set up the RMS power detector. The detector operates in
the fS / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B
(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).
Table 10. Registers Required for Using the RMS Power Detector Feature
REGISTER
ADDRESS
DESCRIPTION
RMSDET EN
5420h, 5C20h
Enables RMS detector
Programs the block length to be used for RMS power computation. The block length
is defined in terms of fS / 8 clocks.
PWRDETACCU
5421h, 5C21h
The block length can be programmed as 2M with M = 0 to 16.
The computed average power is compared against these high and low thresholds.
One LSB of the thresholds represents 1 / 216. For example: is PWRDETH is set to
–14 dBFS from peak, [10(–14 / 20)]2 × 216 = 2609, then set 5422h, 5423h, 5C22h,
5C23h = 0A31h.
5422h, 5423h, 5424h,
5425h, 5C22h, 5C23h,
5C24h, 5C25h
PWRDETH,
PWRDETL
RMS2BIT EN
5427h, 5C27h
Enables 2-bit output format for the RMS detector output.
5432h, 5433h,
5434h, 5435h
OUTSEL GPIO[4:1]
Connects the PWRDET alarms to the GPIO pins; common register.
IODIR
5437h
Selects the direction for the four GPIO pins; common register.
After configuration, reset the AGC module to start operation.
RESET AGC
542Bh, 5C2Bh
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9.3.8.4 GPIO AGC MUX
The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs for channel A and B.
The GPIO pins can be configured through the SPI control to output the alarm from the peak power (1 bit),
crossing detector (1 or 2 bit), faster overrange, or the RMS power output, as shown in Figure 108.
The programmable output MUX allows connecting any signal (including the NCO control) to any of the four GPIO
pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming.
IIR PK DET0 [2]
IIR PK DET1 [2]
BLKPKDETH [1]
To GPIO
BLKPKDETL [1]
AGC Pins
FOVR
PWR DET [2]
OUTSEL GPIO[4:1]
Figure 108. GPIO Output MUX Implementation
9.3.9 Power-Down Mode
The ADC32RF44 provides a lot of configurability for the power-down mode. Power-down can be enabled using
the PDN pin or the SPI register writes.
9.3.10 ADC Test Pattern
The ADC32RF44 provides several different options to output test patterns instead of the actual output data of the
ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output
data path is shown in Figure 109.
Digital Block
ADC Section
Transport Layer
Link Layer
PHY Layer
Interleaving
Engine
Data Mapping
Frame
ADC
DDC
Decimation
12-bit
Construction
Filter Block
RAMP
Scrambler
1 + x14 + x15
8b, 10b
Encoding
Serializer
JESD204B Long
Transport Layer
Test Pattern
Test
Patterns
JESD204B
Link Layer
Test Pattern
Figure 109. Test Pattern Generator Implementation
9.3.10.1 Digital Block
The ADC test pattern replaces the actual output data of the ADC. The test patterns listed in Table 11 are
available when the DDC is enabled and located in register 37h of the decimation filter page. When programmed,
the test patterns are output for each converter (M) stream. The number of converter streams per channel
increases by 2 when complex (I, Q) output or dual-band DDC is selected. The test patterns can be synchronized
for both ADC channels using the SYSREF signal.
Additionally, a 12-bit ramp test pattern is available in DDC bypass mode.
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NOTE
The number of converters increases in dual-band DDC mode and with a complex output.
Table 11. Test Pattern Options (Register 37h)
BIT
NAME
DEFAULT
DESCRIPTION
Test pattern outputs on channel A and B.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating sequence of
10101010101010 and 01010101010101
7-4
TEST PATTERN
0000
0100 = Output digital ramp: output data increment by one LSB every
clock cycle from code 0 to 65535
0110 = Single pattern: output data are a custom pattern 1 (75h and 76h)
0111 Double pattern: output data alternate between custom pattern 1 and
custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
9.3.10.2 Transport Layer
The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or 0's are added when needed. Alternatively, the JESD204B long transport layer test
pattern can be substituted instead of the ADC data with the JESD frame, as shown in Table 12.
Table 12. Transport Layer Test Mode EN (Register 01h)
BIT
NAME
DEFAULT
DESCRIPTION
Generates long transport layer test pattern mode according
to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
4
TESTMODE EN
0
1 = Test mode disabled
9.3.10.3 Link Layer
The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer.
Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted.
The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test
patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 13.
Table 13. Link Layer Test Mode (Register 03h)
BIT
NAME
DEFAULT
DESCRIPTION
Generates a pattern according to section 5.3.3.8.2 of the
JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat the initial lane alignment (generates a K28.5
character and repeats lane alignment sequences
continuously)
7-5
LINK LAYER TESTMODE
000
100 = 12-octet random pattern (RPAT) jitter pattern
Furthermore, a 215 pseudo-random binary sequence (PRBS) can be enabled by setting up a custom test pattern
(AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.
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9.4 Device Functional Modes
9.4.1 Device Configuration
The ADC32RF44 can be configured using a serial programming interface, as described in the Serial Interface
section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.
9.4.2 JESD204B Interface
The ADC32RF44 supports device subclass 1 with a maximum output data rate of 12.5 Gbps for each serial
transmitter.
An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific
sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing
and alignment uncertainty. The SYNCB input is used to control the JESD204B SerDes blocks, as shown in
Figure 110.
Depending on the ADC sampling rate, the JESD204B output interface can be operated with one, two, or four
lanes per ADC channel. The JESD204B setup and configuration of the frame assembly parameters is controlled
through the SPI interface.
SysRef
SYNCB
JESD
204B
JESD204B
D[3:0]
INA
INB
JESD
204B
JESD204B
D[3:0]
Sample Clock
Copyright © 2016, Texas Instruments Incorporated
Figure 110. JESD Signal Overview
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Device Functional Modes (continued)
The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown
in Figure 111. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b, 10b data
encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
Scrambler
1+x14+x15
8b, 10b
Encoding
D[3:0]
Comma Characters
Initial Lane
Alignment
Test Patterns
SYNCB
Copyright © 2016, Texas Instruments Incorporated
Figure 111. JESD Digital Block Implementation
9.4.2.1 JESD204B Initial Lane Alignment (ILA)
The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB
signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected
on the SYNCB input, the ADC32RF44 starts transmitting comma (K28.5) characters to establish the code group
synchronization, as shown in Figure 112.
When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF44 starts
the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF44 transmits
four multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame
start and end symbols. The second multiframe also contains the JESD204 link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi
Frame
SYNCb
Transmit Data
xxx
K28.5
K28.5
ILA
ILA
DATA
DATA
Code Group
Synchronization
Initial Lane Alignment
Data Transmission
Figure 112. JESD Internal Timing Information
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Device Functional Modes (continued)
9.4.2.2 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
•
•
•
•
F is the number of octets per frame clock period
L is the number of lanes per link
M is the number of converters for the device
S is the number of samples per frame
9.4.2.3 JESD204B Frame Assembly in Bypass Mode
Table 14 lists the available JESD204B formats and valid ranges for the ADC32RF44. The ranges are limited by
the SerDes line rate and the maximum ADC sample frequency. The sample alignment for the bypass modes on
the different lanes is shown in Table 15.
Table 14. JESD Mode Options: Bypass Mode
DECIMATION
SETTING
(Complex)
OUTPUT
RESOLUTION
(Bits)
JESD
JESD
JESD
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
12-BIT
MODE MODE
PLL
MAX fCLK
(Gsps)
L
M
F
S
MODE MODE MODE
0
3
1
1
0
0
2
0
0
12(1)
8
8
2
2
8
2
20
4
3
0
16X
20X
2.6
2.5
4
5
Bypass
14
(1) In full rate output, the two LSBs are truncated to a 12-bit output.
Table 15. JESD Sample Lane Alignments: Bypass Mode(1)
OUTPUT
LANE
LMFS = 8224
LMFS = 82820
A0[3:0],
A1[11:8]
A2[3:0],
A3[11:8]
A4[3:0],
0000
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
A0[13:6]
A0[5:0], 00
A1[5:0], 00
A0[11:4]
A5[11:4]
A1[7:0]
A6[7:0]
A11[7:0]
A16[7:0]
B1[7:0]
B6[7:0]
B11[7:0]
B16[7:0]
A2[11:4]
A7[11:4]
A12[11:4]
A17[11:4]
B2[11:4]
B7[11:4]
B12[11:4]
B17[11:4]
A3[7:0]
A8[7:0]
A13[7:0]
A18[7:0]
B3[7:0]
B8[7:0]
B13[7:0]
B18[7:0]
A4[11:4]
A5[3:0],
A6[11:8]
A7[3:0],
A8[11:8]
A9[3:0],
0000
A1[13:6]
A2[13:6]
A3[13:6]
B0[13:6]
B1[13:6]
B2[13:6]
B3[13:6]
A9[11:4]
A14[11:4]
A19[11:4]
B4[11:4]
B9[11:4]
B14[11:4]
B19[11:4]
A10[3:0],
A11[11:8]
A12[3:0],
A13[11:8]
A14[3:0],
0000
A2[5:0], 00 A10[11:4]
A3[5:0], 00 A15[11:4]
A15[3:0],
A16[11:8]
A17[3:0],
A18[11:8]
A19[3:0],
0000
B0[3:0],
B1[11:8]
B2[3:0],
B3[11:8]
B4[3:0],
0000
B0[5:0], 00
B1[5:0], 00
B0[11:4]
B5[11:4]
B5[3:0],
B6[11:8]
B7[3:0],
B8[11:8]
B9[3:0],
0000
B10[3:0],
B11[11:8]
B12[3:0],
B13[11:8]
B14[3:0],
0000
B2[5:0], 00 B10[11:4]
B3[5:0], 00 B15[11:4]
B15[3:0],
B16[11:8]
B17[3:0],
B18[11:8]
B19[3:0],
0000
(1) Blue shading indicates channel A and yellow shading indicates channel B.
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9.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output
Table 16 lists the available JESD204B interface formats and valid ranges for the ADC32RF44 with decimation
(single-band DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the
maximum ADC sample frequency. The sample alignment on the different lanes is shown in Table 17.
Table 16. JESD Mode Options: Single-Band Complex Output
DECIMATION
SETTING
(Complex)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
NUMBER OF
ACTIVE DDCS
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
L
M
F
S
8
8
4
4
8
8
4
4
4
2
4
2
4
2
4
2
4
2
4
2
4
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
2
4
1
2
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
4
4
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
20X
20X
40X
40X
20X
20X
40X
40X
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
40X
40X
1
1
0
2
1
1
0
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2.5
5
Divide-by-4
Divide-by-6
1 per channel
1 per channel
1.67
3.33
2.5
5
Divide-by-8
Divide-by-9
Divide-by-10
Divide-by-12
Divide-by-16
Divide-by-18
Divide-by-20
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
2.22
4.44
2
4
1.67
3.33
1.25
2.5
1.11
2.22
1
2
Divide-by-24
Divide-by-32
1 per channel
1 per channel
1.67
1.25
Table 17. JESD Sample Lane Alignments: Single-Band Complex Output(1)
OUTPUT
LANE
LMFS
= 8411
LMFS = 4421
20X
LMFS = 4421
40X
LMFS = 8422
LMFS = 4442
LMFS = 2441
AI0
[15:8]
AI0
[15:8]
AI0
[7:0]
AI0
[15:8]
AI0
[7:0]
DA0
AI0
[7:0]
AI1
[15:8]
AI1
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AI0
[15:8]
AI0
[7:0]
AI0
[15:8]
AI0
[7:0]
AI1
[15:8]
AI1
[7:0]
AI0
[15:8]
AI0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
DA1
DA2
DA3
DB0
DB1
DB2
DB3
AQ0
[15:8]
AQ0
[15:8]
AQ0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AQ1
[15:8]
AQ1
[7:0]
AQ0
[7:0]
AQ1
[15:8]
AQ1
[7:0]
BI0
[15:8]
BI0
[15:8]
BI0
[7:0]
BI0
[15:8]
BI0
[7:0]
BI0
[7:0]
BI1
[15:8]
BI1
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
BI0
[15:8]
BI0
[7:0]
BI1
[15:8]
BI1
[7:0]
BI0
[15:8]
BI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BQ0
[15:8]
BQ0
[15:8
BQ0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
BQ1
[15:8]
BQ1
[7:0]
BQ0
[7:0]
BQ1
[15:8]
BQ1
[7:0]
(1) Blue shading indicates channel A and yellow shading indicates channel B.
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9.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
Table 18 lists the available JESD204B formats and valid ranges for the ADC32RF44 with decimation (single-
band DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum
ADC sample frequency. The sample alignment on the different lanes is shown in Table 19.
Table 18. JESD Mode Options: Single-Band Real Output (Wide Bandwidth)
DECIMATION
SETTING
(Complex)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
NUMBER OF
ACTIVE DDCS
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
L
M
F
S
8
4
4
8
4
4
2
2
2
2
2
2
2
4
1
2
4
1
4
4
1
4
4
1
20X
40X
40X
20X
40X
40X
1
2
0
1
2
0
0
0
1
0
0
0
0
0
0
0
0
1
2.5
Divide-by-4
(Divide-by-2 real)
1 per channel
1 per channel
5
1.67
3.33
Divide-by-6
(Divide-by-3 real)
Table 19. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth)(1)
OUTPUT
LANE
LMFS = 8224
LMFS = 4244
LMFS = 4211
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
A0[15:8]
A0[7:0]
A1[7:0]
A2[7:0]
A3[7:0]
B0[7:0]
B1[7:0]
B2[7:0]
B3[7:0]
A1[15:8]
A2[15:8]
A3[15:8]
B0[15:8]
B1[15:8]
B2[15:8]
B3[15:8]
A0[15:8]
A2[15:8]
A0[7:0]
A1[15:8]
A3[15:8]
A1[7:0]
A3[7:0]
A0[15:8]
A0[7:0]
A2[7:0]
B0[15:8]
B0[15:8]
B0[7:0]
B2[7:0]
B1[15:8]
B3[15:8]
B1[7:0]
B3[7:0]
B0[15:8]
B0[7:0]
(1) Blue shading indicates channel A and yellow shading indicates channel B.
54
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9.4.2.6 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output
Table 20 lists the available JESD204B formats and valid ranges for the ADC32RF44 with decimation (dual-band
DDC) when using a complex output format. The sample alignment on the different lanes is shown in Table 21.
Table 20. JESD Mode Options: Single-Band Real Output
DECIMATION
SETTING
(Complex)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
NUMBER OF
ACTIVE DDCS
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
L
M
F
S
4
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
2
4
2
4
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
40X
40X
40X
40X
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
0
2
0
2
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
2.5
5
Divide-by-8
(Divide-by-4 real)
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
1 per channel
2.22
4.44
2
Divide-by-9
(Divide-by-4.5 real)
Divide-by-10
(Divide-by-5 real)
4
1.67
3.33
1.25
2.5
1.11
2.22
1
Divide-by-12
(Divide-by-6 real)
Divide-by-16
(Divide-by-8 real)
Divide-by-18
(Divide-by-9 real)
Divide-by-20
(Divide-by-10 real)
2
Divide-by-24
(Divide-by-12 real)
1 per channel
1 per channel
1.67
1.25
Divide-by-32
(Divide-by-16 real)
Table 21. JESD Sample Lane Assignment: Single-Band Real Output(1)
OUTPUT
LANE
LMFS =
4211
LMFS = 4222
LMFS = 2221
LMFS = 2242
DA0
DA1
DB0
DB1
A0[15:8]
A0[7:0]
B0[15:8]
B0[7:0]
A0[15:8]
A0[7:0]
A1[7:0]
B0[7:0]
B1[7:0]
A1[15:8]
B0[15:8]
B1[15:8]
A0 [15:8]
A0[7:0]
B0[7:0]
A0[15:8]
B0[15:8]
A0[7:0]
A1[15:8]
B1[15:8]
A1[7:0]
B1[7:0]
B0[15:8]
B0[7:0]
(1) Blue shading indicates channel A and yellow shading indicates channel B.
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9.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output
Table 22 lists the available JESD204B formats and valid ranges for the ADC32RF44 with decimation (dual-band
DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the maximum
ADC sample frequency. The sample alignment on the different lanes is shown in Table 23.
Table 22. JESD Mode Options: Dual-Band Complex Output
DECIMATION
SETTING
(Complex)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
NUMBER OF
ACTIVE DDCS
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
L
M
F
S
8
4
8
4
8
4
8
4
8
4
8
4
8
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2
4
2
4
2
4
2
4
2
4
2
4
2
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
20X
40X
40X
40X
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2.5
5
Divide-by-8
Divide-by-9
Divide-by-10
Divide-by-12
Divide-by-16
Divide-by-18
Divide-by-20
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2.22
4.44
2
4
1.67
3.33
1.25
2.5
1.11
2.22
1
2
Divide-by-24
Divide-by-32
2 per channel
2 per channel
1.67
1.25
Table 23. JESD Sample Lane Assignment: Dual-Band Complex Output(1)
OUTPUT LANE
DA0
LMFS = 8821
A10[15:8]
LMFS = 4841
A10[7:0]
A1Q0[7:0]
A2I0[7:0]
A2Q0[7:0]
B1I0[7:0]
B1Q0[7:0]
B2I0[7:0]
B2Q0[7:0]
DA1
A1Q0[15:8]
A2I0[15:8]
A2Q0[15:8]
B1I0[15:8]
B1Q0[15:8]
B2I0[15:8]
B2Q0[15:8]
A1I0[15:8]
A2I0[15:8]
A1I0[7:0]
A1Q0[15:8]
A2Q0[15:8]
A1Q0[7:0]
A2Q0[7:0]
DA2
A2I0[7:0]
DA3
DB0
DB1
B1I0[15:8]
B2I0[15:8]
B1I0[7:0]
B2I0[7:0]
B1Q0[15:8]
B2Q0[15:8]
B1Q0[7:0]
B2Q0[7:0]
DB2
DB3
(1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.
56
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9.4.2.8 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output
Table 24 lists the available JESD204B formats and valid ranges for the ADC32RF44 with decimation (dual-band
DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum ADC
sample frequency. The sample alignment on the different lanes is shown in Table 25.
Table 24. JESD Mode Options: Dual-Band Real Output
DECIMATION
SETTING
(Complex)
RATIO
[fSerDes / fCLK
(Gbps / GSPS)]
NUMBER OF
ACTIVE DDCS
PLL
MODE
JESD
MODE0
JESD
MODE1
JESD
MODE2
L
M
F
S
8
8
4
4
8
8
4
4
8
8
4
4
8
8
4
4
8
8
4
4
8
8
4
4
8
8
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
1
2
2
4
2
4
2
4
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
20X
20X
40X
40X
40X
40X
40X
40X
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
1
1
0
2
0
2
0
2
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
2.5
5
Divide-by-8
(Divide-by-4 real)
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2 per channel
2.22
4.44
2
Divide-by-9
(Divide-by-4.5 real)
Divide-by-10
(Divide-by-5 real)
4
1.67
3.33
1.25
2.5
1.11
2.22
1
Divide-by-12
(Divide-by-6 real)
Divide-by-16
(Divide-by-8 real)
Divide-by-18
(Divide-by-9 real)
Divide-by-20
(Divide-by-10 real)
2
Divide-by-24
(Divide-by-12 real)
2 per channel
2 per channel
1.67
1.25
Divide-by-32
(Divide-by-16 real)
Table 25. JESD Sample Lane Assignment: Dual-Band Complex Output(1)
OUTPUT
LMFS = 8411
LMFS = 8422
A10[15:8]
LMFS = 4421
LMFS = 4442
LANE
DA0
DA1
DA2
DA3
DB0
DB1
DB2
DB3
A10[15:8]
A10[7:0]
A20[15:8]
A20[7:0]
B10[15:8]
B10[7:0]
B20[15:8]
B20[7:0]
A10[7:0]
A11[7:0]
A20[7:0]
A21[7:0]
B10[7:0]
B11[7:0]
B20[7:0]
B21[7:0]
A11[15:8]
A20[15:8]
A21[15:8]
B10[15:8]
B11[15:8]
B20[15:8]
B21[15:8]
A10[15:8]
A10[7:0]
A20[7:0]
A10[15:8]
A20[15:8]
A10[7:0]
A11[15:8]
A21[15:8]
A11[7:0]
A21[7:0]
A20[15:8]
A20[7:0]
B10[15:8]
B20[15:8]
B10[7:0]
B20[7:0]
B10[15:8]
B20[15:8]
B10[7:0]
B20[7:0]
B11[15:8]
B21[15:8]
B11[7:0]
B21[7:0]
(1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.
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9.4.3 Serial Interface
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the
device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active
(low), as shown in Figure 113. The interface can function with SCLK frequencies from 20 MHz down to low
speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 26.
The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits
to distinguish between read/write, page and register, and individual channel access, as described in Table 27.
Register Address [11:0]
Register Data [7:0]
SDIN
SCLK
R/W
M
P
CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
tDH
tSCLK
tDSU
tSLOADH
tSLOADS
SEN
RESET
Figure 113. SPI Timing Diagram
Table 26. SPI Timing Information
MIN
TYP
MAX
UNIT
MHz
ns
fSCLK
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIN setup time
)
1
50
50
10
10
20
tSLOADS
tSLOADH
tDSU
ns
ns
tDH
SDIN hold time
ns
tSDOUT
Delay between SCLK falling edge to SDOUT
10
ns
58
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ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
Table 27. SPI Input Description
SPI BIT
DESCRIPTION
OPTIONS
0 = SPI write
1 = SPI read back
R/W bit
M bit
Read/write bit
0 = Analog SPI bank (master)
1 = All digital SPI banks (main digital, interleaving,
decimation filter, JESD digital, and so forth)
SPI bank access
JESD page selection bit
0 = Page access
1 = Register access
P bit
SPI access for a specific channel of the JESD SPI
bank
0 = Channel B
1 = Channel A
CH bit
ADDR[11:0]
DATA[7:0]
SPI address bits
SPI data bits
—
—
Figure 114 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT
bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.
SCLK
tSDOUT
SDOUT
Figure 114. SDOUT Timing
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9.4.3.1 Serial Register Write: Analog Bank
The internal register of the ADC32RF44 analog bank (Figure 115) can be programmed by:
1. Driving the SEN pin low.
2. Initiating a serial interface cycle selecting the page address of the register whose content must be written. To
select the master page: write address 0012h with 04h. To select the ADC page: write address 0011h with
FFh.
3. Writing the register content. When a page is selected, multiple registers located in the same page can be
programmed.
Register Address [11:0]
Register Data [7:0]
0
0
0
0
SDIN
SCLK
R/W
M
P
CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SEN
RESET
Figure 115. SPI Write Timing Diagram for the Analog Bank
9.4.3.2 Serial Register Readout: Analog Bank
Contents of the registers located in the two pages of the analog bank (Figure 116) can be readback by:
1. Driving the SEN pin low.
2. Selecting the page address of the register whose content must be read. Master page: write address 0012h
with 04h. ADC page: write address 0011h with FFh.
3. Setting the R/W bit to 1 and writing the address to be read back.
4. Reading back the register content on the SDOUT pin. When a page is selected, the contents of multiple
registers located in same page can be readback.
Register Address [11:0]
Register Data [7:0] = XX
1
0
0
0
SDIN
SCLK
R/W
M
P
CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SEN
RESET
SDOUT
D7 D6 D5 D4 D3 D2 D1 D0
SDOUT [7:0]
Figure 116. SPI Read Timing Diagram for the Analog Bank
60
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9.4.3.3 Serial Register Write: Digital Bank
The digital bank contains seven pages (Offset Corrector Page for channel A and B; Digital Gain Page for channel
A and B; Main digital Page for channel A and B; and JESD Digital Page). The timing for the individual page
selection is shown in Figure 117. The registers located in the pages of the digital bank can be programmed by:
1. Driving the SEN pin low.
2. Setting the M bit to 1 and specifying the page with with the desired register. There are seven pages in Digital
Bank. These pages can be selected by appropriately programming register bits DIGITAL BANK PAGE SEL,
located in addresses 002h, 003h, and 004h, using three consecutive SPI cycles. Addressing in a SPI cycle
begins with 4xxx when selecting a page from digital bank because the M bit must be set to 1.
–
–
–
–
–
–
–
To select the offset corrector page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h
with 00h.
To select the offset corrector page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h
with 00h.
To select the digital gain page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h with
05h.
To select the digital gain page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h with
05h.
To select the main digital page channel A: write address 4004h with 68h, 4003h with 00h, and 4002h with
00h.
To select the main digital page channel B: write address 4004h with 68h, 4003h with 01h, and 4002h with
00h.
To select the JESD digital page: write address 4004h with 69h, 4003h with 00h, and 4002h with 00h.
Register Address [11:0]
Register Data [7:0]
0
1
0
0
SDIN
SCLK
R/W
M
P
CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SEN
RESET
Figure 117. SPI Write Timing Diagram for Digital Bank Page Selection
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3. Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page
is selected, multiple writes into the same page can be done. Addressing in an SPI cycle begins with 6xxx
when selecting a page from the digital bank because the M bit must be set to 1, as shown in Figure 118.
Note that the JESD digital page is common for both channels. The CH bit can be used to distinguish
between two channels when programming registers in the JESD digital page. When CH = 0, registers are
programmed for channel B; when CH = 1, registers are programmed for channel A. Thus, an SPI cycle to
program registers for channel B begins with 6xxx and channel A begins with 7xxx.
Register Address [11:0]
Register Data [7:0]
0
1
1
0
SDIN
SCLK
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SEN
RESET
Figure 118. SPI Write Timing Diagram for Digital Bank Register Write
62
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9.4.3.4 Serial Register Readout: Digital Bank
Readback of the register in one of the digital banks (as shown in Figure 119) can be accomplished by:
1. Driving the SEN pin low.
2. Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.
3. Set the R/W, M, and P bits to 1, select channel A or channel B, and write the address to be read back.
–
JESD digital page: use the CH bit to select channel B (CH = 0) or channel A (CH = 1).
4. Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the
same page can be done.
Register Address [11:0]
Register Data [7:0] = XX
1
1
1
0
SDIN
SCLK
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SEN
RESET
SDOUT
D7
D6
D5
D4
D3
D2
D1
D0
SDOUT [7:0]
Figure 119. SPI Read Timing Diagram for the Digital Bank
9.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages
The decimation filter and power detector pages are special pages that accept direct addressing. The sampling
clock and SYSREF signal are required to properly configure the decimation settings. Registers located in these
pages can be programmed in one SPI cycle (Figure 120).
1. Drive the SEN pin low.
2. Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1
and CH = 1. Additionally, address bit A[10] selects the decimation filter page (A[10] = 0) or the power
detector page (A[10] = 1). Address bit A[11] selects channel A (A[11] = 0) or channel B (A[11] = 1).
–
–
Decimation filter page: write address 50xxh for channel A or 58xxh for channel B.
Power detector page: write address 54xxh for channel A or 5Cxxh for channel B.
Example: Writing address 5001h with 02h selects the decimation filter page for channel A and programs
decimation factor of divide-by-8 (complex output).
Register Address [7:0]
Register Data [7:0]
0
1
0
1
0/1 0/1
0
0
R/W
SDIN
SCLK
M
P
CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SEN
RESET
Figure 120. SPI Write Timing Diagram for the Decimation and Power Detector Pages
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9.5 Register Maps
The ADC32RF44 contains two main SPI banks. The analog SPI bank provides access to the ADC core and the digital SPI bank controls the digital blocks
(including the serial JESD interface). Figure 121 and Figure 122 provide a conceptual view of the SPI registers inside the ADC32RF44. The analog SPI
bank contains the master and ADC pages. The digital SPI bank is divided into multiple pages (the main digital, digital gain, decimation filter, JESD digital,
and power detector pages).
Register Address[11:0]
Register Data[7:0]
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SPI Cycle
SCLK
SEN
Initiate an SPI Cycle(1)
R/W, M, P, CH, Bits Decoder
M = 0
M = 1
Analog Bank(3)
Digital Bank
General Register
General Register
(Address 00h,
Keep M, P = 0)
(Global Reset)
Select Master Page
(Address 12h, value 04h,
Keep M, P = 0)
Select ADC Page
(Address 11h, Value FFh,
Keep M, P = 0)
1st SPI Cycle:
Page Selection
Select DIGITAL Bank Page
(Address 04h, Address 03h, and Address 02h bits DIGITAL BANK PAGE SEL[23:0],
Keep M = 1, P = 0)
(Address 05h,
Keep M = 1, P = 0)
Value 04h
Value FFh
SPI cycle:
These Pages
are directly
programmed
in one SPI
cycle.
Value 610000h
Value 610100h
Value 610005h
Value 610105h
Value 690000h
Value 680000h
Value 680100h
Master Page
(PDN,
ADC Page
(Slow Speed
Enable,
Initialization
Registers)
Direct
Addressing
Pages:
Offset Corr Page
ChA
(Offset Corr)
Offset Corr Page
ChB
(Offset Corr)
Digital Gain Page
ChA
(Digital Gain)
Digital Gain Page
ChB
(Digital Gain)
Main
Digital Page for
ChA
Main
Digital Page for
ChB
JESD
Digital Page
(JESD
DC Coupling,
SYSREF Delay,
JESD Swing,
initialization
Registers)
DDC and
Power
Configuration)
2nd SPI Cycle:
Page Programing
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
(Nyquist Zone)
(Nyquist Zone)
Keep M, P, R/W =
0 when writing to
this page, and
keep these bits =
1 when reading
from this page
Detector(2)
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep M, P = 1,
CH = 0 for ChB,
CH = 1 for ChA
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading
from this page
Keep
M, P, CH bits =
(1, 1, 0).
R/W = 0 when
writing to this
page, and = 1
when reading from
this page
Keep M, P, R/W =
0 when writing to
this page, and
keep these bits =
1 when reading
from this page
Keep R/W = 0
when writing to
this page, and = 1
when reading
from this page
In general, SPI writes are completed in two steps. The first step is to access the necessary page. The second step is to program the desired register in that page. When
a page is accessed, the registers in that page can be programmed multiple times.
Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle.
The CH bit is a don't care bit and is recommended to be kept at 0.
Figure 121. SPI Registers, Two-Step Addressing
64
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Register Maps (continued)
Register Address[11:0]
Register Data[7:0]
R/W
M
P
CH
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDIN
SPI Cycle
SCLK
SEN
Initiate an SPI Cycle
R/W, M, P, CH, Bits Decoder
M = 0
Direct Addressing Pages
M = 1
Digital Bank
Analog Bank
1st SPI Cycle:
M=1,P=0, CH=1,
A11=1, A10=0
M=1,P=0, CH=1,
M=1,P=0, CH=1,
A11=1, A10=1
A11=0, A10=1
M=1,P=0, CH=1,
A11=0, A10=0
Page Selection
SPI cycle(1)
These pages
are directly
:
Addr
Addr
Addr
00h(3)
00h(3)
Addr
00h(3)
00h(3)
programmed
in one SPI
cycle.
Program
Decimation
Program
Program
Power
Program
Power
Decimation
Filter Page for
ChB(2)
2nd SPI Cycle:
Page Programing
Filter Page for
Detector Page
Detector Page
ChA(2)
for ChA(3)
for ChB(3)
(DDC modes)
(DDC modes)
Addr
3Ah
Addr
25h
Addr
25h
Addr
3Ah
Registers in the decimation filter page and the power detector page can be directly programmed in one SPI cycle.
To program registers in the decimation filter page, aet M = 1, CH = 1, A[10] = 0, and A[11] = 0 or 1 for channel A or B. Addressing begins at 50xx for channel A and
58xx for channel B.
To program registers in power detector page, set M = 1, CH = 1, A[10] = 1, and A[11] = 0 or 1 for channel A or B. Addressing begins at 54xx for channel A and 5Cxx for
channel B.
Figure 122. SPI Registers: Direct Addressing
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Register Maps (continued)
Table 28 lists the register map for the ADC32RF44.
Table 28. Register Map
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
4
7
6
5
3
2
1
0
GENERAL REGISTERS
000
002
003
004
010
011
RESET
0
0
0
0
0
0
RESET
DIGITAL BANK PAGE SEL[7:0]
DIGITAL BANK PAGE SEL[15:8]
DIGITAL BANK PAGE SEL[23:16]
0
0
0
0
0
0
0
0
0
0
0
0
3 or 4 WIRE
0
ADC PAGE SEL
MASTER PAGE
SEL
012
0
0
MASTER PAGE (M = 0)
020
0
0
0
0
PDN SYSREF
0
0
0
0
0
0
0
0
GLOBAL PDN
0
INCR CM
IMPEDANCE
032
039
03C
03D
05A
0
0
0
ALWAYS WRITE 1
SYSREF DEL EN
0
0
0
0
ALWAYS WRITE 1
0
0
0
0
0
0
SYNC TERM DIS
0
0
0
SYSREF DEL[4:3]
JESD OUTPUT SWING
0
SYSREF DEL[2:0]
0
0
0
0
0
0
ASSERT SYSREF
REG
057
0
0
0
0
0
SEL SYSREF REG
0
0
0
058
SYNCB POL
0
ADC PAGE (FFh, M = 0)
03F
042
0
0
0
0
0
0
0
0
0
SLOW SP EN1
0
0
0
0
0
SLOW SP EN2
Offset Corr Page Channel A (610000h, M = 1)
FREEZE OFFSET
DIS OFFSET
CORR
68
0
ALWAYS WRITE 1
0
0
0
ALWAYS WRITE 1
ALWAYS WRITE 1
0
0
CORR
Offset Corr Page Channel B (610100h, M = 1)
FREEZE OFFSET
DIS OFFSET
CORR
68
0
0
ALWAYS WRITE 1
0
0
0
CORR
Digital Gain Page Channel A (610005, M = 1)
0A6
0
DIGITAL GAIN
66
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
Digital Gain Page Channel B (610105, M = 1)
0A6
0
0
0
0
DIGITAL GAIN
Main Digital Page Channel A (680000h, M = 1)
DIG CORE RESET
GBL
000
0A2
0
0
0
0
0
0
0
0
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
Main Digital Page Channel B (680100h, M = 1)
000
0A2
0
0
0
0
0
0
0
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
JESD DIGITAL PAGE (690000h, M = 1)
001
002
CTRL K
0
0
0
TESTMODE EN
0
0
LANE ALIGN
JESD MODE1
FRAME ALIGN
JESD MODE2
TX LINK DIS
SYNC REG
SYNC REG EN
12BIT MODE
JESD MODE0
LMFC MASK
RESET
003
LINK LAYER TESTMODE
LINK LAY RPAT
RAMP 12BIT
004
006
007
016
0
0
0
0
0
0
0
0
0
0
0
0
0
REL ILA SEQ
SCRAMBLE EN
0
0
0
FRAMES PER MULTIFRAME (K)
LANE 2
LANE 0
LANE 1
LANE 3
LANE0
POL
LANE1
POL
LANE2
POL
LANE3
POL
017
0
0
0
0
032
033
034
035
036
037
SEL EMP LANE 0
SEL EMP LANE 1
SEL EMP LANE 2
SEL EMP LANE 3
0
0
0
0
0
0
0
0
0
0
80X MODE EN
0
CMOS SYNCB
0
0
0
0
0
0
0
0
0
PLL MODE
MASK CLKDIV
SYSREF
MASK NCO
SYSREF
03E
0
0
0
0
0
0
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
DECIMATION FILTER PAGE (Direct Addressing, 16-Bit Address, 5000h for Channel A and 5800h for Channel B)
000
001
002
005
006
007
008
009
00A
00B
00C
00D
00E
00F
010
011
014
016
01E
01F
033
034
035
036
037
038
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDC EN
DECIM FACTOR
0
0
0
0
0
0
0
0
0
DUAL BAND EN
REAL OUT EN
DDC MUX
DDC0 NCO1 LSB
DDC0 NCO1 MSB
DDC0 NCO2 LSB
DDC0 NCO2 MSB
DDC0 NCO3 LSB
DDC0 NCO3 MSB
DDC1 NCO4 LSB
DDC1 NCO4 MSB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NCO SEL PIN
0
NCO SEL
LMFC RESET MODE
0
0
0
DDC0 6DB GAIN
DDC1 6DB GAIN
0
0
0
0
0
DDC DET LAT
0
0
0
WBF 6DB GAIN
CUSTOM PATTERN1[7:0]
CUSTOM PATTERN1[15:8]
CUSTOM PATTERN2[7:0]
CUSTOM PATTERN2[15:8]
0
0
0
0
TEST PATTERN SEL
TEST PATTERN DDC2 Q-DATA
TEST PATTERN DDC2 I -DATA
USE COMMON
TEST PATTERN
039
03A
0
0
0
0
0
0
0
0
0
0
0
0
0
TEST PAT RES
TP RES EN
68
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
POWER DETECTOR PAGE (Direct Addressing, 16-Bit Address, 5400h for Channel A and 5C00h for Channel B)
000
001
002
003
007
008
009
00A
00B
00C
00D
00E
00F
010
011
012
013
016
017
018
019
01A
01D
01E
020
021
022
023
024
025
0
0
0
0
0
0
0
PKDET EN
BLKPKDET [7:0]
BLKPKDET [15:8]
0
0
0
0
0
0
0
BLKPKDET [16]
BLKTHHH
BLKTHHL
BLKTHLH
BLKTHLL
DWELL[7:0]
DWELL[15:8]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FILT0LPSEL
TIMECONST
FIL0THH[7:0]
FIL0THH[15:8]
FIL0THL[7:0]
FIL0THL[15:8]
0
0
0
0
0
0
0
IIR0 2BIT EN
FIL1THH[7:0]
FIL1THH[15:8]
FIL1THL[7:0]
FIL1THL[15:8]
0
0
0
0
0
0
0
0
IIR1 2BIT EN
IIR0 2BIT EN
DWELLIIR[7:0]
DWELLIIR[15:8]
0
0
0
0
0
0
PWRDETACCU
PWRDETH[7:0]
PWRDETH[15:8]
PWRDETL[7:0]
PWRDETL[15:8]
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Register Maps (continued)
Table 28. Register Map (continued)
REGISTER
ADDRESS
A[11:0] (Hex)
REGISTER DATA
7
6
5
4
3
2
1
0
POWER DETECTOR PAGE (continued)
027
02B
037
038
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RMS 2BIT EN
0
RESET AGC
0
0
0
0
IODIR GPIO4
0
IODIR GPIO3
0
IODIR GPIO2
IODIR GPIO1
INSEL1
INSEL0
POWER DETECTOR PAGE (Direct Addressing, 16-Bit Address, 5400h)
032
033
034
035
OUTSEL GPIO1
OUTSEL GPIO2
OUTSEL GPIO3
OUTSEL GPIO4
70
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9.5.1 Example Register Writes
This section provides three different example register writes. Table 29 describes a global power-down register
write, Table 30 describes the register writes when the scrambler is enabled, and Table 31 describes the register
writes for 8X decimation for channels A and B (complex output, 1 DDC mode) with the NCO set to 1.56 GHz (fS
= 2.6 GSPS) and the JESD format configured to LMFS = 4421.
Table 29. Global Power-Down
ADDRESS
12h
DATA
04h
COMMENT
Set the master page
20h
01h
Set the global power-down
Table 30. Scrambler Enable
ADDRESS
4004h
DATA
69h
COMMENT
Select the digital JESD page
4003h
00h
6006h
80h
Scrambler enable, channel A
Scrambler enable, channel B
7006h
80h
Table 31. 8X Decimation for Channel A and B
ADDRESS
4004h
4003h
6000h
6000h
4003h
6000h
6000h
4004h
4003h
6002h
7002h
5000h
5001h
5007h
5008h
5014h
5801h
5807h
5808h
5814h
DATA
COMMENT
68h
00h
01h
00h
01h
01h
00h
69h
00h
01h
01h
01h
02h
9Ah
99h
01h
02h
9Ah
99h
01h
Select the main digital page for channel A
Issue a digital reset for channel A
Clear the digital for reset channel A
Select the main digital page for channel B
Issue a digital reset for channel B
Clear the digital reset for channel B
Select the digital JESD page
Set JESD MODE0 = 1, channel A
Set JESD MODE0 = 1, channel B
Enable the DDC, channel A
Set decimation to 8X complex
Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.56GHz, fS = 2.6 GSPS)
Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.56 GHz, fS = 2.6 GSPS)
Enable the 6-dB digital gain of DDC0
Set decimation to 8X complex
Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.56 GHz, fS = 2.6 GSPS)
Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.56 GHz, fS = 2.6 GSPS)
Enable the 6-dB digital gain of DDC0
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9.5.2 Register Descriptions
9.5.2.1 General Registers
9.5.2.1.1 Register 000h (address = 000h), General Registers
Figure 123. Register 000h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
RESET
R/W-0h
RESET
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0h
0 = Normal operation
1 = Internal software reset, clears back to 0
6-1
0
0
W
0h
0h
Must write 0
0 = Normal operation(1)
RESET
R/W
1 = Internal software reset, clears back to 0
(1) Both bits (7, 0) must be set simultaneously to perform a reset.
9.5.2.1.2 Register 002h (address = 002h), General Registers
Figure 124. Register 002h
7
6
5
4
3
2
1
0
DIGITAL BANK PAGE SEL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 33. Register 002h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[7:0]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
72
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9.5.2.1.3 Register 003h (address = 003h), General Registers
Figure 125. Register 003h
7
6
5
4
3
2
1
0
DIGITAL BANK PAGE SEL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 34. Register 003h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[15:8]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
9.5.2.1.4 Register 004h (address = 004h), General Registers
Figure 126. Register 004h
7
6
5
4
3
2
1
0
DIGITAL BANK PAGE SEL[23:16]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 35. Register 004h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DIGITAL BANK PAGE SEL[23:16]
R/W
0h
Program the JESD BANK PAGE SEL[23:0] bits to access the
desired page in the JESD bank.
680000h = Main digital page CHA selected
680100h = Main digital page CHB selected
610000h = Digital function page CHA selected
610100h = Digital function page CHB selected
690000h = JESD digital page selected
9.5.2.1.5 Register 010h (address = 010h), General Registers
Figure 127. Register 010h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
3 or 4 WIRE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write; -n = value after reset
Table 36. Register 010h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
3 or 4 WIRE
R/W
0h
0 = 4-wire SPI (default)
1 = 3-wire SPI where SDIN become input or output
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9.5.2.1.6 Register 011h (address = 011h), General Registers
Figure 128. Register 011h
7
6
5
4
3
2
1
0
ADC PAGE SEL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 37. Register 011h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
ADC PAGE SEL
R/W
0h
00000000 = Normal operation, ADC page is not selected
11111111 = ADC page is selected; MASTER PAGE SEL must
be set to 0
9.5.2.1.7 Register 012h (address = 012h), General Registers
Figure 129. Register 012h
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
MASTER PAGE SEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 38. Register 012h Field Descriptions
Bit
7-3
2
Field
Type
W
Reset
0h
Description
0
Must write 0
MASTER PAGE SEL
R/W
0h
0 = Normal operation
1 = Selects the master page address; ADC PAGE must be set
to 0
1-0
0
W
0h
Must write 0
74
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9.5.3 Master Page (M = 0)
9.5.3.1 Register 020h (address = 020h), Master Page
Figure 130. Register 020h
7
0
6
0
5
0
4
3
0
2
0
1
0
PDN SYSREF
R/W-0h
PDN CHB
R/W-0h
GLOBAL PDN
R/W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 020h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
PDN SYSREF
R/W
0h
This bit powers down the SYSREF input buffer.
0 = Normal operation
1 = SYSREF input capture buffer is powered down and further
SYSREF input pulses are ignored
3-2
1
0
W
0h
0h
Must write 0
PDN CHB
R/W
This bit powers down channel B.
0 = Normal operation
1 = Channel B is powered down
0
GLOBAL PDN
R/W
0h
This bit enables the global power-down.
0 = Normal operation
1 = Global power-down enabled
9.5.3.2 Register 032h (address = 032h), Master Page
Figure 131. Register 032h
7
0
6
0
5
4
3
2
0
1
0
0
0
INCR CM
IMPEDANCE
0
0
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 032h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0
INCR CM IMPEDANCE
R/W
0h
Only use this bit when analog inputs are dc-coupled to the
driver.
0 = VCM buffer directly drives the common point of biasing
resistors.
1 = VCM buffer drives the common point of biasing resistors with
> 5 kΩ
4-0
0
W
0h
Must write 0
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9.5.3.3 Register 039h (address = 039h), Master Page
Figure 132. Register 039h
7
0
6
5
0
4
3
0
2
0
1
0
ALWAYS
WRITE 1
ALWAYS
WRITE 1
PDN CHB EN
R/W-0h
SYNC TERM DIS
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 039h Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
ALWAYS WRITE 1
W
0h
Always set this bit to 1
Must write 0
5
0
W
0h
4
ALWAYS WRITE 1
W
0h
Always set this bit to 1
Must write 0
3-2
1
0
W
0h
PDN CHB EN
R/W
0h
This bit enables the power-down control of channel B through
the SPI in register 20h.
0 = PDN control disabled
1 = PDN control enabled
0
SYNC TERM DIS
R/W
0h
This bit disables the on-chip, 100-Ω termination resistors on the
SYNCB input.
0 = On-chip, 100-Ω termination enabled
1 = On-chip, 100-Ω termination disabled
9.5.3.4 Register 03Ch (address = 03Ch), Master Page
Figure 133. Register 03Ch
7
0
6
5
4
3
2
0
1
0
SYSREF DEL EN
R/W-0h
0
0
0
SYSREF DEL[4:3]
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 03Ch Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
SYSREF DEL EN
R/W
0h
This bit allows an internal delay to be added to the SYSREF
input.
0 = SYSREF delay disabled
1 = SYSREF delay enabled through register settings [3Ch (bits
1-0), 5Ah (bits 7-5)]
5-2
1-0
0
W
0h
0h
Must write 0
SYSREF DEL[4:3]
R/W
When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
The PVT variation of each 25-ps step is ±10 ps. The 175-ps step
is ±50 ps; see Table 44.
76
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9.5.3.5 Register 05Ah (address = 05Ah), Master Page
Figure 134. Register 05Ah
7
6
5
4
0
3
0
2
0
1
0
0
0
SYSREF DEL[2:0]
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 43. Register 05Ah Field Descriptions
Bit
7
Field
Type
W
Reset
Description
SYSREF DEL2
SYSREF DEL1
SYSREF DEL0
0
0h
When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
The PVT variation of each 25-ps step is ±10 ps. The 175-ps step
is ±50 ps; see Table 44.
6
R/W
W
5
4-0
W
0h
Must write 0
Table 44. SYSREF DEL[2:0] Bit Settings
STEP
SETTING
01000
00111
00110
00101
00100
00011
STEP (NOM)
175 ps
25 ps
TOTAL DELAY (NOM)
175 ps
1
2
3
4
5
6
200 ps
25 ps
225 ps
25 ps
250 ps
25 ps
275 ps
25 ps
300 ps
9.5.3.6 Register 03Dh (address = 3Dh), Master Page
Figure 135. Register 03Dh
7
0
6
0
5
0
4
0
3
0
2
1
0
JESD OUTPUT SWING
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 03Dh Field Descriptions
Bit
7-3
2-0
Field
Type
W
Reset
0h
Description
0
Must write 0
JESD OUTPUT SWING
R/W
0h
These bits select the output amplitude, VOD (mVPP), of the JESD
transmitter for all lanes.
0 = 860 mVPP
1= 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP
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9.5.3.7 Register 057h (address = 057h), Master Page
Figure 136. Register 057h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
SEL SYSREF REG
R/W-0h
ASSERT SYSREF REG
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. Register 057h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
SEL SYSREF REG
R/W
0h
SYSREF can be asserted using this bit. Ensure that the SEL
SYSREF REG register bit is set high before using this bit; see
the Using SYSREF section.
0 = SYSREF is logic low
1 = SYSREF is logic high
3
ASSERT SYSREF REG
R/W
W
0h
0h
Set this bit to use the SPI register to assert SYSREF.
0 = SYSREF is asserted by device pins
1 = SYSREF can be asserted by the ASSERT SYSREF REG
register bit
Other bits = 0
2-0
0
Must write 0
9.5.3.8 Register 058h (address = 058h), Master Page
Figure 137. Register 058h
7
0
6
0
5
4
3
2
0
1
0
0
0
SYNCB POL
R/W-0h
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 47. Register 058h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0
SYNCB POL
R/W
0h
This bit inverts the SYNCB polarity.
0 = Polarity is not inverted; this setting matches the timing
diagrams in this document and is the proper setting to use
1 = Polarity is inverted
4-0
0
W
0h
Must write 0
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9.5.4 ADC Page (FFh, M = 0)
9.5.4.1 Register 03Fh (address = 03Fh), ADC Page
Figure 138. Register 03Fh
7
0
6
0
5
0
4
0
3
0
2
1
0
0
0
SLOW SP EN1
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 48. Register 03Fh Field Descriptions
Bit
7-3
2
Field
Type
W
Reset
0h
Description
0
Must write 0
SLOW SP EN1
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
1-0
0
W
0h
Must write 0
9.5.4.2 Register 042h (address = 042h), ADC Page
Figure 139. Register 042h
7
0
6
0
5
0
4
3
2
0
1
0
0
0
SLOW SP EN2
R/W-0h
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 49. Register 042h Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
SLOW SP EN2
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
3-0
0
W
0h
Must write 0
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9.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)
9.5.5.1 Register A6h (address = 0A6h), Digital Function Page
Figure 140. Register 0A6h
7
0
6
0
5
0
4
0
3
2
1
0
DIG GAIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 50. Register 0A6h Field Descriptions
Bit
7-4
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIG GAIN
R/W
0h
These bits set the digital gain of the ADC output data prior to
decimation up to 11 dB; see Table 51.
Table 51. DIG GAIN Bit Settings
SETTING
0000
0001
0010
…
DIGITAL GAIN
0 dB
1 dB
2 dB
…
1010
1011
10 dB
11 dB
9.5.6 Offset Corr Page Channel A (610000h, M = 1)
9.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A
Figure 141. Register 034h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SEL EXT EST
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 52. Register 034h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
SEL EXT EST
R/W
0h
This bit selects the external estimate for the offset correction
block; see the Using DC Coupling in the ADC32RF44 section.
80
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9.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A
Figure 142. Register 068h
7
6
0
5
4
0
3
0
2
1
0
0
DIS
OFFSET
CORR
FREEZE OFFSET
CORR
ALWAYS WRITE 1
R/W-0h
ALWAYS WRITE 1
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 53. Register 068h Field Descriptions
Bit
Field
Type
Reset
Description
7
FREEZE OFFSET CORR
R/W
0h
Use this bit and bits 5 and 1 to freeze the offset estimation
process of the offset corrector; see the Using DC Coupling in
the ADC32RF44 section.
011 = Apply this setting after powering up the device
111 = Offset corrector is frozen, does not estimate offset
anymore, and applies the last computed value.
Others = Do not use
6
5
0
W
0h
0h
Must write 0
ALWAYS WRITE 1
R/W
Always write this bit as 1 for the offset correction block to work
properly.
4-3
2
0
W
0h
0h
Must write 0
DIS OFFSET CORR
R/W
0 = Offset correction block works and removes fS/8, fS/4, 3fS/8
,
and fS/2 spurs
1 = Offset correction block is disabled
1
0
ALWAYS WRITE 1
0
R/W
W
0h
0h
Always write this bit as 1 for the offset correction block to work
properly.
Must write 0
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9.5.7 Offset Corr Page Channel B (610000h, M = 1)
9.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B
Figure 143. Register 068h
7
6
0
5
4
0
3
0
2
1
0
0
DIS
OFFSET
CORR
FREEZE OFFSET
CORR
ALWAYS WRITE 1
R/W-0h
ALWAYS WRITE 1
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 54. Register 068h Field Descriptions
Bit
Field
Type
Reset
Description
7,5,1
FREEZE OFFSET CORR
R/W
0h
Use this bit and bits 5 and 1 to freeze the offset estimation
process of the offset corrector; see the Using DC Coupling in
the ADC32RF44 section.
011 = Apply this setting after powering up the device
111 = Offset corrector is frozen, does not estimate offset
anymore, and applies the last computed value.
Others = Do not use
6
5
0
W
0h
0h
Must write 0
ALWAYS WRITE 1
R/W
Always write this bit as 1 for the offset correction block to work
properly.
4-3
2
0
W
0h
0h
Must write 0
DIS OFFSET CORR
R/W
0 = Offset correction block works and removes fS/8, fS/4, 3fS/8
,
and fS/2 spurs
1 = Offset correction block is disabled
1
0
ALWAYS WRITE 1
0
R/W
W
0h
0h
Always write this bit as 1 for the offset correction block to work
properly.
Must write 0
82
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9.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)
9.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page
Figure 144. Register 0A6h
7
0
6
0
5
0
4
0
3
2
1
0
DIGITAL GAIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 55. Register 0A6h Field Descriptions
Bit
7-4
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIGITAL GAIN
R/W
0h
These bits apply a digital gain to the ADC data (before the DDC)
up to 11 dB.
0000 = Default
0001 = 1 dB
1011 = 11 dB
Others = Do not use
9.5.9 Main Digital Page Channel A (680000h, M = 1)
9.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A
Figure 145. Register 000h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIG CORE RESET GBL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 56. Register 000h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIG CORE RESET GBL
R/W
0h
Pulse this bit (0 →1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.
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9.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
Figure 146. Register 0A2h
7
0
6
0
5
0
4
0
3
2
1
0
NQ ZONE EN
R/W-0h
NYQUIST ZONE
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 0A2h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
NQ ZONE EN
R/W
0h
This bit allows for specification of the operating Nyquist zone.
0 = Nyquist zone specification disabled
1 = Nyquist zone specification enabled
2-0
NYQUIST ZONE
R/W
0h
These bits specify the operating Nyquist zone for the analog
correction loop.
Set the NQ ZONE EN bit before programming these bits.
For example, at a 2.6-GSPS chip clock, the first Nyquist zone is
from dc to 1.3 GHz, the second Nyquist zone is from 1.3 GHz to
2.6 GHz, and so on.
000 = First Nyquist zone (dc – fS / 2)
001 = Second Nyquist zone (fS / 2 – fS)
010 = Third Nyquist zone
011 = Fourth Nyquist zone
9.5.10 Main Digital Page Channel B (680100h, M = 1)
9.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
Figure 147. Register 000h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIG CORE RESET GBL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 58. Register 000h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DIG CORE RESET GBL
R/W
0h
Pulse this bit (0 →1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.
84
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9.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B
Figure 148. Register 0A2h
7
0
6
0
5
0
4
0
3
2
1
0
NQ ZONE EN
R/W-0h
NYQUIST ZONE
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 59. Register 0A2h Field Descriptions
Bit
7-4
3
Field
Type
W
Reset
0h
Description
0
Must write 0
NQ ZONE EN
R/W
0h
This bit allows for specification of the operating Nyquist zone.
0 = Nyquist zone specification disabled
1 = Nyquist zone specification enabled
2-0
NYQUIST ZONE
R/W
0h
These bits specify the operating Nyquist zone for the analog
correction loop.
Set the NQ ZONE EN bit before programming these bits.
For example, at a 2.6-GSPS chip clock, first Nyquist zone is
from dc to 1.3 GHz, the second Nyquist zone is from 1.3 GHz to
2.6 GHz, and so on.
000 = First Nyquist zone (dc – fS / 2)
001 = Second Nyquist zone (fS / 2 – fS)
010 = Third Nyquist zone
011 = Fourth Nyquist zone
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9.5.11 JESD Digital Page (6900h, M = 1)
9.5.11.1 Register 001h (address = 001h), JESD Digital Page
Figure 149. Register 001h
7
6
0
5
0
4
3
0
2
1
0
CTRL K
R/W-0h
TESTMODE EN
R/W-0h
LANE ALIGN
R/W-0h
FRAME ALIGN
R/W-0h
TX LINK DIS
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 60. Register 001h Field Descriptions
Bit
Field
Type
Reset
Description
7
CTRL K
R/W
0h
This bit is the enable bit for the number of frames per
multiframe.
0 = Default is five frames per multiframe
1 = Frames per multiframe can be set in register 06h
6-5
4
0
R/W
0h
0
Must write 0
TESTMODE EN
This bit generates a long transport layer test pattern mode
according to section 5.1.6.3 of the JESD204B specification.
0 = Test mode disabled
1 = Test mode enabled
3
2
0
W
0h
0h
Must write 0
LANE ALIGN
R/W
This bit inserts a lane alignment character (K28.3) for the
receiver to align to the lane boundary per section 5.3.3.5 of the
JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
1
0
FRAME ALIGN
TX LINK DIS
R/W
R/W
0h
0h
This bit inserts a frame alignment character (K28.7) for the
receiver to align to the frame boundary per section 5.3.35 of the
JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
This bit disables sending the initial link alignment (ILA) sequence
when SYNC is deasserted.
0 = Normal operation
1 = ILA disabled
86
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9.5.11.2 Register 002h (address = 002h ), JESD Digital Page
Figure 150. Register 002h
7
6
5
0
4
0
3
2
1
0
SYNC REG
R/W-0h
SYNC REG EN
R/W-0h
12BIT MODE
R/W-0h
JESD MODE0
R/W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 61. Register 002h Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC REG
R/W
0h
This bit provides SYNC control through the SPI.
0 = Normal operation
1 = ADC output data are replaced with K28.5 characters
6
SYNC REG EN
R/W
0h
This bit is the enable bit for SYNC control through the SPI.
0 = Normal operation
1 = SYNC control through the SPI is enabled (ignores the
SYNCB input pins)
5-4
3-2
0
W
0h
0h
Must write 0
12BIT MODE
R/W
This bit enables the 12-bit output mode for more efficient data
packing.
00 = Normal operation, 14-bit output
01, 10 = Unused
11 = High-efficient data packing enabled
1-0
JESD MODE0
R/W
0h
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section.
00 = 0
01 = 1
10 = 2
11 = 3
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9.5.11.3 Register 003h (address = 003h), JESD Digital Page
Figure 151. Register 003h
7
6
5
4
3
2
1
0
LMFC MASK
RESET
LINK LAYER TESTMODE
R/W-0h
LINK LAY RPAT
R/W-0h
JESD MODE1
R/W-1h
JESD MODE2
R/W-0h
RAMP 12BIT
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 62. Register 003h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LINK LAYER TESTMODE
R/W
0h
These bits generate a pattern according to section 5.3.3.8.2 of
the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high-frequency jitter pattern)
010 = K28.5 (mixed-frequency jitter pattern)
011 = Repeat initial lane alignment (generates a K28.5 character
and repeats lane alignment sequences continuously)
100 = 12-octet RPAT jitter pattern
4
LINK LAY RPAT
R/W
0h
This bit changes the running disparity in a modified RPAT
pattern test mode (only when link layer test mode = 100).
0 = Normal operation
1 = Changes disparity
3
2
LMFC MASK RESET
JESD MODE1
R/W
R/W
0h
1h
0 = Normal operation
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section
1
0
JESD MODE2
RAMP 12BIT
R/W
R/W
0h
0h
These bits select the configuration register to configure the
correct LMFS frame assemblies for different decimation settings;
see the JESD frame assembly tables in the JESD204B Frame
Assembly section
This bit enables the RAMP test pattern for 12-bit mode only
(LMFS = 82820).
0 = Normal data output
1 = Digital output is the RAMP pattern
9.5.11.4 Register 004h (address = 004h), JESD Digital Page
Figure 152. Register 004h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
REL ILA SEQ
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 004h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
REL ILA SEQ
R/W
0h
These bits delay the generation of the lane alignment sequence
by 0, 1, 2, or 3 multiframes after the code group synchronization.
00 = 0 multiframe delays
01 = 1 multiframe delay
10 = 2 multiframe delays
11 = 3 multiframe delays
88
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9.5.11.5 Register 006h (address = 006h), JESD Digital Page
Figure 153. Register 006h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
SCRAMBLE EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 64. Register 006h Field Descriptions
Bit
Field
Type
Reset
Description
7
SCRAMBLE EN
R/W
0h
This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0
0
W
0h
Must write 0
9.5.11.6 Register 007h (address = 007h), JESD Digital Page
Figure 154. Register 007h
7
0
6
0
5
0
4
3
2
1
0
FRAMES PER MULTIFRAME (K)
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 65. Register 007h Field Descriptions
Bit
7-5
4-0
Field
Type
W
Reset
0h
Description
0
Must write 0
FRAMES PER MULTIFRAME (K)
R/W
0h
These bits set the number of multiframes.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
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9.5.11.7 Register 016h (address = 016h), JESD Digital Page
Figure 155. Register 016h
7
6
5
4
3
2
1
0
LANE 0
R/W-0h
LANE 1
R/W-0h
LANE 2
R/W-0h
LANE 03
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 66. Register 016h Field Descriptions
Bit
7-6
5-4
3-2
1-0
Field
Type
R/W
R/W
R/W
R/W
Reset
0h
Description
LANE 0
LANE 1
LANE 2
LANE 3
For 80X mode: set these bits as 70h. Also set the 80X MODE
EN register bit.
For 40X mode: set these bits as 70h.
For 20X mode: these bits can be used to swap the data on
output lanes as shown in Table 67 and Figure 156.
0h
0h
0h
Table 67. Swapping Data on Output Lanes for 20X Serialization
OUTPUT
LANE0
CARRIES
OUTPUT
LANE1
CARRIES
OUTPUT
LANE2
CARRIES
OUTPUT
LANE3
CARRIES
REGISTER BIT
LANE 0
REGISTER BIT
LANE 1
REGISTER BIT
LANE 2
REGISTER BIT
LANE 3
00
01
10
11
D0
D1
D2
D3
00
01
10
11
D1
D2
D3
D0
00
01
10
11
D2
D3
D0
D1
00
01
10
11
D3
D0
D1
D2
Output Mux
D0
D1
D2
D3
Lane0
Lane1
Lane2
Lane3
Digital JESD Logic
20x
(PLL Mode)
Figure 156. Output Lane Multiplexer
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9.5.11.8 Register 017h (address = 017h), JESD Digital Page
Figure 157. Register 017h
7
0
6
0
5
0
4
0
3
2
1
0
Lane0
POL
Lane1
POL
Lane2
POL
Lane3
POL
W-0h
R/W-0h
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 68. Register 017h Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
Must write 0
Must write 0
0
6-4
3-0
0
R/W
W
0h
Lane[3:0] POL
0h
These bits set the polarity of the individual JESD output lanes.
0 = Polarity as given in the pinout (noninverted)
1 = Inverts polarity (positive, P, or negative, M)
9.5.11.9 Register 032h-035h (address = 032h-035h), JESD Digital Page
Figure 158. Register 032h
7
6
5
4
3
2
2
2
2
1
0
0
0
SEL EMP LANE 0
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 159. Register 033h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 1
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 160. Register 034h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 2
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
Figure 161. Register 035h
7
6
5
4
3
1
0
0
0
SEL EMP LANE 3
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
W-0h
W-0h
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Table 69. Register 032h-035h Field Descriptions
Bit
Field
Type
Reset
Description
7-2
SEL EMP LANE
R/W
0h
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
settled value of the voltage in one bit period.
0 = 0 dB
1 = –1 dB
3 = –2 dB
7 = –4.1 dB
15 = –6.2 dB
31 = –8.2 dB
63 = –11.5 dB
1-0
0
W
0h
Must write 0
9.5.11.10 Register 036h (address = 036h), JESD Digital Page
Figure 162. Register 036h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
80X MODE EN CMOS SYNCB
R/W-0h R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 70. Register 036h Field Descriptions
Bit
Field
Type
Reset
Description
7
80X MODE EN
R/W
0h
This bit enables the 80X mode.
0 = 80X mode disable
1 = 80X mode enable
6
CMOS SYNCB
R/W
0h
This bit enables single-ended control of SYNCB using the
GPIO4 pin (pin 63). The differential SYNCB input is ignored.
0 = Differential SYNCB input
1 = Single-ended SYNCB input using pin 63
5-0
0
W
0h
Must write 0
9.5.11.11 Register 037h (address = 037h), JESD Digital Page
Figure 163. Register 037h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
PLL MODE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 71. Register 037h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
PLL MODE
R/W
0h
These bits select the PLL multiplication factor; see the JESD
tables in the JESD204B Frame Assembly section for settings.
00 = 20X mode
01 = 16X mode
10 = 40X mode (write register 16h with 70h)
11 = 80X mode (the 40X_80X MODE bit in register 16h must
also be set)
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9.5.11.12 Register 03Eh (address = 03Eh), JESD Digital Page
Figure 164. Register 03Eh
7
0
6
5
4
0
3
0
2
0
1
0
0
0
MASK CLKDIV SYSREF
R/W-0h
MASK NCO SYSREF
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 72. Register 03Eh Field Descriptions
Bit
7
Field
Type
W
Reset
0h
Description
0
Must write 0
6
MASK CLKDIV SYSREF
R/W
0h
Use this bit to mask the SYSREF going to the input clock
divider.
0 = Input clock divider is reset when SYSREF is asserted (that
is, when SYSREF transitions from low to high)
1 = Input clock divider ignores SYSREF assertions
5
MASK NCO SYSREF
R/W
W
0h
0h
Use this bit to mask the SYSREF going to the NCO in the DDC
block and LMFC counter of the JESD interface.
0 = NCO phase and LMFC counter are reset when SYSREF is
asserted (that is, when SYSREF transitions from low to high)
1 = NCO and LMFC counter ignore SYSREF assertions
4-0
0
Must write 0
9.5.12 Decimation Filter Page
Direct Addressing, 16-Bit Address, 5000h for Channel A, 5800h for Channel B
9.5.12.1 Register 000h (address = 000h), Decimation Filter Page
Figure 165. Register 000h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DDC EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 73. Register 000h Field Descriptions
Bit
7-1
0
Field
0
Type
W
Reset
0h
Description
Must write 0
DDC EN
R/W
0h
This bit enables the decimation filter and disables the bypass
mode.
0 = Bypass mode (DDC disabled)
1 = Decimation filter enabled
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9.5.12.2 Register 001h (address = 001h), Decimation Filter Page
Figure 166. Register 001h
7
0
6
0
5
0
4
0
3
2
1
0
DECIM FACTOR
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 74. Register 001h Field Descriptions
Bit
7-4
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
DECIM FACTOR
R/W
0h
These bits configure the decimation filter setting.
0000 = Divide-by-4 complex
0001 = Divide-by-6 complex
0010 = Divide-by-8 complex
0011 = Divide-by-9 complex
0100 = Divide-by-10 complex
0101 = Divide-by-12 complex
0110 = Not used
0111 = Divide-by-16 complex
1000 = Divide-by-18 complex
1001 = Divide-by-20 complex
1010 = Divide-by-24 complex
1011 = Not used
1100 = Divide-by-32 complex
9.5.12.3 Register 002h (address = 2h), Decimation Filter Page
Figure 167. Register 002h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DUAL BAND EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 75. Register 002h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DUAL BAND EN
R/W
0h
This bit enables the dual-band DDC filter for the corresponding
channel.
0 = Single-band DDC
1 = Dual-band DDC
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9.5.12.4 Register 005h (address = 005h), Decimation Filter Page
Figure 168. Register 005h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
REAL OUT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 76. Register 005h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
REAL OUT EN
R/W
0h
This bit converts the complex output to real output at 2x the
output rate.
0 = Complex output format
1 = Real output format
9.5.12.5 Register 006h (address = 006h), Decimation Filter Page
Figure 169. Register 006h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DDC MUX
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 77. Register 006h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DDC MUX
R/W
0h
This bit connects the DDC to the alternate channel ADC to
enable up to four DDCs with one ADC and completely turn off
the other ADC channel.
0 = Normal operation
1 = DDC block takes input from the alternate ADC
9.5.12.6 Register 007h (address = 007h), Decimation Filter Page
Figure 170. Register 007h
7
6
5
4
3
2
1
0
DDC0 NCO1 LSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 78. Register 007h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO1 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO1 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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9.5.12.7 Register 008h (address = 008h), Decimation Filter Page
Figure 171. Register 008h
7
6
5
4
3
2
1
0
DDC0 NCO1 MSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 79. Register 008h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO1 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO1 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
9.5.12.8 Register 009h (address = 009h), Decimation Filter Page
Figure 172. Register 009h
7
6
5
4
3
2
1
0
DDC0 NCO2 LSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 80. Register 009h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO2 MSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO2 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
9.5.12.9 Register 00Ah (address = 00Ah), Decimation Filter Page
Figure 173. Register 00Ah
7
6
5
4
3
2
1
0
DDC0 NCO2 MSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 81. Register 00Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO2 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO2 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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9.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page
Figure 174. Register 00Bh
7
6
5
4
3
2
1
0
DDC0 NCO3 LSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 82. Register 00Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO3 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO3 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
9.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page
Figure 175. Register 00Ch
7
6
5
4
3
2
1
0
DDC0 NCO3 MSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 83. Register 00Ch Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC0 NCO3 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO3 of
DDC0 (band 1).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
9.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page
Figure 176. Register 00Dh
7
6
5
4
3
2
1
0
DDC1 NCO4 LSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 84. Register 00Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC1 NCO4 LSB
R/W
0h
These bits are the LSB of the NCO frequency word for NCO4 of
DDC1 (band 2, only when dual-band mode is enabled).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
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9.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page
Figure 177. Register 00Eh
7
6
5
4
3
2
1
0
DDC1 NCO4 MSB
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 85. Register 00Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DDC1 NCO4 MSB
R/W
0h
These bits are the MSB of the NCO frequency word for NCO4 of
DDC1 (band 2, only when dual-band mode is enabled).
The LSB represents fS / (216), where fS is the ADC sampling
frequency.
9.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page
Figure 178. Register 00Fh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
NCO SEL PIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 86. Register 00Fh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
NCO SEL PIN
R/W
0h
This bit enables NCO selection through the GPIO pins.
0 = NCO selection through SPI (see address 0h10)
1 = NCO selection through GPIO pins
9.5.12.15 Register 010h (address = 010h), Decimation Filter Page
Figure 179. Register 010h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
NCO SEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 87. Register 010h Field Descriptions
Bit
7-2
1-0
Field
0
Type
W
Reset
0h
Description
Must write 0
NCO SEL
R/W
0h
These bits enable NCO selection through register setting.
00 = NCO1 selected for DDC 1
01 = NCO2 selected for DDC 1
10 = NCO3 selected for DDC 1
98
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9.5.12.16 Register 011h (address = 011h), Decimation Filter Page
Figure 180. Register 011h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LMFC RESET MODE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 88. Register 011h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0
LMFC RESET MODE
R/W
0h
These bits reset the configuration for all DDCs and NCOs.
00 = All DDCs and NCOs are reset with every LMFC RESET
01 = Reset with first LMFC RESET after DDC start. Afterwards,
reset only when analog clock dividers are resynchronized.
10 = Reset with first LMFC RESET after DDC start. Afterwards,
whenever analog clock dividers are resynchronized, use two
LMFC resets.
11 = Do not use an LMFC reset at all. Reset the DDCs only
when a DDC start is asserted and afterwards continue normal
operation. Deterministic latency is not ensured.
9.5.12.17 Register 014h (address = 014h), Decimation Filter Page
Figure 181. Register 014h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DDC0 6DB GAIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 89. Register 014h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DDC0 6DB GAIN
R/W
0h
This bit scales the output of DDC0 by 2 (6 dB) to compensate
for real-to-complex conversion and image suppression. This
scaling does not apply to the high-bandwidth filter path (divide-
by-4 and -6); see register 1Fh.
0 = Normal operation
1 = 6-dB digital gain is added
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9.5.12.18 Register 016h (address = 016h), Decimation Filter Page
Figure 182. Register 016h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DDC1 6DB GAIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 90. Register 016h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
DDC1 6DB GAIN
R/W
0h
This bit scales the output of DDC0 by 2 (6 dB) to compensate
for real-to-complex conversion and image suppression. This
scaling does not apply to the high-bandwidth filter path (divide-
by-4 and -6); see register 1Fh.
0 = Normal operation
1 = 6-dB digital gain is added
9.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page
Figure 183. Register 01Eh
7
0
6
5
4
3
0
2
0
1
0
0
0
DDC DET LAT
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 91. Register 01Eh Field Descriptions
Bit
7
Field
Type Reset
Description
0
W
0h
0h
Must write 0
6-4
DDC DET LAT
R/W
These bits ensure deterministic latency depending on the decimation setting
used; see Table 92.
3-0
0
W
0h
Must write 0
Table 92. DDC DET LAT Bit Settings
SETTING
10h
COMPLEX DECIMATION SETTING
Divide-by-24, -32 complex
20h
Divide-by-16, -18, -20 complex
Divide-by-by 6, -12 complex
Divide-by-4, -8, -9, -10 complex
40h
50h
100
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9.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page
Figure 184. Register 01Fh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
WBF 6DB GAIN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 93. Register 01Fh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
WBF 6DB GAIN
R/W
0h
This bit scales the output of the wide bandwidth DDC filter by 2
(6 dB) to compensate for real-to-complex conversion and image
suppression. This setting only applies to the high-bandwidth filter
path (divide-by-4 and -6).
0 = Normal operation
1 = 6-dB digital gain is added
9.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page
Figure 185. Register 033h
7
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
CUSTOM PATTERN1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 186. Register 034h
7
6
5
4
3
CUSTOM PATTERN1[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 187. Register 035h
7
6
5
4
3
CUSTOM PATTERN2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 188. Register 036h
7
6
5
4
3
CUSTOM PATTERN2[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 94. Register 033h-036h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOM PATTERN
R/W
0h
These bits set the custom test pattern in address 33h, 34h, 35h,
or 36h.
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9.5.12.22 Register 037h (address = 037h), Decimation Filter Page
Figure 189. Register 037h
7
0
6
0
5
0
4
0
3
2
1
0
TEST PATTERN SEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 95. Register 037h Field Descriptions
Bit
7-3
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
TEST PATTERN SEL
R/W
0h
These bits select the test pattern output on the channel.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating
sequence of 10101010101010 and 01010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 16384
0110 = Single pattern: output data are custom pattern 1 (75h
and 76h)
0111 = Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
102
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9.5.12.23 Register 038h (address = 038h), Decimation Filter Page
Figure 190. Register 038h
7
6
5
4
3
2
1
0
TEST PATTERN DDC2 Q-DATA
R/W-0h
TEST PATTERN DDC2 I-DATA
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 96. Register 038h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
TEST PATTERN DDC2 Q-DATA
R/W
0h
These bits select the test patten for the Q stream of the DDC2.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating
sequence of 10101010101010 and 01010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 65535
0110 = Single pattern: output data are a custom pattern 1 (75h
and 76h)
0111 Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
3-0
TEST PATTERN DDC2 I-DATA
R/W
0h
These bits select the test patten for the I stream of the DDC2.
0000 = Normal operation using ADC output data
0001 = Outputs all 0s
0010 = Outputs all 1s
0011 = Outputs toggle pattern: output data are an alternating
sequence of 10101010101010 and 01010101010101
0100 = Output digital ramp: output data increment by one LSB
every clock cycle from code 0 to 65535
0110 = Single pattern: output data are a custom pattern 1 (75h
and 76h)
0111 Double pattern: output data alternate between custom
pattern 1 and custom pattern 2
1000 = Deskew pattern: output data are AAAAh
1001 = SYNC pattern: output data are FFFFh
9.5.12.24 Register 039h (address = 039h), Decimation Filter Page
Figure 191. Register 039h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
USE COMMON TEST
PATTERN
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 97. Register 039h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
USE COMMON TEST PATTERN
R/W
0h
0 = Each data stream sends test patterns programmed by
bits[3:0] of register 37h.
1 = Test patterns are individually programmed for the I and Q
stream of each DDC using the TEST PATTERN DDCx y-DATA
register bits (where x = 1 or 2 and y = I or Q).
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9.5.12.25 Register 03Ah (address = 03Ah), Decimation Filter Page
Figure 192. Register 03Ah
7
0
6
0
5
0
4
0
3
0
2
0
1
0
TEST PAT RES
R/W-0h
TP RES EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 98. Register 03Ah Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0
TEST PAT RES
R/W
0h
Pulsing this bit resets the test pattern. The test pattern reset
must be enabled first (bit D0).
0 = Normal operation
1 = Reset the test pattern
0
TP RES EN
R/W
0h
This bit enables the test pattern reset.
0 = Reset disabled
1 = Reset enabled
104
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9.5.13 Power Detector Page
9.5.13.1 Register 000h (address = 000h), Power Detector Page
Figure 193. Register 000h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PKDET EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 99. Register 000h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
PKDET EN
R/W
0h
This bit enables the peak power and crossing detector.
0 = Power detector disabled
1 = Power detector enabled
9.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page
Figure 194. Register 001h
7
6
5
4
3
2
2
1
1
0
0
BLKPKDET [7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 195. Register 002h
7
6
5
4
3
BLKPKDET [15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 100. Register 001h-002h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BLKPKDET
R/W
0h
This register specifies the block length in terms of number of
samples (S`) used for peak power computation. Each sample S`
is a peak of 8 actual ADC samples. This parameter is a 17-bit
value directly in linear scale. In decimation mode, the block
length must be a multiple of a divide-by-4 or -6 complex: length
= 5 × decimation factor.
The divide-by-8 to -32 complex: length = 10 × decimation factor.
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9.5.13.3 Register 003h (address = 003h), Power Detector Page
Figure 196. Register 003h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
BLKPKDET[16]
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 101. Register 003h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
BLKPKDET[16]
R/W
0h
This register specifies the block length in terms of number of
samples (S`) used for peak power computation. Each sample S`
is a peak of 8 actual ADC samples. This parameter is a 17-bit
value directly in linear scale. In decimation mode, the block
length must be a multiple of a divide-by-4 or -6 complex: length
= 5 × decimation factor.
The divide-by-8 to -32 complex: length = 10 × decimation factor.
9.5.13.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page
Figure 197. Register 007h
7
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
BLKTHHH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 198. Register 008h
7
6
5
4
3
BLKTHHL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 199. Register 009h
7
6
5
4
3
BLKTHLH
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 200. Register 00Ah
7
6
5
4
3
BLKTHLL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 102. Register 007h-00Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BLKTHHH
BLKTHHL
BLKTHLH
BLKTHLL
R/W
0h
These registers set the four different thresholds for the
hysteresis function threshold values from 0 to 256 (2TH), where
256 is equivalent to the peak amplitude.
Example: BLKTHHH is set to –2 dBFS from peak: 10(-2 / 20) × 256
= 203, then set 5407h, 5C07h = CBh.
106
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9.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page
Figure 201. Register 00Bh
7
6
5
4
3
2
2
1
1
0
0
DWELL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 202. Register 00Ch
7
6
5
4
3
DWELL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 103. Register 00Bh-00Ch Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DWELL
R/W
0h
DWELL time counter.
When the computed block peak crosses the upper thresholds
BLKTHHH or BLKTHLH, the peak detector output flags are set.
In order to be reset, the computed block peak must remain
continuously lower than the lower threshold (BLKTHHL or
BLKTHLL) for the period specified by the DWELL value. This
threshold is 16 bits, is specified in terms of fS / 8 clock cycles,
and must be set to 0 for the crossing detector. Example: if fS = 3
GSPS, fS / 8 = 375 MHz, and DWELL = 0100h then the DWELL
time = 29 / 375 MHz = 1.36 µs.
9.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page
Figure 203. Register 00Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FILT0LPSEL
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 104. Register 00Dh Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
FILT0LPSEL
R/W
0h
This bit selects either the block detector output or 2-bit output as
the input to the IIR filter.
0 = Use the output of the high comparators (HH and HL) as the
input of the IIR filter
1 = Combine the output of the high (HH and HL) and low (LH
and LL) comparators to generate a 3-level input to the IIR filter
(–1, 0, 1)
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9.5.13.7 Register 00Eh (address = 00Eh), Power Detector Page
Figure 204. Register 00Eh
7
0
6
0
5
0
4
0
3
2
1
0
TIMECONST
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 105. Register 00Eh Field Descriptions
Bit
7-4
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
TIMECONST
R/W
0h
These bits set the crossing detector time period for N = 0 to 15
as 2N × fS / 8 clock cycles. The maximum time period is 32768 ×
fS / 8 clock cycles (approximately 100 µs at 2.6 GSPS).
9.5.13.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power
Detector Page
Figure 205. Register 00Fh
7
6
5
4
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
FIL0THH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 206. Register 010h
7
6
5
4
3
FIL0THH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 207. Register 011h
7
6
5
4
3
FIL0THL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 208. Register 012h
7
6
5
4
3
FIL0THL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 209. Register 016h
7
6
5
4
3
FIL1THH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
108
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Figure 210. Register 017h
7
6
5
4
3
2
2
2
1
1
1
0
0
0
FIL1THH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 211. Register 018h
7
6
5
4
3
FIL1THL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 212. Register 019h
7
6
5
4
3
FIL1THL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 106. Register 00Fh, 010h, 011h, 012h, 016h, 017h, 018h, and 019h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FIL0THH
FIL0THL
FIL1THH
FIL1THL
R/W
0h
Comparison thresholds for the crossing detector counter. This
threshold is 16 bits in 2.14 signed notation. A value of 1 (4000h)
corresponds to 100% crossings, a value of 0.125 (0800h)
corresponds to 12.5% crossings.
9.5.13.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page
Figure 213. Register 013h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IIR0 2BIT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Figure 214. Register 01Ah
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IIR1 2BIT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 107. Register 013h and 01Ah Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
IIR0 2BIT EN
IIR1 2BIT EN
R/W
0h
This bit enables 2-bit output format of the IIR0 and IIR1 output
comparators.
0 = Selects 1-bit output format
1 = Selects 2-bit output format
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9.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page
Figure 215. Register 01Dh
7
6
5
4
3
2
1
1
0
DWELLIIR[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 216. Register 01Eh
7
6
5
4
3
2
0
DWELLIIR[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 108. Register 01Dh-01Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DWELLIIR
R/W
0h
DWELL time counter for the IIR output comparators. When the
IIR filter output crosses the upper thresholds FIL0THH or
FIL1THH, the IIR peak detector output flags are set. In order to
be reset, the output of the IIR filter must remain continuously
lower than the lower threshold (FIL0THL or FIL1THL) for the
period specified by the DWELLIIR value. This threshold is 16
bits and is specified in terms of fS / 8 clock cycles.
Example: if fS = 2.6 GSPS, fS / 8 = 325 MHz, and DWELLIIR =
0100h, then the DWELL time = 29 / 325 MHz = 1.57 µs.
9.5.13.11 Register 020h (address = 020h), Power Detector Page
Figure 217. Register 020h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RMSDET EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 109. Register 020h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
RMSDET EN
R/W
0h
This bit enables the RMS power detector.
0 = Power detector disabled
1 = Power detector enabled
110
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9.5.13.12 Register 021h (address = 021h), Power Detector Page
Figure 218. Register 021h
7
0
6
0
5
0
4
3
2
1
0
PWRDETACCU
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 110. Register 021h Field Descriptions
Bit
7-5
4-0
Field
Type
W
Reset
0h
Description
0
Must write 0
PWRDETACCU
R/W
0h
These bits program the block length to be used for RMS power
computation.
The block length is defined in terms of fS / 8 clocks and can be
programmed as 2M, where M = 0 to 16.
9.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page
Figure 219. Register 022h
7
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
PWRDETH[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 220. Register 023h
7
6
5
4
3
PWRDETH[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 221. Register 024h
7
6
5
4
3
PWRDETL[7:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 222. Register 025h
7
6
5
4
3
PWRDETL[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 111. Register 022h-025h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PWRDETH[15:0]
PWRDETL[15:0]
R/W
0h
The computed average power is compared against these high and low
thresholds. One LSB of the thresholds represents 1 / 216
.
Example: if PWRDETH is set to –14 dBFS from peak, (10(–14 / 20))2 × 216 = 2609,
then set 5422h, 5423h, 5C22h, 5C23h = 0A31h.
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9.5.13.14 Register 027h (address = 027h), Power Detector Page
Figure 223. Register 027h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RMS 2BIT EN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 112. Register 027h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0
RMS 2BIT EN
R/W
0h
This bit enables 2-bit output format on the RMS output
comparators.
0 = Selects 1-bit output format
1 = Selects 2-bit output format
9.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page
Figure 224. Register 02Bh
7
0
6
0
5
0
4
3
0
2
0
1
0
0
0
RESET AGC
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 113. Register 02Bh Field Descriptions
Bit
7-5
4
Field
Type
W
Reset
0h
Description
0
Must write 0
RESET AGC
R/W
0h
After configuration, the AGC module must be reset and then
brought out of reset to start operation.
0 = Clear AGC reset
1 = Set AGC reset
Example: set 542Bh to 10h and then to 00h.
3-0
0
W
0h
Must write 0
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9.5.13.16 Register 037h (address = 037h), Power Detector Page
Figure 225. Register 037h
7
0
6
0
5
0
4
0
3
2
1
0
IODIR GPIO4
R/W-0h
IODIR GPIO3
R/W-0h
IODIR GPIO2
R/W-0h
IODIR GPIO1
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 114. Register 037h Field Descriptions
Bit
7-4
3-0
Field
Type
W
Reset
0h
Description
0
Must write 0
IODIRGPIO[4:1]
R/W
0h
These bits select the output direction for the GPIO[4:1] pins.
0 = Input (for the NCO control)
1 = Output (for the AGC alarm function)
9.5.13.17 Register 038h (address = 038h), Power Detector Page
Figure 226. Register 038h
7
0
6
0
5
4
3
0
2
0
1
0
INSEL1
R/W-0h
INSEL0
R/W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 115. Register 038h Field Descriptions
Bit
7-6
5-4
Field
0
Type
W
Reset
0h
Description
Must write 0
INSEL1
R/W
0h
These bits select which GPIO pin is used for the INSEL1 bit.
00 = GPIO4
01 = GPIO1
10 = GPIO3
11 = GPIO2
Table 116 lists the NCO selection, based on the bit settings of
the INSEL pins.
3-2
1-0
0
W
0h
0h
Must write 0
INSEL0
R/W
These bits select which GPIO pin is used for the INSEL0 bit.
00 = GPIO4
01 = GPIO1
10 = GPIO3
11 = GPIO2
Table 116 lists the NCO selection, based on the bit settings of
the INSEL pins.
Table 116. INSEL Bit Settings
INSEL1
INSEL2
NCO SELECTED
NCO1
0
0
1
1
0
1
0
1
NCO2
NCO3
n/a
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9.5.13.18 Power Detector Page (Direct Addressing, 16-Bit Address, 5400h)
9.5.13.18.1 Register 032h-035h (address = 032h-035h), Power Detector Page
Figure 227. Register 032h
7
6
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
OUTSEL GPIO1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 228. Register 033h
7
6
5
4
3
OUTSEL GPIO2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 229. Register 034h
7
6
5
4
3
OUTSEL GPIO3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Figure 230. Register 035h
7
6
5
4
3
OUTSEL GPIO4
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 117. Register 032h-035h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
OUTSEL GPIOx
R/W
0h
These bits set the function or signal for each GPIO pin.
0 = IIR PK DET0[0] of channel A
1 = IIR PK DET0[1] of channel A (2-bit mode)
2 = IIR PK DET1[0] of channel A
3 = IIR PK DET1[1] of channel A (2-bit mode)
4 = BLKPKDETH of channel A
5 = BLKPKDETL of channel A
6 = PWR Det[0] of channel A
7 = PWR Det[1] of channel A (2-bit mode)
8 = FOVR of channel A
9-17 = Repeat outputs 0-8 but for channel B instead
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Start-Up Sequence
The steps in Table 118 are recommended as the power-up sequence when the ADC32RF42 is in bypass mode
with a 12-bit output (LMFS = 82820).
Table 118. Initialization Sequence
PAGE, REGISTER
ADDRESS AND DATA
STEP
DESCRIPTION
COMMENT
Supply all supply voltages. There is no required
power-supply sequence for the 1.15 V, 1.2 V,
and 1.9 V supplies, and can be supplied in any
order.
1
—
—
2
3
Provide the SYSREF signal.
—
—
—
—
Pulse a hardware reset (low-to-high-to-low) on
pins 33 and 34.
The Power-up config file contains analog
trim registers that are required for best
performance of the ADC. Write these
registers every time after power up.
Write the register addresses described in the
PowerUpConfig file.
See the files located in
SBAA226
4
5
Write the register addresses mentioned in the
ILConfigNyqX_ChA file, where X is the Nyquist
zone.
See the files located in
SBAA226
Based on the signal band of interest, provide
the Nyquist zone information to the device.
Write the register addresses mentioned in the
ILConfigNyqX_ChB file, where X is the Nyquist
zone.
See the files located in
SBAA226
This step optimizes device’ performance by
reducing interleaving mismatch errors.
6
Wait for 50 ms for the device to estimate the
interleaving errors.
6.1
—
—
Depending upon the Nyquist band of operation,
choose and write the registers from the
appropriate file, NLConfigNyqX_ChA, where X
is the Nyquist zone.
See the files located in
SBAA226
Third-order nonlinearity of the device is
optimized by this step for channel A.
7
Depending upon the Nyquist band of operation,
choose and write the registers from the
appropriate file, NLConfigNyqX_ChB, where X
is the Nyquist zone.
See the files located in
SBAA226
Third-order nonlinearity of the device is
optimized by this step for channel B.
7.1
8
Configure the JESD interface and DDC block
by writing the registers mentioned in the DDC
Config file.
Determine the DDC and JESD interface
LMFS options. Program these options in this
step.
See the files located in
SBAA226
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10.1.2 Hardware Reset
Timing information for the hardware reset is shown in Figure 231 and Table 119.
Power Supplies
t1
RESET
t2
t3
SEN
Figure 231. Hardware Reset Timing Diagram
Table 119. Hardware Reset Timing Information
MIN
TYP
MAX
UNIT
ms
µs
t1
t2
t3
Power-on delay from power-up to active high RESET pulse
1
1
Reset pulse duration: active high RESET pulse duration
Register write delay from RESET disable to SEN active
100
ns
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10.1.3 SNR and Clock Jitter
The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,
and jitter, as shown in Equation 5. The quantization noise is typically not noticeable in pipeline converters and is
84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the
SNR for higher input frequencies.
2
2
2
SNRQuantization Noise
SNRThermal Noise
SNRJitter
20
≈
∆
’
÷
÷
◊
≈
’
÷
÷
◊
≈
’
÷
-
-
-
∆
20
20
∆
SNRADC dBc = -20log 10
+ 10
+ 10
»
ÿ
⁄
∆
«
∆
«
∆
«
÷
◊
(5)
(6)
The SNR limitation resulting from sample clock jitter can be calculated by Equation 6:
SNRJitter dBc = -20log 2p ì f ì tJitter
»
ÿ
⁄
IN
The total clock jitter (TJitter) has two components: the internal aperture jitter (90 fS) is set by the noise of the clock
input buffer and the external clock jitter. TJitter can be calculated by Equation 7:
2
2
tJitter
=
t
,
+ t
Jitter Ext _Clock _Input
Aperture_ ADC
(7)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.
The ADC32RF44 has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 fS. The
SNR, depending on the amount of external jitter for different input frequencies, is shown in Figure 232.
63
62
61
60
59
58
57
35 fs
50 fs
56
100 fs
150 fs
200 fs
55
54
53
52
10
100
1000
5000
Input Frequency (MHz)
D048
Figure 232. ADC SNR vs Input Frequency and External Clock Jitter
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10.1.3.1 External Clock Phase Noise Consideration
External clock jitter can be calculated by integrating the phase noise of the clock source out to approximately two
times of the ADC sampling rate (2 × fS), as shown in Figure 233. In order to maximize the ADC SNR, an external
band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the
broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the
band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a
certain input frequency.
Clock Phase Noise
Integration Bandwidth
Frequency Offset
fmin
2 ì fS
Figure 233. Integration Bandwidth for Extracting Jitter from Clock Phase Noise
However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity,
the phase noise information can be used directly to estimate the noise budget contribution at a certain offset
frequency, as shown in Figure 234.
Inband Blocker
Clock Phase Noise
Modulated Onto the Blocker
ADC Noise Floor
Wanted Signal
Figure 234. Small Wanted Signal in Presence of Interferer
At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example,
the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the
signal band of interest is too large, the wanted signal cannot not be recovered.
The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and
frequency of the input signal. The ADC sampling rate scales the clock phase noise, as shown in Equation 8.
≈
∆
«
’
÷
◊
fS
ADCNSD dBc / Hz = PN
dBc / Hz - 20 ì log
(
)
(
)
CLK
f
IN
(8)
Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock
can be calculated.
118
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10.1.4 Power Consumption in Different Modes
The ADC32RF44 consumes approximately 5.8 W of power when both channels are active with a 12-bit,
2.6-GSPS output and a DDC option is not used (bypass mode). When different DDC options are used, the power
consumption on the DVDD supply changes by a small amount but remains unaffected on other supplies. In the
applications requiring just one channel to be active, channel A must be chosen as the active channel and
channel B can be powered down. Power consumption reduces to approximately 3.5 W in single-channel
operation with a 12-bit, 2.6-GSPS output (bypass mode).
Table 120 shows power consumption in different DDC modes for dual-channel and single-channel operation.
Table 120. Power Consumption in Different DDC Modes
DECIMATION
OPTION
ACTIVE
CHANNEL
TOTAL POWER
(mW)
ACTIVE DDC
AVDD1P9 (mA)
AVDD1P2 (mA)
DVDD1P2 (mA)
Bypass mode
Divide-by-4
Divide-by-8
Divide-by-8
Divide-by-16
Divide-by-16
Divide-by-24
Divide-by-24
Divide-by-32
Divide-by-32
Bypass mode
Divide-by-4
Divide-by-8
Divide-by-8
Divide-by-16
Divide-by-16
Divide-by-24
Divide-by-24
Divide-by-32
Divide-by-32
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channels A, B
Channel A
NA
1730
1725
1724
1724
1724
1725
1721
1722
1721
1721
940
860
867
854
860
870
868
867
865
860
860
550
556
553
546
562
553
561
553
557
549
1416
1530
1674
1466
1674
1448
1684
1391
1534
1326
913
5904
6034
6183
5951
6201
5941
6204
5866
6023
5784
3468
3525
3601
3463
3621
3490
3598
3450
3524
3387
Single
Dual
Single
Dual
Single
Dual
Single
Dual
Single
NA
Channel A
Single
Dual
939
958
Channel A
941
1024
911
Channel A
Single
Dual
941
Channel A
937
1039
930
Channel A
Single
Dual
939
Channel A
935
1023
899
Channel A
Single
Dual
937
Channel A
936
961
Channel A
Single
937
848
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10.1.5 Using DC Coupling in the ADC32RF44
The ADC32RF44 can be used in dc-coupling applications. However, the following points must be considered
when designing the system:
1. Ensure that the correct common-mode voltage is used at the ADC analog inputs.
The analog inputs are internally self-biased to VCM through approximately a 33-Ω resistor. The internal
biasing resistors also function as a termination resistor. However, if a different termination is required, the
external resistor RTERM can be differentially placed between the analog inputs, as shown in Figure 235. The
amplifier VOCM pin is recommended to be driven from the CM pin of the ADC to help the amplifier output
common-mode voltage track the required common-mode voltage of the ADC.
ADC32RF45
ADC
Digital
INxP
OUTP
RS / 2
RDC/2(2)
JESD
204B
Interface
Digital
Ouput
Low-Pass
Filter
Offset
Corrector
Interleaving
Engine
DDC
Block
RTERM
Driving Amp
(1)
RCM
VCM
RDC / 2
RS / 2
OUTM
VOCM
INxM
CM
Copyright © 2016, Texas Instruments Incorporated
Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω.
RDC is approximately 65 Ω.
Figure 235. The ADC32RF44 in a DC-Coupling Application
2. Ensure that the correct SPI settings are written to the ADC.
As shown in Figure 236, the ADC32RF44 has a digital block that estimates and corrects the offset mismatch
among four interleaving ADC cores for a given channel.
Offset Corrector
Data Out
Data In
+
+
œ
Freeze
Correction
Disable
Correction
Estimator
Figure 236. Offset Corrector in the ADC32RF44
The offset corrector block nullifies dc, fS / 8, fS / 4, 3 fS / 8, and fS / 2. The resulting spectrum becomes free
from static spurs at these frequencies. The corrector continuously processes the data coming from the
interleaving ADC cores and cannot distinguish if the tone at these frequencies is part of signal or if the tone
originated from a mismatch among the interleaving ADC cores. Thus, in applications where the signal is
present at these frequencies, the offset corrector block can be bypassed.
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10.1.5.1 Bypassing the Offset Corrector Block
When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC
output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the
ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector
is frozen so that the last estimated value is held. Required register writes are provided in Table 121.
Table 121. Freezing and Bypassing the Offset Corrector Block
STEP
REGISTER WRITE
COMMENT
STEPS FOR FREEZING THE CORRECTOR BLOCK
1
2
—
Signal source is turned off. The device detects an idle channel at its input.
Wait for at least 0.4 ms for the corrector to estimate the internal offset
—
Address 4001h, value 00h
Address 4002h, value 00h
Address 4003h, value 00h
Address 4004h, value 61h
Address 6068h, value C2h
Address 4003h, value 01h
Address 6068h, value C2h
—
Select Offset Corr Page Channel A
3
Freeze the corrector for channel A
Select Offset Corr Page Channel B
Freeze the corrector for channel B
Signal source can now be turned on
4
STEPS FOR BYPASSING THE CORRECTOR BLOCK
Address 4001h, value 00h
Address 4002h, value 00h
Address 4003h, value 00h
Address 4004h, value 61h
Address 6068h, value 46h
Address 4003h, value 01h
Address 6068h, value 46h
—
1
Select Offset Corr Page Channel A
Disable the corrector for channel A
Select Offset Corr Page Channel B
Disable the corrector for channel B
10.1.5.1.1 Effect of Temperature
Figure 237 and Figure 238 show the behavior of nfS / 8 tones with respect to temperature when the offset
corrector block is frozen or disabled.
-40
-50
-20
-30
-40
-50
-60
-70
-80
-90
-100
Average of fS/8
Average of 3fS/8
Average of fS/4
Average of fS/4
Average of fS/8
Average of 3fS/8
-60
-70
-80
-90
-100
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 237. Offset Corrector Block Frozen at Room
Temperature
Figure 238. Offset Corrector Block Disabled
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10.2 Typical Application
The ADC32RF44 is designed for wideband receiver applications demanding high dynamic range over a large
input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 239.
Decoupling capacitors with low ESL are recommended to be placed as close as possible at the pins indicated in
Figure 239. Additional capacitors can be placed on the remaining power pins.
DVDD
Matching Network
10 kꢀ
0.1 ꢁF
Driver
SPI Master
GND
DVDD
0.1 ꢁF
0.1 ꢁF
0.1 ꢁF
0.1 ꢁF
10 nF
AVDD19
AVDD
AVDD19
AVDD
DVDD
100-ꢀ Differential
18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
10 nF
DB2P
DB2M
DVDD
DB1P
DB1M
GND
GPIO1
GPIO2
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DVDD
10 nF
GND
GPIO3
10 nF
10 nF
VCM
0.1 ꢁF
GND
0.1 ꢁF
AVDD19
AVDD19
AVDD
DB0P
DB0M
DVDD
GPIO4
DA0M
DA0P
GND
Matching
Network
AVDD
0.1 ꢁF
GND
DVDD
CLKINP
CLKINM
GND
0.1 ꢁF
ADC32RF44
GND Pad (Back Side)
GND
10 nF
0.1 ꢁF
AVDD
Low Jitter Clock
Generator
AVDD19
GND
AVDD19
0.1 ꢁF
10 nF
10 nF
DA1M
DA1P
DVDD
DA2M
DA2P
FPGA
SYSREFP
SYSREFM
SYNCBP
SYNCBM
DVDD
10 nF
GND
10 nF
10 nF
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
100-ꢀ Differential
AVDD19
AVDD
DVDD
AVDD
AVDD19
0.1 ꢁF
DVDD
0.1 ꢁF
0.1 ꢁF
GND
Driver
0.1 ꢁF
Matching Network
Copyright © 2017, Texas Instruments Incorporated
Figure 239. Typical Application Implementation Diagram
122
Copyright © 2017, Texas Instruments Incorporated
ADC32RF44
www.ti.com.cn
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
Typical Application (continued)
10.2.1 Design Requirements
10.2.1.1 Transformer-Coupled Circuits
Typical applications involving transformer-coupled circuits are discussed in this section. To ensure good
amplitude and phase balance at the analog inputs, transformers (such as TC1-1-13 and TC1-1-43) can be used
from the dc to 1000-MHz range and from the 1000-MHz to 4-GHz range of input frequencies, respectively. When
designing the driving circuits, the ADC input impedance (or SDD11) must be considered.
By using the simple drive circuit of Figure 240, uniform performance can be obtained over a wide frequency
range. The buffers present at the analog inputs of the device help isolate the external drive source from the
switching currents of the sampling circuit.
5 ꢀ
(Optional)
0.1 ꢁF
T2
CHx_INP
T1
0.1 ꢁF
RIN
CIN
5 ꢀ
(Optional)
0.1 ꢁF
CHx_INM
1:1
1:1
TI Device
Copyright © 2016, Texas Instruments Incorporated
Figure 240. Input Drive Circuit
10.2.2 Detailed Design Procedure
For optimum performance, the analog inputs must be driven differentially. This architecture improves common-
mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input
pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 240.
10.2.3 Application Curves
Figure 241 and Figure 242 show the typical performance at 100 MHz and 1850 MHz, respectively.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
260
520
780
1040
1300
0
260
520
780
1040
1300
Frequency (MHz)
Frequency (MHz)
D001
D003
SNR = 62.7 dBFS, SINAD = 62 dBFS,
SNR = 58.5 dBFS, SINAD = 58.2 dBFS,
HD2 = –68 dBc, HD3 = –83 dBc, SFDR = 68 dBc,
THD = 68 dBc, IL spur = 83 dBc,
HD2 = –76 dBc, HD3 = –71 dBc, SFDR = 71 dBc,
THD = 70 dBc, IL spur = 77 dBc,
SFDR (non HD2, HD3) = 74 dBc
SFDR (non HD2, HD3) = 74 dBc
Figure 241. FFT for 100-MHz Input Frequency
Figure 242. FFT for 1850-MHz Input Frequency
Copyright © 2017, Texas Instruments Incorporated
123
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
11 Power Supply Recommendations
The DVDD power supply (1.15 V) must be stable before ramping up the AVDD19 supply (1.9 V), as shown in
Figure 243. The AVDD supply (1.15 V) can come up in any order during the power sequence. The power
supplies can ramp up at any rate and there is no hard requirement for the time delay between DVDD (1.15 V)
ramping up to AVDD (1.9 V) ramping up (which can be in orders of microseconds but is recommended to be a
few milliseconds).
AVDD
(1.15 V)
DVDD
(1.15 V)
AVDD19
(1.9 V)
Figure 243. Power Sequencing for the ADC32RF8x Family of Devices
12 Layout
12.1 Layout Guidelines
The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A
layout diagram of the EVM top layer is provided in Figure 244. The ADC32RF45/RF80 EVM Quick Startup Guide
provides a complete layout of the EVM. Some important points to remember during board layout are:
•
•
•
Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package
level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown
in the reference layout of Figure 244 as much as possible.
In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling. This configuration is also maintained on the reference layout of Figure 244 as much as
possible.
Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output
traces must not be kept parallel to the analog input traces because this configuration can result in coupling
from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver
[such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be
matched in length to avoid skew among outputs.
•
At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the
device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
124
Copyright © 2017, Texas Instruments Incorporated
ADC32RF44
www.ti.com.cn
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
12.2 Layout Example
Figure 244. ADC32RF44EVM Layout
版权 © 2017, Texas Instruments Incorporated
125
ADC32RF44
ZHCSG60A –FEBRUARY 2017–REVISED MARCH 2017
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档:
•
•
《ADC32RF45/RF80 EVM 快速启动指南》
《ADC32RF45 的配置文件》
13.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册,即可收到任意产
品信息更改每周摘要。有关更改的详细信息,请查看任意已修订文档中包含的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时,我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本,请参见左侧的导航栏。
126
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC32RF44IRMP
ADC32RF44IRMPR
ADC32RF44IRMPT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RMP
RMP
RMP
72
72
72
168
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
AZ32RF44
1500 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
AZ32RF44
AZ32RF44
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC32RF44IRMPR
VQFN
RMP
72
1500
330.0
24.4
10.25 10.25 2.25
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RMP 72
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
ADC32RF44IRMPR
1500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADC32RF44IRMP
RMP
VQFNP
72
168
8 X 21
150
315 135.9 7620 14.65
11
11.95
Pack Materials-Page 3
PACKAGE OUTLINE
RMP0072A
VQFN - 0.9 mm max height
SCALE 1.700
VQFN
10.1
9.9
A
B
PIN 1 ID
10.1
9.9
0.9 MAX
0.05
0.00
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
19
36
18
37
SYMM
4X
8.5
8.5 0.1
PIN 1 ID
(R0.2)
1
54
0.30
0.18
72X
72
55
68X 0.5
SYMM
0.5
0.3
0.1
C B
A
72X
0.05
C
4221047/B 02/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RMP0072A
VQFN - 0.9 mm max height
VQFN
(
8.5)
SYMM
72X (0.6)
SEE DETAILS
55
72
1
54
72X (0.24)
(0.25) TYP
SYMM
(9.8)
(1.315) TYP
68X (0.5)
(
0.2) TYP
VIA
37
18
19
36
(1.315) TYP
(9.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4221047/B 02/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RMP0072A
VQFN - 0.9 mm max height
VQFN
(9.8)
72X (0.6)
(1.315) TYP
72
55
1
54
72X (0.24)
(1.315)
TYP
(0.25) TYP
SYMM
(9.8)
(1.315)
TYP
68X (0.5)
METAL
TYP
37
18
(
0.2) TYP
VIA
19
36
36X ( 1.115)
(1.315) TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
62% PRINTED SOLDER COVERAGE BY AREA
SCALE:8X
4221047/B 02/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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