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ADC32RF80, ADC32RF83

SBAS774A –MAY 2016–REVISED DECEMBER 2016

ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices

1 Features

3 Description

The ADC32RF8x (ADC32RF80 and ADC32RF83) is

a 14-bit, 3-GSPS, dual-channel telecom receiver and

feedback device family that supports RF sampling

with input frequencies up to 4 GHz and beyond.

Designed for high signal-to-noise ratio (SNR), the

ADC32RF8x family delivers a noise spectral density

of –155 dBFS/Hz as well as dynamic range and

channel isolation over a large input frequency range.

The buffered analog input with on-chip termination

provides uniform input impedance across a wide

frequency range and minimizes sample-and-hold

glitch energy.

1

•

14-Bit, Dual-Channel, 3-GSPS ADC

Noise Floor: –155 dBFS/Hz

•

RF Input Supports Up to 4.0 GHz

Aperture Jitter: 90 f_S

Channel Isolation: 95 dB at f_IN= 1.8 GHz

Spectral Performance (f_IN= 900 MHz, –2 dBFS):

–

SNR: 60.1 dBFS

SFDR: 66-dBc HD2, HD3

SFDR: 76-dBc Worst Spur

•

Spectral Performance (f_IN= 1.85 GHz, –2 dBFS):

Each channel can be connected to a dual-band,

digital down-converter (DDC) with up to three

independent, 16-bit numerically-controlled oscillators

(NCOs) per DDC for phase-coherent frequency

hopping. Additionally, the ADC is equipped with front-

end peak and RMS power detectors and alarm

functions to support external automatic gain control

(AGC) algorithms.

–

SNR: 58.9 dBFS

SFDR: 67-dBc HD2, HD3

SFDR: 76-dBc Worst Spur

On-Chip Digital Down-Converters:

–

Up to 4 DDCs (Dual-Band Mode)

Up to 3 Independent NCOs per DDC

•

On-Chip Input Clamp for Overvoltage Protection

The ADC32RF8x supports the JESD204B serial

interface with subclass 1-based deterministic latency

using data rates up to 12.5 Gbps with up to four lanes

per ADC. The device is offered in a 72-pin VQFN

package (10 mm × 10 mm) and supports the

industrial temperature range (–40°C to +85°C).

Programmable On-Chip Power Detectors with

Alarm Pins for AGC Support

•

On-Chip Dither

On-Chip Input Termination

Input Full-Scale: 1.35 V_PP

Support for Multi-Chip Synchronization

JESD204B Interface:

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

ADC32RF8x

VQFN (72)

10.00 mm × 10.00 mm

–

Subclass 1-Based Deterministic Latency

4 Lanes Per Channel at 12.5 Gbps

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

Power Dissipation: 3.2 W/Ch at 3.0 GSPS

72-Pin VQFN Package (10 mm × 10 mm)

Simplified Block Diagram

2 Applications

Buffer

DA[0,1]P/M

DA[2,3]P/M

Digital Block

N

50 ꢀ

!5/

ADC

!5/

Interleave

Correction

INAP/M

•

Multi-Carrier GSM Cellular Infrastructure Base

Stations

FAST

DET.

NCO

•

Telecommunications Receivers

DPD Observation Receivers

NCO

CTRL

GPIO1..4

CLKINP/M

SYSREFP/M

SYNCBP/M

PLL

Backhaul Receivers

NCO

RF Repeaters and Distributed Antenna Systems

FAST

DET.

0º/180º

Clock

NCO

N

Buffer

DB[0,1]P/M

DB[2,3]P/M

Digital Block

!5/

Interleave

Correction

ADC

INBP/M

50 ꢀ

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADC32RF80, ADC32RF83

SBAS774A –MAY 2016–REVISED DECEMBER 2016

www.ti.com

Table of Contents

8.1 Overview ................................................................. 27

8.2 Functional Block Diagram ....................................... 27

8.3 Feature Description................................................. 28

8.4 Device Functional Modes........................................ 55

8.5 Register Maps......................................................... 68

Application and Implementation ...................... 119

9.1 Application Information.......................................... 119

9.2 Typical Application ................................................ 126

1

2

3

4

5

6

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

9

10 Power Supply Recommendations ................... 128

11 Layout................................................................. 128

11.1 Layout Guidelines ............................................... 128

11.2 Layout Example .................................................. 129

12 Device and Documentation Support ............... 130

12.1 Documentation Support ...................................... 130

12.2 Related Links ...................................................... 130

6.6 AC Performance Characteristics: f_S= 2949.12

MSPS......................................................................... 7

6.7 AC Performance Characteristics: f_S= 2457.6 MSPS

(Performance Optimized for F + A + D Band) ........... 9

6.8 AC Performance Characteristics: f_S= 2457.6 MSPS

(Performance Optimized for F + A Band) .................. 9

12.3 Receiving Notification of Documentation

Updates.................................................................. 130

6.9 Digital Requirements............................................... 10

6.10 Timing Requirements............................................ 11

6.11 Typical Characteristics.......................................... 13

Parameter Measurement Information ................ 26

7.1 Input Clock Diagram ............................................... 26

Detailed Description ............................................ 27

12.4 Community Resources........................................ 130

12.5 Trademarks......................................................... 130

12.6 Electrostatic Discharge Caution.......................... 130

12.7 Glossary.............................................................. 130

7

8

13 Mechanical, Packaging, and Orderable

Information ......................................................... 130

4 Revision History

Changes from Original (May 2016) to Revision A

Page

•

Released to production........................................................................................................................................................... 1

2

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SBAS774A –MAY 2016–REVISED DECEMBER 2016

5 Pin Configuration and Functions

RMP Package

72-Pin VQFN

Top View

DB3M

DB3P

GND

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

DA3M

DA3P

GND

2

3

DVDD

SDIN

4

DVDD

PDN

5

SCLK

SEN

6

GND

7

RESET

DVDD

AVDD

AVDD19

AVDD

INAP

DVDD

AVDD

AVDD19

SDOUT

AVDD

INBP

8

9

Thermal

Pad

10

11

12

13

14

15

16

17

18

INBM

INAM

AVDD

AVDD19

AVDD

GND

AVDD

AVDD19

AVDD

GND

Not to scale

Pin Functions

NAME

NO.

I/O

DESCRIPTION

INPUT, REFERENCE

INAM

INAP

INBM

INBP

CM

41

42

14

13

22

I

Differential analog input for channel A

I

Differential analog input for channel B

O

Common-mode voltage for analog inputs, 1.2 V

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Pin Functions (continued)

NAME

NO.

I/O

DESCRIPTION

CLOCK, SYNC

CLKINM

28

27

34

33

19

20

21

63

Differential clock input for the analog-to-digital converter (ADC).

This pin has an internal differential 100-Ω termination.

I

CLKINP

SYSREFM

SYSREFP

GPIO1

External sync input. This pin has an internal, differential 100-Ω termination and

requires external biasing.

GPIO control pin; configured through the SPI. This pin can be configured to be

either a fast overrange output for channel A and B, a fast detect alarm signal from

the peak power detect, or a numerically-controlled oscillator (NCO) control.

GPIO 4 (pin 63) can also be configured as a single-ended SYNCB input.

GPIO2

I/O

GPIO3

GPIO4

CONTROL, SERIAL

RESET

48

6

I

Hardware reset; active high. This pin has an internal 20-kΩ pulldown resistor.

Serial interface clock input. This pin has an internal 20-kΩ pulldown resistor.

SCLK

Serial interface data input. This pin has an internal 20-kΩ pulldown resistor. SDIN

can be data input in 4-wire mode, data input and output in 3 wire-mode.

SDIN

5

I/O

SEN

7

I

Serial interface enable. This pin has an internal 20-kΩ pullup resistor to DVDD.

SDOUT

11

O

Serial interface data output in 4-wire mode

Power down; active high. This pin can be configured through an SPI register setting

and can be configured to a fast overrange output channel B through the SPI.

This pin has an internal 20-kΩ pulldown resistor.

PDN

50

I

DATA INTERFACE

DA0M

62

61

59

58

56

55

54

53

65

66

68

69

71

72

1

DA0P

DA1M

DA1P

O

JESD204B serial data output for channel A

DA2M

DA2P

DA3M

DA3P

DB0M

DB0P

DB1M

DB1P

O

JESD204B serial data output for channel B

DB2M

DB2P

DB3M

DB3P

2

SYNCBM

36

Synchronization input for the JESD204B port. This pin has an LVDS or 1.8-V logic

input, an optional on-chip 100-Ω termination, and is selectable through the SPI.

This pin requires external biasing.

I

SYNCBP

35

POWER SUPPLY

AVDD19

AVDD

DVDD

GND

10, 16, 24, 31, 39, 45

I

Analog 1.9-V power supply

9, 12, 15, 17, 25, 30,

38, 40, 43, 44, 46

Analog 1.15-V power supply

4, 8, 47, 51, 57, 64, 70

Digital 1.15 V-power supply, including the JESD204B transmitter

Ground; shorted to thermal pad inside device

3, 18, 23, 26, 29, 32,

37, 49, 52, 60, 67

4

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SBAS774A –MAY 2016–REVISED DECEMBER 2016

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

2.1

UNIT

AVDD19

Supply voltage range

AVDD

1.4

V

DVDD

1.4

INAP, INAM and INBP, INBM

CLKINP, CLKINM

AVDD19 + 0.3

AVDD + 0.6

Voltage applied to input pins

V

SYSREFP, SYSREFM, SYNCBP, SYNCBM

SCLK, SEN, SDIN, RESET, PDN, GPIO1, GPIO2,

GPIO3, GPIO4

–0.2

AVDD19 + 0.2

Voltage applied to output pins

Temperature

–0.3

–40

–65

2.2

85

V

Operating free-air, T_A

Storage, T_stg

°C

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±1000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.8

NOM

1.9

MAX

2.0

UNIT

AVDD19

Supply voltage⁽¹⁾

Temperature

AVDD

1.1

1.15

1.25

1.2

V

DVDD

1.1

Operating free-air, T_A

Operating junction, T_J

–40

85

°C

105⁽²⁾

125

(1) Always power up the DVDD supply (1.15 V) before the AVDD19 (1.9 V) supply. The AVDD (1.15 V) supply can come up in any order.

(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

ADC32RF80

THERMAL METRIC⁽¹⁾

RMP (VQFN)

UNIT

72 PINS

21.8

4.4

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

2.0

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

2.0

R_θJC(bot)

0.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER CONSUMPTION⁽¹⁾(Dual-Channel Operation, Both Channels A and B are Active; Divide-by-4, Complex Output Mode⁽²⁾

)

I_AVDD19

I_AVDD

I_DVDD

P_D

1.9-V analog supply current

1.15-V analog supply current

1.15-V digital supply current

Power dissipation

f_S= 2949.12 MSPS

1777

970

1989

1103

1955

7.07

mA

W

1785

6.54

Global power-down power

dissipation

360

mW

ANALOG INPUTS

Resolution

14

1.35

1.2⁽³⁾

65

Bits

V_PP

V

Differential input full-scale

Input common-mode voltage

Input resistance

V_IC

R_IN

C_IN

Differential resistance at dc

Differential capacitance at dc

Ω

Input capacitance

2

pF

V

V_CMcommon-mode voltage output

1.2

Analog input bandwidth

(–3-dB point)

ADC driven with 50-Ω source

3200

MHz

ISOLATION

f_IN= 100 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2700 MHz

f_IN= 3500 MHz

100

99

95

86

85

Crosstalk isolation between channel

A and channel B⁽⁴⁾

dBc

CLOCK INPUT⁽⁵⁾

Input clock frequency

1.5

0.5

3

GSPS

V_PP

Differential (peak-to-peak) input

clock amplitude

1.5

2.5

Input clock duty cycle

Internal clock biasing

45%

50%

1.0

55%

V

Internal clock termination

(differential)

100

Ω

(1) See the Power Consumption in Different Modes section for more details.

(2) Full-scale signal is applied to the analog inputs of all active channels.

(3) When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within V_CM±25 mV for best

performance.

(4) Crosstalk is measured with a –2-dBFS input signal on aggressor channel and no input on the victim channel.

(5) See Figure 79.

6

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SBAS774A –MAY 2016–REVISED DECEMBER 2016

6.6 AC Performance Characteristics: f_S= 2949.12 MSPS

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance⁽¹⁾, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 100 MHz, A_OUT= –2 dBFS

MIN⁽²⁾

NOM

62.6

61.1

58.9

58.2

56.8

54.1

154.3

152.8

150.6

149.9

148.5

145.8

63.1

24.7

61.7

60.2

58.4

57.6

54.8

53.6

10.0

9.7

MAX

UNIT

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

55.4

SNR

NSD

Signal-to-noise ratio

dBFS

f_IN= 900 MHz, A_OUT= –2 dBFS

Noise spectral density

averaged across the

Nyquist zone

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 1850 MHz, A_OUT= –40 dBFS

f_IN= 100 MHz, A_OUT= –2 dBFS

147.1

dBFS/Hz

Small-signal SNR

Noise figure

dBFS

dB

NF⁽⁴⁾

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

Signal-to-noise and

distortion ratio

SINAD

dBFS

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

9.4

ENOB

SFDR

HD2⁽⁵⁾

Effective number of bits

Bits

9.3

8.8

8.6

68.0

66.0

67.0

64.0

58.0

62.0

72.0

73.0

67.0

64.0

58.0

62.0

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

58

Spurious-free dynamic

range

dBc

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2700 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

Second-order harmonic

distortion

dBc

(1) Performance is shown with DDC bypassed. When DDC is enabled, performance improves by the decimation filtering process.

(2) Minimum values are specified at A_OUT= –3 dBFS.

(3) Output amplitude, A_OUT, refers to the signal amplitude in the ADC digital output that is same as the analog input amplitude, A_IN, except

when the digital gain feature is used. If digital gain is G, then A_OUT= G + A_IN

(4) The ADC internal resistance = 65 Ω, the driving source resistance = 50 Ω.

(5) The minimum value of HD2 is specified by bench characterization.

.

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AC Performance Characteristics: f_S= 2949.12 MSPS (continued)

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance⁽¹⁾, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 100 MHz, A_OUT= –2 dBFS

MIN⁽²⁾

NOM

68.0

66.0

73.0

80.0

72.0

65.0

85.0

81.0

84.0

80.0

87.0

90.0

77.0

79.0

76.0

77.0

84.0

82.0

80.0

76.0

65.0

77.0

80.0

76.0

75.0

71.0

MAX

UNIT

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

61

Third-order harmonic

distortion

HD3

dBc

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

61

69

62

64

HD4,

HD5

Fourth- and fifth-order

harmonic distortion

dBc

f_IN= 900 MHz, A_OUT= –2 dBFS

Interleaving spurs:

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

IL spur

f_S/ 2 – f_IN

,

f_S/ 4 ± f_IN

f_IN= 900 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

f_IN= 100 MHz, A_OUT= –2 dBFS

Interleaving spur for HD2:

f_S/ 2 – HD2

HD2 IL

f_IN= 900 MHz, A_OUT= –2 dBFS

Spurious-free dynamic

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 3500 MHz, A_OUT⁽³⁾= –3 dBFS with 2-dB gain

Worst

spur

range (excluding HD2, HD3,

HD4, HD5, and interleaving

spurs IL and HD2 IL)

dBc

f_IN1= 1770 MHz, f_IN2= 1790 MHz,

A_OUT= –8 dBFS (each tone)

70

73

67

Two-tone, third-order

intermodulation distortion

f_IN1= 1800 MHz, f_IN2= 2600 MHz,

A_OUT= –8 dBFS (each tone)

IMD3

dBFS

f_IN1= 3490 MHz, f_IN2= 3510 MHz,

A_OUT= –8 dBFS (each tone) with 2-dB gain

8

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SBAS774A –MAY 2016–REVISED DECEMBER 2016

6.7 AC Performance Characteristics: f_S= 2457.6 MSPS

(Performance Optimized for F + A + D Band⁽¹⁾)

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

MIN

NOM

58.5

55.8

60.0

57.0

59.0

57.0

75.0

65.0

84.0

MAX

UNIT

SNR

SFDR

HD2

Signal-to-noise ratio

dBFS

Spurious-free dynamic

range

dBc

Second-order harmonic

distortion

Third-order harmonic

distortion

HD3

Interleaving spurs:

IL spur

f_S/ 2 – f_IN

f_S/ 4 ± f_IN

,

dBc

f_IN= 2600 MHz, A_OUT= –2 dBFS

76.0

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2600 MHz, A_OUT= –2 dBFS

76.0

67.0

Interleaving spur for HD2:

f_S/ 2 – HD2

HD2 IL

IMD3

dBc

Two-tone, third-order

intermodulation distortion

f_IN1= 1800 MHz, f_IN2= 2600 MHz,

A_OUT= –8 dBFS (each tone)

67.0

dBFS

(1) F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz.

6.8 AC Performance Characteristics: f_S= 2457.6 MSPS

(Performance Optimized for F + A Band⁽¹⁾)

typical values specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

f_IN= 1850 MHz, A_OUT= –2 dBFS

MIN

NOM

58.7

57.9

71.0

69.0

71.0

69.0

75.0

76.0

82.0

MAX

UNIT

SNR

SFDR

HD2

Signal-to-noise ratio

dBFS

Spurious-free dynamic

range

dBc

Second-order harmonic

distortion

Third-order harmonic

distortion

HD3

Interleaving spurs:

IL spur

HD2 IL

f_S/ 2 – f_IN

f_S/ 4 ± f_IN

,

dBc

f_IN= 2100 MHz, A_OUT= –2 dBFS

84.0

f_IN= 1850 MHz, A_OUT= –2 dBFS

f_IN= 2100 MHz, A_OUT= –2 dBFS

80.0

Interleaving spur for HD2:

f_S/ 2 – HD2

(1) F-band = 1880 MHz to 1920 MHz, A-band = 2010 MHz to 2025 MHz, and D-band = 2570 MHz to 2620 MHz.

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6.9 Digital Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock duty

cycle, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SEN, SDIN, PDN, GPIO1, GPIO2, GPIO3, GPIO4)

V_IH

V_IL

I_IH

I_IL

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

Input capacitance

0.8

V

0.4

50

–50

4

µA

pF

C_i

DIGITAL OUTPUTS (SDOUT, GPIO1, GPIO2, GPIO3, GPIO4)

AVDD19

–0.1

V_OH

V_OL

High-level output voltage

Low-level output voltage

AVDD19

V

0.1

DIGITAL INPUTS (SYSREFP and SYSREFM; SYNCBP and SYNCBM; Requires External Biasing)

V_ID

Differential input voltage

350

450

1.2

800

mV_PP

V

V_CM

Input common-mode voltage

1.05

1.325

DIGITAL OUTPUTS (JESD204B Interface: DA[3:0], DB[3:0], Meets JESD204B LV-0IF-11G-SR Standard)

|V_OD

|

Output differential voltage

700

450

mV_PP

mV

|V_OCM

|

Output common-mode voltage

Transmitter pins shorted to any voltage

between –0.25 V and 1.45 V

Transmitter short-circuit current

Single-ended output impedance

Output capacitance

–100

100

mA

Ω

z_os

C_o

50

2

Output capacitance inside the device, from

either output to ground

pF

10

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6.10 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

MIN

NOM

MAX

UNIT

SAMPLE TIMING

Aperture delay

250

750

ps

Aperture delay matching between two channels on the same device

±15

±150

90

Aperture delay matching between two devices at the same

temperature and supply voltage

ps

Aperture jitter, clock amplitude = 2 V_PP

f_S

Input

clock

cycles

Latency

Data latency, ADC sample to

DDC block bypassed⁽³⁾, LMFS = 8224

digital output

424

(1)(2)

Fast overrange latency, ADC sample to FOVR indication on GPIO pins

70

6

Propagation delay time: logic gates and output buffer delay

(does not change with f_S)

t_PD

ns

SYSREF TIMING⁽⁴⁾

t_{SU_SYSREF}SYSREF setup time: referenced to clock rising edge, 2949.12 MSPS

t_{H_SYSREF}SYSREF hold time: referenced to clock rising edge, 2949.12 MSPS

Valid transition window sampling period: t_{SU_SYSREF}– t_{H_SYSREF}, 2949.12 MSPS

JESD OUTPUT INTERFACE TIMING

140

50

70

20

ps

143

UI

Unit interval: 12.5 Gbps

80

100

10.0

60

400

ps

Gbps

ps

Serial output data rate

2.5

12.5

Rise, fall times: 1-pF, single-ended load capacitance to ground

Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps

Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps

25

%UI

0.99

%UI, rms

%UI, pk-

pk

Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps

9.1

(1) Overall latency = latency + t_PD

.

(2) Latency increases when the DDC modes are used; see Table 5.

(3) For latency in different DDC options, see .

(4) Common-mode voltage for the SYSREF input is kept at 1.2 V.

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SYSREFP, SYNCP, DxP

V_ID/ 4, V_OD/ 4

(1)

V_ICM, V_OCM

V_ID/ 4, V_OD/ 4

SYSREFM, SYNCM, DxM

SYSREF = SYSREFP-SYNCP,

SYNC = SYNCP-SYNCM,

Dx = DxP-DxM

(1)

V_IDor V_OD

0 V

GND

V_OCMis not the same as V_ICM. Similarly, V_ODis not the same as V_ID

.

Figure 1. Logic Levels for Digital Inputs and Outputs

Sample N

CLKP

CLKM

t_{SU_SYSREF}

t_{H_SYSREF}

SYSREFP

SYSREFM

Valid Transition Window

Figure 2. SYSREF Timing Diagram

12

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6.11 Typical Characteristics

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D055

0

300

600

900

1200

1500

D001

Input Frequency (MHz)

SNR = 62.4 dBFS; SFDR = 71 dBc;

SNR = 62.2 dBFS; SFDR = 68 dBc;

HD2 = –71 dBc; HD3 = –83 dBc; non HD2, HD3 = 82 dBc;

IL spur = 80 dBc; f_IN= 100 MHz

HD2 = –68 dBc; HD3 = –73 dBc; non HD2, HD3 = 77 dBc;

IL spur = 86 dBc; f_IN= 100 MHz

Figure 4. FFT for 100-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 3. FFT for 100-MHz Input Frequency

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D056

0

300

600

900

1200

1500

D002

Input Frequency (MHz)

SNR = 62.1 dBFS; SFDR = 76 dBc;

SNR = 61.2 dBFS; SFDR = 66 dBc;

HD2 = –76 dBc; HD3 = –83 dBc; non HD2, HD3 = 82 dBc;

IL spur = 83 dBc; f_IN= 900 MHz

HD2 = –77 dBc; HD3 = –66 dBc; non HD2, HD3 = 80 dBc;

IL spur = 83 dBc; f_IN= 900 MHz

Figure 6. FFT for 900-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 5. FFT for 900-MHz Input Signal

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D057

0

300

600

900

1200

1500

D003

Input Frequency (MHz)

SNR = 58 dBFS; SFDR = 69 dBc;

SNR = 59.1 dBFS; SFDR = 65 dBc;

HD2 = –69 dBc; HD3 = –75 dBc; non HD2, HD3 = 74 dBc;

IL spur = 78 dBc; f_IN= 1.85 GHz

HD2 = –65 dBc; HD3 = –73 dBc; non HD2, HD3 = 73 dBc;

IL spur = 76 dBc; f_IN= 1.7 GHz

Figure 8. FFT for 1850-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 7. FFT for 1780-MHz Input Signal

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D058

0

300

600

900

1200

1500

D004

Input Frequency (MHz)

SNR = 57.5 dBFS; SFDR = 70 dBc;

SNR = 58.2 dBFS; SFDR = 64 dBc;

HD2 = –70 dBc; HD3 = –81 dBc; non HD2, HD3 = 75 dBc;

IL spur = 77 dBc; f_IN= 2.1 GHz

HD2 = –64 dBc; HD3 = –85 dBc; non HD2, HD3 = 73 dBc;

IL spur = 74 dBc; f_IN= 2.1 GHz

Figure 10. FFT for 2100-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 9. FFT for 2100-MHz Input Signal

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D059

0

300

600

900

1200

1500

D005

Input Frequency (MHz)

SNR = 55.4 dBFS; SFDR = 60 dBc;

SNR = 56.9 dBFS; SFDR = 62 dBc;

HD2 = –60 dBc; HD3 = –67 dBc; non HD2, HD3 = 72 dBc;

IL spur = 75 dBc; f_IN= 2.6 GHz

HD2 = –62 dBc; HD3 = –72 dBc; non HD2, HD3 = 72 dBc;

IL spur = 64 dBc; f_IN= 2.6 GHz

Figure 12. FFT for 2600-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 11. FFT for 2600-MHz Input Signal

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

D060

0

300

600

900

1200

1500

D006

Input Frequency (MHz)

SNR = 53.6 dBFS; SFDR = 47 dBc;

SNR = 54.2 dBFS; SFDR = 60 dBc;

HD2 = –50 dBc; HD3 = –47 dBc; non HD2, HD3 = 70 dBc;

IL spur = 67 dBc; f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB gain

HD2 = –60 dBc; HD3 = –64 dBc; non HD2, HD3 = 71 dBc;

IL spur = 80 dBc; f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB gain

Figure 14. FFT for 3500-MHz Input Signal (f_S= 2457.6 MSPS)

Figure 13. FFT for 3500-MHz Input Signal

14

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0

300

600

900

1200

1500

Input Frequency (MHz)

D001

D074

f_IN1= 900 MHz, f_IN2= 950 MHz, A_IN= –8 dBFS, IMD = 79 dBFS

f_IN1= 900 MHz, f_IN2= 950 MHz, A_IN= –36 dBFS, IMD = 97 dBFS

Figure 15. FFT for Two-Tone Input Signal (–8 dBFS)

Figure 16. FFT for Two-Tone Input Signal (–36 dBFS)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

0

250

500

750

1000

1250

Input Frequency (MHz)

D075

D076

f_IN1= 900 MHz, f_IN2= 950 MHz, A_IN= –8 dBFS, IMD = 75 dBFS

f_IN1= 900 MHz, f_IN2= 950 MHz, A_IN= –36 dBFS,

IMD = 92 dBFS

Figure 18. FFT for Two-Tone Input Signal

(–36 dBFS, f_S= 2457.6 MSPS)

Figure 17. FFT for Two-Tone Input Signal

(–8 dBFS, f_S= 2457.6 MSPS)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0

300

600

900

1200

1500

Input Frequency (MHz)

D007

D008

f_IN1= 1.77 GHz, f_IN2= 1.79 GHz, A_IN= –8 dBFS, IMD = 70 dBFS

f_IN1= 1.77 GHz, f_IN2= 1.790 GHz, A_IN= –36 dBFS,

IMD = 97 dBFS

Figure 20. FFT for Two-Tone Input Signal (–36 dBFS)

Figure 19. FFT for Two-Tone Input Signal (–8 dBFS)

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

0

250

500

750

1000

1250

Input Frequency (MHz)

D061

D062

f_IN1= 1.77 GHz, f_IN2= 1.79 GHz, A_IN= –8 dBFS,

IMD = 76 dBFS

f_IN1= 1.77 GHz, f_IN2= 1.790 GHz, A_IN= –36 dBFS,

IMD = 96 dBFS

Figure 21. FFT for Two-Tone Input Signal

(–8 dBFS, f_S= 2457.6 MSPS)

Figure 22. FFT for Two-Tone Input Signal

(–36 dBFS, f_S= 2457.6 MSPS)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0

300

600

900

1200

1500

Input Frequency (MHz)

D009

D010

f_IN1= 1.8 MHz, f_IN2= 2.6 GHz, A_IN= –8 dBFS, IMD = 71 dBFS

f_IN1= 1.8 GHz, f_IN2= 2.6 GHz, A_IN= –36 dBFS, IMD = 94 dBFS

Figure 23. FFT for Two-Tone Input Signal (–8 dBFS)

Figure 24. FFT for Two-Tone Input Signal

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

250

500

750

1000

1250

0

250

500

750

1000

1250

Input Frequency (MHz)

D063

D064

f_IN1= 2.09 GHz, f_IN2= 2.1 GHz, A_IN= –8 dBFS, IMD = 76 dBFS

f_IN1= 2.09 MHz, f_IN2= 2.1 GHz, A_IN= –36 dBFS,

IMD = 94 dBFS

Figure 26. FFT for Two-Tone Input Signal

(–36 dBFS, f_S= 2457.6 MSPS)

Figure 25. FFT for Two-Tone Input Signal

(–8 dBFS, f_S= 2457.6 MSPS)

16

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0

300

600

900

1200

1500

Input Frequency (MHz)

D011

D012

f_IN1= 3.49 MHz, f_IN2= 3.51 GHz, IMD = 66 dBFS,

A_IN= –3 dBFS with 2-dB gain

f_IN1= 3.49 GHz, f_IN2= 3.51 GHz, IMD = 92 dBFS,

A_IN= –3 dBFS with 2-dB gain

Figure 27. FFT for Two-Tone Input Signal (–8 dBFS)

Figure 28. FFT for Two-Tone Input Signal (–36 dBFS)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-100

-110

0

250

500

750

1000

1250

0

250

500

750

1000

1250

Input Frequency (MHz)

D065

D066

f_IN1= 2.59 GHz, f_IN2= 2.6 GHz, A_IN= –8 dBFS, IMD = 65 dBFS

f_IN1= 2.59 GHz, f_IN2= 2.6 GHz, A_IN= –36 dBFS,

IMD = 92 dBFS

Figure 30. FFT for Two-Tone Input Signal

(–36 dBFS, f_S= 2457.6 MSPS)

Figure 29. FFT for Two-Tone Input Signal

(–8 dBFS, f_S= 2457.6 MSPS)

-60

-70

-60

-70

-80

-90

-100

-110

-36

-32

-28

-24

-20

-16

-12

-8

-36

-32

-28

-24

-20

-16

-12

-8

Each Tone Amplitude (dBFS)

D013

D067

f_IN1= 1.77 GHz, f_IN2= 1.79 GHz

Figure 31. Intermodulation Distortion vs Input Amplitude

(1770 MHz and 1790 MHz)

Figure 32. Intermodulation Distortion vs Input Amplitude

(1770 MHz and 1790 MHz, f_S= 2457.6 MSPS)

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

-60

-70

-78

-80

-86

-90

-94

-100

-102

-110

-36

-32

-28

-24

-20

-16

-12

-8

-36

-32

-28

-24

-20

-16

-12

-8

Each Tone Amplitude (dBFS)

D014

D068

f_IN1= 1.8 GHz, f_IN2= 2.6 GHz, A_IN= –36 dBFS

f_IN1= 2.09 GHz, f_IN2= 2.1 GHz

Figure 33. Intermodulation Distortion vs Input Amplitude

(1800 MHz and 2600 MHz)

Figure 34. Intermodulation Distortion vs Input Amplitude

(1800 MHz and 2600 MHz, f_S= 2457.6 MSPS)

-60

-70

-80

-90

-100

-110

-36

-32

-28

-24

-20

-16

-12

-8

-36

-32

-28

-24

-20

-16

-12

-8

Each Tone Amplitude (dBFS)

D069

D015

f_IN1= 2.59GHz, f_IN2= 2.6 GHz

f_IN1= 3.49 GHz, f_IN2= 3.51 GHz with 2-dB digital gain

Figure 36. Intermodulation Distortion vs Input Amplitude

(3490 MHz and 3510 MHz, f_S= 2457.6 MSPS)

Figure 35. Intermodulation Distortion vs Input Amplitude

(3490 MHz and 3510 MHz)

90

78

66

54

42

30

90

78

66

54

42

30

0

500 1000 1500 2000 2500 3000 3500 4000

0

500

1000

1500

2000

2500

3000

3500

InputFrequency (MHz)

D016

D070

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

Figure 37. Spurious-Free Dynamic Range vs

Input Frequency

Figure 38. Spurious-Free Dynamic Range vs

Input Frequency (f_S= 2457.6 MSPS)

18

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

100

95

90

85

80

75

70

65

60

105

100

95

f_IN+ f_S/4 (dBc)

f_IN- f_S/2 (dBc)

f_IN- f_S/4 (dBc)

2f_IN+ f_S/4 (dBc)

2f_IN- f_S/2 (dBc)

2f_IN- f_S/4 (dBc)

f_IN+ f_S/4 (dBc)

f_IN- f_S/2 (dBc)

f_IN- f_S/4 (dBc)

2f_IN+ f_S/4 (dBc)

2f_IN- f_S/2 (dBc)

2f_IN- f_S/4 (dBc)

90

85

80

75

70

65

0

500 1000 1500 2000 2500 3000 3500 4000

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

D017

D071

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

Figure 39. IL Spur vs Input Frequency

Figure 40. IL Spur vs Input Frequency (f_S= 2457.6 MSPS)

63

61

59

57

55

53

61

59

57

55

53

0

500 1000 1500 2000 2500 3000 3500 4000

0

500

1000

1500

2000

2500

3000

3500

Input Frequency (MHz)

D018

D072

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

A_OUT= –2 dBFS with 0-dB gain for f_INless than 3 GHz,

A_OUT= –3 dBFS with 2-dB gain for f_INmore than 3 GHz

Figure 41. Signal-to-Noise Ratio vs Input Frequency

Figure 42. Signal-to-Noise Ratio vs Input Frequency

(f_S= 2457.6 MSPS)

61

72

AVDD = 1.1 V

AVDD = 1.15 V

AVDD = 1.2 V

AVDD = 1.1 V

AVDD = 1.15 V

AVDD = 1.2 V

AVDD = 1.25 V

60

70

AVDD = 1.25 V

59

68

66

64

62

58

57

56

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D019

D020

f_IN= 1.78 GHz, A_IN= –2 dBFS

Figure 43. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

Figure 44. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

57

56

55

54

53

52

66

64

62

60

58

56

AVDD = 1.1 V

AVDD = 1.15 V

AVDD = 1.2 V

AVDD = 1.25 V

AVDD = 1.1 V

AVDD = 1.15 V

AVDD = 1.2 V

AVDD = 1 .25 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D021

D022

f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB digital gain

f_IN= 3.5GHz, A_IN= –3 dBFS with 2-dB digital gain

Figure 45. Signal-to-Noise Ratio vs

AVDD Supply and Temperature

Figure 46. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature

61

72

70

68

66

64

62

DVDD = 1.1 V

DVDD = 1.15 V

DVDD = 1.2 V

DVDD = 1.1 V

DVDD = 1.15 V

DVDD = 1.2 V

60

59

58

57

56

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D023

D024

f_IN= 1.78 GHz, A_IN= –2 dBFS

Figure 47. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

Figure 48. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

57

68

66

64

62

60

58

DVDD = 1.1 V

DVDD = 1.15 V

DVDD = 1.2 V

DVDD = 1.1 V

DVDD = 1.15 V

DVDD = 1.2 V

56

55

54

53

52

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D025

D026

f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB digital gain

Figure 49. Signal-to-Noise Ratio vs

DVDD Supply and Temperature

Figure 50. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

61

60

59

58

57

56

72

70

68

66

64

62

AVDD19 = 1.8 V

AVDD19 = 1.85 V

AVDD19 = 1.9 V

AVDD19 = 1.95 V

AVDD19 = 2 V

AVDD19 = 1.8 V

AVDD19 = 1.85 V

AVDD19 = 1.9 V

AVDD19 = 1.95 V

AVDD19 = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D027

D028

f_IN= 1.78 GHz, A_IN= –2 dBFS

Figure 51. Signal-to-Noise Ratio vs

AVDD19 Supply and Temperature

Figure 52. Spurious-Free Dynamic Range vs

AVDD19 Supply and Temperature

57

56

55

54

53

52

66

64

62

60

58

56

AVDD19 = 1.8 V

AVDD19 = 1.85 V

AVDD19 = 1.9 V

AVDD19 = 1.95 V

AVDD19 = 2 V

AVDD19 = 1.8 V

AVDD19 = 1.85 V

AVDD19 = 1.9 V

AVDD19 = 1.95 V

AVDD19 = 2 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D029

D030

f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB digital gain

Figure 53. Signal-to-Noise Ratio vs

AVDD19 Supply and Temperature

Figure 54. Spurious-Free Dynamic Range vs

AVDD19 Supply and Temperature

35

24

Temp = -40°C

Temp = 25°C

Temp = 85°C

25

Temp = -40°C

Temp = 25°C

Temp = 85°C

30

20

16

12

8

20

15

10

5

4

0

D031

D032

HD2 (dBFS)

f_IN= 1.78 GHz

Figure 55. HD2 Histogram at AVDD19 = 1.8 V

Figure 56. HD2 Histogram at AVDD19 = 1.9 V

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

72

70

68

66

64

62

60

58

56

54

52

50

48

120

110

100

90

80

70

60

50

40

30

20

10

0

25

20

15

10

5

SNR (dBFS)

SFDR (dBFS)

SFDR (dBc)

Temp = -40°C

Temp = 25°C

Temp = 85°C

0

-70

-60

-50

-40

-30

-20

-10

0

D033

HD2 (dBFS)

Amplitude (dBFS)

D034

f_IN= 1.78 GHz

f_IN= 1.78 GHz, A_IN= –2 dBFS

Figure 57. HD2 Histogram at AVDD19 = 2.0 V

Figure 58. Performance vs Amplitude

72

70

68

66

64

62

60

58

56

54

52

50

48

120

62

61

60

59

58

57

56

67

66

65

64

63

62

61

SNR (dBFS)

SFDR (dBFS)

SFDR (dBc)

SNR

SFDR

110

100

90

80

70

60

50

40

30

20

10

0

-70

-60

-50

-40

-30

-20

-10

0

0.5

0.9

1.3

1.7

2.1

2.5

Amplitude (dBFS)

Differential Clock Amplitude (Vpp)

D035

D036

f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB digital gain

f_IN= 1.78 GHz, A_IN= –2 dBFS

Figure 59. Performance vs Amplitude

Figure 60. Performance vs Clock Amplitude

60

59

58

57

56

55

75

SNR

SFDR

56

64

SNR

SFDR

72.5

55

62

60

58

56

54

70

54

53

52

51

67.5

65

62.5

60

40

45

50

55

0.5

0.9

1.3

1.7

2.1

2.5

Input Clock Duty Cycle (%)

Differential Clock Amplitude (Vpp)

D039

D038

D037

f_IN= 1.78 GHz, A_IN= –2 dBFS

f_IN= 3.5 GHz, A_IN= –3 dBFS

Figure 62. Performance vs Clock Duty Cycle

Figure 61. Performance vs Clock Amplitude

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

56

55

54

53

52

51

63

62

61

60

59

58

SNR

SFDR

40

45

50

55

60

0

300

600

900

1200

1500

Input Clock Duty Cycle (%)

Input Frequency (MHz)

D039

D040

f_IN= 3.5 GHz, A_IN= –3 dBFS with 2-dB digital gain

f_IN= 3.5 GHz, A_IN= –3 dBFS, PSRR = 37 dB,

f_PSRR= 3 MHz, A_PSRR= 50 mV_PP, AVDD = 1.9 V

Figure 64. Power-Supply Rejection Ratio FFT for

Test Signal on AVDD Supply

Figure 63. Performance vs Clock Duty Cycle

0

75

PSRR with 50-mVpp Signal on AVDD

PSRR with 50-mVpp Signal on AVDD19

-10

-20

65

-30

55

45

35

25

15

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0.02 0.05

0.2 0.5

1

2 3 45 710 20 50 100 200 500

Input Frequency (MHz)

Frequency of Signal on Supply (MHz)

D042

D041

CMRR = 32 dB, f_CMRR= 32 dB, A_PSRR= 50 mV_PP

Figure 66. Common-Mode Rejection Ratio FFT

Figure 65. Power-Supply Rejection Ratio vs

Tone Frequency

45

40

35

30

25

20

15

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

50

100

150

200

250

-375

-225

-75

75

225

375

Frequency of Input Common-Mode Signal (MHz)

Input Frequency (MHz)

D043

D044

f_IN= 1.8 GHz, A_OUT= –2 dBFS

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 60.6 dBFS, SFDR (includes IL) = 75 dBc

Figure 68. FFT in 4X Decimation (Complex Output)

Figure 67. Common-Mode Rejection Ratio vs

Tone Frequency

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

-250

-150

-50

50

150

250

-187.5

-112.5

-37.5

37.5

112.5

187.5

D046

Input Frequency (MHz)

D045

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 61.6 dBFS, SFDR (includes IL) = 82 dBc

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 62.6 dBFS, SFDR (includes IL) = 86 dBc

Figure 69. FFT in 6X Decimation (Complex Output)

Figure 70. FFT in 8X Decimation (Complex Output)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

-150

-90

-30

30

90

150

-166

-99.6

-33.2

33.2

99.6

166

Input Frequency (MHz)

D047

D048

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 63 dBFS, SFDR (includes IL) = 82 dBc

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 63.3 dBFS, SFDR (includes IL) = 81 dBc

Figure 71. FFT in 9X Decimation (Complex Output)

Figure 72. FFT in 10X Decimation (Complex Output)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

-125

-75

-25

25

75

125

-93.75

-56.25

-18.75

Input Frequency (MHz)

18.75

56.25

93.75

D050

Input Frequency (MHz)

D049

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 63.9 dBFS, SFDR (includes IL) = 83 dBc

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 63.7 dBFS, SFDR (includes IL) = 83 dBc

Figure 74. FFT in 16X Decimation (Complex Output)

Figure 73. FFT in 12X Decimation (Complex Output)

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Typical Characteristics (continued)

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and ADC sampling rate = 2949.12 MSPS, DDC bypassed performance, 50% clock

duty cycle, AVDD19 = 1.9 V, AVDD = DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

-83

-49.8

-16.6

16.6

49.8

83

-75

-45

-15

15

45

75

Input Frequency (MHz)

D051

D052

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 64 dBFS, SFDR (includes IL) = 83 dBc

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 64.4 dBFS, SFDR (includes IL) = 84 dBc

Figure 75. FFT in 18X Decimation (Complex Output)

Figure 76. FFT in 20X Decimation (Complex Output)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

-62.5

-37.5

-12.5

12.5

37.5

62.5

-46.875

-28.125

-9.375

Input Frequency (MHz)

9.375

28.125

46.875

D054

Input Frequency (MHz)

D054

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 64.4 dBFS, SFDR (includes IL) = 82 dBc

f_IN= 1.78 GHz, A_IN= –2 dBFS, f_S= 2949.12 MSPS,

SNR = 64.5 dBFS, SFDR (includes IL) = 79 dBc

Figure 77. FFT in 24X Decimation (Complex Output)

Figure 78. FFT in 32X Decimation (Complex Output)

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7 Parameter Measurement Information

7.1 Input Clock Diagram

Figure 79 shows the input clock diagram.

V_{CLKIN_DIFF}

=

V_CLKIN+- V_CLKIN-

V_CLKIN+

V_CLKIN-

Figure 79. Input Clock Diagram

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8 Detailed Description

8.1 Overview

The ADC32RF8x is a dual, 14-bit, 2949.12-MSPS, telecom receiver and feedback device family containing

analog-to-digital converters (ADCs) followed by multi-band digital down-converters (DDCs), and a back-end

JESD204B digital interface.

The ADCs are preceded by input buffers and on-chip termination to provide a uniform input impedance over a

large input frequency range. Furthermore, an internal differential clamping circuit provides first-level protection

against overvoltage conditions. Each ADC channel is internally interleaved four times and equipped with

background, analog and digital, and interleaving correction.

The on-chip DDC enables single- or dual-band internal processing to pre-select and filter smaller bands of

interest and also reduces the digital output data traffic. Each DDC is equipped with up to three independent,

16-bit numerically-controlled oscillators (NCOs) for phase coherent frequency hopping; the NCOs can be

controlled through the SPI or GPIO pins. The ADC32RF8x also provides three different power detectors on-chip

with alarm outputs in order to support external automatic gain control (AGC) loops.

The processed data are passed into the JESD204B interface where the data are framed, encoded, serialized,

and output on one to four lanes per channel, depending on the ADC sampling rate and decimation. The CLKIN,

SYSREF, and SYNCB inputs provide the device clock and the SYSREF and SYNCB signals to the JESD204B

interface that are used to derive the internal local frame and local multiframe clocks and establish the serial link.

All features of the ADC32RF8x are configurable through the SPI.

8.2 Functional Block Diagram

Buffer

DA[0,1]P/M

DA[2,3]P/M

Digital Block

N

!5/

ADC

50 ꢀ

!5/

Interleave

Correction

INAP/M

FAST

NCO

DET.

NCO

CTRL

GPIO1..4

CLKINP/M

SYSREFP/M

SYNCBP/M

PLL

NCO

FAST

DET.

0º/180º

Clock

NCO

N

Buffer

DB[0,1]P/M

DB[2,3]P/M

Digital Block

!5/

Interleave

Correction

ADC

INBP/M

50 ꢀ

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8.3 Feature Description

8.3.1 Analog Inputs

The ADC32RF8x analog signal inputs are designed to be driven differentially. The analog input pins have internal

analog buffers that drive the sampling circuit. The ADC32RF8x provides on-chip, differential termination to

minimize reflections. The buffer also helps isolate the external driving circuit from the internal switching currents

of the sampling circuit, thus resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to CM using the 32.5-Ω termination resistors

that allow for ac-coupling of the input drive network. Figure 80 and Figure 81 show SDD11 at the analog inputs

from dc to 5 GHz with a 100-Ω reference impedance.

TI Device

INxP

C_IN

R_IN

Z_IN= R_IN|| C_IN

SDD11 = (Z_INœ 100) / (Z_IN+ 100)

INxM

Figure 80. Equivalent Input Impedance

Figure 81. SDD11 Over the Input Frequency Range

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Feature Description (continued)

The input impedance of analog inputs can also be modelled as parallel combination of equivalent resistance and

capacitance. Figure 82 and Figure 83 show how equivalent impedance (C_INand R_IN) vary over frequency.

3

2

0.07

0.06

0.05

0.04

0.03

0.02

0.01

1

0

-1

-2

-3

0

500

1000

1500

2000

2500

3000

0

500

1000

1500

2000

2500

3000

Input Frequency (MHz)

D063

D00614

Figure 82. Differential Input Capacitance vs

Input Frequency

Figure 83. Differential Input Resistance vs Input Frquency

Each input pin (INP, INM) must swing symmetrically between (CM + 0.3375 V) and (CM – 0.3375 V), resulting in

a 1.35-V_PP(default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to

approximately 3.2 GHz, as shown in Figure 84.

2

1

0

-1

-2

-3

-4

-5

-6

100 Ohm Source

-7

50 Ohm Source

-8

100

200 300

500 700 1000

2000 3000 5000

Input Frequency (MHz)

D062

Figure 84. Input Bandwidth with a 100-Ω Source Resistance

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Feature Description (continued)

8.3.1.1 Input Clamp Circuit

The ADC32RF8x analog inputs include an internal, differential clamp for overvoltage protection. The clamp

triggers for any input signals at approximately 600 mV above the input common-mode voltage, effectively limiting

the maximum input signal to approximately 2.4 V_PP, as shown in Figure 85 and Figure 86.

When the clamp circuit conducts, the maximum differential current flowing through the circuit (via input pins)

must be limited to 20 mA.

ADC32RF80

+600 mV

INxP

To Analog Buffer

+337.5 mV

INP

675 mV_PPfor INP and INM

(1.35 V_PPDifferentially)

R_DC/ 2

Input Vcm

INM

Clamp

Circuit

I_DIFF

œ337.5 mV

œ600 mV

VCM

R_DC/ 2

To Analog Buffer

INxM

Figure 85. Clamp Circuit in the ADC32RF8x

Figure 86. Clamp Response Timing Diagram

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Feature Description (continued)

8.3.2 Clock Input

The ADC32RF8x sampling clock input includes internal 100-Ω differential termination along with on-chip biasing.

The clock input is recommended to be ac-coupled externally. The input bandwidth of the clock input is

approximately 3 GHz; the clock input impedance is shown with a 100-Ω reference impedance in the smith chart

of Figure 87.

Figure 87. SDD11 of the Clock Input

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Feature Description (continued)

The analog-to-digital converter (ADC) aperture jitter is a function of the clock amplitude applied to the pins. The

equivalent aperture jitter for input frequencies at a 1-GHz and a 2-GHz input is shown in Figure 88. Depending

on the clock frequency, a matching circuit can be designed in order to maximize the clock amplitude.

350

f_IN= 1 GHz

f_IN= 2 GHz

300

250

200

150

100

50

0.2

1

2

Clock Amplitude (v_PP

)

D061

Figure 88. Equivalent Aperture Jitter vs Input Clock Amplitude

8.3.3 SYSREF Input

The SYSREF signal is a periodic signal that is sampled by the ADC32RF8x device clock and is used to align the

boundary of the local multiframe clock inside the data converter. SYSREF is also used to reset critical blocks

[such as the clock divider for the interleaved ADCs, numerically-controlled oscillators (NCOs), decimation filters

and so forth].

The SYSREF input requires external biasing. Furthermore, SYSREF must be established before the SPI

registers are programmed. A programmable delay on the SYSREF input, as shown in Figure 89, is available to

help with skew adjustment when the sampling clock and SYSREF are not provided from the same source.

CLKINP

50 ꢀ

ë_/a

50 ꢀ

CLKINM

Delay

SYSREFP

SYSREF

Capture

100 ꢀ

SYSREFM

Figure 89. SYSREF Internal Circuit Diagram

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Feature Description (continued)

8.3.3.1 Using SYSREF

The ADC32RF8x uses SYSREF information to reset the clock divider, the NCO phase, and the LMFC counter of

the JESD interface. The device provides flexibility to provide SYSREF information either from dedicated pins or

through SPI register bits. SYSREF is asserted by a low-to-high transition on the SYSREF pins or a 0-to-1 change

in the ASSERT SYSREF REG bit when using SPI registers, as shown in Figure 90.

Input Clock

Divider

(Divide-by-4)

NCO,

JESD Interface

(LMFC Counter)

CLKIN

(CLKP-CLKM)

DLL

PDN SYSREF

(In Master Page)

MASK CLKDIV SYSREF

(In JESD Digital Page)

0

1

SYSREF

(SYSREFP-SYSREFM)

ASSERT SYSREF REG

(In Master Page)

SEL SYSREF REG

(In Master Page)

MASK NCO SYSREF

(In JESD Digital Page)

Figure 90. Using SYSREF to Reset the Clock Divider, the NCO, and the LMFC Counter

The ADC32RF8x samples the SYSREF signal on the input clock rising edge. Required setup and hold time are

listed in the Timing Requirements table. The input clock divider gets reset each time that SYSREF is asserted,

whereas the NCO phase and the LMFC counter of the JESD interface are reset on each SYSREF assertion after

disregarding the first two assertions, as shown in Table 1.

Table 1. Asserting SYSREF

ACTION

SYSREF ASSERTION INDEX

INPUT CLOCK DIVIDER

Gets reset

NCO PHASE

Does not get reset

Gets reset

LMFC COUNTER

Does not get reset

Gets reset

1

2

Gets reset

3

Gets reset

4 and onwards

Gets reset

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The SESREF use-cases can be classified broadly into two categories:

1. SYSREF is applied as aperiodic multi-shot pulses.

Figure 91 shows a case when only a counted number of pulses are applied as SYSREF to the ADC.

CLKIN

SYSREF

t_DLL

(Must be Kept > 40 ms)

1^stSYSREF pulse.

Only the input clock

divider is reset.

2^ndSYSREF pulse. If

the MASK CLKDIV bit is

set, the clock divider

ignores this pulse and

any subsequent

3^rdSYSREF pulse.

The NCO phase and

LMFC counter are reset.

4^thSYSREF pulse (and

subsequent pulses).

Ignored by the input clock

divider, NCO, and the JESD

interface.

SYSREF pulses.

1 (The input clock divider ignores the SYSREF pulses.)

MASK CLKDIV SYSREF Register Bit

0

1 (The NCO and LMFC counter of the JESD interface

ignore the SYSREF pulses.)

MASK NCO SYSREF Register Bit⁽¹⁾

0

Alternatively, the SYSREF buffer can be powered down with the PDN SYSREF bit.

Figure 91. SYSREF Used as a Periodic, Finite Number of Pulses

After the first SYSREF pulse is applied, allow the DLL in the clock path to settle by waiting for the t_DLLtime (>

40 µs) before applying the second pulse. During this time, mask the SYSREF going to the input clock divider

by setting the MASK CLKDIV SYSREF bit so that the divider output phase remains stable. The NCO phase

and LMFC counter are reset on the third SYSREF pulse. After the third SYSREF pulse, the SYSREF going

to the NCO and JESD block can be disabled by setting the MASK NCO SYSREF bit to avoid any unwanted

resets.

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2. SYSREF is applied as a periodic pulse.

Figure 92 shows how SYSREF can be applied as a continuous periodic waveform.

Mask SYSREF to the NCO after

resetting the NCO phase.

The NCO phase is reset here for

the last time.

Then, the NCO mask is set high to

ignore further SYSREF pulses.

CLKIN

SYSREF⁽¹⁾

Time > t_DLL+ 2 x t_SYSREF

1^stSYSREF pulse.

The input clock divider

is reset.

1 (The NCO and LMFC counter of the JESD

interface ignore the SYSREF pulses.)

MASK NCO SYSREF Register Bit⁽²⁾

0

t_SYSREFis a period of the SYSREF waveform.

Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit.

Figure 92. SYSREF Used as a Periodic Waveform

After applying the SYSREF signal, DLL must be allowed to lock, and the NCO phase and LMFC counter

must be allowed to reset by waiting for at least the t_DLL(40 µs) + 2 × t_SYSREFtime. Then, the SYSREF going

to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.

8.3.3.2 Frequency of the SYSREF Signal

When SYSREF is a periodic signal, its frequency is required to be a sub-harmonic of the internal local multi-

frame clock (LMFC) frequency, as described in Equation 1. The LMFC frequency is determined by the selected

decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.

SYSREF = LMFC / N

where

•

N is an integer value (1, 2, 3, and so forth)

(1)

In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a

multiple of f_S/ 64. Table 2 provides a summary of the valid LMFC clock settings.

Table 2. . SYSREF and LMFC Clock Frequency

OPERATING MODE

LMFS SETTING

LMFC CLOCK FREQUENCY

f_S⁽¹⁾/ (D × S⁽²⁾× K⁽³⁾

SYSREF FRQUENCY

f_S/ (N × LCM⁽⁴⁾(64, D⁽⁵⁾× S × K))

Decimation

Various

)

(1) f_S= sampling (device) clock frequency.

(2) S = samples per frame.

(3) K = number of frames per multi-frame.

(4) LCM = least-common multiple.

(5) D = decimation ratio.

The SYSREF signal is recommended to be a low-frequency signal less than 5 MHz in order to reduce coupling to

the signal path both on the printed circuit board (PCB) as well as internal to the device.

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Example: f_S= 2949.12 MSPS, Divide-by-4 (LMFS = 8411), K = 16

SYSREF = 2949.12 MSPS / LCM (4 ,64, 16) = 46.08 MHz / N

Operate SYSREF at 2.88 MHz (effectively divide-by-1024, N = 16)

For proper device operation, disable the SYSREF signal after the JESD synchronization is established.

8.3.4 DDC Block

The ADC32RF8x provides a sophisticated on-chip, digital down converter (DDC) block that can be controlled

through SPI register settings and the general-purpose input/output (GPIO) pins. The DDC block supports two

basic operating modes: receiver (RX) mode with single- or dual-band DDC and wide-bandwidth observation

receiver mode.

Note that the ADC32RF80 and ADC32RF83 are identical devices except the fact that the ADC32RF83 offers

only single-band DDC option whereas the ADC32RF80 offers both single-band and dual-band DDC options, as

shown in Table 3.

Table 3. DDC Option Availability

DDC OPTION

Wide-band DDC

Single-band DDC

Dual-band DDC

AVAILABILITY IN DEVICE

ADC32RF80, ADC32RF83

ADC32RF80 only

Each ADC channel is followed by two DDC chains consisting of the digital filter along with a complex digital mixer

with a 16-bit numerically-controlled oscillator (NCO), as shown in Figure 93. The NCOs allow accurate frequency

tuning within the Nyquist zone prior to the digital filtering. One DDC chain is intended for supporting a dual-band

DDC configuration in receiver mode and the second DDC chain supports the wide-bandwidth output option for

the observation configuration. At any given time, either the single-band DDC, the dual-band DDC, or the

wideband DDC can be enabled. Furthermore, three different NCO frequencies can be selected on that path and

are quickly switched using the SPI or the GPIO pins to enable wide-bandwidth observation in a multi-band

application.

f_OUT/ 4

NCO 1,

16 Bits

NCO 2,

16 Bits

NCO 3,

16 Bits

Wideband Real Output

Wideband IQ Output

IQ data

Real[ ]

GPIO

2,3

2

LPF

3 GSPS

IQ data, 3 GSPS

RX1 IQ Output

ADC

N/2

JESD204B

RX1 Real Output

Real[ ]

IQ data

f_OUT/ 4

IQ 3 GSPS

RX2 IQ Output

2

LPF

N/2

RX2 Real Output

Real[ ]

NCO 4,

16 Bits

IQ data

SYSREF

f_OUT/ 4

NOTE: Red traces show SYSREF going to the NCO blocks.

Figure 93. DDC Chains Overview (One ADC Channel Shown)

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Additionally, the decimation filter block provides the option to convert the complex output back to real format at

twice the decimated, complex output rate. The filter response with a real output is identical to a complex output.

The band is centered in the middle of the Nyquist zone (mixed with f_OUT/ 4) based on a final output data rate of

f_OUT

.

8.3.4.1 Operating Mode: Receiver

In receiver mode, the DDC block can be configured to single- or dual-band operation, as shown in Figure 94.

Both DDC chains use the same decimation filter setting and the available options are discussed in the

Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of

lanes of the JESD204B interface.

f_OUT/ 4

NCO 1,

16 Bits

NCO 2,

16 Bits

NCO 3,

16 Bits

Wideband Real Output

Wideband IQ Output

IQ data

Real[ ]

GPIO

2,3

2

LPF

3 GSPS

IQ data, 3 GSPS

RX1 IQ Output

ADC

N/2

JESD204B

RX1 Real Output

Real[ ]

IQ data

f_OUT/ 4

IQ 3 GSPS

RX2 IQ Output

2

LPF

N/2

RX2 Real Output

Real[ ]

NCO 4,

16 Bits

IQ data

SYSREF

f_OUT/ 4

NOTE: Red traces show SYSREF going to the NCO blocks.

Figure 94. Decimation Filter Option for Single- or Dual-Band Operation

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8.3.4.2 Operating Mode: Wide-Bandwidth Observation Receiver

This mode is intended for using a DDC with a wide bandwidth output, but for multiple bands. This mode uses a

single DDC chain where up to three NCOs can be used to perform wide-bandwidth observation in a multi-band

environment, as shown in Figure 95. The three NCOs can be switched dynamically using either the GPIO pins or

an SPI command. All three NCOs operate continuously to ensure phase continuity; however, when the NCO is

switched, the output data are invalid until the decimation filters are completely flushed with data from the new

band.

f_OUT/ 4

NCO 1,

16 Bits

NCO 2,

16 Bits

NCO 3,

16 Bits

Wideband Real Output

Wideband IQ Output

IQ data

Real[ ]

GPIO

2,3

2

LPF

3 GSPS

IQ data, 3 GSPS

RX1 IQ Output

ADC

N/2

JESD204B

RX1 Real Output

Real[ ]

IQ data

f_OUT/ 4

IQ 3 GSPS

RX2 IQ Output

2

LPF

N/2

RX2 Real Output

Real[ ]

NCO 4,

16 Bits

IQ data

SYSREF

f_OUT/ 4

NOTE: Red traces show SYSREF going to the NCO blocks.

Figure 95. Decimation Filter Implementation for Single-Band and Wide-Bandwidth Mode

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8.3.4.3 Decimation Filters

The stop-band rejection of the decimation filters is approximately 90 dB with a pass-band bandwidth of

approximately 80%. Table 4 gives an overview of the pass-band bandwidth depending on decimation filter setting

and ADC sampling rate.

Table 4. Decimation Filter Summary and Maximum Available Output Bandwidth

BANDWIDTH ADC SAMPLE RATE = N MSPS ADC SAMPLE RATE = 3 GSPS

NO. OF DDCS

NOMINAL

PASSBAND

GAIN

OUTPUT

COMPLEX

OUTPUT

DECIMATION

SETTING

AVAILABLE

PER

CHANNEL

OUTPUT RATE

(MSPS) PER

BAND

3 dB 1 dB

BANDWIDTH OUTPUT RATE BANDWIDTH

(MHz) PER

BAND

(%)

(MSPS) PER

BAND

(MHz) PER

BAND

Divide-by-4

complex

1

2

–0.4 dB

–0.65 dB

–0.27 dB

–0.45 dB

–0.58 dB

–0.55 dB

–0.42 dB

–0.83 dB

–0.91 dB

–0.95 db

–0.78 dB

90.9

90.6

91.0

90.7

90.8

91.2

91.1

86.8

86.1

86.8

86.3

N / 4 complex

N / 6 complex

N / 8 complex

N / 9 complex

0.4 × N / 2

0.4 × N / 3

0.4 × N / 4

0.4 × N / 4.5

0.4 × N / 5

0.4 × N / 6

0.4 × N / 8

0.4 × N / 9

0.4 × N / 10

0.4 × N / 12

0.4 × N / 16

750

500

600

400

300

266.6

240

200

150

133

120

100

75

Divide-by-6

complex

Divide-by-8

complex

375

Divide-by-9

complex

333.3

300

Divide-by-10

complex

86.3 N / 10 complex

86.4 N / 12 complex

86.4 N / 16 complex

87.0 N / 18 complex

87.0 N / 20 complex

86.9 N / 24 complex

86.8 N / 32 complex

Divide-by-12

complex

250

Divide-by-16

complex

187.5

166.6

150

Divide-by-18

complex

Divide-by-20

complex

Divide-by-24

complex

125

Divide-by-32

complex

93.75

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A dual-band example with a divide-by-8 complex is shown in Figure 96.

NCO 1,

16 Bits

Band 1

Filter

8

IQ

750 MSPS

IQ Output

Band 1

3 GSPS

IQ 3 GSPS

ADC

IQ

750 MSPS

IQ Output

Band 2

8

f_S/16

Filter

NCO 2,

16 Bits

Band 2

f_S/4

Band 1

f_S/16

f_S/2

NCO 2

NCO 1

Figure 96. Dual-Band Example

The decimation filter responses normalized to the ADC sampling clock are illustrated in Figure 96 to Figure 119

and can be interpreted as follows:

Each figure contains the filter pass-band, transition bands, and alias bands, as shown in Figure 97. The x-axis in

Figure 97 shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling clock

frequency.

For example, in the divide-by-4 complex, the output data rate is an f_S/ 4 complex with a Nyquist zone of f_S/ 8 or

0.125 × f_S. The transition band is centered around 0.125 × f_Sand the alias transition band is centered at 0.375 ×

f_S. The alias bands that alias on top of the wanted signal band are centered at 0.25 × f_Sand 0.5 × f_S(and are

colored in red).

The decimation filters of the ADC32RF8x provide greater than 90-dB attenuation for the alias bands.

.and Çhat Colds .ack ꢀn

Cilter

Çransition

.and

Çop of Çransition .and

.ands Çhat !liases ꢀn

Çop of {ignal .and

Figure 97. Interpretation of the Decimation Filter Plots

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8.3.4.3.1 Divide-by-4

Peak-to-peak pass-band ripple: approximately 0.22 dB

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Passband

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-20

-40

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.02

0.04

0.06

0.08

0.1

0.12

Frequency

D023

D024

Figure 98. Divide-by-4 Filter Response

Figure 99. Divide-by-4 Filter Response (Zoomed)

8.3.4.3.2 Divide-by-6

Peak-to-peak pass-band ripple: approximately 0.38 dB

0

Pass Band

Transition Band

Alias Band

Attn Spec

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

Frequency

0.3

0.4

0.5

0

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08

Frequency

D025

D026

Figure 100. Divide-by-6 Filter Response

Figure 101. Divide-by-6 Filter Response (Zoomed)

8.3.4.3.3 Divide-by-8

Peak-to-peak pass-band ripple: approximately 0.25 dB

0

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.01

0.02

0.03

0.04

0.05

0.06

Frequency

D027

D028

Figure 102. Divide-by-8 Filter Response

Figure 103. Divide-by-8 Filter Response (Zoomed)

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8.3.4.3.4 Divide-by-9

Peak-to-peak pass-band ripple: approximately 0.39 dB

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Pass Band

Transition Band

Alias Band

Attn Spec

Pass Band

Transition Band

-20

-40

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.01

0.02

0.03

0.04

0.05

Frequency

D029

D030

Figure 104. Divide-by-9 Filter Response

Figure 105. Divide-by-9 Filter Response (Zoomed)

8.3.4.3.5 Divide-by-10

Peak-to-peak pass-band ripple: approximately 0.39 dB

0

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.01

0.02

0.03

0.04

0.05

Frequency

D029

D032

Figure 106. Divide-by-10 Filter Response

Figure 107. Divide-by-10 Filter Response (Zoomed)

8.3.4.3.6 Divide-by-12

Peak-to-peak pass-band ripple: approximately 0.36 dB

0

Passband

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

Frequency

0.3

0.4

0.5

0

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

Frequency

D033

D034

Figure 108. Divide-by-12 Filter Response

Figure 109. Divide-by-12 Filter Response (Zoomed)

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8.3.4.3.7 Divide-by-16

Peak-to-peak pass-band ripple: approximately 0.29 dB

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-20

-40

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

Frequency

D035

D036

Figure 110. Divide-by-16 Filter Response

Figure 111. Divide-by-16 Filter Response (Zoomed)

8.3.4.3.8 Divide-by-18

Peak-to-peak pass-band ripple: approximately 0.33 dB

0

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

Frequency

0.3

0.4

0.5

0

0.005

0.01

Frequency

0.015

0.02

0.025

D038

D037

Figure 112. Divide-by-18 Filter Response

Figure 113. Divide-by-18 Filter Response (Zoomed)

8.3.4.3.9 Divide-by-20

Peak-to-peak pass-band ripple: approximately 0.32 dB

0

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.2

-20

-40

-0.4

-0.6

-0.8

-1

-60

-80

-100

-120

-1.2

-1.4

0

0.1

0.2

Frequency

0.3

0.4

0.5

0

0.005

0.01

Frequency

0.015

0.02

0.025

D040

D039

Figure 114. Divide-by-20 Filter Response

Figure 115. Divide-by-20 Filter Response (Zoomed)

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8.3.4.3.10 Divide-by-24

Peak-to-peak pass-band ripple: approximately 0.30 dB

0

-0.2

-0.4

-0.6

-0.8

-1

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-20

-40

-60

-80

-100

-120

-1.2

-1.4

0

0.1

0.2

0.3

0.4

0.5

0

0.005

0.01

0.015

0.02

0.025

Frequency

D041

D042

Figure 116. Divide-by-24 Filter Response

Figure 117. Divide-by-24 Filter Response (Zoomed)

8.3.4.3.11 Divide-by-32

Peak-to-peak pass-band ripple: approximately 0.24 dB

0

Pass Band

Attn Spec

Transition Band

Alias Band

Pass Band

Transition Band

-0.1

-20

-40

-0.2

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

-60

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

0

0.005

0.01

0.015

0.02

Frequency

D043

D044

Figure 118. Divide-by-32 Filter Response

Figure 119. Divide-by-32 Filter Response (Zoomed)

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8.3.4.3.12 Latency with Decimation Options

Device latency in 12-bit bypass mode (with LMFS = 8224) is 424 clock cycles. When the DDC option is used,

latency increases as a result of decimation filters, as described in Table 5.

Table 5. Latency with different Decimation options

DECIMATION OPTION

Divide-by-4

TOTAL LATENCY, DEVICE CLOCK CYCLES

516

746

Divide-by-6

Divide-by-8

621

Divide-by-9

763.5

811

Divide-by-10

Divide-by-12

Divide-by-16

Divide-by-18

Divide-by-20

Divide-by-24

Divide-by-32

897

1045

1164

1256

1443

1773

8.3.4.4 Digital Multiplexer (MUX)

The ADC32RF8x supports a mode where the output data of the ADC channel A can be routed internally to the

digital blocks of both channel A and channel B. The ADC channel B can be powered down as shown in

Figure 120. In this manner, the ADC32RF8x can be configured as a single-channel ADC with up to four

independent DDC chains or two wideband DDC chains. All decimation filters and JESD204B format

configurations are identical to the two ADC channel operation.

N

ADC A

To JESD ChA

N

NCO

N

ADC B

To JESD ChB

NCO

Figure 120. Digital Multiplexer Option

8.3.4.5 Numerically-Controlled Oscillators (NCOs) and Mixers

The ADC32RF8x is equipped with three independent, complex NCOs per ADC channel. The oscillator generates

a complex exponential sequence, as shown in Equation 2.

x[n] = e^–jωn

where

•

frequency (ω) is specified as a signed number by the 16-bit register setting

(2)

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The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down

to 0 Hz.

Each ADC channel has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first

DDC can dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth

mode (lower decimation factors, for example, 4 and 6), there can only be one DDC for each ADC channel. The

NCO frequencies can be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB

register settings.

The NCO frequency setting is set by the 16-bit register value given by Equation 3:

DDCxNCOy ì f_S

f_NCO

=

2¹⁶

where

•

x = 0, 1

y = 1 to 4

(3)

(4)

For example:

If f_S= 2949.12 MSPS, then the NCO register setting = 38230 (decimal).

Thus, f_NCOis defined by Equation 4:

2949.12 MSPS

f_NCO= 38230ì

= 1720.35 MHz

2¹⁶

Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic

NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the

register setting.

8.3.5 NCO Switching

The first DDC (DDC0) on each ADC channel provides three different NCOs that can be used for phase-coherent

frequency hopping. This feature is available in both single-band and dual-band mode, but only affects DDC0.

The NCOs can be switched through an SPI control or by using the GPIO pins with the register configurations

shown in Table 6 for channel A (50xxh) and channel B (58Xxh). The assignment of which GPIO pin to use for

INSEL0 and INSEL1 is done based on Table 7, using registers 5438h and 5C38h. The NCO selection is done

based on the logic selection on the GPIO pins; see Table 8 and Figure 121.

Table 6. NCO Register Configurations

REGISTER

ADDRESS

DESCRIPTION

NCO CONTROL THROUGH GPIO PINS

NCO SEL pin

500Fh, 580Fh

5438h, 5C38h

Selects the NCO control through the SPI (default) or a GPIO pin.

Selects which two GPIO pins are used to control the NCO.

INSEL0, INSEL1

NCO CONTROL THROUGH SPI CONTROL

NCO SEL pin

NCO SEL

500Fh, 580Fh

5010h, 5810h

Selects the NCO control through the SPI (default) or a GPIO pin.

Selects which NCO to use for DDC0.

Table 7. GPIO Pin Assignment

INSELx[1:0] (Where x = 0 or 1)

GPIO PIN SELECTED

GPIO4

00

01

10

11

GPIO1

GPIO3

GPIO2

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Table 8. NCO Selection

NCO SEL[1]

NCO SEL[0]

NCO SELECTED

NCO1

0

1

0

1

0

1

NCO2

NCO3

n/a

NCO for DDC1 of

channel x

NCO1

NCO2

NCO3

N/A

0

1

2

3

GPIO4

GPIO1

DtLh3

GPIO2

0

1

2

3

NCO SEL[1:0]

0

1

INSEL1[1:0]

NCO SEL PIN

GPIO4

GPIO1

GPIO3

GPIO2

0

1

2

3

INSEL0[1:0]

Figure 121. NCO Switching from GPIO and SPI

8.3.6 SerDes Transmitter Interface

Each 12.3-Gbps serializer, deserializer (SerDes) LVDS transmitter output requires ac-coupling between the

transmitter and receiver. Terminate the differential pair with 100-Ω resistance (that is, two 50-Ω resistors) as

close to the receiving device as possible to avoid unwanted reflections and signal degradation, as shown in

Figure 122.

0.1 mF

DA[3:0]P,

DB[3:0]P

R_t= Z_O

Transmission Line,

VCM

Receiver

Z_O

R_t= Z_O

DA[3:0]M,

DB[3:0]M

0.1 mF

Figure 122. External Serial JESD204B Interface Connection

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8.3.7 Eye Diagrams

Figure 123 and Figure 124 show the serial output eye diagrams of the ADC32RF8x at 5.0 Gbps and 12 Gbps

against the JESD204B mask.

Figure 123. Data Eye at 5 Gbps

Figure 124. Data Eye at 12 Gbps

8.3.8 Alarm Outputs: Power Detectors for AGC Support

The GPIO pins can be configured as alarm outputs for channels A and B. The ADC32RF8x supports three

different power detectors (an absolute peak power detector, crossing detector, and RMS power detector) as well

as fast overrange from the ADC. The power detectors operate off the full-rate ADC output prior to the decimation

filters.

8.3.8.1 Absolute Peak Power Detector

In this detector mode, the peak is computed over eight samples of the ADC output. Next, the peak for a block of

N samples (N × S`) is computed over a programmable block length and then compared against a threshold to

either set or reset the peak detector output (Figure 125 and Figure 126). There are two sets of thresholds and

each set has two thresholds for hysteresis. The programmable DWELL-time counter is used for clearing the

block detector alarm output.

BLKTHHH,

BLKTHHL,

BLKTHLH,

BLKTHLL

BLKPKDET

N = [1..2¹⁶

]

>TH_High

>TH_Low

Hysteresis

and DWELL

BLKPKDETH

BLKPKDETL

S`

f_S/ 8

Block:

Peak over N

Samples (S`)

f_S/ (8N)

f_S

Output

of ADC

Peak over 8

Samples

>TL_High

>TL_Low

Hysteresis

and DWELL

DWELL

Figure 125. Peak Power Detector Implementation

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DWELL Time

THHH

THHL

BLKPKDET

Figure 126. Peak Power Detector Timing Diagram

Table 9 shows the register configurations required to set up the absolute peak power detector. The detector

operates in the f_S/ 8 clock domain; one peak sample is calculated over eight actual samples.

The automatic gain control (AGC) modes can be configured separately for channel A (54xxh) and channel B

(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).

Table 9. Registers Required for the Peak Power Detector

REGISTER

ADDRESS

DESCRIPTION

PKDET EN

5400, 5C00h

Enables peak detector

5401h, 5402h,

5403h, 5C01h,

5C02h, 5C03h

Sets the block length N of number of samples (S`). Number of actual ADC samples is 8X this

value: N is 17 bits: 1 to 2¹⁶

BLKPKDET

.

BLKTHHH,

BLKTHHL,

BLKTHLH,

BLKTHLL

5407h, 5408h,

5409h, 540Ah,

5C07h, 5C08h,

5C09h, 5C0Ah

Sets the different thresholds for the hysteresis function values from 0 to 256 (where 256 is

equivalent to the peak amplitude).

For example: if BLKTHHH is to –2 dBFS from peak, 10^{(–2 / 20)}× 256 = 203, then set 5407h and

5C07h = CBh.

When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak

detector output flags are set. In order to be reset, the computed block peak must remain

continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by

the DWELL value. This threshold is 16 bits and is specified in terms of f_S/ 8 clock cycles.

540Bh, 540Ch,

5C0Bh, 5C0Ch

DWELL

OUTSEL

GPIO[4:1]

5432h, 5433h,

5434h, 5435h

Connects the BLKPKDETH, BLKPKDETL alarms to the GPIO pins; common register.

IODIR

5437h

Selects the direction for the four GPIO pins; common register.

After configuration, reset the AGC module to start operation.

RESET AGC

542Bh, 5C2Bh

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8.3.8.2 Crossing Detector

In this detector mode the peak is computed over eight samples of the ADC output. Next, the peak for a block of

N samples (N × S`) is computed over a programmable block length and then the peak is compared against two

sets of programmable thresholds (with hysteresis). The crossing detector counts how many f_S/ 8 clock cycles

that the block detector outputs are set high over a programmable time period and compares the counter value

against the programmable thresholds. The alarm outputs are updated at the end of the time period, routed to the

GPIO pins, and held in that state through the next cycle, as shown in Figure 127 and Figure 128. Alternatively, a

2-bit format can be used but (because the ADC32RF8x has four GPIO pins available) this feature uses all four

pins for a single channel.

BLKTHHH,

FILT0LP

SEL

2-Bit Mode

10: High

00: Mid

BLKTHHL,

BLKTHLH,

BLKTHLL

1 or 2-Bit

Mode

BLKPKDET

Time

N = [1..2¹⁶

]

Constant

01: Low

>TH_High

>TH_Low

Hysteresis

and DWELL

BLKPKDETH

2-Bit Mode

S`

f_S/8

>FIL0TH_H

>FIL0TH_L

IIR LPF

IIR PK DET0

IIR PK DET1

f_S/(8N)

Block:

Peak Over N

Samples (S`)

f_S

ADC

Output

Peak Over

8 Samples

Combine

>TL_High

>TL_Low

Hysteresis

and DWELL

BLKPKDETHL

>FIL1TH_H

>FIL1TH_L

BLKPKDETL

1-Bit Mode

DWELL

With Hysteresis and Dwell

1: High

Time

Constant

1 or 2-Bit

Mode

0: Low

Figure 127. Crossing Detector Implementation

Crossing Detector Time Period

THHH

THHL

BLKPKDET

Crossing Detector Counter Threshold

Crossing Detector Counter

IIR PK DET

Figure 128. Crossing Detector Timing Diagram

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Table 10 shows the register configurations required to set up the crossing detector. The detector operates in the

f_S/ 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B (5Cxxh),

although some registers are common in 54xxh (such as the GPIO pin selection).

Table 10. Registers Required for the Crossing Detector Operation

REGISTER

ADDRESS

DESCRIPTION

PKDET EN

5400h, 5C00h

Enables peak detector

5401h, 5402h, 5403h,

5C01h, 5C02h, 5C03h

Sets the block length N of number of samples (S`).

BLKPKDET

Number of actual ADC samples is 8X this value: N is 17 bits: 1 to 2¹⁶

.

Sets the different thresholds for the hysteresis function values from 0 to 256

(where 256 is equivalent to the peak amplitude).

5407h, 5408h, 5409h,

540Ah, 5C07h, 5C08h,

5C09h, 5C0Ah

BLKTHHH, BLKTHHL,

BLKTHLH, BLKTHLL

For example: if BLKTHHH is to –2 dBFS from peak, 10^{(–2 / 20)}× 256 = 203, then

set 5407h and 5C07h = CBh.

Select block detector output or 2-bit output mode as the input to the interrupt

identification register (IIR) filter.

FILT0LPSEL

TIMECONST

540Dh, 5C0Dh

Sets the crossing detector time period for N = 0 to 15 as 2N × f_S/ 8 clock cycles.

The maximum time period is 32768 × f_S/ 8 clock cycles (approximately 87 µs at

3 GSPS).

540Eh, 540Fh,

5C0Eh, 5C0Fh

540Fh-5412h, 5C0Fh-

5C12h, 5416h-5419h,

5C16h-5C19h

Comparison thresholds for the crossing detector counter. These thresholds are 16-

bit thresholds in 2.14-signed notation. A value of 1 (4000h) corresponds to 100%

crossings, a value of 0.125 (0800h) corresponds to 12.5% crossings.

FIL0THH, FIL0THL,

FIL1THH, FIL1THL

541Dh, 541Eh, 5C1Dh,

5C1Eh

DWELLIIR

DWELL counter for the IIR filter hysteresis.

IIR0 2BIT EN,

IIR1 2BIT EN

5413h, 54114h,

5C13h, 5C114h

Enables 2-bit output format for the crossing detector.

5432h, 5433h,

5434h, 5435h

OUTSEL GPIO[4:1]

Connects the IIRPKDET0, IIRPKDET1 alarms to the GPIO pins; common register.

IODIR

5437h

Selects the direction for the four GPIO pins; common register.

After configuration, reset the AGC module to start operation.

RESET AGC

542Bh, 5C2Bh

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8.3.8.3 RMS Power Detector

In this detector mode the peak power is computed for a block of N samples over a programmable block length

and then compared against two sets of programmable thresholds (with hysteresis).

The RMS power detector circuit provides configuration options, as shown in Figure 129. The RMS power value

(1 or 2 bit) can be output onto the GPIO pins. In 2-bit output mode, two different thresholds are used whereas the

1-bit output provides one threshold together with hysteresis.

M = [1..2¹⁶

]

2^-M

2-Bit Mode

10: High

00: Mid

01: Low

f_S/8

Randomly

Pick 1 Out of

8 Samples

Accumulate

Over 2^M

Inputs

>TH_High

>TH_Low

Hysteresis

f_S

Output

of ADC

^2

PWR DET

1-Bit Mode

With Hysteresis

1: High

0: Low

1 or 2-Bit

Mode

Figure 129. RMS Power Detector Implementation

Table 11 shows the register configurations required to set up the RMS power detector. The detector operates in

the f_S/ 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B

(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).

Table 11. Registers Required for Using the RMS Power Detector Feature

REGISTER

ADDRESS

DESCRIPTION

RMSDET EN

5420h, 5C20h

Enables RMS detector

Programs the block length to be used for RMS power computation. The block length

is defined in terms of f_S/ 8 clocks.

PWRDETACCU

5421h, 5C21h

The block length can be programmed as 2^Mwith M = 0 to 16.

The computed average power is compared against these high and low thresholds.

One LSB of the thresholds represents 1 / 2¹⁶. For example: is PWRDETH is set to

–14 dBFS from peak, [10^{(–14 / 20)}]²× 2¹⁶= 2609, then set 5422h, 5423h, 5C22h,

5C23h = 0A31h.

5422h, 5423h, 5424h,

5425h, 5C22h, 5C23h,

5C24h, 5C25h

PWRDETH,

PWRDETL

RMS2BIT EN

5427h, 5C27h

Enables 2-bit output format for the RMS detector output.

5432h, 5433h,

5434h, 5435h

OUTSEL GPIO[4:1]

Connects the PWRDET alarms to the GPIO pins; common register.

IODIR

5437h

Selects the direction for the four GPIO pins; common register.

After configuration, reset the AGC module to start operation.

RESET AGC

542Bh, 5C2Bh

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8.3.8.4 GPIO AGC MUX

The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs for channel A and B.

The GPIO pins can be configured through the SPI control to output the alarm from the peak power (1 bit),

crossing detector (1 or 2 bit), faster overrange, or the RMS power output, as shown in Figure 130.

The programmable output MUX allows connecting any signal (including the NCO control) to any of the four GPIO

pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming.

IIR PK DET0 [2]

IIR PK DET1 [2]

BLKPKDETH [1]

To GPIO

BLKPKDETL [1]

AGC Pins

FOVR

PWR DET [2]

OUTSEL GPIO[4:1]

Figure 130. GPIO Output MUX Implementation

8.3.9 Power-Down Mode

The ADC32RF8x provides a lot of configurability for the power-down mode. Power-down can be enabled using

the PDN pin or the SPI register writes.

8.3.10 ADC Test Pattern

The ADC32RF8x provides several different options to output test patterns instead of the actual output data of the

ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output

data path is shown in Figure 131.

Digital Block

ADC Section

Transport Layer

Link Layer

PHY Layer

Interleaving

Engine

Data Mapping

Frame

ADC

DDC

Decimation

12-bit

Construction

Filter Block

RAMP

Scrambler

1 + x¹⁴+ x¹⁵

8b, 10b

Encoding

Serializer

JESD204B Long

Transport Layer

Test Pattern

Test

Patterns

JESD204B

Link Layer

Test Pattern

Figure 131. Test Pattern Generator Implementation

8.3.10.1 Digital Block

The ADC test pattern replaces the actual output data of the ADC. The test patterns listed in Table 12 are

available when the DDC is enabled and located in register 37h of the decimation filter page. When programmed,

the test patterns are output for each converter (M) stream. The number of converter streams per channel

increases by 2 when complex (I, Q) output or dual-band DDC is selected. The test patterns can be synchronized

for both ADC channels using the SYSREF signal.

Additionally, a 12-bit test pattern is also available.

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NOTE

The number of converters increases in dual-band DDC mode and with a complex output.

Table 12. Test Pattern Options (Register 37h and 38h in Decimation Filter Page)

BIT

NAME

DEFAULT

DESCRIPTION

Test pattern outputs onI and Q stream of channel A and B when DDC

option is chosen.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

TEST PATTERN DDC1 I-

DATA,

TEST PATTERN DDC1 Q-

DATA,

TEST PATTERN DDC2 I-

DATA,

0011 = Outputs toggle pattern: output data are an alternating sequence of

10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB every

clock cycle from code 0 to 65535

Address 37h,

38h (bits 7-0)

0000

TEST PATTERN DDC2 Q-

DATA,

0110 = Single pattern: output data are a custom pattern 1 (75h and 76h)

0111 Double pattern: output data alternate between custom pattern 1 and

custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

8.3.10.2 Transport Layer

The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the

LMFS parameters. Tail bits or 0's are added when needed. Alternatively, the JESD204B long transport layer test

pattern can be substituted instead of the ADC data with the JESD frame, as shown in Table 13.

Table 13. Transport Layer Test Mode EN (Register 01h)

BIT

NAME

DEFAULT

DESCRIPTION

Generates long transport layer test pattern mode according

to section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

4

TESTMODE EN

0

1 = Test mode disabled

8.3.10.3 Link Layer

The link layer contains the scrambler and the 8b, 10b encoding of any data passed on from the transport layer.

Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted.

The link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test

patterns do not pass through the 8b, 10b encoder and contain the options listed in Table 14.

Table 14. Link Layer Test Mode (Register 03h)

BIT

NAME

DEFAULT

DESCRIPTION

Generates a pattern according to section 5.3.3.8.2 of the

JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat the initial lane alignment (generates a K28.5

character and repeats lane alignment sequences

continuously)

7-5

LINK LAYER TESTMODE

000

100 = 12-octet random pattern (RPAT) jitter pattern

Furthermore, a 2¹⁵pseudo-random binary sequence (PRBS) can be enabled by setting up a custom test pattern

(AAAAh) in the ADC section and running AAAAh through the 8b, 10b encoder with scrambling enabled.

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8.4 Device Functional Modes

8.4.1 Device Configuration

The ADC32RF8x can be configured using a serial programming interface, as described in the Serial Interface

section. In addition, the device has one dedicated parallel pin (PDN) for controlling the power-down modes.

8.4.2 JESD204B Interface

The ADC32RF8x supports device subclass 1 with a maximum output data rate of 12.5 Gbps for each serial

transmitter.

An external SYSREF signal is used to align all internal clock phases and the local multiframe clock to a specific

sampling clock edge. This alignment allows synchronization of multiple devices in a system and minimizes timing

and alignment uncertainty. The SYNCB input is used to control the JESD204B SerDes blocks, as shown in

Figure 132.

Depending on the ADC sampling rate, the JESD204B output interface can be operated with one, two, or four

lanes per ADC channel. The JESD204B setup and configuration of the frame assembly parameters is controlled

through the SPI interface.

SysRef

SYNCB

JESD

204B

JESD204B

D[3:0]

INA

INB

JESD

204B

JESD204B

D[3:0]

Sample Clock

Figure 132. JESD Signal Overview

The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown

in Figure 133. The transport layer maps the ADC output data into the selected JESD204B frame data format and

manages if the ADC output data or test patterns are transmitted. The link layer performs the 8b, 10b data

encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally, data

from the transport layer can be scrambled.

JESD204B Block

Transport Layer

Link Layer

Frame Data

Mapping

Scrambler

1+x¹⁴+x¹⁵

8b, 10b

Encoding

D[3:0]

Comma Characters

Initial Lane

Alignment

Test Patterns

SYNCB

Figure 133. JESD Digital Block Implementation

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Device Functional Modes (continued)

8.4.2.1 JESD204B Initial Lane Alignment (ILA)

The receiving device starts the initial lane alignment process by deasserting the SYNCB signal. The SYNCB

signal can be issued using the SYNCB input pins or by setting the proper SPI bits. When a logic low is detected

on the SYNCB input, the ADC32RF8x starts transmitting comma (K28.5) characters to establish the code group

synchronization, as shown in Figure 134.

When synchronization completes, the receiving device reasserts the SYNCB signal and the ADC32RF8x starts

the initial lane alignment sequence with the next local multiframe clock boundary. The ADC32RF8x transmits four

multiframes, each containing K frames (K is SPI programmable). Each of the multiframes contains the frame start

and end symbols. The second multiframe also contains the JESD204 link configuration data.

SYSREF

LMFC Clock

LMFC Boundary

Multi

Frame

SYNCb

Transmit Data

xxx

K28.5

ILA

DATA

Code Group

Synchronization

Initial Lane Alignment

Data Transmission

Figure 134. JESD Internal Timing Information

8.4.2.2 JESD204B Frame Assembly

The JESD204B standard defines the following parameters:

•

F is the number of octets per frame clock period

L is the number of lanes per link

M is the number of converters for the device

S is the number of samples per frame

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Device Functional Modes (continued)

8.4.2.3 JESD204B Frame Assembly with Decimation (Single-Band DDC): Complex Output

Table 15 lists the available JESD204B interface formats and valid ranges for the ADC32RF8x with decimation

(single-band DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the

maximum ADC sample frequency. The sample alignment on the different lanes is shown in Table 16.

Table 15. JESD Mode Options: Single-Band Complex Output

DECIMATION

SETTING

(Complex)

RATIO

[f_SerDes/ f_CLK

(Gbps / GSPS)]

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

L

M

F

S

8

4

8

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

1

2

4

1

2

4

2

4

2

4

2

4

2

4

2

4

2

4

2

4

1

2

1

2

1

2

1

2

1

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

1

0

2

1

0

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

0

1

0

1

0

1

0

2.5

5

Divide-by-4

Divide-by-6

1 per channel

1.67

3.33

2.5

5

Divide-by-8

Divide-by-9

Divide-by-10

Divide-by-12

Divide-by-16

Divide-by-18

Divide-by-20

1 per channel

2.22

4.44

2

4

1.67

3.33

1.25

2.5

1.11

2.22

1

2

Divide-by-24

Divide-by-32

1 per channel

1.67

1.25

Table 16. JESD Sample Lane Alignments: Single-Band Complex Output

OUTPUT

LANE

LMFS

= 8411

LMFS = 4421

20X

LMFS = 4421

40X

LMFS = 8422

LMFS = 4442

LMFS = 2441

AI₀

[15:8]

AI₀

[15:8]

AI₀

[7:0]

AI₀

[15:8]

AI₀

[7:0]

DA0

AI₀

[7:0]

AI₁

[15:8]

AI₁

[7:0]

AQ₀

[15:8]

AQ₀

[7:0]

AI₀

[15:8]

AI₀

[7:0]

AI₀

[15:8]

AI₀

[7:0]

AI₁

[15:8]

AI₁

[7:0]

AI₀

[15:8]

AI₀

[7:0]

AQ₀

[15:8]

AQ₀

[7:0]

DA1

DA2

DA3

DB0

DB1

DB2

DB3

AQ₀

[15:8]

AQ₀

[15:8]

AQ₀

[7:0]

AQ₀

[15:8]

AQ₀

[7:0]

AQ₀

[15:8]

AQ₀

[7:0]

AQ₁

[15:8]

AQ₁

[7:0]

AQ₀

[7:0]

AQ₁

[15:8]

AQ₁

[7:0]

BI₀

[15:8]

BI₀

[15:8]

BI₀

[7:0]

BI₀

[15:8]

BI₀

[7:0]

BI₀

[7:0]

BI₁

[15:8]

BI₁

[7:0]

BQ₀

[15:8]

BQ₀

[7:0]

BI₀

[15:8]

BI₀

[7:0]

BI₀

[15:8]

BI₀

[7:0]

BI₁

[15:8]

BI₁

[7:0]

BI₀

[15:8]

BI₀

[7:0]

BQ₀

[15:8]

BQ₀

[7:0]

BQ₀

[15:8]

BQ₀

[15:8

BQ₀

[7:0]

BQ₀

[15:8]

BQ₀

[7:0]

BQ₀

[15:8]

BQ₀

[7:0]

BQ₁

[15:8]

BQ₁

[7:0]

BQ₀

[7:0]

BQ₁

[15:8]

BQ₁

[7:0]

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8.4.2.4 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output

Table 17 lists the available JESD204B formats and valid ranges for the ADC32RF8x with decimation (single-

band DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum

ADC sample frequency. The sample alignment on the different lanes is shown in Table 18.

Table 17. JESD Mode Options: Single-Band Real Output (Wide Bandwidth)

DECIMATION

SETTING

(Complex)

RATIO

[f_SerDes/ f_CLK

(Gbps / GSPS)]

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

L

M

F

S

8

4

8

4

2

4

1

2

4

1

4

1

4

1

20X

40X

20X

40X

1

2

0

1

2

0

1

0

1

2.5

Divide-by-4

(Divide-by-2 real)

1 per channel

5

1.67

3.33

Divide-by-6

(Divide-by-3 real)

Table 18. JESD Sample Lane Alignment: Single-Band Real Output (Wide Bandwidth)

OUTPUT

LANE

LMFS = 8224

LMFS = 4244

LMFS = 4211

DA0

DA1

DA2

DA3

DB0

DB1

DB2

DB3

A₀[15:8]

A₀[7:0]

A₁[7:0]

A₂[7:0]

A₃[7:0]

B₀[7:0]

B₁[7:0]

B₂[7:0]

B₃[7:0]

A₁[15:8]

A₂[15:8]

A₃[15:8]

B₀[15:8]

B₁[15:8]

B₂[15:8]

B₃[15:8]

A₀[15:8]

A₂[15:8]

A₀[7:0]

A₁[15:8]

A₃[15:8]

A₁[7:0]

A₃[7:0]

A₀[15:8]

A₀[7:0]

A₂[7:0]

B₀[15:8]

B₀[7:0]

B₂[7:0]

B₁[15:8]

B₃[15:8]

B₁[7:0]

B₃[7:0]

B₀[15:8]

B₀[7:0]

58

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8.4.2.5 JESD204B Frame Assembly with Decimation (Single-Band DDC): Real Output

Table 19 lists the available JESD204B formats and valid ranges for the ADC32RF8x with decimation (dual-band

DDC) when using a complex output format. The sample alignment on the different lanes is shown in Table 20.

Table 19. JESD Mode Options: Single-Band Real Output

DECIMATION

SETTING

(Complex)

RATIO

[f_SerDes/ f_CLK

(Gbps / GSPS)]

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

L

M

F

S

4

2

4

2

4

2

4

2

4

2

4

2

4

2

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

2

4

2

4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

0

2

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2.5

5

Divide-by-8

(Divide-by-4 real)

1 per channel

2.22

4.44

2

Divide-by-9

(Divide-by-4.5 real)

Divide-by-10

(Divide-by-5 real)

4

1.67

3.33

1.25

2.5

1.11

2.22

1

Divide-by-12

(Divide-by-6 real)

Divide-by-16

(Divide-by-8 real)

Divide-by-18

(Divide-by-9 real)

Divide-by-20

(Divide-by-10 real)

2

Divide-by-24

(Divide-by-12 real)

1 per channel

1.67

1.25

Divide-by-32

(Divide-by-16 real)

Table 20. JESD Sample Lane Assignment: Single-Band Real Output

OUTPUT

LANE

LMFS =

4211

LMFS = 4222

LMFS = 2221

LMFS = 2242

DA0

DA1

DB0

DB1

A₀[15:8]

A₀[7:0]

B₀[15:8]

B₀[7:0]

A₀[15:8]

A₀[7:0]

A₁[7:0]

B₀[7:0]

B₁[7:0]

A₁[15:8]

B₀[15:8]

B₁[15:8]

A₀[15:8]

A₀[7:0]

B₀[7:0]

A₀[15:8]

B₀[15:8]

A₀[7:0]

A₁[15:8]

B₁[15:8]

A₁[7:0]

B₁[7:0]

B₀[15:8]

B₀[7:0]

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8.4.2.6 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Complex Output

Table 21 lists the available JESD204B formats and valid ranges for the ADC32RF8x with decimation (dual-band

DDC) when using a complex output format. The ranges are limited by the SerDes line rate and the maximum

ADC sample frequency. The sample alignment on the different lanes is shown in Table 22.

Table 21. JESD Mode Options: Dual-Band Complex Output

DECIMATION

SETTING

(Complex)

RATIO

[f_SerDes/ f_CLK

(Gbps / GSPS)]

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

L

M

F

S

8

4

8

4

8

4

8

4

8

4

8

4

8

4

8

2

4

2

4

2

4

2

4

2

4

2

4

2

4

1

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

1

2

1

2

1

2

1

2

1

2

1

2

1

2

0

2.5

5

Divide-by-8

Divide-by-9

Divide-by-10

Divide-by-12

Divide-by-16

Divide-by-18

Divide-by-20

2 per channel

2.22

4.44

2

4

1.67

3.33

1.25

2.5

1.11

2.22

1

2

Divide-by-24

Divide-by-32

2 per channel

1.67

1.25

Table 22. JESD Sample Lane Assignment: Dual-Band Complex Output⁽¹⁾

OUTPUT LANE

DA0

LMFS = 8821

A1₀[15:8]

LMFS = 4841

A1₀[7:0]

A1Q₀[7:0]

A2I₀[7:0]

A2Q₀[7:0]

B1I₀[7:0]

B1Q₀[7:0]

B2I₀[7:0]

B2Q₀[7:0]

DA1

A1Q₀[15:8]

A2I₀[15:8]

A2Q₀[15:8]

B1I₀[15:8]

B1Q₀[15:8]

B2I₀[15:8]

B2Q₀[15:8]

A1I₀[15:8]

A2I₀[15:8]

A1I₀[7:0]

A1Q₀[15:8]

A2Q₀[15:8]

A1Q₀[7:0]

A2Q₀[7:0]

DA2

A2I₀[7:0]

DA3

DB0

DB1

B1I₀[15:8]

B2I₀[15:8]

B1I₀[7:0]

B2I₀[7:0]

B1Q₀[15:8]

B2Q₀[15:8]

B1Q₀[7:0]

B2Q₀[7:0]

DB2

DB3

(1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.

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8.4.2.7 JESD204B Frame Assembly with Decimation (Dual-Band DDC): Real Output

Table 23 lists the available JESD204B formats and valid ranges for the ADC32RF8x with decimation (dual-band

DDC) when using real output format. The ranges are limited by the SerDes line rate and the maximum ADC

sample frequency. The sample alignment on the different lanes is shown in Table 24.

Table 23. JESD Mode Options: Dual-Band Real Output

DECIMATION

SETTING

(Complex)

RATIO

[f_SerDes/ f_CLK

(Gbps / GSPS)]

NUMBER OF

ACTIVE DDCS

PLL

MODE

JESD

MODE0

JESD

MODE1

JESD

MODE2

L

M

F

S

8

4

8

4

8

4

8

4

8

4

8

4

8

4

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

1

2

4

2

4

2

4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

20X

40X

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

1

0

2

0

2

0

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

2.5

5

Divide-by-8

(Divide-by-4 real)

2 per channel

2.22

4.44

2

Divide-by-9

(Divide-by-4.5 real)

Divide-by-10

(Divide-by-5 real)

4

1.67

3.33

1.25

2.5

1.11

2.22

1

Divide-by-12

(Divide-by-6 real)

Divide-by-16

(Divide-by-8 real)

Divide-by-18

(Divide-by-9 real)

Divide-by-20

(Divide-by-10 real)

2

Divide-by-24

(Divide-by-12 real)

2 per channel

1.67

1.25

Divide-by-32

(Divide-by-16 real)

Table 24. JESD Sample Lane Assignment: Dual-Band Complex Output⁽¹⁾

OUTPUT

LMFS = 8411

LMFS = 8422

A1₀[15:8]

LMFS = 4421

LMFS = 4442

LANE

DA0

DA1

DA2

DA3

DB0

DB1

DB2

DB3

A1₀[15:8]

A1₀[7:0]

A2₀[15:8]

A2₀[7:0]

B1₀[15:8]

B1₀[7:0]

B2₀[15:8]

B2₀[7:0]

A1₀[7:0]

A1₁[7:0]

A2₀[7:0]

A2₁[7:0]

B1₀[7:0]

B1₁[7:0]

B2₀[7:0]

B2₁[7:0]

A1₁[15:8]

A2₀[15:8]

A2₁[15:8]

B1₀[15:8]

B1₁[15:8]

B2₀[15:8]

B2₁[15:8]

A1₀[15:8]

A1₀[7:0]

A2₀[7:0]

A1₀[15:8]

A2₀[15:8]

A1₀[7:0]

A1₁[15:8]

A2₁[15:8]

A1₁[7:0]

A2₁[7:0]

A2₀[15:8]

A2₀[7:0]

B1₀[15:8]

B2₀[15:8]

B1₀[7:0]

B2₀[7:0]

B1₀[15:8]

B2₀[15:8]

B1₀[7:0]

B2₀[7:0]

B1₁[15:8]

B2₁[15:8]

B1₁[7:0]

B2₁[7:0]

(1) Blue and green shading indicates the two bands for channel A; yellow and orange shading indicates the two bands for channel B.

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8.4.3 Serial Interface

The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), and SDIN (serial interface data) pins. Serially shifting bits into the

device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active

(low), as shown in Figure 135. The interface can function with SCLK frequencies from 20 MHz down to low

speeds (of a few hertz) and also with a non-50% SCLK duty cycle, as shown in Table 25.

The SPI access uses 24 bits consisting of eight register data bits, 12 register address bits, and four special bits

to distinguish between read/write, page and register, and individual channel access, as described in Table 26.

Register Address [11:0]

Register Data [7:0]

SDIN

SCLK

R/W

M

P

CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

t_DH

t_SCLK

t_DSU

t_SLOADH

t_SLOADS

SEN

RESET

Figure 135. SPI Timing Diagram

Table 25. SPI Timing Information

MIN

TYP

MAX

UNIT

MHz

ns

f_SCLK

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIN setup time

)

1

50

10

20

t_SLOADS

t_SLOADH

t_DSU

ns

t_DH

SDIN hold time

ns

t_SDOUT

Delay between SCLK falling edge to SDOUT

10

ns

62

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Table 26. SPI Input Description

SPI BIT

DESCRIPTION

OPTIONS

0 = SPI write

1 = SPI read back

R/W bit

M bit

Read/write bit

0 = Analog SPI bank (master)

1 = All digital SPI banks (main digital, interleaving,

decimation filter, JESD digital, and so forth)

SPI bank access

JESD page selection bit

0 = Page access

1 = Register access

P bit

SPI access for a specific channel of the JESD SPI

bank

0 = Channel A

1 = Channel B

CH bit

ADDR[11:0]

DATA[7:0]

SPI address bits

SPI data bits

—

Figure 136 shows the SDOUT timing when data are read back from a register. Data are placed on the SDOUT

bus at the SCLK falling edge so that the data can be latched at the SCLK rising edge by the external receiver.

SCLK

t_SDOUT

SDOUT

Figure 136. SDOUT Timing

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8.4.3.1 Serial Register Write: Analog Bank

The internal register of the ADC32RF8x analog bank (Figure 137) can be programmed by:

1. Driving the SEN pin low.

2. Initiating a serial interface cycle selecting the page address of the register whose content must be written. To

select the master page: write address 0012h with 04h. To select the ADC page: write address 0011h with

FFh.

3. Writing the register content. When a page is selected, multiple registers located in the same page can be

programmed.

Register Address [11:0]

Register Data [7:0]

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SEN

RESET

Figure 137. SPI Write Timing Diagram for the Analog Bank

8.4.3.2 Serial Register Readout: Analog Bank

Contents of the registers located in the two pages of the analog bank (Figure 138) can be readback by:

1. Driving the SEN pin low.

2. Selecting the page address of the register whose content must be read. Master page: write address 0012h

with 04h. ADC page: write address 0011h with FFh.

3. Setting the R/W bit to 1 and writing the address to be read back.

4. Reading back the register content on the SDOUT pin. When a page is selected, the contents of multiple

registers located in same page can be readback.

Register Address [11:0]

Register Data [7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SEN

RESET

SDOUT

D7 D6 D5 D4 D3 D2 D1 D0

SDOUT [7:0]

Figure 138. SPI Read Timing Diagram for the Analog Bank

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8.4.3.3 Serial Register Write: Digital Bank

The digital bank contains seven pages (Offset Corrector Page for channel A and B; Digital Gain Page for channel

A and B; Main digital Page for channel A and B; and JESD Digital Page). The timing for the individual page

selection is shown in Figure 139. The registers located in the pages of the digital bank can be programmed by:

1. Driving the SEN pin low.

2. Setting the M bit to 1 and specifying the page with with the desired register. There are seven pages in Digital

Bank. These pages can be selected by appropriately programming register bits DIGITAL BANK PAGE SEL,

located in addresses 002h, 003h, and 004h, using three consecutive SPI cycles. Addressing in a SPI cycle

begins with 4xxx when selecting a page from digital bank because the M bit must be set to 1.

–

To select the offset corrector page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h

with 00h.

To select the offset corrector page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h

with 00h.

To select the digital gain page channel A: write address 4004h with 61h, 4003h with 00h, and 4002h with

05h.

To select the digital gain page channel B: write address 4004h with 61h, 4003h with 01h, and 4002h with

05h.

To select the main digital page channel A: write address 4004h with 68h, 4003h with 00h, and 4002h with

00h.

To select the main digital page channel B: write address 4004h with 68h, 4003h with 01h, and 4002h with

00h.

To select the JESD digital page: write address 4004h with 69h, 4003h with 00h, and 4002h with 00h.

Register Address [11:0]

Register Data [7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SEN

RESET

Figure 139. SPI Write Timing Diagram for Digital Bank Page Selection

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3. Writing into the desired register by setting both the M bit and P bit to 1. Write register content. When a page

is selected, multiple writes into the same page can be done. Addressing in an SPI cycle begins with 6xxx

when selecting a page from the digital bank because the M bit must be set to 1, as shown in Figure 140.

Note that the JESD digital page is common for both channels. The CH bit can be used to distinguish

between two channels when programming registers in the JESD digital page. When CH = 0, registers are

programmed for channel B; when CH = 1, registers are programmed for channel A. Thus, an SPI cycle to

program registers for channel B begins with 6xxx and channel A begins with 7xxx.

Register Address [11:0]

Register Data [7:0]

0

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

Figure 140. SPI Write Timing Diagram for Digital Bank Register Write

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8.4.3.4 Serial Register Readout: Digital Bank

Readback of the register in one of the digital banks (as shown in Figure 141) can be accomplished by:

1. Driving the SEN pin low.

2. Selecting the page in the digital page: follow step 2 in the Serial Register Write: Digital Bank section.

3. Set the R/W, M, and P bits to 1, select channel A or channel B, and write the address to be read back.

–

JESD digital page: use the CH bit to select channel B (CH = 0) or channel A (CH = 1).

4. Read back the register content on the SDOUT pin. When a page is selected, multiple read backs from the

same page can be done.

Register Address [11:0]

Register Data [7:0] = XX

1

0

SDIN

SCLK

R/W

M

P

CH

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

SEN

RESET

SDOUT

D7

D6

D5

D4

D3

D2

D1

D0

SDOUT [7:0]

Figure 141. SPI Read Timing Diagram for the Digital Bank

8.4.3.5 Serial Register Write: Decimation Filter and Power Detector Pages

The decimation filter and power detector pages are special pages that accept direct addressing. The sampling

clock and SYSREF signal are required to properly configure the decimation settings. Registers located in these

pages can be programmed in one SPI cycle (Figure 142).

1. Drive the SEN pin low.

2. Directly write to the decimation filter or power detector pages. To program registers in these pages, set M = 1

and CH = 1. Additionally, address bit A[10] selects the decimation filter page (A[10] = 0) or the power

detector page (A[10] = 1). Address bit A[11] selects channel A (A[11] = 0) or channel B (A[11] = 1).

–

Decimation filter page: write address 50xxh for channel A or 58xxh for channel B.

Power detector page: write address 54xxh for channel A or 5Cxxh for channel B.

Example: Writing address 5001h with 02h selects the decimation filter page for channel A and programs

decimation factor of divide-by-8 (complex output).

Register Address [7:0]

Register Data [7:0]

0

1

0

1

0/1 0/1

0

R/W

SDIN

SCLK

M

P

CH A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SEN

RESET

Figure 142. SPI Write Timing Diagram for the Decimation and Power Detector Pages

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8.5.1 Example Register Writes

This section provides three different example register writes. Table 28 describes a global power-down register

write, Table 29 describes the register writes when the scrambler is enabled, and Table 30 describes the register

writes for 8X decimation for channels A and B (complex output, 1 DDC mode) with the NCO set to 1.8 GHz (f_S=

3 GSPS) and the JESD format configured to LMFS = 4421.

Table 28. Global Power-Down

ADDRESS

12h

DATA

04h

COMMENT

Set the master page

20h

01h

Set the global power-down

Table 29. Scrambler Enable

ADDRESS

4004h

DATA

69h

COMMENT

Select the digital JESD page

4003h

00h

6006h

80h

Scrambler enable, channel A

Scrambler enable, channel B

7006h

80h

Table 30. 8X Decimation for Channel A and B

ADDRESS

4004h

4003h

6000h

4003h

6000h

4004h

4003h

6002h

7002h

5000h

5001h

5007h

5008h

5014h

5801h

5807h

5808h

5814h

DATA

COMMENT

68h

00h

01h

00h

01h

00h

69h

00h

01h

02h

9Ah

99h

01h

02h

9Ah

99h

01h

Select the main digital page for channel A

Issue a digital reset for channel A

Clear the digital for reset channel A

Select the main digital page for channel B

Issue a digital reset for channel B

Clear the digital reset for channel B

Select the digital JESD page

Set JESD MODE0 = 1, channel A

Set JESD MODE0 = 1, channel B

Enable the DDC, channel A

Set decimation to 8X complex

Set the LSB of DDC0, NCO1 to 9Ah (f_NCO= 1.8 GHz, f_S= 3 GSPS)

Set the MSB of DDC0, NCO1 to 99h (f_NCO= 1.8 GHz, f_S= 3 GSPS)

Enable the 6-dB digital gain of DDC0

Set decimation to 8X complex

Set the LSB of DDC0, NCO1 to 9Ah (f_NCO= 1.8 GHz, f_S= 3 GSPS)

Set the MSB of DDC0, NCO1 to 99h (f_NCO= 1.8 GHz, f_S= 3 GSPS)

Enable the 6-dB digital gain of DDC0

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8.5.2 Register Descriptions

8.5.2.1 General Registers

8.5.2.1.1 Register 000h (address = 000h), General Registers

Figure 145. Register 000h

7

6

0

5

0

4

0

3

0

2

0

1

0

RESET

R/W-0h

RESET

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 31. Register 000h Field Descriptions

Bit

Field

Type

Reset

Description

7

RESET

R/W

0h

0 = Normal operation

1 = Internal software reset, clears back to 0

6-1

0

W

0h

Must write 0

0 = Normal operation⁽¹⁾

RESET

R/W

1 = Internal software reset, clears back to 0

(1) Both bits (7, 0) must be set simultaneously to perform a reset.

8.5.2.1.2 Register 002h (address = 002h), General Registers

Figure 146. Register 002h

7

6

5

4

3

2

1

0

DIGITAL BANK PAGE SEL[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 32. Register 002h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIGITAL BANK PAGE SEL[7:0]

R/W

0h

Program the JESD BANK PAGE SEL[23:0] bits to access the

desired page in the JESD bank.

680000h = Main digital page CHA selected

680100h = Main digital page CHB selected

610000h = Digital function page CHA selected

610100h = Digital function page CHB selected

690000h = JESD digital page selected

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8.5.2.1.3 Register 003h (address = 003h), General Registers

Figure 147. Register 003h

7

6

5

4

3

2

1

0

DIGITAL BANK PAGE SEL[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 33. Register 003h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIGITAL BANK PAGE SEL[15:8]

R/W

0h

Program the JESD BANK PAGE SEL[23:0] bits to access the

desired page in the JESD bank.

680000h = Main digital page CHA selected

680100h = Main digital page CHB selected

610000h = Digital function page CHA selected

610100h = Digital function page CHB selected

690000h = JESD digital page selected

8.5.2.1.4 Register 004h (address = 004h), General Registers

Figure 148. Register 004h

7

6

5

4

3

2

1

0

DIGITAL BANK PAGE SEL[23:16]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 34. Register 004h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DIGITAL BANK PAGE SEL[23:16]

R/W

0h

Program the JESD BANK PAGE SEL[23:0] bits to access the

desired page in the JESD bank.

680000h = Main digital page CHA selected

680100h = Main digital page CHB selected

610000h = Digital function page CHA selected

610100h = Digital function page CHB selected

690000h = JESD digital page selected

8.5.2.1.5 Register 010h (address = 010h), General Registers

Figure 149. Register 010h

7

0

6

0

5

0

4

3

2

0

1

0

3 or 4 WIRE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write; -n = value after reset

Table 35. Register 010h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

3 or 4 WIRE

R/W

0h

0 = 4-wire SPI (default)

1 = 3-wire SPI where SDIN become input or output

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8.5.2.1.6 Register 011h (address = 011h), General Registers

Figure 150. Register 011h

7

6

5

4

3

2

1

0

ADC PAGE SEL

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 36. Register 011h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

ADC PAGE SEL

R/W

0h

00000000 = Normal operation, ADC page is not selected

11111111 = ADC page is selected; MASTER PAGE SEL must

be set to 0

8.5.2.1.7 Register 012h (address = 012h), General Registers

Figure 151. Register 012h

7

0

6

0

5

0

4

3

2

1

0

MASTER PAGE SEL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 37. Register 012h Field Descriptions

Bit

7-3

2

Field

Type

W

Reset

0h

Description

0

Must write 0

MASTER PAGE SEL

R/W

0h

0 = Normal operation

1 = Selects the master page address; ADC PAGE must be set

to 0

1-0

0

W

0h

Must write 0

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8.5.3 Master Page (M = 0)

8.5.3.1 Register 020h (address = 020h), Master Page

Figure 152. Register 020h

7

0

6

0

5

0

4

3

0

2

0

1

0

PDN SYSREF

R/W-0h

PDN CHB

R/W-0h

GLOBAL PDN

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 38. Register 020h Field Descriptions

Bit

7-5

4

Field

Type

W

Reset

0h

Description

0

Must write 0

PDN SYSREF

R/W

0h

This bit powers down the SYSREF input buffer.

0 = Normal operation

1 = SYSREF input capture buffer is powered down and further

SYSREF input pulses are ignored

3-2

1

0

W

0h

Must write 0

PDN CHB

R/W

This bit powers down channel B.

0 = Normal operation

1 = Channel B is powered down

0

GLOBAL PDN

R/W

0h

This bit enables the global power-down.

0 = Normal operation

1 = Global power-down enabled

8.5.3.2 Register 032h (address = 032h), Master Page

Figure 153. Register 032h

7

0

6

0

5

4

3

2

0

1

0

INCR CM

IMPEDANCE

0

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 39. Register 032h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0

INCR CM IMPEDANCE

R/W

0h

Only use this bit when analog inputs are dc-coupled to the

driver.

0 = VCM buffer directly drives the common point of biasing

resistors.

1 = VCM buffer drives the common point of biasing resistors with

> 5 kΩ

4-0

0

W

0h

Must write 0

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8.5.3.3 Register 039h (address = 039h), Master Page

Figure 154. Register 039h

7

0

6

5

0

4

3

0

2

0

1

0

ALWAYS

WRITE 1

ALWAYS

WRITE 1

PDN CHB EN

R/W-0h

SYNC TERM DIS

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 40. Register 039h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0

6

ALWAYS WRITE 1

W

0h

Always set this bit to 1

Must write 0

5

0

W

0h

4

ALWAYS WRITE 1

W

0h

Always set this bit to 1

Must write 0

3-2

1

0

W

0h

PDN CHB EN

R/W

0h

This bit enables the power-down control of channel B through

the SPI in register 20h.

0 = PDN control disabled

1 = PDN control enabled

0

SYNC TERM DIS

R/W

0h

This bit disables the on-chip, 100-Ω termination resistors on the

SYNCB input.

0 = On-chip, 100-Ω termination enabled

1 = On-chip, 100-Ω termination disabled

8.5.3.4 Register 03Ch (address = 03Ch), Master Page

Figure 155. Register 03Ch

7

0

6

5

4

3

2

0

1

0

SYSREF DEL EN

R/W-0h

0

SYSREF DEL[4:3]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 41. Register 03Ch Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0

6

SYSREF DEL EN

R/W

0h

This bit allows an internal delay to be added to the SYSREF

input.

0 = SYSREF delay disabled

1 = SYSREF delay enabled through register settings [3Ch (bits

1-0), 5Ah (bits 7-5)]

5-2

1-0

0

W

0h

Must write 0

SYSREF DEL[4:3]

R/W

When the SYSREF delay feature is enabled (3Ch, bit 6) the

delay can be adjusted in 25-ps steps; the first step is 175 ps.

The PVT variation of each 25-ps step is ±10 ps. The 175-ps step

is ±50 ps; see Table 43.

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8.5.3.5 Register 05Ah (address = 05Ah), Master Page

Figure 156. Register 05Ah

7

6

5

4

0

3

0

2

0

1

0

SYSREF DEL[2:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 42. Register 05Ah Field Descriptions

Bit

7

Field

Type

W

Reset

Description

SYSREF DEL2

SYSREF DEL1

SYSREF DEL0

0

0h

When the SYSREF delay feature is enabled (3Ch, bit 6) the

delay can be adjusted in 25-ps steps; the first step is 175 ps.

The PVT variation of each 25-ps step is ±10 ps. The 175-ps step

is ±50 ps; see Table 43.

6

R/W

W

5

4-0

W

0h

Must write 0

Table 43. SYSREF DEL[2:0] Bit Settings

STEP

SETTING

01000

00111

00110

00101

00100

00011

STEP (NOM)

175 ps

25 ps

TOTAL DELAY (NOM)

175 ps

1

2

3

4

5

6

200 ps

25 ps

225 ps

25 ps

250 ps

25 ps

275 ps

25 ps

300 ps

8.5.3.6 Register 03Dh (address = 3Dh), Master Page

Figure 157. Register 03Dh

7

0

6

0

5

0

4

0

3

0

2

1

0

JESD OUTPUT SWING

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 44. Register 03Dh Field Descriptions

Bit

7-3

2-0

Field

Type

W

Reset

0h

Description

0

Must write 0

JESD OUTPUT SWING

R/W

0h

These bits select the output amplitude, V_OD(mV_PP), of the JESD

transmitter for all lanes.

0 = 860 mV_PP

1= 810 mV_PP

2 = 770 mV_PP

3 = 745 mV_PP

4 = 960 mV_PP

5 = 930 mV_PP

6 = 905 mV_PP

7 = 880 mV_PP

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8.5.3.7 Register 057h (address = 057h), Master Page

Figure 158. Register 057h

7

0

6

0

5

0

4

3

2

0

1

0

SEL SYSREF REG

R/W-0h

ASSERT SYSREF REG

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 45. Register 057h Field Descriptions

Bit

7-5

4

Field

Type

W

Reset

0h

Description

0

Must write 0

SEL SYSREF REG

R/W

0h

SYSREF can be asserted using this bit. Ensure that the SEL

SYSREF REG register bit is set high before using this bit; see

Using SYSREF .

0 = SYSREF is logic low

1 = SYSREF is logic high

3

ASSERT SYSREF REG

R/W

W

0h

Set this bit to use the SPI register to assert SYSREF.

0 = SYSREF is asserted by device pins

1 = SYSREF can be asserted by the ASSERT SYSREF REG

register bit

Other bits = 0

2-0

0

Must write 0

8.5.3.8 Register 058h (address = 058h), Master Page

Figure 159. Register 058h

7

0

6

0

5

4

3

2

0

1

0

SYNCB POL

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 46. Register 058h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0

SYNCB POL

R/W

0h

This bit inverts the SYNCB polarity.

0 = Polarity is not inverted; this setting matches the timing

diagrams in this document and is the proper setting to use

1 = Polarity is inverted

4-0

0

W

0h

Must write 0

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8.5.4 ADC Page (FFh, M = 0)

8.5.4.1 Register 03Fh (address = 03Fh), ADC Page

Figure 160. Register 03Fh

7

0

6

0

5

0

4

0

3

0

2

1

0

SLOW SP EN1

R/W-0h

W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 47. Register 03Fh Field Descriptions

Bit

7-3

2

Field

Type

W

Reset

0h

Description

0

Must write 0

SLOW SP EN1

R/W

0h

This bit must be enabled for clock rates below 2.5 GSPS.

0 = ADC sampling rates are faster than 2.5 GSPS

1 = ADC sampling rates are slower than 2.5 GSPS

1-0

0

W

0h

Must write 0

8.5.4.2 Register 042h (address = 042h), ADC Page

Figure 161. Register 042h

7

0

6

0

5

0

4

3

2

0

1

0

SLOW SP EN2

R/W-0h

0

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 48. Register 042h Field Descriptions

Bit

7-5

4

Field

Type

W

Reset

0h

Description

0

Must write 0

SLOW SP EN2

R/W

0h

This bit must be enabled for clock rates below 2.5 GSPS.

0 = ADC sampling rates are faster than 2.5 GSPS

1 = ADC sampling rates are slower than 2.5 GSPS

3-0

0

W

0h

Must write 0

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8.5.5 Digital Function Page (610000h, M = 1 for Channel A and 610100h, M = 1 for Channel B)

8.5.5.1 Register A6h (address = 0A6h), Digital Function Page

Figure 162. Register 0A6h

7

0

6

0

5

0

4

0

3

2

1

0

DIG GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 49. Register 0A6h Field Descriptions

Bit

7-4

3-0

Field

Type

W

Reset

0h

Description

0

Must write 0

DIG GAIN

R/W

0h

These bits set the digital gain of the ADC output data prior to

decimation up to 11 dB; see Table 50.

Table 50. DIG GAIN Bit Settings

SETTING

0000

0001

0010

…

DIGITAL GAIN

0 dB

1 dB

2 dB

…

1010

1011

10 dB

11 dB

8.5.6 Offset Corr Page Channel A (610000h, M = 1)

8.5.6.1 Register 034h (address = 034h), Offset Corr Page Channel A

Figure 163. Register 034h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

SEL EXT EST

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 51. Register 034h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

SEL EXT EST

R/W

0h

This bit selects the external estimate for the offset correction

block; see the Using DC Coupling in the ADC32RF8x section.

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8.5.6.2 Register 068h (address = 068h), Offset Corr Page Channel A

Figure 164. Register 068h

7

6

0

5

4

0

3

0

2

1

0

DIS

OFFSET

CORR

FREEZE OFFSET

CORR

ALWAYS WRITE 1

R/W-0h

ALWAYS WRITE 1

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 52. Register 068h Field Descriptions

Bit

Field

Type

Reset

Description

7

FREEZE OFFSET CORR

R/W

0h

Use this bit and bits 5 and 1 to freeze the offset estimation

process of the offset corrector; see the Using DC Coupling in

the ADC32RF8x section.

011 = Apply this setting after powering up the device

111 = Offset corrector is frozen, does not estimate offset

anymore, and applies the last computed value.

Others = Do not use

6

5

0

W

0h

Must write 0

ALWAYS WRITE 1

R/W

Always write this bit as 1 for the offset correction block to work

properly.

4-3

2

0

W

0h

Must write 0

DIS OFFSET CORR

R/W

0 = Offset correction block works and removes f_S/ 8, f_S/ 4,

3f_S/ 8, and f_S/ 2 spurs

1 = Offset correction block is disabled

1

0

ALWAYS WRITE 1

0

R/W

W

0h

Always write this bit as 1 for the offset correction block to work

properly.

Must write 0

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8.5.7 Offset Corr Page Channel B (610000h, M = 1)

8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B

Figure 165. Register 068h

7

6

0

5

4

0

3

0

2

1

0

DIS

OFFSET

CORR

FREEZE OFFSET

CORR

ALWAYS WRITE 1

R/W-0h

ALWAYS WRITE 1

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 53. Register 068h Field Descriptions

Bit

Field

Type

Reset

Description

7,5,1

FREEZE OFFSET CORR

R/W

0h

Use this bit and bits 5 and 1 to freeze the offset estimation

process of the offset corrector; see the Using DC Coupling in

the ADC32RF8x section.

011 = Apply this setting after powering up the device

111 = Offset corrector is frozen, does not estimate offset

anymore, and applies the last computed value.

Others = Do not use

6

5

0

W

0h

Must write 0

ALWAYS WRITE 1

R/W

Always write this bit as 1 for the offset correction block to work

properly.

4-3

2

0

W

0h

Must write 0

DIS OFFSET CORR

R/W

0 = Offset correction block works and removes f_S/ 8, f_S/ 4,

3f_S/ 8, and f_S/ 2 spurs

1 = Offset correction block is disabled

1

0

ALWAYS WRITE 1

0

R/W

W

0h

Always write this bit as 1 for the offset correction block to work

properly.

Must write 0

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8.5.8 Digital Gain Page (610005h, M = 1 for Channel A and 610105h, M = 1 for Channel B)

8.5.8.1 Register 0A6h (address = 0A6h), Digital Gain Page

Figure 166. Register 0A6h

7

0

6

0

5

0

4

0

3

2

1

0

DIGITAL GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 54. Register 0A6h Field Descriptions

Bit

7-4

3-0

Field

Type

W

Reset

0h

Description

0

Must write 0

DIGITAL GAIN

R/W

0h

These bits apply a digital gain to the ADC data (before the DDC)

up to 11 dB.

0000 = Default

0001 = 1 dB

1011 = 11 dB

Others = Do not use

8.5.9 Main Digital Page Channel A (680000h, M = 1)

8.5.9.1 Register 000h (address = 000h), Main Digital Page Channel A

Figure 167. Register 000h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIG CORE RESET GBL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 55. Register 000h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DIG CORE RESET GBL

R/W

0h

Pulse this bit (0 →1 →0) to reset the digital core (applies to both

channel A and B).

All Nyquist zone settings take effect when this bit is pulsed.

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8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A

Figure 168. Register 0A2h

7

0

6

0

5

0

4

0

3

2

1

0

NQ ZONE EN

R/W-0h

NYQUIST ZONE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 56. Register 0A2h Field Descriptions

Bit

7-4

3

Field

Type

W

Reset

0h

Description

0

Must write 0

NQ ZONE EN

R/W

0h

This bit allows for specification of the operating Nyquist zone.

0 = Nyquist zone specification disabled

1 = Nyquist zone specification enabled

2-0

NYQUIST ZONE

R/W

0h

These bits specify the operating Nyquist zone for the analog

correction loop.

Set the NQ ZONE EN bit before programming these bits.

For example, at s 3-GSPS chip clock, the first Nyquist zone is

from dc to 1.5 GHz, the second Nyquist zone is from 1.5 GHz to

3 GHz, and so on.

000 = First Nyquist zone (dc – f_S/ 2)

001 = Second Nyquist zone (f_S/ 2 – f_S)

010 = Third Nyquist zone

011 = Fourth Nyquist zone

8.5.10 Main Digital Page Channel B (680001h, M = 1)

8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B

Figure 169. Register 000h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIG CORE RESET GBL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 57. Register 000h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DIG CORE RESET GBL

R/W

0h

Pulse this bit (0 →1 →0) to reset the digital core (applies to both

channel A and B).

All Nyquist zone settings take effect when this bit is pulsed.

88

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8.5.10.2 Register 0A2h (address = 0A2h), Main Digital Page Channel B

Figure 170. Register 0A2h

7

0

6

0

5

0

4

0

3

2

1

0

NQ ZONE EN

R/W-0h

NYQUIST ZONE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 58. Register 0A2h Field Descriptions

Bit

7-4

3

Field

Type

W

Reset

0h

Description

0

Must write 0

NQ ZONE EN

R/W

0h

This bit allows for specification of the operating Nyquist zone.

0 = Nyquist zone specification disabled

1 = Nyquist zone specification enabled

2-0

NYQUIST ZONE

R/W

0h

These bits specify the operating Nyquist zone for the analog

correction loop.

Set the NQ ZONE EN bit before programming these bits.

For example, at a 3-GSPS chip clock, first Nyquist zone is from

dc to 1.5 GHz, the second Nyquist zone is from 1.5 GHz to 3

GHz, and so on.

000 = First Nyquist zone (dc – f_S/ 2)

001 = Second Nyquist zone (f_S/ 2 – f_S)

010 = Third Nyquist zone

011 = Fourth Nyquist zone

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8.5.11 JESD Digital Page (6900h, M = 1)

8.5.11.1 Register 001h (address = 001h), JESD Digital Page

Figure 171. Register 001h

7

6

0

5

0

4

3

0

2

1

0

CTRL K

R/W-0h

TESTMODE EN

R/W-0h

LANE ALIGN

R/W-0h

FRAME ALIGN

R/W-0h

TX LINK DIS

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 59. Register 001h Field Descriptions

Bit

Field

Type

Reset

Description

7

CTRL K

R/W

0h

This bit is the enable bit for the number of frames per

multiframe.

0 = Default is five frames per multiframe

1 = Frames per multiframe can be set in register 06h

6-5

4

0

R/W

0h

0

Must write 0

TESTMODE EN

This bit generates a long transport layer test pattern mode

according to section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

3

2

0

W

0h

Must write 0

LANE ALIGN

R/W

This bit inserts a lane alignment character (K28.3) for the

receiver to align to the lane boundary per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts lane alignment characters

1

0

FRAME ALIGN

TX LINK DIS

R/W

0h

This bit inserts a frame alignment character (K28.7) for the

receiver to align to the frame boundary per section 5.3.35 of the

JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

This bit disables sending the initial link alignment (ILA) sequence

when SYNC is deasserted.

0 = Normal operation

1 = ILA disabled

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8.5.11.2 Register 002h (address = 002h ), JESD Digital Page

Figure 172. Register 002h

7

6

5

0

4

0

3

2

1

0

SYNC REG

R/W-0h

SYNC REG EN

R/W-0h

12BIT MODE

R/W-0h

JESD MODE0

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 60. Register 002h Field Descriptions

Bit

Field

Type

Reset

Description

7

SYNC REG

R/W

0h

This bit provides SYNC control through the SPI.

0 = Normal operation

1 = ADC output data are replaced with K28.5 characters

6

SYNC REG EN

R/W

0h

This bit is the enable bit for SYNC control through the SPI.

0 = Normal operation

1 = SYNC control through the SPI is enabled (ignores the

SYNCB input pins)

5-4

3-2

0

W

0h

Must write 0

12BIT MODE

R/W

This bit enables the 12-bit output mode for more efficient data

packing.

00 = Normal operation, 14-bit output

01, 10 = Unused

11 = High-efficient data packing enabled

1-0

JESD MODE0

R/W

0h

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section.

00 = 0

01 = 1

10 = 2

11 = 3

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8.5.11.3 Register 003h (address = 003h), JESD Digital Page

Figure 173. Register 003h

7

6

5

4

3

2

1

0

LMFC MASK

RESET

LINK LAYER TESTMODE

R/W-0h

LINK LAY RPAT

R/W-0h

JESD MODE1

R/W-1h

JESD MODE2

R/W-0h

RAMP 12BIT

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 61. Register 003h Field Descriptions

Bit

Field

Type

Reset

Description

7-5

LINK LAYER TESTMODE

R/W

0h

These bits generate a pattern according to section 5.3.3.8.2 of

the JESD204B document.

000 = Normal ADC data

001 = D21.5 (high-frequency jitter pattern)

010 = K28.5 (mixed-frequency jitter pattern)

011 = Repeat initial lane alignment (generates a K28.5 character

and repeats lane alignment sequences continuously)

100 = 12-octet RPAT jitter pattern

4

LINK LAY RPAT

R/W

0h

This bit changes the running disparity in a modified RPAT

pattern test mode (only when link layer test mode = 100).

0 = Normal operation

1 = Changes disparity

3

2

LMFC MASK RESET

JESD MODE1

R/W

0h

1h

0 = Normal operation

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section

1

0

JESD MODE2

RAMP 12BIT

R/W

0h

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section

12-bit RAMP test pattern.

0 = Normal data output

1 = Digital output is the RAMP pattern

8.5.11.4 Register 004h (address = 004h), JESD Digital Page

Figure 174. Register 004h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

REL ILA SEQ

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 62. Register 004h Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0

REL ILA SEQ

R/W

0h

These bits delay the generation of the lane alignment sequence

by 0, 1, 2, or 3 multiframes after the code group synchronization.

00 = 0 multiframe delays

01 = 1 multiframe delay

10 = 2 multiframe delays

11 = 3 multiframe delays

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8.5.11.5 Register 006h (address = 006h), JESD Digital Page

Figure 175. Register 006h

7

6

0

5

0

4

0

3

0

2

0

1

0

SCRAMBLE EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 63. Register 006h Field Descriptions

Bit

Field

Type

Reset

Description

7

SCRAMBLE EN

R/W

0h

This bit is the scramble enable bit in the JESD204B interface.

0 = Scrambling disabled

1 = Scrambling enabled

6-0

0

W

0h

Must write 0

8.5.11.6 Register 007h (address = 007h), JESD Digital Page

Figure 176. Register 007h

7

0

6

0

5

0

4

3

2

1

0

FRAMES PER MULTIFRAME (K)

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 64. Register 007h Field Descriptions

Bit

7-5

4-0

Field

Type

W

Reset

0h

Description

0

Must write 0

FRAMES PER MULTIFRAME (K)

R/W

0h

These bits set the number of multiframes.

Actual K is the value in hex + 1 (that is, 0Fh is K = 16).

8.5.11.7 Register 016h (address = 016h), JESD Digital Page

Figure 177. Register 016h

7

0

6

5

4

3

0

2

0

1

0

40x MODE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 65. Register 016h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0

6-4

40x MODE

R/W

0h

This register must be set for 40X mode operation.

000 = Register is set for 20X and 80X mode

111 = Register must be set for 40X mode

3-0

0

W

0h

Must write 0

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8.5.11.8 Register 017h (address = 017h), JESD Digital Page

Figure 178. Register 017h

7

0

6

0

5

0

4

0

3

2

1

0

Lane0

POL

Lane1

POL

Lane2

POL

Lane3

POL

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 66. Register 017h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

Must write 0

0

6-4

3-0

0

R/W

W

0h

Lane[3:0] POL

0h

These bits set the polarity of the individual JESD output lanes.

0 = Polarity as given in the pinout (noninverted)

1 = Inverts polarity (positive, P, or negative, M)

8.5.11.9 Register 032h-035h (address = 032h-035h), JESD Digital Page

Figure 179. Register 032h

7

6

5

4

3

2

1

0

SEL EMP LANE 0

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

W-0h

Figure 180. Register 033h

7

6

5

4

3

1

0

SEL EMP LANE 1

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

W-0h

Figure 181. Register 034h

7

6

5

4

3

1

0

SEL EMP LANE 2

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

W-0h

Figure 182. Register 035h

7

6

5

4

3

1

0

SEL EMP LANE 3

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

W-0h

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Table 67. Register 032h-035h Field Descriptions

Bit

Field

Type

Reset

Description

7-2

SEL EMP LANE

R/W

0h

These bits select the amount of de-emphasis for the JESD

output transmitter. The de-emphasis value in dB is measured as

the ratio between the peak value after the signal transition to the

settled value of the voltage in one bit period.

0 = 0 dB

1 = –1 dB

3 = –2 dB

7 = –4.1 dB

15 = –6.2 dB

31 = –8.2 dB

63 = –11.5 dB

1-0

0

W

0h

Must write 0

8.5.11.10 Register 036h (address = 036h), JESD Digital Page

Figure 183. Register 036h

7

0

6

5

0

4

0

3

0

2

0

1

0

CMOS SYNCB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 68. Register 036h Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0

6

CMOS SYNCB

R/W

0h

This bit enables single-ended control of SYNCB using the

GPIO4 pin (pin 63). The differential SYNCB input is ignored. Set

the EN CMOS SYNCB bit and keep the CH bit high to make this

bit effective.

0 = Differential SYNCB input

1 = Single-ended SYNCB input using pin 63

5-0

0

W

0h

Must write 0

8.5.11.11 Register 037h (address = 037h), JESD Digital Page

Figure 184. Register 037h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PLL MODE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 69. Register 037h Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0

PLL MODE

R/W

0h

These bits select the PLL multiplication factor; see the JESD

tables in the JESD204B Frame Assembly section for settings.

00 = 20X mode

01 = 16X mode

10 = 40x mode (the 40x MODE bit in register 16h must also be

set)

11 = 80x mode

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8.5.11.12 Register 03Ch (address = 03Ch), JESD Digital Page

Figure 185. Register 03Ch

7

0

6

0

5

0

4

0

3

0

2

0

1

0

EN CMOS SYNCB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 70. Register 03Ch Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

EN CMOS SYNCB

R/W

0h

Set this bit and the CMOS SYNCB bit high to provide a single-

ended SYNC input to the device instead of differential. Also,

keep the CH bit high. Thus:

1. Select the JESD digital page.

2. Write address 7036h with value 40h.

3. Write address 703Ch with value 01h.

96

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8.5.11.13 Register 03Eh (address = 03Eh), JESD Digital Page

Figure 186. Register 03Eh

7

0

6

5

4

0

3

0

2

0

1

0

MASK CLKDIV SYSREF

R/W-0h

MASK NCO SYSREF

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 71. Register 03Eh Field Descriptions

Bit

7

Field

Type

W

Reset

0h

Description

0

Must write 0

6

MASK CLKDIV SYSREF

R/W

0h

Use this bit to mask the SYSREF going to the input clock

divider.

0 = Input clock divider is reset when SYSREF is asserted (that

is, when SYSREF transitions from low to high)

1 = Input clock divider ignores SYSREF assertions

5

MASK NCO SYSREF

R/W

W

0h

Use this bit to mask the SYSREF going to the NCO in the DDC

block and LMFC counter of the JESD interface.

0 = NCO phase and LMFC counter are reset when SYSREF is

asserted (that is, when SYSREF transitions from low to high)

1 = NCO and LMFC counter ignore SYSREF assertions

4-0

0

Must write 0

8.5.12 Decimation Filter Page

Direct Addressing, 16-Bit Address, 5000h for Channel A, 5800h for Channel B

8.5.12.1 Register 000h (address = 000h), Decimation Filter Page

Figure 187. Register 000h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DDC EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 72. Register 000h Field Descriptions

Bit

7-1

0

Field

0

Type

W

Reset

0h

Description

Must write 0

DDC EN

R/W

0h

This bit enables the decimation filter and disables the bypass

mode.

0 = Do not use

1 = Decimation filter enabled

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8.5.12.2 Register 001h (address = 001h), Decimation Filter Page

Figure 188. Register 001h

7

0

6

0

5

0

4

0

3

2

1

0

DECIM FACTOR

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 73. Register 001h Field Descriptions

Bit

7-4

3-0

Field

Type

W

Reset

0h

Description

0

Must write 0

DECIM FACTOR

R/W

0h

These bits configure the decimation filter setting.

0000 = Divide-by-4 complex

0001 = Divide-by-6 complex

0010 = Divide-by-8 complex

0011 = Divide-by-9 complex

0100 = Divide-by-10 complex

0101 = Divide-by-12 complex

0110 = Not used

0111 = Divide-by-16 complex

1000 = Divide-by-18 complex

1001 = Divide-by-20 complex

1010 = Divide-by-24 complex

1011 = Not used

1100 = Divide-by-32 complex

8.5.12.3 Register 002h (address = 2h), Decimation Filter Page

Figure 189. Register 002h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DUAL BAND EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 74. Register 002h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DUAL BAND EN

R/W

0h

This bit enables the dual-band DDC filter for the corresponding

channel.

0 = Single-band DDC; available in both ADC32RF80 and

ADC32RF83

1 = Dual-band DDC; available in ADC32RF80 only

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8.5.12.4 Register 005h (address = 005h), Decimation Filter Page

Figure 190. Register 005h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

REAL OUT EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 75. Register 005h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

REAL OUT EN

R/W

0h

This bit converts the complex output to real output at 2x the

output rate.

0 = Complex output format

1 = Real output format

8.5.12.5 Register 006h (address = 006h), Decimation Filter Page

Figure 191. Register 006h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DDC MUX

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 76. Register 006h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DDC MUX

R/W

0h

This bit connects the DDC to the alternate channel ADC to

enable up to four DDCs with one ADC and completely turn off

the other ADC channel.

0 = Normal operation

1 = DDC block takes input from the alternate ADC

8.5.12.6 Register 007h (address = 007h), Decimation Filter Page

Figure 192. Register 007h

7

6

5

4

3

2

1

0

DDC0 NCO1 LSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 77. Register 007h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO1 LSB

R/W

0h

These bits are the LSB of the NCO frequency word for NCO1 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

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8.5.12.7 Register 008h (address = 008h), Decimation Filter Page

Figure 193. Register 008h

7

6

5

4

3

2

1

0

DDC0 NCO1 MSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 78. Register 008h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO1 MSB

R/W

0h

These bits are the MSB of the NCO frequency word for NCO1 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

8.5.12.8 Register 009h (address = 009h), Decimation Filter Page

Figure 194. Register 009h

7

6

5

4

3

2

1

0

DDC0 NCO2 LSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 79. Register 009h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO2 MSB

R/W

0h

These bits are the LSB of the NCO frequency word for NCO2 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

8.5.12.9 Register 00Ah (address = 00Ah), Decimation Filter Page

Figure 195. Register 00Ah

7

6

5

4

3

2

1

0

DDC0 NCO2 MSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 80. Register 00Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO2 MSB

R/W

0h

These bits are the MSB of the NCO frequency word for NCO2 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

100

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8.5.12.10 Register 00Bh (address = 00Bh), Decimation Filter Page

Figure 196. Register 00Bh

7

6

5

4

3

2

1

0

DDC0 NCO3 LSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 81. Register 00Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO3 LSB

R/W

0h

These bits are the LSB of the NCO frequency word for NCO3 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

8.5.12.11 Register 00Ch (address = 00Ch), Decimation Filter Page

Figure 197. Register 00Ch

7

6

5

4

3

2

1

0

DDC0 NCO3 MSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 82. Register 00Ch Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC0 NCO3 MSB

R/W

0h

These bits are the MSB of the NCO frequency word for NCO3 of

DDC0 (band 1).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

8.5.12.12 Register 00Dh (address = 00Dh), Decimation Filter Page

Figure 198. Register 00Dh

7

6

5

4

3

2

1

0

DDC1 NCO4 LSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 83. Register 00Dh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC1 NCO4 LSB

R/W

0h

These bits are the LSB of the NCO frequency word for NCO4 of

DDC1 (band 2, only when dual-band mode is enabled).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

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8.5.12.13 Register 00Eh (address = 00Eh), Decimation Filter Page

Figure 199. Register 00Eh

7

6

5

4

3

2

1

0

DDC1 NCO4 MSB

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 84. Register 00Eh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DDC1 NCO4 MSB

R/W

0h

These bits are the MSB of the NCO frequency word for NCO4 of

DDC1 (band 2, only when dual-band mode is enabled).

The LSB represents f_S/ (2¹⁶), where f_Sis the ADC sampling

frequency.

8.5.12.14 Register 00Fh (address = 00Fh), Decimation Filter Page

Figure 200. Register 00Fh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

NCO SEL PIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 85. Register 00Fh Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

NCO SEL PIN

R/W

0h

This bit enables NCO selection through the GPIO pins.

0 = NCO selection through SPI (see address 0h10)

1 = NCO selection through GPIO pins

8.5.12.15 Register 010h (address = 010h), Decimation Filter Page

Figure 201. Register 010h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

NCO SEL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 86. Register 010h Field Descriptions

Bit

7-2

1-0

Field

0

Type

W

Reset

0h

Description

Must write 0

NCO SEL

R/W

0h

These bits enable NCO selection through register setting.

00 = NCO1 selected for DDC 1

01 = NCO2 selected for DDC 1

10 = NCO3 selected for DDC 1

102

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8.5.12.16 Register 011h (address = 011h), Decimation Filter Page

Figure 202. Register 011h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LMFC RESET MODE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 87. Register 011h Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0

LMFC RESET MODE

R/W

0h

These bits reset the configuration for all DDCs and NCOs.

00 = All DDCs and NCOs are reset with every LMFC RESET

01 = Reset with first LMFC RESET after DDC start. Afterwards,

reset only when analog clock dividers are resynchronized.

10 = Reset with first LMFC RESET after DDC start. Afterwards,

whenever analog clock dividers are resynchronized, use two

LMFC resets.

11 = Do not use an LMFC reset at all. Reset the DDCs only

when a DDC start is asserted and afterwards continue normal

operation. Deterministic latency is not ensured.

8.5.12.17 Register 014h (address = 014h), Decimation Filter Page

Figure 203. Register 014h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DDC0 6DB GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 88. Register 014h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DDC0 6DB GAIN

R/W

0h

This bit scales the output of DDC0 by 2 (6 dB) to compensate

for real-to-complex conversion and image suppression. This

scaling does not apply to the high-bandwidth filter path (divide-

by-4 and -6); see register 1Fh.

0 = Normal operation

1 = 6-dB digital gain is added

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8.5.12.18 Register 016h (address = 016h), Decimation Filter Page

Figure 204. Register 016h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DDC1 6DB GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 89. Register 016h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

DDC1 6DB GAIN

R/W

0h

This bit scales the output of DDC1 by 2 (6 dB) to compensate

for real-to-complex conversion and image suppression. This

scaling does not apply to the high-bandwidth filter path (divide-

by-4 and -6); see register 1Fh.

0 = Normal operation

1 = 6-dB digital gain is added

8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page

Figure 205. Register 01Eh

7

0

6

5

4

3

0

2

0

1

0

DDC DET LAT

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 90. Register 01Eh Field Descriptions

Bit

7

Field

Type Reset

Description

0

W

0h

Must write 0

6-4

DDC DET LAT

R/W

These bits ensure deterministic latency depending on the decimation setting

used; see Table 91.

3-0

0

W

0h

Must write 0

Table 91. DDC DET LAT Bit Settings

SETTING

10h

COMPLEX DECIMATION SETTING

Divide-by-24, -32 complex

20h

Divide-by-16, -18, -20 complex

Divide-by-by 6, -12 complex

Divide-by-4, -8, -9, -10 complex

40h

50h

104

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8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page

Figure 206. Register 01Fh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

WBF 6DB GAIN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 92. Register 01Fh Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

WBF 6DB GAIN

R/W

0h

This bit scales the output of the wide bandwidth DDC filter by 2

(6 dB) to compensate for real-to-complex conversion and image

suppression. This setting only applies to the high-bandwidth filter

path (divide-by-4 and -6).

0 = Normal operation

1 = 6-dB digital gain is added

8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page

Figure 207. Register 033h

7

6

5

4

3

2

1

0

CUSTOM PATTERN1[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 208. Register 034h

7

6

5

4

3

CUSTOM PATTERN1[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 209. Register 035h

7

6

5

4

3

CUSTOM PATTERN2[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 210. Register 036h

7

6

5

4

3

CUSTOM PATTERN2[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 93. Register 033h-036h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CUSTOM PATTERN

R/W

0h

These bits set the custom test pattern in address 33h, 34h, 35h,

or 36h.

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8.5.12.22 Register 037h (address = 037h), Decimation Filter Page

Figure 211. Register 037h

7

6

5

4

3

2

1

0

TEST PATTERN DDC1 Q-DATA

W-0h W-0h

TEST PATTERN DDC1 I-DATA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 94. Register 037h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TEST PATTERN DDC1 Q-DATA

W

0h

These bits select the test patten for the Q stream of the DDC1.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating

sequence of 10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB

every clock cycle from code 0 to 65535

0110 = Single pattern: output data are a custom pattern 1 (75h

and 76h)

0111 Double pattern: output data alternate between custom

pattern 1 and custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

3-0

TEST PATTERN DDC1 I-DATA

R/W

0h

These bits select the test patten for the I stream of the DDC1.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating

sequence of 10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB

every clock cycle from code 0 to 65535

0110 = Single pattern: output data are a custom pattern 1 (75h

and 76h)

0111 Double pattern: output data alternate between custom

pattern 1 and custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

106

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8.5.12.22.1 Register 038h (address = 038h), Decimation Filter Page

Figure 212. Register 038h

7

6

5

4

3

2

1

0

TEST PATTERN DDC2 Q-DATA

R/W-0h

TEST PATTERN DDC2 I -DATA

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 95. Register 038h Field Descriptions

Bit

Field

Type

Reset

Description

7-4

TEST PATTERN DDC2 Q-DATA

W

0h

These bits select the test patten for the Q stream of the DDC2.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating

sequence of 10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB

every clock cycle from code 0 to 65535

0110 = Single pattern: output data are a custom pattern 1 (75h

and 76h)

0111 Double pattern: output data alternate between custom

pattern 1 and custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

3-0

TEST PATTERN DDC2 I -DATA

R/W

0h

These bits select the test patten for the I stream of the DDC2.

0000 = Normal operation using ADC output data

0001 = Outputs all 0s

0010 = Outputs all 1s

0011 = Outputs toggle pattern: output data are an alternating

sequence of 10101010101010 and 01010101010101

0100 = Output digital ramp: output data increment by one LSB

every clock cycle from code 0 to 65535

0110 = Single pattern: output data are a custom pattern 1 (75h

and 76h)

0111 Double pattern: output data alternate between custom

pattern 1 and custom pattern 2

1000 = Deskew pattern: output data are AAAAh

1001 = SYNC pattern: output data are FFFFh

8.5.12.22.2 Register 039h (address = 039h), Decimation Filter Page

Figure 213. Register 039h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

USE COMMON TEST

PATTERN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 96. Register 039h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

USE COMMON TEST PATTERN

R/W

0h

0 = Each data stream sends test patterns programmed by

bits[3:0] of register 37h.

1 = Test patterns are individually programmed for the I and Q

stream of each DDC using the TEST PATTERN DDCx y-DATA

register bits (where x = 1 or 2 and y = I or Q).

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8.5.12.23 Register 03Ah (address = 03Ah), Decimation Filter Page

Figure 214. Register 03Ah

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TEST PAT RES

R/W-0h

TP RES EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 97. Register 03Ah Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0

TEST PAT RES

R/W

0h

Pulsing this bit resets the test pattern. The test pattern reset

must be enabled first (bit D0).

0 = Normal operation

1 = Reset the test pattern

0

TP RES EN

R/W

0h

This bit enables the test pattern reset.

0 = Reset disabled

1 = Reset enabled

108

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8.5.13 Power Detector Page

8.5.13.1 Register 000h (address = 000h), Power Detector Page

Figure 215. Register 000h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PKDET EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 98. Register 000h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

PKDET EN

R/W

0h

This bit enables the peak power and crossing detector.

0 = Power detector disabled

1 = Power detector enabled

8.5.13.2 Register 001h-002h (address = 001h-002h), Power Detector Page

Figure 216. Register 001h

7

6

5

4

3

2

1

0

BLKPKDET [7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 217. Register 002h

7

6

5

4

3

BLKPKDET [15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 99. Register 001h-002h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BLKPKDET

R/W

0h

This register specifies the block length in terms of number of

samples (S`) used for peak power computation. Each sample S`

is a peak of 8 actual ADC samples. This parameter is a 17-bit

value directly in linear scale. In decimation mode, the block

length must be a multiple of a divide-by-4 or -6 complex: length

= 5 × decimation factor.

The divide-by-8 to -32 complex: length = 10 × decimation factor.

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8.5.13.3 Register 003h (address = 003h), Power Detector Page

Figure 218. Register 003h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

BLKPKDET[16]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 100. Register 003h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

BLKPKDET[16]

R/W

0h

This register specifies the block length in terms of number of

samples (S`) used for peak power computation. Each sample S`

is a peak of 8 actual ADC samples. This parameter is a 17-bit

value directly in linear scale. In decimation mode, the block

length must be a multiple of a divide-by-4 or -6 complex: length

= 5 × decimation factor.

The divide-by-8 to -32 complex: length = 10 × decimation factor.

8.5.13.4 Register 007h-00Ah (address = 007h-00Ah), Power Detector Page

Figure 219. Register 007h

7

6

5

4

3

2

1

0

BLKTHHH

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 220. Register 008h

7

6

5

4

3

BLKTHHL

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 221. Register 009h

7

6

5

4

3

BLKTHLH

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 222. Register 00Ah

7

6

5

4

3

BLKTHLL

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 101. Register 007h-00Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BLKTHHH

BLKTHHL

BLKTHLH

BLKTHLL

R/W

0h

These registers set the four different thresholds for the

hysteresis function threshold values from 0 to 256 (2TH), where

256 is equivalent to the peak amplitude.

Example: BLKTHHH is set to –2 dBFS from peak: 10^{(-2 / 20) × 256}

= 203, then set 5407h, 5C07h = CBh.

110

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8.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page

Figure 223. Register 00Bh

7

6

5

4

3

2

1

0

DWELL[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 224. Register 00Ch

7

6

5

4

3

DWELL[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 102. Register 00Bh-00Ch Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DWELL

R/W

0h

DWELL time counter.

When the computed block peak crosses the upper thresholds

BLKTHHH or BLKTHLH, the peak detector output flags are set.

In order to be reset, the computed block peak must remain

continuously lower than the lower threshold (BLKTHHL or

BLKTHLL) for the period specified by the DWELL value. This

threshold is 16 bits, is specified in terms of f_S/ 8 clock cycles,

and must be set to 0 for the crossing detector. Example: if f_S= 3

GSPS, f_S/ 8 = 375 MHz, and DWELL = 0100h then the DWELL

time = 2⁹/ 375 MHz = 1.36 µs.

8.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page

Figure 225. Register 00Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FILT0LPSEL

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 103. Register 00Dh Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

FILT0LPSEL

R/W

0h

This bit selects either the block detector output or 2-bit output as

the input to the IIR filter.

0 = Use the output of the high comparators (HH and HL) as the

input of the IIR filter

1 = Combine the output of the high (HH and HL) and low (LH

and LL) comparators to generate a 3-level input to the IIR filter

(–1, 0, 1)

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8.5.13.7 Register 00Eh (address = 00Eh), Power Detector Page

Figure 226. Register 00Eh

7

0

6

0

5

0

4

0

3

2

1

0

TIMECONST

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 104. Register 00Eh Field Descriptions

Bit

7-4

3-0

Field

Type

W

Reset

0h

Description

0

Must write 0

TIMECONST

R/W

0h

These bits set the crossing detector time period for N = 0 to 15

as 2^N× f_S/ 8 clock cycles. The maximum time period is 32768 ×

f_S/ 8 clock cycles (approximately 87 µs at 3 GSPS).

8.5.13.8 Register 00Fh, 010h-012h, and 016h-019h (address = 00Fh, 010h-012h, and 016h-019h), Power

Detector Page

Figure 227. Register 00Fh

7

6

5

4

3

2

1

0

FIL0THH[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 228. Register 010h

7

6

5

4

3

FIL0THH[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 229. Register 011h

7

6

5

4

3

FIL0THL[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 230. Register 012h

7

6

5

4

3

FIL0THL[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 231. Register 016h

7

6

5

4

3

FIL1THH[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

112

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Figure 232. Register 017h

7

6

5

4

3

2

1

0

FIL1THH[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 233. Register 018h

7

6

5

4

3

FIL1THL[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 234. Register 019h

7

6

5

4

3

FIL1THL[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 105. Register 00Fh, 010h, 011h, 012h, 016h, 017h, 018h, and 019h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

FIL0THH

FIL0THL

FIL1THH

FIL1THL

R/W

0h

Comparison thresholds for the crossing detector counter. This

threshold is 16 bits in 2.14 signed notation. A value of 1 (4000h)

corresponds to 100% crossings, a value of 0.125 (0800h)

corresponds to 12.5% crossings.

8.5.13.9 Register 013h-01Ah (address = 013h-01Ah), Power Detector Page

Figure 235. Register 013h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

IIR0 2BIT EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Figure 236. Register 01Ah

7

0

6

0

5

0

4

0

3

0

2

0

1

0

IIR1 2BIT EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 106. Register 013h and 01Ah Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

IIR0 2BIT EN

IIR1 2BIT EN

R/W

0h

This bit enables 2-bit output format of the IIR0 and IIR1 output

comparators.

0 = Selects 1-bit output format

1 = Selects 2-bit output format

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8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page

Figure 237. Register 01Dh

7

6

5

4

3

2

1

0

DWELLIIR[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 238. Register 01Eh

7

6

5

4

3

2

0

DWELLIIR[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 107. Register 01Dh-01Eh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DWELLIIR

R/W

0h

DWELL time counter for the IIR output comparators. When the

IIR filter output crosses the upper thresholds FIL0THH or

FIL1THH, the IIR peak detector output flags are set. In order to

be reset, the output of the IIR filter must remain continuously

lower than the lower threshold (FIL0THL or FIL1THL) for the

period specified by the DWELLIIR value. This threshold is 16

bits and is specified in terms of f_S/ 8 clock cycles.

Example: if f_S= 3 GSPS, f_S/ 8 = 375 MHz, and DWELLIIR =

0100h, then the DWELL time = 29 / 375 MHz = 1.36 µs.

8.5.13.11 Register 020h (address = 020h), Power Detector Page

Figure 239. Register 020h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

RMSDET EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 108. Register 020h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

RMSDET EN

R/W

0h

This bit enables the RMS power detector.

0 = Power detector disabled

1 = Power detector enabled

114

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8.5.13.12 Register 021h (address = 021h), Power Detector Page

Figure 240. Register 021h

7

0

6

0

5

0

4

3

2

1

0

PWRDETACCU

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 109. Register 021h Field Descriptions

Bit

7-5

4-0

Field

Type

W

Reset

0h

Description

0

Must write 0

PWRDETACCU

R/W

0h

These bits program the block length to be used for RMS power

computation.

The block length is defined in terms of f_S/ 8 clocks and can be

programmed as 2M, where M = 0 to 16.

8.5.13.13 Register 022h-025h (address = 022h-025h), Power Detector Page

Figure 241. Register 022h

7

6

5

4

3

2

1

0

PWRDETH[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 242. Register 023h

7

6

5

4

3

PWRDETH[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 243. Register 024h

7

6

5

4

3

PWRDETL[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 244. Register 025h

7

6

5

4

3

PWRDETL[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 110. Register 022h-025h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PWRDETH[15:0]

PWRDETL[15:0]

R/W

0h

The computed average power is compared against these high and low

thresholds. One LSB of the thresholds represents 1 / 2¹⁶

.

Example: if PWRDETH is set to –14 dBFS from peak, (10^{(–14 / 20)})²× 2¹⁶= 2609,

then set 5422h, 5423h, 5C22h, 5C23h = 0A31h.

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8.5.13.14 Register 027h (address = 027h), Power Detector Page

Figure 245. Register 027h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

RMS 2BIT EN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 111. Register 027h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0

RMS 2BIT EN

R/W

0h

This bit enables 2-bit output format on the RMS output

comparators.

0 = Selects 1-bit output format

1 = Selects 2-bit output format

8.5.13.15 Register 02Bh (address = 02Bh), Power Detector Page

Figure 246. Register 02Bh

7

0

6

0

5

0

4

3

0

2

0

1

0

RESET AGC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 112. Register 02Bh Field Descriptions

Bit

7-5

4

Field

Type

W

Reset

0h

Description

0

Must write 0

RESET AGC

R/W

0h

After configuration, the AGC module must be reset and then

brought out of reset to start operation.

0 = Clear AGC reset

1 = Set AGC reset

Example: set 542Bh to 10h and then to 00h.

3-0

0

W

0h

Must write 0

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8.5.13.16 Register 032h-035h (address = 032h-035h), Power Detector Page

Figure 247. Register 032h

7

6

5

4

3

2

1

0

OUTSEL GPIO1

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 248. Register 033h

7

6

5

4

3

OUTSEL GPIO2

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 249. Register 034h

7

6

5

4

3

OUTSEL GPIO3

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 250. Register 035h

7

6

5

4

3

OUTSEL GPIO4

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 113. Register 032h-035h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

OUTSEL GPIO1

OUTSEL GPIO2

OUTSEL GPIO3

OUTSEL GPIO4

R/W

0h

These bits set the function or signal for each GPIO pin.

0 = IIR PK DET0[0] of channel A

1 = IIR PK DET0[1] of channel A (2-bit mode)

2 = IIR PK DET1[0] of channel A

3 = IIR PK DET1[1] of channel A (2-bit mode)

4 = BLKPKDETH of channel A

5 = BLKPKDETL of channel A

6 = PWR Det[0] of channel A

7 = PWR Det[1] of channel A (2-bit mode)

8 = FOVR of channel A

9-17 = Repeat outputs 0-8 but for channel B instead

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8.5.13.17 Register 037h (address = 037h), Power Detector Page

Figure 251. Register 037h

7

0

6

0

5

0

4

0

3

2

1

0

IODIR GPIO4

R/W-0h

IODIR GPIO3

R/W-0h

IODIR GPIO2

R/W-0h

IODIR GPIO1

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 114. Register 037h Field Descriptions

Bit

7-4

3-0

Field

Type

W

Reset

0h

Description

0

Must write 0

IODIRGPIO[4:1]

R/W

0h

These bits select the output direction for the GPIO[4:1] pins.

0 = Input (for the NCO control)

1 = Output (for the AGC alarm function)

8.5.13.18 Register 038h (address = 038h), Power Detector Page

Figure 252. Register 038h

7

0

6

0

5

4

3

0

2

0

1

0

INSEL1

R/W-0h

INSEL0

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 115. Register 038h Field Descriptions

Bit

7-6

5-4

Field

0

Type

W

Reset

0h

Description

Must write 0

INSEL1

R/W

0h

These bits select which GPIO pin is used for the INSEL1 bit.

00 = GPIO4

01 = GPIO1

10 = GPIO3

11 = GPIO2

Table 116 lists the NCO selection, based on the bit settings of

the INSEL pins.

3-2

1-0

0

W

0h

Must write 0

INSEL0

R/W

These bits select which GPIO pin is used for the INSEL0 bit.

00 = GPIO4

01 = GPIO1

10 = GPIO3

11 = GPIO2

Table 116 lists the NCO selection, based on the bit settings of

the INSEL pins.

Table 116. INSEL Bit Settings

INSEL1

INSEL2

NCO SELECTED

NCO1

0

1

0

1

0

1

NCO2

NCO3

n/a

118

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Start-Up Sequence

The steps in Table 117 are recommended as the power-up sequence when the ADC32RF8x is in the decimation-

by-4 complex output mode.

Table 117. Initialization Sequence

PAGE, REGISTER

ADDRESS AND DATA

STEP

DESCRIPTION

COMMENT

Supply all supply voltages. There is no required

power-supply sequence for the 1.15 V, 1.2 V,

and 1.9 V supplies, and can be supplied in any

order.

1

—

2

3

Provide the SYSREF signal.

—

Pulse a hardware reset (low-to-high-to-low) on

pins 33 and 34.

The Power-up config file contains analog

trim registers that are required for best

performance of the ADC. Write these

registers every time after power up.

Write the register addresses described in the

PowerUpConfig file.

See the files located in

SBAA226

4

5

Write the register addresses mentioned in the

ILConfigNyqX_ChA file, where X is the Nyquist

zone.

See the files located in

SBAA226

Based on the signal band of interest, provide

the Nyquist zone information to the device.

Write the register addresses mentioned in the

ILConfigNyqX_ChB file, where X is the Nyquist

zone.

See the files located in

SBAA226

This step optimizes device’ performance by

reducing interleaving mismatch errors.

6

Wait for 50 ms for the device to estimate the

interleaving errors.

6.1

—

Depending upon the Nyquist band of operation,

choose and write the registers from the

appropriate file, NLConfigNyqX_ChA, where X

is the Nyquist zone.

See the files located in

SBAA226

Third-order nonlinearity of the device is

optimized by this step for channel A.

7

Depending upon the Nyquist band of operation,

choose and write the registers from the

appropriate file, NLConfigNyqX_ChB, where X

is the Nyquist zone.

See the files located in

SBAA226

Third-order nonlinearity of the device is

optimized by this step for channel B.

7.1

8

Configure the JESD interface and DDC block

by writing the registers mentioned in the DDC

Config file.

Determine the DDC and JESD interface

LMFS options. Program these options in this

step.

See the files located in

SBAA226

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9.1.2 Hardware Reset

Timing information for the hardware reset is shown in Figure 253 and Table 118.

Power Supplies

t₁

RESET

t₂

t₃

SEN

Figure 253. Hardware Reset Timing Diagram

Table 118. Hardware Reset Timing Information

MIN

TYP

MAX

UNIT

ms

µs

t₁

t₂

t₃

Power-on delay from power-up to active high RESET pulse

1

Reset pulse duration: active high RESET pulse duration

Register write delay from RESET disable to SEN active

100

ns

120

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9.1.3 SNR and Clock Jitter

The signal-to-noise ratio (SNR) of the ADC is limited by three different factors: quantization noise, thermal noise,

and jitter, as shown in Equation 5. The quantization noise is typically not noticeable in pipeline converters and is

84 dB for a 14-bit ADC. The thermal noise limits the SNR at low input frequencies and the clock jitter sets the

SNR for higher input frequencies.

2

SNR_{Quantization Noise}

SNR_{Thermal Noise}

SNR_Jitter

20

≈

∆

’

÷

◊

≈

’

÷

◊

≈

’

÷

-

∆

20

∆

SNRADC dBc = -20log 10

+ 10

»

ÿ

⁄

∆

«

∆

«

∆

«

÷

◊

(5)

(6)

The SNR limitation resulting from sample clock jitter can be calculated by Equation 6:

SNR_JitterdBc = -20log 2p ì f ì t_Jitter

»

ÿ

⁄

(

)

IN

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (90 f_S) is set by the noise of the clock

input buffer and the external clock jitter. T_Jittercan be calculated by Equation 7:

2

t_Jitter

=

t

,

+ t

(

)

Jitter Ext _Clock _Input

Aperture_ ADC

(7)

External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass

filters at the clock input. A faster clock slew rate also improves the ADC aperture jitter.

The ADC32RF8x has a thermal noise of approximately 63 dBFS and an internal aperture jitter of 90 f_S. The SNR,

depending on the amount of external jitter for different input frequencies, is shown in Figure 254.

63

62

61

60

59

58

57

35 fs

50 fs

56

100 fs

150 fs

200 fs

55

54

53

52

10

100

1000

5000

Input Frequency (MHz)

D048

Figure 254. ADC SNR vs Input Frequency and External Clock Jitter

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9.1.3.1 External Clock Phase Noise Consideration

External clock jitter can be calculated by integrating the phase noise of the clock source out to approximately two

times of the ADC sampling rate (2 × f_S), as shown in Figure 255. In order to maximize the ADC SNR, an external

band-pass filter is recommended to be used on the clock input. This filter reduces the jitter contribution from the

broadband clock phase noise floor by effectively reducing the integration bandwidth to the pass band of the

band-pass filter. This method is suitable when estimating the overall ADC SNR resulting from clock jitter at a

certain input frequency.

Clock Phase Noise

Integration Bandwidth

Frequency Offset

f_min

2 ì f_S

Figure 255. Integration Bandwidth for Extracting Jitter from Clock Phase Noise

However, when estimating the affect of a nearby blocker (such as a strong in-band interferer to the sensitivity,

the phase noise information can be used directly to estimate the noise budget contribution at a certain offset

frequency, as shown in Figure 256.

Inband Blocker

Clock Phase Noise

Modulated Onto the Blocker

ADC Noise Floor

Wanted Signal

Figure 256. Small Wanted Signal in Presence of Interferer

At the sampling instant, the phase noise profile of the clock source convolves with the input signal (for example,

the small wanted signal and the strong interferer merge together). If the power of the clock phase noise in the

signal band of interest is too large, the wanted signal cannot not be recovered.

The resulting equivalent phase noise at the ADC input is also dependent on the sampling rate of the ADC and

frequency of the input signal. The ADC sampling rate scales the clock phase noise, as shown in Equation 8.

≈

∆

«

’

÷

◊

f_S

ADC_NSDdBc / Hz = PN

dBc / Hz - 20 ì log

(

)

(

)

CLK

f

IN

(8)

Using this information, the noise contribution resulting from the phase noise profile of the ADC sampling clock

can be calculated.

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9.1.4 Power Consumption in Different Modes

The ADC32RF8x consumes approximately 6.6 W of power when both channels are active with a divide-by-4

complex output. When different DDC options are used, the power consumption on the DVDD supply changes by

a small amount but remains unaffected on other supplies. In the applications requiring just one channel to be

active, channel A must be chosen as the active channel and channel B can be powered down. Power

consumption reduces to approximately 4 W in single-channel operation with a divide-by-4 option at a 2949.12-

MSPS device clock rate.

Table 119 shows power consumption in different DDC modes for dual-channel and single-channel operation.

Table 119. Power Consumption in Different DDC Modes (Sampling Clock Frequency, f_S= 3 GSPS)

DECIMATION

OPTION

ACTIVE

CHANNEL

TOTAL POWER

(mW)

ACTIVE DDC

AVDD19 (mA)

AVDD (mA)

DVDD (mA)

Divide-by-4

Divide-by-8

Divide-by-16

Divide-by-24

Divide-by-32

Divide-by-4

Divide-by-8

Divide-by-16

Divide-by-24

Divide-by-32

Channels A, B

Channel A

Single

Dual

1777

1771

1768

961

970

973

972

975

972

970

796

790

786

789

786

785

787

788

786

1785

1960

1730

1971

1705

1938

1667

1835

1574

1096

1168

1047

1172

1045

1155

1016

1104

978

6545

6749

6485

6761

6455

6715

6400

6587

6285

4002

4078

3934

4081

3932

4051

3894

3992

3845

Single

Dual

Single

Dual

Single

Dual

Single

Dual

Channel A

961

Channel A

Single

Dual

961

Channel A

961

Channel A

Single

Dual

961

Channel A

958

Channel A

Single

Dual

958

Channel A

956

Channel A

Single

956

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9.1.5 Using DC Coupling in the ADC32RF8x

The ADC32RF8x can be used in dc-coupling applications. However, the following points must be considered

when designing the system:

1. Ensure that the correct common-mode voltage is used at the ADC analog inputs.

The analog inputs are internally self-biased to V_CMthrough approximately a 33-Ω resistor. The internal

biasing resistors also function as a termination resistor. However, if a different termination is required, the

external resistor R_TERMcan be differentially placed between the analog inputs, as shown in Figure 257. The

amplifier V_OCMpin is recommended to be driven from the CM pin of the ADC to help the amplifier output

common-mode voltage track the required common-mode voltage of the ADC.

ADC32RF80

ADC

Digital

INxP

OUTP

R_S/ 2

R_DC/2⁽²⁾

JESD

204B

Interface

Digital

Ouput

Low-Pass

Filter

Offset

Corrector

Interleaving

Engine

DDC

Block

R_TERM

Driving Amp

(1)

R_CM

V_CM

R_DC/ 2

R_S/ 2

OUTM

V_OCM

INxM

CM

(1) Set the INCR CM IMPEDANCE bit to increase the RCM from 0 Ω to > 5000 Ω.

(2) R_DCis approximately 65 Ω.

Figure 257. The ADC32RF8x in a DC-Coupling Application

2. Ensure that the correct SPI settings are written to the ADC.

As shown in Figure 258, the ADC32RF8x has a digital block that estimates and corrects the offset mismatch

among four interleaving ADC cores for a given channel.

Offset Corrector

Data Out

Data In

+

œ

Freeze

Correction

Disable

Correction

Estimator

Figure 258. Offset Corrector in the ADC32RF8x

The offset corrector block nullifies dc, f_S/ 8, f_S/ 4, 3 f_S/ 8, and f_S/ 2. The resulting spectrum becomes free

from static spurs at these frequencies. The corrector continuously processes the data coming from the

interleaving ADC cores and cannot distinguish if the tone at these frequencies is part of signal or if the tone

originated from a mismatch among the interleaving ADC cores. Thus, in applications where the signal is

present at these frequencies, the offset corrector block can be bypassed.

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9.1.5.1 Bypassing the Offset Corrector Block

When the offset corrector is bypassed, offset mismatch among interleaving ADC cores appears in the ADC

output spectrum. To correct the effects of mismatch, place the ADC in an idle channel state (no signal at the

ADC inputs) and the corrector must be allowed to run for some time to estimate the mismatch, then the corrector

is frozen so that the last estimated value is held. Required register writes are provided in Table 120.

Table 120. Freezing and Bypassing the Offset Corrector Block

STEP

REGISTER WRITE

COMMENT

STEPS FOR FREEZING THE CORRECTOR BLOCK

1

2

—

Signal source is turned off. The device detects an idle channel at its input.

Wait for at least 0.4 ms for the corrector to estimate the internal offset

—

Address 4001h, value 00h

Address 4002h, value 00h

Address 4003h, value 00h

Address 4004h, value 61h

Address 6068h, value C2h

Address 4003h, value 01h

Address 6068h, value C2h

—

Select Offset Corr Page Channel A

3

Freeze the corrector for channel A

Select Offset Corr Page Channel B

Freeze the corrector for channel B

Signal source can now be turned on

4

STEPS FOR BYPASSING THE CORRECTOR BLOCK

Address 4001h, value 00h

Address 4002h, value 00h

Address 4003h, value 00h

Address 4004h, value 61h

Address 6068h, value 46h

Address 4003h, value 01h

Address 6068h, value 46h

—

1

Select Offset Corr Page Channel A

Disable the corrector for channel A

Select Offset Corr Page Channel B

Disable the corrector for channel B

9.1.5.1.1 Effect of Temperature

Figure 259 and Figure 260 show the behavior of nf_S/ 8 tones with respect to temperature when the offset

corrector block is frozen or disabled.

-40

-50

-20

-30

-40

-50

-60

-70

-80

-90

-100

Average of f_S/8

Average of 3f_S/8

Average of f_S/4

Average of f_S/8

Average of 3f_S/8

-60

-70

-80

-90

-100

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

Figure 259. Offset Corrector Block Frozen at Room

Temperature

Figure 260. Offset Corrector Block Disabled

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9.2 Typical Application

The ADC32RF8x is designed for wideband receiver applications demanding high dynamic range over a large

input frequency range. A typical schematic for an ac-coupled receiver is shown in Figure 261.

Decoupling capacitors with low ESL are recommended to be placed as close as possible at the pins indicated in

Figure 261. Additional capacitors can be placed on the remaining power pins.

DVDD

Matching Network

10 kꢀ

0.1 ꢁF

Driver

SPI Master

GND

DVDD

0.1 ꢁF

10 nF

AVDD19

AVDD

AVDD19

AVDD

DVDD

100-ꢀ Differential

18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

10 nF

DB2P

DB2M

DVDD

DB1P

DB1M

GND

GPIO1

GPIO2

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

DVDD

10 nF

GND

GPIO3

10 nF

VCM

0.1 ꢁF

GND

0.1 ꢁF

AVDD19

AVDD

DB0P

DB0M

DVDD

GPIO4

DA0M

DA0P

GND

Matching

Network

AVDD

0.1 ꢁF

GND

DVDD

CLKINP

CLKINM

GND

0.1 ꢁF

ADC32RF80

GND PAD (backside)

GND

10 nF

0.1 ꢁF

AVDD

Low Jitter Clock

Generator

AVDD19

GND

AVDD19

0.1 ꢁF

10 nF

DA1M

DA1P

DVDD

DA2M

DA2P

FPGA

SYSREFP

SYSREFM

SYNCBP

SYNCBM

DVDD

10 nF

GND

10 nF

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

100-ꢀ Differential

AVDD19

AVDD

DVDD

AVDD

AVDD19

0.1 ꢁF

DVDD

0.1 ꢁF

GND

Driver

0.1 ꢁF

Matching Network

Figure 261. Typical Application Implementation Diagram

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Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Transformer-Coupled Circuits

Typical applications involving transformer-coupled circuits are discussed in this section. To ensure good

amplitude and phase balance at the analog inputs, transformers (such as TC1-1-13 and TC1-1-43) can be used

from the dc to 1000-MHz range and from the 1000-MHz to 4-GHz range of input frequencies, respectively. When

designing the driving circuits, the ADC input impedance (or SDD11) must be considered.

By using the simple drive circuit of Figure 262, uniform performance can be obtained over a wide frequency

range. The buffers present at the analog inputs of the device help isolate the external drive source from the

switching currents of the sampling circuit.

5 ꢀ

(Optional)

0.1 ꢁF

T2

CHx_INP

T1

0.1 ꢁF

R_IN

C_IN

5 ꢀ

(Optional)

0.1 ꢁF

CHx_INM

1:1

TI Device

Figure 262. Input Drive Circuit

9.2.2 Detailed Design Procedure

For optimum performance, the analog inputs must be driven differentially. This architecture improves common-

mode noise immunity and even-order harmonic rejection. A small resistor (5 Ω to 10 Ω) in series with each input

pin is recommended to damp out ringing caused by package parasitics, as shown in Figure 262.

9.2.3 Application Curves

Figure 263 and Figure 264 show the typical performance at 100 MHz and 1780 MHz, respectively.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

300

600

900

1200

1500

0

300

600

900

1200

1500

Input Frequency (MHz)

D001

D003

SNR = 61.8 dBFS, SINAD = 61.2 dBFS,

HD2 = 71 dBc, HD3 = 75 dBc, SFDR = 71 dBc,

SNR = 57.9 dBFS, SINAD = 57.1 dBFS,

HD2 = 63 dBc, HD3 = 66 dBc, SFDR = 63 dBc,

THD = 68 dBc, IL spur = 77 dBc, worst spur = 73 dBc

THD = 60 dBc, IL spur = 79 dBc, worst spur = 77 dBc

Figure 263. FFT for 100-MHz Input Frequency

Figure 264. FFT for 1780-MHz Input Frequency

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10 Power Supply Recommendations

The DVDD power supply (1.15 V) must be stable before ramping up the AVDD19 supply (1.9 V), as shown in

Figure 265. The AVDD supply (1.15 V) can come up in any order during the power sequence. The power

supplies can ramp up at any rate and there is no hard requirement for the time delay between DVDD (1.15 V)

ramping up to AVDD (1.9 V) ramping up (which can be in orders of microseconds but is recommended to be a

few milliseconds).

AVDD

(1.15 V)

DVDD

(1.15 V)

AVDD19

(1.9 V)

Figure 265. Power Sequencing for the ADC32RF8x Family of devices

11 Layout

11.1 Layout Guidelines

The device evaluation module (EVM) layout can be used as a reference layout to obtain the best performance. A

layout diagram of the EVM top layer is provided in Figure 266. The ADC32RF45/RF80 EVM Quick Startup Guide

provides a complete layout of the EVM. Some important points to remember during board layout are:

•

Analog inputs are located on opposite sides of the device pinout to ensure minimum crosstalk on the package

level. To minimize crosstalk onboard, the analog inputs must exit the pinout in opposite directions, as shown

in the reference layout of Figure 266 as much as possible.

In the device pinout, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling. This configuration is also maintained on the reference layout of Figure 266 as much as

possible.

Keep digital outputs away from the analog inputs. When these digital outputs exit the pinout, the digital output

traces must not be kept parallel to the analog input traces because this configuration can result in coupling

from the digital outputs to the analog inputs and degrade performance. All digital output traces to the receiver

[such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs)] must be

matched in length to avoid skew among outputs.

•

At each power-supply pin (AVDD, DVDD, or AVDD19), keep a 0.1-µF decoupling capacitor close to the

device. A separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors can be kept close to the supply source.

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11.2 Layout Example

Figure 266. ADC32RF8xEVM Layout

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

ADC32RF45/RF80 EVM Quick Startup Guide (SLAU620)

Configuration Files for the ADC32RF45 (SBAA226)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 121. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

ADC32RF80

ADC32RF83

Click here

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

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26-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC32RF80IRMPR

ADC32RF80IRMPT

ADC32RF83IRMPR

ADC32RF83IRMPT

VQFN

RMP

72

1500

250

330.0

180.0

330.0

180.0

24.4

10.25 10.25 2.25

16.0

24.0

Q2

1500

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC32RF80IRMPR

ADC32RF80IRMPT

ADC32RF83IRMPR

ADC32RF83IRMPT

VQFN

RMP

72

1500

250

350.0

213.0

350.0

213.0

350.0

191.0

350.0

191.0

43.0

55.0

43.0

55.0

1500

250

Pack Materials-Page 2

PACKAGE OUTLINE

RMP0072A

VQFN - 0.9 mm max height

SCALE 1.700

VQFN

10.1

9.9

A

B

PIN 1 ID

10.1

9.9

0.9 MAX

0.05

0.00

C

SEATING PLANE

0.08 C

(0.2)

4X (45 X0.42)

19

36

18

37

SYMM

4X

8.5

8.5 0.1

PIN 1 ID

(R0.2)

1

54

0.30

0.18

72X

72

55

68X 0.5

SYMM

0.5

0.3

0.1

C B

A

72X

0.05

C

4221047/B 02/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RMP0072A

VQFN - 0.9 mm max height

VQFN

(

8.5)

SYMM

72X (0.6)

SEE DETAILS

55

72

1

54

72X (0.24)

(0.25) TYP

SYMM

(9.8)

(1.315) TYP

68X (0.5)

(

0.2) TYP

VIA

37

18

19

36

(1.315) TYP

(9.8)

LAND PATTERN EXAMPLE

SCALE:8X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221047/B 02/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report

in literature No. SLUA271 (www.ti.com/lit/slua271).

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EXAMPLE STENCIL DESIGN

RMP0072A

VQFN - 0.9 mm max height

VQFN

(9.8)

72X (0.6)

(1.315) TYP

72

55

1

54

72X (0.24)

(1.315)

TYP

(0.25) TYP

SYMM

(9.8)

(1.315)

TYP

68X (0.5)

METAL

TYP

37

18

(

0.2) TYP

VIA

19

36

36X ( 1.115)

(1.315) TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

62% PRINTED SOLDER COVERAGE BY AREA

SCALE:8X

4221047/B 02/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC32RF80IRRHT
厂家：	TEXAS INSTRUMENTS
描述：	ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
文件：	总138页 (文件大小：8994K)
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ADC32RF80IRRHT [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E