ADC3423IRTQR [TI]
四通道、12 位、80MSPS 模数转换器 (ADC) | RTQ | 56 | -40 to 85;
| 型号： | ADC3423IRTQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四通道、12 位、80MSPS 模数转换器 (ADC) | RTQ | 56 | -40 to 85 转换器 模数转换器 |
| 文件： | 总80页 (文件大小：4673K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
ADC342x 四通道、12 位、25MSPS 至 125MSPS 模数转换器
1 特性
3 说明
1
•
•
•
•
•
四通道
ADC342x 属于高线性度、超低功耗、四通道、12 位、
25MSPS 至 125MSPS 模数转换器 (ADC) 系列。 此
类器件专门设计用于支持具有宽动态范围需求且要求苛
刻的高输入频率信号。 当 SYSREF 输入实现整个系统
同步时，时钟输入分频器将给予系统时钟架构设计更高
的灵活性。 ADC342x 系列支持串行低压差分信号
(LVDS)，从而减少接口线路的数量，实现高系统集成
度。 串行 LVDS 接口为双线制，通过两个 LVDS 对串
行输出每个 ADC 数据。 内部锁相环 (PLL) 会将传入
的 ADC 采样时钟加倍，以获得串行输出各通道的 12
位输出数据时所使用的位时钟。 除了串行数据流之
外，数据帧和位时钟也作为 LVDS 输出进行传送。
12 位分辨率
单电源：1.8V
串行低压差分信号 (LVDS) 接口
支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲
器
•
•
fIN = 70MHz 时，信噪比 (SNR) = 70.2dBFS，无杂
散动态范围 (SFDR) = 87dBc
超低功耗：
–
125MSPS 时为每通道 98mW
•
•
•
•
•
通道隔离：105dB
内部抖动和斩波
器件信息(1)
支持多芯片同步
部件号
ADC342x
封装
VQFN (56)
封装尺寸（标称值）
与 14 位版本器件引脚到引脚兼容
8.00mm x 8.00mm
封装：超薄四方扁平无引线 (VQFN)-56 (8mm x
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
8mm)
空白
空白
空白
空白
空白
空白
2 应用
•
•
•
•
•
•
•
•
•
•
多载波、多模式蜂窝基站
雷达和智能天线阵列
炮弹制导
电机控制反馈
网络和矢量分析器
通信测试设备
无损检测
微波接收器
软件定义无线电 (SDR)
正交和分集无线电接收器
10MHz 中频 (IF) 时的频谱
（SFDR = 97dBc，SNR = 70.4dBFS，SINAD = 70.4dBFS，
THD = 98dBc，HD2 = 95dBc，HD3 = 97dBc）
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D201
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS673
ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
目录
7.19 Typical Characteristics: Common ......................... 38
7.20 Typical Characteristics: Contour ........................... 39
Parameter Measurement Information ................ 39
8.1 Timing Diagrams..................................................... 39
Detailed Description ............................................ 41
9.1 Overview ................................................................. 41
9.2 Functional Block Diagram ....................................... 41
9.3 Feature Description................................................. 42
9.4 Device Functional Modes........................................ 46
9.5 Programming........................................................... 47
9.6 Register Maps......................................................... 51
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics: General............................ 6
7.6 Electrical Characteristics: ADC3421, ADC3422 ....... 7
7.7 Electrical Characteristics: ADC3423, ADC3424 ....... 7
7.8 AC Performance: ADC3421...................................... 8
7.9 AC Performance: ADC3422.................................... 10
7.10 AC Performance: ADC3423.................................. 12
7.11 AC Performance: ADC3424.................................. 14
7.12 Digital Characteristics ........................................... 16
7.13 Timing Requirements: General ............................. 16
7.14 Timing Requirements: LVDS Output..................... 17
7.15 Typical Characteristics: ADC3421 ........................ 18
7.16 Typical Characteristics: ADC3422 ........................ 23
7.17 Typical Characteristics: ADC3423 ........................ 28
7.18 Typical Characteristics: ADC3424 ........................ 33
8
9
10 Applications and Implementation...................... 66
10.1 Application Information.......................................... 66
10.2 Typical Applications .............................................. 67
11 Power Supply Recommendations ..................... 69
12 Layout................................................................... 70
12.1 Layout Guidelines ................................................. 70
12.2 Layout Example .................................................... 70
13 器件和文档支持 ..................................................... 71
13.1 相关链接................................................................ 71
13.2 社区资源................................................................ 71
13.3 商标....................................................................... 71
13.4 静电放电警告......................................................... 71
13.5 Glossary................................................................ 71
14 机械、封装和可订购信息....................................... 71
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (July 2014) to Revision A
Page
•
已发布为量产数据................................................................................................................................................................... 1
2
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
5 Device Comparison Table
RESOLUTION
INTERFACE
(Bits)
25 MSPS
ADC3421
ADC3441
—
50 MSPS
ADC3422
ADC3442
ADC34J22
ADC34J42
80 MSPS
ADC3423
ADC3443
ADC34J23
ADC34J43
125 MSPS
ADC3424
ADC3444
ADC34J24
ADC34J44
160 MSPS
—
12
Serial LVDS
14
—
12
ADC34J25
ADC34J45
JESD204B
14
—
6 Pin Configuration and Functions
RTQ Package
VQFN-56
Top View
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
2
42
DA1P
DA1M
DA0P
DA0M
DVDD
AVDD
AVDD
INAM
INAP
DD0M
41
40
39
38
37
36
35
34
33
32
31
30
29
DD0P
DD1M
DD1P
DVDD
PDN
3
4
5
6
7
GND Pad
AVDD
INDM
INDP
AVDD
AVDD
INCP
INCM
AVDD
8
(Back Side)
9
10
11
12
13
14
AVDD
AVDD
INBP
INBM
AVDD
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Copyright © 2014–2015, Texas Instruments Incorporated
3
ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
AVDD
NO.
6, 7, 10, 11, 14,
15, 20, 23, 28, 29,
32, 33, 36
I
Analog 1.8-V power supply
CLKM
CLKP
DA0M
DA0P
DA1M
DA1P
DB0M
DB0P
DB1M
DB1P
DC0M
DC0P
DC1M
DC1P
DD0M
DD0P
DD1M
DD1P
DCLKM
DCLKP
DVDD
FCLKM
FCLKP
GND
21
I
Negative differential clock input for the ADC
Positive differential clock input for the ADC
Negative serial LVDS output for wire-0 of channel A
Positive serial LVDS output for wire-0 of channel A
Negative serial LVDS output for wire-1 of channel A
Positive serial LVDS output for wire-1 of channel A
Negative serial LVDS output for wire-0 of channel B
Positive serial LVDS output for wire-0 of channel B
Negative serial LVDS output for wire-1 of channel B
Positive serial LVDS output for wire-1 of channel B
Negative serial LVDS output for wire-0 of channel C
Positive serial LVDS output for wire-0 of channel C
Negative serial LVDS output for wire-1 of channel C
Positive serial LVDS output for wire-1 of channel C
Negative serial LVDS output for wire-0 of channel D
Positive serial LVDS output for wire-0 of channel D
Negative serial LVDS output for wire-1 of channel D
Positive serial LVDS output for wire-1 of channel D
Negative bit clock output
22
I
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
3
2
1
56
55
54
53
46
45
44
43
42
41
40
39
51
50
Positive bit clock output
5, 38, 47, 52
Digital 1.8-V power supply
49
O
O
I
Negative frame clock output
48
Positive frame clock output
PowerPAD™
Ground, 0 V
INAM
INAP
8
I
Negative differential analog input for channel A
Positive differential analog input for channel A
Negative differential analog input for channel B
Positive differential analog input for channel B
Negative differential analog input for channel C
Positive differential analog input for channel C
Negative differential analog input for channel D
Positive differential analog input for channel D
9
I
INBM
INBP
13
12
30
31
35
34
I
I
INCM
INCP
I
I
INDM
INDP
I
I
Power-down control. This pin can be configured via the SPI. This pin has an internal
150-kΩ pulldown resistor.
PDN
37
I
RESET
SCLK
24
16
17
19
I
I
Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.
Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.
Serial interface data input. This pin has an internal 150-kΩ pulldown resistor.
Serial interface data output
SDATA
SDOUT
I
O
Serial interface enable; active low.
This pin has an internal 150-kΩ pullup resistor to AVDD.
SEN
18
I
SYSREFM
SYSREFP
VCM
26
25
27
I
I
Negative external SYSREF input
Positive external SYSREF input
O
Common-mode voltage for analog inputs
4
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–40
MAX
UNIT
V
Analog supply voltage range, AVDD
2.1
Digital supply voltage range, DVDD
2.1
V
INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM
min (1.9, AVDD + 0.3)
CLKP, CLKM
AVDD + 0.3
Voltage applied to
input pins
V
SYSREFP, SYSREFM
SCLK, SEN, SDATA, RESET, PDN
Operating free-air, TA
Operating junction, TJ
Storage, Tstg
AVDD + 0.3
3.9
85
Temperature
125
150
ºC
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage range
Digital supply voltage range
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DVDD
ANALOG INPUT
For input frequencies < 450 MHz
For input frequencies < 600 MHz
2
1
VID
Differential input voltage
VPP
V
VIC
Input common-mode voltage
VCM ± 0.025
CLOCK INPUT
Input clock frequency
Sampling clock frequency
Sine wave, ac-coupled
LPECL, ac-coupled
15(2)
125(3)
MSPS
VPP
0.2
1.5
1.6
Input clock amplitude (differential)
LVDS, ac-coupled
0.7
Input clock duty cycle
35%
50%
0.95
65%
Input clock common-mode voltage
V
DIGITAL OUTPUTS
Maximum external load capacitance
from each output pin to GND
CLOAD
RLOAD
3.3
pF
Single-ended load resistance
100
Ω
(1) After power-up, use only the RESET pin to reset the device for the first time; see the Register Initialization section for details.
(2) See Table 3 for details.
(3) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
7.4 Thermal Information
ADC342x
RTQ (VQFN)
56 PINS
25.3
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
9.5
3.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
3.3
RθJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics: General
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Differential input full-scale
Input resistance
2.0
6.6
3.7
0.95
10
VPP
kΩ
ri
Differential at dc
Differential at dc
ci
Input capacitance
pF
VOC(VCM)
VCM common-mode voltage output
VCM output current capability
Input common-mode current
V
mA
Per analog input pin
1.5
µA/MSPS
50-Ω differential source driving 50-Ω termination
across INP and INM
Analog input bandwidth (3 dB)
540
MHz
DC ACCURACY
EO
Offset error
–25
–2
25
2
mV
αEO
Temperature coefficient of offset error
± 0.024
mV/°C
Gain error as a result of internal
reference inaccuracy alone
EG(REF)
%FS
EG(CHAN)
Gain error of channel alone
–2
%FS
α(EGCHAN)
Temperature coefficient of EG(CHAN)
±0.008
Δ%FS/Ch
CHANNEL-TO-CHANNEL ISOLATION
Near channel
fIN = 10 MHz
105
105
95
Far channel
Near channel
fIN = 100 MHz
Far channel
105
94
Near channel
fIN = 200 MHz
Crosstalk(1)
dB
Far channel
105
92
Near channel
fIN = 230 MHz
Far channel
105
85
Near channel
fIN = 300 MHz
Far channel
105
(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.
6
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
7.6 Electrical Characteristics: ADC3421, ADC3422
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3421
TYP
ADC3422
TYP
PARAMETER
ADC clock frequency
MIN
MAX
MIN
MAX
UNIT
MSPS
Bits
25
50
Resolution
12
12
1.8-V analog supply current
1.8-V digital supply current
Total power dissipation
Global power-down dissipation
Standby power-down dissipation
54
45
177
5
71
71
71
56
228
5
90
90
mA
mA
240
17
305
17
mW
mW
mW
34
75
35
75
7.7 Electrical Characteristics: ADC3423, ADC3424
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3423
TYP
ADC3424
TYP
PARAMETER
ADC clock frequency
MIN
MAX
MIN
MAX
UNIT
MSPS
Bits
80
125
Resolution
12
12
1.8-V analog supply current
1.8-V digital supply current
Total power dissipation
Global power-down dissipation
Standby power-down dissipation
92
68
288
5
107
100
365
17
119
98
391
5
145
145
475
17
mA
mA
mW
mW
mW
40
88
43
103
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
7.8 AC Performance: ADC3421
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3421 (fS = 25 MSPS)
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
70.9
70.7
70.4
70.3
69.7
68.9
70.2
70.1
69.8
69.6
69.2
68.3
–141.5
MAX
TYP
71.1
70.9
70.6
70.5
69.9
69.1
70.5
70.3
70.0
69.8
69.3
68.5
–141.7
–141.5
–141.2
–141.1
–140.5
–139.7
71.1
70.9
70
MAX
UNIT
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68.9
Signal-to-noise ratio
(from 1-MHz offset)
dBFS
SNR
Signal-to-noise ratio
(full Nyquist band)
dBFS
dBFS/Hz
dBFS
Bits
–141.3 –139.5
–141.0
–140.9
–140.3
–139.5
71
Noise spectral density
(averaged across Nyquist zone)
NSD(1)
67.9
70.8
69.5
70.5
69.6
68.7
11.5
11.4
11.4
11.4
11.3
11.1
93
Signal-to-noise and distortion
ratio
SINAD(1)
ENOB(1)
SFDR
70.7
69.8
68.7
11.5
11.4
11.4
11.4
11.3
11.1
90
11
Effective number of bits
84
91
85
93
88
Spurious-free dynamic range
dBc
85
82
86
85
82
82
(1) Reported from a 1-MHz offset.
8
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
AC Performance: ADC3421 (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3421 (fS = 25 MSPS)
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
93
100
93
94
86
86
96
91
93
85
89
82
99
98
96
95
92
97
90
90
89
84
84
80
MAX
TYP
92
94
92
93
85
82
90
85
88
82
89
82
92
91
92
93
90
91
86
83
85
80
83
79
MAX
UNIT
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
84
84
87
81
Second-order harmonic
distortion
HD2
dBc
HD3
Non
Third-order harmonic distortion
dBc
dBc
Spurious-free dynamic range
HD2, HD3 (excluding HD2, HD3)
THD
Total harmonic distortion
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
–98
–91
–98
–91
Two-tone, third-order
intermodulation distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
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7.9 AC Performance: ADC3422
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3422 (fS = 50 MSPS)
DITHER ON
MIN
DITHER OFF
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
70.8
70.6
70.5
70.4
69.8
68.8
70.2
69.8
69.7
69.8
69.3
68.2
–144.6
MAX
MIN
TYP
71
MAX
UNIT
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68.9
70.8
70.7
70.6
70.1
69
Signal-to-noise ratio
(from 1-MHz offset)
SNR
dBFS
70.4
70.0
69.9
70.1
69.5
68.4
–144.8
–144.6
–144.5
–144.4
–143.9
–142.8
71
Signal-to-noise ratio
(full Nyquist band)
–144.4 –142.7
–144.3
–144.2
–143.6
–142.6
70.8
70.7
70.3
70.6
69.7
68.6
11.5
11.4
11.4
11.4
11.3
11.1
90
Noise spectral density
(averaged across Nyquist zone)
NSD(1)
dBFS/Hz
dBFS
Bits
67.9
70.9
70.6
70.8
69.9
68.8
11.5
11.5
11.5
11.5
11.3
11.1
92
Signal-to-noise and distortion
ratio
SINAD(1)
ENOB(1)
SFDR
11
Effective number of bits
82
95
90
93
92
Spurious-free dynamic range
dBc
87
87
87
86
83
83
(1) Reported from a 1-MHz offset.
10
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
AC Performance: ADC3422 (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3422 (fS = 50 MSPS)
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
95
98
93
94
87
85
90
94
94
87
88
83
99
99
98
95
96
96
88
89
90
86
84
81
MAX
TYP
92
95
92
92
86
83
92
92
92
87
89
88
93
93
92
94
89
90
87
89
87
85
83
81
MAX
UNIT
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
83
82
87
79
Second-order harmonic
distortion
HD2
dBc
HD3
Non
Third-order harmonic distortion
dBc
dBc
Spurious-free dynamic range
HD2, HD3 (excluding HD2, HD3)
THD
Total harmonic distortion
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
–95
–88
–95
–88
Two-tone, third-order
intermodulation distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
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7.10 AC Performance: ADC3423
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3423 (fS = 80 MSPS)
DITHER ON
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
TYP
70.7
70.5
70.3
70.1
69.6
70.3
70.1
69.9
69.7
69.3
–146.6
MAX
TYP
70.9
70.7
70.5
70.3
69.9
70.5
70.4
70.2
69.9
69.6
–146.8
–146.6
–146.4
–146.2
–145.8
70.8
70.4
70.7
70.2
69.7
11.5
11.4
11.5
11.4
11.3
90
MAX
UNIT
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68.7
Signal-to-noise ratio
(from 1-MHz offset)
SNR
dBFS
Signal-to-noise ratio
(full Nyquist band)
–146.4 –144.6
–146.2
–146.0
–145.5
70.7
70.3
70.4
70
Noise spectral density
(averaged across Nyquist zone)
NSD(1)
dBFS/Hz
dBFS
Bits
67.7
Signal-to-noise and distortion
ratio
SINAD(1)
ENOB(1)
SFDR
69.5
11.5
11.4
11.4
11.3
11.3
90
11
Effective number of bits
81
91
90
Spurious-free dynamic range
93
93
dBc
88
86
87
85
(1) Reported from a 1-MHz offset.
12
Copyright © 2014–2015, Texas Instruments Incorporated
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AC Performance: ADC3423 (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless
otherwise noted.
ADC3423 (fS = 80 MSPS)
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
94
96
97
88
87
90
91
93
96
87
99
98
94
95
94
88
89
91
87
84
MAX
TYP
91
92
93
86
85
90
90
99
93
87
94
93
94
92
91
86
86
90
84
82
MAX
UNIT
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
81
81
86
78
Second-order harmonic
distortion
HD2
dBc
HD3
Non
Third-order harmonic distortion
Spurious-free dynamic range
dBc
dBc
HD2, HD3 (excluding HD2, HD3)
THD
Total harmonic distortion
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
–97
–92
–97
–92
Two-tone, third-order
intermodulation distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
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7.11 AC Performance: ADC3424
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,
unless otherwise noted.
ADC3424 (fS = 125 MSPS)
DITHER ON
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
TYP
70.5
70.3
70.1
69.8
69.2
70.3
70.1
70.0
69.6
69.0
–148.4
MAX
TYP
70.7
70.6
70.4
70.3
69.9
70.5
70.4
70.2
70.1
69.7
–148.6
–148.5
–148.3
–148.2
–147.8
70.6
70.5
70.5
70.1
69.1
11.4
11.4
11.4
11.4
11.3
89
MAX
UNIT
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
68
Signal-to-noise ratio
(from 1-MHz offset)
SNR
dBFS
Signal-to-noise ratio
(full Nyquist band)
–148.2 –145.9
–148.0
–147.7
–147.1
70.5
Noise spectral density
(averaged across Nyquist zone)
NSD(1)
dBFS/Hz
dBFS
Bits
67
10.8
80
70.3
Signal-to-noise and distortion
ratio
SINAD(1)
ENOB(1)
SFDR
70.1
69.7
68.6
11.4
11.4
Effective number of bits
11.4
11.3
11.2
93
94
90
Spurious-free dynamic range
90
87
dBc
86
85
81
80
(1) Reported from a 1-MHz offset.
14
Copyright © 2014–2015, Texas Instruments Incorporated
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
AC Performance: ADC3424 (continued)
Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX
= 85°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input,
unless otherwise noted.
ADC3424 (fS = 125 MSPS)
DITHER ON
MIN
DITHER OFF
MIN
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
TYP
93
94
90
86
81
96
95
97
93
87
100
99
94
95
94
90
90
88
85
80
MAX
TYP
92
91
91
85
80
88
89
90
87
86
93
94
93
92
90
85
85
86
82
78
MAX
UNIT
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
80
81
86
77
Second-order harmonic
distortion
HD2
dBc
HD3
Non
Third-order harmonic distortion
Spurious-free dynamic range
dBc
dBc
HD2, HD3 (excluding HD2, HD3)
THD
Total harmonic distortion
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
95
89
95
89
Two-tone, third-order
intermodulation distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
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7.12 Digital Characteristics
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
VIH
VIL
High-level input voltage
Low-level input voltage
1.3
V
V
All digital inputs support 1.8-V and
3.3-V CMOS logic levels
0.4
RESET, SDATA, SCLK,
PDN
SEN(1)
VHIGH = 1.8 V
VHIGH = 1.8 V
VLOW = 0 V
10
0
µA
µA
µA
µA
High-level input
current
IIH
RESET, SDATA, SCLK,
PDN
0
Low-level input
current
IIL
SEN
VLOW = 0 V
10
DIGITAL INPUTS (SYSREFP, SYSREFM)
VIH
VIL
High-level input voltage
1.3
0.5
0.9
V
V
V
Low-level input voltage
Common-mode voltage for SYSREF
DIGITAL OUTPUTS (CMOS Interface, SDOUT)
VOH
VOL
High-level output voltage
Low-level output voltage
DVDD – 0.1
DVDD
0
V
V
0.1
DIGITAL OUTPUTS (LVDS Interface)
VODH
VODL
VOCM
High-level output differential voltage
With an external 100-Ω termination
With an external 100-Ω termination
280
350
–350
1.05
460
mV
mV
V
Low-level output differential voltage
Output common-mode voltage
–460
–280
(1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) can be driven by 1.8 V or 3.3 V CMOS buffers.
7.13 Timing Requirements: General
Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum
and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C.
MIN
TYP
1.44
±70
±150
130
35
MAX
UNIT
ns
tA
Aperture delay
1.24
1.64
Aperture delay matching between two channels of the same device
Aperture delay variation between two devices at same temperature and supply voltage
Aperture jitter
ps
ps
tJ
fS rms
µs
Time to valid data after exiting standby power-down mode
200
450
Wake-up time:
ADC latency(1)
Time to valid data after exiting global power-down mode
(in this mode, both channels power down)
85
9
µs
Clock
cycles
2-wire mode (default)
1-wire mode
:
Clock
cycles
8
tSU_SYSREF
Setup time for SYSREF referenced to input clock rising edge
Hold time for SYSREF referenced to input clock rising edge
1000
100
ps
ps
SYSREF reference time:
tH_SYSREF
(1) Overall latency = ADC latency + tPDI
.
16
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
7.14 Timing Requirements: LVDS Output(1)(2)
Typical values are at TA = 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, 6x Serialization (2-Wire Mode),
CLOAD = 3.3 pF(3), and RLOAD = 100 Ω(4), unless otherwise noted.. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = 85°C.
MIN
TYP
MAX
UNIT
Data setup time: data valid to zero-crossing of differential output clock
(CLKOUTP – CLKOUTM)(5)
tSU
tHO
0.43
0.5
ns
Data hold time: zero-crossing of differential output clock
(CLKOUTP – CLKOUTM) to data becoming invalid(5)
0.48
2.7
0.58
4.5
ns
Clock propagation delay: input clock falling edge cross-over to 1-wire mode
frame clock rising edge cross-over
6.5
5.9
ns
ns
ns
tPDI
2-wire mode
0.44 × tS + tDELAY
(15 MSPS < sampling frequency < 125 MSPS)
tDELAY
Delay time
3
4.5
LVDS bit clock duty cycle: duty cycle of differential clock
(CLKOUTP – CLKOUTM)
49%
tFALL
tRISE
,
Data fall time, data rise time: rise time measured from –100 mV to 100 mV,
15 MSPS ≤ Sampling frequency ≤ 125 MSPS
0.11
0.11
ns
ns
tCLKRISE
tCLKFALL
,
Output clock rise time, output clock fall time: rise time measured from
–100 mV to 100 mV, 15 MSPS ≤ Sampling frequency ≤ 125 MSPS
(1) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time
specifications take into account the effect of jitter on the output data and clock.
(2) Timing parameters are ensured by design and characterization and are not tested in production.
(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(4) RLOAD is the differential load resistance between the LVDS output pair.
(5) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.
Table 1. LVDS Timing at Lower Sampling Frequencies: 6X Serialization (2-Wire Mode)
SETUP TIME
(tSU, ns)
HOLD TIME
(tHO, ns)
SAMPLING FREQUENCY
(MSPS)
MIN
2.61
1.69
1.11
0.81
0.6
TYP
MAX
MIN
2.75
1.8
TYP
MAX
25
40
3.06
1.9
3.12
1.98
1.31
0.97
0.77
60
1.23
0.89
0.68
1.18
0.88
0.68
80
100
Table 2. LVDS Timings at Lower Sampling Frequencies: 12X Serialization (1-Wire Mode)
SETUP TIME
(tSU, ns)
HOLD TIME
(tHO, ns)
SAMPLING FREQUENCY
(MSPS)
MIN
1.3
TYP
MAX
MIN
1.32
0.79
0.61
0.45
0.4
TYP
MAX
25
40
50
60
70
80
1.48
0.88
0.68
0.55
0.44
0.35
1.57
0.97
0.77
0.62
0.51
0.43
0.76
0.57
0.42
0.35
0.26
0.35
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7.15 Typical Characteristics: ADC3421
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D801
D802
SFDR = 95 dBc, SNR = 71 dBFS, SINAD = 71 dBFS,
THD = 94 dBc, HD2 = 106 dBc, HD3 = 95 dBc
SFDR = 90 dBc, SNR = 71.2 dBFS, SINAD = 71.1 dBFS,
THD = 89 dBc, HD2 = 90 dBc, HD3 = 106 dBc
Figure 1. FFT for 10-MHz Input Signal (Dither On)
Figure 2. FFT for 10-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D803
D804
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.3 dBFS,
THD = 91 dBc, HD2 = 105 dBc, HD3 = 92 dBc
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 88 dBc, HD2 = 91 dBc, HD3 = 101 dBc
Figure 3. FFT for 70-MHz Input Signal (Dither On)
Figure 4. FFT for 70-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D805
D806
SFDR = 87 dBc, SNR = 69.8 dBFS, SINAD = 69.7 dBFS,
THD = 85 dBc, HD2 = 90 dBc, HD3 = 87 dBc
SFDR = 85 dBc, SNR = 70 dBFS, SINAD = 69.8 dBFS,
THD = 86 dBc, HD2 = 85 dBc, HD3 = 92 dBc
Figure 5. FFT for 170-MHz Input Signal (Dither On)
Figure 6. FFT for 170-MHz Input Signal (Dither Off)
18
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ADC3421, ADC3422, ADC3423, ADC3424
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3421 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D807
D808
SFDR = 77 dBc, SNR = 68.2 dBFS, SINAD = 67.7 dBFS,
THD = 75 dBc, HD2 = 77 dBc, HD3 = 83 dBc
SFDR = 75 dBc, SNR = 68.4 dBFS, SINAD = 67.5 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 80 dBc
Figure 7. FFT for 270-MHz Input Signal (Dither On)
Figure 8. FFT for 270-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D809
D810
SFDR = 67 dBc, SNR = 66.4 dBFS, SINAD = 66.4 dBFS,
THD = 93 dBc, HD2 = 67 dBc, HD3 = 88 dBc
SFDR = 66 dBc, SNR = 66.5 dBFS, SINAD = 66.5 dBFS,
THD = 87 dBc, HD2 = 66 dBc, HD3 = 93 dBc
Figure 9. FFT for 450-MHz Input Signal (Dither On)
Figure 10. FFT for 450-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D811
D812
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 90,
each tone at = –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105,
each tone at = –36 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3421 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
2.5
5
7.5
10
12.5
0
2.5
5
7.5
10
12.5
Frequency (MHz)
Frequency (MHz)
D813
D814
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 91,
each tone at = –7 dBFS
fIN1 = 184.5 MHz, fIN2 = 189.5 MHz, IMD3 = 98 dBFS,
each tone at –36 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-85
-85
-90
-90
-95
-95
-100
-105
-110
-100
-105
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D815
D816
Figure 15. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
Figure 16. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
72
100
Dither_EN
Dither_EN
Dither_DIS
Dither_DIS
95
90
85
80
75
70
65
60
71
70
69
68
67
66
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
D80117
D818
Figure 17. Signal-to-Noise Ratio vs Input Frequency
Figure 18. Spurious-Free Dynamic Range vs
Input Frequency
20
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3421 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
73
72
71
70
69
68
250
200
150
100
50
72.5
280
240
200
160
120
80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
72
71.5
71
70.5
70
69.5
69
40
0
0
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D819
D820
Figure 19. Performance vs Input Amplitude (30 MHz)
Figure 20. Performance vs Input Amplitude (170 MHz)
78
76
74
72
70
68
105
SNR
SFDR
76
88
86
84
82
80
78
SNR
SFDR
100
95
74
72
70
68
66
90
85
80
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D821
D822
Figure 21. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 22. Performance vs Input Common-Mode Voltage
(170 MHz)
95
72
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
93
91
89
87
85
83
71.6
71.2
70.8
70.4
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D823
D824
Figure 23. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
Figure 24. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3421 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
92
91
90
89
88
87
86
72
71.6
71.2
70.8
70.4
70
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D825
D826
Figure 25. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
Figure 26. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
75
74
73
72
71
70
69
68
67
100
76
100
90
80
70
60
50
40
SNR
SFDR
SNR
SFDR
96
92
88
84
80
76
72
68
73
70
67
64
61
58
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D827
D828
Figure 27. Performance vs Clock Amplitude (40 MHz)
Figure 28. Performance vs Clock Amplitude (150 MHz)
70.6
90
88
86
84
82
80
78
71.5
100
98
96
94
92
90
SNR
SFDR
SNR
SFDR
70.4
70.2
70
71.3
71.1
70.9
70.7
70.5
69.8
69.6
69.4
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D829
D830
Figure 29. Performance vs Clock Duty Cycle (30 MHz)
Figure 30. Performance vs Clock Duty Cycle (150 MHz)
22
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
7.16 Typical Characteristics: ADC3422
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D601
D602
SFDR = 89 dBc, SNR = 70.9 dBFS, SINAD = 70.8 dBFS,
THD = 88 dBc, HD2 = 110 dBc, HD3 = 89 dBc
SFDR = 85 dBc, SNR = 71.2 dBFS, SINAD = 70.9 dBFS,
THD = 83 dBc, HD2 = 92 dBc, HD3 = 85 dBc
Figure 31. FFT for 10-MHz Input Signal (Dither On)
Figure 32. FFT for 10-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D603
D604
SFDR = 101 dBc, SNR = 70.6 dBFS, SINAD = 70.5 dBFS,
THD = 98 dBc, HD2 = 106 dBc, HD3 = 101 dBc
SFDR = 90 dBc, SNR = 70.8 dBFS, SINAD = 70.6 dBFS,
THD = 87 dBc, HD2 = 91 dBc, HD3 = 90 dBc
Figure 33. FFT for 70-MHz Input Signal (Dither On)
Figure 34. FFT for 70-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D605
D606
SFDR = 86 dBc, SNR = 69.9 dBFS, SINAD = 69.8 dBFS,
THD = 85 dBc, HD2 = 93 dBc, HD3 = 86 dBc
SFDR = 85 dBc, SNR = 70.1 dBFS, SINAD = 70 dBFS,
THD = 86 dBc, HD2 = 85 dBc ,HD3 = 112 dBc
Figure 35. FFT for 170-MHz Input Signal (Dither On)
Figure 36. FFT for 170-MHz Input Signal (Dither Off)
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3422 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D607
D608
SFDR = 75 dBc, SNR = 69 dBFS, SINAD = 67.9 dBFS,
THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc
SFDR = 75 dBc, SNR = 69.2 dBFS, SINAD = 67.9 dBFS,
THD = 73 dBc, HD2 = 75 dBc, HD3 = 81 dBc
Figure 37. FFT for 270-MHz Input Signal (Dither On)
Figure 38. FFT for 270-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D609
D610
SFDR = 68 dBc, SNR = 67.2 dBFS, SINAD = 67.1 dBFS,
THD = –86 dBc, HD2 = 75 dBc, HD3 = 73 dBc
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.4 dBFS,
THD = –87 dBc, HD2 = –68 dBc, HD3 = –87 dBc
Figure 39. FFT for 450-MHz Input Signal (Dither On)
Figure 40. FFT for 450-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D611
D612
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 102 dBFS,
each tone at –7 dBFS
fIN1 = 46.3 MHz, fIN2 = 50.3 MHz, IMD3 = 110 dBFS,
each tone at –36 dBFS
Figure 41. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 42. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
24
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3422 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
D613
D614
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 95 dBFS,
each tone at –7 dBFS
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 43. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 44. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-80
-85
-90
-95
-80
-85
-90
-95
-100
-100
-105
-110
-105
-110
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D615
D616
Figure 45. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
Figure 46. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
72
100
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
90
85
80
75
70
65
60
71
70
69
68
67
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
D617
D618
Figure 47. Signal-to-Noise Ratio vs Input Frequency
Figure 48. Spurious-Free Dynamic Range vs
Input Frequency
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3422 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
72
71.5
71
240
200
160
120
80
71.5
240
200
160
120
80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR
SFDR
SFDR
71
70.5
70
70.5
70
69.5
69
69.5
40
40
69
0
68.5
0
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D619
D620
Figure 49. Performance vs Input Amplitude (30 MHz)
Figure 50. Performance vs Input Amplitude (170 MHz)
78
96
94
92
90
88
86
76
88
86
84
82
80
78
SNR
SFDR
SNR
SFDR
76
74
72
70
68
74
72
70
68
66
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D621
D622
Figure 51. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 52. Performance vs Input Common-Mode Voltage
(170 MHz)
96
71.5
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
94
92
90
88
86
84
71.1
70.7
70.3
69.9
69.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D623
D624
Figure 53. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (30 MHz)
Figure 54. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (30 MHz)
26
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3422 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
74
73
72
71
70
69
68
94
92
90
88
86
84
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D625
Figure 56. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (30 MHz)
Figure 55. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (30 MHz)
74
96
78
76
74
72
70
68
66
64
62
60
99
SNR
SFDR
SNR
SFDR
96
93
90
87
84
81
78
75
72
73
72
71
70
69
68
93
90
87
84
81
78
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D627
D628
Figure 57. Performance vs Clock Amplitude (40 MHz)
Figure 58. Performance vs Clock Amplitude (150 MHz)
71.3
94
92
90
88
86
84
70.6
90
88
86
84
82
80
SNR
SFDR
SNR
SFDR
71.1
70.9
70.7
70.5
70.3
70.4
70.2
70
69.8
69.6
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D629
D630
Figure 59. Performance vs Clock Duty Cycle (30 MHz)
Figure 60. Performance vs Clock Duty Cycle (150 MHz)
Copyright © 2014–2015, Texas Instruments Incorporated
27
ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
7.17 Typical Characteristics: ADC3423
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D401
D402
SFDR = 89 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 89 dBc, HD2 = 108 dBc, HD3 = 89 dBc
SFDR = 84 dBc, SNR = 70.9 dBFS, SINAD = 70.7 dBFS,
THD = 83 dBc, HD2 = 92 dBc, HD3 = 84 dBc
Figure 61. FFT for 10-MHz Input Signal (Dither On)
Figure 62. FFT for 10-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D403
D404
SFDR = 92 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 91 dBc, HD2 = 112 dBc, HD3 = 92 dBc
SFDR = 86 dBc, SNR = 70.7 dBFS, SINAD = 70.5 dBFS,
THD = 84 dBc, HD2 = 92 dBc, HD3 = 86 dBc
Figure 63. FFT for 70-MHz Input Signal (Dither On)
Figure 64. FFT for 70-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D405
D406
SFDR = 87 dBc, SNR = 70.2 dBFS, SINAD = 70.1 dBFS,
THD = 93 dBc, HD2 = 102 dBc, HD3 = 87 dBc
SFDR = 86 dBc, SNR = 70.5 dBFS, SINAD = 70.4 dBFS,
THD = 88 dBc, HD2 = 86 dBc, HD3 = 97 dBc
Figure 65. FFT for 170-MHz Input Signal (Dither On)
Figure 66. FFT for 170-MHz Input Signal (Dither Off)
28
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3423 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D407
D408
SFDR = 76 dBc, SNR = 69.2 dBFS, SINAD = 68.3 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc
SFDR = 75 dBc, SNR = 69.5 dBFS, SINAD = 68.4 dBFS,
THD = 75 dBc, HD2 = 75 dBc, HD3 = 82 dBc
Figure 67. FFT for 270-MHz Input Signal (Dither On)
Figure 68. FFT for 270-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D409
D410
SFDR = 68 dBc, SNR = 67.5 dBFS, SINAD = 67.1 dBFS,
THD = 77 dBc, HD2 = 68 dBc, HD3 = 89 dBc
SFDR = 67 dBc SNR = 67.7 dBFS, SINAD = 67.3 dBFS,
THD = 77 dBc, HD2 = 67 dBc, HD3 = 84 dBc
Figure 69. FFT for 450-MHz Input Signal (Dither On)
Figure 70. FFT for 450-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D411
D412
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 98 dBFS,
each tone at –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 71. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 72. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Copyright © 2014–2015, Texas Instruments Incorporated
29
ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3423 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
D413
D414
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 90 dBFS,
each tone at –7 dBFS
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 105 dBFS,
each tone at –36 dBFS
Figure 73. FFT FOR Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 74. FFT FOR Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-85
-90
-95
-80
-85
-90
-95
-100
-100
-105
-110
-105
-110
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D415
D416
Figure 75. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
Figure 76. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
72
100
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
71
70
69
68
67
90
85
80
75
70
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
D417
D418
Figure 77. Signal-to-Noise Ratio vs Input Frequency
Figure 78. Spurious-Free Dynamic Range vs
Input Frequency
30
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3423 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
72
71.5
71
240
200
160
120
80
72
71.5
71
180
160
140
120
100
80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
70.5
70
70.5
70
69.5
69
60
69.5
40
68.5
68
40
69
0
20
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D419
D4210
Figure 79. Performance vs Input Amplitude (30 MHz)
Figure 80. Performance vs Input Amplitude (170 MHz)
76
92
90
88
86
84
82
76
90
88
86
84
82
80
SNR
SFDR
SNR
SFDR
74
72
70
68
66
74
72
70
68
66
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D421
D422
Figure 81. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 82. Performance vs Input Common-Mode Voltage
(170 MHz)
95
71
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
93
91
89
87
85
70.8
70.6
70.4
70.2
70
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D423
D424
Figure 83. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
Figure 84. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3423 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
100
96
92
88
84
80
71.5
71.1
70.7
70.3
69.9
69.5
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D425
D426
Figure 85. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
Figure 86. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
76
105
74
96
SNR
SNR
SFDR
SFDR
74
72
70
68
66
102
99
72
70
68
66
64
92
88
84
80
96
93
90
76
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D427
D428
Figure 87. Performance vs Clock Amplitude (40 MHz)
Figure 88. Performance vs Clock Amplitude (150 MHz)
71.3
92
90
88
86
84
82
70.8
92
90
88
86
84
82
SNR
SFDR
SNR
SFDR
71.1
70.9
70.7
70.5
70.3
70.6
70.4
70.2
70
69.8
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D429
D430
Figure 89. Performance vs Clock Duty cycle (30 MHz)
Figure 90. Performance vs Clock Duty Cycle (150 MHz)
32
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
7.18 Typical Characteristics: ADC3424
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D201
D202
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,
THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc
Figure 91. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
Figure 92. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D203
D204
SFDR = 99 dBc, SNR = 70.3 dBFS, SINAD = 70.3 dBFS,
THD = 95 dBc, HD2 = 103 dBc, HD3 = 99 dBc
SFDR = 91 dBc, SNR = 70.6 dBFS, SINAD = 70.6 dBFS,
THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc
Figure 93. FFT for 70-MHz Input Signal (Dither On)
Figure 94. FFT for 70-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D205
D206
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS,
THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc
SFDR = 85 dBc, SNR = 70.3 dBFS, SINAD = 70.2 dBFS,
THD = 88 dBc, HD2 = 99 dBc, HD3 = 85 dBc
Figure 95. FFT for 170-MHz Input Signal (Dither On)
Figure 96. FFT for 170-MHz Input Signal (Dither Off)
Copyright © 2014–2015, Texas Instruments Incorporated
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ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3424 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D207
D208
SFDR = 76 dBc, SNR = 68.94 dBFS, SINAD = 68.4 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 81 dBc
SFDR = 76 dBc, SNR = 69.3 dBFS, SINAD = 68.6 dBFS,
THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc
Figure 97. FFT for 270-MHz Input Signal (Dither On)
Figure 98. FFT for 270-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D209
D210
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS,
THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc
SFDR = 69 dBc, SNR = 67.8 dBFS, SINAD = 66.8 dBFS,
THD = 73 dBc, HD2 = 77 dBc, HD3 = 69 dBc
Figure 99. FFT for 450-MHz Input Signal (Dither On)
Figure 100. FFT for 450-MHz Input Signal (Dither Off)
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D211
D212
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 100 dBFS,
each tone at –7 dBFS
fIN1 = 46 MHz, fIN2 = 50 MHz, IMD3 = 99 dBFS,
each tone at –36 dBFS
Figure 101. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 102. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
34
Copyright © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
Typical Characteristics: ADC3424 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D213
D214
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 86 dBFS,
each tone at –7 dBFS
fIN1 = 185 MHz, fIN2 = 190 MHz, IMD3 = 102 dBFS,
each tone at –36 dBFS
Figure 103. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 104. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-80
-85
-90
-95
-80
-85
-90
-95
-100
-100
-105
-110
-105
-110
-35
-31
-27
-23
-19
-15
-11
-7
-35
-31
-27
-23
-19
-15
-11
-7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
D215
D216
Figure 105. Intermodulation Distortion vs Input Amplitude
(46 MHz and 50 MHz)
Figure 106. Intermodulation Distortion vs Input Amplitude
(185 MHz and 190 MHz)
100
72
Dither_EN
Dither_DIS
Dither_EN
Dither_DIS
95
71
70
69
68
67
90
85
80
75
70
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
D217
D218
Figure 107. Signal-to-Noise Ratio vs Input Frequency
Figure 108. Spurious-Free Dynamic Range vs
Input Frequency
Copyright © 2014–2015, Texas Instruments Incorporated
35
ADC3421, ADC3422, ADC3423, ADC3424
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
www.ti.com.cn
Typical Characteristics: ADC3424 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
72
71.5
71
240
200
160
120
80
72
71.5
71
180
160
140
120
100
80
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
70.5
70
70.5
70
69.5
69
60
69.5
40
68.5
68
40
69
0
20
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
D219
D220
Figure 109. Performance vs Input Amplitude (30 MHz)
Figure 110. Performance vs Input Amplitude (170 MHz)
76
96
94
92
90
88
86
76
74
72
70
68
66
88
86
84
82
80
78
SNR
SFDR
SNR
SFDR
74
72
70
68
66
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
D221
D222
Figure 111. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 112. Performance vs Input Common-Mode Voltage
(170 MHz)
94
72.5
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
92
90
88
86
84
71.7
70.9
70.1
69.3
68.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D223
D224
Figure 113. Spurious-Free Dynamic Range vs
AVDD Supply and Temperature (170 MHz)
Figure 114. Signal-to-Noise Ratio vs
AVDD Supply and Temperature (170 MHz)
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Typical Characteristics: ADC3424 (continued)
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
94
92
90
88
86
84
71.5
71.1
70.7
70.3
69.9
69.5
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
DVDD = 1.7 V
DVDD = 1.75 V
DVDD = 1.8 V
DVDD = 1.85 V
DVDD = 1.9 V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (°C)
Temperature (°C)
D225
D226
Figure 115. Spurious-Free Dynamic Range vs
DVDD Supply and Temperature (170 MHz)
Figure 116. Signal-to-Noise Ratio vs
DVDD Supply and Temperature (170 MHz)
73
105
100
95
72.5
105
SNR
SFDR
SNR
SFDR
72
71
70
69
68
67
66
65
72
71.5
71
100
95
90
85
80
75
70
65
90
85
70.5
70
80
75
69.5
69
70
65
68.5
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
Differential Clock Amplitude (Vpp)
Differential Clock Amplitude (Vpp)
D227
D228
Figure 117. Performance vs Clock Amplitude (40 MHz)
Figure 118. Performance vs Clock Amplitude (150 MHz)
71.5
96
94
92
90
88
86
70.5
90
SNR
SFDR
SNR
SFDR
71.1
70.7
70.3
69.9
69.5
70.3
70.1
69.9
69.7
69.5
87.5
85
82.5
80
77.5
30
35
40
45
50
55
60
65
70
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
D229
D230
Figure 119. Performance vs Clock Duty Cycle (30 MHz)
Figure 120. Performance vs Clock Duty Cycle (150 MHz)
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7.19 Typical Characteristics: Common
Typical values are at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when chopper is enabled, unless otherwise noted.
0
-10
0
-5
-20
-10
-15
-20
-25
-30
-35
-40
-45
-50
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12ꢀ5
25
37ꢀ5
50
62ꢀ5
0
50
100
150
200
250
300
Crequency (aIz)
Frequency of Signal on Supply (MHz)
D001
D002
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
fIN = 30.1 MHz, fPSRR = 3 MHz, APSRR = 50 mVPP
,
SINAD = 58.51 dBFS, SFDR = 60 dBc
Figure 121. Power-Supply Rejection Ratio vs
Test Signal Frequency
Figure 122. Power-Supply Rejection Ratio Spectrum
0
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12ꢀ5
25
37ꢀ5
50
62ꢀ5
0
50
100
150
200
250
300
Crequency (aIz)
Frequency of Input Common-Mode Signal (MHz)
D003
D004
fIN = 30 MHz, AIN = –1 dBFS,
test signal amplitude = 50 mVPP
fIN = 170.1 MHz, fCMRR = 5 MHz, ACMRR = 50 mVPP
,
SINAD = 69.66 dBFS, SFDR = 75 dBc
Figure 123. Common-Mode Rejection Ratio vs
Test Signal Frequency
Figure 124. Common-Mode Rejection Ratio Spectrum
400
320
Analog Power
Digital Power
Total Power
Analog Power
Digital Power
Total Power
240
360
280
320
280
240
200
160
120
80
200
160
120
80
40
5
15 25 35 45 55 65 75 85 95 105 115 125
Sampling Speed (MSPS)
10
20
30
40
50
60
70
80
Sampling Speed (MSPS)
D009
D010
Figure 125. Power vs Sampling Frequency
(Two-Wire Mode)
Figure 126. Power vs Sampling Frequency
(One-Wire Mode)
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7.20 Typical Characteristics: Contour
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-
dBFS differential input, 2-VPP full-scale, 32k-point FFT, chopper disabled, and SNR reported with a 1-MHz offset from dc
when chopper is disabled and from fS / 2 when is chopper enabled, unless otherwise noted.
120
110
100
90
120
110
100
90
85
81 77
73
70.5
69.5
89
68.5
69
67.5
70
68
69
80
80
85
73
70.5
69.5
81 77
89
70
70
68.5
70
69
69
67.5
68
60
60
50
50
40
40
85
69.5
73
68.5
70
70.5
67.5
69
67
89
68
81 77
30
30
85
66.5
69
50
100
150
200
250
300
350
400
450
50
100
150
200
250
300
350
400
450
Input Frequency, MHz
Input Frequency, MHz
70
75
80
85
66
66.5
67
67.5
68
68.5
69
69.5
70
70.5
Figure 127. Spurious-Free Dynamic Range (SFDR)
Figure 128. Signal-to-Noise Ratio (SNR)
8 Parameter Measurement Information
8.1 Timing Diagrams
DAn_P
DBn_P
Logic 0
VODL = -350 mV(1)
Logic 1
VODH = +350 mV(1)
DAn_M
DBn_M
VOCM
GND
(1) With an external 100-Ω termination.
Figure 129. Serial LVDS Output Voltage Levels
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Timing Diagrams (continued)
CLKIN
FCLK
DCLK
Dx0P
1-Wire (12x Serialization)
D
9
D
D
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
0
10 11
10 11
Dx0M
DCLK
Dx0P
Dx0M
D
5
D
0
D
1
D
2
D
3
D
4
D
5
D
0
2-Wire (6x Serialization)
Dx1P
Dx1M
D
11
D
6
D
7
D
8
D
9
D
10
D
11
D
6
SAMPLE N-1
SAMPLE N
SAMPLE N+1
Figure 130. Output Timing Diagram
DCLK
t HO
Dx0P
Dx0M
t SU
Figure 131. Setup and Hold Time
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9 Detailed Description
9.1 Overview
The ADC342x are a high-linearity, ultra-low power, quad-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-
digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency
signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock
architecture design and the SYSREF input enables complete system synchronization. The ADC342x family
supports a serial low-voltage differential signaling (LVDS) interface in order to reduce the number of interface
lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC
data are serialized and output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming
ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In
addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.
9.2 Functional Block Diagram
DA0P
DA0M
INAP
INAM
12-Bit
ADC
Digital Encoder
and Serializer
DA1P
DA1M
DB0P
DB0M
Digital Encoder
and Serializer
INBP
INBM
12-Bit
ADC
DB1P
DB1M
Bit Clock
CLKP
CLKM
Divide
by 1,2,4
DCLKP
DCLKM
PLL
Frame Clock
FCLKP
FCLKM
SYSREFP
SYSREFM
DC0P
DC0M
INCP
INCM
12-Bit
ADC
Digital Encoder
and Serializer
DC1P
DC1M
DD0P
DD0M
INDP
INDM
12-Bit
ADC
Digital Encoder
and Serializer
DD1P
DD1M
Common
Mode
Configuration
Registers
VCM
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC342x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing
symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input swing.
The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω
termination between INP and INM).
9.3.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
0.95 V using internal 5-kΩ resistors. The self-bias clock inputs of the ADC342x can be driven by the transformer-
coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in
Figure 132, Figure 133, and Figure 134. See Figure 135 for details regarding the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100 W
0.1 mF
CLKM
Device
0.1 mF
Zo
CLKM
NOTE: RT = termination resistor, if necessary.
Device
Figure 132. Differential Sine-Wave Clock Driving
Circuit
Figure 133. LVDS Clock Driving Circuit
0.1 mF
Zo
CLKP
150 W
Typical LVPECL
Clock Input
100 W
0.1 mF
Zo
CLKM
Device
150 W
Figure 134. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2 nH
20 Ω
CLKP
CBOND
1 pF
5 kΩ
CEQ
CEQ
RESR
100 Ω
0.95 V
CEQ
LPKG
2 nH
5 kΩ
20 Ω
CLKM
CBOND
1 pF
RESR
100 Ω
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 135. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 136. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 136. Single-Ended Clock Driving Circuit
9.3.2.1 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization
noise (typically 74 dB for a 12-bit ADC) and thermal noise limit SNR at low input frequencies, and the clock jitter
sets SNR for higher input frequencies.
2
2
2
SNRQuantizatoin
SNR
SNR
Jitter
Noise
≈
’
÷
Thermal Noise
≈
’
÷
≈
’
÷
-
-
-
∆
20
20
20
∆
∆
SNRADC[dBc] = -20∂log 10
+ 10
+ 10
∆
«
÷
◊
∆
«
÷
∆
«
÷
◊
◊
(1)
(2)
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2.
SNRJitter[dBc] = -20∂log(2p ∂ fin ∂TJitter )
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The total clock jitter (TJitter) has two components: the internal aperture jitter (130 fs for the device) which is set by
the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3.
2
TJitter = (TJitter,Ext.Clock _ Input )2 +(TAperture_ ADC
)
(3)
External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input; a faster clock slew rate improves the ADC aperture jitter. The devices have a typical
thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of external
jitter for different input frequencies, is shown in Figure 137.
71.0
70.5
70.0
69.5
69.0
68.5
Ext Clock Jitter
68.0
35 fs
50 fs
67.5
67.0
66.5
66.0
65.5
65.0
100 fs
150 fs
200 fs
10
100
Input Frequency (MHz)
1000
D00316
Figure 137. SNR vs Frequency for Different Clock Jitter
9.3.3 Digital Output Interface
The devices offer two different output format options, thus making interfacing to a field-programmable gate array
(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option can be easily programmed using
the serial interface, as shown in Table 3. The output interface options are:
•
•
One-wire, 1x frame clock, 12x serialization with the DDR bit clock and
Two-wire, 1x frame clock, 6x serialization with the DDR bit clock.
Table 3. Interface Rates
RECOMMENDED SAMPLING
FREQUENCY (MSPS)
BIT CLOCK
FREQUENCY
(MHz)
FRAME CLOCK
FREQUENCY
(MHz)
SERIAL DATA
RATE PER
WIRE (Mbps)
INTERFACE
OPTIONS
SERIALIZATION
MINIMUM
MAXIMUM
15
90
480
60
15
80
20
180
960
120
One-wire
12x
6x
80
Two-wire
(Default after
Reset)
20(1)
125
375
125
750
(1) Use the LOW SPEED ENABLE register bits for low speed operation; see Table 21.
9.3.3.1 One-Wire Interface: 12x Serialization
In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The
data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at
the rising edge of every frame clock, starting with the LSB. The data rate is 12x sample frequency (12x
serialization).
44
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9.3.3.2 Two-Wire Interface: 6x Serialization
The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 6x
sample frequency because six data bits are output every clock cycle on each differential pair. Each ADC sample
is sent over the two wires with the six MSBs on Dx1P, Dx1M and the six LSBs on Dx0P, Dx0M, as shown in
Figure 138.
CLKIN
FCLK
DCLK
1-Wire (12x Serialization)
Dx0P
D
9
D
D
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
D
D
0
10 11
10 11
Dx0M
DCLK
Dx0P
Dx0M
D
5
D
0
D
1
D
2
D
3
D
4
D
5
D
0
2-Wire (6x Serialization)
Dx1P
Dx1M
D
11
D
6
D
7
D
8
D
9
D
10
D
11
D
6
SAMPLE N-1
SAMPLE N
SAMPLE N+1
Figure 138. Output Timing Diagram
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9.4 Device Functional Modes
9.4.1 Input Clock Divider
The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a
faster input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed for
operation with a 125-MHz clock and the divide-by-2 option supports a maximum input clock of 250 MHz and the
divide-by-4 option provides a maximum input clock frequency of 500 MHz.
9.4.2 Chopper Functionality
The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC
noise spectrum by shifting the 1/f noise from dc to fS / 2. Figure 139 shows the noise spectrum with the chopper
off and Figure 140 shows the noise spectrum with the chopper on. This function is especially useful in
applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper
can be enabled via SPI register writes and is recommended for input frequencies below 30 MHz. The chopper
function creates a spur at fS / 2 that must be filtered out digitally.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
D016
D017
fS = 125 MSPS, SNR = 70.4 dBFS,
fIN = 10 MHz, SFDR = 98 dBc
fS = 125 MSPS, SNR = 70.4 dBFS,
fIN = 10 MHz, SFDR = 97 dBc
Figure 139. Chopper Off
Figure 140. Chopper On
9.4.3 Power-Down Control
The power-down functions of the ADC342x can be controlled either through the parallel control pin (PDN) or
through an SPI register setting (see register 15h). The PDN pin can also be configured via SPI to a global power-
down or standby functionality, as shown in Table 4.
Table 4. Power-Down Modes
FUNCTION
Global power-down
Standby
POWER CONSUMPTION (mW)
WAKE-UP TIME (µs)
5
85
35
45
46
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9.4.4 Internal Dither Algorithm
The ADC342x use an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the dither
algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither algorithm
can be turned off by using the DIS DITH CHx registers bits. Figure 141 and Figure 142 show the effect of using
dither algorithms.
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
D201
D202
SFDR = 95 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,
THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc
SFDR = 91 dBc, SNR = 70.7 dBFS, SINAD = 70.6 dBFS,
THD = 86 dBc, HD2 = 92 dBc, HD3 = 91 dBc
Figure 141. FFT for 10-MHz Input Signal
(Chopper On, Dither On)
Figure 142. FFT for 10-MHz Input Signal
(Chopper On, Dither Off)
9.4.5 Summary of Performance Mode Registers
Table 5 lists the location, value, and functions of performance mode registers in the device.
Table 5. Performance Modes
MODE
REGISTER SETTINGS
DESCRIPTION
Special modes
Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3)
Always write 1 for best performance
Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3),
434 (bits 5 and 3), and 534 (bits 5 and 3)
Disable dither
Disable dither to improve SNR
Disable chopper Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1)
Disable chopper (shifts 1/f noise floor at dc)
Improves HD3 by a couple of dB for IF > 100 MHz
Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1),
High IF modes
308h (bits 7-6) and 608h (bits 7-6)
9.5 Programming
The ADC342x can be configured using a serial programming interface, as described in this section.
9.5.1 Serial Interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are
ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can
function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%
SCLK duty cycle.
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Programming (continued)
9.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 143. If required,
the serial interface registers can be cleared during operation either:
1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
9.5.1.1.1 Serial Register Write
The device internal register can be programmed with these steps:
1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.
Figure 143 and Table 6 show the timing requirements for the serial register write operation.
Register Address [13:0]
A13 A12 A11 A1
Register Data [7:0]
SDATA
R/W
= 0
1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
Figure 143. Serial Register Write Timing Diagram
Table 6. Serial Interface Timing(1)
MIN
> dc
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIO setup time
)
20
25
ns
25
ns
tDH
SDIO hold time
25
ns
(1) Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise
noted.
48
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9.5.1.1.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.
This readback mode may be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.
When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the
SDOUT pin must float. Figure 144 shows a timing diagram of the serial register read operation. Data appear on
the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 145.
Register Address [13:0]
A13 A12 A11 A1
Register Data: Don‘t Care
D5 D4 D3 D2
SDATA
R/W
= 1
A0
D7
D7
D6
D6
D1
D1
D0
D0
1
Register Read Data [7:0]
SDOUT
SCLK
D5
D4
D3
D2
SEN
Figure 144. Serial Register Read Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 145. SDOUT Timing Diagram
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9.5.2 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 146 and Table 7.
Power
Supplies
t1
RESET
t2
t3
SEN
Figure 146. Initialization of Serial Registers after Power-Up
Table 7. Power-Up Timing
MIN
1
TYP
MAX
UNIT
ms
ns
t1
t2
t3
Power-on delay from power-up to active high RESET pulse
Reset pulse duration: active high RESET pulse duration
Register write delay from RESET disable to SEN active
10
100
ns
If required, the serial interface registers can be cleared during operation either:
1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
50
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9.6 Register Maps
Table 8. Register Map Summary
REGISTER
REGISTER DATA
ADDRESS,
A[13:0] (Hex)
7
6
5
4
3
2
1
0
Register 01h
Register 03h
Register 04h
Register 05h
DIS DITH CHA
DIS DITH CHB
DIS DITH CHC
DIS DITH CHD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ODD EVEN
FLIP WIRE
1W-2W
TEST
PATTERN EN
Register 06h
Register 07h
Register 09h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
OVR ON LSB
ALIGN TEST
PATTERN
DATA
FORMAT
Register 0Ah
Register 0Bh
Register 0Eh
Register 0Fh
Register 13h
CHA TEST PATTERN
CHB TEST PATTERN
CHD TEST PATTERN
CHC TEST PATTERN 0
CUSTOM PATTERN[11:4]
0
CUSTOM PATTERN[3:0]
0
0
0
0
0
0
0
0
0
LOW SPEED ENABLE
CONFIG PDN
Register 15h
CHA PDN
CHB PDN
CHC PDN
CHD PDN
STANDBY
GLOBAL PDN
0
PIN
Register 25h
Register 27h
LVDS SWING
CLK DIV
0
0
0
0
0
0
0
0
0
0
0
HIGH IF
MODE0
Register 11Dh
Register 122h
0
0
0
0
DIS CHOP
CHA
0
0
0
0
0
Register 134h
Register 139h
0
0
0
0
DIS DITH CHA
0
0
0
DIS DITH CHA
SP1 CHA
0
0
0
0
0
0
HIGH IF
MODE1
Register 21Dh
Register 222h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIS CHOP
CHD
Register 234h
Register 239h
Register 308
0
0
0
0
DIS DITH CHD
0
0
0
DIS DITH CHD
0
0
0
0
0
0
0
0
0
0
0
SP1 CHD
0
HIGH IF MODE <5:4>
HIGH IF
MODE2
Register 41Dh
Register 422h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIS CHOP
CHB
Register 434h
Register 439h
0
0
0
0
DIS DITH CHB
0
0
0
DIS DITH CHB
SP1 CHB
0
0
0
0
0
0
HIGH IF
MODE3
Register 51Dh
Register 522h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIS CHOP
CHC
Register 534h
Register 539h
Register 608h
Register 70Ah
0
0
0
0
DIS DITH CHC
0
0
0
0
DIS DITH CHC
0
0
0
0
0
0
0
0
0
0
0
0
SP1 CHC
0
HIGH IF MODE <7:6>
0
0
0
0
0
PDN SYSREF
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9.6.1 Serial Register Description
9.6.1.1 Register 01h (address = 01h)
Figure 147. Register 01h
7
6
5
4
3
2
1
0
DIS DITH CHA
R/W-0h
DIS DITH CHB
R/W-0h
DIS DITH CHC
R/W-0h
DIS DITH CHD
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 9. Register 01h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
DIS DITH CHA
R/W
0h
These bits enable or disable the on-chip dither. Control this bit
along with bits 5 and 3 of register 134h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
5-4
3-2
1-0
DIS DITH CHB
DIS DITH CHC
DIS DITH CHD
R/W
R/W
R/W
0h
0h
0h
These bits enable or disable the on-chip dither. Control this bit
along with bits 5 and 3 of register 434h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
These bits enable or disable the on-chip dither. Control this bit
along with bits 5 and 3 of register 534h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
These bits enable or disable the on-chip dither. Control this bit
along with bits 5 and 3 of register 234h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
9.6.1.2 Register 03h (address = 03h)
Figure 148. Register 03h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
ODD EVEN
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 10. Register 03h Field Descriptions
Bit
7-6
0
Field
Type
W
Reset
0h
Description
0
Must write 0.
ODD EVEN
R/W
0h
This bit selects the bit sequence on the output wires (in 2-wire
mode only).
0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and
so forth appear on wire-1.
1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and
so forth appear on wire-1.
52
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
9.6.1.3 Register 04h (address = 04h)
Figure 149. Register 04h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FLIP WIRE
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 11. Register 04h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0.
FLIP WIRE
R/W
0h
This bit flips the data on the output wires. Valid only in two wire
configuration.
0 = Default
1 = Data on output wires is flipped. Pin D0x becomes D1x, and
vice versa.
9.6.1.4 Register 05h (address = 05h)
Figure 150. Register 05h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
1W-2W
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 12. Register 05h Field Descriptions
Bit
7-1
0
Field
0
Type
W
Reset
0h
Description
Must write 0.
1W-2W
R/W
0h
This bit transmits output data on either one or two wires.
0 = Output data are transmitted on two wires (Dx0P, Dx0M and
Dx1P, Dx1M)
1 = Output data are transmitted on one wire (Dx0P, Dx0M). In
this mode, the recommended fS is less than 80 MSPS.
9.6.1.5 Register 06h (address = 06h)
Figure 151. Register 06h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
TEST PATTERN EN
R/W-0h
RESET
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 13. Register 06h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
TEST PATTERN EN
R/W
0h
This bit enables test pattern selection for the digital outputs.
0 = Normal output
1 = Test pattern output enabled
0
RESET
R/W
0h
This bit applies a software reset.
This bit resets all internal registers to the default values and self-
clears to 0.
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9.6.1.6 Register 07h (address = 07h)
Figure 152. Register 07h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
OVR ON LSB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 14. Register 07h Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0.
OVR ON LSB
R/W
0h
This bit provides OVR information on the LSB bits.
0 = Output data bit 0 functions as the LSB of the 12-bit data
1 = Output data bit 0 carries the overrange (OVR) information
9.6.1.7 Register 09h (address = 09h)
Figure 153. Register 09h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ALIGN TEST PATTERN
R/W-0h
DATA FORMAT
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 15. Register 09h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
ALIGN TEST PATTERN
R/W
0h
This bit aligns the test patterns across the outputs of both
channels.
0 = Test patterns of both channels are free running
1 = Test patterns of both channels are aligned
0
DATA FORMAT
R/W
0h
This bit selects th digital output data format.
0 = Twos complement
1 = Offset binary
54
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9.6.1.8 Register 0Ah (address = 0Ah)
Figure 154. Register 0Ah
7
6
5
4
3
2
1
0
CHA TEST PATTERN
R/W-0h
CHB TEST PATTERN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 16. Register 0Ah Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CHA TEST PATTERN
R/W
0h
These bits control the test pattern for channel A after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010
and 010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle
from code 0 to 4095
0101 = Custom pattern: output data are the same as
programmed by the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048,
3496, 4095, 3496, 2048, and 599
Others = Do not use
3-0
CHB TEST PATTERN
R/W
0h
These bits control the test pattern for channel B after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010
and 010101010101
0100 = Digital ramp: data increment by 1 LSB every clock cycle
from code 0 to 4095
0101 = Custom pattern: output data are the same as
programmed by the CUSTOM PATTERN register bits
0110 = Deskew pattern: data are AAAh
1000 = PRBS pattern: data are a sequence of pseudo random
numbers
1001 = 8-point sine-wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048,
3496, 4095, 3496, 2048, and 599
Others = Do not use
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9.6.1.9 Register 0Bh (address = 0Bh)
Figure 155. Register 0Bh
7
6
5
4
3
2
1
0
CHC TEST PATTERN
R/W-0h
CHD TEST PATTERN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 17. Register 0Bh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CHC TEST PATTERN
R/W
0h
These bits control the test pattern for channel C after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010
and 010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle
from code 0 to 4095.
0110 = Custom pattern: output data are the same as
programmed by the CUSTOM PATTERN register bits.
1000 = Deskew pattern: data are AAAh.
1010 = PRBS pattern: data are a sequence of pseudo random
numbers.
1011 = 8-point sine wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048,
3496, 4095, 3496, 2048, 599.
Others = Do not use
3-0
CHD TEST PATTERN
R/W
0h
These bits control the test pattern for channel D after the TEST
PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 101010101010
and 010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle
from code 0 to 4095.
0110 = Custom pattern: output data are the same as
programmed by the CUSTOM PATTERN register bits.
1000 = Deskew pattern: data are AAAh.
1010 = PRBS pattern: data are a sequence of pseudo random
numbers.
1011 = 8-point sine wave: data are a repetitive sequence of the
following eight numbers that form a sine-wave: 0, 599, 2048,
3496, 4095, 3496, 2048, 599.
Others = Do not use
9.6.1.10 Register 0Eh (address = 0Eh)
Figure 156. Register 0Eh
7
6
5
4
3
2
1
0
CUSTOM PATTERN[11:4]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 18. Register 0Eh Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CUSTOM PATTERN[11:4]
R/W
0h
These bits set the 12-bit custom pattern (bits 11-4) for all
channels.
56
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ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
9.6.1.11 Register 0Fh (address = 0Fh)
Figure 157. Register 0Fh
7
6
5
4
3
0
2
0
1
0
0
0
CUSTOM PATTERN[3:0]
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 19. Register 0Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-4
CUSTOM PATTERN[3:0]
R/W
0h
These bits set the 12-bit custom pattern (bits 3-0) for all
channels.
3-0
0
W
0h
Must write 0.
9.6.1.12 Register 13h (address = 13h)
Figure 158. Register 13h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LOW SPEED ENABLE
W-0h R/W-0h
W-0h
R/W-0h
R/W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 20. Register 13h Field Descriptions
Bit
7-2
1-0
Field
Type
W
Reset
0h
Description
0
Must write 0.
LOW SPEED ENABLE
R/W
0h
Enables low speed operation in 1-wire and 2-wire mode.
Depending upon sampling frequency, write this bit as per
Table 21.
Table 21. LOW SPEED ENABLE Register Settings Across fS
fS, MSPS
REGISTER BIT LOW SPEED ENABLE
MIN
25
MAX
125
25
1-WIRE MODE
2-WIRE MODE
00
10
10
00
11
20
15
20
Not supported
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9.6.1.13 Register 15h (address = 15h)
Figure 159. Register 15h
7
6
5
4
3
2
1
0
0
CONFIG PDN
PIN
CHA PDN
W-0h
CHB PDN
R/W-0h
CHC PDN
R/W-0h
CHD PDN
W-0h
STANDBY
R/W-0h
GLOBAL PDN
R/W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 22. Register 15h Field Descriptions
Bit
Field
Type
Reset
Description
7
CHA PDN
W
0h
0 = Normal operation
1 = Power-down channel A
6
5
4
3
CHB PDN
CHC PDN
CHD PDN
STANDBY
R/W
R/W
W
0h
0h
0h
0h
0 = Normal operation
1 = Power-down channel B
0 = Normal operation
1 = Power-down channel C
0 = Normal operation
1 = Power-down channel D
R/W
The ADCs of both channels enter standby.
0 = Normal operation
1 = Standby
2
GLOBAL PDN
R/W
0h
0 = Normal operation
1 = Global power-down
1
0
0
W
0h
0h
Must write 0.
CONFIG PDN PIN
R/W
This bit configures the PDN pin as either a global power-down or
standby pin.
0 = Logic high voltage on the PDN pin sends the device into
global power-down
1 = Logic high voltage on the PDN pin sends the device into
standby
9.6.1.14 Register 25h (address = 25h)
Figure 160. Register 25h
7
6
5
4
3
2
1
0
LVDS SWING
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 23. Register 25h Field Descriptions
Bit
Field
Type
Reset
Description
7-0
LVDS SWING
R/W
0h
These bits control the swing of the LVDS outputs (including the
data output, bit clock, and frame clock).
58
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9.6.1.15 Register 27h (address = 27h)
Figure 161. Register 27h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
CLK DIV
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 24. Register 27h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
CLK DIV
R/W
0h
These bits select the internal clock divider for the input sampling
clock.
00 = Divide-by-1
01 = Divide-by-1
10 = Divide-by-2
11 = Divide-by-4
5-0
0
W
0h
Must write 0.
9.6.1.16 Register 11Dh (address = 11Dh)
Figure 162. Register 11Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE0
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 25. Register 11Dh Field Descriptions
Bit
7-2
1
Field
Type
Reset
Description
0
W
0h
Must write 0.
HIGH IF MODE0
Set the HIGH IF MODE[7:0] bits together to 1111.
Improves HD3 by a couple of dB for IF > 100 MHz.
0
0
W
0h
Must write 0.
9.6.1.17 Register 122h (address = 122h)
Figure 163. Register 122h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 26. Register 122h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS CHOP CHA
R/W
0h
This bit disables the chopper.
Set this bit to shift the 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0.
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9.6.1.18 Register 134h (address = 134h)
Figure 164. Register 134h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHA
R/W-0h
DIS DITH CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 27. Register 134h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS DITH CHA
R/W
0h
Set this bit along with bits 7 and 6 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
4
3
0
W
0h
0h
Must write 0.
DIS DITH CHA
R/W
Set this bit along with bits 7 and 6 of register 01h.
00 = Default
11 = Dither is disabled for channel A. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
2-0
0
W
0h
Must write 0.
9.6.1.19 Register 139h (address = 139h)
Figure 165. Register 139h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SP1 CHA
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 28. Register 139h Field Descriptions
Bit
7-4
3
Field
0
Type
W
Reset
0h
Description
Must write 0.
SP1 CHA
R/W
0h
This bit sets the special mode for best performance on channel
A.
Always write 1 after reset.
2-0
0
W
0h
Must write 0.
9.6.1.20 Register 21Dh (address = 21Dh)
Figure 166. Register 21Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE1
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 29. Register 21Dh Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
HIGH IF MODE1
R/W
0h
Set the HIGH IF MODE[7:0] bits together to 1111.
Improves HD3 by a couple of dB for IF > 100 MHz.
0
0
W
0h
Must write 0.
60
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9.6.1.21 Register 222h (address = 222h)
Figure 167. Register 222h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHD
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 30. Register 222h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS CHOP CHD
R/W
0h
This bit disables the chopper.
Set this bit to shift the 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0.
9.6.1.22 Register 234h (address = 234h)
Figure 168. Register 234h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHD
R/W-0h
DIS DITH CHD
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 31. Register 234h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS DITH CHD
R/W
0h
Set this bit with bits 1 and 0 of register 01h.
00 = Default
11 = Dither is disabled for channel D. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
4
3
0
W
0h
0h
Must write 0.
DIS DITH CHD
R/W
Set this bit with bits 1 and 0 of register 01h.
00 = Default
11 = Dither is disabled for channel D. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
2-0
0
W
0h
Must write 0.
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9.6.1.23 Register 239h (address = 239h)
Figure 169. Register 239h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SP1 CHD
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 32. Register 239h Field Descriptions
Bit
7-4
3
Field
0
Type
W
Reset
0h
Description
Must write 0.
SP1 CHD
R/W
0h
This bit sets the special mode for best performance on channel
D.
Always write 1 after reset.
2-0
0
W
0h
Must write 0.
9.6.1.24 Register 308h (address = 308h)
Figure 170. Register 308h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
HIGH IF MODE<5:4>
W-0h W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 33. Register 308h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
HIGH IF MODE<5:4>
R/W
0h
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
5-0
0
W
0h
Must write 0.
9.6.1.25 Register 41Dh (address = 41Dh)
Figure 171. Register 41Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE2
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 34. Register 41Dh Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
HIGH IF MODE2
R/W
0h
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
0
0
W
0h
Must write 0.
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9.6.1.26 Register 422h (address = 422h)
Figure 172. Register 422h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 35. Register 422h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS CHOP CHB
R/W
0h
This bit disables the chopper.
Set this bit to shift the 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0.
9.6.1.27 Register 434h (address = 434h)
Figure 173. Register 434h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHB
R/W-0h
DIS DITH CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 36. Register 434h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS DITH CHB
R/W
0h
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
4
3
0
W
0h
0h
Must write 0.
DIS DITH CHB
R/W
Set this bit with bits 5 and 4 of register 01h.
00 = Default
11 = Dither is disabled for channel B. In this mode, SNR typically
improves by 0.2 dB at 70 MHz.
2-0
0
W
0h
Must write 0.
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9.6.1.28 Register 439h (address = 439h)
Figure 174. Register 439h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SP1 CHB
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 37. Register 439h Field Descriptions
Bit
7-4
3
Field
0
Type
W
Reset
0h
Description
Must write 0.
SP1 CHB
R/W
0h
This bit sets the special mode for best performance on channel
B.
Always write 1 after reset.
2-0
0
W
0h
Must write 0.
9.6.1.29 Register 51Dh (address = 51Dh)
Figure 175. Register 51Dh
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
HIGH IF MODE3
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 38. Register 51Dh Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
HIGH IF MODE3
R/W
0h
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
0
0
W
0h
Must write 0.
9.6.1.30 Register 522h (address = 522h)
Figure 176. Register 522h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
DIS CHOP CHC
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 39. Register 522h Field Descriptions
Bit
7-2
1
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS CHOP CHC
R/W
0h
This bit disables the chopper.
Set this bit to shift the 1/f noise floor at dc.
0 = 1/f noise floor is centered at fS / 2 (default)
1 = Chopper mechanism is disabled; 1/f noise floor is centered
at dc
0
0
W
0h
Must write 0.
64
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9.6.1.31 Register 534h (address = 534h)
Figure 177. Register 534h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHC
R/W-0h
DIS DITH CHC
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 40. Register 534h Field Descriptions
Bit
7-6
5
Field
Type
W
Reset
0h
Description
0
Must write 0.
DIS DITH CHC
R/W
0h
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel C. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
4
3
0
W
0h
0h
Must write 0.
DIS DITH CHC
R/W
Set this bit with bits 3 and 2 of register 01h.
00 = Default
11 = Dither is disabled for channel C. In this mode, SNR
typically improves by 0.2 dB at 70 MHz.
2-0
0
W
0h
Must write 0.
9.6.1.32 Register 539h (address = 539h)
Figure 178. Register 539h
7
0
6
0
5
0
4
0
3
2
0
1
0
0
0
SP1 CHC
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 41. Register 539h Field Descriptions
Bit
7-4
3
Field
0
Type
W
Reset
0h
Description
Must write 0.
SP1 CHC
R/W
0h
This bit sets the special mode for best performance on channel
C.
Always write 1 after reset.
2-0
0
W
0h
Must write 0.
9.6.1.33 Register 608h (address = 608h)
Figure 179. Register 608h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
HIGH IF MODE<7:6>
W-0h W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 608h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
HIGH IF MODE<7:6>
R/W
0h
Set the HIGH IF MODE[7:0] bits together to FFh.
Improves HD3 by a couple of dB for IF > 100 MHz.
5-0
0
W
0h
Must write 0.
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9.6.1.34 Register 70Ah (address = 70Ah)
Figure 180. Register 70Ah
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PDN SYSREF
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 43. Register 70Ah Field Descriptions
Bit
7-1
0
Field
Type
W
Reset
0h
Description
0
Must write 0.
PDN SYSREF
R/W
0h
If the SYSREF pins are not used in the system, the SYSREF
buffer must be powered down by setting this bit.
0 = Normal operation
1 = Powers down the SYSREF buffer
10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC
inputs. When designing the dc driving circuits, the ADC input impedance must be considered. Figure 181 and
Figure 182 show the impedance (Zin = Rin || Cin) across the ADC input pins.
10
6
5
4
3
2
1
1
0.1
0.01
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
D024
D00215
Figure 181. Differential Input Resistance, RIN
Figure 182. Differential Input Capacitance, CIN
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10.2 Typical Applications
10.2.1 Driving Circuit Design: Low Input Frequencies
39 nH
0.1 mF
INP
0.1 mF
50 Ω
50 Ω
25 Ω
25 Ω
0.1 mF
22 pF
50 Ω
50 Ω
INM
1:1
1:1
0.1 mF
39 nH
VCM
Device
Figure 183. Driving Circuit for Low Input Frequencies
10.2.1.1 Design Requirements
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in
series with each input pin can be kept to damp out ringing caused by package parasitic. The drive circuit may
have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and
closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched
impedance to the source.
10.2.1.2 Detailed Design Procedure
A typical application involving using two back-to-back coupled transformers is illustrated in Figure 183. The circuit
is optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used
with the series inductor (39 nH), this combination helps absorb the sampling glitches.
10.2.1.3 Application Curve
Figure 184 shows the performance obtained by using the circuit shown in Figure 183.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D201
SFDR = 97 dBc, SNR = 70.4 dBFS, SINAD = 70.4 dBFS,
THD = 98 dBc, HD2 = 95 dBc, HD3 = 97 dBc
Figure 184. Performance FFT at 10 MHz (Low Input Frequency)
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Typical Applications (continued)
10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
0.1 mF
10 Ω
INP
0.1 mF
15 Ω
25 Ω
0.1 mF
56 nH
10 pF
25 Ω
15 Ω
INM
10 Ω
1:1
1:1
0.1 mF
VCM
Device
Figure 185. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)
10.2.2.1 Design Requirements
See the Design Requirements section for further details.
10.2.2.2 Detailed Design Procedure
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize
performance, as shown in Figure 185.
10.2.2.3 Application Curve
Figure 186 shows the performance obtained by using the circuit shown in Figure 185.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D205
SFDR = 86 dBc, SNR = 69.8 dBFS, SINAD = 69.8 dBFS,
THD = 91 dBc, HD2 = 86 dBc, HD3 = 101 dBc
Figure 186. Performance FFT at 170 MHz (Mid Input Frequency)
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Typical Applications (continued)
10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
0.1 mF
0.1 mF
10 Ω
INP
25 Ω
0.1 mF
25 Ω
INM
1:1
1:1
10 Ω
0.1 mF
VCM
Device
Figure 187. Driving Circuit for High Input Frequencies (fIN > 230 MHz)
10.2.3.1 Design Requirements
See the Design Requirements section for further details.
10.2.3.2 Detailed Design Procedure
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant
improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 187.
10.2.3.3 Application Curve
Figure 188 shows the performance obtained by using the circuit shown in Figure 187.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
12.5
25
37.5
50
62.5
Frequency (MHz)
D209
SFDR = 71 dBc, SNR = 67.2 dBFS, SINAD = 66.5 dBFS,
THD = 74 dBc, HD2 = 71 dBc, HD3 = 79 dBc
Figure 188. Performance FFT at 450 MHz (High Input Frequency)
11 Power Supply Recommendations
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply
requirements during device power-up. AVDD and DVDD can power up in any order.
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12 Layout
12.1 Layout Guidelines
The ADC342x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram
of the EVM top layer is provided in Figure 189. Some important points to remember during laying out the board
are:
1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the
package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,
as shown in the reference layout of Figure 189 as much as possible.
2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 189
as much as possible.
3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital
output traces must not be kept parallel to the analog input traces because this configuration can result in
coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the
receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)]
must be matched in length to avoid skew among outputs.
4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A
separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
12.2 Layout Example
{ampling
/lock
wouting
!nalog
Lnput
wouting
!5/34xx
5igital
hutput
wouting
Figure 189. Typical Layout of the ADC342x Board
70
版权 © 2014–2015, Texas Instruments Incorporated
ADC3421, ADC3422, ADC3423, ADC3424
www.ti.com.cn
ZHCSE81A –JULY 2014–REVISED OCTOBER 2015
13 器件和文档支持
13.1 相关链接
下面的表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，以及样片或购买的快速访
问。
表 44. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
ADC3421
ADC3422
ADC3423
ADC3424
13.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 商标
E2E is a trademark of Texas Instruments.
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2015, Texas Instruments Incorporated
71
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC3421IRTQR
ADC3421IRTQT
ADC3422IRTQR
ADC3422IRTQT
ADC3423IRTQR
ADC3423IRTQT
ADC3424IRTQR
ADC3424IRTQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFN
QFN
QFN
QFN
QFN
QFN
QFN
QFN
RTQ
RTQ
RTQ
RTQ
RTQ
RTQ
RTQ
RTQ
56
56
56
56
56
56
56
56
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AZ3421
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
AZ3421
AZ3422
AZ3422
AZ3423
AZ3423
AZ3424
AZ3424
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC3421IRTQR
ADC3422IRTQR
ADC3423IRTQR
ADC3424IRTQR
QFN
QFN
QFN
QFN
RTQ
RTQ
RTQ
RTQ
56
56
56
56
2000
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
2.25
2.25
2.25
2.25
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC3421IRTQR
ADC3422IRTQR
ADC3423IRTQR
ADC3424IRTQR
QFN
QFN
QFN
QFN
RTQ
RTQ
RTQ
RTQ
56
56
56
56
2000
2000
2000
2000
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTQ 56
8 x 8, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224653/A
www.ti.com
PACKAGE OUTLINE
RTQ0056C
VQFN - 1 mm max height
S
C
A
L
E
1
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
8.15
7.85
A
B
PIN 1 INDEX AREA
8.15
7.85
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
2X 6.5
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
28
15
14
29
SYMM
57
2X 6.5
6.6 0.1
1
42
52X 0.5
PIN 1 ID
0.30
0.18
56
43
56X
0.5
0.3
0.1
C A B
56X
0.05
4224872/A 03/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTQ0056C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.05) TYP
SEE SOLDER MASK
DETAIL
(0.62) TYP
(1.24)
TYP
56X (0.6)
56X (0.24)
56
43
1
42
52X (0.5)
(3.05) TYP
(1.24) TYP
(R0.05) TYP
57
SYMM
(7.8)
(0.62) TYP
(
6.6)
0.2) TYP
VIA
14
29
28
15
SYMM
(7.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224872/A 03/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTQ0056C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.24) TYP
43
56X (0.6)
56X (0.24)
56
1
42
52X (0.5)
(R0.05) TYP
(1.24) TYP
(7.8)
57
SYMM
25X ( 1.04)
14
29
15
28
SYMM
(7.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 57
62% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4224872/A 03/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
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将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
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