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ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

ADC344x 四通道、14 位、25MSPS 至 125MSPS 模数转换器

1 特性

3 说明

1

•

四通道

ADC344x 器件属于高线性度、超低功耗、四通道、14

位、25MSPS 至 125MSPS 模数转换器 (ADC) 系列。

此类器件专门设计用于支持具有宽动态范围需求且要求

苛刻的高输入频率信号。输入时钟分频器可给予系统时

钟架构设计更高的灵活性，同时 SYSREF 输入可实现

整个系统同步。

14 位分辨率

单电源：1.8V

串行低压差分信号 (LVDS) 接口

支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲

器

•

f_IN= 70MHz 时，信噪比 (SNR) = 72.4dBFS，无杂

散动态范围 (SFDR) = 87dBc

ADC344x 系列支持串行低压差分信令 (LVDS)，从而

减少接口线路的数量，实现高系统集成密度。串行

LVDS 接口为双线制，通过两个 LVDS 对串行输出每

个 ADC 数据。此外，也可提供单线制串行 LVDS 接

口。内部锁相环 (PLL) 会将传入的 ADC 采样时钟加

倍，以获得串行输出各通道的 14 位输出数据时所使用

的位时钟。除了串行数据流之外，数据帧和位时钟也作

为 LVDS 输出进行传送。

超低功耗：

–

125MSPS 时为每通道 98mW

•

通道隔离：105dB

内部抖动和斩波

支持多芯片同步

与 12 位版本器件之间具有引脚到引脚兼容性

封装：超薄四方扁平无引线 (VQFN)-56 (8mm x

8mm)

器件信息

器件型号

ADC344x

封装

VQFN (56)

封装尺寸（标称值）

2 应用

8.00mm x 8.00mm

•

多载波、多模式蜂窝基站

(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

雷达和智能天线阵列

炮弹制导

电机控制反馈

网络和矢量分析器

通信测试设备

无损检测

微波接收器

软件定义无线电 (SDR)

正交和分集无线电接收器

10MHz 时的频谱

0

-10

SFDR = 95 dBc

SNR = 72.7 dBFS

SINAD = 72.6 dBFS

THD = 100 dBc

HD2 = 95 dBc

-20

-30

HD3 = 96 dBc

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS670

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

7.20 Typical Characteristics: Contour ........................... 44

Parameter Measurement Information ................ 44

8.1 Timing Diagrams..................................................... 44

Detailed Description ............................................ 47

9.1 Overview ................................................................. 47

9.2 Functional Block Diagram ....................................... 47

9.3 Feature Description................................................. 48

9.4 Device Functional Modes........................................ 53

9.5 Programming........................................................... 54

9.6 Register Maps......................................................... 59

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

7.1 Absolute Maximum Ratings ...................................... 6

7.2 ESD Ratings.............................................................. 6

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 7

7.5 Electrical Characteristics: General............................ 7

7.6 Electrical Characteristics: ADC3441, ADC3442 ....... 8

7.7 Electrical Characteristics: ADC3443, ADC3444 ....... 8

7.8 AC Performance: ADC3441...................................... 9

7.9 AC Performance: ADC3442.................................... 11

7.10 AC Performance: ADC3443.................................. 13

7.11 AC Performance: ADC3444.................................. 15

7.12 Digital Characteristics ........................................... 17

7.13 Timing Requirements: General ............................. 17

7.14 Timing Requirements: LVDS Output..................... 18

7.15 Typical Characteristics: ADC3441 ........................ 19

7.16 Typical Characteristics: ADC3442 ........................ 25

7.17 Typical Characteristics: ADC3443 ........................ 31

7.18 Typical Characteristics: ADC3444 ........................ 37

7.19 Typical Characteristics: Common ......................... 43

8

9

10 Application and Implementation........................ 74

10.1 Application Information.......................................... 74

10.2 Typical Applications .............................................. 75

11 Power Supply Recommendations ..................... 77

12 Layout................................................................... 78

12.1 Layout Guidelines ................................................. 78

12.2 Layout Example .................................................... 78

13 器件和文档支持 ..................................................... 79

13.1 相关链接................................................................ 79

13.2 接收文档更新通知 ................................................. 79

13.3 社区资源................................................................ 79

13.4 商标....................................................................... 79

13.5 静电放电警告......................................................... 79

13.6 Glossary................................................................ 79

14 机械、封装和可订购信息....................................... 79

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision A (October 2015) to Revision B

Page

•

已添加在说明部分添加了有关可提供单线制串行 LVDS 接口的说明..................................................................................... 1

已更改 10MHz 时的频谱图，显示曲线内的情况 ..................................................................................................................... 1

Changed description of AVDD, DVDD, and GND pins and added active high to description of PDN pin in Pin

Functions table ....................................................................................................................................................................... 5

•

Deleted maximum from parameter description in Recommended Operating Conditions table ............................................ 6

Changed Digital Outputs, R_LOADparameter description in Recommended Operating Conditions table ............................... 6

Changed conditions of all Electrical Characteristics and AC Performance tables ................................................................. 7

Added minimum and maximum specifications to Analog Input, V_OC(VCM)parameter in Electrical Characteristics:

General table .......................................................................................................................................................................... 7

•

Changed description of Analog Input, Analog input bandwidth parameter in Electrical Characteristics: General table........ 7

Deleted footnote 1 from Electrical Characteristics: General table.......................................................................................... 7

Added DC Accuracy, E_Gparameter with its test conditions and footnote 3 to Electrical Characteristics: General table....... 7

Deleted E_G(REF)and E_G(CHAN)from DC Accuracy in Electrical Characteristics: General table ............................................... 7

Changed DC Accuracy, α_(EGCHAN)to α_EGand updated its parameter in Electrical Characteristics: General table ................. 7

Changed Channel-to-Channel Isolation, Crosstalk parameter in Electrical Characteristics: General table: changed

test conditions, added footnote 2............................................................................................................................................ 7

•

Changed test conditions for IMD3 parameter in AC Performance: ADC3441 table ............................................................ 10

Added INL and DNL rows to all AC Performance tables...................................................................................................... 10

Changed Digital Inputs (SYSREFP, SYSREFM) subsection in Digital Characteristics table, added footnote 2 ................. 17

2

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

修订历史记录 (接下页)

•

Changed specifications of Digital Outputs (LVDS Interface), V_OCMparameter in Digital Characteristics table.................... 17

Changed rising to falling in description of SYSREF reference time parameter in Timing Requirements: General table ... 17

Changed Typical Characteristics sections: added dither on to all section condition statements, changed Non 23 to

excluding HD2, HD3 ............................................................................................................................................................. 19

•

Added INL and DNL plots in Typical Characteristics: ADC3441 section ............................................................................. 24

Changed conditions of Figure 34, Figure 35 ........................................................................................................................ 25

Added INL and DNL plots in Typical Characteristics: ADC3442 section ............................................................................ 30

Changed conditions of Figure 67, Figure 68 ........................................................................................................................ 31

Added INL and DNL plots in Typical Characteristics: ADC3443 section ............................................................................ 36

Changed conditions of Figure 100, Figure 101 .................................................................................................................... 37

Added INL and DNL plots in Typical Characteristics: ADC3444 section. ........................................................................... 42

Changed conditions of Figure 134 ...................................................................................................................................... 43

Added Figure 141 to Timing Diagrams section .................................................................................................................... 44

Added Using the SYSREF Input section.............................................................................................................................. 50

Changed the description about synchronization of the phase of the divided clock in each device to the common

sampling clock in Using the SYSREF Input section. ........................................................................................................... 50

•

Added ADC3441 Power-Up Requirements section, deleted the Register Initialization section........................................... 57

Added last sentence to Detailed Design Procedure section of first typical application........................................................ 75

Added Chopper On to caption of Figure 198 ...................................................................................................................... 75

Added Chopper Off to caption of Figure 200 ...................................................................................................................... 76

Changed the caption of Figure 202 from FFT for 450-MHz Input Signal (Dither On) to FFT for 450-MHz Input Signal

(Chopper Off, Dither On) ...................................................................................................................................................... 77

Changes from Original (July 2014) to Revision A

Page

•

已发布量产.............................................................................................................................................................................. 1

3

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

5 Device Comparison Table

RESOLUTION

INTERFACE

(Bits)

25 MSPS

ADC3421

ADC3441

—

50 MSPS

ADC3422

ADC3442

ADC34J22

ADC34J42

80 MSPS

ADC3423

ADC3443

ADC34J23

ADC34J43

125 MSPS

ADC3424

ADC3444

ADC34J24

ADC34J44

160 MSPS

—

12

Serial LVDS

14

—

12

ADC34J25

ADC34J45

JESD204B

14

—

6 Pin Configuration and Functions

RTQ Package

56-Pin VQFN

Top View

56

55

54

53

52

51

50

49

48

47

46

45

44

43

1

2

42

DA1P

DA1M

DA0P

DA0M

DVDD

AVDD

INAM

INAP

DD0M

41

40

39

38

37

36

35

34

33

32

31

30

29

DD0P

DD1M

DD1P

DVDD

PDN

3

4

5

6

7

GND Pad

AVDD

INDM

INDP

AVDD

INCP

INCM

AVDD

8

(Back Side)

9

10

11

12

13

14

AVDD

INBP

INBM

AVDD

15

16

17

18

19

20

21

22

23

24

25

26

27

28

4

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Pin Functions

I/O

DESCRIPTION

NAME

NO.

6, 7, 10, 11, 14,

15, 20, 23, 28, 29,

32, 33, 36

AVDD

I

Analog 1.8-V power supply, decoupled with capacitors

CLKM

CLKP

DA0M

DA0P

DA1M

DA1P

DB0M

DB0P

DB1M

DB1P

DC0M

DC0P

DC1M

DC1P

DD0M

DD0P

DD1M

DD1P

DCLKM

DCLKP

DVDD

FCLKM

FCLKP

GND

21

I

Negative differential clock input for the ADC

Positive differential clock input for the ADC

22

I

4

O

I

Negative serial LVDS output for wire-0 of channel A

Positive serial LVDS output for wire-0 of channel A

Negative serial LVDS output for wire-1 of channel A

Positive serial LVDS output for wire-1 of channel A

Negative serial LVDS output for wire-0 of channel B

Positive serial LVDS output for wire-0 of channel B

Negative serial LVDS output for wire-1 of channel B

Positive serial LVDS output for wire-1 of channel B1

Negative serial LVDS output for wire-0 of channel C

Positive serial LVDS output for wire-0 of channel C

Negative serial LVDS output for wire-1 of channel C

Positive serial LVDS output for wire-1 of channel C

Negative serial LVDS output for wire-0 of channel D

Positive serial LVDS output for wire-0 of channel D

Negative serial LVDS output for wire-1 of channel D

Positive serial LVDS output for wire-1 of channel D

Negative bit clock output

3

2

1

56

55

54

53

46

45

44

43

42

41

40

39

51

50

Positive bit clock output

5, 38, 47, 52

Digital 1.8-V power supply, decoupled with capacitors

Negative frame clock output

49

O

I

48

Positive frame clock output

PowerPAD™

Ground, 0 V. Connect to the printed circuit board (PCB) ground plane.

Negative differential analog input for channel A

Positive differential analog input for channel A

Negative differential analog input for channel B

Positive differential analog input for channel B

Negative differential analog input for channel C

Positive differential analog input for channel C

Negative differential analog input for channel D

Positive differential analog input for channel D

INAM

INAP

8

I

9

I

INBM

INBP

13

12

30

31

35

34

I

INCM

INCP

I

INDM

INDP

I

Power-down control; active high. This pin may be configured through the SPI.

This pin has an internal 150-kΩ pulldown resistor.

PDN

37

I

RESET

SCLK

24

16

17

19

I

Hardware reset; active high. This pin has an internal 150-kΩ pulldown resistor.

Serial interface clock input. This pin has an internal 150-kΩ pulldown resistor.

Serial interface data input. This pin has an internal 150-kΩ pulldown resistor.

Serial interface data output

SDATA

SDOUT

I

O

Serial interface enable; active low.

This pin has an internal 150-kΩ pullup resistor to AVDD.

SEN

18

I

SYSREFM

SYSREFP

VCM

26

25

27

I

Negative external SYSREF input

Positive external SYSREF input

O

Common-mode voltage for analog inputs

5

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

MAX

UNIT

V

Analog supply voltage range, AVDD

Digital supply voltage range, DVDD

INAP, INBP, INAM, INBM

2.1

V

min (1.9, AVDD + 0.3)

CLKP, CLKM

AVDD + 0.3

Voltage applied to

input pins

V

SYSREFP, SYSREFM

SCLK, SEN, SDATA, RESET, PDN

Operating free-air, T_A

Operating junction, T_J

Storage, T_stg

AVDD + 0.3

3.9

85

Temperature

125

150

ºC

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

UNIT

V_(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX

UNIT

SUPPLIES

AVDD

Analog supply voltage range

Digital supply voltage range

1.7

1.8

1.9

V

DVDD

ANALOG INPUT

For input frequencies < 450 MHz

For input frequencies < 600 MHz

2

1

V_ID

Differential input voltage

V_PP

V

V_IC

Input common-mode voltage

VCM ± 0.025

CLOCK INPUT

Input clock frequency

Sampling clock frequency

Sine wave, ac-coupled

LPECL, ac-coupled

15⁽²⁾

125⁽³⁾

MSPS

V_PP

0.2

1.5

1.6

Input clock amplitude (differential)

LVDS, ac-coupled

0.7

Input clock duty cycle

35%

50%

0.95

65%

Input clock common-mode voltage

V

DIGITAL OUTPUTS

C_LOAD

External load capacitance from each output pin to GND

3.3

pF

Differential load resistance to be placed across the positive and negative

pins of the LVDS output pair

R_LOAD

100

Ω

(1) After power-up, only use the RESET pin to reset the device for the first time; see the Register Initialization section for details.

(2) See Table 3 for details.

(3) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 500 MSPS.

6

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.4 Thermal Information

ADC344x

THERMAL METRIC⁽¹⁾

RTQ (VQFN)

UNIT

56 PINS

25.3

9.5

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

3.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

3.3

R_θJC(bot)

0.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics: General

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

PARAMETER

ANALOG INPUT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Differential input full-scale

Input resistance

2.0

6.6

3.7

V_PP

kΩ

pF

r_i

Differential at dc

c_i

Input capacitance

Differential at dc

VCM common-mode voltage

output

V_OC(VCM)

0.8

0.95

1.1

V

VCM output current capability

Input common-mode current

10

mA

Per analog input pin

1.5

µA/MSPS

Analog input bandwidth

(–3-dB point)

50-Ω differential source driving 50-Ω

termination across INP and INM

540

±0.024

0.005

MHz

DC ACCURACY

E_O

Offset error

–25

25

mV

Temperature coefficient of offset

error

α_EO

mV/°C

ADC3441

–2

2

Overall dc gain error of a

channel

E_G

%FS

ADC3442, ADC3443, ADC3444

-2.5

2.5

Temperature coefficient of

overall gain error

α_EG

Δ%FS/°C

CHANNEL-TO-CHANNEL ISOLATION

Between near channels

f_IN= 10 MHz

105

95

Between far channels

Between near channels

f_IN= 100 MHz

Between far channels

105

94

Between near channels

f_IN= 200 MHz

Crosstalk⁽¹⁾⁽²⁾

dB

Between far channels

105

92

Between near channels

f_IN= 230 MHz

Between far channels

105

85

Between near channels

f_IN= 300 MHz

Between far channels

105

(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.

(2) Channels A and B are near to each other but far from channels C and D. Similarly, channels C and D are near to each other but far

from channels A and B; see the Pin Configuration and Functions section for more information.

7

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

7.6 Electrical Characteristics: ADC3441, ADC3442

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3441

TYP

ADC3442

TYP

PARAMETER

ADC clock frequency

MIN

MAX

MIN

MAX

UNIT

MSPS

Bits

25

50

Resolution

14

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

Global power-down dissipation

Standby power-down dissipation

54

45

177

5

74

67

71

56

228

5

97

83

mA

215

17

277

17

mW

34

103

35

103

7.7 Electrical Characteristics: ADC3443, ADC3444

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3443

TYP

ADC3444

TYP

PARAMETER

ADC clock frequency

MIN

MAX

MIN

MAX

UNIT

MSPS

Bits

80

125

Resolution

14

1.8-V analog supply current

1.8-V digital supply current

Total power dissipation

Global power-down dissipation

Standby power-down dissipation

92

68

288

5

125

101

350

17

119

98

391

5

162

145

475

17

mA

mW

40

103

43

103

8

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.8 AC Performance: ADC3441

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3441 (f_S= 25 MSPS)

DITHER ON

MIN

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

73.1

72.9

72.5

72.4

71.4

70.3

72.4

72.2

71.9

71.7

70.9

69.7

–143.7

MAX

MIN

TYP

73.5

73.4

73

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.9

Signal-to-noise ratio

(from 1-MHz offset)

72.7

71.7

70.5

72.9

72.7

72.4

72.0

71.1

69.9

–144.1

–143.9

–143.6

–143.3

–142.3

–141.1

73.4

73.2

71.9

72.8

71.4

70.1

11.9

11.8

11.6

11.4

89

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–143.5 –141.5

–143.1

–143.0

–142.0

–140.9

73.1

72.9

71.7

72.6

71.2

69.9

11.9

11.8

11.7

11.8

11.5

11.3

91

Noise spectral density

(averaged across Nyquist zone)

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

69.9

11.3

82

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

Effective number of bits

91

85

92

87

Spurious-free dynamic range

dBc

85

82

86

85

81

(1) Reported from a 1-MHz offset.

9

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

AC Performance: ADC3441 (continued)

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3441 (f_S= 25 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

92

96

86

84

96

93

85

89

82

100

97

92

98

90

84

80

MAX

TYP

93

91

94

85

84

90

89

88

82

89

82

93

92

94

90

92

86

85

80

83

80

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

82

87

79

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

dBc

Spurious-free dynamic range

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz,

each tone at –7 dBFS

–97

–88

–97

–88

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz,

each tone at –7 dBFS

INL

Integral nonlinearity

f_IN= 20 MHz

±0.75

±0.6

±3

±0.75

±0.6

LSBs

DNL

Differential nonlinearity

–0.95

10

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7.9 AC Performance: ADC3442

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3442 (f_S= 50 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

73.1

72.9

72.7

71.9

71.5

70.4

72.5

72.3

71.9

71.3

71.0

69.8

–146.9

MAX

TYP

73.5

73.3

73.1

72.6

71.8

70.8

72.9

72.7

72.3

72.1

71.2

70.2

–147.3

–146.9

–146.4

–145.6

–144.6

73.4

72.7

73.2

71.8

70.1

11.9

11.8

11.9

11.6

11.4

90

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.7

Signal-to-noise ratio

(from 1-MHz offset)

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–146.7 –144.5

–146.5

–145.7

–145.3

–144.2

73

Noise spectral density

(averaged across Nyquist zone)

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

69.7

11.3

82

72.2

72.1

71.4

69.8

11.9

11.8

11.7

11.6

11.4

90

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

Effective number of bits

92

90

92

90

Spurious-free dynamic range

dBc

87

86

84

83

82

(1) Reported from a 1-MHz offset.

11

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AC Performance: ADC3442 (continued)

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3442 (f_S= 50 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

95

99

93

92

87

85

90

94

87

88

83

99

92

97

89

90

86

85

81

MAX

TYP

92

94

91

92

85

83

92

91

87

89

88

95

93

94

89

91

87

85

83

81

MAX

UNIT

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

83

82

87

79

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

dBc

Spurious-free dynamic range

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–92

–87

–92

–87

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

INL

Integral nonlinearity

f_IN= 20 MHz

±0.8

±0.6

±3

±0.8

±0.6

LSBs

DNL

Differential nonlinearity

–0.95

12

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.10 AC Performance: ADC3443

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3443 (f_S= 80 MSPS)

DITHER ON

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

72.9

72.8

72.5

72.1

71.4

72.5

72.4

72.1

71.7

71.1

–148.8

MAX

TYP

73.2

73.1

72.9

72.4

71.7

72.8

72.6

72.0

71.4

–149.1

–149.0

–148.8

–148.3

–147.6

73.2

72.4

73

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.7

Signal-to-noise ratio

(from 1-MHz offset)

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–148.7 –146.6

–148.4

–148.0

–147.3

72.8

Noise spectral density

(averaged across Nyquist zone)

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

69.7

11.3

81

72.2

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

72.7

71.9

72.2

71.4

11.9

11.8

11.7

11.6

89

71.2

11.8

Effective number of bits

11.8

11.7

11.5

89

90

89

Spurious-free dynamic range

92

dBc

88

86

84

(1) Reported from a 1-MHz offset.

13

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AC Performance: ADC3443 (continued)

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3443 (f_S= 80 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

94

96

97

88

87

89

91

94

95

87

100

98

95

94

88

89

91

87

84

MAX

TYP

91

94

86

85

90

100

93

87

95

94

92

86

87

90

84

82

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

81

86

78

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

dBc

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–98

–88

–98

–88

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

INL

Integral nonlinearity

f_IN= 70 MHz

±0.8

±0.7

±3

±0.8

±0.7

LSBs

DNL

Differential nonlinearity

–0.95

14

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.11 AC Performance: ADC3444

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3444 (f_S= 125 MSPS)

DITHER ON

DITHER OFF

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

MIN

TYP

72.6

72.5

72.2

71.7

70.8

72.4

72.3

72.1

71.5

70.6

–150.4

MAX

MIN

TYP

73

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

70.2

72.9

72.7

72.3

71.7

72.8

72.7

72.5

72.1

71.5

–150.9

–150.8

–150.5

–150.2

–149.6

72.9

72.7

72

Signal-to-noise ratio

(from 1-MHz offset)

SNR

dBFS

Signal-to-noise ratio

(full Nyquist band)

–150.4 –148.1

–150.1

–149.5

–148.7

72.6

Noise spectral density

(averaged across Nyquist zone)

NSD⁽¹⁾

dBFS/Hz

dBFS

Bits

69.3

11.2

80

72.3

Signal-to-noise and distortion

ratio

SINAD⁽¹⁾

ENOB⁽¹⁾

SFDR

72.3

71.5

69.9

70.6

11.8

11.7

11.6

87

11.8

Effective number of bits

11.7

11.6

11.4

92

93

88

Spurious-free dynamic range

89

dBc

86

84

82

(1) Reported from a 1-MHz offset.

15

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AC Performance: ADC3444 (continued)

at maximum sampling rate, 50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise

noted); typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an

ambient temperature range of –40°C to +85°C

ADC3444 (f_S= 125 MSPS)

DITHER ON

MIN

DITHER OFF

MIN

PARAMETER

TEST CONDITIONS

f_IN= 10 MHz

TYP

93

94

90

86

81

96

95

93

87

100

99

94

96

94

91

88

85

80

MAX

TYP

93

91

90

85

80

88

89

87

86

93

94

92

93

90

85

86

82

78

MAX

UNIT

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 100 MHz

f_IN= 170 MHz

f_IN= 230 MHz

80

81

86

77

Second-order harmonic

distortion

HD2

dBc

HD3

Non

Third-order harmonic distortion

Spurious-free dynamic range

dBc

HD2, HD3 (excluding HD2, HD3)

THD

Total harmonic distortion

dBc

f_IN1= 45 MHz,

f_IN2= 50 MHz

–97

–87

–97

–87

Two-tone, third-order

intermodulation distortion

IMD3

dBFS

f_IN1= 185 MHz,

f_IN2= 190 MHz

INL

Integral nonlinearity

f_IN= 70 MHz

±0.75

±0.7

±3

±0.75

±0.7

LSBs

DNL

Differential nonlinearity

–0.95

16

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.12 Digital Characteristics

the dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1; AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, PDN)

V_IH

V_IL

High-level input voltage

Low-level input voltage

1.3

V

All digital inputs support 1.8-V and

3.3-V CMOS logic levels

0.4

RESET, SDATA, SCLK,

PDN

SEN⁽¹⁾

V_HIGH= 1.8 V

V_LOW= 0 V

10

0

High-level input

current

I_IH

µA

RESET, SDATA, SCLK,

PDN

0

Low-level input

current

I_IL

SEN

V_LOW= 0 V

10

DIGITAL INPUTS (SYSREFP, SYSREFM)

Differential swing

0.2

0.8

0.9

1.0

0.1

V

Common-mode voltage for SYSREF⁽²⁾

DIGITAL OUTPUTS (CMOS Interface, SDOUT)

V_OH

V_OL

High-level output voltage

Low-level output voltage

DVDD – 0.1

DVDD

0

V

DIGITAL OUTPUTS (LVDS Interface)

V_ODH

V_ODL

V_OCM

High-level output differential voltage

With an external 100-Ω termination

280

–460

0.9

350

–350

1.05

–280

–460

1.2

mV

V

Low-level output differential voltage

Output common-mode voltage

(1) SEN has an internal 150-kΩ pullup resistor to AVDD. SPI pins (SEN, SCLK, SDATA) may be driven by 1.8 V or 3.3 V CMOS buffers.

(2) SYSREF is internally biased to 0.9 V.

7.13 Timing Requirements: General

typical values are at T_A= 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input (unless otherwise noted); minimum

and maximum values are across the full temperature range: T_MIN= –40°C to T_MAX= +85°C

MIN

TYP

1.44

±70

MAX

UNIT

ns

t_A

Aperture delay

1.24

1.64

Aperture delay matching between two channels of the same device

ps

Variation of aperture delay between two devices at the same temperature and

supply voltage

±150

ps

f_Srms

µs

t_J

Aperture jitter

130

35

Time to valid data after exiting standby power-

200

450

down mode

Wake-up time

Time to valid data after exiting global power-down

85

9

µs

mode (in this mode, both channels power down)

Clock

cycles

2-wire mode (default)

ADC latency⁽¹⁾

Clock

cycles

1-wire mode

8

Setup time for SYSREF referenced to input clock

falling edge

t_{SU_SYSREF}

1000

100

ps

SYSREF reference time

Hold time for SYSREF referenced to input clock

falling edge

t_{H_SYSREF}

(1) Overall latency = ADC latency + t_PDI; see Figure 141.

17

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7.14 Timing Requirements: LVDS Output

typical values are at 25°C, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 7x serialization (2-wire mode), C_LOAD

=

3.3 pF⁽¹⁾, and R_LOAD= 100 Ω⁽²⁾(unless otherwise noted); minimum and maximum values are across the full temperature

range: T_MIN= –40°C to T_MAX= +85°C⁽³⁾⁽⁴⁾

MIN

TYP

MAX

UNIT

Data setup time: data valid to zero-crossing of differential output clock

(CLKOUTP – CLKOUTM)⁽⁵⁾

t_SU

t_HO

0.36

0.42

ns

Data hold time: zero-crossing of differential output clock (CLKOUTP – CLKOUTM) to data

becoming invalid⁽⁵⁾

0.36

0.47

ns

LVDS bit clock duty cycle: duty cycle of differential clock (CLKOUTP – CLKOUTM)

49%

4.5

Clock propagation delay: input clock falling edge cross-over to frame 1-wire mode

clock rising edge cross-over 15 MSPS < sampling frequency <

2.7

6.5

ns

t_PDI

2-wire mode

125 MSPS

0.44 × t_S+ t_DELAY

t_DELAY

Delay time

3

4.5

5.9

t_FALL

t_RISE

,

Data fall time, data rise time: rise time measured from –100 mV to 100 mV,

15 MSPS ≤ Sampling frequency ≤ 125 MSPS

0.11

ns

t_CLKRISE

t_CLKFALL

,

Output clock rise time, output clock fall time: rise time measured from –100 mV to 100 mV,

15 MSPS ≤ Sampling frequency ≤ 125 MSPS

0.11

(1) C_LOADis the effective external single-ended load capacitance between each output pin and ground

(2) R_LOADis the differential load resistance between the LVDS output pair.

(3) Measurements are done with a transmission line of a 100-Ω characteristic impedance between the device and load. Setup and hold time

specifications take into account the effect of jitter on the output data and clock.

(4) Timing parameters are ensured by design and characterization and are not tested in production.

(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.

Table 1. LVDS Timings at Lower Sampling Frequencies: 7x Serialization (2-Wire Mode)

SETUP TIME

(t_SU, ns)

HOLD TIME

(t_HO, ns)

SAMPLING FREQUENCY

(MSPS)

MIN

2.27

1.44

1.2

TYP

MAX

MIN

2.41

1.51

1.24

0.97

0.72

0.53

TYP

MAX

25

40

2.6

1.6

2.6

1.7

50

1.32

1.04

0.75

0.57

1.4

60

0.95

0.68

0.5

1.09

0.81

0.62

80

100

Table 2. LVDS Timings at Lower Sampling Frequencies: 14x Serialization (1-Wire Mode)

SETUP TIME

(t_SU, ns)

HOLD TIME

(t_HO, ns)

SAMPLING FREQUENCY

(MSPS)

MIN

1.1

TYP

MAX

MIN

1.19

0.74

0.54

0.42

0.3

TYP

MAX

25

40

50

60

80

1.24

0.72

0.55

0.41

0.24

1.34

0.82

0.64

0.51

0.38

0.66

0.48

0.35

0.17

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7.15 Typical Characteristics: ADC3441

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D701

D702

SFDR = 98 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 97 dBc, HD2 = 110.0 dBc,

SFDR = 90 dBc, SNR = 73.5 dBFS, SINAD = 73.2 dBFS,

THD = 88 dBc, HD2 = 90 dBc,

HD3 = 98 dBc, SFDR = 100 dBc (excluding HD2, HD3)

HD3 = 100 dBc, SFDR = 92 dBc (excluding HD2, HD3)

Figure 1. FFT for 10-MHz Input Signal (Dither On)

Figure 2. FFT for 10-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D703

D704

SFDR = 92 dBc, SNR = 72.5 dBFS, SINAD = 72.3 dBFS,

THD = 91 dBc, HD2 = 108 dBc,

SFDR = 90 dBc, SNR = 72.9 dBFS, SINAD = 72.7 dBFS,

THD = 89 dBc, HD2 = 90 dBc,

HD3 = 92 dBc, SFDR = 101 dBc (excluding HD2, HD3)

HD3 = 101 dBc, SFDR = 93 dBc (excluding HD2, HD3)

Figure 3. FFT for 70-MHz Input Signal (Dither On)

Figure 4. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D705

D706

SFDR = 87 dBc, SNR = 71.5 dBFS, SINAD = 71.1 dBFS,

THD = 85 dBc, HD2 = 90 dBc,

SFDR = 88 dBc, SNR = 71.7 dBFS, SINAD = 71.4 dBFS,

THD = 85 dBc, HD2 = 88 dBc,

HD3 = 87 dBc, SFDR = 100 dBc (excluding HD2, HD3)

HD3 = 91 dBc, SFDR = 93 dBc (excluding HD2, HD3)

Figure 5. FFT for 170-MHz Input Signal (Dither On)

Figure 6. FFT for 170-MHz Input Signal (Dither Off)

19

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3441 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D707

D708

SFDR = 76 dBc, SNR = 69.4 dBFS, SINAD = 68.8 dBFS,

THD = 75 dBc, HD2 = 76 dBc,

SFDR = 75 dBc, SNR = 69.6 dBFS, SINAD = 68.6 dBFS,

THD = 74 dBc, HD2 = 75 dBc,

HD3 = 83 dBc, SFDR = 96 dBc (excluding HD2, HD3)

HD3 = 80 dBc, SFDR = 91 dBc (excluding HD2, HD3)

Figure 7. FFT for 270-MHz Input Signal (Dither On)

Figure 8. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D709

D710

SFDR = 68 dBc, SNR = 66.7 dBFS, SINAD = 66.5 dBFS,

THD = 92 dBc, HD2 = 68 dBc,

SFDR = 66 dBc, SNR = 66.8 dBFS, SINAD = 66.5 dBFS,

THD = 88 dBc, HD2 = 66 dBc,

HD3 = 90 dBc, SFDR = 91 dBc (excluding HD2, HD3)

HD3 = 97 dBc, SFDR = 90 dBc (excluding HD2, HD3)

Figure 9. FFT for 450-MHz Input Signal (Dither On)

Figure 10. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D710

D712

f_IN1= 46.3 MHz, f_IN2= 50.3 MHz, IMD3 = 86 dBFS,

each tone at –7 dBFS

f_IN1= 46.3 MHz, f_IN2= 50.3 MHz, IMD3 = 105 dBFS,

each tone at –36 dBFS

Figure 11. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 12. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

20

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3441 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D713

D714

f_IN1= 184.5 MHz, f_IN2= 189.5 MHz, IMD3 = 93 dBFS,

each tone at –7 dBFS

f_IN1= 184.5 MHz, f_IN2= 189.5 MHz, IMD3 = 109 dBFS,

each tone at –36 dBFS

Figure 13. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 14. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-90

-95

-80

-85

-90

-100

-105

-110

-115

-95

-100

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D715

D716

Figure 15. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 16. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

75

104

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

74

73

72

71

70

69

68

67

96

88

80

72

64

56

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D717

D718

Figure 17. Signal-to-Noise Ratio vs Input Frequency

Figure 18. Spurious-Free Dynamic Range vs

Input Frequency

21

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3441 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

75

74.5

74

180

160

140

120

100

80

75.5

74.5

73.5

72.5

71.5

70.5

69.5

68.5

280

240

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

73.5

73

72.5

72

60

40

71.5

71

40

20

0

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D719

D720

Figure 19. Performance vs Input Amplitude (30 MHz)

Figure 20. Performance vs Input Amplitude (170 MHz)

80

78

76

74

72

70

97.5

SNR

SFDR

78

76

74

72

70

68

87.5

SNR

SFDR

95

85

92.5

90

82.5

80

87.5

77.5

85

75

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D721

D722

Figure 21. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 22. Performance vs Input Common-Mode Voltage

(170 MHz)

100

74

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

96

92

88

84

80

73.7

73.4

73.1

72.8

72.5

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D723

D724

Figure 23. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (30 MHz)

Figure 24. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (30 MHz)

22

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3441 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

92

91

90

89

88

87

86

74

73.6

73.2

72.8

72.4

72

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D725

D726

Figure 25. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (30 MHz)

Figure 26. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (30 MHz)

85

120

110

100

90

78

95

SNR

SFDR

SNR

SFDR

81

77

73

69

65

61

57

76

74

72

70

68

66

64

90

85

80

75

70

65

60

80

70

60

50

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D727

D728

Figure 27. Performance vs Clock Amplitude (40 MHz)

Figure 28. Performance vs Clock Amplitude (150 MHz)

74

99

74

73.2

72.4

71.6

70.8

70

90

88

86

84

82

80

SNR

SFDR

SNR

SFDR

73.8

73.6

73.4

73.2

73

97.5

96

94.5

93

91.5

72.8

90

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D729

D730

Figure 29. Performance vs Clock Duty Cycle (30 MHz)

Figure 30. Performance vs Clock Duty Cycle (150 MHz)

23

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3441 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 25 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

1

0.6

0.2

-0.2

-0.6

-1

15

12.5

10

7.5

5

2.5

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D901

D731

Output Code (LSB)

RMS Noise = 1.33 LSBs

Figure 32. Integral Nonlinearity for 20-MHz Input

Figure 31. Idle Channel Histogram

1

0.6

0.2

-0.2

-0.6

-1

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D902

Figure 33. Differential Nonlinearity for 20-MHz Input

24

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.16 Typical Characteristics: ADC3442

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D501

D502

SFDR = 89 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 89 dBc, HD2 = 111 dBc,

SFDR = 85 dBc, SNR = 73.5 dBFS, SINAD = 73.3 dBFS,

THD = 84 dBc, HD2 = 92 dBc,

HD3 = 89 dBc, SFDR = 100 dBc (excluding HD2, HD3)

HD3 = 85 dBc, SFDR = 96 dBc (excluding HD2, HD3)

Figure 34. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

Figure 35. FFT for 10-MHz Input Signal

(Chopper On, Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D503

D504

SFDR = 86 dBc, SNR = 72.7 dBFS, SINAD = 72.5 dBFS,

THD = 85 dBc, HD2 = 92 dBc,

SFDR = 90 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 88 dBc, HD2 = 92 dBc,

HD3 = 86 dBc, SFDR = 100 dBc (excluding HD2, HD3)

HD3 = 90 dBc, SFDR = 95 dBc (excluding HD2, HD3)

Figure 36. FFT for 70-MHz Input Signal (Dither On)

Figure 37. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D505

D506

SFDR = 86 dBc, SNR = 71.6 dBFS, SINAD = 71.4 dBFS,

THD = 85 dBc, HD2 = 92 dBc,

SFDR = 90 dBc, SNR = 71.8 dBFS, SINAD = 71.6 dBFS,

THD = 87 dBc, HD2 = 90 dBc,

HD3 = 86 dBc, SFDR = 99 dBc (excluding HD2, HD3)

HD3 = 108 dBc, SFDR = 93 dBc (excluding HD2, HD3)

Figure 38. FFT for 170-MHz Input Signal (Dither On)

Figure 39. FFT for 170-MHz Input Signal (Dither Off)

25

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3442 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D507

D508

SFDR = 75 dBc, SNR = 70.3 dBFS, SINAD = 69.1 dBFS,

THD = 74 dBc, HD2 = -75 dBc,

SFDR = 75 dBc, SNR = 70.6 dBFS, SINAD = 69.6 dBFS,

THD = 73 dBc, HD2 = 75 dBc,

HD3 = 81 dBc, SFDR = 95 dBc (excluding HD2, HD3)

HD3 = 78 dBc, SFDR = 91 dBc (excluding HD2, HD3)

Figure 40. FFT for 270-MHz Input Signal (Dither On)

Figure 41. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D509

D510

SFDR = 68 dBc, SNR = 68.2 dBFS, SINAD = 68 dBFS,

THD = 86 dBc, HD2 = 68 dBc, HD3 = 87 dBc

SFDR = 68 dBc, SNR = 68.5 dBFS, SINAD = 68.3 dBFS,

THD = 86 dBc, HD2 = 68 dBc, HD3 = 90 dBc

Figure 42. FFT for 450-MHz Input Signal (Dither On)

Figure 43. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D511

D512

f_IN1= 46.3 MHz, f_IN2= 50.3 MHz, IMD3 = 102 dBFS,

each tone at –7 dBFS

f_IN1= 46.3 MHz, f_IN2= 50.3 MHz, IMD3 = 110 dBFS,

each tone at –36 dBFS

Figure 44. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 45. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

26

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3442 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

5

10

15

20

25

0

5

10

15

20

25

Frequency (MHz)

D513

D514

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 93 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 105 dBFS,

each tone at –36 dBFS

Figure 46. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 47. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-85

-90

-95

-80

-85

-90

-95

-100

-105

-110

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D515

D516

Figure 48. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 49. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

74

104

Dither_EN

Dither_DIS

73

96

72

71

70

69

68

88

80

72

64

56

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D517

D518

Figure 50. Signal-to-Noise Ratio vs Input Frequency

Figure 51. Spurious-Free Dynamic Range vs

Input Frequency

27

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3442 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

74.5

180

160

140

120

100

80

75.5

74.5

73.5

72.5

71.5

70.5

69.5

68.5

280

240

200

160

120

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

72.5

72

71.5

71

60

40

70.5

20

0

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D519

D520

Figure 52. Performance vs Input Amplitude (30 MHz)

Figure 53. Performance vs Input Amplitude (170 MHz)

80

78

76

74

72

70

95

78

76

74

72

70

68

90

SNR

SFDR

SNR

SFDR

92.5

90

87.5

85

87.5

85

82.5

80

82.5

77.5

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D521

D522

Figure 54. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 55. Performance vs Input Common-Mode Voltage

(170 MHz)

98

73.7

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

96

94

92

90

88

86

84

82

73.4

73.1

72.8

72.5

72.2

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D523

D524

Figure 56. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (30 MHz)

Figure 57. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (30 MHz)

28

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3442 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

100

96

92

88

84

80

74

73.6

73.2

72.8

72.4

72

DVDD = 1.7V

DVDD = 1.75V

DVDD = 1.8V

DVDD = 1.85V

DVDD = 1.9V

DVDD = 1.7V

DVDD = 1.75V

DVDD = 1.8V

DVDD = 1.85V

DVDD = 1.9V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D525

D526

Figure 58. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (30 MHz)

Figure 59. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (30 MHz)

79

102

81

100

95

90

85

80

75

70

65

SNR

SFDR

SNR

SFDR

78

75

72

69

66

63

60

77

75

73

71

69

96

90

84

78

72

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D528

Figure 60. Performance vs Clock Amplitude (40 MHz)

Figure 61. Performance vs Clock Amplitude (150 MHz)

74.2

94.5

72.4

90

88

86

84

82

80

SNR

SFDR

SNR

SFDR

73.8

73.4

73

93

72.2

72

91.5

90

71.8

71.6

71.4

72.6

88.5

72.2

87

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D529

D530

Figure 62. Performance vs Clock Duty Cycle (30 MHz)

Figure 63. Performance vs Clock Duty Cycle (150 MHz)

29

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3442 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

1

0.6

0.2

-0.2

-0.6

-1

20

16

12

8

4

0

D531

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D903

RMS noise = 1.3 LSBs

Figure 64. Idle Channel Histogram

Figure 65. Integral Nonlinearity for 20-MHz Input

1

0.6

0.2

-0.2

-0.6

-1

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D904

Figure 66. Differential Nonlinearity for 20-MHz Input

30

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.17 Typical Characteristics: ADC3443

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D301

D302

SFDR = 89 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 89 dBc, HD2 = 110 dBc, HD3 = 89 dBc

SFDR = 84 dBc, SNR = 73.2 dBFS, SINAD = 73.1 dBFS,

THD = 83 dBc, HD2 = 94 dBc, HD3 = 84 dBc

Figure 67. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

Figure 68. FFT for 10-MHz Input Signal

(Chopper On, Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D303

D304

SFDR = 91 dBc, SNR = 72.9 dBFS, SINAD = 72.8 dBFS,

THD = 91 dBc, HD2 = 110 dBc, HD3 = 91 dBc

SFDR = 85 dBc, SNR = 73.1 dBFS, SINAD = 72.9 dBFS,

THD = 84 dBc, HD2 = 91 dBc, HD3 = 85 dBc

Figure 69. FFT for 70-MHz Input Signal (Dither On)

Figure 70. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D305

D306

SFDR = 95 dBc, SNR = 72.1 dBFS, SINAD = 71.9 dBFS,

THD = 93 dBc, HD2 = 106 dBc, HD3 = 95 dBc

SFDR = 92 dBc, SNR = 72.4 dBFS, SINAD = 72.2 dBFS,

THD = 88 dBc, HD2 = 92 dBc, HD3 = 95 dBc

Figure 71. FFT for 170-MHz Input Signal (Dither On)

Figure 72. FFT for 170-MHz Input Signal (Dither Off)

31

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3443 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D307

D308

SFDR = 75 dBc, SNR = 70.5 dBFS, SINAD = 69.6 dBFS,

THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc

SFDR = 75 dBc, SNR = 71 dBFS, SINAD = 69.7 dBFS,

THD = 74 dBc, HD2 = 75 dBc, HD3 = 81 dBc

Figure 73. FFT for 270-MHz Input Signal (Dither On)

Figure 74. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D309

D310

SFDR = 66 dBc, SNR = 68.4 dBFS, SINAD = 64.6 dBFS,

THD = 66 dBc, HD2 = 66 dBc, HD3 = 89 dBc

SFDR = 65 dBc, SNR = 68.7 dBFS, SINAD = 64.4 dBFS,

THD = 65 dBc, HD2 = 65 dBc, HD3 = 82 dBc

Figure 75. FFT for 450-MHz Input Signal (Dither On)

Figure 76. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D311

D312

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 99 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 105 dBFS,

each tone at –36 dBFS

Figure 77. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 78. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

32

ADC3441, ADC3442, ADC3443, ADC3444

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3443 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

8

16

24

32

40

0

8

16

24

32

40

Frequency (MHz)

D313

D314

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 90 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 106 dBFS,

each tone at –36 dBFS

Figure 79. FFT FOR Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 80. FFT FOR Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-85

-90

-95

-80

-85

-90

-95

-100

-105

-110

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D315

D316

Figure 81. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 82. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

100

74.5

Dither_EN

Dither_DIS

95

73.5

90

85

80

75

70

65

60

72.5

71.5

70.5

69.5

68.5

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D317

D318

Figure 83. Signal-to-Noise Ratio vs Input Frequency

Figure 84. Spurious-Free Dynamic Range vs

Input Frequency

33

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3443 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

74.5

180

160

140

120

100

80

74.5

180

160

140

120

100

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

73.5

73

72.5

72

72.5

72

71.5

71

60

71.5

71

60

40

70.5

20

70.5

20

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D319

D320

Figure 85. Performance vs Input Amplitude (30 MHz)

Figure 86. Performance vs Input Amplitude (170 MHz)

78

92

90

88

86

84

82

78

92

90

88

86

84

82

SNR

SFDR

SNR

SFDR

76

74

72

70

68

76

74

72

70

68

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D321

D322

Figure 87. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 88. Performance vs Input Common-Mode Voltage

(170 MHz)

95

75

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

74.5

74

93

91

89

87

85

73.5

73

72.5

72

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D323

D324

Figure 89. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (170 MHz)

Figure 90. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (170 MHz)

34

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www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3443 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

100

96

92

88

84

80

74.5

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

74

73.5

73

72.5

72

71.5

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D325

D326

Figure 91. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (170 MHz)

Figure 92. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (170 MHz)

78

135

78

96

SNR

SFDR

76

74

72

70

68

66

64

93

76

74

72

70

68

120

105

90

87

84

81

75

78

60

75

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D327

D328

Figure 93. Performance vs Clock Amplitude (40 MHz)

Figure 94. Performance vs Clock Amplitude (150 MHz)

74.2

90

89

88

87

86

85

72.8

92

90

88

86

84

82

SNR

SFDR

SNR

SFDR

73.8

73.4

73

72.6

72.4

72.2

72

72.6

72.2

71.8

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D329

D330

Figure 95. Performance vs Clock Duty cycle (30 MHz)

Figure 96. Performance vs Clock Duty Cycle (150 MHz)

35

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3443 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

1

0.6

0.2

-0.2

-0.6

-1

24

22

20

18

16

14

12

10

8

6

4

2

0

D331

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D905

RMS noise = 1.28 LSBs

Figure 97. Idle Channel Histogram

Figure 98. Integral Nonlinearity for 70-MHz Input

1

0.6

0.2

-0.2

-0.6

-1

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D906

Figure 99. Differential Nonlinearity for 70-MHz Input

36

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

7.18 Typical Characteristics: ADC3444

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D101

D102

SFDR = 95 dBc, SNR = 72.7 dBFS, SINAD = 72.6 dBFS,

THD = 100 dBc, HD2 = 95 dBc, HD3 = 96 dBc

SFDR = 91.8 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 87 dBc, HD2 = 94 dBc, HD3 = 92 dBc

Figure 100. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

Figure 101. FFT for 10-MHz Input Signal

(Chopper On, Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D103

D104

SFDR = 96 dBc, SNR = 72.5 dBFS, SINAD = 72.4 dBFS,

THD = 94 dBc, HD2 = 101 dBc, HD3 = 96 dBc

SFDR = 91 dBc, SNR = 73 dBFS, SINAD = 72.8 dBFS,

THD = 87 dBc, HD2 = 91 dBc, HD3 = 95 dBc

Figure 102. FFT for 70-MHz Input Signal (Dither On)

Figure 103. FFT for 70-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D105

D106

SFDR = 86 dBc, SNR = 71.7 dBFS, SINAD = 71.6 dBFS,

THD = 93 dBc, HD2 = 86 dBc, HD3 = 99 dBc

SFDR = 85 dBc, SNR = 72.3 dBFS, SINAD = 72.1 dBFS,

THD = 87 dBc, HD2 = 97 dBc, HD3 = 85 dBc

Figure 104. FFT for 170-MHz Input Signal (Dither On)

Figure 105. FFT for 170-MHz Input Signal (Dither Off)

37

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

Typical Characteristics: ADC3444 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D107

D108

SFDR = 77 dBc, SNR = 70.4 dBFS, SINAD = 69.6 dBFS,

THD = 75 dBc, HD2 = 77 dBc, HD3 = 81 dBc

SFDR = 74 dBc, SNR = 71 dBFS, SINAD = 70.1 dBFS,

THD = 75 dBc, HD2 = 76 dBc, HD3 = 82 dBc

Figure 106. FFT for 270-MHz Input Signal (Dither On)

Figure 107. FFT for 270-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D109

D110

SFDR = 72 dBc, SNR = 68.2 dBFS, SINAD = 67.3 dBFS,

THD = 74 dBc, HD2 = 72 dBc, HD3 = 79 dBc

SFDR = 70 dBc, SNR = 68.9 dBFS, SINAD = 67.6 dBFS,

THD = 73 dBc, HD2 = 77 dBc, HD3 = 70 dBc

Figure 108. FFT for 450-MHz Input Signal (Dither On)

Figure 109. FFT for 450-MHz Input Signal (Dither Off)

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D111

D112

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 102 dBFS,

each tone at –7 dBFS

f_IN1= 46 MHz, f_IN2= 50 MHz, IMD3 = 100 dBFS,

each tone at –36 dBFS

Figure 110. FFT for Two-Tone Input Signal

(–7 dBFS at 46 MHz and 50 MHz)

Figure 111. FFT for Two-Tone Input Signal

(–36 dBFS at 46 MHz and 50 MHz)

38

ADC3441, ADC3442, ADC3443, ADC3444

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ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Characteristics: ADC3444 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

12.5

25

37.5

50

62.5

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D113

D114

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 88 dBFS,

each tone at –7 dBFS

f_IN1= 185 MHz, f_IN2= 190 MHz, IMD3 = 104 dBFS,

each tone at –36 dBFS

Figure 112. FFT for Two-Tone Input Signal

(–7 dBFS at 185 MHz and 190 MHz)

Figure 113. FFT for Two-Tone Input Signal

(–36 dBFS at 185 MHz and 190 MHz)

-85

-90

-95

-80

-85

-90

-95

-100

-105

-110

-105

-110

-35

-31

-27

-23

-19

-15

-11

-7

-35

-31

-27

-23

-19

-15

-11

-7

Each Tone Amplitude (dBFS)

D115

D116

Figure 114. Intermodulation Distortion vs Input Amplitude

(46 MHz and 50 MHz)

Figure 115. Intermodulation Distortion vs Input Amplitude

(185 MHz and 190 MHz)

74

100

Dither_EN

Dither_DIS

Dither_EN

Dither_DIS

73

95

72

71

70

69

68

90

85

80

75

70

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Frequency (MHz)

D117

D118

Figure 116. Signal-to-Noise Ratio vs Input Frequency

Figure 117. Spurious-Free Dynamic Range vs

Input Frequency

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Typical Characteristics: ADC3444 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

74.5

180

160

140

120

100

80

74

73.5

73

180

160

140

120

100

80

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

74

73.5

73

72.5

72

72.5

72

71.5

71

71.5

71

60

40

70.5

70

40

70.5

20

-70

-60

-50

-40

-30

-20

-10

0

-70

-60

-50

-40

-30

-20

-10

0

Amplitude (dBFS)

D119

D120

Figure 118. Performance vs Input Amplitude (30 MHz)

Figure 119. Performance vs Input Amplitude (170 MHz)

78

96

94

92

90

88

86

78

76

74

72

70

68

88

86

84

82

80

78

SNR

SFDR

SNR

SFDR

76

74

72

70

68

0.85

0.9

0.95

1

1.05

1.1

0.85

0.9

0.95

1

1.05

1.1

Input Common-Mode Voltage (V)

D121

D122

Figure 120. Performance vs Input Common-Mode Voltage

(30 MHz)

Figure 121. Performance vs Input Common-Mode Voltage

(170 MHz)

94

74

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

AVDD = 1.7 V

AVDD = 1.75 V

AVDD = 1.8 V

AVDD = 1.85 V

AVDD = 1.9 V

73.5

73

92

90

88

86

84

72.5

72

71.5

71

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D123

D124

Figure 122. Spurious-Free Dynamic Range vs

AVDD Supply and Temperature (170 MHz)

Figure 123. Signal-to-Noise Ratio vs

AVDD Supply and Temperature (170 MHz)

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Typical Characteristics: ADC3444 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

94

92

90

88

86

84

73.5

73.1

72.7

72.3

71.9

71.5

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

DVDD = 1.7 V

DVDD = 1.75 V

DVDD = 1.8 V

DVDD = 1.85 V

DVDD = 1.9 V

-40

-15

10

35

60

85

-40

-15

10

35

60

85

Temperature (°C)

D125

D126

Figure 124. Spurious-Free Dynamic Range vs

DVDD Supply and Temperature (170 MHz)

Figure 125. Signal-to-Noise Ratio vs

DVDD Supply and Temperature (170 MHz)

80

78

76

74

72

70

68

66

120

77

100

95

90

85

80

75

70

SNR

SFDR

SNR

SFDR

110

75

73

71

69

67

65

100

90

80

70

60

50

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

Differential Clock Amplitude (Vpp)

D127

D128

Figure 126. Performance vs Clock Amplitude (40 MHz)

Figure 127. Performance vs Clock Amplitude (150 MHz)

74.2

95

94

93

92

91

90

72.4

90

SNR

SFDR

SNR

SFDR

73.8

73.4

73

72.2

72

87.5

85

71.8

71.6

71.4

82.5

80

72.6

72.2

77.5

30

35

40

45

50

55

60

65

70

30

35

40

45

50

55

60

65

70

Input Clock Duty Cycle (%)

D129

D130

Figure 128. Performance vs Clock Duty Cycle (30 MHz)

Figure 129. Performance vs Clock Duty Cycle (150 MHz)

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Typical Characteristics: ADC3444 (continued)

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

1

0.6

0.2

-0.2

-0.6

-1

20

16

12

8

4

0

D131

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D907

RMS noise = 1.4 LSBs

Figure 130. Idle Channel Histogram

Figure 131. Integral Nonlinearity for 70-MHz Input

1

0.6

0.2

-0.2

-0.6

-1

0

2048 4096 6144 8192 10240 12288 14336 16384

Output Code (LSB)

D908

Figure 132. Differential Nonlinearity for 70-MHz Input

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7.19 Typical Characteristics: Common

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when chopper is enabled, and dither on (unless otherwise noted)

0

-10

0

-5

-20

-10

-15

-20

-25

-30

-35

-40

-45

-50

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12ꢀ5

25

37ꢀ5

50

62ꢀ5

0

50

100

150

200

250

300

Crequency (aIz)

Frequency of Signal on Supply (MHz)

D001

D006

f_IN= 30 MHz, A_IN= –1 dBFS,

test signal amplitude = 50 mV_PP

f_IN= 30.1 MHz, f_PSRR= 3 MHz, A_PSRR= 50 mV_PP

,

SINAD = 58.63 dBFS, SFDR = 61.57 dBc

Figure 133. Power-Supply Rejection Ratio vs

Test Signal Frequency

Figure 134. Power-Supply Rejection Ratio Spectrum

(Chopper On)

0

-20

-25

-30

-35

-40

-45

-50

-55

-60

-65

-70

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12ꢀ5

25

37ꢀ5

50

62ꢀ5

0

50

100

150

200

250

300

Crequency (aIz)

Frequency of Input Common-Mode Signal (MHz)

D007

D008

f_IN= 170 MHz, A_IN= –1 dBFS,

test signal amplitude = 50 mV_PP, input VCM = 0.95 V

f_IN= 170.1 MHz, f_CMRR= 5 MHz, A_CMRR= 50 mV_PP

,

SINAD = 69.66 dBFS, SFDR = 75.66 dBc

Figure 135. Common-Mode Rejection Ratio vs

Test Signal Frequency

Figure 136. Common-Mode Rejection Ratio Spectrum

400

320

Analog Power

Digital Power

Total Power

Analog Power

Digital Power

Total Power

240

360

320

280

240

200

160

120

80

280

200

160

120

80

40

5

15 25 35 45 55 65 75 85 95 105 115 125

Sampling Speed (MSPS)

10

20

30

40

50

60

70

80

Sampling Speed (MSPS)

D009

D010

Figure 137. Power vs Sampling Frequency

(Two-Wire Mode)

Figure 138. Power vs Sampling Frequency

(One-Wire Mode)

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7.20 Typical Characteristics: Contour

typical values are at T_A= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = 1.8 V, DVDD = 1.8 V, –1-

dBFS differential input, 2-V_PPfull-scale, 32k-point FFT, chopper disabled, SNR reported with a 1-MHz offset from dc when

chopper is disabled and from f_S/ 2 when is chopper enabled, and dither on (unless otherwise noted)

120

110

100

90

120

110

100

90

85

81

77

72.5

70.5

89

73

71

70

68.5

69

69.5

69

72

71.5

80

85

72.5

77

70.5

81

73

89

70

71

70

72

69

68.5

69

69.5

60

71.5

50

40

85

71.5

150

73

72.5

70.5

69.5

72

68.5

67.5

68

89

73

71

77

70

69

81

30

85

69

67

50

100

150

200

250

300

350

400

450

50

100

68

200

250

300

350

400

450

Input Frequency, MHz

70

75

80

85

67

69

70

71

72

73

Figure 139. Spurious-Free Dynamic Range (SFDR)

Figure 140. Signal-to-Noise Ratio (SNR)

8 Parameter Measurement Information

8.1 Timing Diagrams

t_A

Analog

Input

CLKIN

t_PDI

CLKIN

FCLK

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

Dx0P

10 11 12 13

t_A

Latency = 8 x CLKIN Cycles + t_PDI- t_A

CLKIN

FCLK

Dx0P

D[N-8]

D[N-7]

D[N-6]

D[N-5]

D[N-4]

D[N-3]

D[N-2]

D[N-1]

D[N]

D[N+1]

Figure 141. Latency Timing Diagram

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Timing Diagrams (continued)

DAn_P

DBn_P

Logic 0

V_ODL= -350 mV⁽¹⁾

Logic 1

V_ODH= +350 mV⁽¹⁾

DAn_M

DBn_M

V_OCM

GND

(1) With an external 100-Ω termination.

Figure 142. Serial LVDS Output Voltage Levels

CLKIN

FCLK

DCLK

1-Wire (14x Serialization)

Dx0P

Dx0M

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

D

13

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

10 11 12 13

CLKIN

FCLK

DCLK

Dx0P

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

2-Wire (7x Serialization)

Dx0M

Dx1P

Dx1M

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

SAMPLE N-1

SAMPLE N

SAMPLE N+1

Figure 143. Output Timing Diagram

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Timing Diagrams (continued)

DCLK

t _HO

Dx0P

Dx0M

t _SU

Figure 144. Setup and Hold Time

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9 Detailed Description

9.1 Overview

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS,

analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input

frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system

clock architecture design while the SYSREF input enables complete system synchronization. The ADC344x

family supports serial LVDS interface in order to reduce the number of interface lines, thus allowing for high

system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and

output over two LVDS pairs. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to

derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data

streams, the frame and bit clocks are also transmitted as LVDS outputs.

9.2 Functional Block Diagram

DA0P

DA0M

INAP

INAM

14-Bit

ADC

Digital Encoder

and Serializer

DA1P

DA1M

DB0P

DB0M

Digital Encoder

and Serializer

INBP

INBM

14-Bit

ADC

DB1P

DB1M

Bit Clock

CLKP

CLKM

Divide

by 1,2,4

DCLKP

DCLKM

PLL

Frame Clock

FCLKP

FCLKM

SYSREFP

SYSREFM

DC0P

DC0M

INCP

INCM

14-Bit

ADC

Digital Encoder

and Serializer

DC1P

DC1M

DD0P

DD0M

INDP

INDM

14-Bit

ADC

Digital Encoder

and Serializer

DD1P

DD1M

Common

Mode

Configuration

Registers

VCM

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9.3 Feature Description

9.3.1 Analog Inputs

The ADC344x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must swing

symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-V_PP(default) differential input swing.

The input sampling circuit has a 3-dB bandwidth that extends up to 540 MHz (50-Ω source driving 50-Ω

termination between INP and INM).

9.3.2 Clock Input

The device clock inputs may be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with

little or no difference in performance between them. The common-mode voltage of the clock inputs is set to

0.95 V using internal 5-kΩ resistors. The ADC344x self-bias clock inputs may be driven by the transformer-

coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in

Figure 145, Figure 146, and Figure 147. See Figure 148 for details regarding the internal clock buffer.

0.1 mF

Z_o

CLKP

Differential

Sine-Wave

Clock Input

R_T

Typical LVDS

Clock Input

100 W

0.1 mF

CLKM

Device

0.1 mF

Z_o

CLKM

NOTE: R_T= termination resistor, if necessary.

Device

Figure 145. Differential Sine-Wave Clock Driving

Circuit

Figure 146. LVDS Clock Driving Circuit

0.1 mF

Z_o

CLKP

150 W

Typical LVPECL

Clock Input

100 W

0.1 mF

Z_o

CLKM

Device

150 W

Figure 147. LVPECL Clock Driving Circuit

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Clock Buffer

L_PKG

2 nH

20 Ω

CLKP

C_BOND

1 pF

5 kΩ

C_EQ

R_ESR

100 Ω

0.95 V

C_EQ

L_PKG

2 nH

5 kΩ

20 Ω

CLKM

C_BOND

1 pF

R_ESR

100 Ω

NOTE: C_EQis 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.

Figure 148. Internal Clock Buffer

A single-ended CMOS clock may be ac-coupled to the CLKP input, with CLKM connected to ground with a

0.1-μF capacitor, as shown in Figure 149. However, for best performance the clock inputs must be driven

differentially, thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI

recommends using a clock source with low jitter. Band-pass filtering of the clock source may help reduce the

effects of jitter. There is no change in performance with a non-50% duty cycle clock input.

0.1 mF

CMOS

Clock Input

CLKP

0.1 mF

CLKM

Device

Figure 149. Single-Ended Clock Driving Circuit

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9.3.2.1 Using the SYSREF Input

The ADC344x has a SYSREF input pin that can be used when the clock-divider feature is used. A logic low-to-

high transition on the SYSREF pin aligns the falling edge of the divided clock with the next falling edge of the

input clock, essentially resetting the phase of the divided clock, as shown in Figure 150. When multiple ADC344x

devices are onboard and the clock divider option is used, the phase of the divided clock among the devices may

not be the same. The phase of the divided clock in each device can be synchronized to the common sampling

clock by using the SYSREF pins. SYSREF can applied as mono-shot or periodic waveform. When applied as

periodic waveform, its period must be integer multiple of period of the divided clock. When not used, the

SYSREFP and SYSREFM pins can be connected to AVDD and GND, respectively. Alternatively, the SYSREF

buffer inside the device can be powered down using the PDN SYSREF register bit.

TI Device

Input Clock

(CLKP-CLKM)

Clock Divider

(Divide-by-2,

-4)

Divided Clock

SYSREF

(SYSREFP-SYSREFM)

The falling edge of the input clock

and the divided clock are aligned

after a sampling low-to-high

transition on SYSREF.

SYSREF is sampled by this edge.

SYSREF

Input Clock

Divided

Clock

Figure 150. Using SYSREF for Synchronization

9.3.2.2 SNR and Clock Jitter

The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization

noise (typically 86 dB for a 14-bit ADC) and thermal noise limit SNR at low input frequencies while the clock jitter

sets SNR for higher input frequencies.

2

SNR_Quantizatoin

SNR

Jitter

Noise

≈

’

÷

Thermal Noise

≈

’

÷

≈

’

÷

-

∆

20

∆

SNR_ADC[dBc] = -20∂log 10

+ 10

∆

«

÷

◊

∆

«

÷

∆

«

÷

◊

(1)

(2)

The SNR limitation resulting from sample clock jitter may be calculated with Equation 2.

SNR_Jitter[dBc] = -20∂log(2p ∂ f_in∂T_Jitter)

The total clock jitter (T_Jitter) has two components: the internal aperture jitter (130 fs for the device) which is set by

the noise of the clock input buffer and the external clock. T_Jittermay be calculated with Equation 3.

2

T_Jitter= (T_{Jitter,Ext.Clock _ Input})²+(T_{Aperture_ ADC}

)

(3)

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External clock jitter may be minimized by using high-quality clock sources and jitter cleaners as well as band-

pass filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a

typical thermal noise of 72.7 dBFS and internal aperture jitter of 130 fs. The SNR, depending on the amount of

external jitter for different input frequencies, is shown in Figure 151.

73.0

Ext Clock Jitter

72.5

35 fs

72.0

71.5

71.0

70.5

70.0

69.5

69.0

68.5

68.0

67.5

67.0

50 fs

100 fs

150 fs

200 fs

10

100

1000

Input Frequency (MHz)

D03061

Figure 151. SNR vs Frequency for Different Clock Jitter

9.3.3 Digital Output Interface

The devices offer two different output format options, thus making interfacing to a field-programmable gate array

(FPGA) or an application-specific integrated circuit (ASIC) easy. Each option may be easily programmed using

the serial interface, as shown in Table 3. The output interface options are:

•

One-wire, 1x frame clock, 14x serialization with the DDR bit clock

Two-wire, 1x frame clock, 7x serialization with the DDR bit clock.

Table 3. Interface Rates

RECOMMENDED SAMPLING

FREQUENCY (MSPS)

BIT CLOCK

FREQUENCY

(MHz)

FRAME CLOCK

FREQUENCY

(MHz)

INTERFACE

OPTIONS

SERIAL DATA

RATE (Mbps)

SERIALIZATION

MINIMUM

15⁽¹⁾

—

MAXIMUM

—

80

105

560

15

80

210

1120

140

1-wire

14x

7x

20⁽¹⁾

—

70

10

2-wire (default

after reset)

—

125

437.5

62.5

875

(1) Use the LOW SPEED ENABLE register bits for low speed operation; see Table 20.

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9.3.3.1 One-Wire Interface: 14x Serialization

In this interface option, the device outputs the data of each ADC serially on a single LVDS pair (one-wire). The

data are available at the rising and falling edges of the bit clock (DDR bit clock). The ADC outputs a new word at

the rising edge of every frame clock, starting with the LSB. The data rate is 14x sample frequency (14x

serialization).

9.3.3.2 Two-Wire Interface: 7x Serialization

The two-wire interface is recommended for sampling frequencies above 65 MSPS. The output data rate is 7x

sample frequency because seven data bits are output every clock cycle on each differential pair. Each ADC

sample is sent over the two wires with the seven MSBs on Dx1P, Dx1M and the seven LSBs on Dx0P, Dx0M, as

shown in Figure 152.

CLKIN

FCLK

DCLK

1-Wire (14x Serialization)

Dx0P

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

D

13

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

0

10 11 12 13

Dx0M

CLKIN

FCLK

DCLK

Dx0P

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

2-Wire (7x Serialization)

Dx0M

Dx1P

Dx1M

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

D

8

D

9

D

10

D

11

D

12

D

13

D

7

SAMPLE N-1

SAMPLE N

SAMPLE N+1

Figure 152. Output Timing Diagram

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9.4 Device Functional Modes

9.4.1 Input Clock Divider

The devices are equipped with an internal divider on the clock input. The clock divider allows operation with a

faster input clock, thus simplifying the system clock distribution design. The clock divider may be bypassed for

operation with a 125-MHz clock while the divide-by-2 option supports a maximum input clock of 250 MHz and the

divide-by-4 option provides a maximum input clock frequency of 500 MHz.

9.4.2 Chopper Functionality

The devices are equipped with an internal chopper front-end. Enabling the chopper function swaps the ADC

noise spectrum by shifting the 1/f noise from dc to f_S/ 2. Figure 153 shows the noise spectrum with the chopper

off and Figure 154 shows the noise spectrum with the chopper on. This function is especially useful in

applications requiring good ac performance at low input frequencies or in dc-coupled applications. The chopper

may be enabled through SPI register writes and is recommended for input frequencies below 30 MHz. The

chopper function creates a spur at f_S/ 2 that must be filtered out digitally.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

10

20

30

40

50

60

0

10

20

30

40

50

60

Frequency (MHz)

D016

D017

f_S= 125 MSPS, SNR = 72.7 dBFS,

f_IN= 10 MHz, SFDR = 94 dBc

f_S= 125 MSPS, SNR = 72.7 dBFS,

f_IN= 10 MHz, SFDR = 94 dBc

Figure 153. Chopper Off

Figure 154. Chopper On

9.4.3 Power-Down Control

The ADC344x power-down functions may be controlled either through the parallel control pin (PDN) or through

an SPI register setting (see register 15h). The PDN pin may also be configured through SPI to a global power-

down or standby functionality, as shown in Table 4.

Table 4. Power-Down Modes

FUNCTION

Global power-down

Standby

POWER CONSUMPTION (mW)

WAKE-UP TIME (µs)

5

85

35

45

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9.4.4 Internal Dither Algorithm

The ADC344x family uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the

dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither

algorithm may be turned off by using the DIS DITH CHx registers bits. Figure 155 and Figure 156 show the effect

of using dither algorithms.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

0

2.5

5

7.5

10

12.5

0

2.5

5

7.5

10

12.5

Frequency (MHz)

D701

D702

SFDR = 98 dBc, SNR = 73.1 dBFS, SINAD = 73 dBFS,

THD = 97 dBc, HD2 = 110.0 dBc,

SFDR = 90 dBc, SNR = 73.5 dBFS, SINAD = 73.2 dBFS,

THD = 88 dBc, HD2 = 90 dBc,

HD3 = 98 dBc, SFDR = 100 dBc (excluding HD2, HD3)

HD3 = 100 dBc, SFDR = 92 dBc (excluding HD2, HD3)

Figure 155. FFT for 10-MHz Input Signal (Dither On)

Figure 156. FFT for 10-MHz Input Signal (Dither Off)

9.4.5 Summary of Performance Mode Registers

Table 5 lists the location, value, and functions of performance mode registers in the device.

Table 5. Performance Modes

MODE

LOCATION

FUNCTION

Special modes

Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3)

Always write 1 for best performance.

Registers 1 (bits 7-0), 134 (bits 5 and 3), 234 (bits 5 and 3),

434 (bits 5 and 3), and 534 (bits 5 and 3)

Disable dither

Disables the dither to improve SNR.

Disable chopper Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1)

Disables the chopper (shifts the 1/f noise floor at dc).

Improves HD3 by a couple of dB for IF > 100 MHz

Registers 11Dh (bit 1), 21Dh (bit 1), 41Dh (bit 1), 51Dh (bit 1),

High IF modes

308h (bits 7-6) and 608h (bits 7-6)

9.5 Programming

The ADC344x device may be configured using a serial programming interface, as described in this section.

9.5.1 Serial Interface

The device has a set of internal registers that may be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data

output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at

every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th

SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are

ignored. Data may be loaded in multiples of 24-bit words within a single active SEN pulse. The interface may

function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%

SCLK duty cycle.

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Programming (continued)

9.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin (of durations greater than 10 ns), as shown in Figure 157. If required,

the serial interface registers may be cleared during operation either:

1. Through a hardware reset, or

2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)

to high. This setting initializes the internal registers to the default values and then self-resets the RESET bit

low. In this case, the RESET pin is kept low.

9.5.1.1.1 Serial Register Write

The device internal register may be programmed with these steps:

1. Drive the SEN pin low,

2. Set the R/W bit to 0 (bit A15 of the 16-bit address),

3. Set bit A14 in the address field to 1,

4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be

written, and

5. Write the 8-bit data that are latched in on the SCLK rising edge.

Figure 157 and Table 6 show the timing requirements for the serial register write operation.

Register Address [13:0]

A13 A12 A11 A1

Register Data [7:0]

SDATA

R/W

= 0

1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 157. Serial Register Write Timing Diagram

Table 6. Serial Interface Timing⁽¹⁾

MIN

> DC

25

TYP

MAX

UNIT

MHz

ns

f_SCLK

t_SLOADS

t_SLOADH

t_DSU

SCLK frequency (equal to 1 / t_SCLK

SEN to SCLK setup time

SCLK to SEN hold time

SDIO setup time

)

20

25

ns

25

ns

t_DH

SDIO hold time

25

ns

(1) Typical values are at 25°C, full temperature range is from T_MIN= –40°C to T_MAX= 85°C, and AVDD = DVDD = 1.8 V, unless otherwise

noted.

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9.5.1.1.2 Serial Register Readout

The device includes a mode where the contents of the internal registers may be read back using the SDOUT pin.

This readback mode may be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low.

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.

3. Set bit A14 in the address field to 1.

4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.

5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.

6. The external controller may latch the contents at the SCLK rising edge.

7. To enable register writes, reset the R/W register bit to 0.

When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the

SDOUT pin must float. Figure 158 shows a timing diagram of the serial register read operation. Data appear on

the SDOUT pin at the SCLK falling edge with an approximate delay (t_{SD_DELAY}) of 20 ns, as shown in Figure 159.

Register Address [13:0]

A13 A12 A11 A1

Register Data: Don‘t Care

D5 D4 D3 D2

SDATA

R/W

= 1

A0

D7

D6

D1

D0

1

Register Read Data [7:0]

SDOUT

SCLK

D5

D4

D3

D2

SEN

Figure 158. Serial Register Read Timing Diagram

SCLK

t_{SD_DELAY}

SDOUT

Figure 159. SDOUT Timing Diagram

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9.5.2 ADC3441 Power-Up Requirements

Power-up begins with the application of AVDD and DVDD. The exact sequencing and ramp rate of AVDD and

DVDD are not important as long as the parameters in Table 7 are met.

After power-up, the RESET pin must be pulsed high to reset the internal registers to the default values.

Figure 160 and Table 7 show a power-up sequence.

During operation, the device registers can be restored to the default values by either pulsing the RESET pin high

or by issuing a software reset via the SPI interface. A software reset can be issued by writing bit 0 of register 06h

high. This bit is self-clearing.

t₃

t₁

!ë55

t₂

5ë55

t₄

t₅

t₆

w9{9Ç

{9b

5evice ready for

register readꢀꢁrite

Lnternal pull-up to !ë55

ëalid

conversions

t₇

t₈

/[Y frequency has staꢂilized

/[Y

Figure 160. Power-Up Timing

Table 7. Power-Up Timing Table

MIN

NOM

MAX

10

UNIT

ms

ns

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

AVDD supply power-up ramp time

DVDD supply power-up ramp time

AVDD to DVDD power-up delay

10

-10

1

10

Device power-up to RESET assertion

RESET assertion duration

10

RESET deassertion to SEN assertion

RESET deassertion to valid conversions

CLK stable frequency to valid conversions

10

µs

150

µs

After the power supplies are valid, enable the sample clock. The sampling clock can be enabled before or after

reset, but conversions are not valid until at least a minimum time after reset and the time that the sample clock

reaches a stable frequency, as shown in Table 7.

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Before using samples from the device, a minimum register write sequence must be applied, as described in

Table 8. Apply this register write sequence after any further application of the hardware or software reset.

Table 8. Required Register Writes after Power-up or Reset

ADDRESS

139h

439h

539h

239h

137h

437h

537h

237h

137h

437h

537h

237h

DATA

08h

40h

00h

NOTE

Channel A - best performance default

Channel B - best performance default

Channel C - best performance default

Channel D - best performance default

ADC core latch reset

These register writes configure the optimal settings for ADC performance and apply a reset to the internal latches

inside the ADC core that are not part of the device reset function. After the register writes of Table 8 are written,

any use-case-specific registers must be applied before using the conversion values.

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9.6 Register Maps

Table 9. Register Map Summary

REGISTER

REGISTER DATA

ADDRESS,

A[13:0] (Hex)

7

6

5

4

3

2

1

0

Register 01h

Register 03h

Register 04h

Register 05h

DIS DITH CHA

DIS DITH CHB

DIS DITH CHC

DIS DITH CHD

0

ODD EVEN

FLIP WIRE

1W-2W

TEST

PATTERN EN

Register 06h

Register 07h

Register 09h

0

RESET

0

OVR ON LSB

ALIGN TEST

PATTERN

DATA

FORMAT

Register 0Ah

Register 0Bh

Register 13h

Register 0Eh

Register 0Fh

CHA TEST PATTERN

CHC TEST PATTERN

CHB TEST PATTERN

CHD TEST PATTERN

0

LOW SPEED ENABLE

CUSTOM PATTERN[13:6]

CUSTOM PATTERN[5:0]

0

CONFIG PDN

Register 15h

CHA PDN

CHB PDN

CHC PDN

CHD PDN

STANDBY

GLOBAL PDN

Register 25h

Register 27h

LVDS SWING

CLK DIV

0

HIGH IF

MODE0

Register 11Dh

Register 122h

0

DIS CHOP

CHA

0

Register 134h

Register 139h

0

DIS DITH CHA

0

DIS DITH CHA

SP1 CHA

0

HIGH IF

MODE1

Register 21Dh

Register 222h

0

DIS CHOP

CHD

Register 234h

Register 239h

Register 308

0

DIS DITH CHD

0

DIS DITH CHD

0

SP1 CHD

0

HIGH IF MODE <5:4>

HIGH IF

MODE2

Register 41Dh

Register 422h

0

DIS CHOP

CHB

Register 434h

Register 439h

0

DIS DITH CHB

0

DIS DITH CHB

SP1 CHB

0

HIGH IF

MODE3

Register 51Dh

Register 522h

0

DIS CHOP

CHC

Register 534h

Register 539h

Register 608h

Register 70Ah

0

DIS DITH CHC

0

DIS DITH CHC

0

SP1 CHC

0

HIGH IF MODE <7:6>

0

PDN SYSREF

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9.6.1 Serial Register Description

9.6.1.1 Register 01h (address = 01h)

Figure 161. Register 01h

7

6

5

4

3

2

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHB

R/W-0h

DIS DITH CHC

R/W-0h

DIS DITH CHD

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 10. Register 01h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

DIS DITH CHA

R/W

0h

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 134h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

5-4

3-2

1-0

DIS DITH CHB

DIS DITH CHC

DIS DITH CHD

R/W

0h

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 434h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 534h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

These bits enable or disable the on-chip dither. Control this bit

along with bits 5 and 3 of register 234h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

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9.6.1.2 Register 03h (address = 03h)

Figure 162. Register 03h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ODD EVEN

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 11. Register 03h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

ODD EVEN

R/W

0h

This bit selects the bit sequence on the output wires (in 2-wire mode only).

0 = Bits 0, 1, 2, and so forth appear on wire-0; bits 7, 8, 9, and so forth appear

on wire-1.

1 = Bits 0, 2, 4, and so forth appear on wire-0; bits 1, 3, 5, and so forth appear

on wire-1.

9.6.1.3 Register 04h (address = 04h)

Figure 163. Register 04h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

FLIP WIRE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 12. Register 04h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

FLIP WIRE

R/W

0h

This bit flips the data on the output wires. Valid only in two wire

configuration.

0 = Default

1 = Data on output wires is flipped. Pin D0x becomes D1x, and

vice versa.

9.6.1.4 Register 05h (address = 05h)

Figure 164. Register 05h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1W-2W

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 13. Register 05h Field Descriptions

Bit

7-1

0

Field

0

Type

W

Reset

0h

Description

Must write 0.

1W-2W

R/W

0h

This bit transmits output data on either one or two wires.

0 = Output data are transmitted on two wires (Dx0P, Dx0M and

Dx1P, Dx1M)

1 = Output data are transmitted on one wire (Dx0P, Dx0M). In

this mode, the recommended f_Sis less than 80 MSPS.

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9.6.1.5 Register 06h (address = 06h)

Figure 165. Register 06h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TEST PATTERN EN

R/W-0h

RESET

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 14. Register 06h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

TEST PATTERN EN

R/W

0h

Enables test pattern selection for the digital outputs.

0 = Normal output

1 = Test pattern output enabled

0

RESET

R/W

0h

Software reset applied.

This bit resets all internal registers to the default values and self-

clears to 0.

9.6.1.6 Register 07h (address = 07h)

Figure 166. Register 07h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OVR ON LSB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 15. Register 07h Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

OVR ON LSB

R/W

0h

OVR information on the LSB bits.

0 = Output data bit 0 functions as the LSB of the 14-bit data

1 = Output data bit 0 carries the overrange (OVR) information.

9.6.1.7 Register 09h (address = 09h)

Figure 167. Register 09h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ALIGN TEST PATTERN

R/W-0h

DATA FORMAT

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 16. Register 09h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

ALIGN TEST PATTERN

R/W

0h

This bit aligns the test patterns across the outputs of both

channels.

0 = Test patterns of both channels are free running

1 = Test patterns of both channels are aligned

0

DATA FORMAT

R/W

0h

Digital output data format.

0 = Twos complement

1 = Offset binary

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9.6.1.8 Register 0Ah (address = 0Ah)

Figure 168. Register 0Ah

7

6

5

4

3

2

1

0

CHA TEST PATTERN

R/W-0h

CHB TEST PATTERN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 17. Register 0Ah Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CHA TEST PATTERN

R/W

0h

These bits control the test pattern for channel A after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, 2399.

Others = Do not use

3-0

CHB TEST PATTERN

R/W

0h

These bits control the test pattern for channel B after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, 2399.

Others = Do not use

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9.6.1.9 Register 0Bh (address = 0Bh)

Figure 169. Register 0Bh

7

6

5

4

3

2

1

0

CHC TEST PATTERN

R/W-0h

CHD TEST PATTERN

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 18. Register 0Bh Field Descriptions

Bit

Field

Type

Reset

Description

7-4

CHC TEST PATTERN

R/W

0h

These bits control the test pattern for channel C after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, 2399.

Others = Do not use

3-0

CHD TEST PATTERN

R/W

0h

These bits control the test pattern for channel D after the TEST

PATTERN EN bit is set.

0000 = Normal operation

0001 = All 0's

0010 = All 1's

0011 = Toggle pattern: data alternate between 10101010101010

and 01010101010101

0100 = Digital ramp: data increment by 1 LSB every clock cycle

from code 0 to 16383

0101 = Custom pattern: output data are the same as

programmed by the CUSTOM PATTERN register bits

0110 = Deskew pattern: data are 2AAAh

1000 = PRBS pattern: data are a sequence of pseudo random

numbers

1001 = 8-point sine-wave: data are a repetitive sequence of the

following eight numbers that form a sine-wave: 0, 2399, 8192,

13984, 16383, 13984, 8192, 2399.

Others = Do not use

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9.6.1.10 Register 13h (address = 13h)

Figure 170. Register 13h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

LOW SPEED ENABLE

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 19. Register 13h Field Descriptions

Bit

7-2

1-0

Field

Type

W

Reset

0h

Description

0

Must write 0.

LOW SPEED ENABLE

R/W

0h

Enables low speed operation in 1-wire and 2-wire mode.

Depending upon sampling frequency, write this bit as per

Table 20.

Table 20. LOW SPEED ENABLE Register Settings Across f_S

f_S, MSPS

REGISTER BIT LOW SPEED ENABLE

MIN

25

MAX

125

25

1-WIRE MODE

2-WIRE MODE

00

10

00

10

20

15

20

Not supported

9.6.1.11 Register 0Eh (address = 0Eh)

Figure 171. Register 0Eh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[13:6]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 21. Register 0Eh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CUSTOM PATTERN[13:6]

R/W

0h

These bits set the 14-bit custom pattern (bits 13-6) for all

channels.

9.6.1.12 Register 0Fh (address = 0Fh)

Figure 172. Register 0Fh

7

6

5

4

3

2

1

0

CUSTOM PATTERN[5:0]

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 22. Register 0Fh Field Descriptions

Bit

Field

Type

Reset

Description

7-2

CUSTOM PATTERN[5:0]

R/W

0h

These bits set the 14-bit custom pattern (bits 5-0) for all

channels.

1-0

0

W

0h

Must write 0.

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9.6.1.13 Register 15h (address = 15h)

Figure 173. Register 15h

7

6

5

4

3

2

1

0

CONFIG PDN

CHA PDN

W-0h

CHB PDN

R/W-0h

CHC PDN

R/W-0h

CHD PDN

W-0h

STANDBY

R/W-0h

GLOBAL PDN

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 23. Register 15h Field Descriptions

Bit

Field

Type

Reset

Description

7

CHA PDN

W

0h

0 = Normal operation

1 = Power-down channel A

6

5

4

3

CHB PDN

CHC PDN

CHD PDN

STANDBY

R/W

W

0h

0 = Normal operation

1 = Power-down channel B

0 = Normal operation

1 = Power-down channel C

0 = Normal operation

1 = Power-down channel D

R/W

ADCs of both channels enter standby.

0 = Normal operation

1 = Standby

2

GLOBAL PDN

R/W

0h

0 = Normal operation

1 = Global power-down

1

0

W

0h

Must write 0.

CONFIG PDN PIN

R/W

This bit configures the PDN pin as either a global power-down or

standby pin.

0 = Logic high voltage on PDN pin sends the device into global

power-down

1 = Logic high voltage on PDN pin sends the device into

standby

9.6.1.14 Register 25h (address = 25h)

Figure 174. Register 25h

7

6

5

4

3

2

1

0

LVDS SWING

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 24. Register 25h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

LVDS SWING

R/W

0h

These bits control the swing of the LVDS outputs (including the

data output, bit clock, and frame clock).

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9.6.1.15 Register 27h (address = 27h)

Figure 175. Register 27h

7

6

5

0

4

0

3

0

2

0

1

0

CLK DIV

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 25. Register 27h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

CLK DIV

R/W

0h

Internal clock divider for the input sampling clock.

00 = Divide-by-1

01 = Divide-by-1

10 = Divide-by-2

11 = Divide-by-4

5-0

0

W

0h

Must write 0.

9.6.1.16 Register 11Dh (address = 11Dh)

Figure 176. Register 11Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE0

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 26. Register 11Dh Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

0

W

0h

Must write 0.

HIGH IF MODE0

Set the HIGH IF MODE[7:0] bits together to 1111.

Improves HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

9.6.1.17 Register 122h (address = 122h)

Figure 177. Register 122h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 27. Register 122h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHA

R/W

0h

Disables the chopper.

Set this bit to shift 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc

0

W

0h

Must write 0.

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9.6.1.18 Register 134h (address = 134h)

Figure 178. Register 134h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHA

R/W-0h

DIS DITH CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 28. Register 134h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHA

R/W

0h

Set this bit with bits 7 and 6 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHA

R/W

Set this bit with bits 7 and 6 of register 01h.

00 = Default

11 = Dither is disabled for channel A. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

9.6.1.19 Register 139h (address = 139h)

Figure 179. Register 139h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHA

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 29. Register 139h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHA

R/W

0h

Special mode for best performance on channel A.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

9.6.1.20 Register 21Dh (address = 21Dh)

Figure 180. Register 21Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE1

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 30. Register 21Dh Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

0

W

0h

Must write 0.

HIGH IF MODE1

Set the HIGH IF MODE[7:0] bits together to 1111.

Improves HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

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9.6.1.21 Register 222h (address = 222h)

Figure 181. Register 222h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHD

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 31. Register 222h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHD

R/W

0h

Disables the chopper.

Set this bit to shift 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc

0

W

0h

Must write 0.

9.6.1.22 Register 234h (address = 234h)

Figure 182. Register 234h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHD

R/W-0h

DIS DITH CHD

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 32. Register 234h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHD

R/W

0h

Set this bit with bits 1 and 0 of register 01h.

00 = Default

11 = Dither is disabled for channel D. In this mode, SNR

typically improves by 0.5 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHD

R/W

Set this bit with bits 1 and 0 of register 01h.

00 = Default

11 = Dither is disabled for channel D. In this mode, SNR

typically improves by 0.5 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

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9.6.1.23 Register 239h (address = 239h)

Figure 183. Register 239h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHD

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 33. Register 239h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHD

R/W

0h

Special mode for best performance on channel D.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

9.6.1.24 Register 308h (address = 308h)

Figure 184. Register 308h

7

6

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE<5:4>

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 34. Register 308h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

HIGH IF MODE<5:4>

W

0h

Set the HIGH IF MODE[7:0] bits together to FFh.

Improves HD3 by a couple of dB for IF > 100 MHz.

5-0

0

W

0h

Must write 0.

9.6.1.25 Register 41Dh (address = 41Dh)

Figure 185. Register 41Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE2

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 35. Register 41Dh Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

0

W

0h

Must write 0.

HIGH IF MODE2

Set the HIGH IF MODE[7:0] bits together to FFh.

Improves HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

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9.6.1.26 Register 422h (address = 422h)

Figure 186. Register 422h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 36. Register 422h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHB

R/W

0h

Disables the chopper.

Set this bit to shift 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc

0

W

0h

Must write 0.

9.6.1.27 Register 434h (address = 434h)

Figure 187. Register 434h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHB

R/W-0h

DIS DITH CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 37. Register 434h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHB

R/W

0h

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHB

R/W

Set this bit with bits 5 and 4 of register 01h.

00 = Default

11 = Dither is disabled for channel B. In this mode, SNR typically

improves by 0.5 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

9.6.1.28 Register 439h (address = 439h)

Figure 188. Register 439h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHB

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 38. Register 439h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHB

R/W

0h

Special mode for best performance on channel B.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

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9.6.1.29 Register 51Dh (address = 51Dh)

Figure 189. Register 51Dh

7

0

6

0

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE3

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 39. Register 51Dh Field Descriptions

Bit

7-2

1

Field

Type

Reset

Description

0

W

0h

Must write 0.

HIGH IF MODE3

Set the HIGH IF MODE[7:0] bits together to FFh.

Improves HD3 by a couple of dB for IF > 100 MHz.

0

W

0h

Must write 0.

9.6.1.30 Register 522h (address = 522h)

Figure 190. Register 522h

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DIS CHOP CHC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 40. Register 522h Field Descriptions

Bit

7-2

1

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS CHOP CHC

R/W

0h

Disables the chopper.

Set this bit to shift 1/f noise floor at dc.

0 = 1/f noise floor is centered at f_S/ 2 (default)

1 = Chopper mechanism is disabled; 1/f noise floor is centered at dc

0

W

0h

Must write 0.

9.6.1.31 Register 534h (address = 534h)

Figure 191. Register 534h

7

0

6

0

5

4

0

3

2

0

1

0

DIS DITH CHC

R/W-0h

DIS DITH CHC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 41. Register 534h Field Descriptions

Bit

7-6

5

Field

Type

W

Reset

0h

Description

0

Must write 0.

DIS DITH CHC

R/W

0h

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel C. In this mode, SNR

typically improves by 0.5 dB at 70 MHz.

4

3

0

W

0h

Must write 0.

DIS DITH CHC

R/W

Set this bit with bits 3 and 2 of register 01h.

00 = Default

11 = Dither is disabled for channel C. In this mode, SNR

typically improves by 0.5 dB at 70 MHz.

2-0

0

W

0h

Must write 0.

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9.6.1.32 Register 539h (address = 539h)

Figure 192. Register 539h

7

0

6

0

5

0

4

0

3

2

0

1

0

SP1 CHC

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 42. Register 539h Field Descriptions

Bit

7-4

3

Field

0

Type

W

Reset

0h

Description

Must write 0.

SP1 CHC

R/W

0h

Special mode for best performance on channel C.

Always write 1 after reset.

2-0

0

W

0h

Must write 0.

9.6.1.33 Register 608h (address = 608h)

Figure 193. Register 608h

7

6

5

0

4

0

3

0

2

0

1

0

HIGH IF MODE<7:6>

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 43. Register 608h Field Descriptions

Bit

Field

Type

Reset

Description

7-6

HIGH IF MODE<7:6>

Set the HIGH IF MODE[7:0] bits together to FFh.

Improves HD3 by a couple of dB for IF > 100 MHz.

5-0

0

W

0h

Must write 0.

9.6.1.34 Register 70Ah (address = 70Ah)

Figure 194. Register 70Ah

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PDN SYSREF

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 44. Register 70Ah Field Descriptions

Bit

7-1

0

Field

Type

W

Reset

0h

Description

0

Must write 0.

PDN SYSREF

R/W

0h

If the SYSREF pins are not used in the system, the SYSREF

buffer must be powered down by setting this bit.

0 = Normal operation

1 = Powers down the SYSREF buffer

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as

ADT1-1WT or WBC1-1) may be used up to 250 MHz to achieve good phase and amplitude balances at ADC

inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 195 and

Figure 196 show the impedance (Z_in= R_in|| C_in) across the ADC input pins.

10

6

5

4

3

2

1

0.1

0.01

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

0

100 200 300 400 500 600 700 800 900 1000

Frequency (MHz)

D024

D00215

Figure 195. Differential Input Resistance, R_IN

Figure 196. Differential Input Capacitance, C_IN

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10.2 Typical Applications

10.2.1 Driving Circuit Design: Low Input Frequencies

39 nH

0.1 mF

INP

0.1 mF

50 Ω

25 Ω

0.1 mF

22 pF

50 Ω

INM

1:1

0.1 mF

39 nH

VCM

Device

Figure 197. Driving Circuit for Low Input Frequencies

10.2.1.1 Design Requirements

For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in

series with each input pin may be kept to damp out ringing caused by package parasitic. The drive circuit may

have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and

closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched

impedance to the source.

10.2.1.2 Detailed Design Procedure

A typical application involving using two back-to-back coupled transformers is shown in Figure 197. The circuit is

optimized for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used

with the series inductor (39 nH), this combination helps absorb the sampling glitches. To improve phase and

amplitude balance of first transformer, the termination resistors can be split between two transformers. For

example, 25-Ω to 25-Ω termination across the secondary winding of the second transformer can be changed to

50-Ω to 50-Ω termination and another 50-Ω to 50-Ω resistor can be placed inside the dashed box between the

transformers in Figure 197.

10.2.1.3 Application Curve

Figure 198 shows the performance obtained by using the circuit shown in Figure 197.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D101

SFDR = 95 dBc, SNR = 72.7 dBFS, SINAD = 72.6 dBFS,

THD = 100 dBc, HD2 = 95 dBc, HD3 = 96 dBc

Figure 198. FFT for 10-MHz Input Signal

(Chopper On, Dither On)

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Typical Applications (continued)

10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz

0.1 mF

10 Ω

INP

0.1 mF

15 Ω

25 Ω

0.1 mF

56 nH

10 pF

25 Ω

15 Ω

INM

10 Ω

1:1

0.1 mF

VCM

Device

Figure 199. Driving Circuit for Mid-Range Input Frequencies (100 MHz < f_IN< 230 MHz)

10.2.2.1 Design Requirements

See the Design Requirements section for further details.

10.2.2.2 Detailed Design Procedure

When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit may be used to optimize

performance, as shown in Figure 199.

10.2.2.3 Application Curve

Figure 200 shows the performance obtained by using the circuit shown in Figure 199.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D105

SFDR = 86 dBc, SNR = 71.7 dBFS, SINAD = 71.6 dBFS,

THD = 93 dBc, HD2 = 86 dBc, HD3 = 99 dBc

Figure 200. FFT for 170-MHz Input Signal (Chopper Off, Dither On)

76

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

Typical Applications (continued)

10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz

0.1 mF

10 Ω

INP

25 Ω

0.1 mF

25 Ω

INM

1:1

10 Ω

0.1 mF

VCM

Device

Figure 201. Driving Circuit for High Input Frequencies (f_IN> 230 MHz)

10.2.3.1 Design Requirements

See the Design Requirements section for further details.

10.2.3.2 Detailed Design Procedure

For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant

improvement in performance. However, a series resistance of 10 Ω may be used as shown in Figure 201.

10.2.3.3 Application Curve

Figure 202 shows the performance obtained by using the circuit shown in Figure 201.

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

0

12.5

25

37.5

50

62.5

Frequency (MHz)

D109

SFDR = 72 dBc, SNR = 68.2 dBFS, SINAD = 67.3 dBFS,

THD = 74 dBc, HD2 = 72 dBc, HD3 = 79 dBc

Figure 202. FFT for 450-MHz Input Signal (Chopper Off, Dither On)

11 Power Supply Recommendations

The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply

requirements during device power-up. AVDD and DVDD may power up in any order. See Figure 160 for other

power-up requirements.

77

ADC3441, ADC3442, ADC3443, ADC3444

ZHCSE80B –JULY 2014–REVISED APRIL 2017

www.ti.com.cn

12 Layout

12.1 Layout Guidelines

The ADC344x EVM layout may be used as a reference layout to obtain the best performance. A layout diagram

of the EVM top layer is provided in Figure 203. Some important points to remember during laying out the board

are:

1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the

package level. To minimize crosstalk onboard, the analog inputs must exit the pin out in opposite directions,

as shown in the reference layout of Figure 203 as much as possible.

2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to

minimize coupling between them. This configuration is also maintained on the reference layout of Figure 203

as much as possible.

3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, the digital

output traces must not be kept parallel to the analog input traces because this configuration may result in

coupling from digital outputs to analog inputs and degrade performance. All digital output traces to the

receiver [such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)]

must be matched in length to avoid skew among outputs.

4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A

separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF

capacitors may be kept close to the supply source.

12.2 Layout Example

{ampling

/lock

wouting

!nalog

Lnput

wouting

!5/34xx

5igital

hutput

wouting

Figure 203. Typical Layout of the ADC344x Board

78

ADC3441, ADC3442, ADC3443, ADC3444

www.ti.com.cn

ZHCSE80B –JULY 2014–REVISED APRIL 2017

13 器件和文档支持

13.1 相关链接

下面的表格列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件，并且可通过快速访问立刻订

购。

表 45. 相关链接

器件

产品文件夹

请单击此处

立即订购

请单击此处

技术文档

请单击此处

工具与软件

请单击此处

支持与社区

请单击此处

ADC3441

ADC3442

ADC3443

ADC3444

13.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

13.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

13.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

13.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

79

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC3441IRTQR

ADC3442IRTQR

ADC3443IRTQR

ADC3444IRTQR

QFN

RTQ

56

2000

330.0

16.4

8.3

2.25

12.0

16.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC3441IRTQR

ADC3442IRTQR

ADC3443IRTQR

ADC3444IRTQR

QFN

RTQ

56

2000

350.0

43.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

RTQ 56

8 x 8, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224653/A

www.ti.com

PACKAGE OUTLINE

RTQ0056C

VQFN - 1 mm max height

S

C

A

L

E

1

.

5

0

PLASTIC QUAD FLATPACK - NO LEAD

8.15

7.85

A

B

PIN 1 INDEX AREA

8.15

7.85

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

2X 6.5

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

28

15

14

29

SYMM

57

2X 6.5

6.6 0.1

1

42

52X 0.5

PIN 1 ID

0.30

0.18

56

43

56X

0.5

0.3

0.1

C A B

56X

0.05

4224872/A 03/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTQ0056C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(3.05) TYP

SEE SOLDER MASK

DETAIL

(0.62) TYP

(1.24)

TYP

56X (0.6)

56X (0.24)

56

43

1

42

52X (0.5)

(3.05) TYP

(1.24) TYP

(R0.05) TYP

57

SYMM

(7.8)

(0.62) TYP

(

6.6)

0.2) TYP

VIA

14

29

28

15

SYMM

(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224872/A 03/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTQ0056C

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.24) TYP

43

56X (0.6)

56X (0.24)

56

1

42

52X (0.5)

(R0.05) TYP

(1.24) TYP

(7.8)

57

SYMM

25X ( 1.04)

14

29

15

28

SYMM

(7.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 10X

EXPOSED PAD 57

62% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4224872/A 03/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

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型号：	ADC3443IRTQT
厂家：	TEXAS INSTRUMENTS
描述：	四通道、14 位、80MSPS 模数转换器 (ADC) \| RTQ \| 56 \| -40 to 85 转换器模数转换器
文件：	总88页 (文件大小：4868K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC3443IRTQT [TI]

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