ADC34J45IRGZR [TI]
四通道、14 位、160MSPS 模数转换器 (ADC) | RGZ | 48 | -40 to 85;
| 型号： | ADC34J45IRGZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四通道、14 位、160MSPS 模数转换器 (ADC) | RGZ | 48 | -40 to 85 转换器 模数转换器 |
| 文件： | 总91页 (文件大小：7456K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
ADC34J4x 具有 JESD204B 接口的四通道 14 位 50MSPS 至 160MSPS
模数转换器
1 特性
3 说明
1
•
•
•
•
四通道
ADC34J4x 是一款高线性度、超低功耗、四通道、14
位、50MSPS 至 160MSPS 模数转换器 (ADC)。 此类
器件专门设计用于支持具有宽动态范围需求且要求苛刻
的高输入频率信号。 当 SYSREF 输入实现整个系统同
步时，时钟输入分频器将给予系统时钟架构设计更高的
灵活性。 ADC34J4x 系列支持串行电流模式逻辑
(CML) 和 JESD204B 接口，从而减少接口线路的数
量，实现高系统集成度。 JESD204B 接口是串行接
口，仅通过一个差分对即可串行输出每个 ADC 的数
据。 内部锁相环 (PLL) 会将传入的 ADC 采样时钟乘
以 20，以获得串行输出各通道的 14 位数据时所使用
的位时钟。 ADC34J4x 器件支持子类 1，接口速率高
达 3.2Gbps。
14 位分辨率
1.8V 单电源
支持 1 分频、2 分频和 4 分频的灵活输入时钟缓冲
器
•
•
fIN = 70 MHz 时，信噪比 (SNR) = 72dBFS，无杂
散动态范围 (SFDR) = 86dBc
超低功耗：
–
160MSPS 时为每通道 203mW
•
•
•
通道隔离：105dB
内部抖动
JESD204B 串口：
–
–
支持子类 0、1、2
器件信息(1)
支持每个 ADC 一条通道（高达 160MSPS）
器件型号
ADC34J4x
封装
VQFN (48)
封装尺寸（标称值）
•
•
•
支持多芯片同步
7.00mm x 7.00mm
与 12 位版本器件引脚到引脚兼容
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
封装：超薄四方扁平无引线 (VQFN)-48 (7mm x
7mm)
启用抖动功能时的快速傅立叶变换 (FFT)
（fS = 160MSPS，fIN = 10MHz，SNR =
72.5dBFS，SFDR = 88dBc）
2 应用
•
•
•
•
•
•
•
•
•
•
多载波、多模式蜂窝基站
0
雷达和智能天线阵列
炮弹制导
±20
±40
电机控制反馈
网络和矢量分析器
通信测试设备
±60
±80
无损检测
±100
±120
微波接收器
软件定义无线电 (SDR)
正交和分集无线电接收器
0
16
32
48
64
80
Frequency (MHz)
C001
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBAS664
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
目录
7.19 Typical Characteristics: Common Plots ................ 43
7.20 Typical Characteristics: Contour Plots.................. 44
Parameter Measurement Information ................ 46
8.1 Timing Diagrams..................................................... 46
Detailed Description ............................................ 48
9.1 Overview ................................................................. 48
9.2 Functional Block Diagram ....................................... 48
9.3 Feature Description................................................. 49
9.4 Device Functional Modes........................................ 56
9.5 Programming........................................................... 57
9.6 Register Map........................................................... 61
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 Handling Ratings....................................................... 5
7.3 Recommended Operating Conditions....................... 5
7.4 Summary of Special Mode Registers........................ 6
7.5 Thermal Information.................................................. 6
7.6 Electrical Characteristics: ADC34J44, ADC34J45.... 7
7.7 Electrical Characteristics: ADC34J42, ADC34J43 ... 7
7.8 Electrical Characteristics: General............................ 8
7.9 AC Performance: ADC34J45 .................................... 9
7.10 AC Performance: ADC34J44 ................................ 11
7.11 AC Performance: ADC34J43 ................................ 13
7.12 AC Performance: ADC34J42 ............................... 15
7.13 Digital Characteristics ........................................... 17
7.14 Timing Characteristics........................................... 18
7.15 Typical Characteristics: ADC34J45 ...................... 19
7.16 Typical Characteristics: ADC34J44 ...................... 25
7.17 Typical Characteristics: ADC34J43 ...................... 31
7.18 Typical Characteristics: ADC34J42 ...................... 37
8
9
10 Application and Implementation........................ 77
10.1 Application Information.......................................... 77
10.2 Typical Applications .............................................. 77
11 Power-Supply Recommendations ..................... 80
12 Layout................................................................... 81
12.1 Layout Guidelines ................................................. 81
12.2 Layout Example .................................................... 81
13 器件和文档支持 ..................................................... 82
13.1 相关链接................................................................ 82
13.2 商标....................................................................... 82
13.3 静电放电警告......................................................... 82
13.4 术语表 ................................................................... 82
14 机械封装和可订购信息 .......................................... 82
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2014) to Revision B
Page
•
•
文档状态从混合状态更改为生产数据 ...................................................................................................................................... 1
已将 ADC43J2、ADC43J3 和 ADC43J4 的状态更改为生产数据........................................................................................... 1
Changes from Original (May 2014) to Revision A
Page
•
•
文档状态从产品预览更改为混合状态：ADC34J45 发布为生产数据....................................................................................... 1
更改了产品预览数据表 ........................................................................................................................................................... 1
2
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
5 Device Comparison Table
RESOLUTION
INTERFACE
(Bits)
25 MSPS
ADC3421
ADC3441
—
50 MSPS
ADC3422
ADC3442
ADC34J22
ADC34J42
80 MSPS
ADC3423
ADC3443
ADC34J23
ADC34J43
125 MSPS
ADC3424
ADC3444
ADC34J24
ADC34J44
160 MSPS
—
12
Serial LVDS
14
—
12
ADC34J25
ADC34J45
JESD204B
14
—
6 Pin Configuration and Functions
RGZ Package
VQFN-48
(Top View)
48
47
46
45
44
43
42
41
40
39
38
37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
OVRB
OVRA
DVDD
AVDD
AVDD
INAM
INAP
OVRC
OVRD
DVDD
PDN
3
4
5
AVDD
INDM
INDP
6
GND Pad
(Back Side)
7
8
AVDD
AVDD
INBP
AVDD
AVDD
INCP
9
10
11
12
INBM
AVDD
INCM
AVDD
13
14
15
16
17
18
19
20
21
22
23
24
Copyright © 2014, Texas Instruments Incorporated
3
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
4, 5, 8, 9, 12, 17,
20, 25, 28, 29, 32,
39, 46
AVDD
I
Analog 1.8-V power supply
CLKM
CLKP
DAM
18
I
I
Negative differential clock input for the ADC
Positive differential clock input for the ADC
Negative serial JESD204B output for channel A
Positive serial JESD204B output for channel A
Negative serial JESD204B output for channel B
Positive serial JESD204B output for channel B
Negative serial JESD204B output for channel C
Positive serial JESD204B output for channel C
Negative serial JESD204B output for channel D
Positive serial JESD204B output for channel D
Digital 1.8-V power supply
19
48
O
O
O
O
O
O
O
O
I
DAP
47
DBM
45
DBP
44
DCM
41
DCP
40
DDM
38
DDP
37
DVDD
GND
3, 34
PowerPAD™
I
Ground, 0 V
INAM
INAP
INBM
INBP
INCM
INCP
INDM
INDP
OVRA
OVRB
OVRC
OVRD
PDN
6
I
Negative differential analog input for channel A
Positive differential analog input for channel A
Negative differential analog input for channel B
Positive differential analog input for channel B
Negative differential analog input for channel C
Positive differential analog input for channel C
Negative differential analog input for channel D
Positive differential analog input for channel D
Overrange indicator for channel A
7
I
11
10
26
27
31
30
2
I
I
I
I
I
I
O
O
O
O
I
1
Overrange indicator for channel B
36
35
33
21
13
14
16
Overrange indicator for channel C
Overrange indicator for channel D
Power-down control. This pin has an internal 150-kΩ pull-down resistor.
RESET
SCLK
SDATA
SDOUT
I
Hardware reset; active high. This pin has an internal 150-kΩ, pull-down resistor.
Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
Serial interface data output
I
I
O
Serial interface enable. Active low.
This pin has an internal 150-kΩ pull-up resistor to AVDD.
SEN
15
I
SYNCM~
SYNCP~
SYSREFM
SYSREFP
VCM
42
43
23
22
24
I
I
Negative JESD204B synch input
Positive JESD204B synch input
I
Negative external SYSREF input
I
Positive external SYSREF input
O
Common-mode voltage output for the analog inputs
4
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
MAX
2.1
UNIT
V
Supply voltage range, AVDD
Supply voltage range, DVDD
2.1
V
Minimum
(AVDD + 0.3, 2.1)
INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM
CLKP, CLKM(2)
–0.3
–0.3
–0.3
V
V
V
Minimum
(AVDD + 0.3, 2.1)
Voltage applied to input
pins:
Minimum
(AVDD + 0.3, 2.1)
SYSREFP, SYSREFM, SYNCP~, SYNCM~
SCLK, SEN, SDATA, RESET, PDN
Operating free-air, TA
–0.3
–40
3.6
85
V
°C
°C
Temperature range
Operating junction, TJ
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When AVDD is turned off, TI recommends switching off the input clock (or ensuring the voltage on CLKP, CLKM is less than |0.3 V|).
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
Electrostatic discharge
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
V(ESD)
2
kV
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage range
Digital supply voltage range
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DVDD
ANALOG INPUT
For input frequencies < 450 MHz
For input frequencies < 600 MHz
2
1
VPP
VPP
V
VID
VIC
Differential input voltage
Input common-mode voltage
VCM ± 0.025
CLOCK INPUT
Input clock frequency
Sampling clock frequency
Sine wave, ac-coupled
LVPECL, ac-coupled
LVDS, ac-coupled
15
160(2)
MSPS
0.2
1.5
1.6
V
V
V
Input clock amplitude (differential)
0.7
Input clock duty cycle
35%
50%
0.95
65%
Input clock common-mode voltage
V
DIGITAL OUTPUTS
Maximum external load capacitance
from each output pin to GND
CLOAD
RLOAD
3.3
50
pF
Single-ended load resistance
Ω
(1) After power-up, to reset the device for the first time, only use the RESET pin; see the Register Initialization section.
(2) With the clock divider enabled by default for divide-by-1. Maximum sampling clock frequency for the divide-by-4 option is 640 MSPS.
Copyright © 2014, Texas Instruments Incorporated
5
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
7.4 Summary of Special Mode Registers
Table 1 lists the location, value, and functions of special mode registers in the device.
Table 1. Special Modes Summary
MODE
LOCATION
01h [7:6], 134h[5,3]
01h [5:4], 434h[5,3]
01h [3:2], 534h[5,3]
01h [1:0], 234h[5,3]
06h[4:2]
VALUE AND FUNCTION
DIS DITH CHA
Creates a noise floor cleaner and improves SFDR; see the
Internal Dither Algorithm section.
0000 = Dither disabled
DIS DITH CHB
Dither mode
DIS DITH CHC
1111 = Dither enabled
DIS DITH CHD
SPECIAL MODE 1 CHA
SPECIAL MODE 1 CHB
SPECIAL MODE 1 CHC
SPECIAL MODE 1 CHD
SPECIAL MODE 2 CHA
SPECIAL MODE 2 CHB
SPECIAL MODE 2 CHC
SPECIAL MODE 2 CHD
Use for better HD3.
000 = Default after reset
010 = Use for frequency < 120 MHz
111 = Use for frequency > 120 MHz
07h[4:2]
Special mode 1
Special mode 2
08h[4:2]
09h[4:2]
122h[1:0]
Helps improve HD2.
00 = Default after reset
11 = Improves HD2
422h[1:0]
522h[1:0]
222h[1:0]
7.5 Thermal Information
ADC34J4x
THERMAL METRIC(1)
RGZ (VQFN)
UNIT
48 PINS
25.7
18.9
3.0
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
3
RθJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.6 Electrical Characteristics: ADC34J44, ADC34J45
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock
duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J44
TYP
ADC34J45
TYP
PARAMETER
MIN
MAX
125
14
MIN
MAX
160
14
UNIT
MSPS
Bits
mA
ADC clock frequency
Resolution
1.8-V analog supply (AVDD) current
1.8-V digital supply current
Total power dissipation
318
79
354
97
490
150
1010
mA
715
22
812
22
mW
mW
µs
Global power-down dissipation
Wake-up time from global power-down
Standby power-down dissipation
Wake-up time from standby power-down
85
85
100
300
177
35
185
35
mW
µs
7.7 Electrical Characteristics: ADC34J42, ADC34J43
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock
duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J42
TYP
ADC34J43
TYP
PARAMETER
MIN
MAX
50
MIN
MAX
80
UNIT
MSPS
Bits
mA
ADC clock frequency
Resolution
14
14
1.8-V analog supply current
1.8-V digital supply current
Total power dissipation
233
39
269
56
mA
491
22
584
22
mW
mW
µs
Global power-down dissipation
Wake-up time from global power-down
Standby power-down dissipation
Wake-up time from standby power-down
85
85
155
35
166
35
mW
µs
Copyright © 2014, Texas Instruments Incorporated
7
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
7.8 Electrical Characteristics: General
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, maximum sampling rate, 50% clock
duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential input full-scale
Input resistance
2.0
6.5
5.2
VPP
kΩ
pF
ri
Differential at dc
ci
Input capacitance
Differential at dc
VCM common-mode voltage
output
VOC(VCM)
0.95
V
VCM output current capability
Input common-mode current
10
mA
Per analog input pin
1.5
µA/MSPS
50-Ω differential source driving 50-Ω
termination across INP and INM
Analog input bandwidth (3 dB)
450
MHz
DC ACCURACY
EO
Offset error
–20
–3
20
3
mV
%FS
Gain error as a result of internal
reference inaccuracy alone
EG(REF)
EG(CHAN) Gain error of channel alone
±1
%FS
Temperature coefficient of
EG(CHAN)
α(EGCHAN)
–0.017
Δ%FS/C
CHANNEL-TO-CHANNEL ISOLATION
Near channel
fIN = 10 MHz
105
105
95
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Far channel
Near channel
fIN = 100 MHz
Far channel
105
94
Near channel
fIN = 200 MHz
Crosstalk(1)
Far channel
105
93
Near channel
fIN = 230 MHz
Far channel
105
85
Near channel
fIN = 300 MHz
Far channel
105
(1) Crosstalk is measured with a –1-dBFS input signal on the aggressor channel and no input on the victim channel.
8
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.9 AC Performance: ADC34J45
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS,
50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J45 (fS = 160 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
72.4
71.6
72.7
72
70.4
SNR
Signal-to-noise ratio
70.9
71.3
70.4
69.5
–151.7
–151
–150.3
–149.4
–148.5
72.4
71.6
71.1
70
dBFS
69.9
68.8
–151.4
–149.5 –150.6
–149.9
Noise spectral density
(averaged across Nyquist zone)
NSD
dBFS/Hz
dBFS
Bits
–148.9
–147.8
72.1
69.6
11.3
81
71.2
70.7
69.5
68.4
11.8
11.7
11.6
11.3
11.1
88
SINAD
ENOB
SFDR
HD2
Signal-to-noise and distortion ratio fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
69
11.8
11.7
11.6
11.3
11.1
86
Effective number of bits
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
86
85
Spurious-free dynamic range
Second harmonic distortion
86
86
dBc
83
83
80
80
–91
–94
–93
–83
–80
–88
–86
–86
–92
–85
98
–93
–92
–91
–83
–80
–86
–85
–86
–87
–82
95
81
dBc
81
HD3
Non
Third harmonic distortion
dBc
87
98
94
Spurious-free dynamic range
96
93
dBc
HD2, HD3 (excluding HD2, HD3)
92
91
92
90
Copyright © 2014, Texas Instruments Incorporated
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
AC Performance: ADC34J45 (continued)
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 160 MSPS,
50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J45 (fS = 160 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
TYP
–84
–86
–84
–82
–78
MAX
MIN
TYP
–84
–83
–84
–80
–77
MAX
UNIT
fIN = 70 MHz
76.5
THD
Total harmonic distortion
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
93
88
93
88
Third-order intermodulation
distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
10
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.10 AC Performance: ADC34J44
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS,
50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J44 (fS = 125 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
72.5
72.1
72.9
72.5
72.3
71.4
70.6
–151.9
–151.5
–151.3
–150.4
–149.6
72.8
72.4
72.1
70.9
70.1
11.9
11.8
11.7
11.5
11.2
93
70.8
SNR
Signal-to-noise ratio
71.8
dBFS
70.6
69.8
–151.5
–148.8 –151.1
–150.8
Noise spectral density
(averaged across Nyquist zone)
NSD
dBFS/Hz
dBFS
Bits
–149.6
–148.8
72.4
68.6
11.1
81
72.1
71.7
70.4
69.4
11.9
11.7
11.7
11.4
11.1
93
SINAD
ENOB
SFDR
HD2
Signal-to-noise and distortion ratio fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
Effective number of bits
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
94
91
Spurious-free dynamic range
Second harmonic distortion
92
92
dBc
83
83
81
80
–93
–94
–92
–83
–81
–95
–94
–95
–88
–90
99
–93
81
–94
–92
dBc
–83
–80
–94
83
–91
HD3
Non
Third harmonic distortion
–93
dBc
–85
–90
96
87
98
95
Spurious-free dynamic range
98
95
dBc
HD2, HD3 (excluding HD2, HD3)
97
92
96
93
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
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www.ti.com.cn
AC Performance: ADC34J44 (continued)
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 125 MSPS,
50% clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J44 (fS = 125 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
TYP
–89
–89
–88
–82
–80
MAX
MIN
TYP
–87
–87
–86
–80
–79
MAX
UNIT
fIN = 70 MHz
76.5
THD
Total harmonic distortion
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
92
90
92
90
Third-order intermodulation
distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
12
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.11 AC Performance: ADC34J43
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50%
clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J43 (fS = 80 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
72.3
72
72.8
72.4
72.1
71.3
70.5
–151.8
–151.4
–151.1
–150.3
–149.5
72.6
72.2
71.9
70.9
69.9
11.8
11.9
11.7
11.4
11.2
94
70.7
–146.8
68.6
11.1
82
SNR
Signal-to-noise ratio
71.7
70.9
70.1
–151.3
–151
–150.7
–149.9
–149.1
72.3
71.9
71.6
70.6
69.6
11.8
11.8
11.7
11.4
11.2
94
dBFS
Noise spectral density
(averaged across Nyquist zone)
NSD
dBFS/Hz
dBFS
Bits
SINAD
ENOB
SFDR
HD2
Signal-to-noise and distortion ratio fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
Effective number of bits
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN= 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
94
94
Spurious-free dynamic range
Second harmonic distortion
89
91
dBc
83
83
80
81
–94
–94
–91
–83
–80
–99
–99
–99
–99
–99
98
–94
82
–94
–91
dBc
–83
–81
–94
83
–95
HD3
Non
Third harmonic distortion
–89
dBc
–90
–83
92
87
98
92
Spurious-free dynamic range
97
92
dBc
HD2, HD3 (excluding HD2, HD3)
95
91
94
91
Copyright © 2014, Texas Instruments Incorporated
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
AC Performance: ADC34J43 (continued)
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 80 MSPS, 50%
clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J43 (fS = 80 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
TYP
–91
–91
–87
–82
–78
MAX
MIN
TYP
–86
–86
–84
–81
–78
MAX
UNIT
fIN = 70 MHz
76.5
THD
Total harmonic distortion
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
94
89
94
89
Third-order intermodulation
distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
14
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7.12 AC Performance: ADC34J42
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50%
clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J42 (fS = 50 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
70.7
72.4
72
72.8
72.4
72.2
71.3
70.1
–151.8
–151.4
–151.2
–150.3
–149.1
72.6
72.2
71.9
70.9
69.5
11.9
11.7
11.8
11.4
11.1
92
SNR
Signal-to-noise ratio
71.9
71
dBFS
69.9
–145.9 –151.4
–151
Noise spectral density
(averaged across Nyquist zone)
NSD
–150.9
dBFS/Hz
dBFS
Bits
–150
–148.9
68.6
11.1
82
72.2
71.9
71.7
70.7
69.4
11.8
11.7
11.7
11.4
11.1
93
SINAD
ENOB
SFDR
HD2
Signal-to-noise and distortion ratio fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
Effective number of bits
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
fIN = 10 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
93
92
Spurious-free dynamic range
Second harmonic distortion
90
89
dBc
83
83
80
80
82
–93
–93
–90
–83
–80
–94
–94
–91
–91
–84
98
–92
–96
–90
dBc
–83
–80
83
–93
–92
HD3
Non
Third harmonic distortion
–89
dBc
–90
–83
87
92
98
92
Spurious-free dynamic range
96
92
dBc
HD2, HD3 (excluding HD2, HD3)
96
91
96
91
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
AC Performance: ADC34J42 (continued)
Typical values are at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 50 MSPS, 50%
clock duty cycle, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted.
ADC34J42 (fS = 50 MSPS)
DITHER ON
DITHER OFF
PARAMETER
TEST CONDITIONS
fIN = 10 MHz
MIN
76.5
TYP
–91
–89
–86
–82
–78
MAX
MIN
TYP
–85
–85
–84
–81
–78
MAX
UNIT
fIN = 70 MHz
THD
Total harmonic distortion
fIN = 100 MHz
fIN = 170 MHz
fIN = 230 MHz
dBc
fIN1 = 45 MHz,
fIN2 = 50 MHz
93
86
93
86
Third-order intermodulation
distortion
IMD3
dBFS
fIN1 = 185 MHz,
fIN2 = 190 MHz
16
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.13 Digital Characteristics
The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = DVDD = 1.8 V and –1-dBFS differential input, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (RESET, SCLK, SEN, SDATA, PDN)(1)
VIH
VIL
High-level input voltage
Low-level input voltage
All digital inputs support 1.8-V and 3.3-V logic levels
1.2
V
All digital inputs support 1.8-V and 3.3-V logic levels
0.4
V
SEN
0
10
10
0
µA
µA
µA
µA
IIH
High-level input current
Low-level input current
RESET, SCLK, SDATA, PDN
SEN
IIL
RESET, SCLK, SDATA, PDN
DIGITAL INPUTS (SYNCP~, SYNCM~, SYSREFP, SYSREFM)
VIH
VIL
High-level input voltage
Low-level input voltage
1.3
0.5
V
V
Common-mode voltage for SYNC~
and SYSREF
V(CM_DIG)
0.9
V
DIGITAL OUTPUTS (SDOUT, OVRA, OVRB, OVRC, OVRD)
DVDD –
0.1
VOH
High-level output voltage
DVDD
V
V
VOL
Low-level output voltage
0.1
DIGITAL OUTPUTS (JESD204B Interface: DxP, DxM)(2)
VOH
VOL
VOD
VOC
High-level output voltage
Low-level output voltage
Output differential voltage
Output common-mode voltage
DVDD
DVDD – 0.4
0.4
V
V
V
V
DVDD – 0.2
Transmitter pins shorted to any voltage between
–0.25 V and 1.45 V
Transmitter short-circuit current
Single-ended output impedance
Output capacitance
–100
100
mA
Ω
zos
50
2
Output capacitance inside the device,
from either output to ground
pF
(1) RESET, SCLK, SDATA, and PDN pins have 150-kΩ (typical) internal pull-down resistor to ground, while SEN pin has 150-kΩ (typical)
pull-up resistor to AVDD.
(2) 50-Ω, single-ended external termination to 1.8 V.
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7.14 Timing Characteristics
Typical values are at 25°C, AVDD = DVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted. Minimum and
maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C. See Figure 143.
PARAMETER
SAMPLE TIMING CHARACTERISTICS
Aperture delay
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.85
1.25
±70
1.65
ns
ps
Between four channels on the same device
Aperture delay matching
Between two devices at the same temperature and supply
voltage
±150
ps
Aperture jitter
Wake-up time
200
35
fS rms
µs
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of global power-down
Referenced to input clock rising edge
100
300
85
µs
tSU_SYNC~
tH_SYNC~
tSU_SYSREF
tH_SYSREF
Setup time for SYNC~
Hold time for SYNC~
Setup time for SYSREF
Hold time for SYSREF
1
100
1
ns
Referenced to input clock rising edge
ps
Referenced to input clock rising edge
ns
Referenced to input clock rising edge
100
ps
CML OUTPUT TIMING CHARACTERISTICS
Unit interval
312.5
1667
3.2
ps
Serial output data rate
Gbps
P-PUI
Total jitter
3.125 Gbps (20x mode, fS = 156.25 MSPS)
0.3
Rise and fall times measured from 20% to 80%,
differential output waveform,
600 Mbps ≤ bit rate ≤ 3.125 Gbps
Data rise time,
data fall time
tR, tF
105
ps
Table 2. Latency in Different Modes(1)(2)
MODE
PARAMETER
LATENCY (N Cycles)
TYPICAL DATA DELAY (tD, ns)
0.29 × tS + 3
0.5 × tS + 2
ADC latency
17
9
Normal OVR latency
20x
Fast OVR latency
7
0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3)
From SYNC~ rising edge to ILA sequence(4)
ADC latency
15
17
16
9
0.3 × tS + 4
0.3 × tS + 4
0.85 × tS + 3.9
0.5 × tS + 2
Normal OVR latency
40x
Fast OVR latency
7
0.5 × tS + 2
From SYNC~ falling edge to CGS phase(3)
From SYNC~ rising edge to ILA sequence(4)
14
12
0.9 × tS + 4
0.9 × tS + 4
(1) Overall latency = latency + tD.
(2) tS is the time period of the ADC conversion clock.
(3) Latency is specified for subclass 2. In subclass 0, the SYNC~ falling edge to CGS phase latency is 16 clock cycles in 10x mode and 15
clock cycles in 20x mode.
(4) Latency is specified for subclass 2. In subclass 0, the SYNC~ rising edge to ILA sequence latency is 11 clock cycles in 10x mode and
11 clock cycles in 20x mode.
18
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.15 Typical Characteristics: ADC34J45
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C001
C002
fS = 160 MSPS, SNR = 72.5 dBFS, fIN = 10 MHz, SFDR = 88 dBc
fS = 160 MSPS, SNR = 72.7 dBFS, fIN = 10 MHz, SFDR = 85 dBc
Figure 1. FFT for 10-MHz Input signal, Dither On
Figure 2. FFT for 10-MHz Input signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C003
C004
fS = 160 MSPS, SNR = 71.4 dBFS, fIN = 70 MHz, SFDR = 86 dBc
fS = 160 MSPS, SNR = 71.8 dBFS, fIN = 70 MHz, SFDR = 85 dBc
Figure 3. FFT for 70-MHz Input Signal, Dither On
Figure 4. FFT for 70-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C005
C006
fS = 160 MSPS, SNR = 69.7 dBFS, fIN = 170 MHz,
SFDR = 83 dBc
fS = 160 MSPS, SNR = 70.4 dBFS, fIN = 70 MHz, SFDR = 81 dBc
Figure 5. FFT for 170-MHz Input Signal, Dither On
Figure 6. FFT for 170-MHz Input Signal, Dither Off
Copyright © 2014, Texas Instruments Incorporated
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
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Typical Characteristics: ADC34J45 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C007
C008
fS = 160 MSPS, SNR = 68.2 dBFS, fIN = 270 MHz,
SFDR = 76 dBc
fS = 160 MSPS, SNR = 68.8 dBFS, fIN = 270 MHz,
SFDR = 75 dBc
Figure 7. FFT for 270-MHz Input Signal, Dither On
Figure 8. FFT for 270-MHz Input Signal, Dither Off
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C009
C010
fS = 160 MSPS, SNR = 63.3 dBFS, fIN = 450 MHz,
SFDR = 64 dBc
fS = 160 MSPS, SNR = 63.4 dBFS, fIN = 450 MHz,
SFDR = 63 dBc
Figure 9. FFT for 450-MHz Input Signal, Dither On
Figure 10. FFT for 450-MHz Input Signal, Dither Off
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C011
C012
fS = 160 MSPS, IMD = 92 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 99 dBFS
fS = 160 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 102 dBFS
Figure 11. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
Figure 12. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
20
Copyright © 2014, Texas Instruments Incorporated
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J45 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C013
C014
fS = 160 MSPS, IMD = 87 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 90 dBFS
fS = 160 MSPS, IMD = 100 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 102 dBFS
Figure 13. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 14. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
-85
-90
±80
±85
-95
±90
-100
-105
-110
±95
±100
±105
±35
±31
±27
±23
±19
±15
±11
±7
±35
±31
±27
±23
±19
±15
±11
±7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
C015
C016
fS = 160 MSPS, fIN1 = 46 MHz, fIN2 = 50 MHz
fS = 160 MSPS, fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 15. IMD vs Input Amplitude (46 MHz and 50 MHz)
Figure 16. IMD vs Input Amplitude (185 MHz and 190 MHz)
95
74
Dither_EN
Dither_EN
Dither_DIS
90
85
80
75
70
65
Dither_DIS
72
70
68
66
64
0
50
100
150
200
250
300
350
400
Frequency (MHz)
c018
0
50
100
150
200
250
300
350
400
Input Frequency (MHz)
C017
Figure 18. SFDR vs Input Frequency
Figure 17. SNR vs Input Frequency
Copyright © 2014, Texas Instruments Incorporated
21
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J45 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
78
76
74
72
70
68
66
64
62
115
110
105
100
95
10 MHz
70 MHz
10 MHz
70 MHz
100 MHz
230 MHz
400 MHz
170 MHz
270 MHz
100 MHz
270 MHz
230MHz
170 MHz
400 MHz
90
85
80
75
70
65
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
C019
C020
Figure 19. SNR vs Digital Gain and Input Frequency
Figure 20. SFDR vs Digital Gain and Input Frequency
74
73.5
73
130
120
110
100
90
75
110
100
90
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
74.5
74
72.5
72
73.5
73
80
70
71.5
71
80
70
72.5
72
60
70.5
70
60
50
50
71.5
71
40
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
69.5
69
40
30
30
68.5
20
70.5
20
-70
-60
-50
-40
-30
-20
-10
0
0
±70
±60
±50
±40
±30
±20
±10
Amplitude (dBFS)
C022
Amplitude (dBFS)
C021
Figure 22. Performance Across Input Amplitude (170 MHz)
Figure 21. Performance Across Input Amplitude (30 MHz)
73.2
94
92
90
88
86
84
82
70
69.8
69.6
69.4
69.2
69
86
84
82
80
78
76
SNR(dBFS)
SFDR(dBc)
SNR(dBFS)
SFDR(dBc)
73
72.8
72.6
72.4
72.2
72
71.8
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V))
C023
Input Common-Mode Voltage (V))
C024
Figure 23. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 24. Performance vs Input Common-Mode Voltage
(170 MHz)
22
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J45 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
92
90
88
86
84
82
80
78
73
72
71
70
69
68
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
10
35
60
85
10
35
60
85
±40
±15
±40
±15
Temperature (oC)
Temperature (oC)
C025
C026
Figure 25. SFDR vs AVDD Supply and Temperature
Figure 26. SNR vs AVDD Supply and Temperature
71
70.5
70
88
87
86
85
84
83
82
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
69.5
69
68.5
68
10
35
60
85
10
35
60
85
±40
±15
±40
±15
Temperature (oC)
Temperature (oC)
C027
C028
Figure 27. SFDR vs DVDD Supply and Temperature
Figure 28. SNR vs DVDD Supply and Temperature
75
91
90
89
88
87
86
85
78
87
SNR
SNR
SFDR
SFDR
86
76
74
72
70
68
66
64
74
85
84
83
82
81
80
73
72
71
70
69
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
C029
C030
Figure 29. Performance vs Clock Amplitude (40 MHz)
Figure 30. Performance vs Clock Amplitude (150 MHz)
Copyright © 2014, Texas Instruments Incorporated
23
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J45 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, Dither enable, special modes written, unless otherwise noted.
74
73.5
73
95
94
93
92
91
90
72.5
92
91
90
89
88
87
86
SNR
SNR
SFDR
SFDR
72
71.5
71
72.5
72
70.5
70
71.5
69.5
30
40
50
60
70
30
40
50
60
70
Input Clock Duty Cycle (%)
C031
Input Clock Duty Cycle (%)
C032
Figure 31. Performance vs Clock Duty Cycle (40 MHz)
Figure 32. Performance vs Clock Duty Cycle (150 MHz)
35
28.89
30
25
24.95
18.33
20
14.93
15
10
5.41
1.45
0.2
4.73
5
0
0.97
0.11
0
0.01
0.01
0
0
Output Code (LSB)
C033
RMS noise = 1.3 LSBs
Figure 33. Idle Channel Histogram
24
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.16 Typical Characteristics: ADC34J44
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C001
C002
fS = 125 MSPS, SNR = 72.6 dBFS, fIN = 10 MHz, SFDR = 94 dBc
fS = 125 MSPS, SNR = 73.1 dBFS, fIN = 10 MHz, SFDR = 88 dBc
Figure 34. FFT for 10-MHz Input Signal, Dither On
Figure 35. FFT for 10-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C003
C004
fS = 125 MSPS, SNR = 72.2 dBFS, fIN = 70 MHz, SFDR = 95 dBc
fS = 125 MSPS, SNR = 72.7 dBFS, fIN = 70 MHz, SFDR = 89 dBc
Figure 36. FFT for 70-MHz Input Signal, Dither On
Figure 37. FFT for 70-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C005
C006
fS = 125 MSPS, SNR = 70.5 dBFS, fIN = 170 MHz,
SFDR = 87 dBc
fS = 125 MSPS, SNR = 71.4 dBFS, fIN = 70 MHz,
SFDR = 86 dBc
Figure 38. FFT for 170-MHz Input Signal, Dither On
Figure 39. FFT for 170-MHz Input Signal, Dither Off
Copyright © 2014, Texas Instruments Incorporated
25
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J44 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C007
C008
fS = 125 MSPS, SNR = 69.6 dBFS, fIN = 270 MHz,
SFDR = 80 dBc
fS = 125 MSPS, SNR = 70.3 dBFS, fIN = 270 MHz,
SFDR = 79 dBc
Figure 40. FFT for 270-MHz Input Signal, Dither On
Figure 41. FFT for 270-MHz Input Signal, Dither Off
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C009
C010
fS = 125 MSPS, SNR = 65.8 dBFS, fIN = 450 MHz,
SFDR = 68 dBc
fS = 125 MSPS, SNR = 66.5 dBFS, fIN = 450 MHz,
SFDR = 67 dBc
Figure 42. FFT for 450-MHz Input Signal, Dither On
Figure 43. FFT for 450-MHz Input Signal, Dither Off
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C011
C012
fS = 125 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 97 dBFS
fS = 125 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 106 dBFS
Figure 44. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
Figure 45. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
26
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J44 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
12.5
25
37.5
50
62.5
0
12.5
25
37.5
50
62.5
Frequency (MHz)
Frequency (MHz)
C013
C014
fS = 125 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 190 dBFS
fS = 125 MSPS, IMD = 99 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 104 dBFS
Figure 46. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 47. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
±85
±90
±85
±90
±95
±95
±100
±105
±110
±100
±105
±35
±31
±27
±23
±19
±15
±11
±7
±35
±31
±27
±23
±19
±15
±11
±7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
C015
C016
Figure 48. IMD vs Input Amplitude (46 MHz and 50 MHz)
Figure 49. IMD vs Input Amplitude (185 MHz and 190 MHz)
73
95
Dither_EN
Dither_EN
90
85
80
75
70
65
60
Dither_DIS
Dither_DIS
72
71
70
69
68
67
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
C017
C018
Figure 50. SNR vs Input Frequency
Figure 51. SFDR vs Input Frequency
Copyright © 2014, Texas Instruments Incorporated
27
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J44 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
74
73
72
71
70
69
68
67
66
65
64
115
110
105
100
95
10 MHz
70 MHz
170 MHz
270 MHz
10 MHz
70 MHz
170 MHz
270 MHz
100 MHz
230 MHz
400 MHz
100 MHz
230 MHz
400 MHz
90
85
80
75
70
65
60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
C019
C020
Figure 52. SNR vs Digital Gain and Input Frequency
Figure 53. SFDR vs Digital Gain and Input Frequency
75.5
75
130
120
110
100
90
75
74.5
74
130
120
110
100
90
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
74.5
74
73.5
73
73.5
73
72.5
72
80
80
70
72.5
72
70
71.5
71
60
60
50
71.5
71
50
70.5
70
40
40
30
70.5
30
69.5
20
-70
-60
-50
-40
-30
-20
-10
0
±70
±60
±50
±40
±30
±20
±10
0
Amplitude (dBFS)
Amplitude (dBFS)
C021
C022
Figure 54. Performance Across Input Amplitude (30 MHz)
Figure 55. Performance Across Input Amplitude (170 MHz)
73.2
96
94
92
90
88
86
71
70.8
70.6
70.4
70.2
70
86
85
84
83
82
81
80
SNR
SNR
SFDR
SFDR
73
72.8
72.6
72.4
72.2
69.8
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
Input Common-Mode Voltage (V)
C023
C024
Figure 56. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 57. Performance vs Input Common-Mode Voltage
(170 MHz)
28
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J44 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
89
88
87
86
85
84
83
82
72
71.5
71
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
70.5
70
69.5
69
±40
±15
10
35
60
85
±40
±15
10
35
60
85
Temperature (oC)
Temperature (oC)
C025
C026
Figure 58. SFDR vs AVDD Supply and Temperature
Figure 59. SNR vs AVDD Supply and Temperature
71.5
71
88
87
86
85
84
83
82
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
70.5
70
69.5
69
±40
±15
10
35
60
85
±40
±15
10
35
60
85
Temperature (oC)
Temperature (oC)
C027
C028
Figure 60. SFDR vs DVDD Supply and Temperature
Figure 61. SNR vs DVDD Supply and Temperature
75
100
95
90
85
80
75
70
85
95
SNR
SNR
SFDR
SFDR
90
74
80
75
70
65
60
73
72
71
70
69
85
80
75
70
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
C029
C030
Figure 62. Performance vs Clock Amplitude (40 MHz)
Figure 63. Performance vs Clock Amplitude (150 MHz)
Copyright © 2014, Texas Instruments Incorporated
29
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J44 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
74.5
105
100
95
72.5
95
90
85
80
75
70
SNR
SNR
SFDR
SFDR
74
72
73.5
73
71.5
71
90
72.5
72
85
70.5
70
80
30
40
50
60
70
30
40
50
60
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
C031
C032
Figure 64. Performance vs Clock Duty Cycle (40 MHz)
Figure 65. Performance vs Clock Duty Cycle (150 MHz)
40
34.53
30
16.81
15.06
10.92
20
16.24
10
2.86
1.76
1.14
0.03
0.56
0.08
0.02
0
0
0
0
Output Code (LSB)
C035
RMS noise = 1.4 LSBs
Figure 66. Idle Channel Histogram
30
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.17 Typical Characteristics: ADC34J43
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C001
C002
fS = 80 MSPS, SNR = 72.4 dBFS, fIN = 10 MHz, SFDR = 96 dBc
fS = 80 MSPS, SNR = 73 dBFS, fIN = 10 MHz, SFDR = 90 dBc
Figure 67. FFT for 10-MHz Input Signal, Dither On
Figure 68. FFT for 10-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C003
C004
fS = 80 MSPS, SNR = 72 dBFS, fIN = 70 MHz, SFDR = 95 dBc
fS = 80 MSPS, SNR = 72.5 dBFS, fIN = 70 MHz, SFDR = 89 dBc
Figure 69. FFT for 70-MHz Input Signal, Dither On
Figure 70. FFT for 70-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C005
C006
fS = 80 MSPS, SNR = 70.7 dBFS, fIN = 170 MHz, SFDR = 93 dBc
fS = 80 MSPS, SNR = 71.4 dBFS, fIN = 10 MHz, SFDR = 90 dBc
Figure 71. FFT for 170-MHz Input Signal, Dither On
Figure 72. FFT for 170-MHz Input Signal, Dither Off
Copyright © 2014, Texas Instruments Incorporated
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ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J43 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C007
C008
fS = 80 MSPS, SNR = 69.5 dBFS, fIN = 270 MHz, SFDR = 76 dBc
fS = 80 MSPS, SNR = 69.8 dBFS, fIN = 270 MHz, SFDR = 75 dBc
Figure 73. FFT for 270-MHz Input Signal, Dither On
Figure 74. FFT for 270-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C009
C010
fS = 80 MSPS, SNR = 63.2 dBFS, fIN = 450 MHz, SFDR = 67 dBc
fS = 80 MSPS, SNR = 64.1 dBFS, fIN = 450 MHz, SFDR = 67 dBc
Figure 75. FFT for 450-MHz Input Signal, Dither On
Figure 76. FFT for 450-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
C012
Frequency (MHz)
C011
fS = 80 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 106 dBFS
fS = 80 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 98 dBFS
Figure 78. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Figure 77. FFT for Two-Tone Input Signal
(–7 dBFS at 46 MHz and 50 MHz)
32
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J43 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
8
16
24
32
40
0
8
16
24
32
40
Frequency (MHz)
Frequency (MHz)
C013
C014
fS = 80 MSPS, IMD = 88 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 94 dBFS
fS = 80 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 102 dBFS
Figure 79. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 80. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
±85
±90
±80
±85
±90
±95
±95
±100
±105
±110
±100
±105
±110
±35
±31
±27
±23
±19
±15
±11
±7
±35
±31
±27
±23
±19
±15
±11
±7
Each Tone Amplitude (dBFS)
Each Tone Amplitude (dBFS)
C015
C016
Figure 81. IMD vs Input Amplitude (46 MHz and 50 MHz)
Figure 82. IMD vs Input Amplitude (185 MHz and 190 MHz)
73
100
Dither_EN
Dither_EN
Dither_DIS
Dither_DIS
95
90
85
80
75
70
65
72
71
70
69
68
67
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
C017
C018
Figure 83. SNR vs Input Frequency
Figure 84. SFDR vs Input Frequency
Copyright © 2014, Texas Instruments Incorporated
33
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J43 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
74
72
70
68
66
64
115
105
95
10 MHz
70 MHz
170 MHz
270 MHz
10 MHz
70 MHz
100 MHz
230 MHz
400 MHz
100 MHz
230 MHz
400 MHz
170 MHz
270 MHz
85
75
65
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
C019
C020
Figure 85. SNR vs Digital Gain and Input Frequency
Figure 86. SFDR vs Digital Gain and Input Frequency
75.5
75
130
120
110
100
90
75.5
140
130
120
110
100
90
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
75
74.5
74
74.5
74
73.5
73
73.5
73
80
72.5
72
80
72.5
72
70
70
60
71.5
71
60
71.5
71
50
50
40
70.5
70
40
70.5
30
30
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
C021
C022
Figure 87. Performance Across Input Amplitude (30 MHz)
Figure 88. Performance Across Input Amplitude (170 MHz)
73.5
73.25
73
98
96
94
92
90
88
86
84
71
70.75
70.5
86
85
84
83
82
81
80
SNR
SNR
SFDR
SFDR
72.75
72.5
72.25
72
70.25
70
69.75
69.5
71.75
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V)
C023
Input Common-Mode Voltage (V)
C024
Figure 89. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 90. Performance vs Input Common-Mode Voltage
(170 MHz)
34
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
www.ti.com.cn
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J43 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
73.5
72.5
71.5
70.5
69.5
68.5
90
89
88
87
86
85
84
83
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
±40
±15
10
35
60
85
10
35
60
85
±40
±15
Temperature (oC)
Temperature (oC)
C026
C025
Figure 92. SNR vs AVDD Supply and Temperature
Figure 91. SFDR vs AVDD Supply and Temperature
90
89
88
87
86
85
84
83
72
71.5
71
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
70.5
70
69.5
69
±40
±15
10
35
60
85
±40
±15
10
35
60
85
Temperature (oC)
Temperature (oC)
C027
C028
Figure 93. SFDR vs DVDD Supply and Temperature
Figure 94. SNR vs DVDD Supply and Temperature
75
95
77
100
95
90
85
80
75
70
SNR
SFDR
73
71
69
67
65
63
61
59
90
85
80
75
70
65
60
55
75
73
71
69
67
65
SNR
SFDR
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
C029
C030
Figure 95. Performance vs Clock Amplitude (40 MHz)
Figure 96. Performance vs Clock Amplitude (150 MHz)
Copyright © 2014, Texas Instruments Incorporated
35
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J43 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 80 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
74
73.5
73
110
105
100
95
72
71.5
71
100
95
90
85
80
75
SNR
SNR
SFDR
SFDR
72.5
72
70.5
70
90
71.5
85
69.5
30
40
50
60
70
30
40
50
60
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
C031
C032
Figure 97. Performance vs Clock Duty Cycle (40 MHz)
Figure 98. Performance vs Clock Duty Cycle (150 MHz)
36
31.43
30
20.48
21.53
24
18
11.74
12
6.34
0.79
4.89
6
2.34
0.03
0.17
0
0.25
0.01
0
0
Output Code (LSB)
C033
RMS noise = 1.4 LSBs
Figure 99. Idle Channel Histogram
36
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.18 Typical Characteristics: ADC34J42
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C001
C002
fS = 50 MSPS, SNR = 72.3 dBFS, fIN = 10 MHz, SFDR = 95 dBc
fS = 50 MSPS, SNR = 72.9 dBFS, fIN = 10 MHz, SFDR = 89 dBc
Figure 100. FFT for 10-MHz Input Signal, Dither On
Figure 101. FFT for 10-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C003
C004
fS = 50 MSPS, SNR = 71.8 dBFS, fIN = 70 MHz, SFDR = 93 dBc
fS = 50 MSPS, SNR = 72.3 dBFS, fIN = 70 MHz, SFDR = 87 dBc
Figure 102. FFT for 70-MHz Input Signal, Dither On
Figure 103. FFT for 70-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C005
C006
fS = 50 MSPS, SNR = 70.8 dBFS, fIN = 170 MHz, SFDR = 87 dBc
fS = 50 MSPS, SNR = 71.2 dBFS, fIN = 170 MHz, SFDR = 86 dBc
Figure 104. FFT for 170-MHz Input Signal, Dither On
Figure 105. FFT for 170-MHz Input Signal, Dither Off
Copyright © 2014, Texas Instruments Incorporated
37
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J42 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C007
C008
fS = 50 MSPS, SNR = 69.5 dBFS, fIN = 270 MHz, SFDR = 76 dBc
fS = 50 MSPS, SNR = 69.6 dBFS, fIN = 270 MHz, SFDR = 76 dBc
Figure 106. FFT for 270-MHz Input Signal, Dither On
Figure 107. FFT for 270-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C009
C010
fS = 50 MSPS, SNR = 66.3 dBFS, fIN = 450 MHz, SFDR = 63 dBc
fS = 50 MSPS, SNR = 66.9 dBFS, fIN = 450 MHz, SFDR = 63 dBc
Figure 108. FFT for 450-MHz Input Signal, Dither On
Figure 109. FFT for 450-MHz Input Signal, Dither Off
0
0
±20
±40
±20
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
C012
Frequency (MHz)
C011
fS = 50 MSPS, IMD = 101 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 106 dBFs
fS = 50 MSPS, IMD = 93 dBFS, fIN1 = 46 MHz, fIN2 = 50 MHz,
SFDR = 96 dBFS
Figure 111. FFT for Two-Tone Input Signal
(–36 dBFS at 46 MHz and 50 MHz)
Figure 110. FFT for Two-Tone Input Signal
(–7dBFS at 46 MHz and 50 MHz)
38
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J42 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
0
±20
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
5
10
15
20
25
0
5
10
15
20
25
Frequency (MHz)
Frequency (MHz)
C013
C014
fS = 50 MSPS, IMD = 86 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 92 dBFS
fS = 50 MSPS, IMD = 99 dBFS, fIN1 = 185 MHz, fIN2 = 190 MHz,
SFDR = 102 dBFs
Figure 112. FFT for Two-Tone Input Signal
(–7 dBFS at 185 MHz and 190 MHz)
Figure 113. FFT for Two-Tone Input Signal
(–36 dBFS at 185 MHz and 190 MHz)
±85
±90
±80
±85
±90
±95
±95
±100
±105
±110
±100
±105
±110
±35
±31
±27
±23
±19
±15
±11
±7
±35
±31
±27
±23
±19
±15
±11
±7
Each Tone Amplitude (dBFS)
C015
Each Tone Amplitude (dBFS)
C016
Figure 114. IMD vs Input Amplitude (46 MHz and 50 MHz)
Figure 115. IMD vs Input Amplitude (185 MHz and 190 MHz)
73
100
Dither_EN
Dither_EN
Dither_DIS
95
72
Dither_DIS
90
85
80
75
70
65
71
70
69
68
67
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Frequency (MHz)
C017
C018
Figure 116. SNR vs Input Frequency
Figure 117. SFDR vs Input Frequency
Copyright © 2014, Texas Instruments Incorporated
39
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J42 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
73
72
71
70
69
68
67
66
65
64
120
110
100
90
10 MHz
70 MHz
170 MHz
270 MHz
10 MHz
70 MHz
100 MHz
230 MHz
400 MHz
100 MHz
230 MHz
400 MHz
170 MHz
270 MHz
80
70
60
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
C019
C020
Figure 118. SNR vs Digital Gain and Input Frequency
Figure 119. SFDR vs Digital Gain and Input Frequency
76
75.5
75
130
120
110
100
90
75.5
130
120
110
100
90
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
SNR(dBFS)
SFDR(dBc)
SFDR(dBFS)
75
74.5
74
74.5
74
73.5
73
80
73.5
73
80
72.5
72
70
70
60
72.5
72
60
71.5
71
50
50
40
71.5
71
40
70.5
70
30
30
20
-70
-60
-50
-40
-30
-20
-10
0
-70
-60
-50
-40
-30
-20
-10
0
Amplitude (dBFS)
Amplitude (dBFS)
C021
C022
Figure 120. Performance Across Input Amplitude (30 MHz)
Figure 121. Performance Across Input amplitude (170 MHz)
73.25
97
96
95
94
93
92
72
71.5
71
87
86
85
84
83
82
81
SNR
SNR
SFDR
SFDR
73
72.75
72.5
72.25
72
70.5
70
69.5
69
0.85
0.9
0.95
1
1.05
1.1
0.85
0.9
0.95
1
1.05
1.1
Input Common-Mode Voltage (V))
Input Common-Mode Voltage (V))
C023
C024
Figure 122. Performance vs Input Common-Mode Voltage
(30 MHz)
Figure 123. Performance vs Input Common-Mode Voltage
(170 MHz)
40
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
Typical Characteristics: ADC34J42 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
101
100
99
73.5
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
AVDD = 1.7
AVDD = 1.8
AVDD = 1.9
AVDD = 1.75
AVDD = 1.85
73
72.5
72
98
97
71.5
71
96
95
±40
±15
10
35
60
85
±40
±15
10
35
60
85
Temperature (oC)
Temperature (oC)
C025
C026
Figure 124. SFDR vs AVDD Supply and Temperature
Figure 125. SNR vs AVDD Supply and Temperature
100
99
98
97
96
95
73
72.75
72.5
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
DVDD = 1.7
DVDD = 1.8
DVDD = 1.9
DVDD = 1.75
DVDD = 1.85
72.25
72
71.75
71.5
±40
±15
10
35
60
85
±40
±15
10
35
60
85
Temperature (oC)
Temperature (oC)
C027
C028
Figure 126. SFDR vs DVDD Supply and Temperature
Figure 127. SNR vs DVDD Supply and Temperature
80
105
100
95
80
90
85
80
75
70
65
SNR
SFDR
78
75
75
73
70
68
65
70
65
60
55
90
85
80
SNR
SFDR
75
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Differential Clock Amplitudes (Vpp)
Differential Clock Amplitudes (Vpp)
C029
C030
Figure 128. Performance vs Clock Amplitude (40 MHz)
Figure 129. Performance vs Clock Amplitude (150 MHz)
Copyright © 2014, Texas Instruments Incorporated
41
ADC34J42, ADC34J43, ADC34J44, ADC34J45
ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
www.ti.com.cn
Typical Characteristics: ADC34J42 (continued)
Typical values are at TA= 25°C, ADC sampling rate = 50 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
72
71.5
71
100
95
90
85
80
75
73.5
105
100
95
SNR
SNR
SFDR
SFDR
73
72.5
72
90
70.5
70
71.5
71
85
80
69.5
30
40
50
60
70
30
40
50
60
70
Input Clock Duty Cycle (%)
Input Clock Duty Cycle (%)
C031
C032
Figure 130. Performance vs Clock Duty Cycle (40 MHz)
Figure 131. Performance vs Clock Duty Cycle (150 MHz)
35
29.26
30
25
20
15
23.35
21.22
10.84
9.94
10
5
2.96
1.68
0.4
0.02
0.03
0.3
0
0
0
0
Output Code (LSB)
RMS noise = 1.3 LSBs
C033
Figure 132. Idle Channel Histogram
42
Copyright © 2014, Texas Instruments Incorporated
ADC34J42, ADC34J43, ADC34J44, ADC34J45
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ZHCSCR5B –MAY 2014–REVISED NOVEMBER 2014
7.19 Typical Characteristics: Common Plots
Typical values are at TA= 25°C, ADC sampling rate = 160 MSPS, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS
differential input, 2-VPP full-scale, and 32k-point FFT, unless otherwise noted.
0
±20
±35
±40
±45
±50
±55
±60
±65
Input Frequency = 30MHz
50-mVPP Signal Superimposed on VCM
±40
±60
±80
±100
±120
0
30
60
90
120 150 180 210 240 270 300
0
16
32
48
64
80
Common-Mode Test Signal Frequency (MHz))
C041
Frequency (MHz)
C040
fS = 160 MSPS, fCM = 10 MHz, 50 mVPP, fIN = 30 MHz, Amplitude
(fIN + fCM ) = –98 dBFS, Amplitude (fIN – fCM ) = –91 dBFS
Figure 134. CMRR vs Test Signal Frequency
Figure 133. CMRR FFT
0
±25
±30
±35
±40
±45
±50
±55
±60
Input Frequency = 30MHz
50-mVPP Signal Superimposed on AVDD
±20
±40
±60
±80
±100
±120
0
30
60
90
120 150 180 210 240 270 300
0
16
32
48
64
80
Test Signal Frequency On Supply (MHz)
C043
Frequency (MHz)
C042
fS = 160 MSPS, fPSRR = 5 MHz, 50 mVPP, fIN = 30 MHz, Amplitude
(fIN + fPSRR ) = –65 dBFS, Amplitude (fIN – fPSRR ) = –67 dBFS
Figure 136. PSRR vs Test Signal Frequency
Figure 135. PSRR FFT for AVDD Supply
1.0
1.0
0.8
0.6
0.4
0.2
0.0
AVDD_POWER
AVDD_POWER
DVDD_POWER
TOTAL_POWER
DVDD_POWER
0.8
TOTAL_POWER
0.6
0.4
0.2
0.0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Sampling Speed (MSPS)
Sampling Speed (MSPS)
C048
C049
Figure 137. Power vs Sampling Frequency 20x Mode
Figure 138. Power vs Sampling Frequency 40x Mode
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7.20 Typical Characteristics: Contour Plots
Typical values are at TA= 25°C, 50% clock duty cycle, AVDD = DVDD = 1.8 V, –1-dBFS differential input, 2-VPP
full-scale, and 32k-point FFT, unless otherwise noted.
160
90
75
80
70
85
140
120
100
80
90
85
75
80
70
90
60
85
80
75
70
90
50
100
150
200
250
300
350
400
90
Input Frequency, MHz
70
75
80
85
Figure 139. Spurious-Free Dynamic Range (SFDR) for 0-dB Gain
160
68
84
76
80
84
88
72
140
120
100
80
80
76
84
88
72
60
72
88
80
76
84
50
100
150
200
250
300
350
400
450
88
Input Frequency, MHz
68
70
72
74
76
78
80
82
84
86
Figure 140. Spurious-Free Dynamic Range (SFDR) for 6-dB Gain
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Typical Characteristics: Contour Plots (continued)
160
66
71.5
71
70.5
72
67
68
70
140
120
100
80
69
72.5
70.5
71.5
68
71
72
70
69
72.5
60
70.5
71.5
68
69
70
71
72
50
100
150
200
250
300
350
400
Input Frequency, MHz
66
67
68
69
70
71
72
Figure 141. Signal-to-Noise Ratio (SNR) for 0-dB Gain
160
63.2
63.8
64.4
66.2
65.4
66.6
65
140
120
100
80
65.8
65.4
66.2
65
66.6
65.8
64.
65.8
60
65.4
66.6
65
66.2
50
100
150
200
250
300
350
400
450
Input Frequency, MHz
62.5
63
63.5
64
64.5
65
65.5
66
66.5
Figure 142. Signal-to-Noise Ratio (SNR) for 6-dB Gain
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8 Parameter Measurement Information
8.1 Timing Diagrams
N + Latency + 2
N + 4
N + 3
N + Latency + 1
N + Latency
N + 2
Sample
N
N + 1
tA
CLKP
CLKM
Input
Clock
ADC Latency(1)
tD
DxP, DxM(2)
N - Latency-1
N + Latency
N - Latency+1 N - Latency+2 N - Latency+3
N - 1
N
N + 1
N + 1
(1) Overall latency = ADC latency + tD.
(2) x = A for channel A and B for channel B.
Figure 143. ADC Latency
CLKINP
Input
Clock
CLKINM
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Asserted Latency
CGS Phase
DxP, DxM(1)
Data
Data
Data
Data
Data
Data
Data
Data
Data
K28.5
(1) x = A for channel A and B for channel B.
Figure 144. SYNC~ Latency in CGS Phase (Two-Lane Mode)
CLKINP
CLKINM
Input
Clock
tSU_SYNC~
tH_SYNC~
SYNC~
tD
SYNC~ Deasserted Latency
ILA Sequence
DxP, DxM(1)
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.5
K28.0
K28.0
(1) x = A for channel A and B for channel B.
Figure 145. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
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Timing Diagrams (continued)
Sample N
tSU_SYSREF
tH_SYSREF
CLKIN
SYSREF
Figure 146. SYSREF Timing (Subclass 1)
Sample N
tSU_SYNC~
tH_SYNC~
CLKIN
SYNC~
Figure 147. SYNC~ Timing (Subclass 2)
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9 Detailed Description
9.1 Overview
The ADC34J4x are a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-
digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency
signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock
architecture design while the SYSREF input enables complete system synchronization. The devices support a
JESD204B interface in order to reduce the number of interface lines, thus allowing for high system integration
density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over
only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20
to derive the bit clock which is used to serialize the 14-bit data from each channel. The devices support subclass
1 with interface speeds up to 3.2 Gbps.
9.2 Functional Block Diagram
DAP,
DAM
Digital
Encoder and
JESD204B
INAP,
INAM
14-Bit
ADC
OVRA
DBP,
DBM
Digital
Encoder and
JESD204B
INBP,
INBM
14-Bit
ADC
OVRB
CLKP,
CLKM
Divide
by 1,2,4
PLL
SYNCP,
SYNCM
SYSREFP,
SYSREFM
DCP,
DCM
Digital
Encoder and
JESD204B
INCP,
INCM
14-Bit
ADC
OVRC
DDP,
DDM
Digital
Encoder and
JESD204B
INDP,
INDM
14-Bit
ADC
OVRD
Common
Mode
VCM
Configuration Registers
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9.3 Feature Description
9.3.1 Analog Inputs
The ADC34J4x analog signal inputs are designed to be driven differentially. Each input pin (INP, INM) must
swing symmetrically between (VCM + 0.5 V) and (VCM – 0.5 V), resulting in a 2-VPP (default) differential input
swing. The input sampling circuit has a 3-dB bandwidth that extends up to 450 MHz (50-Ω source driving 50-Ω
termination between INP and INM).
9.3.2 Clock Input
The device clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to 1.4 V
using internal 5-kΩ resistors. The self-bias clock inputs of the ADC34J4x can be driven by the transformer-
coupled, sine-wave clock source or by the ac-coupled, LVPECL and LVDS clock sources, as shown in
Figure 148, Figure 149, and Figure 150. See Figure 151 for details regarding the internal clock buffer.
0.1 mF
0.1 mF
Zo
CLKP
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100 W
0.1 mF
CLKM
Device
0.1 mF
Zo
CLKM
NOTE: RT = termination resistor, if necessary.
Device
Figure 148. Differential Sine-Wave Clock Driving
Circuit
Figure 149. LVDS Clock Driving Circuit
0.1 mF
Zo
CLKP
150 W
Typical LVPECL
Clock Input
100 W
0.1 mF
Zo
CLKM
Device
150 W
Figure 150. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
CEQ
CEQ
5 kW
1 pF
RESR
100 W
1.4 V
LPKG
2 nH
5 kW
20 W
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 151. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 152. However, for best performance the clock inputs must be driven differentially,
thereby reducing susceptibility to common-mode noise. For high input frequency sampling, TI recommends using
a clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter.
There is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
0.1 mF
CLKM
Device
Figure 152. Single-Ended Clock Driving Circuit
9.3.2.1 SNR and Clock Jitter
The signal-to-noise ratio of the ADC is limited by three different factors, as shown in Equation 1. Quantization
noise is typically not noticeable in pipeline converters and is 86 dB for a 14-bit ADC. Thermal noise limits SNR at
low input frequencies while the clock jitter sets SNR for higher input frequencies.
2
2
2
SNRQuantizatoin
SNR
SNR
Jitter
Noise
§
·
¸
Thermal Noise
§
·
¸
§
·
¸
ꢁ
ꢁ
ꢁ
¨
20
20
20
¨
¨
SNRADC[dBc] ꢁ20log 10
ꢀ 10
ꢀ 10
¨
©
¸
¹
¨
©
¸
¨
©
¸
¹
¹
(1)
(2)
The SNR limitation resulting from sample clock jitter can be calculated with Equation 2:
SNRJitter[dBc] ꢀ20log(2S fin TJitter )
The total clock jitter (TJitter) has two components: the internal aperture jitter (200 fs for the device) which is set by
the noise of the clock input buffer and the external clock. TJitter can be calculated with Equation 3:
2
TJitter (TJitter,Ext.Clock _ Input )2 ꢀ(TAperture_ ADC
)
(3)
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External clock jitter can be minimized by using high-quality clock sources and jitter cleaners as well as band-pass
filters at the clock input while a faster clock slew rate improves the ADC aperture jitter. The devices have a
thermal noise of 73 dBFS and internal aperture jitter of 200 fs. The SNR, depending on amount of external jitter
for different input frequencies, is shown in Figure 153.
73
72
71
70
69
68
67
66
65
Ext Clock Jitter
35 fs
50 fs
100 fs
150 fs
200 fs
10
100
1000
Input Frequency (MHz)
D036
Figure 153. SNR vs Frequency vs Jitter
9.3.2.2 Input Clock Divider
The devices are equipped with an internal divider on the clock input. The divider allows operation with a faster
input clock, thus simplifying the system clock distribution design. The clock divider can be bypassed (divide-by-1)
for operation with a 160-MHz clock while the divide-by-2 option supports a maximum input clock of 320 MHz and
the divide-by-4 option provides a maximum input clock frequency of 640 MHz.
9.3.3 Power-Down Control
The power-down functions of the ADC34J4x can be controlled either through the parallel control pin (PDN) or
through an SPI register setting (see register Figure 181, register 15h). The PDN pin can also be configured via
SPI to a global power-down or standby functionality, as shown in Table 3.
Table 3. Power-Down Modes
FUNCTION
Global power-down
Standby
POWER CONSUMPTION (mW)
WAKE-UP TIME (µs)
5
85
35
118
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9.3.4 Internal Dither Algorithm
The ADC34J4x uses an internal dither algorithm to achieve high SFDR and a clean spectrum. However, the
dither algorithm marginally degrades SNR, creating a trade-off between SNR and SFDR. If desired, the dither
algorithm can be turned off by using the DIS DITH CHx registers bits. Figure 154 and Figure 155 show the effect
of using dither algorithms.
0
±20
0
±20
±40
±40
±60
±60
±80
±80
±100
±120
±100
±120
0
16
32
48
64
80
0
16
32
48
64
80
Frequency (MHz)
Frequency (MHz)
C003
C004
fS = 160 MSPS, SNR = 71.4 dBFS, fIN = 70 MHz,
SFDR = 86 dBc
fS = 160 MSPS, SNR = 71.8 dBFS, fIN = 70 MHz,
SFDR = 85 dBc
Figure 154. FFT with Dither On
Figure 155. FFT with Dither Off
9.3.5 JESD204B Interface
The ADC34J4x support device subclass 0, 1, and 2 with a maximum output data rate of 3.2 Gbps for each serial
transmitter, as shown in Figure 156. The data of each ADC are serialized by 20x using an internal PLL and then
transmitted out on one differential pair each. An external SYSREF (subclass 1) or SYNC (subclass 2) signal is
used to align all internal clock phases and the local multiframe clock to a specific sampling clock edge. This
process allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty.
SYSREF SYNC
JESD204B
DA
INA
INB
DB
DC
JESD
204B
INC
IND
DD
Sample
Clock
Figure 156. JESD204B Interface
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The JESD204B transmitter block consists of the transport layer, the data scrambler, and the link layer, as shown
in Figure 157. The transport layer maps the ADC output data into the selected JESD204B frame data format and
manages if the ADC output data or test patterns are being transmitted. The link layer performs the 8b/10b data
encoding as well as the synchronization and initial lane alignment using the SYNC input signal. Optionally data
from the transport layer can be scrambled.
JESD204B Block
Transport Layer
Link Layer
Frame Data
Mapping
8b, 10b
Encoding
DA
DB
DC
DD
Scrambler
1+x14+x15
Comma Characters
Initial Lane Alignment
Test Patterns
Figure 157. JESD204B Block
9.3.5.1 JESD204B Initial Lane Alignment (ILA)
The initial lane alignment process is started by the receiving device by asserting the SYNC signal. When a logic
high is detected on the SYNC input pins, the ADC34J4x starts transmitting comma (K28.5) characters to
establish code group synchronization. When synchronization is complete, the receiving device de-asserts the
SYNC signal and the ADC34J4x starts the initial lane alignment sequence with the next local multiframe clock
boundary. The ADC34J4x transmits four multiframes, each containing K frames (K is SPI programmable). Each
multiframe contains the frame start and end symbols; the second multiframe also contains the JESD204 link
configuration data.
9.3.5.2 JESD204B Test Patterns
There are three different test patterns available in the transport layer of the JESD204B interface. The ADC34J4x
supports a clock output, an encoded, and a PRBS (215 – 1) pattern. These patterns can be enabled via SPI
register writes and are located in address 2Ah (bits 7:6).
9.3.5.3 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
•
•
•
•
L is the number of lanes per link,
M is the number of converters per device,
F is the number of octets per frame clock period, and
S is the number of samples per frame.
Table 4 lists the available JESD204B format and valid range for the ADC34J4x. The ranges are limited by the
SERDES line rate and the maximum ADC sample frequency.
Table 4. LMFS Values and Interface Rate
MINIMUM ADC
SAMPLING RATE
(MSPS)
MAXIMUM ADC
SAMPLING RATE
(Msps)
MINIMUM
fSERDES (Mbps)
MAXIMUM
fSERDES (GSPS)
L
4
2
M
4
F
2
4
S
1
1
MODE
20x (default)
40x
15
10
300
400
160
80
3.2
3.2
4
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The detailed frame assembly for quad-channel mode is shown in Figure 158. The frame assembly configuration
can be changed from 20x (default) to 40x by setting the registers listed in Table 5.
Figure 158. JESD Frame Assembly
Table 5. Configuring 40x Mode
ADDRESS
2Bh
DATA
01h
30h
03h
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9.3.5.4 Digital Outputs
The ADC34J4x JESD204B transmitter uses differential CML output drivers. The CML output current is
programmable from 5 mA to 20 mA using SPI register settings. The output driver expects to drive a differential
100-Ω load impedance; place the termination resistors as close to the receiver inputs as possible to avoid
unwanted reflections and signal distortion. Because the JESD204B employs 8b, 10b encoding, the output data
stream is dc-balanced and ac-coupling can be used avoiding the need to match up common-mode voltages
between transmitter and receivers. Connect the termination resistors to the termination voltage as shown in
Figure 159.
Vterm
Rt = ZO
Rt = ZO
Transmission Line, Zo
0.1 PF
DAP, DBP
DAM, DBM
Receiver
0.1 PF
Figure 159. CML Output Connections
Figure 160 shows the data eye measurements of the device JESD204B transmitter against the JESD204B
transmitter mask at 3.125 Gbps (156.25 MSPS, 20x mode).
300
150
0
-150
-300
-200
-150
-100
-50
0
50
100
150
200
Time (ps)
Figure 160. Eye Diagram: 3.125 Gbps
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9.4 Device Functional Modes
9.4.1 Digital Gain
The input full-scale amplitude can be selected between 1 VPP to 2 VPP (default is 2 VPP) by choosing the
appropriate digital gain setting via an SPI register write. Digital gain provides an option to trade-off SNR for
SFDR performance. A larger input full-scale increases SNR performance (2 VPP recommended for maximum
SNR) while reduced input swing typically results in better SFDR performance. Table 6 lists the available digital
gain settings.
Table 6. Digital Gain vs Full-Scale Amplitude
DIGITAL GAIN (dB)
MAX INPUT VOLTAGE (VPP)
0
0.5
1
2.0
1.89
1.78
1.68
1.59
1.50
1.42
1.34
1.26
1.19
1.12
1.06
1.00
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
9.4.2 Overrange Indication
The ADC34J4x provides two different overrange indications. The normal OVR (default) is triggered if the final 14-
bit data output exceeds the maximum code value. The fast OVR is triggered if the input voltage exceeds the
programmable overrange threshold and is presented after just nine clock cycles, thus enabling a quicker reaction
to an overrange event. By default, the normal overrange indication is output on the OVRx pins (where x is A, B,
C, or D). The fast OVR indication can be presented on the overrange pins by using the EN FOVR register bit.
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9.5 Programming
The ADC34J4x can be configured using a serial programming interface, as described in this section.
9.5.1 Serial Interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), SDATA (serial interface data), and SDOUT (serial interface data
output) pins. Serially shifting bits into the device is enabled when SEN is low. Serial data SDATA are latched at
every SCLK rising edge when SEN is active (low). The serial data are loaded into the register at every 24th
SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are
ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can
function with SCLK frequencies from 20 MHz down to very low speeds (of a few hertz) and also with a non-50%
SCLK duty cycle.
9.5.1.1 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin (of durations greater than 10 ns); see Figure 161. If required, the serial
interface registers can be cleared during operation either:
1. Through a hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
9.5.1.1.1 Serial Register Write
The device internal register can be programmed with these steps:
1. Drive the SEN pin low,
2. Set the R/W bit to 0 (bit A15 of the 16-bit address),
3. Set bit A14 in the address field to 1,
4. Initiate a serial interface cycle by specifying the address of the register (A13 to A0) whose content must be
written, and
5. Write the 8-bit data that are latched in on the SCLK rising edge.
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Programming (continued)
Figure 161 and Table 7 show the timing requirements for the serial register write operation.
Register Address [13:0>]
A13 A12 A11 A1
Register Data [7:0]
SDATA
R/W
= 0
1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
Figure 161. Serial Register Write Timing Diagram
Table 7. Serial Interface Timing(1)
PARAMETER
MIN
> dc
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
SCLK frequency (equal to 1 / tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDIO setup time
)
20
25
ns
25
ns
tDH
SDIO hold time
25
ns
(1) Typical values are at 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, and AVDD = DVDD = 1.8 V, unless otherwise
noted.
9.5.1.1.2 Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back using the SDOUT pin.
This readback mode may be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. Given below is the procedure to read contents of serial registers:
1. Drive the SEN pin low.
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers.
3. Set bit A14 in the address field to 1.
4. Initiate a serial interface cycle specifying the address of the register (A13 to A0) whose content must be read.
5. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin.
6. The external controller can latch the contents at the SCLK rising edge.
7. To enable register writes, reset the R/W register bit to 0.
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When READOUT is disabled, the SDOUT pin is in a high-impedance mode. If serial readout is not used, the
SDOUT pin must float. Figure 162 shows a timing diagram of the serial register read operation. Data appear on
the SDOUT pin at the SCLK falling edge with an approximate delay (tSD_DELAY) of 20 ns, as shown in Figure 163.
Register Address [13:0]
A13 A12 A11 A1
Register Data: GRQ¶WꢀFDUH
D5 D4 D3 D2
SDATA
R/W
= 1
A0
D7
D7
D6
D6
D1
D1
D0
D0
1
Register Read Data [7:0]
SDOUT
SCLK
D5
D4
D3
D2
SEN
Figure 162. Serial Register Read Timing Diagram
SCLK
tSD_DELAY
SDOUT
Figure 163. SDOUT Timing Diagram
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9.5.2 Register Initialization
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a high pulse on the RESET pin, as shown in Figure 164 and Table 8.
Power
Supplies
t1
RESET
t2
t3
SEN
Figure 164. Initialization of Serial Registers after Power-Up
Table 8. Power-Up Timing
PARAMETER
Power-on delay
CONDITIONS
MIN
TYP
MAX
UNIT
ms
ns
Delay from power up to active
high RESET pulse
t1
t2
t3
1
Reset pulse width
Register write delay
Active high RESET pulse width
10
1000
Delay from RESET disable to
SEN active
100
ns
If required, the serial interface registers can be cleared during operation either:
1. Through hardware reset, or
2. By applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 06h)
high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.
In this case, the RESET pin is kept low.
9.5.3 Start-Up Sequence
After power-up, the sequence described in Table 9 can be used to set up the ADC34J4x for basic operation.
Table 9. Start-Up Settings
STEP
DESCRIPTION
REGISTER ADDRESS AND DATA
Supply all supply voltages. There is no required power supply sequence for
AVDD and DVDD
1
2
3
4
—
—
Pulse hardware reset (low to high to low) on pin 24
Optionally, configure the LMFS of the JESD204B interface in 40x mode,
LMFS = 2441 (default is 20x mode, LMFS = 4421)
Address 2Bh, data 01h
Address 30h, data 03h
Pulse SYNC~ from high to low to transmit data from k28.5 sync mode
—
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9.6 Register Map
Table 10. Serial Register Map
REGISTER
ADDRESS
REGISTER DATA
A[13:0] (Hex)
7
6
5
4
3
2
1
0
01
02
03
04
05
DIS DITH CHA
DIS DITH CHB
DIS DITH CHC
DIS DITH CHD
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHA GAIN EN
CHB GAIN EN
CHC GAIN EN
CHD GAIN EN
0
0
0
0
TEST PATTERN
EN
06
0
0
0
SPECIAL MODE1 CHA
RESET
07
08
0
0
0
0
0
0
SPECIAL MODE1 CHB
SPECIAL MODE1 CHC
EN FOVR
0
0
0
ALIGN TEST
PATTERN
09
0
0
0
SPECIAL MODE1 CHD
DATA FORMAT
0A
0B
0C
0D
0E
0F
15
27
CHA TEST PATTERN
CHC TEST PATTERN
CHA DIGITAL GAIN
CHC DIGITAL GAIN
CHB TEST PATTERN
CHD TEST PATTERN
CHB DIGITAL GAIN
CHD DIGITAL GAIN
CUSTOM PATTERN (13:6)
CUSTOM PATTERN (5:0)
CHC PDN CHD PDN
0
0
CHA PDN
CHB PDN
STANDBY
0
GLOBAL PDN
0
0
PDN PIN DISABLE
0
CLK DIV
0
0
0
TRP LAYER
TESTMODE EN
TXMIT LINKDATA
DIS
2A
SERDES TEST PATTERN
IDLE SYNC
FLIP ADC DATA
LANE ALIGN
FRAME ALIGN
2B
0
0
0
0
0
0
0
0
0
0
0
CTRL K
0
CTRL F
0
2F
30
31
34
SCR (SCR EN)
OCTETS PER FRAME
0
0
0
0
FRAMES PER MULTI FRAME
0
SUBCLASSV
0
0
0
0
0
0
0
OPTION SYNC
REG
3A
3B
3C
SYNC REQ
OUTPUT CURRENT SEL
LINK LAYER
RPAT
LINK LAYER TESTMODE SEL[2:0]
PULSE DET MODES
LMFC COUNT INIT
FORCE LMFC
COUNT
LMFC COUNT INIT
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Register Map (continued)
Table 10. Serial Register Map (continued)
REGISTER
ADDRESS
REGISTER DATA
A[13:0] (Hex)
7
0
0
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
5
4
0
0
0
0
0
0
0
0
3
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
SPECIAL
MODE2 CHA [1:0]
122
134
222
234
422
434
522
534
0
0
DIS DITH CHA
DIS DITH CHA
0
0
0
0
SPECIAL
MODE2 CHD [1:0]
0
0
DIS DITH CHD
DIS DITH CHD
SPECIAL
MODE2 CHB [1:0]
0
0
DIS DITH CHB
0
DIS DITH CHB
0
SPECIAL
MODE2 CHC [1:0]
DIS DITH CHC
DIS DITH CHC
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9.6.1 Serial Register Description
Figure 165. Register 01h
7
6
5
4
3
2
1
0
DIS DITH CHA
DIS DITH CHB
DIS DITH CHC
DIS DITH CHD
Table 11. Register 01h Description
Name
Description
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
DIS DITH CHA
00 = Default
11 = Dither is disabled, high SNR mode is selected for channel A. In this mode, SNR typically improves
by 0.5 dB at 70 MHz. Ensure that register 134 (bits 5 and 3) are also set to 11.
DIS DITH CHB
00 = Default
11 = Dither is disabled, high SNR mode is selected for channel B. In this mode, SNR typically improves
by 0.5 dB at 70 MHz. Ensure that register 434 (bits 5 and 3) are also set to 11.
DIS DITH CHC
00 = Default
11 = Dither is disabled, high SNR mode is selected for channel C. In this mode, SNR typically improves
by 0.5 dB at 70 MHz. Ensure that register 534 (bits 5 and 3) are also set to 11.
DIS DITH CHD
00 = Default
11 = Dither is disabled, high SNR mode is selected for channel D. In this mode, SNR typically improves
by 0.5 dB at 70 MHz. Ensure that register 234 (bits 5 and 3) are also set to 11.
Figure 166. Register 02h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CHA GAIN EN
Table 12. Register 02h Description
Name
Description
Bits 7:2
Bit 1
Must write 0
CHA GAIN EN
Enable digital gain control for channel A.
0 = Default
1 = Digital gain for channel A can be programmed with the CHA DIGITAL GAIN bits.
Bit 0
Must write 0
Figure 167. Register 03h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CHB GAIN EN
Table 13. Register 03h Description
Name
Description
Bits 7:2
Bit 1
Must be 0
CHB GAIN EN:
Enable digital gain control for channel B.
0 = Default
1 = Digital gain for channel B can be programmed with the CHB DIGITAL GAIN bits.
Bit 0
Must write 0
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Figure 168. Register 04h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CHC GAIN EN
Table 14. Register 04h Description
Name
Description
Bits 7:2
Bit 1
Must write 0
CHC GAIN EN
Enable digital gain control for channel C.
0 = Default
1 = Digital gain for channel C can be programmed with the CHC DIGITAL GAIN bits.
Bit 0
Must write 0
Figure 169. Register 05h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
CHD GAIN EN
Table 15. Register 05h Description
Name
Description
Bits 7:2
Bit 1
Must write 0
CHD GAIN EN:
Enable digital gain control for channel D
0 = Default
1 = Digital gain for channel D can be programmed with the CHD DIGITAL GAIN bits.
Bit 0
Must write 0
Figure 170. Register 06h
7
6
0
5
0
4
3
2
1
0
TEST
PATTERN EN
0
SPECIAL MODE1 CHA
RESET
Table 16. Register 06h Description
Name
Description
Bits 7:5
Bits 4:2
Must write 0
SPECIAL MODE1 CHA
010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
Bit 1
Bit 0
TEST PATTERN EN
This bit enables test pattern selection for the digital outputs.
0 = Normal operation
1 = Test pattern output enabled
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0.
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Figure 171. Register 07h
7
0
6
0
5
0
4
3
2
1
0
0
SPECIAL MODE1 CHB
EN FOVR
Table 17. Register 07h Description
Name
Description
Bits 7:5
Bits 4:2
Must write 0
SPECIAL MODE1 CHB
010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
Bit 1
Bit 0
EN FOVR
0 = Normal OVR on OVRx pins
1 = Enable fast OVR on OVRx pins
Must write 0
Figure 172. Register 08h
7
0
6
0
5
0
4
3
2
1
0
0
0
SPECIAL MODE1 CHC
Table 18. Register 08h Description
Name
Description
Bits 7:5
Bits 4:2
Must write 0
SPECIAL MODE1 CHC
010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
Bits 1:0
Must write 0
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Figure 173. Register 09h
7
0
6
0
5
0
4
3
2
1
0
ALIGN TEST
PATTERN
DATA
FORMAT
SPECIAL MODE1 CHD
Table 19. Register 09h Description
Name
Description
Bits 7:5
Bits 4:2
Must write 0
SPECIAL MODE1 CHD
010 = For frequencies < 120 MHz
111 = For frequencies > 120 MHz
Bit 1
Bit 0
ALIGN TEST PATTERN
This bit aligns test patterns across the outputs of four channels.
0 = Test patterns of four channels are free running.
1 = Test patterns of four channels are aligned.
DATA FORMAT: Digital output data format
0 = Twos complement
1 = Offset binary
Figure 174. Register 0Ah
7
6
5
4
3
2
1
0
CHA TEST PATTERN
CHB TEST PATTERN
Table 20. Register 0Ah Description
Name
Description
Bits 7:4
CHA TEST PATTERN
These bits control the test pattern for channel A after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101 = Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register
bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a
sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
Others = Do not use
Bits 3:0
CHB TEST PATTERN
These bits control the test pattern for channel B after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101= Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register
bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a
sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
Others = Do not use
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Figure 175. Register 0Bh
7
6
5
4
3
2
1
0
CHC TEST PATTERN
CHD TEST PATTERN
Table 21. Register 0Bh Description
Name
Description
Bits 7:4
CHC TEST PATTERN
These bits control the test pattern for channel C after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101= Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register
bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a
sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
Others = Do not use
Bits 3:0
CHD TEST PATTERN
These bits control the test pattern for channel D after the TEST PATTERN EN bit is set.
0000 = Normal operation
0001 = All 0's
0010 = All 1's
0011 = Toggle pattern: data alternate between 10101010101010 and 01010101010101.
0100 = Digital ramp: data increment by 1 LSB every clock cycle from code 0 to 16383.
0101= Custom pattern: output data are the same as programmed by the CUSTOM PATTERN register
bits.
0110 = Deskew pattern: data are 3AAAh.
1000 = PRBS pattern: data are a sequence of pseudo random numbers.
1001 = 8-point sine wave: data are a repetitive sequence of the following eight numbers that form a
sine-wave: 0, 2399, 8192, 13984, 16383, 13984, 8192, 2399.
Others = Do not use
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Figure 176. Register 0Ch
7
6
5
4
3
2
1
0
CHA TEST PATTERN
CHB TEST PATTERN
Table 22. Register 0Ch Description
Name
Description
Bits 7:4
CHA TEST PATTERN
In address 0Ch, these bits control the test pattern for channel A after the CHA GAIN EN bit is set. See
Table 23 for register settings.
Bits 3:0
CHB TEST PATTERN
In address 0Ch, these bits control the test pattern for channel B after the CHB GAIN EN bit is set. See
Table 23 for register settings.
Table 23. Channel Digital Gain
REGISTER VALUE
0000
DIGITAL GAIN (dB)
MAXIMUM INPUT VOLTAGE (VPP)
0
0.5
1
2.0
0001
1.89
1.78
1.68
1.59
1.50
1.42
1.34
1.26
1.19
1.12
1.06
1.00
0010
0011
1.5
2
0100
0101
2.5
3
0110
0111
3.5
4
1000
1001
4.5
5
1010
1011
5.5
6
1100
Figure 177. Register 0Dh
7
6
5
4
3
2
1
0
CHC TEST PATTERN
CHD TEST PATTERN
Table 24. Register 0Dh Description
Name
Description
Bits 7:4
CHC TEST PATTERN
In address 0Dh, these bits control the test pattern for channel C after the CHC GAIN EN bit is set. See
Table 23 for register settings.
Bits 3:0
CHD TEST PATTERN
In address 0Dh, these bits control the test pattern for channel D after the CHD GAIN EN bit is set. See
Table 23 for register settings.
Figure 178. Register 0Eh
7
6
5
4
3
2
1
0
CUSTOM PATTERN (13:6)
Table 25. Register 0Eh Description
Name
Description
Bits 7:0
CUSTOM PATTERN (13:6)
These bits set the 14-bit custom pattern (13:6) for all channels.
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Figure 179. Register 0Fh
7
6
5
4
3
2
1
0
0
0
CUSTOM PATTERN (5:0)
Table 26. Register 0Fh Description
Name
Description
Bits 7:2
CUSTOM PATTERN (5:0)
These bits set the 14-bit custom pattern (5:0) for all channels.
Bits 1:0
Must write 0
Figure 180. Register 13h
7
6
0
5
0
4
0
3
0
2
0
1
0
0
LOW SPEED MODE
0
Table 27. Register 13h Description
Name
Bit 7
Description
LOW SPEED MODE
Use this bit for sampling frequencies < 25 MSPS.
0 = Normal operation
1 = Low-speed mode enabled
Bits 6:0
Must write 0
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Figure 181. Register 15h
7
6
5
4
3
2
1
0
0
CONFIG PDN
PIN
CHA PDN
CHB PDN
CHC PDN
CHD PDN
STANDBY
GLOBAL PDN
Table 28. Register 15h Description
Name
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CHA PDN: Power-down channel A
0 = Normal operation
1 = Power-down channel A
CHB PDN: Power-down channel B
0 = Normal operation
1 = Power-down channel B
CHC PDN: Power-down channel C
0 = Normal operation
1 = Power-down channel C
CHD PDN: Power-down channel D
0 = Normal operation
1 = Power-down channel D
STANDBY
This bit places the ADCs of all four channels into standby.
0 = Normal operation
1 = Standby
Bit 2
GLOBAL PDN
Places device in global power down.
0 = Normal operation
1 = Global power-down
Bit 1
Bit 0
Must write 0
CONFIG PDN PIN
This bit configures the PDN pin as either global power-down or standby pin.
0 = Logic high voltage on the PDN pin sends places the into global power-down.
1 = Logic high voltage on the PDN pin places the device into standby.
Figure 182. Register 27h
7
6
5
0
4
0
3
0
2
0
1
0
0
0
CLK DIV
Table 29. Register 27h Description
Name
Description
Bits 7:6
CLK DIV: Internal clock divider for the input sampling clock
00 = Clock divider bypassed
01 = Divide-by-1
10 = Divide-by-2
11 = Divide-by-4
Bits 5:0
Must write 0
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Figure 183. Register 2Ah
7
6
5
4
3
2
1
0
TX LINK
FRAME ALIGN CONFIG DATA
DIS
TESTMODE
EN
FLIP ADC
DATA
SERDES TEST PATTERN
IDLE SYNC
LANE ALIGN
Table 30. Register 2Ah Description
Name
Bits 7:6
Description
SERDES TEST PATTERN:
These bits set the test patterns in the transport layer of the JESD204B interface.
00 = Normal operation
01 = Outputs clock pattern (output is 10101010)
10 = Encoded pattern (output is 1111111100000000)
11 = Output is 215 – 1
Bit 5
IDLE SYNC
This bit generates the long transport layer test pattern mode according to 5.1.6.3 clause of JESD204B
specification.
0 = Test mode disabled
1 = Test mode enabled
Bit 4
Bit 3
Bit 2
TESTMODE EN
This bit sets the output pattern when SYNC is high.
0 = Sync code is k28.5 (0xBCBC)
1 = Sync code is 0xBC50
FLIP ADC DATA
This bit sets the output pattern when SYNC is high.
0 = Normal operation
1 = Output data order is reversed: MSB – LSB
LANE ALIGN
This bit inserts a lane alignment character (K28.3) for the receiver to align to the lane boundary per
section 5.3.3.5 of the JESD204B specification.
0 = Normal operation
1 = Inserts lane alignment characters
Bit 1
Bit 0
FRAME ALIGN
This bit inserts a frame alignment character (K28.7) for the receiver to align to the frame boundary per
section 5.3.3.4 of the JESD204B specification.
0 = Normal operation
1 = Inserts frame alignment characters
TX LINK CONFIG DATA DIS
This bit disables the initial link alignment (ILA) sequence when SYNC is de-asserted.
0 = Normal operation
1 = ILA disabled
Figure 184. Register 2Bh
7
6
0
5
0
4
0
3
0
2
0
1
0
0
CTRL K
CTRL F
Table 31. Register 2Bh Description
Name
Description
Bits 7:2
Bit 1
Must write 0
CTRL K: Enable bit for number of frames per multiframe
0 = Default is 9 frames (20x mode) per multiframe
1 = Frames per multiframe can be set in register 31h
Bit 0
CTRL F: Enable bit for number of octets per frame
0 = 20x mode using one lane per ADC (default is F = 2)
1 = Octets per frame can be specified in register 30h
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Figure 185. Register 2Fh
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
SCRAMBLE EN
Table 32. Register 2Fh Description
Name
Bit 7
Description
SCRAMBLE EN
This bit scrambles the enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
Bits 6:0
Must write 0
Figure 186. Register 30h
7
6
5
4
3
2
1
0
OCTETS PER FRAME
Table 33. Register 30h Description
Name
Description
Bits 7:0
OCTETS PER FRAME
These bits set the number of octets per frame (F).
00000000 = 20x serialization: two octets per frame
00000011 = 40x serialization: four octets per frame
Figure 187. Register 31h
7
6
0
5
0
4
3
2
FRAMES PER MULTI FRAME
1
0
0
Table 34. Register 31h Description
Name
Description
Bits 7:5
Bits 4:0
Must write 0
FRAMES PER MULT IFRAME
These bits set the number of frames per multiframe.
After reset, the default settings for frames per multiframe are:
20x mode: K = 8 (for each mode, do not set K to a lower value).
Figure 188. Register 34h
7
6
5
4
0
3
0
2
0
1
0
0
0
SUBCLASS
Table 35. Register 34h Description
Name
Description
Bits 7:5
SUBCLASS
These bits set the JESD204B subclass.
000 = Subclass 0 (backward compatibility with JESD204A)
001 = Subclass 1 (deterministic latency using SYSREF signal)
010 = Subclass 2 (deterministic latency using SYNC detection)
Bits 4:0
Must write 0
Figure 189. Register 3Ah
7
6
5
0
4
0
3
2
1
0
0
SYNC REQ
SYNC REQ EN
OUTPUT CURRENT SEL
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Table 36. Register 3Ah Description
Name
Bit 7
Description
SYNC REQ
This bit generates a synchronization request only when the SYNC REQ EN register bit is set.
0 = Normal operation
1 = Generates sync request
Bit 6
SYNC REQ EN
0 = Sync request is made with the SYNCP~, SYNCM~ pins
1 = Sync request is made with the SYNC REQ register bit
Bits 5:4
Bits 3:1
Must write 0
OUTPUT CURRENT SEL: JESD output buffer current selection
Program current (mA)
000 =16
001 = 12
010 = 8
011 = 4
100 = 32
101 = 28
110 = 24
111 = 20
Bit 0
Must write 0
Figure 190. Register 3Bh
7
6
5
4
3
0
2
1
0
LINK LAYER
RPAT
LINK LAYER TESTMODE
PULSE DET MODES
Table 37. Register 3Bh Description
Name
Description
Bits 7:5
LINK LAYER TESTMODE
These bits generate a pattern according to clause 5.3.3.8.2 of the JESD204B document.
000 = Normal ADC data
001 = D21.5 (high frequency jitter pattern)
010 = K28.5 (mixed frequency jitter pattern)
011 = Repeat initial lane alignment (generates K28.5 character and repeat lane alignment sequences
continuously)
100 = 12 octet RPAT jitter pattern
Bit 4
LINK LAYER RPAT
This bit changes the running disparity in the modified RPAT pattern test mode (only when link layer test
mode = 100).
0 = normal operation
1 = changes disparity
Bit 3
Must write 0
Bits 2:0
PULSE DET MODES
These bits select different detection modes for SYSREF (subclass 1) and SYNC (subclass2).
Table 38. PULSE DET MODES Register Settings
D2
D1
D0
0
FUNCTIONALITY
Allow all pulses to reset input clock dividers
0
1
Don’t care
Don’t care
0
Do not allow reset of analog clock dividers
Don’t care
0 to 1 transition
1
Allow one pulse immediately after the 0 to1 transition to reset the divider
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Figure 191. Register 3Ch
7
6
5
4
3
2
1
0
FORCE LMFC
COUNT
LMFC COUNT INIT
RELEASE ILANE SEQ
Table 39. Register 3Ch Description
Name
Bit 7
Description
FORCE LMFC COUNT: Force LMFC count
0 = Normal operation
1 = Enables using different starting values for the LMFC counter
Bits 6:2
Bits 1:0
LMFC COUNT INIT
If SYSREF is transmitted to the digital block, the LMFC count resets to 0 and K28.5 stops transmitting
when the LMFC count reaches 31. The initial value that the LMFC count resets to can be set using
LMFC COUNT INIT. In this manner, the Rx can be synchronized early because the Rx receives the
LANE ALIGNMENT SEQUENCE early. The FORCE LMFC COUNT register bit must be enabled.
RELEASE ILANE SEQ
These bits delay the lane alignment sequence generation by 0, 1, 2, or 3 multiframes after the code
group synchronization.
00 = 0
01 = 1
10 = 2
11 = 3
Figure 192. Register 122h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
SPECIAL
MODE2 CHA [1:0]
Table 40. Register 122h Description
Name
Description
Bits 7:2
Bit 1:0
Must write 0
SPECIAL MODE2 CHA [1:0]
Always write 1 for better HD2 performance.
Figure 193. Register 134h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHA
DIS DITH CHA
Table 41. Register 134h Description
Name
Bits 7:6
Bit 5
Description
Must write 0
DIS DITH CHA
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bit 4
Bit 3
Must write 0
DIS DITH CHA
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel A. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bits 2:0
Must write 0
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Figure 194. Register 222h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SPECIAL
MODE2 CHD [1:0]
Table 42. Register 222h Description
Name
Description
Bits 7:2
Bit 1:0
Must write 0
SPECIAL MODE2 CHD [1:0]
Always write 1 for better HD2 performance.
Figure 195. Register 234h
7
0
6
0
5
4
0
3
2
0
1
0
0
DIS DITH CHD
DIS DITH CHD
0
Table 43. Register 234h Description
Name
Bits 7:6
Bit 5
Description
Must write 0
DIS DITH CHD
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bit 4
Bit 3
Must write 0
DIS DITH CHD
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel D. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bits 2:0
Must write 0
Figure 196. Register 422h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SPECIAL
MODE2 CHB [1:0]
Table 44. Register 422h Description
Name
Description
Bits 7:2
Bit 1:0
Must write 0
SPECIAL MODE2 CHB [1:0]
Always write 1 for better HD2 performance.
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Figure 197. Register 434h
7
0
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHB
DIS DITH CHB
Table 45. Register 434h Description
Name
Description
Bits 7:6
Bit 5
Must write 0
DIS DITH CHB
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bit 4
Bit 3
Must write 0
DIS DITH CHB
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel B. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bits 2:0
Must write 0
Figure 198. Register 522h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
SPECIAL
MODE2 CHC [1:0]
Table 46. Register 522h Description
Name
Description
Bits 7:2
Bit 1:0
Must write 0
SPECIAL MODE2 CHC [1:0]
Always write 1 for better HD2 performance.
Figure 199. Register 534h
7
6
0
5
4
0
3
2
0
1
0
0
0
DIS DITH CHC
DIS DITH CHC
0
Table 47. Register 534h Description
Name
Description
Bits 7:6
Bit 5
Must write 0
DIS DITH CHC
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bit 4
Bit 3
Must write 0
DIS DITH CHC
00 = Default
11 = Dither is disabled and high SNR mode is selected for channel C. In this mode, SNR typically
improves by 0.5 dB at 70 MHz. Ensure that register 01h (bits 3:2) are also set to 11.
Bits 2:0
Must write 0
76
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
Typical applications involving transformer-coupled circuits are discussed in this section. Transformers (such as
ADT1-1WT or WBC1-1) can be used up to 250 MHz to achieve good phase and amplitude balances at ADC
inputs. While designing the dc driving circuits, the ADC input impedance must be considered. Figure 200 and
Figure 201 show the impedance (Zin = Rin || Cin) across the ADC input pins.
10
6
5
4
3
2
1
1
0.1
0.01
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
0
100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
D024
D025
Figure 200. Differential Input Resistance, RIN
Figure 201. Differential Input Capacitance, CIN
10.2 Typical Applications
10.2.1 Driving Circuit Design: Low Input Frequencies
39 nH
0.1uF
INP
0.1uF
50
50
25
25
0.1uF
22 pF
50
50
INM
1:1
1:1
0.1uF
39 nH
VCM
Device
Figure 202. Driving Circuit for Low Input Frequencies
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Typical Applications (continued)
10.2.1.1 Design Requirements
For optimum performance, the analog inputs must be driven differentially. An optional 5-Ω to 15-Ω resistor in
series with each input pin can be kept to damp out ringing caused by package parasitics. The drive circuit may
have to be designed to minimize the impact of kick-back noise generated by sampling switches opening and
closing inside the ADC, as well as ensuring low insertion loss over the desired frequency range and matched
impedance to the source.
10.2.1.2 Detailed Design Procedure
A typical application using two back-to-back coupled transformers is shown in Figure 202. The circuit is optimized
for low input frequencies. An external R-C-R filter using 50-Ω resistors and a 22-pF capacitor is used. With the
series inductor (39 nH), this combination helps absorb the sampling glitches.
10.2.1.3 Application Curve
Figure 203 shows the performance obtained by using the circuit in Figure 202.
0
±20
±40
±60
±80
±100
±120
0
16
32
48
64
80
Frequency (MHz)
C001
fS = 160 MSPS, SNR = 72.3 dBFS, fIN = 10 MHz, SFDR = 87 dBc
Figure 203. Performance FFT at 10 MHz (Low Input Frequency)
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Typical Applications (continued)
10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
0.1 PF
10 ꢀ
INP
0.1 PF
15 ꢀ
25 ꢀ
0.1 PF
56 nH
10 pF
25 ꢀ
15 ꢀ
10 ꢀ
INM
1:1
1:1
0.1 PF
VCM
Device
Figure 204. Driving Circuit for Mid-Range Input Frequencies (100 MHz < fIN < 230 MHz)
10.2.2.1 Design Requirements
See the Design Requirements section for further details.
10.2.2.2 Detailed Design Procedure
When input frequencies are between 100 MHz to 230 MHz, an R-LC-R circuit can be used to optimize
performance, as shown in Figure 204.
10.2.2.3 Application Curve
Figure 205 shows the performance obtained by using the circuit shown in Figure 204.
0
±20
±40
±60
±80
±100
±120
0
16
32
48
64
80
Frequency (MHz)
C005
fS = 160 MSPS, SNR = 69.7 dBFS, fIN = 170 MHz,
SFDR = 83 dBc
Figure 205. Performance FFT at 170 MHz (Mid Input Frequency)
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Typical Applications (continued)
10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
0.1uF
10
0.1uF
INP
25
0.1uF
25
INM
1:1
1:1
10
0.1uF
VCM
Device
Figure 206. Driving Circuit for High Input Frequencies (fIN > 230 MHz)
10.2.3.1 Design Requirements
See the Design Requirements section for further details.
10.2.3.2 Detailed Design Procedure
For high input frequencies (> 230 MHz), using the R-C-R or R-LC-R circuit does not show significant
improvement in performance. However, a series resistance of 10 Ω can be used as shown in Figure 206.
10.2.3.3 Application Curve
Figure 207 shows the performance obtained by using the circuit shown in Figure 206.
0
±20
±40
±60
±80
±100
±120
0
16
32
48
64
80
Frequency (MHz)
C009
fS = 160 MSPS, SNR = 63.4 dBFS, fIN = 450 MHz,
SFDR = 63 dBc
Figure 207. Performance FFT at 450 MHz (High Input Frequency)
11 Power-Supply Recommendations
The device requires a 1.8-V nominal supply for AVDD and DVDD. There are no specific sequence power-supply
requirements during device power-up. AVDD and DVDD can power up in any order.
80
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12 Layout
12.1 Layout Guidelines
The ADC34J4x EVM layout can be used as a reference layout to obtain the best performance. A layout diagram
of the EVM top layer is provided in Figure 208. Some important points to remember while laying out the board
are:
1. Analog inputs are located on opposite sides of the device pin out to ensure minimum crosstalk on the
package level. To minimize crosstalk onboard, the analog input traces exit the pin out in opposite directions,
as shown in the reference layout of Figure 208 as much as possible.
2. In the device pin out, the sampling clock is located on a side perpendicular to the analog inputs in order to
minimize coupling between them. This configuration is also maintained on the reference layout of Figure 208
as much as possible.
3. Keep digital outputs away from the analog inputs. When these digital outputs exit the pin out, do not keep the
digital output traces parallel to the analog input traces because this configuration may result in coupling from
digital outputs to analog inputs and degrade performance. Design all digital output traces to the receiver
[such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)] to be
matched in length to avoid skew among outputs.
4. At each power-supply pin (AVDD and DVDD), keep a 0.1-µF decoupling capacitor close to the device. A
separate decoupling capacitor group consisting of a parallel combination of 10-µF, 1-µF, and 0.1-µF
capacitors can be kept close to the supply source.
12.2 Layout Example
ADC3xJxx
Analog
Input
Routing
Sampling
Clock
Routing
Digital
Output
Routing
Clock
Distribution IC
Figure 208. Typical Layout of the ADC34J4x Board
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13 器件和文档支持
13.1 相关链接
以下表格列出了快速访问链接。 范围包括技术文档、支持与社区资源、工具和软件，并且可以快速访问样片或购买
链接。
表 48. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持与社区
请单击此处
请单击此处
请单击此处
请单击此处
ADC34J42
ADC34J43
ADC34J44
ADC34J45
13.2 商标
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
13.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC34J42IRGZR
ADC34J42IRGZT
ADC34J43IRGZR
ADC34J43IRGZT
ADC34J44IRGZR
ADC34J44IRGZT
ADC34J45IRGZR
ADC34J45IRGZT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
RGZ
48
48
48
48
48
48
48
48
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
AZ34J42
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
NIPDAUAG
AZ34J42
AZ34J43
AZ34J43
AZ34J44
AZ34J44
AZ34J45
AZ34J45
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADC34J42IRGZR
ADC34J43IRGZR
ADC34J44IRGZR
ADC34J45IRGZR
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
2500
2500
2500
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
7.3
7.3
7.3
7.3
7.3
7.3
7.3
7.3
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADC34J42IRGZR
ADC34J43IRGZR
ADC34J44IRGZR
ADC34J45IRGZR
VQFN
VQFN
VQFN
VQFN
RGZ
RGZ
RGZ
RGZ
48
48
48
48
2500
2500
2500
2500
350.0
350.0
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48
7 x 7, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048D
VQFN - 1 mm max height
S
C
A
L
E
1
.
9
0
0
PLASTIC QUAD FLATPACK - NO LEAD
7.1
6.9
A
B
0.5
0.3
PIN 1 INDEX AREA
7.1
6.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
5.6 0.1
2X 5.5
(0.2) TYP
13
24
44X 0.5
12
25
EXPOSED
THERMAL PAD
2X
49
SYMM
5.5
SEE TERMINAL
DETAIL
1
36
0.30
48X
0.18
37
48
PIN 1 ID
(OPTIONAL)
SYMM
0.1
C A B
0.5
0.3
48X
0.05
4219046/B 11/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
5.6)
SYMM
48
37
48X (0.6)
1
36
48X (0.24)
6X
(1.22)
44X (0.5)
SYMM
10X
(1.33)
49
(6.8)
(R0.05)
TYP
(
0.2) TYP
VIA
25
12
13
24
10X (1.33)
6X (1.22)
(6.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:12X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219046/B 11/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048D
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.665 TYP)
(1.33) TYP
16X ( 1.13)
37
48
48X (0.6)
49
36
1
48X (0.24)
44X (0.5)
(1.33)
TYP
(0.665)
TYP
SYMM
(6.8)
(R0.05) TYP
25
12
METAL
TYP
13
24
SYMM
(6.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 49
66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:15X
4219046/B 11/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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