ADC34RF52IRTDT [TI]
Quad-channel, 14-bit, 1.5-GSPS low-noise spectral density (NSD) RF-sampling ADC
| RTD | 64 | -40 to 85;
| 型号： | ADC34RF52IRTDT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quad-channel, 14-bit, 1.5-GSPS low-noise spectral density (NSD) RF-sampling ADC | RTD | 64 | -40 to 85 |
| 文件： | 总107页 (文件大小：4255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADC34RF52
ZHCSPO3 –MARCH 2023
ADC34RF52 四通道14 位1.5GSPS 射频采样数据转换器
1 特性
3 说明
• 14 位四通道1.5GSPS ADC
• 噪声频谱密度：
– 未求平均值时为-153dBFS/Hz
– 取2 次平均值时为-156dBFS/Hz
• 单核（非交错）ADC 架构
• 孔径抖动：50fs
• 低近端残留相位噪声：
– 10kHz 偏移时为-133dBc/Hz
• 频谱性能（fIN = 900MHz，–4dBFS）：
ADC34RF52 是一款单核 14 位、1.5GSPS 双通道模
数转换器(ADC)，支持输入频率高达2.5GHz 的射频采
样。该设计更大限度地提高了信噪比 (SNR) 并提供
-153dBFS/Hz 的噪声频谱密度。使用额外的内部 ADC
以及片上信号平均，噪声密度提高到-156dBFS/Hz。
每个 ADC 通道都可以使用支持相位同调的 48 位NCO
连接到双频带数字下变频器 (DDC)。使用 GPIO 引脚
进行NCO 频率控制，可以在不到1µs 的时间内实现跳
频。
– 2x 内部平均
– SNR：65.2dBFS
– SFDR HD2,3：74dBc
ADC34RF52 支持具有子类 1 确定性延迟的
JESD204B 串行数据接口，使用高达 13Gbps 的数据
速率。每个ADC 通道只有2 条串行器/解串器通道。
– SFDR 最严重毛刺：90dBFS
• 满量程输入：1.0/1.1Vpp (1/1.8dBm)
• 全功率输入带宽(-3dB)：1.6 GHz
• JESD204B 串行数据接口
高能效 ADC 架构在 1.5GSPS 时的功耗为 0.73W/通
道，并以较低的采样率提供功率调节。
器件信息
封装(1)
– 最大通道速率：13 Gbps
– 支持子类1 确定性延迟
• 数字下变频器
器件型号
最大采样率
ADC34RF52
QFN (64)
1.5GSPS
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
– 每个ADC 通道最多两个DDC
– 复杂输出：4x 至128x 抽取
– 48 位NCO 相位同调跳频
– 快速跳频：< 1µs
DDC
NCO
DDC
100
100
N
DOUT0/1P/M
DOUT2/3P/M
ADC
INAP/M
• 功耗：0.73W/通道(1x AVG)
• 电源：1.8 V/1.2 V
DDC
DDC
NCO
N
ADC
INBP/M
CLKP/M
2 应用
• 相控阵雷达
• 频谱分析仪
• 软件定义无线电(SDR)
• 电子战
• 高速数字转换器
• 电缆基础设施
• 通信基础设施
SYSREFP/M
INCP/M
DDC
DDC
NCO
100
100
DOUT4/5P/M
DOUT6/7P/M
N
ADC
DDC
DDC
NC
NCO
N
INDP/M
ADC
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAI7
ADC34RF52
ZHCSPO3 –MARCH 2023
www.ti.com.cn
Table of Contents
7.2 Functional Block Diagram.........................................25
7.3 Feature Description...................................................26
7.4 Device Functional Modes..........................................58
7.5 Programming............................................................ 59
7.6 Register Maps...........................................................61
8 Application Information Disclaimer.............................84
8.1 Application Information............................................. 84
8.2 Typical Application.................................................... 84
8.3 Initialization Set Up................................................... 87
8.4 Power Supply Recommendations.............................97
8.5 Layout....................................................................... 98
9 Device and Documentation Support..........................100
9.1 接收文档更新通知................................................... 100
9.2 支持资源..................................................................100
9.3 Trademarks.............................................................100
9.4 静电放电警告.......................................................... 100
9.5 术语表..................................................................... 100
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics - Power Consumption.........6
6.6 Electrical Characteristics - DC Specifications.............7
6.7 Electrical Characteristics - AC Specifications
(Dither DISABLED)........................................................9
6.8 Electrical Characteristics - AC Specifications
(Dither ENABLED).......................................................11
6.9 Timing Requirements................................................13
6.10 Typical Characteristics............................................15
7 Detailed Description......................................................25
7.1 Overview...................................................................25
Information.................................................................. 100
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2023
*
Initial Release
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5 Pin Configuration and Functions
DOUT1P
DOUT1M
DVDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DOUT5P
2
DOUT5M
DVDD
3
DOUT0P
DOUT0M
DGND
4
DOUT4P
DOUT4M
DGND
DVDD
5
6
DVDD
7
DGND
8
DGND
DVDD
Thermal
Pad
DVDD
9
SPISEL
RESETb
AGND
10
11
12
13
14
15
16
GPIO1
GPIO2
AGND
AVDD12
INAP
AVDD12
INCP
INAM
INCM
AVDD12
AVDD12
Not to scale
图5-1. RTD Package, 64 Pin QFN (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
ANALOG INPUTS
INAP
14
15
18
19
35
34
31
30
26
I
I
I
Differential analog input for channel A. 100 Ωdifferential internal termination.
Differential analog input for channel B. 100 Ωdifferential internal termination.
Differential analog input for channel C. 100 Ωdifferential internal termination.
INAM
INBP
INBM
INCP
INCM
INDP
I
Differential analog input for channel D. 100 Ωdifferential internal termination.
INDM
VCM
O
Common-mode voltage output for the analog inputs.
CLOCK, SYNCHRONIZATION
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表5-1. Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
23
CLKP
I
I
Differential sampling clock input. 100 Ωdifferential internal termination.
CLKM
24
SYSREFP
SYSREFM
CONTROL
RESETb
27
Differential external synchronization input.
28
11
57
I
I
Hardware reset. Active low. This pin has an internal 21 kΩpull-up resistor to AVDD18.
Serial interface enable. Active low. This pin has an internal 21 kΩpull-up resistor to
AVDD18.
SEN
SCLK
SDIO
55
56
I
Serial interface clock input. This pin has an internal 21 kΩpull-down resistor.
I/O
Serial interface data input and output. This pin has an internal 21 kΩpull-down resistor.
GPIO control pin. This pin is configured through SPI interface for power down or NCO
control function.
GPIO1
GPIO2
SPISEL
39
38
10
I/O
I/O
I
GPIO control pin. This pin is configured through SPI interface for power down or NCO
control function.
Determines the functional of the SPI interface pins: either normal SPI for register
programming or fast access to NCO selection only for fast frequency hopping.
DIGITAL DATA INTERFACE
DOUT0P
DOUT0M
DOUT1P
DOUT1M
DOUT2P
DOUT2M
DOUT3P
DOUT3M
DOUT4P
DOUT4M
DOUT5P
DOUT5M
DOUT6P
DOUT6M
DOUT7P
DOUT7M
POWER SUPPLY
AVDD18
4
O
O
O
O
O
O
O
O
5
1
2
63
64
60
61
45
44
48
47
50
49
53
52
JESD204B high-speed serial data output interface pins for channels A to D.
Output lanes can be reordered using the output MUX.
17,20,29,32, 58
13,16,21,33, 36
I
I
Analog 1.8-V power supply
Analog 1.2-V power supply
AVDD12
Clock 1.2-V power supply. Very sensitive to power supply noise. Directly impacts close in
aperture phase noise.
CLKVDD
DVDD
25
I
I
3,7,9,40,42,
46,54,59
Digital 1.2-V power supply
AGND
12,37
22
I
I
I
Analog ground, shorted to thermal pad.
Clock ground.
CLKGND
DGND
6,8,41,43,51,62
Digital ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
–0.3
–0.3
–0.6
–0.3
–0.3
MAX UNIT
Supply voltage range, AVDD18
2.1
1.4
V
V
V
V
V
Supply voltage range, AVDD12, CLKVDD, DVDD
INAP/M, INBP/M, INCP/M, INDP/M
CLKP/M
1.2
CLKVDD + 0.3
AVDD12 + 0.6
Voltage applied to input pins
SYSREFP/M
GPIO1/2, PDN, RESET, SCLK, SEN, SDIO,
SPISEL
AVDD18 + 0.2
V
–0.3
Peak RF input power (INAP/M, INBP/M, INCP/M,
INDP/M)
12 dBm
Differential 100 Ω termination.
Junction temperature, TJ
Storage temperature, Tstg
Junction temperature, TJ
Storage temperature, Tstg
115
150
°C
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
± 1000
± 500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002((2))
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.75
NOM
1.8
MAX UNIT
AVDD18
AVDD12
CLKVDD
DVDD
1.8 V analog supply
1.85
1.225
1.225
1.225
85
V
V
1.2 V analog supply
1.15
1.2
1.2 V clock supply
1.175
1.15
1.2
V
1.2 V digital supply
1.2
V
TA
Operating free-air temperature
Operating junction temperature
Maximum Operating Junction Temperature Range
°C
–40
105(1)
TJ
°C
125
(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
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6.4 Thermal Information
ADC34RF5x
RTD (QFN)
64 Pins
20.1
THERMAL METRIC(1)
UNIT
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
6.8
5.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ΨJT
5.1
ΨJB
RΘJC(bot)
0.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics - Power Consumption
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FS = 1.5 GSPS
IAVDD18
IAVDD12
Supply current, 1.8 V analog supply
Supply current, 1.2 V analog supply
330
740
80
mA
W
Bypass mode, LMFS = 8-4-8-10
1x average
ICLKVDD Supply current, 1.2 V clock supply
IDVDD
Supply current, 1.2 V digital supply
Power dissipation
1110
2.92
500
1110
86
PDIS
IAVDD18
IAVDD12
Supply current, 1.8 V analog supply
Supply current, 1.2 V analog supply
mA
Bypass mode, LMFS = 8-4-8-10
2x average
ICLKVDD Supply current, 1.2 V clock supply
IDVDD
PDIS
Supply current, 1.2 V digital supply
Power dissipation
1410
4.05
W
POWER DOWN MODES
PDIS Power down mode power consumption
Fast wake up time
210
mW
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6.6 Electrical Characteristics - DC Specifications
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 1x AVG, 50% clock duty cycle,
AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
No missing codes
Differential nonlinearity
Integral nonlinearity
Offset error
14
bits
LSB
DNL
FIN = 10 MHz
FIN = 10 MHz
±0.9
±4
INL
LSB
VOS_ERR
GAINERR
±0.2
±0.2
%FSR
%FSR
Gain error
ADC ANALOG INPUTS (INAP/M, INBP/M, INCP/M, INDP/M)
1x or 2x AVG, RSW = 0
0.95
1.0
FS
Input full scale (differential)
1x AVG, RSW = 1
2x AVG, RSW = 1
Vpp
mV
1.1
VICM
ZIN
Input common model voltage
Differential input impedance
Output common mode voltage
250
350
100
350
1.6
450
Differential at 100 MHz
Ω
VOCM
mV
No averaging, RSW=1
2x averaging, RSW=1
BW
Analog Input Bandwidth (-3 dB)
GHz
1.5
Phase imbalance, analog input
Amplitude imablance, analog input
CLOCK INPUT (CLKP/M)
Input clock frequency
±2
deg
dB
±0.5
500
0.65
45
1500
2.4
MHz
Vpp
V
VID
Differential input voltage
1
0.75
100
50
VICM
ZIN
Input common mode voltage
Differential input impedance
0.85
Differential at 1.5 GHz
Ω
Clock duty cycle
55
%
SYSREF INPUT (SYSREFP/M)
VID
Differential input voltage
0.6
0.8
1.2
1
Vpp
V
VICM
ZIN
Input common mode voltage
Differential input termination
Input common mode voltage
1.05
1.4
100
Ω
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO, GPIO1/2, SPISEL)
VIH
VIL
CI
High-level input voltage
Low-level input voltage
Input capacitance
0.8
V
V
0.4
0.1
0.6
pF
DIGITAL OUTPUTS (SDIO)
AVDD18
–0.1
VOH
VOL
High-level output voltage
Low-level output voltage
ILOAD = -400 uA
ILOAD = 400 uA
V
V
CML SERDES OUTPUTS: DOUT[0..7]P/M
VOD
Serdes transmitter output amplitude
differential peak-peak
0.7
Vpp
V
Serdes transmitter output common
mode
VOCM
0.425
Serdes transmitter single ended
termination impedance
ZTX
50
Ω
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6.6 Electrical Characteristics - DC Specifications (continued)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 1x AVG, 50% clock duty cycle,
AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmitter pins shorted to any voltage
between –0.25 V and 1.45 V
Transmitter short-circuit current
100
mA
–100
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6.7 Electrical Characteristics - AC Specifications (Dither DISABLED)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 900 MHz, AIN = -20 dBFS
no averaging
-153.3
NSD
NF
Noise Spectral Density
dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging
-156.1
21.7
fIN = 900 MHz, AIN = -20 dBFS
no averaging
Noise Figure
dB
fIN = 900 MHz, AIN = -20 dBFS
2x averaging
19.7
fIN = 100 MHz
64.1
64.1
63.9
65.1
63.6
66.5
66.6
66.3
67.9
65.9
60.6
62.2
62.1
61.4
62.0
10.4
10.4
10.3
10.5
10.3
64
fIN = 600 MHz
Signal-to-noise ratio
no averaging
fIN = 900 MHz
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
SNR
dBFS
fIN = 100 MHz
fIN = 600 MHz
Signal-to-noise ratio
2x averaging
fIN = 900 MHz
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
Signal to noise and distortion
ratio
SINAD
ENOB
THD
fIN = 900 MHz
dBFS
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
Effective number of bits
fIN = 900 MHz
Bits
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
67
Total Harmonic Distortion (First
five harmonics)
fIN = 900 MHz
67
dBc
dBc
dBc
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
64
68
fIN = 100 MHz
72
fIN = 600 MHz
70
HD2
Second Harmonic Distortion
Third Harmonic Distortion
fIN = 900 MHz
71
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
68
69
fIN = 100 MHz
65
fIN = 600 MHz
73
HD3
fIN = 900 MHz
71
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
69
81
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6.7 Electrical Characteristics - AC Specifications (Dither DISABLED) (continued)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fIN = 100 MHz
fIN = 600 MHz
fIN = 900 MHz
82
83
Non
HD2,3
Spur free dynamic range
(excluding HD2 and HD3)
83
dBFS
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
93
81
Two tone inter-modulation
distortion
IMD3
f1 = 900 MHz, f2 = 1000 MHz, AIN = -7 dBFS/tone
81
dBFS
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6.8 Electrical Characteristics - AC Specifications (Dither ENABLED)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –4-dBFS differential input and dither ENABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(2)
TYP
MAX
UNIT
fIN = 900 MHz, AIN = -20 dBFS
no averaging
-151.0
-153.3
NSD(1)
Noise Spectral Density
dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging
-153.0
-156.1
21.6
fIN = 900 MHz, AIN = -20 dBFS
no averaging
NF(1)
Noise Figure
dB
fIN = 900 MHz, AIN = -20 dBFS
2x averaging
19.7
fIN = 100 MHz
63.6
64.4
64.4
65.2
63.8
66.3
66.9
66.8
68.0
66.1
62.2
63.4
63.6
64.4
62.8
10.3
10.4
10.4
10.5
10.3
68
fIN = 600 MHz
Signal-to-noise ratio
no averaging
fIN = 900 MHz
61.3
62.9
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
SNR(1)
dBFS
fIN = 100 MHz
fIN = 600 MHz
Signal-to-noise ratio
2x averaging
fIN = 900 MHz
63.9
64.9
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
Signal to noise and distortion
ratio
SINAD(1)
fIN = 900 MHz
dBFS
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
ENOB(1) Effective number of bits
fIN = 900 MHz
Bits
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
fIN = 100 MHz
fIN = 600 MHz
72
Total Harmonic Distortion (First
five harmonics)
THD
fIN = 900 MHz
72
dBc
dBc
dBc
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
72
71
fIN = 100 MHz
75
fIN = 600 MHz
75
HD2
HD3
Second Harmonic Distortion
Third Harmonic Distortion
fIN = 900 MHz
70
71
74
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
87
72
fIN = 100 MHz
70
fIN = 600 MHz
77
fIN = 900 MHz
79
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
74
81
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6.8 Electrical Characteristics - AC Specifications (Dither ENABLED) (continued)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –4-dBFS differential input and dither ENABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN(2)
TYP
MAX
UNIT
fIN = 100 MHz
fIN = 600 MHz
fIN = 900 MHz
92
89
Non
HD2,3
Spur free dynamic range
(excluding HD2 and HD3)
85
90
dBFS
fIN = 900 MHz, Ain = -20 dBFS
fIN = 1.4 GHz
97
94
Two tone inter-modulation
distortion
IMD3
f1 = 900 MHz, f2 = 1000 MHz, AIN = -10 dBFS/tone
74
84
dBFS
(1) Measured from 100 MHz to Nyquist (FS/2) excluding dither
(2) SNR, IMD3 minimum values are specified by ATE, HD2, HD3 and Non HD23 are specified by bench characterization.
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6.9 Timing Requirements
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM MAX
UNIT
ADC TIMING SPECIFICATIONS
Aperture Delay
TAD
0.17
0.07
50
ns
fs
Aperure Delay variation
TA
Aperture Jitter
3-dB overload condition
10
clock
cycles
Overload recovery time
6-dB overload condition
50
ADC
clock
cycles
ADC latency from sampling instant to internal
hand-off to digital
68
5
Internal propagation delay
ns
ADC
clock
cycles
Latency adder for 2x averaging
4
LMFS = 8-4-8-10
163
131
LMFS = 8-4-2-2
4x real decimation, LMFS = 8-4-2-2
4x decimation, F (number of octets) = 2
4x decimation, F = 4
456
394
374
4x decimation, F = 8
367
8x decimation, F = 2
560
8x decimation, F = 4
520
8x decimation, F = 8
506
8x decimation, F = 16
16x decimation, F = 2
16x decimation, F = 4
16x decimation, F = 8
16x decimation, F = 16
16x decimation, F = 32
32x decimation, F = 2
32x decimation, F = 4
32x decimation, F = 8
32x decimation, F = 16
32x decimation, F = 32
64x decimation, F = 2
64x decimation, F = 4
64x decimation, F = 8
64x decimation, F = 16
64x decimation, F = 32
128x decimation, F = 2
128x decimation, F = 4
128x decimation, F = 8
128x decimation, F = 16
128x decimation, F = 32
491
900
820
tADC
792
762
ADC
clock
cycles
748
Deterministic delay from digital block (DDC (if
used) and JESD interface)
1596
1436
1380
1320
1292
2940
2620
2508
2388
2332
5668
5028
4804
4564
4452
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6.9 Timing Requirements (continued)
Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.
Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 =
1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN NOM MAX
UNIT
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency
1
10
10
10
10
20
MHz
ns
tSU(SEN)
tH(SEN)
tSU(SDIO)
tH(SDIO)
SEN to rising edge of SCLK
SEN from rising edge of SCLK
SDIO to rising edge of SCLK
SDIO from rising edge of SCLK
ns
ns
ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD)
t(ODZ)
t(OD)
SDIO tri-state to driven
10
14
10
ns
ns
ns
SDIO data to tri-state
SDIO valid from falling edge of SCLK
TIMING: SYSREFP/M
Setup time, SYSREFP/M valid to rising edge
ts(SYSREF)
50
50
ps
ps
of CLKP/M
Hold time, SYSREFP/M valid to rising edge
of CLKP/M
th(SYSREF)
CML SERDES OUTPUTS: DOUT[0..7]P/M
fSerdes
RJ
Serdes bit rate
0.5
12.8 13.0
Gbps
ps
Random jitter, RMS
RPAT, 6.4 Gbps
0.7
0.6
RJ
Random jitter, RMS
RPAT, 12.8 Gbps
RPAT, 6.4 Gbps
RPAT, 12.8 Gbps
RPAT, 6.4 Gbps
RPAT, 12.8 Gbps
ps
DJ
Deterministic jitter, peak to peak
Deterministic jitter, peak to peak
Total jitter, peak to peak
Total jitter, peak to peak
8.9
ps
DJ
14.7
19.5
24
ps
TJ
ps
TJ
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6.10 Typical Characteristics
Typical values are at TA = 25°C, ADC sampling rate = 1.5 GSPS, 50% clock duty cycle, AVDD18 = 1.8 V,
AVDD12, CLKVDD, DVDD = 1.2 V and –1-dBFS differential input, Dither = DIS, unless otherwise noted
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 64.5 dBFS, HD23 = 77 dBc, Non HD23 = 84 dBFS
AIN = -1 dBFS, 1x AVG, Dither = DIS
SNR = 64.3 dBFS1, HD23 = 76 dBc, Non HD23 = 89 dBFS
AIN = -4 dBFS, 1x AVG, Dither = EN
图6-1. Single Tone FFT at FIN = 100 MHz
图6-2. Single Tone FFT at FIN = 100 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 64.4 dBFS, HD23 = 72 dBc, Non HD23 = 81 dBFS
AIN = -1 dBFS, 1x AVG, Dither = DIS
SNR = 64.4 dBFS1, HD23 = 75 dBc, Non HD23 = 84 dBFS
AIN = -4 dBFS, 1x AVG, Dither = EN
图6-3. Single Tone FFT at FIN = 600 MHz
图6-4. Single Tone FFT at FIN = 600 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 64.3 dBFS, HD23 = 72 dBc, Non HD23 = 84 dBFS
AIN = -1 dBFS, 1x AVG, Dither = DIS
SNR = 64.4 dBFS1, HD23 = 76 dBc, Non HD23 = 83 dBFS
AIN = -4 dBFS, 1x AVG, Dither = EN
图6-5. Single Tone FFT at FIN = 900 MHz
图6-6. Single Tone FFT at FIN = 900 MHz
1
Measured from 100 MHz to FS/2
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0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 63.8 dBFS, HD23 = 69 dBc, Non HD23 = 80 dBFS
AIN = -1 dBFS, 1x AVG, Dither = DIS
SNR = 64.1 dBFS1, HD23 = 71 dBc, Non HD23 = 86 dBFS
AIN = -4 dBFS, 1x AVG, Dither = EN
图6-7. Single Tone FFT at FIN = 1400 MHz
图6-8. Single Tone FFT at FIN = 1400 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 62.6 dBFS, HD23 = 60 dBc, Non HD23 = 79 dBFS
AIN = -1 dBFS, 1x AVG, Dither = DIS
SNR = 63.4 dBFS1, HD23 = 63 dBc, Non HD23 = 89 dBFS
AIN = -4 dBFS, 1x AVG, Dither = EN
图6-9. Single Tone FFT at FIN = 1900 MHz
图6-10. Single Tone FFT at FIN = 1900 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 66.8 dBFS, HD23 = 67 dBc, Non HD23 = 82 dBFS
AIN = -1 dBFS, 2x AVG, Dither = DIS
SNR = 67.0 dBFS1, HD23 = 72 dBc, Non HD23 = 89 dBFS
AIN = -4 dBFS, 2x AVG, Dither = EN
图6-11. Single Tone FFT at FIN = 900 MHz
图6-12. Single Tone FFT at FIN = 900 MHz
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0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 65.2 dBFS, HD23 = 64 dBc, Non HD23 = 88 dBFS
AIN = -20 dBFS, 1x AVG, Dither = DIS
SNR = 64.8 dBFS1, HD23 = 59 dBc, Non HD23 = 79 dBFS
AIN = -20 dBFS, 1x AVG, Dither = EN
图6-13. Single Tone FFT at FIN = 900 MHz
图6-14. Single Tone FFT at FIN = 900 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
SNR = 67.9 dBFS, HD23 = 64 dBc, Non HD23 = 86 dBFS
AIN = -20 dBFS, 2x AVG, Dither = DIS
SNR = 67.6 dBFS1, HD23 = 67 dBc, Non HD23 = 87 dBFS
AIN = -20 dBFS, 2x AVG, Dither = EN
图6-15. Single Tone FFT at FIN = 900 MHz
图6-16. Single Tone FFT at FIN = 900 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
IMD3 = 73 dBc
IMD3 = 75 dBc
AIN = -7 dBFS/tone, 1x AVG, Dither = DIS
AIN = -10 dBFS/tone, 1x AVG, Dither = EN
图6-17. Two Tone FFT at FIN = 900, 1000 MHz
图6-18. Two Tone FFT at FIN = 900, 1000 MHz
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0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-100
-120
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
IMD3 = 70 dBc
AIN = -20 dBFS/tone, 1x AVG, Dither = DIS
IMD3 = 72 dBc
AIN = -20 dBFS/tone, 1x AVG, Dither = EN
图6-19. Two Tone FFT at FIN = 900, 1000 MHz
图6-20. Two Tone FFT at FIN = 900, 1000 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
IMD3 = 72 dBc
IMD3 = 79 dBc
AIN = -7 dBFS/tone, 2x AVG, Dither = DIS
AIN = -10 dBFS/tone, 2x AVG, Dither = EN
图6-21. Two Tone FFT at FIN = 900, 1000 MHz
图6-22. Two Tone FFT at FIN = 900, 1000 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
IMD3 = 63 dBc
IMD3 = 77 dBc
AIN = -20 dBFS/tone, 2x AVG, Dither = DIS
AIN = -20 dBFS/tone, 2x AVG, Dither = EN
图6-23. Two Tone FFT at FIN = 900, 1000 MHz
图6-24. Two Tone FFT at FIN = 900, 1000 MHz
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69
68
67
66
65
64
63
62
100
95
90
85
80
75
70
65
60
72
71
70
69
68
67
66
65
64
63
110
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
105
100
95
90
85
80
75
70
61
0
65
200 400 600 800 1000 1200 1400 1600 1800 2000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Input Frequency (MHz)
Input Frequency (MHz)
AIN = -1 dBFS, Dither = DIS
AIN = -4 dBFS, Dither = EN
图6-25. AC Performance vs FIN
图6-26. AC Performance vs FIN
135
130
125
120
115
110
105
100
-152
-153
-154
-155
-156
-157
-158
Dither DIS (1x)
Dither DIS (2x)
Dither EN (1x)
Dither EN (2x)
95
-80
-70
-60
-50
-40
-30
-20
-10
0
0
200
400
600
800
1000 1200 1400 1600 1800 2000
Input Amplitude (dBFS)
Input Frequency (MHz)
FIN = 900 MHz
AIN = -20 dBFS
图6-27. Dither Spur vs AIN
图6-28. NSD Performance vs FIN
74
73
72
71
70
69
68
67
66
65
64
63
62
135
130
125
120
115
110
105
100
95
75
140
135
130
125
120
115
110
105
100
95
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
74
73
72
71
70
69
68
67
66
65
64
63
62
90
85
90
80
85
75
80
61
70
75
-80
-70
-60
-50
-40
-30
-20
-10
0
-80
-70
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
Dither = DIS
Dither = EN
图6-29. AC Performance vs AIN
图6-30. AC Performance vs AIN
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72
90
85
80
75
70
65
60
140
130
120
110
100
90
SNR (1x)
HD23 (1x)
Non HD23 (1x)
SNR (2x)
HD23 (2x)
Non HD23 (2x)
1x (FIN = 900/1000 MHz)
2x (FIN = 900/1000 MHz)
70
68
66
64
62
60
80
70
0.5
0.75
1
1.25
1.5
-80
-70
-60
-50
-40
-30
-20
-10
0
Sampling Rate (GSPS)
Input Amplitude/Tone (dBFS)
FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS
Dither = DIS
图6-31. AC Performance vs FS
图6-32. IMD3 Performance vs AIN
130
120
110
100
90
140
130
120
110
100
90
ChA to ChB
ChA to ChC
ChA to ChD
ChB to ChD
1x (FIN = 900/1000 MHz)
2x (FIN = 900/1000 MHz)
80
70
60
80
50
-80
-70
-60
-50
-40
-30
-20
-10
0
0
250
500
750
1000 1250 1500 1750 2000
Input Amplitude/Tone (dBFS)
Input Frequency (MHz)
Dither = EN
图6-34. Isolation vs Input Frequency
图6-33. IMD3 Performance vs AIN
68
67
66
65
64
90
85
80
75
70
68
67
66
65
64
63
62
90
85
80
75
70
65
60
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
SNR, 1x AVG
HD23, 1x AVG
Non HD23, 1x AVG
SNR, 2x AVG
HD23, 2x AVG
Non HD23, 2x AVG
40
45
50
Clock Duty Cycle (%)
55
60
1.75
1.8
AVDD18 (V)
1.85
FIN = 900 MHz, AIN = -1 dBFS, 1x AVG, Dither = DIS
FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS
图6-35. AC Performance vs Clock Duty Cycle
图6-36. AC Performance vs AVDD18
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69
90
85
80
75
70
65
69
68
67
66
65
64
63
62
61
60
110
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
105
100
95
68
67
66
65
90
85
80
75
70
65
64
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
1.15
1.2
AVDD12 (V)
1.25
Ambient Temperature (degC)
FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS
FIN = 900 MHz, AIN = -1 dBFS, Dither = DIS
图6-37. AC Performance vs AVDD12
图6-38. AC Performance vs Temperature
68
110
100
90
5
SNR (1x)
SNR (2x)
HD23 (1x)
HD23 (2x)
Non HD23 (1x)
Non HD23 (2x)
1x AVG
2x AVG
4
3
67
66
65
64
63
2
1
0
80
-1
-2
-3
-4
-5
70
60
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
0
1024
2048
Code
3072
4096
Ambient Temperature (degC)
FIN = 900 MHz, AIN = -1 dBFS, Dither = EN
FIN = 900 MHz, Dither = DIS
图6-39. AC Performance vs Temperature
图6-40. INL vs Code
1.5
30%
25%
20%
15%
10%
5%
1x AVG
2x AVG
1x AVG
2x AVG
1.25
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-1.25
-1.5
0
2054 2055 2056 2057 2058 2059 2060 2061 2062 2063
Output Code
0
1024
2048
Code
3072
4096
FIN = 900 MHz, Dither = DIS
Dither = DIS
图6-41. DNL vs Code
图6-42. DC Offset Histogram
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2
1.8
1.6
1.4
1.2
1
70
AVDD18 (1x)
AVDD12 (1x)
DVDD (1x)
AVDD18 (2x)
AVDD12 (2x)
DVDD (2x)
FIN = 900 MHz
FIN = 1800 MHz
60
50
40
30
20
10
CLKVDD (1x)
CLKVDD (2x)
0.8
0.6
0.4
0.2
0
0.1
1
10
100
500
0.5
0.7
0.9
1.1
1.3
1.5
Frequency (MHz)
Sampling Rate (GSPS)
AIN = -1 dBFS, 1x AVG, Dither = DIS
DDC Bypass
图6-43. CMRR
图6-44. Current vs Sampling Rate vs Averaging
1.25
1
1.5
/4 (8-4-2-2)
/8 (8-4-2-2)
/164 (8-4-2-2)
/4 (4-4-2-1)
/8 (4-4-2-1)
/16 (4-4-2-1)
/32 (4-4-2-1)
/4 (2-4-4-1)
/8 (2-4-4-1)
/16 (2-4-4-1)
/32 (2-4-4-1)
/64 (2-4-4-1)
/4 (1-4-8-1)
/8 (1-4-8-1)
/16 (1-4-8-1)
/32 (1-4-8-1)
/64 (1-4-8-1)
/128 (1-4-8-1)
1.25
1
0.75
0.5
0.75
0.5
0.25
0.25
0.5
0.75
1
1.25
1.5
0.5
0.75
1
1.25
1.5
Sampling Rate (GSPS)
Sampling Rate (GSPS)
AIN = -1 dBFS, 1x AVG
AIN = -1 dBFS, 1x AVG
图6-45. Current vs Sampling Rate vs Real
图6-46. Current vs Sampling Rate vs Real
Decimation
Decimation
1.75
1.5
/4 (2-8-8-1)
/8 (2-8-8-1)
/16 (2-8-8-1)
/32 (2-8-8-1)
/64 (2-8-8-1)
/128 (2-8-8-1)
/8 (1-8-16-1)
/16 (1-8-16-1)
/32 (1-8-16-1)
/64 (1-8-16-1)
/128 (1-8-16-1)
/4 (8-8-2-1)
/8 (8-8-2-1)
/16 (8-8-2-1)
/32 (8-8-2-1)
/4 (4-8-4-1)
/8 (4-8-4-1)
/16 (4-8-4-1)
/32 (4-8-4-1)
/64 (4-8-4-1)
1.5
1.25
1
1.25
1
0.75
0.5
0.75
0.5
0.5
0.75
1
1.25
1.5
0.5
0.75
1
1.25
1.5
Sampling Rate (GSPS)
Sampling Rate (GSPS)
AIN = -1 dBFS, 1x AVG
Single Band Decimation
AIN = -1 dBFS, 1x AVG
Single Band Decimation
图6-47. Current vs Sampling Rate vs Complex
图6-48. Current vs Sampling Rate vs Complex
Decimation
Decimation
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2.25
2
1.75
1.5
1.25
1
/4 (8-16-4-1)
/8 (8-16-4-1)
/16 (8-16-4-1)
/32 (8-16-4-1)
/64 (8-16-4-1)
/4 (4-16-8-1)
/8 (4-16-8-1)
/16 (4-16-8-1)
/32 (4-16-8-1)
/64 (4-16-8-1)
/128 (4-16-8-1)
/8 (2-16-16-1)
/16 (2-16-16-1)
/32 (2-16-16-1)
/64 (2-16-16-1)
/128 (2-16-16-1)
/16 (1-16-32-1)
/32 (1-16-32-1)
/64 (1-16-32-1)
/128 (1-16-32-1)
1.75
1.5
1.25
1
0.75
0.5
0.75
0.5
0.5
0.75
1
1.25
1.5
0.5
0.75
1
1.25
1.5
Sampling Rate (GSPS)
Sampling Rate (GSPS)
AIN = -1 dBFS, 1x AVG
Dual Band Decimation
AIN = -1 dBFS, 1x AVG
Dual Band Decimation
图6-49. Current vs Sampling Rate vs Complex
图6-50. Current vs Sampling Rate vs Complex
Decimation
Decimation
2.5
2.5
AVDD18 (1x)
AVDD18 (2x)
AVDD12 (1x)
AVDD12 (2x)
DVDD (1x)
DVDD (2x)
AVDD18 (1x)
AVDD18 (2x)
AVDD12 (1x)
AVDD12 (2x)
DVDD (1x)
DVDD (2x)
2
1.5
1
2
1.5
1
0.5
0
0.5
0
1.75
1.775
1.8
1.825
1.85
1.15
1.175
1.2
1.225
AVDD18 (V)
AVDD12 (V)
AIN = -1 dBFS, Dither DIS
AIN = -1 dBFS, Dither DIS
图6-51. Current vs AVDD18
图6-52. Current vs AVDD12
2.5
2
2.5
2.25
2
AVDD18 (1x)
AVDD18 (2x)
AVDD12 (1x)
AVDD12 (2x)
DVDD (1x)
DVDD (2x)
CLKVDD (1x)
CLKVDD (2x)
AVDD18 (1x)
AVDD18 (2x)
AVDD12 (1x)
AVDD12 (2x)
DVDD (1x)
DVDD (2x)
1.75
1.5
1.25
1
1.5
1
0.75
0.5
0.25
0
0.5
0
1.175
1.2
1.225
-40
-20
0
20
40
60
80
100
120
DVDD (V)
Ambient Temperature (degC)
AIN = -1 dBFS, Dither DIS
AIN = -1 dBFS, Dither DIS
图6-53. Current vs DVDD
图6-54. Current vs Temperature
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50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
60%
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
85C
-40C
85C
-40C
0
0
1.19 1.21 1.23 1.25 1.27 1.29 1.31 1.33 1.35
1.92
2.0
2.08
2.16
2.24
2.32
2.40
2.48
2.56
AVDD12 (A)
DVDD (A)
AIN = -1 dBFS
AIN = -1 dBFS
图6-55. AVDD12 Distribution
图6-56. DVDD Distribution
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7 Detailed Description
7.1 Overview
The ADC34RF52 is a single core (non-interleaved) 14-bit, 1.5 GSPS, quad channel analog to digital converter
(ADC).The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -153 dBFS/Hz.
Additional internal ADCs can be used for on-chip averaging to further improve the noise density to as low as
-156 dBFS/Hz.
The analog signal input is non-buffered to save power consumption with a nominal differential input impedance
of 100 Ω. The full power input bandwidth is 1.6 GHz (-3dB) and the device supports direct RF sampling with
input frequencies through the L-band. The device is designed for low residual phase noise to support high
performance radar applications. The sampling clock input has a dedicated power supply input which requires a
clean power supply.
Each ADC channel can be connected to a dual-band digital down-converter (DDC) using a 48-bit NCO which
supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency
hopping is achieved in less than 1 µs. The digital down converters support a wide range of instantaneous
bandwidth (IBW) coverage. A single wide band mode with 4x complex decimation up to two narrow bandwidth
channels with as high as 128x complex decimation.
The ADC34RF52 supports the JESD204B serial data interface with subclass 1 deterministic latency using data
rates up to 13.0 GBPS. The device is pin-pin compatible with the ADC34RF54 (2.6 GSPS) and ADC34RF55 (3
GSPS).
The power efficient ADC architecture consumes 0.73 W/ch at 1.5 GSPS at maximum sampling rate and provides
power scaling with lower sampling rates (0.55 W/ch at 0.6 GSPS).
7.2 Functional Block Diagram
DDC
NCO
DDC
100
100
N
DOUT0/1P/M
DOUT2/3P/M
ADC
INAP/M
DDC
DDC
NCO
N
ADC
INBP/M
CLKP/M
SYSREFP/M
INCP/M
DDC
DDC
NCO
100
100
DOUT4/5P/M
DOUT6/7P/M
N
ADC
DDC
DDC
NCO
N
ADC
INDP/M
RESETb
SEN
SPI Registers and
Device Control
SCLK
SDIO
GPIO2 SPISEL
GPIO1
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7.3 Feature Description
7.3.1 Analog Inputs
The ADC34RF52 provides up to two internal ADCs per channel for purpose of averaging to improve the noise
performance. Two ADCs are connected internally to the same differential input pins as shown in the equivalent
input schematic (see 图 7-1). The analog inputs have a differential 100 Ω split termination with internal biasing.
When only a single ADC is used, there is a minor parasitic capacitance remaining from the unused ADC.
Sampling Switch
7 ꢀ
11 ꢀ
AVDD12
ADCx
0.4 pF
1.4 pF
0.7 pF
0.6 nH
2 ꢀ
1 nH
xINP/
xINM
GND
GND
GND
7 ꢀ
11 ꢀ
50 ꢀ
0.2 pF
GND
ADCy
VCM
0.4 pF
1.4 pF
0.7 pF
GND
GND
GND
GND
图7-1. Equivalent input schematic
7.3.1.1 Input Bandwidth and Full-Scale
The input bandwidth (-3 dB) and input fullscale are dependent on what input termination and averaging mode
are chosen as shown in the summary in 表 7-1. With averaging enabled the -3 dB bandwidth reduces to ~ 1.5
GHz and 100 Ωdifferential termination; the bandwidth can be increased by changing the input termination to
50 Ωdifferential.
表7-1. Digital averaging vs full power input bandwidth (–3 dB)
Selected differential input
# of ADCs averaged
Input Bandwidth (-3 dB)
Reset Switch
Input Full-scale
termination
1 (Default)
1.6 GHz
1.5 GHz
1.5 GHz
0.8 GHz
1
1
0
0
+ 1 dBm
+ 1.8 dBm
+ 0.5 dBm
2
1
2
100 Ω
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There is an internal RESET switch which resets the sampling capacitor to VCM in between samples when
enabled. The full power input bandwidth plots with input RESET switch disabled (RSW0) and enabled (RSW1)
are shown in 图7-2.
2
0
-2
-4
-6
-8
-10
RSW1, 1x AVG
RSW1, 2x AVG
RSW0, 1x AVG
-12
RSW0, 2x AVG
-14
0.1
1
4
Input Frequency (MHz)
图7-2. Full power input bandwidth (100 Ω)
The RESET switch is enabled by default and can be disabled with the following register writes:
表7-2. Register Write Example for Configuring the RESET Switch
ADDR
0x05
DATA
0x40
0xC0
0x08
DESCRIPTION
Select ANALOG page
0x6D
0x6E
Disable RESET Switch (to enable: 0x00)
Disable RESET Switch (to enable: 0x00)
7.3.1.2 Input Imbalance
The AC performance is sensitive to amplitude and phase imbalance of the analog inputs, as shown in 图7-3 and
图7-4 for 1x and 2x internal averaging (FS = 1.5 GSPS, FIN = 0.9 GHz, AIN = -1 dBFS, dither = DIS).
67
66
65
64
63
62
61
60
59
58
57
56
55
100
95
90
85
80
75
70
65
60
55
50
45
40
67
66
65
64
63
62
61
60
59
58
57
56
55
100
95
90
85
80
75
70
65
60
55
50
45
40
SNR (1x)
SNR (2x)
HD2 (1x)
HD2 (2x)
Non HD23 (1x)
Non HD23 (2x)
SNR (1x)
SNR (2x)
HD2 (1x)
HD2 (2x)
Non HD23 (1x)
Non HD23 (2x)
-10
-5
0
5
10
-1
-0.5
0
0.5
1
Phase Imbalance (°)
Amplitude Imbalance (dB)
图7-3. Amplitude Imbalance vs SNR
图7-4. Phase Imbalance vs SNR
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7.3.1.3 Overrange Indication
The ADC provides two options (configured using SPI) to indicate if input fullscale overrange occurred:
• Fast Overrange on GPIO1/2 pins: indication is available after ~ 6 clock cycles and the overrange indication
flag stays high (sticky) until it is cleared via SPI register writes. Note: OVRA and OVRB are OR-ed together
and OVRC and OVRD are OR-ed together and given on GPIO1/2.
• Overrange embedded in JESD stream: in this configuration the overrange indicator replaces the LSB of the
output data of the corresponding channel. The indicator is output ahead of the data and is updated every
clock cycle.
表7-3. JESD OVR Latency
OVR Latency (incl JESD, in sampling
Decimation
# of Bands
clock cycles)
DDC Bypass
-
140-144
44
Single (real and complex)
8
16
32
64
128
Dual
33
Single (real and complex)
80
Dual
Single (real and complex)
Dual
58
152
108
296
208
584
408
Single (real and complex)
Dual
Single (real and complex)
Dual
The overrange output flag (GPIO or JESD) is the output of individual overrange flags of all ADCs per channel
being used. For example, in non-averaged mode the overrange indication per channel is for a single ADC while
in 2x average mode the overrange flag of all 2 ADCs are OR-ed together. 表 7-4 shows how to configure the
OVR using SPI registers.
表7-4. Programming example to configure the OVR to GPIO or JESD
ADDR
DATA
DESCRIPTION
ADDR
DATA
DESCRIPTION
OVR on GPIO1 and GPIO2, OVR sticky
OVR on JESD
0x05
0x238
0x383
0x02
0xF0
0x02
Select DIGITAL page
0x05
0x2E
0x05
0x02
D0
Select DIGITAL page
Set D0 = 1 to enable OVR on JESD
0x00
Clear OVR
These extra writes are only needed using decimation
0x05
0x74
0x74
0x84
0x84
0x40
0x04
0x00
0x04
0x00
Select ANALOG page
0x05
0x20
0x18
0x06
Select DDCAB/ DDCCD page
Enable OVR on JESD
Clear OVR flag chA
Clear OVR flag chB
Change OVR from sticky to non sticky (self clear)
0x05
0x31
0x40
0x06
Select ANALOG page
Set OVR to non-sticky
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7.3.1.4 Analog out-of-band dither
The ADC34RF52 provides optional (enabled via SPI writes) analog out-of-band, large amplitude dither. It has a
bandwidth of ~ 20 MHz located at DC and an adjustable amplitude with a maximum dither power of
approximately ~ -20 dBFS (PAR ~ 9 dB). The dither is completely rolled-off into the noise floor within ~ 100 MHz
as illustrated in 图7-5. Since the dither is large, the amplitude is recommended for the signal input not to exceed
-2.5 dBFS to avoid input saturation. The dither signal also couples to the input signal and, depending on input
frequency, can degrade the close in phase noise for offsets > 1 MHz.
~ 20 MHz
ADC Noise
Floor
~ 100 MHz
FS/2
图7-5. Analog out-of-band dither
In the frequency domain, the dither signal shows up in individual tones as shown in 图 7-6. The dither update
frequency can be adjusted with the dither divider setting. The dither update frequency is: FS / 4 / 2047 / 'Dither
Divider'. In the frequency spectrum, there is a 2 larger dither spurs at FIN +/- FS / 4 / 'Dither Divider'.
By default, the divider is set to 50, which translates to a dither spur spacing of ~ 7 kHz. A divider setting of 32
translates to a dither spacing of ~ 11 kHz as shown in 图 7-7. The lower the divider setting, the higher the dither
tone frequency. 图 7-7 also shows that the dither energy reduces as the offset frequency increases. Less dither
energy reduces the higher harmonic spur improvement.
-80
-90
-100
-110
-120
-130
-140
-150
-160
Dither by 32
Dither by 16
Dither by 8
-100
-110
-120
-130
-140
-150
-160
-170
-180
0.001
0.01
0.1
1
0.001
0.01
0.1
1
Frequency Offset (MHz)
Frequency Offset (MHz)
图7-6. Dither Close-Up
图7-7. Dither vs Dither Divider Setting
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The analog dither must be enabled in multiple locations. The different dither amplitudes must be used based on
the internal averaging as shown in 表7-5.
表7-5. Recommended dither amplitude settings
Mode
Amplitude
±1024 codes
±768 codes
±1024 codes
±768 codes
Dither Amp1
Dither Amp2
1x AVG
1x AVG
2x AVG
2x AVG
0
0
3
0
0
-4
0
0
The internal analog dither can be enabled via the following register writes. After enabling the dither (or changing
the dither amplitude) another calibration needs to be performed. See 表7-6.
表7-6. Register write example for configuring the internal dither
ADDR
0x05
DATA
0x40
0x00
0x00
0x01
DESCRIPTION
ADDR
0xB1
0xB2
0xAF
0xAF
DATA
0x00
0x00
0x18
0x10
DESCRIPTION
Select ANALOG page
Sets dither divider. 0x00 = /50
0xA8
0xCD
0x04
DITHER AMP1: 3 = 0x80, 0 = 0x00
DITHER AMP2: -4 = 0x40, 0 = 0x00
0x10 = dither ENABLED, 0x90 = dither
DISABLED
0x20
0x91
0xAF
0x04
0x40
0x10
0x04
0x20
0x04
0x01
0x00
0x00
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7.3.2 Sampling Clock Input
The internal sampling clock path was designed for lowest residual phase noise contribution. The sampling clock
circuitry requires a dedicated low noise power supply for best performance. The internal residual clock phase
noise is also sensitive to clock amplitude and for best performance the clock amplitude should be larger than
1 VPP
.
表7-7. Internal Aperture Clock Phase Noise
(FS = 1.5 Gsps, VIN = 1 VPP
)
Frequency Offset (MHz)
Amplitude (dBc/Hz)
0.001
0.01
0.1
1
-123
-133
-143
-152
-157
-160
10
250
The clock input and ADC sampling circuitry also have an amplitude noise component which modulates on to the
sampled input signal. Unlike phase noise, the amplitude noise does not scale with input frequency as shown in
图7-8. This noise component can dominate the close in noise performance at lower input frequencies.
-110
FIN = 300 MHz
FIN = 1000 MHz
-115
-120
-125
-130
-135
-140
-145
-150
-155
-160
0.001
0.01
0.1
1
10
Offset Frequency (MHz)
图7-8. Amplitude Noise
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The internal aperture jitter is also dependent on the amplitude of the external clock input signal. 图 7-9and 图
7-10 show the expected SNR performance with dither on/off across clock amplitude.
66
65
64
63
62
61
60
59
66
65
64
63
62
61
60
59
1x AVG, Dither OFF
1x AVG, Dither ON
2x AVG, Dither OFF
2x AVG, Dither ON
1x AVG, Dither OFF
1x AVG, Dither ON
2x AVG, Dither OFF
2x AVG, Dither ON
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Clock Amplitude (Vpp)
Clock Amplitude (Vpp)
图7-9. SNR vs Clock Amplitude (FIN = 900 MHz)
图7-10. SNR vs Clock Amplitude (FIN = 1800 MHz)
The sampling clock input is internally terminated to 100 Ωdifferentially and provides a return loss better than 10
dB (see 图 7-11). The clock input consists of a single clock input buffer followed by a dedicated clock buffer for
ADCA/B as well as ADCC/D. When averaging two ADCs internally, there is some decrease in clock buffer noise
which is correlated and does not improve with averaging.
VCM
To ADCA/B
5 k
CLKP
Buffer
100
5 k
CLKM
To ADCC/D
VCM
图7-11. Clock Input Internal Circuitry
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7.3.3 SYSREF
The SYSREF input signal is used to reset internal digital blocks and align them to the internal multi-frame clock
to achieve deterministic latency subclass 1. The SYSREF input signal can be AC or DC coupled (selected via
SPI register option) as shown in 图 7-12. The ADC34RF52 has internal 100-Ω termination for DC coupling and
internal biasing when using AC coupling.
A register mask can be used to only give SYSREF to the NCO (see NCO section) in the decimation filter block.
Leave all other blocks such as JESD interface unaffected.
When giving a periodic SYSREF signal, the frequency must be a sub-harmonic of the internal local multi-frame
clock (LMFC). The LMFC frequency is determined by the selected decimation: frames per multi-frame setting
(K), samples per frame (S), and the device sampling frequency (FS).
表7-8. LMFC and SYSREF settings for different operating modes
Operating Mode
LMFS Mode
LMFC Clock Frequency
SYSREF Frequency
FS / (N x 20 x K)
FS / (N x 4 x K)
DDC Bypass Mode
84810
FS / (20 x K)
8422
FS / (4 x K)
Decimation
Various
FS / (D x S x K)
FS / (N x D x S x K)
Where N is an integer value (1, 2, 3...).
After enabling SYSREF input, the internal SYSREF input ignores any incoming SYSREF pulse after the first 16
pulses.
0.7V
5 kꢀ
SYSREFP
SYSREFM
SYSREFP
SYSREFM
Buffer
Buffer
100 ꢀ
5 kꢀ
0.7V
图7-12. SYSREF Input Circuitry and Edge Alignment
The internal synchronization using the external SYSREF signal can be enabled with the following register writes.
表7-9. Register Write Example for Enabling SYSREF Synchronization
ADDR
0x05
DATA
0x02
0x02
0x03
DESCRIPTION
Select DIGITAL page
0x236
0x236
Enable internal SYSREF input and clear SYSREF pulse counter
Starts internal SYSREF counter
AC coupling with internal biasing of the SYSREF input can be enabled with the following SPI register writes.
表7-10. Register Write Example for Enabling SYSREF AC Coupling
ADDR
0x05
DATA
0x40
0x01
DESCRIPTION
Select ANALOG page
Enable external AC coupling with internal biasing on SYSREF
0xB4
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7.3.3.1 SYSREF Capture Detection
The SYSREF input signal rising edge should be edge aligned with the rising edge of the sampling clock to
maximize the setup and hold times. The ADC34RF52 includes an internal SYSREF monitoring circuitry to detect
possible metastability resulting in a clock cycle slip, and thus, misalignment across devices.
The sampling clock gets delayed by ~ 160 ps and then captures the SYSREF signal. The SYSREF monitoring
circuitry captures the SYSREF signal ±50 ps (-50, -25, +16, +32, +48 ps) around the main SYSREF capture.
Ideally no SYSREF transition happens within the 100 ps SYSREF capture window and all XOR flags show "0". If
a SYSREF/clock misalignment happens and the SYSREF transition falls within the SYSREF monitoring window,
then one of the XOR flags (which monitor adjacent SYSREF captures within the window) will show a "1" and the
SYSREF can be adjusted externally.
The SYSREF monitor registers are not 'sticky' registers and they are updated at every rising edge of SYSREF.
110 ps
delay
25 ps
delay
25 ps
delay
16 ps
delay
16 ps
delay
16 ps
delay
CLK
SYSREF
A
B
C
D
E
F
XOR
5
XOR
1
XOR
3
XOR
4
XOR
2
SYSREF captured to ADC
图7-13. SYSREF Detection Circuitry
The example in 图 7-14 shows a misaligned SYSREF signal where the SYSREF signal arrives much later than
the sampling clock rising edge. The SYSREF window feature checks if the SYSREF transition is within ±50 ps of
the instant when the SYSREF signal gets captured by the sampling clock.
In this example, the delayed SYSREF signal transitions between the "B" and "C" flip flop which raises the XOR2
flag. The XOR flags is reported in register 0x22F in the digital page. Register 0x22F in this example would read
back 0x8B, as shown in 表7-11.
+/- 50ps
SYSREF and
sampling clock are
edge aligned
XOR XOR XOR XORXOR
4
1
2
3
5
SYSREF
CLK
CLK + 160ps
图7-14. Detection of SYSREF Transition within Capture Window
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表7-11. SYSREF Window Register Example (0x22F)
ADDR
D7
1
D6
D5
D4
D3
D2
D1
D0
1
SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1 SYSREF OR
0x22F
1
0
0
0
1
0
1
1
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7.3.4 ADC Foreground Calibration
The internal ADC architecture is sensitive to temperature changes. The ADC34RF52 contains two additional
internal ADC cores (one for channel A/B and one for channel C/D) which are used whenever one of the ADCs is
in calibration. ADCs are calibrated as pairs where one ADC at a time is connected to the internal calibration
DAC. The calibration is configured via SPI register writes and can be executed using SPI register writes or using
the GPIO1 pin. When executed the calibration takes ~ 27 ms/ADC pair (~13.5 ms/ADC). The example in 图
7-15shows 2x internal averaging where 4 ADC cores (#1,2,3,4 for chA/B and #6,7,8,9 for chC/D) are used in
operation and ADCs #5 and #10 for calibration.
#1
ChA
#2
#3
ChB
#4
#5
CAL
DAC
#10
#9
ChD
#8
#7
ChC
#6
图7-15. Internal ADC setup for 2x averaging mode
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7.3.4.1 Calibration Control
图7-16 shows a timing diagram of the calibration control using GPIO1 pin.
When GPIO1 transitions to LOW logic state:
• an ADC pair gets swapped out within approximately 120 ns
• a new calibration gets triggered immediately
If GPIO1 is being held low when the calibration of an ADC pair is completed, the next ADC pair is switched and a
new calibration is triggered. The order in which ADC pair gets calibrated can be configured via SPI to serial or
random.
When using 2x averaging for example, the calibration must be executed for 5 ADC pairs to make sure all ADCs
in use have been calibrated recently.
1
2
3
4
6
7
8
9
5
2
3
4
10
7
5
2
3
4
10
7
1
5
3
4
6
10
8
1
5
3
4
6
10
8
1
2
5
4
6
7
1
2
3
5
6
7
1
2
3
5
6
7
ADCs
In use
8
8
10
9
8
8
9
9
9
9
10
10
ADCs
O -line
5
10
1
6
2
7
4
9
ADCs
in cal
1
6
2
7
3
8
4
9
GPIO1
Time
27ms
27ms
27ms
27ms
图7-16. Timing diagram - calibration (2x AVG example)
图7-17 shows the ADC switch happens approximately 120 ns after the logic level change on GPIO1 is detected.
Input
GPIO
120ns
图7-17. Timing diagram shows the ADC switch
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7.3.4.2 ADC Switch
During the ADC transition, the amplitude may drop less 1% for 1-2 samples as shown in 图 7-18. The gain
variation from one ADC to the next is ~ < 0.05 dB while the phase change is less 0.01 deg as shown in 图7-19.
-2.94
-2.95
-2.96
-2.97
-2.98
-2.99
-3
39.52
39.5
Amplitude
Phase
39.48
39.46
39.44
39.42
39.4
-3.01
-3.02
-3.03
-3.04
-3.05
-3.06
39.38
39.36
39.34
39.32
39.3
39.28
-100
-50
0
50
100
Time (us)
图7-19. Amplitude and Phase vs Time
图7-18. Output Code vs ADC Sample
7.3.4.3 Calibration Configuration
The ADC34RF52 provides 3 different options to configure the internal foreground calibration:
• Continous calibration - see 表7-12
• Calibrate all ADCs one time using SPI trigger - see 表7-13
• Calibrate 2 ADC pairs at a time using GPIO trigger - see 表7-14
The status of the calibration can be read back from register 0x298 (CALIBRATION page). Successful calibration
reads back 0x0E.
表7-12. Register writes to trigger CONTINOUS calibration of all ADCs using SPI
ADDR
0x05
DATA
0x20
0x03
DESCRIPTION
Select CALIBRATION page
0x46
表7-13. Register writes to trigger SINGLE calibration of all ADCs using SPI
ADDR
0x05
0x48
0x45
0x45
DATA
0x20
0x15
0x8A
0x0A
DESCRIPTION
Select CALIBRATION page
Toggle calibration start
wait 2 s
表7-14. Register writes to trigger ADC pair calibration using the GPIO pin
ADDR
0x05
0x46
0x45
0x05
0x234
DATA
0x20
0x02
0x4A
0x02
0x04
DESCRIPTION
Select CALIBRATION page
Select DIGITAL page
Use GPIO1 pin to freeze calibration switch
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7.3.5 Decimation Filter
The ADC34RF52 provides up to two digital down converters per ADC channel (see 图 7-20). The decimation
filters provide a flexible option to cover a wide range of instantaneous bandwidths (IBW) as shown in 表 7-15.
Single band decimation supports a wide bandwidth up to complex decimation by 4x. In dual band decimation
mode the widest bandwidth supported is complex decimation by 8.
DDC
DDC
NCO
2x
Averaging
ADC
N
JESD204B
图7-20. Digital Decimation Filter Options
表7-15. Summary of Different Decimation Filter Band Options
# of DDCs
Minimum Complex Decimation
Maximum Complex Decimation
1
2
4
8
128
128
The decimation filter can be configured to two different operating modes:
• Complex Decimation: This mode provides complex output with ~ 80% passband bandwidth using a 48-bit
phase coherent NCO.
During the complex mixing operation the digital output is reduced by 6-dB. This reduces the fullscale from 0-
dBFS to -6-dBFS. This 6-dB change applies to signals and noise and thus no dynamic range is lost.
• Real Decimation: In real decimation mode the complex mixer is bypassed (NCO should be set to 0 for lowest
power consumption) and the digital filter acts as a low pass filter. There is no frequency shifting and the
output passband bandwidth is ~ 40%.
Since the JESD204B interface is common across all ADC channels, the decimation ratio as well as the # of
DDCs/ADC has to be the same across all ADC channels.
By default, the output of values of the decimation filter are rounded to 16-bit resolution. To avoid quantization
noise limitation when using high order of decimation (that is, /64 or /128), a special 32-bit output mode can be
enabled (see 32-bit mode).
表7-16 provides an overview of the available complex decimation settings and resulting complex and real output
bandwidths.
表7-16. Decimation Setting vs Output Bandwidth
FS = 1.5 Gsps
FS = 1.5 Gsps
Decimation Complex Output
Real Output
Bandwidth per
DDC
Complex Output
Real Output
Factor N
Bandwidth per
DDC
Complex Output
Rate per DDC
Real Output Rate
per DDC
Bandwidth per
DDC
Bandwidth per
DDC
(complex)
4
8
0.8 x FS / 4
0.8 x FS / 8
375 Msps
187.5 Msps
300 MHz
150 MHz
75 MHz
0.4 x FS / 4
0.4 x FS / 8
375 Msps
187.5 Msps
150 MHz
75 MHz
16
32
64
128
0.8 x FS / 16
0.8 x FS / 32
0.8 x FS / 64
0.8 x FS / 128
93.75 Msps
0.4 x FS / 16
0.4 x FS / 32
0.4 x FS / 64
0.4 x FS / 128
93.75 Msps
37.5 MHz
18.75 MHz
9.375 MHz
4.6875 MHz
46.875 Msps
23.4375 Msps
11.71875 Msps
37.5 MHz
18.75 MHz
9.375 MHz
46.875 Msps
23.4375 Msps
11.71875 Msps
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7.3.5.1 Decimation Filter Response
This section provides the different decimation filter responses with a normalized ADC sampling rate. The
complex filter pass band is ~ 80% (-1 dB) with a minimum of 85 dB stop band rejection.
图7-21. Complex Decimation by 4 Filter Response
图7-22. Decimation by 4 Passband Ripple
Response
0
0
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
Attn Spec
-0.1
-0.2
-20
-40
Attn Spec
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-23. Complex Decimation by 8 Filter Response
图7-24. Decimation by 8 Passband Ripple
Response
0
0
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
Attn Spec
-0.1
-0.2
-20
-40
Attn Spec
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-25. Complex Decimation by 16 Filter
图7-26. Decimation by 16 Passband Ripple
Response
Response
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0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-20
-40
-60
-80
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.0025 0.005 0.0075 0.01 0.0125 0.015 0.0175 0.02 0.0225 0.025
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-27. Complex Decimation by 32 Filter
图7-28. Decimation by 32 Passband Ripple
Response
Response
0
0
Passband
Transition Band
Alias Band
Passband
Transition Band
Alias Band
-20
-40
-20
-40
Attn Spec
Attn Spec
-60
-60
-80
-80
-100
-120
-100
-120
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.025
0.05
0.075
0.1
0.125
0.15
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-29. Complex Decimation by 64 Filter
图7-30. Complex Decimation by 64 Filter
Response
Response
0
0
Passband
Transition Band
Alias Band
Attn Spec
Passband
Transition Band
Alias Band
-0.1
-0.2
-20
-40
Attn Spec
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
-60
-80
-100
-120
0
0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-31. Decimation by 64 Passband Ripple
图7-32. Complex Decimation by 128 Filter
Response
Response
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0
-10
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Passband
Passband
Transition Band
Alias Band
Attn Spec
Transition Band
Alias Band
Attn Spec
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
0.008 0.016 0.024 0.032
0.04
0.048 0.056 0.064 0.072
0
0.00075
0.0015
0.00225
0.003
0.00375
0.0045
Normalized Frequency (Fs)
Normalized Frequency (Fs)
adc3
adc3
图7-33. Complex Decimation by 128 Filter
图7-34. Decimation by 128 Passband Ripple
Response
Response
7.3.5.2 Decimation Filter Configuration
The decimation filter is configured with these register writes.
表7-17. Register writes to enable the internal decimation filter
ADDR
0x05
0x2C
0x2D
0x05
0x22
0x24
0x25
0x9F
0xA0
0xA1
DATA
DESCRIPTION
0x02
Select DIGITAL page
Select single/dual band
Select decimation
0x04
Select JESD page
Select LMFS mode
Select DDC CLK setting
Select JESD TX CLK DIV setting
Select JESD PLL1/2 settings
Select JESD PLL INPUT1 setting
Select JESD PLL INPUT2 settings
7.3.5.3 20-bit Output Mode
The device includes a 20-bit output resolution mode which can be used for high order decimation (such as: 64x,
128x) to avoid SNR degradation due to quantization noise limitation. In this mode, no additional JESD204B
output lanes are added but the output data is transmitted at 2x the output rate and two consecutive 16-bit
samples are filled with one 20-bit sample. So for example, a single band complex decimation would go from
LMFS = 4841 (16-bit output mode) to LMFS = 4881 (20-bit output mode) as illustrated in 表7-18.
表7-18. JESD Frame Assembly Comparison between 16-bit and 20-bit Output Mode
LMFS = 4841
LMFS = 4881
xI0[7:0] xQ0[31:24] xQ0[23:16] xQ0[15:8]
0000 00000000 20-bit sample Q 0000 00000000
xI0[15:8]
xI0[7:0] xQ0[15:8]
xQ0[7:0]
xI0[31:24]
xI0[23:16]
xI0[15:8]
xQ0[7:0]
20-bit sample I
The 20-bit output mode is enabled by setting D7 in 0x2C (DIGITAL page) and selecting viable decimation and
LMFS mode.
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7.3.5.4 Numerically Controlled Oscillator (NCO)
Each digital down-converter (DDC) uses a 48-bit numerically controlled oscillator (NCO) to fine tune the
frequency placement prior to the digital filtering. Different NCO frequencies for each DDC are programmed using
SPI register writes and the desired NCO frequency can be selected using SPI or the GPIO pins. When using the
GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The digital NCO is
designed to have a SFDR of at least 100 dB. The number of available, programmable NCO frequencies
depends on # of DDC bands used as illustrated in 表7-19.
GPIO
or SPI
DDC
Freq f1
NCO
Freq fX
I
ADC
N
Q
图7-35. NCO Block Diagram
表7-19. Available # of Frequencies per NCO
depending on # of DDCs used
# of DDCs used
# of Frequencies per NCO
1
2
4
4
There are two different NCO operating modes available - phase continuous and infinite phase coherent.
Phase Continuous NCO: During a NCO frequency change, the NCO phase gradually adjusts to the new
frequency as shown in 图7-36. The 'dashed' line shows the phase of original f1 frequency.
Infinite Phase Coherent NCO: With a phase coherent NCO, all frequencies are synchronized to a single event
using SYSREF. This enables an infinite amount of frequency hops without the need to reset the NCO as phase
coherency is maintained between frequency hops. This is illustrated in 图 7-36 (right). When returning to the
original frequency f1, the NCO phase appears as if the NCO have never changed frequencies.
f1
f2
f1
f1
f2
f1
图7-36. Phase Continuous (left) and Infinite Phase Coherent (right) NCO Frequency Switching
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The oscillator generates a complex exponential sequence of:
ejωn (default) or e–jωn
(1)
where: frequency (ω) is specified as a signed number by the 48-bit register setting
The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a
frequency equal to fIN + fNCO. The NCO frequency can be tuned from –FS/2 to +FS/2 and is processed as a
signed, 2s complement number.
The NCO frequency setting is set by the 48-bit register value given and calculated as:
NCO frequency (0 to + FS/2): NCO = fNCO × 248 / FS
(2)
(3)
NCO frequency (-FS/2 to 0): NCO = (fNCO + FS) × 248 / FS
where:
• NCO = NCO register setting (decimal value)
• fNCO = Desired NCO frequency (MHz)
• FS = ADC sampling rate (MSPS)
The NCO programming is illustrated with this example:
• ADC sampling rate FS = 1300 MSPS
• Desired NCO frequency = 460 MHz
NCO frequency setting = fNCO × 248 / FS = 460 MHz x 248 / 1300 MSPS = 99,598,837,913,001
(4)
表7-20 shows the register writes to set frequency 1 of NCO1 of DDCA to that frequency:
表7-20. Example register writes to change NCO frequency
ADDR
DATA
0x08
0x5A
0x95
0xA9
0x5A
0x95
0xA9
0x00
0x30
DESCRIPTION
0x05
Select DDCA page
0x105
0x104
0x103
0x102
0x101
0x100
0x181
0x181
Frequency = 460 MHz with FS = 1.3 GSPS
99,598,837,913,001 = 0x5A95A95A95A9 where the MSB goes to address 0x105 and the
LSB to 0x100.
Load and update NCO1 with the new frequency.
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7.3.5.5 NCO Frequency programming using the SPI interface
There are 2 separate NCOs per channel - one for each band (that is, NCO1 = band 1) and 4 different
frequencies can be programmed per NCO as shown in 图 7-37. The NCO frequencies are located in the
DDCAB/CD pages (0x05 0x08 for channel A/B and 0x05 0x10 for channel C/D) in registers 0x100 to 0x17D.
Depending on # of bands used, the frequencies for each NCO are selected in registers 0x3B and 0x41 (DIGITAL
page) as shown in 表 7-21. If the NCO frequencies are the same for channel A/B and channel C/D, the
frequencies can be written to both DDCAB and DDCCD pages simultaneously by selecting both pages (0x05
0x18).
Channel A
Channel B
Channel C
Channel D
NCO1
NCO1
NCO1
NCO1
1: 0x100..0x105
1: 0x140..0x145
1: 0x100..0x105
1: 0x140..0x145
2: 0x108..0x10D 2: 0x148..0x14D 2: 0x108..0x10D 2: 0x148..0x14D
3: 0x110..0x115 3: 0x150..0x155 3: 0x110..0x115 3: 0x150..0x155
4: 0x118..0x11D 4: 0x158..0x15D 4: 0x118..0x11D 4: 0x158..0x15D
NCO2
NCO2
NCO2
NCO2
1: 0x120..0x125
1: 0x160..0x165
1: 0x120..0x125
1: 0x160..0x165
2: 0x128..0x12D 2: 0x168..0x16D 2: 0x128..0x12D 2: 0x168..0x16D
3: 0x130..0x135 3: 0x170..0x175 3: 0x130..0x135 3: 0x170..0x175
4: 0x138..0x13D 4: 0x178..0x17D 4: 0x138..0x13D 4: 0x178..0x17D
图7-37. Multi-Band NCO
Single band DDC uses the frequencies of both NCO1 and NCO2 for a combined 8 different frequencies for
NCO1 using 3 bit control (NCO2 CHx [1] and NCO1 CHx [1:0]). The NCO2 selection bit (D3) decides if
frequencies from NCO1 or NCO2 are being used. In dual and quad band DDC operating mode, there are 4
frequencies per NCO available and selected using 2 register bits (NCOx CHx [1:0]).
.
表7-21. NCO Frequency Selection SPI Interface Registers
# OF BANDS
ADDR
0x3B
0x41
0x3B
0x41
D7
D6
D5
D4
D3
D2
D1
D0
NCO2 CHB [1]
NCO2 CHD [1]
0
NCO1 CHB [1:0]
NCO1 CHD [1:0]
NCO1 CHB [1:0]
NCO1 CHD [1:0]
NCO2 CHA [1]
NCO2 CHC [1]
0
NCO1 CHA [1:0]
NCO1 CHC [1:0]
NCO1 CHA [1:0]
NCO1 CHC [1:0]
SINGLE
0
0
NCO2 CHB [1:0]
NCO2 CHD [1:0]
NCO2 CHA [1:0]
NCO2 CHC [1:0]
DUAL
To select a different frequency for the NCO, two registers (0x3B and 0x41) in the DIGITAL page must be
updated. Assuming a SPI clock frequency of 10 MHz (100 ns period), programming two registers (2x (16 bit
address and 8 bit data) = 48 bit) means that the NCO frequency would be updated in ~ 5 us.
When updating the currently being used NCO frequency to a new frequency, the following command has to be
written to load the new frequency into the NCO - 0x181 0x00/0x30 in each of the DDCAB/CD pages.
表7-22. Example Register Writes
ADDR
0x05
DATA
0x02
0x01
0xFF
0x08
0x..
DESCRIPTION
Select DIGITAL page
0x3B
Select frequency 2 for NCO1 of channel A.
Select NCO using SPI
0x235
0x05
Select DDCAB page
0x10D...0x108
0x181
Write new frequency in frequency 2 of NCO1 of channel A
0x00
0x30
Update NCO with current frequencies from the register map.
0x181
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The NCO phase accumulators can be reset using the external SYSREF signal. A SYSREF mask can be setup
such the SYSREF signal only goes to the NCO and the remaining device remains unaffected. The following
register writes configure the SYSREF mask to only affect the NCO. After completion, the SYSREF mask should
be set back to default.
表7-23. Example Register Writes to configure the SYSREF MASK
ADDR
0x05
DATA
0x18
0x40
0x02
0xA2
0x02
DESCRIPTION
Select DDCAB/CD page
0x181
0x05
Reset NCO phases with SYSREF toggle
Select DIGITAL page
0x357
0x358
SYSREF mask settings (0x00 is mask default)
SYSREF mask settings (0x00 is mask default)
7.3.5.6 Fast Frequency Hopping
The ADC34RF52 supports several different options to update the NCO frequencies. Fast frequency hopping can
be achieved in one of the following ways:
• Using the GPIO1/2 pins to select the NCO frequency
• Using the GPIO1/2, SPISEL and SCLK/SDIO pins to select the NCO frequency
• Using the GPIO1/2 pins to program the NCO frequency selection (Fast SPI)
NCO SEL
MODE
NCO CONTROL
SCLK
SDATA
SPISEL
GPIO1
GPIO2
Regular SPI (default)
GPIO1/2
SPI Interface
0
0
1
1
used for other purpose
used for NCO control
used for NCO control
00
SPI Interface
NCO CONTROL
SPI Interface
00
GPIO1/2, SPISEL, SCLK/SDATA
FAST SPI
00
SDATA
SCLK
10
The internal NCO is switched quickly; however, the switching time depends primarily on the time it takes to flush
out the decimation filter as shown in 表7-24.
表7-24. NCO Switching Time (FS = 1.5 GSPS) vs Decimation Setting
Decimation Setting
NCO Switching Time
~ 500 ns
~ 700 ns
~ 1.2 us
/4
/8
/16
/32
/64
/128
~ 2 us
~ 4 us
~ 8 us
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7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
The NCO frequency is selected as shown in 表7-25. This mode is enabled with the following register writes:
1. Set 0x234 to 0x03 (NCO SEL MODE = 0, GPIO MODE = 3)
*** selection common to all NCOs. there is option to only update single nco??
表7-25. NCO Frequency Selection using GPIO1/2 Pins
# OF BANDS
GPIO2
GPIO1
GPIO2
GPIO1
GPIO2
GPIO1
GPIO2
GPIO1
0
0
0
0
NCO1 CHB [1:0]
0
0
0
0
NCO1 CHA [1:0]
SINGLE
NCO1 CHD [1:0]
NCO1 CHB [1:0]
NCO1 CHD [1:0]
NCO1 CHC [1:0]
NCO1 CHA [1:0]
NCO1 CHC [1:0]
NCO2 CHB [1:0]
NCO2 CHD [1:0]
NCO2 CHA [1:0]
NCO2 CHC [1:0]
DUAL
7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
This mode is enabled by setting the SPISEL to logic high and using the following register writes:
1. NCO SEL MODE in address 0x234 needs to be set to 3
表7-26. NCO Frequency Selection SPI Interface Registers
# OF BANDS
SDATA
SEN
GPIO2
GPIO1
SDATA
SEN
GPIO2
GPIO1
NCO1 CHB [2]
NCO1 CHD [2]
0
0
NCO1 CHB [1:0]
NCO1 CHA [2]
NCO1 CHC [2]
0
0
NCO1 CHA [1:0]
SINGLE
NCO1 CHD [1:0]
NCO1 CHB [1:0]
NCO1 CHD [1:0]
NCO1 CHC [1:0]
NCO1 CHA [1:0]
NCO1 CHC [1:0]
NCO2 CHB [1:0]
NCO2 CHD [1:0]
NCO2 CHA [1:0]
NCO2 CHC [1:0]
DUAL
7.3.5.6.3 Fast frequency hopping using the fast SPI
In this mode the GPIO1/2 pins are used as a "fast SPI" input which only updates the NCO selection registers. No
register address information needs to be sent. GPIO1 pin is SDATA and GPIO2 pin is SCLK.
This mode is enabled by setting the SPISEL to logic high and using the following register writes:
1. Set 0x234 to 0x43 (NCO SEL MODE = 2, GPIO MODE = 3)
The NCO frequencies are selected as shown in 表7-27.
表7-27. NCO Frequency Programming using FAST SPI
# OF
BANDS
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NCO1
CHD
[2]
NCO1
CHC
[2]
NCO1
CHB
[2]
NCO1
CHA
[2]
NCO1 CHD
[1:0]
NCO1 CHC
[1:0]
NCO1 CHB
[1:0]
NCO1 CHA
[1:0]
SINGLE
0
0
0
0
NCO2 CHD
[1:0]
NCO1 CHD
[1:0]
NCO2 CHC
[1:0]
NCO1 CHC
[1:0]
NCO2 CHB
[1:0]
NCO1 CHB
[1:0]
NCO2 CHA
[1:0]
NCO1 CHA
[1:0]
DUAL
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7.3.6 JESD204B Interface
The ADC34RF52 uses the JESD204B high-speed serial interface to transfer data from the ADC to the receiving
logic device. ADC34RF52 serialized lanes are capable of operating up to 13 Gbps, slightly above the JESD204B
max lane rate. A maximum of 8 lanes can be used to allow lower lane rates for interfacing with speed limited
logic devices. 图7-38 shows a simplified block diagram of the JESD204B interface.
ADC
JESD204B BLOCK
JESD204B
TRANSPORT
LAYER
SCRAMBLER
(Optional)
JESD204B
LINK LAYER
8B/10B
ENCODER
JESD204B
TX
ADC
图7-38. JESD204B Block Diagram
7.3.6.1 JESD204B Initial Lane Alignment (ILA)
The receiving device starts the initial lane alignment process by deasserting the SYNC signal. When a logic low
state is detected on the SYNC input, the ADC starts transmitting comma characters (K28.5) to establish the code
group synchronization, as shown in 图 7-39. When synchronization is completed, the receiving device reasserts
the SYNC signal and the ADC starts the initial lane alignment sequence with the next local multi-frame clock
(LMFC) boundary. The ADC transmits four multi-frames, each containing K frame (K is SPI programmable).
EAch of the multi-frames contains the frame start and frame end symbols. The second multi-frame also contains
the JESD204B link configuration data.
SYSREF
LMFC Clock
LMFC Boundary
Multi-
Frame
SYNC
Transmit Data
xxx
K28.5
K28.5
ILA
ILA
DATA
DATA
Code Group Synchronization
Initial Lane Alignment
Data Transmission
图7-39. JESD204B Internal Timing Diagram
7.3.6.1.1 SYNC Signal
The SYNC signal can be issued using one of two different methods:
• One of the GPIO1/2 pins can be configured via SPI to become the SYNC input pin (address 0x234 in the
digital page)
• The synchronization command can be issued via SPI register write (address 0x21 in the JESD page)
When using the GPIO1/2 pins for the SYNC signal input, the device also supports the option to invert the signal
polarity (address 0x236 in the digital page).
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7.3.6.2 JESD204B Frame Assembly
The JESD204B standard defines the following parameters:
• L: number of lanes per link
• M: number of converters per device
• F: number of octets per frame clock period
• S: number of samples per frame
7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
表7-28 lists the available JESD204B formats and corresponding valid sampling rate ranges for the ADC34RF52.
The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock
frequencies. The JESD204B frame assembly for the different lanes is shown in 表7-29.
表7-28. JESD Mode Options: Bypass Mode
DECIMATION
SETTING D
(complex)
OUTPUT
RESOLUTION
(Bits)
MIN FS
(Gsps)
MAX FS
(Gsps)
RATIO
[fSERDES/FS]
L
M
F
S
12(1)
8
8
4
4
4
4
8
2
2
10
2
0.5
0.5
0.5
1.5
1.3
8
Bypass
10
20
14/16(2)
1
0.65
(1) In full rate output, two LSBs are truncated to a 12-bit output.
(2) When using digital averaging the output resolution changes to 16-bit.
表7-29. JESD Sample Frame Assembly: Bypass Mode
OUTPUT
LANE
LMFS = 84810
LMFS = 8422
LMFS = 4421
A0[3:0],
A1[11:8]
A2[3:0],
A3[11:8]
A4[3:0],
0000
A0[5:0],
00
A0[5:0],
00
DOUT0 A0[11:4]
DOUT1 A5[11:4]
DOUT2 B0[11:4]
DOUT3 B5[11:4]
DOUT4 C0[11:4]
DOUT5 C5[11:4]
DOUT6 D0[11:4]
DOUT7 D5[11:4]
A1[7:0] A2[11:4]
A6[7:0] A7[11:4]
B1[7:0] B2[11:4]
B6[7:0] B7[11:4]
C1[7:0] C2[11:4]
C6[7:0] C7[11:4]
D1[7:0] D2[11:4]
D6[7:0] D7[11:4]
A3[7:0] A4[11:4]
A8[7:0] A9[11:4]
B3[7:0] B4[11:4]
B8[7:0] B9[11:4]
C3[7:0] C4[11:4]
C8[7:0] C9[11:4]
D3[7:0] D4[11:4]
D8[7:0] D9[11:4]
A0[13:6]
A0[13:6]
A5[3:0],
A6[11:8]
A7[3:0],
A8[11:8]
A9[3:0],
0000
A1[5:0],
00
B0[5:0],
00
A1[13:6]
B0[13:6]
B1[13:6]
C0[13:6]
C1[13:6]
D0[13:6]
D1[13:6]
B0[13:6]
C0[13:6]
D0[13:6]
B0[3:0],
B1[11:8]
B2[3:0],
B3[11:8]
B4[3:0],
0000
B0[5:0],
00
C0[5:0],
00
B5[3:0],
B6[11:8]
B7[3:0],
B8[11:8]
B9[3:0],
0000
B1[5:0],
00
D0[5:0],
00
C0[3:0],
C1[11:8]
C2[3:0],
C3[11:8]
C4[3:0],
0000
C0[5:0],
00
C5[3:0],
C6[11:8]
C7[3:0],
C8[11:8]
C9[3:0],
0000
C1[5:0],
00
D0[3:0],
D1[11:8]
D2[3:0],
D3[11:8]
D4[3:0],
0000
D0[5:0],
00
D5[3:0],
D6[11:8]
D7[3:0],
D8[11:8]
D9[3:0],
0000
D1[5:0],
00
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7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
表7-30 lists the available JESD204B formats and corresponding valid sampling rate ranges for the ADC34RF52.
The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock
frequencies. The JESD204B frame assembly for the different lanes is shown in 表7-31.
表7-30. JESD Mode Options: Real Decimation
DECIMATION
SETTING D
(complex)
MIN FS
(Gsps)
MAX FS
(Gsps)
RATIO
[fSERDES/(FS/D)]
L
M
F
S
/4
/8
0.5
0.8
8
4
2
2
1.5
10
20
/16
/4
/8
0.5
0.8
4
2
4
4
2
4
1
1
1.5
1.3
1.5
1.3
1.5
/16
/32
/4
/8
0.5
0.8
0.5
0.8
/16
/32
/64
/8
40
80
/16
/32
/64
/128
1
4
8
1
表7-31. JESD Sample Frame Assembly: Real Decimation - Single Band
OUTPUT
LANE
LMFS = 8422 LMFS = 4421
LMFS = 2441
LMFS = 1481
A0
A0
A0
A0
A0
A0
B0
B0
A0
A0
B0
B0
C0
C0
D0
D0
DOUT0
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
A1 A1 B0 B0 C0 C0 D0 D0
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
B0 B0 C0 C0
[15:8] [7:0] [15:8] [7:0]
B1 B1 D0 D0
[15:8] [7:0] [15:8] [7:0]
C0 C0
[15:8] [7:0]
C1 C1
[15:8] [7:0]
D0 D0
[15:8] [7:0]
D1 D1
[15:8] [7:0]
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
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7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
表 7-32 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the
ADC34RF52 with complex decimation (single band). The sampling rates are limited by the minimum and
maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the
different lanes are shown in 表7-33 and 表7-34.
表7-32. JESD Mode Options: Decimation - Single Band
DECIMATION
SETTING D
(complex)
MIN FS
(Gsps)
MAX FS
(Gsps)
RATIO
[fSERDES/(FS/D)]
L
M
F
S
/4
/8
0.5
0.8
8
8
2
1
1.5
1.3
1.5
20
40
/16
/32
/4
/8
0.5
0.8
/16
/32
/64
/4
4
2
1
8
8
8
4
8
1
1
1
0.65
1.3
/8
/16
/32
/64
/128
/8
0.5
0.8
0.5
80
1.5
0.65
1.3
/16
/32
/64
/128
16
160
1.5
表7-33. JESD Sample Frame Assembly: Decimation - Single Band
OUTPU
T
LMFS = 8821
LMFS = 4841
LMFS = 2881
LANE
AI0
[15:8]
AI0
[7:0]
AI0
[15:8]
AI0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
AI0
[15:8]
AI0
[7:0]
AQ0
[15:8]
AQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
AQ0
[15:8]
AQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
CI0
[15:8]
CI0
[7:0]
CQ0
[15:8]
CQ0
[7:0]
DI0
[15:8]
DI0
[7:0]
DQ0
[15:8]
DQ0
[7:0]
BI0
[15:8]
BI0
[7:0]
CI0
[15:8]
CI0
[7:0]
CQ0
[15:8]
CQ0
[7:0]
BQ0
[15:8]
BQ0
[7:0]
DI0
[15:8]
DI0
[7:0]
DQ0
[15:8]
DQ0
[7:0]
CI0
[15:8]
CI0
[7:0]
CQ0
[15:8]
CQ0
[7:0]
DI0
[15:8]
DI0
[7:0]
DQ0
[15:8]
DQ0
[7:0]
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表7-34. JESD Sample Frame Assembly: Decimation - Single Band
OUTP
UT
LMFS = 1-8-16-1
LANE
DOUT
0
AI0
AI0
AQ0
AQ0
CI0
CI0
CQ0
[15:8]
CQ0
[7:0]
BI0
BI0
BQ0
BQ0
DI0
DI0
DQ0
DQ0
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
DOUT
1
DOUT
2
DOUT
3
DOUT
4
DOUT
5
DOUT
6
DOUT
7
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7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
表 7-35 lists the available JESD204B interface formats and corresponding valid sampling rate ranges for the
ADC34RF52 with complex decimation (dual band). The sampling rates are limited by the minimum and
maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B frame assembly for the
different lanes are shown in 表7-36, 表7-37 and 表7-38.
表7-35. JESD Mode Options: Decimation - Dual Band
DECIMATION
SETTING D
(complex)
MIN FS
(Gsps)
MAX FS
(Gsps)
RATIO
[fSERDES/(FS/D)]
L
M
F
S
/8
/16
/32
/64
/8
0.5
0.8
8
16
4
1
1.5
1.5
40
80
/16
/32
/64
/128
/8
0.5
0.8
4
16
8
1
0.65
1.3
/16
/32
/64
/128
/16
/32
/64
/128
2
1
16
16
16
32
1
1
0.5
0.5
160
320
1.5
0.65
1.3
1.5
表7-36. JESD Sample Frame Assembly: Decimation - Dual Band
OUTPUT
LANE
LMFS = 8-16-4-1
LMFS = 4-16-8-1
A1I0
[15:8]
A1I0
[7:0]
A1Q0
[15:8]
A1Q0
[7:0]
A1I0
[15:8]
A1I0
[7:0]
A1Q0
[15:8]
A1Q0
[7:0]
A2I0
[15:8]
A2I0
[7:0]
A2Q0
[15:8]
A2Q0
[7:0]
DOUT0
A2I0
[15:8]
A2I0
[7:0]
A2Q0
[15:8]
A2Q0
[7:0]
B1I0
[15:8]
B1I0
[7:0]
B1Q0
[15:8]
B1Q0
[7:0]
B2I0
[15:8]
B2I0
[7:0]
B2Q0
[15:8]
B2Q0
[7:0]
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
B1I0
[15:8]
B1I0
[7:0]
B1Q0
[15:8]
B1Q0
[7:0]
C1I0
[15:8]
C1I0
[7:0]
C1Q0
[15:8]
C1Q0
[7:0]
C2I0
[15:8]
C2I0
[7:0]
C2Q0
[15:8]
C2Q0
[7:0]
B2I0
[15:8]
B2I0
[7:0]
B2Q0
[15:8]
B2Q0
[7:0]
D1I0
[15:8]
D1I0
[7:0]
D1Q0
[15:8]
D1Q0
[7:0]
D2I0
[15:8]
D2I0
[7:0]
D2Q0
[15:8]
D2Q0
[7:0]
CI0
[15:8]
C1I0
[7:0]
C1Q0
[15:8]
C1Q0
[7:0]
C2I0
[15:8]
C2I0
[7:0]
C2Q0
[15:8]
C2Q0
[7:0]
D1I0
[15:8]
D1I0
[7:0]
D1Q0
[15:8]
D1Q0
[7:0]
D2I0
[15:8]
D2I0
[7:0]
D2Q0
[15:8]
D2Q0
[7:0]
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表7-37. JESD Sample Frame Assembly: Decimation - Dual Band
OUTP
UT
LMFS = 2-16-16-1
LANE
DOUT A1I0
A1I0 A1Q0 A1Q0 A2I0
A2I0 A2Q0 A2Q0 B1I0
B1I0 B1Q0 B1Q0 B2I0
B2I0 B2Q0 B2Q0
0
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
DOUT C1I0 C1I0 C1Q0 C1Q0 C2I0 C2I0 C2Q0 C2Q0 D1I0 D1I0 D1Q0 D1Q0 D2I0 D2I0 D2Q0 D2Q0
1
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
DOUT
2
DOUT
3
DOUT
4
DOUT
5
DOUT
6
DOUT
7
表7-38. JESD Sample Frame Assembly: Decimation - Dual Band
OUTP
UT
LMFS = 1-16-32-1
LANE
A1I0
A1I0 A1Q0 A1Q0 A2I0
A2I0 A2Q0 A2Q0 B1I0
B1I0 B1Q0 B1Q0 B2I0
B2I0 B2Q0 B2Q0
...
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
DOUT
0
C1I0 C1I0 C1Q0 C1Q0 C2I0 C2I0 C2Q0 C2Q0 D1I0 D1I0 D1Q0 D1Q0 D2I0 D2I0 D2Q0 D2Q0
[15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0]
...
DOUT
1
DOUT
2
DOUT
3
DOUT
4
DOUT
5
DOUT
6
DOUT
7
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7.3.6.3 SERDES Output MUX
The SERDES output block contains one digital mux per SERDES output lane with a 3-bit register. This allows
routing any of the 8 digital lanes to any output serdes transmitter as shown in the example for output lane
DOUT0 in 图7-40.
Lane 0
Lane 1
MUX
DOUT0P/M
Lane 6
Lane 7
SPI:
Lane 0 mux
select
图7-40. SERDES Output Mux for DOUT0
By default after power the active SERDES lanes start on lane DOUT0 as shown for the complex decimation
single band example in 表 7-39. After power up the output is transmitted on lanes DOUT0..3. Using the digital
output muxes, the output data for channel B is shifted from lanes DOUT2,3 to DOUT4,5. All SERDES
transmitters are powered up and enabled by default. After configuring the output mux unused lanes can be
powered down to save power consumption.
表7-39. JESD Sample Frame Assembly: Complex Decimation - Single Band with LMFS = 4841
OUTPUT
Default
AQ0 [15:8]
Using MUX
LANE
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
AI0 [15:8]
BI0 [15:8]
CI0 [15:8]
DI0 [15:8]
AI0 [7:0]
BI0 [7:0]
CI0 [7:0]
DI0 [7:0]
AQ0 [7:0]
BQ0 [7:0]
CQ0 [7:0]
DQ0 [7:0]
AI0 [15:8]
BI0 [15:8]
AI0 [7:0]
AQ0 [15:8]
BQ0 [15:8]
AQ0 [7:0]
BQ0 [7:0]
BQ0 [15:8]
CQ0 [15:8]
DQ0 [15:8]
BI0 [7:0]
CI0 [15:8]
DI0 [15:8]
CI0 [7:0]
DI0 [7:0]
CQ0 [15:8]
DQ0 [15:8]
CQ0 [7:0]
DQ0 [7:0]
表7-40 shows the register writes to shift the output lanes from default as illustrated in 表7-39.
表7-40. Example register writes to shift the output serdes lanes using the SERDES Output MUX
ADDR
0x05
0x81
0x82
DATA
0x04
0x54
0x32
DESCRIPTION
Select JESD page
Select internal JESD streams 4 and 5 to lanes DOUT2 and DOUT3
Select internal JESD streams 2 and 3 to lanes DOUT4 and DOUT5
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7.3.7 Test Pattern
The ADC34RF52 provides several different options to output test patterns instead of the actual output data of the
ADC to simplify the serial interface and system debug of the JESD204B digital interface link. The output data
path is shown in 图7-41.
ADC Section
Digital Block
Transport Layer
Link Layer
PHY Layer
Data Mapping
Frame Construction
8b/10b
encoding
Decimation
Filter Block
ADC
Scrambler
1+x14+x15
Serializer
Transport Layer Test
Pattern
Link Layer Test Pattern
图7-41. Test Pattern Options
The available test patterns in each block are described in 表 7-41. Both test pattern blocks replace output data
from the digital block (and not from the ADC); therefore, are available in decimation or decimation bypass mode.
表7-41. Test Pattern Overview
TEST PATTERN LOCATION
TYPE
8b/10b encoded
REGISTER PAGE
REGISTER
0x2E, D0
0x2E, D1
0x2E, D2
0x2F, D0
CUSTOM PATTERN
TOGGLE 1010 PATTERN
RAMP PATTERN
Yes
Yes
TRANSPORT LAYER
Yes
JESD
0x05 0x04
PRBS PATTERN (27.. 231
)
Yes
JESD204B TEST PATTERNS
Depends
No
0x2D, D2-D0
0x2F, D4
LINK LAYER
PRBS PATTERN (27.. 231
)
The RAMP pattern provides two different output options. Internally each ADC data bus consists of 4 parallel data
streams (1 stream per serdes lane). The RAMP pattern is generated for each stream and a different starting
value can be set for each stream. By default the starting values are 0. For example a LMFS mode using 2
lanes/ADC would show a slow ramp which increments once every 2 clock cycles with starting values set to 0 and
ramp increment = 1. Also, a RAMP pattern which increments every clock cycle can be set using different starting
values (that is, 0/1) for the 2 streams/lanes and setting the RAMP increment to 2. 表 7-42 shows how to enable
the RAMP test pattern.
表7-42. Example Register Writes to Enable RAMP Test Pattern
ADDR
0x05
0x32
0x36
0x42
0x46
0x2E
DATA
0x04
0x01
0x03
0x01
0x03
0x14
DESCRIPTION
Select JESD page
Set lane DOUT1 starting value = 1
Set lane DOUT3 starting value = 1
Set lane DOUT5 starting value = 1
Set lane DOUT7 starting value = 1
Enable RAMP pattern, RAMP increment = 2
7.3.7.1 Transport Layer
The transport layer maps the ADC output data into 8-bit octets and constructs the JESD204B frames using the
LMFS parameters. Tail bits or 0's are added when needed. Alternatively, test patterns can be substituted instead
of the ADC data with the JESD frame, as shown in 表7-41.
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7.3.7.2 Link Layer
The link layer contains the scrambler and the 8b/10b encoding of any data passed on from the transport layer.
Additionally, the link layer also handles the initial lane alignment sequence that can be manually restarted. The
link layer test patterns are intended for testing the quality of the link (jitter testing and so forth). The test patterns
do not pass through the 8b/10b encoder and contain the options listed in 表7-41.
7.3.7.3 Internal Capture Memory Buffer
The ADC includes a small internal capture memory buffer which can store up to 64 samples. Once a strobe is
given to the memory using SPI register write, the memory will store the next continuous 64 samples of one ADC
channel (selected via SPI register write) and stop. The samples are captured from the ADC cores (prior to
averaging or decimation). These samples can be read back using the SPI interface without involving the
JESD204B interface at all.
This mode allows debug of the analog front end during the initial bring-up phase even if the JESD204B interface
is not operational yet.
表7-43. Register writes to enable the internal sample capture buffer
ADDR
0x05
DATA
DESCRIPTION
0x02
Select DIGITAL page
0x34
Select ADC channel (D5/D4) and give strobe (D6).
The 64 samples are stored in 0x800 to 0x87F in the digital page
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7.4 Device Functional Modes
The device offers two different operating modes: bypass mode and digital averaging. Both operating modes use
the same digital back end and JESD204B output configurations.
7.4.1 Bypass Mode
This default operating mode provides the lowest power consumption.
7.4.2 Digital Averaging
The ADC34RF52 provides a total of eight internal single core 1.5 Gsps ADCs. The normal operating mode uses
only four ADC cores (one ADC per channel). The four additional ADC cores can be enabled to trade off
additional noise density improvement against a small power increase. 图 7-42 shows the internal block diagram
in digital averaging mode where one external input is connected to 2 ADC cores internally.
ADC
50
,
100
ADC
INxP/M
图7-42. Internal Digital Averaging
表7-44 provides a trade-off comparison of digital averaging mode vs the non-averaged mode (default).
表7-44. Digital averaging vs full power input bandwidth (–3 dB)
# of ADCs averaged
Input Bandwidth (-3 dB)
Effective input termination
Noise density
-153 dBFS/Hz
-156 dBFS/Hz
Power/ch (W)
Default
2
1.6 GHz
0.7
1.0
100 Ω
100 Ω
1.5 GHz
Digital averaging improves decorrelated noise contributions by 3 dB per 2x AVG (ideal) while correlated noise
does not improve with averaging. Some of the dominant noise sources are correlated (that is, clock jitter
(external or first clock input buffer) or power supply noise) while others (that is, ADC thermal noise, clock
distribution buffers) are decorrelated.
SNR: When operating close to ADC full scale, some of the SNR limitation is due to jitter and hence the SNR
improvement won’t reach 3 dB (2x AVG). As the input full scale is reduced, the clock jitter contribution to SNR
becomes less and the SNR improvement is approaching the ideal 3 dB per 2x AVG. The same phenomenon can
be observed when using digital decimation. As the decimation factor increases, the close-in (correlated noise)
becomes the more dominating noise unless the input signal amplitude is reduced.
SFDR: The amplitude of low order harmonics (HD2-HD5) and IMD3 typically is similar across ADCs, and thus,
the improvement with averaging is small.
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7.5 Programming
The device is primarily configured and controlled using the serial programming interface (SPI); however, the
device can operate in a default configuration without requiring the SPI interface. Furthermore, the power down
function as well as internal/external reference configuration is possible via pin control (PDN/SYNC pin).
7.5.1 GPIO Pin Control
There are several commands which can be executed using SPI programming or GPIO pins. 表 7-45 provides an
overview of the commands available using GPIO pins.
表7-45. GPIO Pin Command Options
FEATURE
DESCRIPTION
JESD SYNC
NCO Control
Fast Overrange
Support for single ended CMOS or differential LVDS
Fast frequency hopping with 3 different control options
GPIO1 indicates overrange for channel A and B and GPIO2 for channel C and D. In this
mode the overrange indication can be made 'sticky' where flag needs to be cleared using
SPI commands.
Calibration Freeze
Freezes swapping of calibration ADC
7.5.2 Configuration using the SPI interface
The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting
bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when
SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.
When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples
of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20 MHz
down to ~ 1 MHz and also with a non-50% SCLK duty cycle.
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7.5.2.1 Register Write
The internal registers can be programmed following these steps:
1. Drive the SEN pin low
2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.
3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and
4. Write the 8-bit data that are latched in on the SCLK rising edges
图7-43 shows the timing requirements for the serial register write operation.
Register Address <11:0>
A7 A6 A5 A4
Register Data <7:0>
R/W
0
SDIO
0
0
0
A11 A10
A9
A8
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
tDH
D0
tSCLK
tDSU
SCLK
SEN
tSLOADS
tSLOADH
RESET
图7-43. Serial Register Write Timing Diagram
7.5.2.2 Register Read
The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.
This readback mode can be useful as a diagnostic check to verify the serial interface communication between
the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:
1. Drive the SEN pin low
2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address
field to 0.
3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read
4. The device outputs the contents (D[7:0]) of the selected register on the SDIO pin
5. The external controller can latch the contents at the SCLK falling edge
Register Address <11:0>
A7 A6 A5 A4
Register Data <7:0>
D5 D4 D3 D2
R/W
1
SDIO
0
0
0
A11 A10
A9
A8
A3
A2
A1
A0
D7
D6
D1
D0
SCLK
SEN
图7-44. Serial Register Read Timing Diagram
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7.6 Register Maps
表7-46. Register Map Summary
REGISTER
REGISTER DATA
ADDRESS
A[11:0]
0x00
PAGE
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
RESET
GLOBAL
ANALOG
PAGE
CALIB
PAGE
DDCCD
PAGE
DDCAB
PAGE
DIGITAL
PAGE
0x05
0
JESD PAGE
0
0x2C
0x2D
0x2E
0x33
0x34
20-BIT OUT
DDC BAND SEL
0
0
0
0
DDC REAL
0
BYP EN
0
0
0
0
DECIMATION
0
0
0
0
0
0
0
0
0
0
1
AVG EN
FORMAT
0
AVG SEL(1)
0
0
GBL PDN
0
MEM
MEM CH SEL
STROBE
0x3B
0x41
NCO2 CHB [1:0]
NCO2 CHD [1:0]
NCO1 CHB [1:0]
NCO1 CHD [1:0]
NCO2 CHA [1:0]
NCO2 CHC [1:0]
NCO1 CHA [1:0]
NCO1 CHC [1:0]
DIGITAL
0x22F
0x234
0X235
0x236
1
0
SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1 SYSREF OR
NCO SEL MODE GPIO MODE
1
0
0
NCO SEL SOURCE
0
0
GPIO2 INV GPIO1 INV GPIO SWAP
0
0
0
SYSREF SYSREF EN
RESET
0x238
0x20
OVR OUTPUT CFG
0
0
0
K
SYNC SPI
0x21
SYNC SPI
DROP LSB
0
0
SYSREF MODE
EN
0x22
0x24
0x25
0x27
0x28
0x2B
0x2D
0x2E
LMFS MODE
DDC CLK DIV
JESD TX CLK DIV
0
0
0
0
0
0
CLK BAL EN
0
SYNC INV
0
JESD TX LANE EN
0
0
0
0
0
0
0
0
0
0
0
0
TEST SEQ SEL
ALT PAT
RAMP INCR
PRBS PAT
RAMP EN
JESD PRBS
EN
0x2F
0
PRBS EN
0
JESD PRBS PAT
JESD
0x30
0x32
0x34
0x36
0x40
0x42
0x44
0x46
0x53
0x5C
0x5D
START VALUE JESD RAMP DOUT0
START VALUE JESD RAMP DOUT1
START VALUE JESD RAMP DOUT2
START VALUE JESD RAMP DOUT3
START VALUE JESD RAMP DOUT4
START VALUE JESD RAMP DOUT5
START VALUE JESD RAMP DOUT6
START VALUE JESD RAMP DOUT7
SCR EN
0
0
0
0
0
0
0
F in ILA
K in ILA
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表7-46. Register Map Summary (continued)
REGISTER
REGISTER DATA
ADDRESS
A[11:0]
0x7A
PAGE
D7
D6
D5
D4
D3
D2
D1
D0
JESD LANE POL INV
0x80
0
0
0
0
0
LANE DOUT1 SEL
LANE DOUT3 SEL
LANE DOUT5 SEL
LANE DOUT7 SEL
0
0
0
0
0
LANE DOUT0 SEL
LANE DOUT2 SEL
LANE DOUT4 SEL
LANE DOUT6 SEL
0x81
0x82
0x83
0x84
0
0
0
0
0
0
0
0
JESD PLL FACTOR
0x89
TX EMPH
DOUT1 [0]
TX EMPH DOUT0 [5:0]
0
0
0
0
0x8A
0x8B
0
0
0
0
0
TX EMPH DOUT1 [5:1]
TX EMPH DOUT2 [5:0]
TX EMPH
DOUT3 [0]
0x8C
0x8D
0
TX EMPH DOUT3 [5:1]
TX EMPH DOUT4 [5:0]
TX EMPH
DOUT5 [0]
JESD
0x8E
0x8F
0
TX EMPH DOUT5 [5:1]
TX EMPH DOUT6 [5:0]
TX EMPH
DOUT7 [0]
0x90
0x9D
0
TX EMPH DOUT7 [5:1]
PD DOUT7 PD DOUT6 PD DOUT5 PD DOUT4 PD DOUT3 PD DOUT2 PD DOUT1 PD DOUT0
[0] [0] [0] [0] [0] [0] [0] [0]
0x9E
PD DOUT7 PD DOUT6 PD DOUT5 PD DOUT4 PD DOUT3 PD DOUT2 PD DOUT1 PD DOUT0
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
0x9F
0
JESD PLL1
JESD PLL INPUT1
JESD PLL INPUT2
0
0
JESD PLL2
0xA0
0
0
0
0
0
0
0
0
0
0
0xA1
0
0
0xA2
0
0
0
0
JESD PLL INPUT3
0
0xED
0
JESD DDC BYP
0
0
0x100..0x105
0x108..0x10D
0x110..0x115
0x118..0x11D
0x120..0x125
0x128..0x12D
0x130..0x135
0x138..0x13D
0x140..0x145
0x148..0x14D
0x150..0x155
0x158..0x15D
0x160..0x165
0x168..0x16D
0x170..0x175
0x178..0x17D
0x181
NCO1 CHA/C FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHA/C FREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHA/C FREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHA/C FREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHA/C FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHA/C FREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHA/C FREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHA/C FREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHB/D FREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHB/DFREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHB/DFREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO1 CHB/DFREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHB/DFREQUENCY1 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHB/DFREQUENCY2 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHB/DFREQUENCY3 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
NCO2 CHB/DFREQUENCY4 [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
DDCAB/
CD
0
0
LOAD NCO
0
0
0
0
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表7-46. Register Map Summary (continued)
REGISTER
REGISTER DATA
ADDRESS
A[11:0]
0x34
PAGE
D7
D6
D5
D4
0
D3
0
D2
D1
D0
1
0
0
0
AVG SEL(2)
CALIBR
ATION
0x45
CAL SPI
CAL GPIO
0
0
1
0
1
0
0x298
0x7B
0
0
0
0
0
0
CAL STATUS
0
TERM AB
TERM CD
0
0
0
0
0
0
0
0
0
0
0
TERM AB
0x8B
0
0
TERM CD
0xA8
0
DITHER AMP1
0
0
0xAF
DITHER DIS
0
0
0
1
0
0xB1
DITHER DIVIDER
ANALOG
0xB4
0
0
0
0
0
0
0
SYSREF AC
EN
0xCD
0xE6
DITH AMP2
0
0
0
0
0
0
0
0
0
TX SWING
[0]
0
0
0
0
0xE7
0
0
0
0
TX SWING [2:1]
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7.6.1 Detailed Register Description
图7-45. Register 0x00
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
RESET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-47. Register 0x00 Field Descriptions
Bit
Field
0
Type
R/W
R/W
Reset
Description
7-1
0
0
0
Must write 0
RESET
This bit resets all internal registers to the default values. Does
not self clear to 0.
图7-46. Register 0x05
7
0
6
5
4
3
2
1
0
0
ANALOG PAGE CALIB PAGE
R/W-0 R/W-0
DDCCD PAGE DDCAB PAGE
R/W-0 R/W-0
JESD PAGE
R/W-0
DIGITAL PAGE
R/W-0
R/W-0
R/W-0
表7-48. Register 0x05 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
6
0
0
0
Must write 0
ANALOG PAGE
This bit enables access to the ANALOG page
0: ANALOG page access disabled
1: ANALOG page access enabled
5
4
CALIB PAGE
R/W
R/W
0
0
This bit enables access to the CALIBRATION page
0: CALIBRATION page access disabled
1: CALIBRATION page access enabled
DDCCD PAGE
This bit enables access to the DDCCD page. Contents can be
written to DDCAB and DDCCD page simultaneously if it is
identical.
0: DDCCD page access disabled
1: DDCCD page access enabled.
3
DDCAB PAGE
R/W
0
This bit enables access to the DDCAB page. Contents can be
written to DDCAB and DDCCD page simultaneously if it is
identical.
0: DDCAB page access disabled
1: DDCAB page access enabled
2
1
0
JESD PAGE
DIGITAL PAGE
0
R/W
R/W
R/W
0
0
0
This bit enables access to the JESD page
0: JESD page access disabled
1: JESD page access enabled
This bit enables access to the DIGITAL page
0: DIGITAL page access disabled
1: DIGITAL page access enabled
Must write 0
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图7-47. Register 0x2C (DIGITAL page)
7
6
5
4
3
2
0
1
0
20-BIT OUT
R/W-0
DDC BAND SEL
0
0
DDC REAL
R/W-0
BYP EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-49. Register 0x2C Field Descriptions
Bit
Field
20-BIT OUT
Type
Reset
Description
7
R/W
0
This bit enables the 20-bit output mode. It carries the output
sample with 20-bit output resolution from the DDC and the
sample is filled to 32-bit with 12 trailing 0s.
0: Normal operation
1: 20-bit output mode
6-5
DDC BAND SEL
R/W
00
Selects 1 or DDC per ADC when complex decimation is enabled
0: Single band
1: Dual band
2,3: not used
4-2
1
0
R
0
0
Must write 0
DDC REAL
R/W
This bit enables real decimation filter (NCO = 0). BYP EN (D0)
must be set to 0.
0: Complex decimation
1: Real decimation
0
BYP EN
R/W
0
This bit enables DDC bypass mode
0: Decimation filter enabled. Complex decimation by default
unless D1 is set
1: Decimation filter bypass
图7-48. Register 0x2D (DIGITAL page)
7
0
6
5
4
3
2
0
1
0
0
0
DECIMATION
R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-50. Register 0x2D Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
0
0
0
Must write 0
6-4
DECIMATION
Selects decimation.
0,1: not used
2: Decimation by 4
3: Decimation by 8
4: Decimation by 16
5: Decimation by 32
6: Decimation by 64
7: Decimation by 128
3-0
0
R/W
0
Must write 0
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图7-49. Register 0x2E (DIGITAL page)
7
0
6
0
5
0
4
3
2
1
0
0
0
AVG EN
R/W-0
AVG SEL (1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-51. Register 0x2E Field Descriptions
Bit
Field
0
Type
R/W
R/W
Reset
Description
7-4
3
0
0
Must write 0
AVG EN
This bit enables averaging
0: no average
1: ADC averaging enabled
2-1
0
AVG SEL (1)
R/W
00
Selects ADC averaging. Also AVG SEL (2) in CALIBRATION
page needs to be set.
0: no average
1: 2 ADC average
0
R/W
0
Must write 0
图7-50. Register 0x33 (DIGITAL page)
7
0
6
5
0
4
3
2
0
1
0
0
0
1
FORMAT
R/W-0
GBL PDN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-52. Register 0x33 Field Descriptions
Bit
Field
Type
R/W
R/W
R/W
Reset
Description
Must write 0
Must write 1
7-5
4
0
0
0
0
1
3
FORMAT
This register bit determines the output data format in DDC
bypass mode only.
0: Offset Binary
1: 2s Complement
DDC mode only supports 2s complement output format.
2
1
0
R/W
R/W
0
0
Must write 0
GBL PDN
This register bit enables global power down mode
0: normal operation
1: global power down mode enabled
0
0
R/W
0
Must write 0
图7-51. Register 0x34 (DIGITAL page)
7
0
6
5
4
3
2
0
1
0
0
0
MEM STROBE
R/W-0
MEM CH SEL
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-53. Register 0x34 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
6
0
0
0
Must write 0
MEM STROBE
This register enables fast power down mode
0: normal operation
1: fast power down mode enabled
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表7-53. Register 0x34 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-4
MEM CH SEL
R/W
0
This register selects which ADC channel is used to fill up the
capture sample buffer. Only 1 channel can be selected at a time
and the samples are captured from the ADC core without
averaging or decimation.
00: capture memory is filled from chA input
01: capture memory is filled from chB input
10: capture memory is filled from chC input
11: capture memory is filled from chD input
0
0
R/W
0
Must write 0
图7-52. Register 0x3B (DIGITAL page)
7
6
NCO2 CHB [1:0]
R/W-0 R/W-0
5
4
3
2
1
0
NCO1 CHB [1:0]
NCO2 CHA [1:0]
NCO1 CHA [1:0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-54. Register 0x3B Field Descriptions
Bit
Field
Type
Reset
Description
7-6
NCO2 CHB [1:0]
R/W
00
This register is used when selecting the NCO frequency for
channel B, band 2 with the SPI interface in dual band DDC
mode.
5-4
3-2
NCO1 CHB [1:0]
NCO2 CHA [1:0]
R/W
R/W
00
00
This register is used when selecting the NCO1 of channel B with
the SPI interface.
This register is used when selecting the NCO frequency for
channel A, band 2 with the SPI interface in dual band DDC
mode.
1-0
NCO1 CHA [1:0]
R/W
00
This register is used when selecting the NCO1 of channel A with
the SPI interface.
图7-53. Register 0x41 (DIGITAL page)
7
6
NCO2 CHD [1:0]
R/W-0 R/W-0
5
4
3
2
1
0
NCO1 CHD [1:0]
NCO2 CHC [1:0]
NCO1 CHC [1:0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-55. Register 0x41 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
NCO2 CHD [1:0]
R/W
00
This register is used when selecting the NCO frequency for
channel D, band 2 with the SPI interface in dual band DDC
mode.
5-4
3-2
NCO1 CHD [1:0]
NCO2 CHC [1:0]
R/W
R/W
00
00
This register is used when selecting the NCO1 of channel D with
the SPI interface.
This register is used when selecting the NCO frequency for
channel C, band 2 with the SPI interface in dual band DDC
mode.
1-0
NCO1 CHC [1:0]
R/W
00
This register is used when selecting the NCO1 of channel C with
the SPI interface.
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图7-54. Register 0x22F (DIGITAL page)
7
6
5
4
3
2
1
0
1
1
SYSREF X5
R/W-0
SYSREF X4
R/W-0
SYSREF X3
R/W-0
SYSREF X2
R/W-0
SYSREF X1
R/W-0
SYSREF OR
R/W-0
R/W-0
R/W-0
表7-56. Register 0x22F Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
1
1
0
Must write 1
6-2
SYSREF X1..5
These bits are the XOR flags from the SYSREF window
monitoring circuitry. The sampling clock gets delayed internally
by ~ 160 ps and used to capture the SYSREF signal. If a
SYSREF signal transition happens within +/- 50 ps of the
SYSREF capture the appropriate XOR flag gets raised. These
bits are not sticky - they get overwritten with the next SYSREF
rising edge.
X1: Window from 110 ps to 135 ps after the rising sampling
clock edge
X2: Window from 135 ps to 160 ps after the rising sampling
clock edge
X3: Window from 160 ps to 176 ps after the rising sampling
clock edge
X4: Window from 176 ps to 192 ps after the rising sampling
clock edge
X5: Window from 192 ps to 208 ps after the rising sampling
clock edge
0: No SYSREF transition detected
1: SYSREF transition detected within given window
1
0
SYSREF OR
R/W
R/W
0
1
This bit is the output of the five SYSREF XOR flags logically
OR'ed together.
0: no SYSREF flag raised
1: one of the five SYSREF XOR flags is raised.
1
Must write 1
图7-55. Register 0x234 (DIGITAL page)
7
0
6
5
4
3
2
1
0
NCO SEL MODE
0
0
GPIO MODE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-57. Register 0x234 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
0
0
Must write 0
6-5
NCO SEL MODE
00
These bits select control of the NCO selection in complex
decimation.
0: NCO selection using GPIO pins (GPIO MODE (D2-D0) needs
to be set accordingly)
2: GPIO1/2 pins are used as a fast serial interface to only up
NCO selection for each digital mixer
others: not used
4-3
2-0
0
R/W
R/W
0
Must write 0
GPIO MODE
000
This register sets the functionality of the two GPIO pins
0: GPIO pins are used as SYNC input (LVDS), GPIO1 = SYNCP,
GPIO2 = SYNCM
1: GPIO1 is used as SYNC input (CMOS)
3: Both GPIO pins are used to select NCOs for the decimation
filters
4: GPIO1 is used to disable the calibration
5: GPIO1 is used as start of SYSREF counter
others: not used
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图7-56. Register 0x235 (DIGITAL page)
7
6
5
4
3
2
1
0
NCO SEL SOURCE
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-58. Register 0x235 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO SEL SOURCE
R/W
0
This register works in conjuction with NCO SEL MODE (0x234).
0x00: NCO selection other than regular SPI (GPIO, Fast SPI
etc)
0xFF: NCO selection using regular SPI with addresses 0x3B/41.
图7-57. Register 0x236 (DIGITAL page)
7
0
6
5
4
3
2
1
0
0
0
GPIO2 INV
R/W-0
GPIO1 INV
R/W-0
GPIO SWAP
R/W-0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-59. Register 0x236 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
6
0
0
0
Must write 0
GPIO2 INV
This bit inverts polarity of the GPIO2 pin
0: Polarity as is
1: Polarity inverted
5
4
GPIO1 INV
GPIO SWAP
0
R/W
R/W
R/W
0
0
0
This bit inverts polarity of the GPIO1 pin
0: Polarity as is
1: Polarity inverted
This bit swaps GPIO1 and GPIO2 pins internally.
0: Normal operation
1: GPIO1 and GPIO2 are swapped
3-0
Must write 0
图7-58. Register 0x238 (DIGITAL page)
7
6
5
4
3
2
1
0
0
0
OVR OUTPUT CFG
R/W-0 R/W-0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-60. Register 0x238 Field Descriptions
Bit
Field
OVR OUTPUT CFG
Type
Reset
Description
7-4
R/W
0000
This bit configures if the overrange indication (OVR) is output on
JESD output stream or on GPIO pins
0000: OVR on JESD
1111: OVR on GPIO
3-0
0
R/W
0
Must write 0
图7-59. Register 0x20 (JESD page)
7
6
5
4
3
2
1
0
K
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-61. Register 0x20 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
K
R/W
00000000 This is JESD204B parameter K which sets number of frames in
a multi-frame. Bit value is set as K minus 1.
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图7-60. Register 0x21 (JESD page)
7
6
5
4
3
2
1
0
0
SYNC SPI EN
R/W-0
SYNC SPI
R/W-0
0
0
SYSREF MODE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-62. Register 0x21 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
6
0
0
0
Must write 0
SYNC SPI EN
This bit enables JESD SYNC control using SPI (ignoring SYNC
using GPIO1/2 pins) using bit D5 (SYNC SPI).
0: SPI SYNC disabled
1: SPI SYNC (using register bit D5) enabled
5
SYNC SPI
R/W
0
This bit enables JESD SYNC. SYNC control via SPI must be
enabled also (D6).
0: ADC outputs data (SYNC disabled)
1: SYNC enabled (ADC outputs K28.5 characters for JESD
interface synchronization)
4-3
2-0
0
R/W
R/W
0
Must write 0
SYSREF MODE
000
This register controls how the ADC processes incoming
SYSREF pulses.
0: Ignore all SYSREF pulses
1: Use all SYSREF pulses
2: Don't use SYSREF pulses
3: Skip one SYSREF pulse then use only the next one
4: Skip one SYSREF pulse then use all pulses
5: Skip two SYSREF pulses and then use one
6: Skip two SYSREF pulses and then use all
图7-61. Register 0x22 (JESD page)
7
6
5
4
3
2
1
0
JESD MODE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-63. Register 0x22 Field Descriptions
Bit
7:0
Field
Type
Reset
Description
JESD MODE
R/W
00000000 This register sets the LMFS configuration
1: LMFS = 8-2-2-4
2: LMFS = 8-4-8-10 (also bit DROP LSB in 0x27 needs to be
set)
3: LMFS = 8-4-2-2
4: LMFS = 8-16-4-1
5: LMFS = 4-16-8-1
6: LMFS = 2-16-16-1
7: LMFS = 1-16-32-1
8: LMFS = 8-8-2-1
9: LMFS = 4-8-4-1
10: LMFS = 2-8-8-1
11: LMFS = 1-8-16-1
12: LMFS = 4-4-2-1
13: LMFS = 2-4-4-1
14: LMFS = 1-4-8-1
others: not used
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图7-62. Register 0x24 (JESD page)
7
6
5
4
3
2
1
0
DDC CLK DIV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-64. Register 0x24 Field Descriptions
Bit
Field
DDC CLK DIV
Type
Reset
Description
7-0
R/W
00000000 This register sets the internal clock divider when using the
decimation filter. See 表7-66
图7-63. Register 0x25 (JESD page)
7
6
5
4
3
2
1
0
JESD TX CLK DIV
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-65. Register 0x25 Field Descriptions
Bit
7-0
Field
JESD TX CLK DIV
Type
Reset
Description
R/W
0000000
This register sets the internal clock divider for the selected
LMFS output mode. See 表7-66
表7-66. Register settings for 0x24/0x25 based on bypass/decimation and LMFS mode
0x24 (DDC CLK DIV)
0x25 (JESD TX CLK DIV)
LMFS
BYP
/4
/8
/16
/32
/64
/128
BYP
/4
/8
/16
/32
/64
/128
8-4-8-10
8-4-2-2
1
1
3
4
0
0
4-4-2-1
8-8-2-1
0
1
3
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8-16-4-1
4-8-4-1
1
1
1
1
1
4-16-8-1
2-8-8-1
3
3
3
3
3
3
3
3
3
3
2-16-16-1
1-8-16-1
1-16-32-1
7
7
7
7
7
7
7
7
7
7
15
15
15
15
15
图7-64. Register 0x27 (JESD page)
7
0
6
0
5
4
3
2
0
1
0
0
DROP LSB
R/W-0
0
0
CLK BAL EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-67. Register 0x27 Field Descriptions
Bit
7-6
5
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
DROP LSB
This register needs to be set when using the 12-bit output LMFS
mode.
0: Drop LSB disabled
1: Drop LSB enabled when using LMFS = 8-4-8-10
4-2
1
0
R/W
R/W
0
0
Must write 0
CLK BAL EN
This register bit needs to be enabled in bypass mode LMFS =
8-4-2-2 only in order to improve some internal clock balancing.
0: CLK BAL disabled
1: CLK BAL EN. Set for LMFS = 8-4-2-2
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表7-67. Register 0x27 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
0
R/W
0
Must write 0
图7-65. Register 0x28 (JESD page)
7
6
5
4
3
2
1
0
JESD LANE EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-68. Register 0x28 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
JESD LANE EN
R/W
11111111
This register turns on individual output lanes
0: Lane powered down
1: Serdes lane enabled
D0: Lane DOUT0
D1: Lane DOUT1
...
D7: Lane DOUT7
图7-66. Register 0x2B (JESD page)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
SYNC INV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-69. Register 0x2B Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-1
0
0
0
0
Must write 0
SYNC INV
This register inverts the polarity from external SYNC pin
0: Polarity as is
1: Polarity inverted
图7-67. Register 0x2D (JESD page)
7
0
6
0
5
0
4
3
2
1
0
0
0
JESD SEQ SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-70. Register 0x2D Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-3
2-0
0
0
Must write 0
JESD SEQ SEL
000
This register selects the JESD test pattern sequence
0: Test sequence disabled
1: Repeat D21.5 high frequency pattern for random jitter (RJ)
2: Repeat K28.5 mixed frequency pattern for deterministic jitter
(DJ)
3: Repeat initial lane alignment (ILA) sequence
4: Modified random pattern
5: Scrambled jitter pattern
6: Repeat K28.7 low frequency pattern
7: Short test pattern
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图7-68. Register 0x2E (JESD page)
7
6
5
4
3
2
1
0
RAMP INCR
0
RAMP EN
R/W-0
ALT PAT
R/W-0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-71. Register 0x2E Field Descriptions
Bit
Field
RAMP INCR
Type
Reset
Description
7-4
R/W
0000
This register value sets the increment step size for the ramp
pattern on 16-bit output. The step size is RAMP INCR plus 1.
3
2
1
0
R/W
R/W
R/W
0
0
0
Must write 0
RAMP EN
ALT PAT
Enables RAMP output pattern in the TRANSPORT LAYER.
Enables a toggle pattern switching between 0x0000 and 0xFFFF
in the TRANSPORT LAYER
0
0
R/W
0
Must write 0
图7-69. Register 0x2F (JESD page)
7
0
6
5
4
3
2
1
0
SERDES PRBS
SERDES PRBS
EN
0
JESD PRBS
JESD PRBS EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-72. Register 0x2F Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
0
0
0
Must write 0
6-5
SERDES PRBS
This register selects the PRBS pattern in the LINK LAYER (no
8b/10b encoding). PRBS pattern must be enabled (D4).
0: PRBS 27-1
1: PRBS 215-1
2: PRBS 223-1
3: PRBS 231-1
4
SERDES PRBS EN
R/W
0
This register enables PRBS test pattern in the LINK LAYER
0: Test pattern mode disabled
1: PRBS test pattern mode enabled
3
0
R/W
R/W
0
0
Must write 0
2-1
JESD PRBS
This register selects the PRBS pattern in the TRANSPORT
LAYER (test pattern will be 8b/10b encoded). PRBS pattern
must be enabled (D0).
0: PRBS 27-1
1: PRBS 215-1
2: PRBS 223-1
3: PRBS 231-1
0
JESD PRBS EN
R/W
0
This register enables PRBS test pattern in the TRANSPORT
LAYER
0: Test pattern mode disabled
1: PRBS test pattern mode enabled
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图7-70. Register 0x30/32/34/36/40/42/44/46 (JESD page)
7
6
5
4
3
2
1
0
START VALUE JESD RAMP DOUT0/1/2/3/4/5/6/7
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-73. Register 0x30/32/34/36/40/42/44/46 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
START VALUE JESD RAMP
DOUT0/1/2/3/4/5/6/7
R/W
00000000 The JESD RAMP test pattern is designed to act as an individual
RAMP pattern on each output lane. If the starting value on each
lane is set to 0 (default) each output lane shows the same
RAMP code at any given time.
The RAMP pattern can be configured such that the RAMP
pattern is constructed across JESD output lanes using the start
value registers.
DOUT1=1, DOUT2=2, DOUT3=3, DOUT4=0, DOUT5=1,
DOUT6=2 and DOUT7=3 as well as the RAMP increment to 4
(RAMP INCR (0x2E) = 0x30) results in a RAMP pattern across
lanes for each channel in bypass mode.
图7-71. Register 0x53 (JESD page)
7
6
0
5
0
4
3
2
0
1
0
0
0
SCR EN
R/W-0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-74. Register 0x53 Field Descriptions
Bit
Field
Type
Reset
Description
7
SCR EN
R/W
0
Enables scrambling of the JESD output data
0: Output scrambling disabled
1: Output scrambling enabled
6-0
0
R/W
0
Must write 0
图7-72. Register 0x5C (JESD page)
7
6
5
4
3
2
1
0
F in ILA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-75. Register 0x53 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
F in ILA
R/W
0
These bits set F in the ILA sequence. Register value is actual F
value -1 (0x01 = F(2)).
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图7-73. Register 0x5D (JESD page)
7
6
5
4
3
2
1
0
K in ILA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-76. Register 0x5D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
K in ILA
R/W
0
These bits set K in the ILA sequence. Register value is actual K
value -1 (0x0F = K(15))
图7-74. Register 0x7A (JESD page)
7
6
5
4
3
2
1
0
JESD LANE POL INV
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-77. Register 0x7A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD LANE POL INV
R/W
00000000 This register inverts the polarity of the individual SERDES output
lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1
to DOUT1 etc
0: Output polarity as is
1: Output polarity inverted
图7-75. Register 0x80/81/82/83 (JESD page)
ADDR
0x80
0x81
0x82
0x83
7
6
5
4
3
2
1
0
0
LANE DOUT1 SEL
LANE DOUT3 SEL
LANE DOUT5 SEL
LANE DOUT7 SEL
R/W-0
0
LANE DOUT0 SEL
LANE DOUT2 SEL
LANE DOUT4 SEL
LANE DOUT6 SEL
R/W-0
0
0
0
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-78. Register 0x80/81/82/83 Field Descriptions
Bit
7,3
6-4
2-0
Field
Type
R/W
R/W
R/W
Reset
Description
0
0
Must write 0
LANE DOUT1/3/5/7 SEL
LANE DOUT0/2/4/6 SEL
000
000
These register bits control the output mux. Any physical serdes
output lane (DOUTx) can be connected to any JESD digital
stream. By default lane DOUT0 is connected to JESD stream 0,
lane DOUT1 to JESD stream 1 etc.
0: JESD stream 0
1: JESD stream 1
...
7: JESD stream 7
图7-76. Register 0x84 (JESD page)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
JESD PLL FACTOR
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-79. Register 0x84 Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
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表7-79. Register 0x84 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
JESD PLL FACTOR
R/W
00
This register bit must be set for 12-bit output LMFS = 8-4-8-10
only.
0: all other JESD LMFS modes
1: Set for LMFS = 8-4-8-10
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图7-77. Register 0x89/8A/8B/8C/8D/8E/8F/90 (JESD page)
7
6
0
0
0
5
0
0
0
4
3
2
1
0
0
TX EMPH
DOUT1 [0]
TX EMPH DOUT0 [5:0]
TX EMPH DOUT2 [5:0]
TX EMPH DOUT4 [5:0]
TX EMPH DOUT6 [5:0]
0
TX EMPH DOUT1 [5:1]
TX EMPH DOUT3 [5:1]
TX EMPH DOUT5 [5:1]
TX EMPH
DOUT3 [0]
0
0
0
0
TX EMPH
DOUT5 [0]
0
TX EMPH
DOUT7 [0]
0
0
0
TX EMPH DOUT7 [5:1]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-80. Register 0x89/8A/8B/8C/8D/8E/8F/90 Field Descriptions
Bit
7-5,0
6-1
Field
Type
R/W
R/W
R/W
Reset
Description
0
0
Must write 0
TX EMPH DOUT0/2/4/6 [5:0]
TX EMPH DOUT1/3/5/7 [5:0]
000000
000000
These bits select the amount of de-emphasis for the JESD
output transmitter. The de-emphasis value in dB is measured as
the ratio between the peak value after the signal transition to the
4-0,7
settled value of the voltage in one bit period.
0: 0 dB
1: –1 dB
3: –2 dB
7: –4.1 dB
15: –6.2 dB
31: –8.2 dB
63: –11.5 dB
图7-78. Register 0x9D/9E (JESD page)
7
6
5
4
3
2
1
0
PD DOUT7
[0,1]
PD DOUT6
[0,1]
PD DOUT5
[0,1]
PD DOUT4
[0,1]
PD DOUT3
[0,1]
PD DOUT2
[0,1]
PD DOUT1
[0,1]
PD DOUT0
[0,1]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-81. Register 0x9D/9E Field Descriptions
Bit
Field
Type
Reset
Description
7-0
PD DOUTx [0,1]
R/W
0
Register 0x9D and 0x9E allow power down of individual serdes
output lanes. Register 0x9D (PD DOUTx [0]) covers the output
driver, 0x9E (PD DOUTx [1]) covers the associated internal
high-speed data clock.
0: Output lane enabled
1: Output lane powered down
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图7-79. Register 0x9F (JESD page)
7
0
6
5
4
3
2
1
0
JESD PLL1
R/W-0
0
JESD PLL2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-82. Register 0x9F Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
0
0
Must write 0
6-4
JESD PLL1
000
Internal JESD PLL input divider setting. See 表7-84 how to
configure it for the different decimation and LMFS settings.
3
0
R/W
R/W
0
Must write 0
2-0
JESD PLL2
000
Internal JESD PLL input divider setting. See 表7-84 how to
configure it for the different decimation and LMFS settings.
图7-80. Register 0xA0/A1/A2 (JESD page)
ADDR
0xA0
0xA1
0xA2
7
0
0
0
6
5
4
3
0
0
2
1
0
0
0
JESD PLL INPUT1
JESD PLL INPUT2
0
0
0
0
0
0
0
0
JESD PLL INPUT3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-83. Register 0xA0/A1/A2 Field Descriptions
Bit
7-0
6-4
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
JESD PLL INPUT1/2
000
Internal JESD PLL input divider setting. See 表7-84 how to
configure it for the different decimation and LMFS settings.
3-1
JESD PLL INPUT3
R/W
000
Internal JESD PLL input divider setting. See 表7-84 how to
configure it for the different decimation and LMFS settings.
表7-84. Register settings for 0x9F/A0/A1/A2 based on bypass/decimation and LMFS mode
JESD PLL1/2, JESD PLL INPUT 2
JESD PLL INPUT 1
JESD PLL INPUT 3
LMFS
8-4-8-10
8-4-2-2
BYP /4
/8
/16 /32 /64 /128 BYP /4
/8
/16 /32 /64 /128 BYP /4
/8
/16 /32 /64 /128
0
0
0
0
0
0
1
1
3
4-4-2-1
8-8-2-1
0
1
0
1
0
0
0
0
0
2
1
2
1
0
0
0
0
0
3
2
3
2
1
1
0
0
0
4
3
4
3
2
2
1
1
0
5
4
5
4
3
3
2
2
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
2
1
2
1
0
0
0
0
0
3
2
3
2
1
1
0
0
0
4
3
4
3
2
2
1
1
0
5
4
5
4
3
3
2
2
1
0
1
0
0
0
1
1
3
3
0
0
0
0
0
0
1
1
3
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8-16-4-1
4-4-2-1
0
0
0
1
4-8-4-1
4-16-8-1
2-8-8-1
0
3
2-16-16-1
1-8-16-1
1-16-32-1
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图7-81. Register 0xED (JESD page)
7
0
6
0
5
4
3
2
0
1
0
0
0
JESD DDC BYP
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-85. Register 0xED Field Descriptions
Bit
7-6
5-4
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
JESD DDC BYP
00
This register needs to be set for the internal JESD frame
assembly in DDC bypass output mode:
0: Any DDC mode
1: LMFS = 8-4-2-2 or 8-4-8-10
2: LMFS = 4-4-2-1
3-0
0
R/W
0
Must write 0
图7-82. Register 0x100..0x17D (DDCAB/CD page)
7
6
5
4
3
2
1
0
NCOx FREQUENCYx [7:0],[15:8],[23:16],[31:24],[39:32],[47:40]
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-86. Register 0x100..0x17D Field Descriptions
Bit
47:0
Field
Type
Reset
Description
NCOx CHAB/CD FREQUENCYx
R/W
0
The frequencies for NCOs are located in addresses 0x100 to
0x17D. Each frequency is 48-bit and the MSB starts on the
highest address.
图7-83. Register 0x181 (DDCAB/CD page)
7
6
0
5
4
3
2
1
0
0
0
0
LOAD NCO
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-87. Register 0x181 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5-4
0
0
Must write 0
LOAD NCO
00
This register loads all the NCO frequencies from the memory to
the NCOs. To update the NCO this register has to be set to 3
and back to 0 as shown in 表7-88
3-0
0
R/W
0
Must write 0
表7-88. NCO frequency programming example
ADDR
DATA
DESCRIPTION
0x105
0x4E
0x81
0xB4
0xE8
0x1B
0x4E
0x00
0x30
0x104
0x103
0x102
0x101
0x100
0x181
0x181
Frequency = 460 MHz with FS = 1.3 GSPS
99,598,837,913,001 = 0x5A95A95A95A9 where the MSB goes to address 0x105 and the
LSB to 0x100.
Load and update all NCO frequencies
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图7-84. Register 0x34 (CALIBRATION page)
7
0
6
0
5
4
3
2
1
0
1
0
0
0
AVG SEL (2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-89. Register 0x34 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-3
2-1
0
0
Must write 0
AVG SEL (2)
00
Selects ADC averaging. Also AVG SEL (1) in DIGITAL page
needs to be set.
0: no average
01: 2 ADC average
10/11: not used
0
1
R/W
1
Must write 1
图7-85. Register 0x45 (CALIBRATION page)
7
6
5
4
3
2
1
1
0
0
CAL SPI
R/W-0
CAL GPIO
R/W-0
0
0
1
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-90. Register 0x45 Field Descriptions
Bit
Field
Type
Reset
Description
7
CAL SPI
R/W
0
This register triggers the calibration using SPI write. It needs to
be toggled (0=>1=>0).
6
5-4
3
CAL GPIO
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
1
0
This register triggers the calibration using the GPIO1 pin.
0
1
0
1
0
Must write 0
Must write 1
Must write 0
Must write 1
Must write 0
2
1
0
图7-86. Register 0x298 (CALIBRATION page)
7
0
6
0
5
4
3
2
1
0
0
0
CAL STATUS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-91. Register 0x298 Field Descriptions
Bit
7-4
3-0
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
CAL STATUS
0000
This register can be used to check if calibration state machine
has finished without any errors. A value of 0xE indicates
successful calibration.
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图7-87. Register 0x7B (ANALOG page)
7
0
6
0
5
4
3
2
1
0
0
TERM AB
R/W-0
0
0
0
TERM AB
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-92. Register 0x7B Field Descriptions
Bit
7-6
5,0
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
TERM AB
00
This register sets the internal termination resistor at the analog
inputs for channel A and B.
0: 100 ohm differential termination
1: 50 ohm differential termination
4-1
0
R/W
0
Must write 0
图7-88. Register 0x8B (ANALOG page)
7
0
6
0
5
4
3
2
1
0
0
TERM CD
R/W-0
0
0
0
TERM CD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-93. Register 0x8B Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-6
5,0
0
0
Must write 0
TERM CD
00
This register sets the internal termination resistor at the analog
inputs for channel C and D.
0: 100 ohm differential termination
1: 50 ohm differential termination
4-1
0
R/W
0
Must write 0
图7-89. Register 0xA8 (ANALOG page)
7
0
6
5
4
3
2
1
0
0
0
DITH AMP1
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-94. Register 0xA8 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7
0
0
Must write 0
6-3
DITH AMP1
0000
This register sets dither amplitude coarse gain. There are two
recommended settings:
0000: Amplitude = 0
0011: Amplitude = 3
Here is a list of all the settings:
0000: Amplitude = 0 (smallest)
0001: Amplitude = 1
...
1110: Amplitude = 14
1111: Amplitude = 15 (largest)
2-0
0
R/W
0
Must write 0
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图7-90. Register 0xAF (ANALOG page)
7
6
0
5
4
3
2
1
0
0
0
DITHER DIS
0
1
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-95. Register 0xAF Field Descriptions
Bit
Field
Type
Reset
Description
7
DITHER DIS
R/W
0
This register disables internal dither.
0: Dither enabled
1: Dither disabled
6-5
4
0
1
0
R/W
R/W
R/W
0
0
0
Must write 0
Must write 1
Must write 0
3-0
图7-91. Register 0xB1 (ANALOG page)
7
6
5
4
3
2
1
0
DITHER DIVIDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-96. Register 0xB1 Field Descriptions
Bit
7-0
Field
Type
Reset
Description
DITHER DIVIDER
R/W
0
This register sets the dither divider frequency. SPI write is actual
-1. For example a divider of 48 is 47 (0x2F).
0x00 (default) is a divide /50
图7-92. Register 0xB4 (ANALOG page)
7
0
6
0
5
4
3
2
1
0
0
0
0
0
0
SYSREF AC
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-97. Register 0xB4 Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
7-1
0
0
0
0
Must write 0
SYSREF AC
This register enables external AC coupling of the SYSREF input
with internal biasing.
0: External DC coupling with internal 100 Ωtermination
1: External AC coupling with internal biasing
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图7-93. Register 0xCD (ANALOG page)
7
0
6
5
4
3
2
1
0
0
0
DITH AMP2
R/W-0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-98. Register 0xCD Field Descriptions
Bit
7
Field
Type
R/W
R/W
Reset
Description
0
0
0
Must write 0
6-4
DITH AMP2
This register sets dither amplitude fine gain. There are two
recommended settings:
000: Amplitude = 0
100: Amplitude = -4
Here is a list of all the settings:
000: Amplitude = 0
001: Amplitude = 1
010: Amplitude = 2
011: Amplitude = 3 (largest)
100: Amplitude = -4 (smallest)
101: Amplitude = -3
110: Amplitude = -2
111: Amplitude = -1
5-0
0
R/W
0
Must write 0
图7-94. Register 0xE6/E7 (ANALOG page)
ADDR
0xE6
0xE7
7
TX SWING [0]
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TX SWING [2:1]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表7-99. Register 0xE6/E7 Field Descriptions
Bit
7-0
Field
Type
R/W
R/W
Reset
Description
0
0
Must write 0
1,0,7
TX SWING [2:0]
000
This register adjusts the output amplitude on all 8 serdes lanes.
0: 850 mVpp
1: 825 mVpp
2: 800 mVpp
3: 775 mVpp
4: 950 mVpp
5: 925 mVpp
6: 900 mVpp
7: 875 mVpp
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8 Application Information Disclaimer
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The ADC34RF52 can be used in a wide range of applications including radar, frequency domain digitizer and
spectrum analyzer, test and communications equipment and software-defined radios (SDRs). The Typical
Applications section describe one configuration that meets the needs of a number of these applications.
8.2 Typical Application
8.2.1 Wideband RF Sampling Receiver
DDC
DDC
BPF
NCO
100 pF
Balun
Balun
RF Input
RF Input
N
INA
INB
ADC
100 pF
100 pF
DDC
DDC
BPF
NCO
N
ADC
100 pF
Device Clock
Up to 8 lanes
JESD204B
LMK04832
SYSREF
100 pF
FPGA
DDC
DDC
BPF
BPF
NCO
Balun
Balun
RF Input
RF Input
N
ADC
INC
IND
100 pF
100 pF
DDC
DDC
NCO
N
ADC
SPI
SPI
Registers
and
100 pF
Device
Control
GPIO1/2
VCM
CVCM
图8-1. Typical Configuration for Wideband RF Sampling
8.2.2 Design Requirements
8.2.2.1 Input Signal Path
Appropriate band limiting filters are be used to reject unwanted frequencies in the receive signal path.
A 1:2 (for 100 Ω effective termination impedance) or a 1:1 (for 50 Ω effective termination impedance) balun
transformer is needed to convert the single ended RF input to differential for input to the ADC. The balun outputs
can be AC coupled with 100 pF capacitors. The balun must have good amplitude (< 2 dB) and phase balance
(less than 2 deg) within the frequency range of interest. A back-to-back balun configuration often times gives
better SFDR performance. 表 8-1 lists a number of recommended baluns for different impedance ratios and
frequency ranges.
The S-parameters of the ADC input can be used to design the front end matching network.
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PART NUMBER
表8-1. Recommended Baluns
MANURACTURER
IMPEDANCE
RATIO
AMPLITUDE
BALANCE (dB)
PHASE
BALANCE (°)
FREQUENCY RANGE
BAL-0009SMG
TCM2-43X+
Marki Microwave
Minicircuits
1:2
1:2
1:2
1:1
0.6
0.5
0.7
0.5
5
7
0.5 MHz to 9 GHz
10 MHz to 4 GHz
10 MHz to 3 GHz
10 MHz to 3 GHz
TCM2-33WX+
TC1-1-13M+
Minicircuits
4
Minicircuits
2-3
8.2.2.2 Clocking
The ADC34RF52 clock inputs must be AC-coupled to the device to provide the rated performance. The clock
source must have low jitter (integrated phase noise) for the ADC to meet the stated SNR performance,
especially when operating at higher input frequencies. The clock signal needs to be filtered with a band pass
filter to remove some of the broad band clock noise.
The JESD204B data converter system (ADC and FPGA) requires additional SYSREF and device clocks. The
LMK04828 or LMK04832 devices are designed to generate these clocks. Depending on the ADC clock
frequency and jitter requirements, the device can also be used as a system clock synthesizer or as a device
clock and SYSREF distribution device when using multiple ADC34RF52 devices in a system.
8.2.3 Detailed Design Procedure
8.2.3.1 Sampling Clock
To maximize the SNR performance of the ADC a low jitter (< 50 fs) sampling clock is required. 图 8-2 shows the
estimated SNR performance vs input frequency vs external clock jitter. The internal ADC aperture jitter also has
some dependency to the clock amplitude (gets more sensitive with higher input frequency) as shown in 图8-3.
When using averaging and/or decimation, the SNR for a single ADC core is estimated before adding the SNR
improvement from internal averaging and/or decimation.
66
1x AVG, Dither OFF
1x AVG, Dither ON
2x AVG, Dither OFF
2x AVG, Dither ON
65
64
63
62
61
60
59
0
0.5
1
1.5
2
2.5
3
3.5
4
Clock Amplitude (Vpp)
图8-3. SNR vs Clock Amplitude
图8-2. SNR vs TJitter vs FIN (1x AVG)
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8.2.4 Application Curves
The following application curves demonstrate performance and results only of the ADC using a balun front end
and configured to 2x internal averaging. The input frequency is 900 MHz (FS = 1.5 GSPS) and input amplitudes
of -1/-4 and -20 dBFS are shown with dither enabled/disabled.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
AIN = -1 dBFS, 2x AVG, Dither = DIS
AIN = -4 dBFS, 2x AVG, Dither = EN
SNR = 66.8 dBFS, HD23 = 67 dBc, Non HD23 = 82 dBFS
SNR = 67.0 dBFS2, HD23 = 72 dBc, Non HD23 = 89 dBFS
图8-4. Single Tone FFT at FIN = 900 MHz
图8-5. Single Tone FFT at FIN = 900 MHz
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
250
500
750
0
250
500
750
Input Frequency (MHz)
Input Frequency (MHz)
AIN = -20 dBFS, 1x AVG, Dither = DIS
AIN = -20 dBFS, 1x AVG, Dither = EN
SNR = 65.2 dBFS, HD23 = 64 dBc, Non HD23 = 88 dBFS
SNR = 64.8 dBFS1, HD23 = 59 dBc, Non HD23 = 79 dBFS
图8-6. Single Tone FFT at FIN = 900 MHz
图8-7. Single Tone FFT at FIN = 900 MHz
2
Measured from 100 MHz to FS/2
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8.3 Initialization Set Up
After power-up, the internal registers must be initialized to their default values through a hardware reset by
applying a low pulse on the RESET pin, as shown in 图8-8.
1. Apply 1.2 V DVDD digital power supply
2. Apply remaining 1.2 V power supplies (AVDD12, CLKVDD), in no specific order
3. Apply 1.8 V AVDD18 power supply
4. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses.
5. Begin programming the internal registers using the SPI interface.
DVDD
AVDD12
CLKVDD
AVDD18
t1
RESET
t2
t3
SEN
图8-8. Initialization of serial registers after power up
表8-2. Power-up timing
MIN
TYP
MAX
UNIT
ms
t1
t2
Power-on delay: delay from power up to active high RESET pulse
Reset pulse width: active low RESET pulse width
1
100
ns
t3
Register write delay: delay from RESET disable to SEN active
45k
Clock cycles
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8.3.1 Initial Device Configuration After Power-Up
The following section outlines the sequence of register writes for the device configuration after initial power up.
表8-3. Summary of programming steps after initial power up
Step
Section
Description
1
RESET
Hardware and software RESET to reset all registers to known state
Configures the digital operating modes like averaging, test pattern output, input termination, internal
dither and decimation.
2
DEVICE CONFIG
3
4
JESD
SYSREF
JESD
Configures the JESD204B interface
Enables SYSREF input and resets internal circuits based on external SYSREF signal.
Clears and configures some of the JESD registers
Set trim settings for best analog performance
Configure the calibration settings
5
6
TRIM
7
CALIB CONFIG
SYSREF
RUN CALIB
JESD
8
Issue SYSREF for trim settings to go into effect
Run power up calibration
9
10
Synchronize the JESD interface with the receiver
The following section outlines the detailed register writes for the device configuration after initial power up. This
includes all the register writes (fields in gray) which are not documented in the register summary table. The
register examples are given for 2x internal averaging, DDC bypass mode (LMFS = 8422).
8.3.1.1 STEP 1: RESET
After the initial power up both hardware and software reset are required.
表8-4. Register programming sequence for software RESET
ADDRESS
0x00
DATA
0x01
0x00
0x00
0x20
0x80
0x00
0x01
0x00
0x40
0x80
0x00
DESCRIPTION
Software set and reset
0x00
0x01
0x09
0x09
These two resets are staggered to minimize strain on external power supply.
0x09
0x08
Internal memory reset (set and reset)
Select ANALOG page
0x08
0x05
0x47
Analog reset (set and reset)
0x47
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8.3.1.2 STEP 2: Device Configuration
In this step, the operating mode and digital features (DDC, test pattern) are configured.
表8-5. Register programming sequence for device configuration
ADDRESS
0x05
DATA
0x20
0x03
0x02
0x01
0x00
0x0B
0x07
0x10
0xE1
0xE1
0x40
0x00
0x00
0x00
0x01
0x04
0x40
0x10
0x00
DESCRIPTION
Select CALIBRATION page
Select 2x averaging (1x AVG: 0x01)
Select DIGITAL page
0x34
0x05
0x2C
0x2D
0x2E
0x23C
0x33
Select DDC Bypass mode
No decimation, step can be skipped
Select 2x averaging (1x: 0x09)
0x2F
Select 2x averaging (1x: 0x99, 2x: 0xE1)
Select 2x averaging (1x: 0x99, 2x: 0xE1)
Select ANALOG page
0x30
0x05
0x7B/8B
0xA8
0xCD
0x04
Select internal input termination (0x00 = 100 ohm)
DITHER AMP1: 3 = 0x80, 0 = 0x00
DITHER AMP2: -4 = 0x40, 0 = 0x00
0x20
0x91
0xAF
0xB1
Sets dither divider. 0x00 = /50
0xB2
0xAF
0x00
0x18
0x10
0x01
0x00
0x00
0x02
0x01
0x08
0x00
0x00
0x14
0x11
0x03
0xFF
0x3C
0x3E
0x00
0x01
0x00
0x00
0x00
0x01
0xAF
0x10 = dither ENABLED, 0x90 = dither DISABLED
0x04
0x20
0x04
0x05
0x363
0x05
Select DDCAB page, load non linearity correction (NLC) trims
0x224
0x223
0x21D
0x21E
0x205
0x204
0x21A
0x31C
0x325
0x325
0x325
0x21C
0x225
0x225
Nyquist zone 1: 0x00, other Nyquist zone 0x02
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表8-5. Register programming sequence for device configuration (continued)
ADDRESS
0x225
0x05
DATA
0x00
0x10
0x00
0x00
0x14
0x11
0x03
0xFF
0x3C
0x00
0x3E
0x00
0x01
0x00
0x00
0x01
0x00
0x08
0x02
0x30
0x30
0x30
DESCRIPTION
Select DDCCD page, load non linearity correction (NLC) trims
0x224
0x223
0x21D
0x21E
0x205
0x204
0x21A
0x21C
0x31C
0x325
0x325
0x325
0x225
0x225
0x225
0x05
Nyquist zone 1: 0x00, other Nyquist zone 0x02
0x20
OVR MUX EN
0x203
0x303
0x180
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8.3.1.3 STEP 3: JESD Interface Configuration (1)
In this step, the JESD204B digital interface and parameters are configured.
表8-6. Register programming sequence for JESD204B interface configuration
ADDRESS
0x05
0x81
0x80
0x7F
0x7E
0x7D
0x7C
0x7B
0x7A
0x79
0x78
0x05
0x23
0x29
0x20
0x21
0x22
0x24
0x25
0x53
0x5C
0x5D
0x6E
0xA0
0xA1
0xA2
0xED
0x9F
0x2A
0x23
0x23
DATA
0x02
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0x3B
0x28
0x51
0x40
0x04
0x03
0xFF
0x0F
0x01
0x03
0x01
0x00
0x80
0x01
0x0F
0x11
0x00
0x00
0x02
0x10
0x00
0x0C
0x02
0x00
DESCRIPTION
Select DIGITAL page
Select JESD page
Set register to 0x03
Set register to 0xFF
Select K (0x0F: K=15)
SYSREF mode
Select LMFS configuration (LMFS = 8-4-2-2)
Select DDC CLK DIV
Select JESD TX CLK DIV
Output scrambler EN/DIS (SCR EN)
F-1 in ILA (F=2)
K-1 in ILA (K=15)
Set JESD PLL INPUT1 = 0 Set JESD PLL INPUT2 = 0 Set JESD PLL INPUT3 = 1
Set JESD DDC BYP to 1
Select JESD PLL setting
JESD INIT toggle
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8.3.1.4 STEP 4: SYSREF Synchronization
After device and JESD204B interface configuration, a synchronization using external SYSREF is necessary.
表8-7. Device synchronization using external SYSREF
ADDRESS
0x05
DATA
0x02
0x02
0x03
DESCRIPTION
Select DIGITAL page
0x236
Enable internal SYSREF input and clear SYSREF pulse counter
Starts SYSREF counter
0x236
8.3.1.5 STEP 5: JESD Interface Configuration (2)
Some registers of the JESD204B interface must be set after the first SYSREF.
表8-8. Register programming sequence for JESD204B interface configuration
ADDRESS
0x05
DATA
0x04
0x00
0x00
DESCRIPTION
Select JESD page
0x29
0x84
JESD PLL factor
8.3.1.6 STEP 6: Analog Trim Settings
The following registers must be set for best analog performance. The register write order is all writes in first 2
columns before moving to the next set of address/data in middle columns and so on.
表8-9. Analog Trim Setting Registers
ADDR
0x05
DATA
0x40
0xF0
ADDR
0x3B
0xA8
0xA8
DATA
0x0C
0x18
0x00
COMMENT
ADDR
0x56
0x56
0x56
DATA
0x03
0x07
0x0F
COMMENT
0xE8
Only for 1x AVG
Only for 2x AVG,
FS<1.1 GSPS
0xE9
0x4B
0x01
0x1F
0xA8
0x08
Only for 2x AVG,
FS=1.1-1.5 GSPS
0x6E
0x08
0x5B
0xEA
0xEB
0x95
0xFC
0xE0
0xE1
0x4C
0x4E
0x4E
0xA1
0xF8
0x31
0xFD
0xAA
0x4D
0xB3
0x64
0x62
0x01
0x00
0x03
0x00
0x28
0x8E
0x03
0x40
0x01
0x00
0x01
0x00
0x20
0x1C
0x02
0x80
0x30
0x10
0x12
0xCD
0xCE
0x100
0x101
0x104
0x105
0x107
0x05
0x00
0x00
0x102
0x103
0xA7
0x02
0xD9
0x00
0x08
0x20
0x09
0xFE
0x03
0xD4
0x03
0xFE
0x03
0xBC
0x1A
0x01
0x63
0x40
0x00
0x00
See 表8-10for sample rate
dependent trim registers
0xA6
0x05
0xC9
0x102
0x103
0x104
0x105
0x106
0x107
0x108
0x109
0x101
0x159
0x05
0x10
0x20
0xE8
0xFF
0x08
0x80
0x03
0x02
0x02
0x20
0x04
0x01
0x0A
0x30
0x31
0x30
0x31
0x32
0x05
0x243
0x05
0x36
0x1F8
0x1FC
0x31
0x4D
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表8-9. Analog Trim Setting Registers (continued)
ADDR
0xFE
0xFC
0xFF
DATA
0x80
0x28
0x14
0x00
0x00
ADDR
0x1F0
0x1F1
0x05
DATA
0x20
0x0C
0x40
0x40
0x01
COMMENT
ADDR
0x62
0x56
0x56
0x56
0x56
0x6E
0xF8
DATA
0x10
0x0E
0x0C
0x08
0x00
0x00
0x06
COMMENT
0x106
0x107
0x39
0x56
表8-10. Sample rate dependent trim registers
FS (GSPS)
0x100
0x101
0x104
0x105
0.6-0.7
0x48
0xC8
0x48
0xC8
0x48
0x00
0x01
0x01
0x00
0x00
0x01
0x81
0x81
0x81
0x81
0x01
0x00
0x00
0x00
0x00
0.7-0.9
0.9-1.1
1.1-1.3
1.3-1.5
8.3.1.7 STEP 7: Calibration Configuration
The following registers configure the internal foreground calibration. The register write order is all writes in first 2
columns before moving to the next set of address/data in middle columns and so on.
表8-11. Calibration Register Settings
ADDRESS
0x05
DATA
0x40
0xC0
0xFF
0x20
0x03
0xC2
0x13
0x00
0x1C
0x00
0x1C
0x08
0xA8
0x02
0x06
0x04
0x00
0xA0
0x28
0x0C
0x2A
0x2E
0x2C
0x28
ADDRESS
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0x36
0x46
0x47
DATA
0x13
0x08
0x04
0x05
0x04
0x13
0x0A
0x04
0x05
0x04
0x13
0x0C
0x04
0x05
0x04
0x13
0x0E
0x04
0x05
0x04
0x03
0x04
0x03
0xC0
ADDRESS
0x47
0x46
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
DATA
0xC7
0x13
0x13
0x00
0x04
0x05
0x04
0x13
0x02
0x04
0x05
0x04
0x13
0x04
0x04
0x05
0x04
0x13
0x06
0x04
0x05
0x04
0x13
0x08
0x68
0x69
0x05
0x46
0x47
0x46
0x1AE
0x1E6
0x1AE
0x1E6
0x1E9
0x1E9
0x1E8
0x1E8
0x1E8
0x1E8
0x1E9
0x1F0
0x1F1
0x1F0
0x1F0
0x1F0
0x1F0
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表8-11. Calibration Register Settings (continued)
ADDRESS
0x1F0
0x1F0
0x1F0
0x1F1
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1AE
0x1E6
0x1AE
0x1E6
0x47
DATA
0x08
0x18
0x38
0x0C
0x3A
0x3E
0x3C
0x38
0x18
0x10
0x00
0x1C
0x00
0x1C
0xC0
0x03
0xC2
0x13
0x13
0x00
0x04
0x05
0x04
0x13
0x02
0x04
0x05
0x04
0x13
0x04
0x04
0x05
0x04
0x13
0x06
0x04
0x05
0x04
ADDRESS
DATA
0x13
0x03
0xC7
0x13
0x00
0x1C
0x00
0x1C
0xA8
0x02
0x06
0x04
0x00
0xA0
0x18
0x08
0x28
0x0C
0x2A
0x2E
0x2C
0x28
0x08
0x18
0x38
0x0C
0x3A
0x3E
0x3C
0x38
0x18
0x10
0x00
0x1C
0x00
0x1C
0xC0
0x03
ADDRESS
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0x36
0x46
0x47
0x46
0x05
0x68
0x69
0x69
0x69
0x69
0x68
0x69
0x69
0x69
0x69
0x93
0x94
0x94
DATA
0x04
0x05
0x04
0x13
0x0A
0x04
0x05
0x04
0x13
0x0C
0x04
0x05
0x04
0x13
0x0E
0x04
0x05
0x04
0x03
0x04
0x03
0xC0
0x13
0x40
0x40
0xFD
0xF5
0xD5
0x55
0x00
0x54
0x50
0x40
0x00
0x0E
0x70
0x77
0x46
0x46
0x47
0x46
0x1AE
0x1E6
0x1AE
0x1E6
0x1E9
0x1E8
0x1E8
0x1E8
0x1E8
0x1E9
0x1F0
0x1F0
0x1F0
0x1F1
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1F1
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1F0
0x1AE
0x1E6
0x1AE
0x1E6
0x47
0x46
0x47
0x46
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0xFC
0xFD
0x36
0x36
0x36
0x46
8.3.1.8 STEP 8: SYSREF Synchronization
After setting the analog trim registers, a synchronization using external SYSREF is necessary.
表8-12. Device synchronization using external SYSREF
ADDRESS
0x05
DATA
0x02
0x02
DESCRIPTION
Select DIGITAL page
0x236
Enable internal SYSREF input and clear SYSREF pulse counter
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表8-12. Device synchronization using external SYSREF (continued)
ADDRESS
0x236
DATA
DESCRIPTION
0x03
Starts SYSREF counter
8.3.1.9 STEP 9: Run Power up Calibration
The following registers start the power up foreground calibration. The register write order is all writes in first 2
columns before moving to the next set of address/data in middle columns and so on.
表8-13. Calibration Register Settings
ADDRESS
0x05
DATA
0x20
0x01
0x02
0x00
0x22
0x00
0x03
0x00
0x1C
0x03
0x03
0x26
0x02
0x88
0xC8
0x00
0x4C
0x3F
0x46
0x2C
0x05
0x7C
0x7C
0x6F
0x7C
0x3F
0x7C
0x3F
0x7C
0x4F
0x7C
0x1C
0x5F
0x1C
0xAF
0x1F
0x7F
0xFF
ADDRESS
DATA
0x20
0x00
0x00
0x01
0x1F
0x20
0x01
0x00
0x00
0x20
0x7C
0x3C
0x01
0x00
0x06
0x01
0x10
0x42
0xA6
0xD6
0xBB
0xDB
0xF4
0x64
0x0E
0xFE
0x0D
0xDD
0x0D
0xDD
0x03
0x00
0x0A
0x02
0x4A
0x05
0x28
0x5E
ADDRESS
0x58
DATA
0x30
0x20
0x00
x020
0x00
0x00
0x10
0x00
0x1E
0x02
0x8A
0x0A
0x93
0xE7
0x20
0x58
0x174
0x178
0x17C
0x3C
0x05
0x58
0x04
0x89
0x20
0x95
0x93
0x96
0xFC
0x04
0x97
0xFD
0x20
0x9C
0x57
0x154
0x155
0xFC
0x04
0x05
0x46
0xC0
0xBC
0xC9
0xC9
0xC9
0x38
0x45
0xEE
0x45
0xEF
Delay 3 seconds
0x18C
0xAE
0x89
0x95
0x96
0x97
0x9C
0x57
0x57
0x57
0x57
0x58
0x58
0x58
0x58
0x58
0x58
0x45
0x45
0x00
0x00
0x00
0x00
0x00
0x1A
0x3A
0x7A
0xFA
0x01
0x03
0x07
0x0F
0x1F
0x3F
0x8A
0x0A
0xAF
0xB0
0x110
0x111
0x112
0x112
0x113
0x113
0x114
0x114
0x115
0x115
0x116
0x116
0x117
0x117
0x46
0xB1
0x4F
0x50
0x51
0x154
0x158
0x159
0x15C
0x15D
0x160
0x161
0x164
0x165
0x16C
0x1B0
0x1B1
0x1D8
0x1D9
0xB2
Delay 3 seconds
0x3D
0x45
0x47
0x46
0x47
0x05
0x20
0x9D
0x9E
0xC0
0x03
0xC0
0x80
0x1F
0x05
0x08
0x46
0x64
0x65
0xB5
0x68
0x165
0x69
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表8-13. Calibration Register Settings (continued)
ADDRESS
0x38
DATA
0x01
0x30
0x7F
0x00
0x63
0x00
0x02
0x80
0x1F
ADDRESS
0x6A
0x6B
0x6C
0x57
DATA
ADDRESS
DATA
0x40
0x00
0x00
0x01
0x1F
0x05
0x08
0x40
03D
0x8B
0xA4
0x8F
0x44
0xDA
0x9A
0x1A
0x3E
0x3C
0x38
0x20
0xC5
0xA8
0x05
0x04
0xA2
0x57
0x20
0xA3
0x57
0x9D
0x9E
0xAD
0x05
0x58
0x58
0x8B
0x20
0x58
8.3.1.10 Step 10: JESD Interface Synchronization
The JESD interface can be synchronized using SPI writes or the GPIO1 pin (needs additional config).
表8-14. JESD interface synchronization using SPI writes
ADDRESS
0x05
DATA
0x04
0x41
0x61
0x41
DESCRIPTION
Select JESD page
0x21
Configure ADC to control SYNC using SPI writes
0x21
Configure JESD interface to send K28.5 characters for receiver synchronization
Configure JESD interface to send normal ADC data
0x21
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8.4 Power Supply Recommendations
The ADC34RF52 requires four different power-supplies. The AVDD18, AVDD12 and CLKVDD rail provides
power for the internal analog and clocking circuits of the ADC while the DVDD rail powers the digital logic
(including averaging and decimation filter) and the JESD204B digital interface.
Power sequencing is required as shown in Initialization Set Up. The AVDD18, AVDD12 and especially the
CLKVDD power supply must be low noise to achieve data sheet performance. For applications operating near
DC, the 1/f noise contribution of the power supply needs to be considered as well.
Power supply decoupling capacitors (0.1 µF) as close to the pins as possible on the top layer are recommended.
80
AVDD12
AVDD18
CLKVDD
70
60
50
40
30
20
10
0
0.01
0.1
1
10
100
500
Frequency of Signal (MHz)
图8-9. Power supply rejection ratio (PSRR) vs frequency
The recommended power supply architecture for a low noise design is to first use a high-efficiency step down
switching regular, followed by a second stage of regulation using a low noise LDO for each power rail as shown
in 图8-10. This provides additional switching noise reduction and improved voltage accuracy.
TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements.
Recommended switching regulators for the first stage include the LMS3635, and similar devices. Recommended
low dropout (LDO) linear regulators include the TPS7A8400, and similar devices.
FB
FB
2.3V
1.8V
DC/DC
Regulator
5V-12V
LDO
AVDD18
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
FB
1.7V
1.2V
DC/DC
Regulator
LDO
AVDD12
10uF 10uF 0.1uF
47uF
47uF
GND
GND
GND
FB
1.2V
LDO
CLKVDD
10uF 10uF 0.1uF
47uF
GND
GND
FB
1.2V
LDO
DVDD
10uF 10uF 0.1uF
47uF
GND
FB = Ferrite bead filter
GND
图8-10. Power supply design example
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AVDD12 or CLKVDD should not be shared with the DVDD to prevent digital switching noise from coupling into
the analog domain.
8.5 Layout
8.5.1 Layout Guidelines
There are several critical signals which require specific care during board design:
1. Analog input and clock signals
• Traces should be as short as possible and vias should be avoided where possible to minimize impedance
discontinuities.
• Traces should be routed using loosely coupled 100-Ωdifferential traces.
• Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2
degradation.
2. Digital JESD204B output interface
• Traces should be routed using tightly coupled 100-Ωdifferential traces.
3. Power and ground connections
• Provide low resistance connection paths to all power and ground pins.
• Use power and ground planes instead of traces.
• Avoid narrow, isolated paths which increase the connection resistance.
• Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power
plane.
8.5.2 Layout Example
The following screen shot shows the top layer of the ADC34RF52 EVM.
• The input signal traces are routed as differential signals on the top layer avoiding vias. Care is taken to
maintain symmetry between positive and negative input with matched trace length to minimize phase
imbalance.
图8-11 shows the layout example for 1x and 2x averaging configuration
• JESD204B output interface lanes are routed differential and length matched
• Bypass caps are close to the power pins on the top layer avoiding vias.
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Analog Inputs on top layer –
symmetric differenꢀal
rouꢀng
JESD204B Lanes
Tightly coupled traces
图8-11. Layout example: top layer of the EVM
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9 Device and Documentation Support
9.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
TI WEBENCH® is a registered trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADC34RF52IRTD
ADC34RF52IRTDT
ACTIVE
ACTIVE
VQFN
VQFN
RTD
RTD
64
64
168
250
RoHS & Green
RoHS & Green
Call TI | NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
AZ34RF52
AZ34RF52
Samples
Samples
Call TI | NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE OUTLINE
RTD0064N
VQFN - 0.9 mm max height
SCALE 1.600
PLASTIC QUAD FLATPACK - NO LEAD
9.1
8.9
A
B
PIN 1 ID
9.1
8.9
(
8.71)
0.975
0.875
C
SEATING PLANE
0.08 C
(0.2)
4X (45 X0.42)
5.566 0.1
32
17
16
33
SYMM
65
4X
6.866 0.1
7.5
48
1
0.3
64X
0.2
0.1
0.05
64X 0.5
49
64
C B A
C
SYMM
0.5
0.3
64X
PIN 1 ID
4226371/A 11/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTD0064N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(5.566)
(1.17) TYP
64X (0.6)
(1.33) TYP
64
49
64X (0.25)
1
48
60X (0.5)
(1.26)
TYP
SYMM
6.866
65
(8.8)
(0.63)
(R0.05) TYP
16
33
(R0.1) TYP
VIA
17
32
SYMM
(8.8)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226371/A 11/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RTD0064N
VQFN - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.665)
(1.33) TYP
49
64X (0.6)
64
64X (0.25)
1
48
(1.26) TYP
60X (0.5)
(1.26) TYP
(8.8)
SYMM
65
20X (1.06)
33
16
METAL
TYP
32
17
SYMM
20X (1.13)
(8.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 65:
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:10X
4226371/A 11/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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