ADC3663IRSBT_技术文档

ADC3663

www.ti.com

SBAS991 – FEBRUARY 2021

ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, low-noise, low power, dual-channel ADC

1 Features

3 Description

•

16-Bit 10-MSPS, 25-MSPS, or 65-MSPS ADCs

Noise floor: –158 dBFS/Hz

Low power consumption:

50 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)

Latency: 1 cycle (1-wire SLVDS)

Specified 16-bit, no missing codes

INL: ± 2 LSB; DNL: ± 0.2 LSB

The ADC3661, ADC3662, and ADC3663 (ADC366x)

family of devices are low-noise, ultra-low power, 16-

bit, 10-MSPS to 65-MSPS, high-speed, dual-channel,

analog-to-digital converters (ADCs). Designed for

lowest noise performance, these devices deliver a

noise spectral density of –158 dBFS/Hz combined

with great linearity and dynamic range. The ADC366x

offers very good dc precision together with IF samp-

ling support, which makes these devices an excellent

choice for a wide range of applications. High-speed

control loops benefit from the short latency as low as

only 1 clock cycle. The ADC consumes only 94

mW/ch at 65 MSPS and power consumption scales

very well with lower sampling rates.

•

Reference: external or internal

Input bandwidth: 900 MHz (3 dB)

Industrial temperature range: –40°C to +105°C

On-chip digital filter (optional)

– Decimation by 2, 4, 8, 16, 32

– 32-bit NCO

•

Serial LVDS digital interface (2-, 1- and 1/2-wire)

Small footprint: 40-WQFN (5 mm × 5 mm) package

Spectral performance (f_IN= 10 MHz):

– SNR: 81.9 dBFS

– SFDR: 92-dBc HD2, HD3

– SFDR: 99-dBFS worst spur

The ADC366x uses a serial LVDS (SLVDS) interface

to output the data. The devices support a two-lane, a

one-lane and a half-lane option. These devices are a

pin-to-pin compatible family with 16-bit and 18-bit

resolution and different speed grades. It comes in a

40-pint QFN package (5x5 mm) and supports the

extended industrial temperature range of –40°C to

+105⁰C.

2 Applications

Device Information

•

High-Speed Data Acquisition

Industrial Monitoring

Software Defined Radio

Power Quality Analyzer

Source Measurement Unit (SMU)

Communications Infrastructure

Spectrum Analyzer

Control Loops

Instrumentation

Imaging

Spectroscopy

Radar

PART NUMBER ⁽¹⁾

PACKAGE

BODY SIZE (NOM)

ADC366x

WQFN (40)

5.00 × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Table 3-1. Device Comparison

PART NUMBER

ADC3661⁽¹⁾

ADC3662⁽¹⁾

ADC3663

RESOLUTION

SAMPLING RATE

16 BIT

10 MSPS

16 BIT

14 BIT

25 MSPS

65 MSPS

ADC3664⁽¹⁾

125 MSPS

Sonar

(1) Product preview

REFBUF

VREF

1.2V REF

Digital Downconverter

NCO

Crosspoint

Switch

ADC

16-bit

N

AIN

DCLKIN

DCLK

0.95V

VCM

FCLK

Dig I/F

SLVDS

NCO

DA0/1

DB0/1

ADC

16-bit

N

BIN

CLK

Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

Submit Document Feedback

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

Product Folder Links: ADC3663

1

DATA.

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics - Power Consumption ........6

6.6 Electrical Characteristics - DC Specifications ............7

6.7 Electrical Characteristics - AC Specifications ............ 9

6.8 Timing Requirements ...............................................12

6.9 Typical Characteristics - ADC3663........................... 14

7 Parameter Measurement Information..........................19

8 Detailed Description......................................................21

8.1 Overview...................................................................21

8.2 Functional Block Diagram.........................................21

8.3 Feature Description...................................................22

8.4 Device Functional Modes..........................................40

8.5 Programming............................................................ 42

8.6 Register Map.............................................................44

9 Application Information Disclaimer.............................59

9.1 Typical Application.................................................... 59

9.2 Initialization Set Up................................................... 62

10 Power Supply Recommendations..............................63

11 Layout...........................................................................65

11.1 Layout Guidelines................................................... 65

11.2 Layout Example...................................................... 65

12 Device and Documentation Support..........................66

12.1 Receiving Notification of Documentation Updates..66

12.2 Support Resources................................................. 66

12.3 Trademarks.............................................................66

12.4 Electrostatic Discharge Caution..............................66

12.5 Glossary..................................................................66

13 Mechanical, Packaging, and Orderable

Information.................................................................... 66

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

DATE

REVISION

NOTES

February 2021

*

Initial release.

2

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

5 Pin Configuration and Functions

40

39

38

37

36

35

34

33

32

31

1

2

30

29

28

27

26

25

24

23

22

21

PDN/SYNC

VREF

IOVDD

FCLKM

FCLKP

3

REFGND

REFBUF

VDDA

CLKP

4

NC

5

IOGND

DCLKINP

DCLKINM

DCLKP

DCLKM

IOVDD

6

7

CLKM

8

VCM

9

RESET

SDIO

GND PAD (backside)

10

11

12

13

14

15

16

17

18

19

20

Figure 5-1. RSB Package, 40-Pin WQFN, Top View

Table 5-1. Pin Descriptions

I/O

Description

Name

No.

INPUT/REFERENCE

AINP

AINM

BINP

BINM

VCM

VREF

12

13

39

38

8

I

Positive analog input, channel A

Negative analog input, channel A

Positive analog input, channel B

Negative analog input, channel B

I

O

I

Common-mode voltage output for the analog inputs, 0.95V

External voltage reference input, 1.6V

2

1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ

pull-up resistor to AVDD. This pin is also used to configure default operating conditions.

REFBUF

4

3

I

REFGND

CLOCK

Reference ground input

CLKP

6

7

I

Positive differential sampling clock input for the ADC

Negative differential sampling clock input for the ADC

CLKM

CONFIGURATION

Power down/Synchronization input. This pin can be configured via the SPI interface. Active

high. This pin has an internal 21 kΩ pull-down resistor.

PDN/SYNC

RESET

1

9

I

Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.

Submit Document Feedback

3

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Table 5-1. Pin Descriptions (continued)

I/O

Description

Name

SEN

SCLK

SDIO

NC

No.

16

35

10

27

I

Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.

Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.

Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.

Do not connect

I/O

-

DIGITAL INTERFACE

DA0P

20

O

I

Positive differential serial LVDS output for lane 0, channel A

Negative differential serial LVDS output for lane 0, channel A

Positive differential serial LVDS output for lane 1, channel A

Negative differential serial LVDS output for lane 1, channel A

Positive differential serial LVDS output for lane 0, channel B

Negative differential serial LVDS output for lane 0, channel B

Positive differential serial LVDS output for lane 1, channel B

Negative differential serial LVDS output for lane 1, channel B

Positive differential serial LVDS bit clock output.

DA0M

19

18

17

31

32

33

34

23

22

28

29

25

24

DA1P

DA1M

DB0P

DB0M

DB1P

DB1M

DCLKP

DCLKM

FCLKP

FCLKM

DCLKINP

DCLKINM

POWER SUPPLY

AVDD

Negative differential serial LVDS bit clock output.

Positive differential serial LVDS frame clock output.

Negative differential serial LVDS frame clock output.

Positive differential serial LVDS bit clock input. Internal 100 Ω differential termination.

Negative differential serial LVDS bit clock input. Internal 100 Ω differential termination.

I

5,15,36

I

Analog 1.8 V power supply

Ground, 0 V

11,14,37,40,

PowerPad

GND

IOVDD

IOGND

21,30

26

I

1.8 V power supply for digital interface

Ground, 0 V for digital interface

4

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

–0.3

MAX

2.1

UNIT

V

Supply voltage range, AVDD, IOVDD

Supply voltage range, GND, IOGND, REFGND

0.3

V

AINP/M, BINP/M, CLKP/M, DCLKINP/M, VREF, REFBUF

PDN/SYNC, RESET, SCLK, SEN, SDIO

2.1

Voltage applied to

input pins

V

2.1

Junction temperature, T_J

Storage temperature, T_stg

105

150

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

2500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101,

all pins⁽²⁾

1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.75

–40

NOM

1.8

MAX UNIT

AVDD⁽¹⁾

1.85

V

Supply

voltage range

IOVDD⁽¹⁾

1.8

T_A

T_J

Operating free-air temperature

Operating junction temperature

105

°C

105⁽²⁾

(1) Measured to GND.

(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

ADC366x

RSB (QFN)

40 Pins

30.7

THERMAL METRIC⁽¹⁾

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

16.4

10.5

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

Ψ_JB

10.5

R_ΘJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

Submit Document Feedback

5

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.5 Electrical Characteristics - Power Consumption

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3661: 10 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

I/O supply current

Power dissipation

External reference

27

28

99

21

35

25

30

27

mA

SLVDS 1-wire

External reference, SLVDS 1-wire

1-wire, 1/2-swing

mW

2-wire

I_IOVDD

I/O supply current

1/2-wire

mA

4x real decimation, 1-wire

4x real decimation, 1/2-wire

ADC3662: 25 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

External reference

1-wire

31

30

mA

I/O supply current

Power dissipation

External reference, 1-wire

1-wire, 1/2-swing

2-wire

110

23

mW

37

I_IOVDD

I/O supply current

1/2-wire

27

mA

4x real decimation, 1-wire

4x real decimation, 1/2-wire

33

29

ADC3663: 65 MSPS

I_AVDD

I_IOVDD

P_DIS

Analog supply current

External reference

63

41

187

30

39

36

37

33

44

40

36

82

57

mA

I/O supply current

Power dissipation

2-wire

External reference, 2-wire

2-wire, 1/2-swing

250

mW

4x real decimation, 1-wire

4x real decimation, 1/2-wire

16x real decimation, 1-wire

16x real decimation, 1/2-wire

4x complex decimation, 1-wire

16x complex decimation, 1-wire

16x complex decimation, 1/2-wire

I_IOVDD

I/O supply current

mA

MISCELLANOUS

Internal reference, additional analog

1

0.3

0.7

5

supply current

External 1.2 V reference (REFBUF),

additional analog supply current

I_AVDD

mA

Single ended clock input, reduces

analog supply current by

Enabled via SPI

Default mask settings, internal

reference

Power consumption in global power

down mode

P_DIS

mW

Default mask settings, external

reference

9

6

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC ACCURACY

No missing codes

PSRR

16

bits

dB

F_IN= 1 MHz

50

ADC3661 - 10 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 4.9 MHz

± 0.2

± 2

± 0.3

± 2.5

TBD

0.4

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

Transition Noise

32

LSB

Offset drift over temperature

Gain error

TBD

0.83

TBD

LSB/ºC

%FSR

ppm/ºC

%FSR

dB

External 1.6V Reference

Internal Reference

TBD

10

Gain drift over temperature

Gain error

TBD

Gain drift over temperature

Internal Reference

LSB

ADC3662 - 25 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 5 MHz

± 0.2

± 2

± 0.3

± 2.5

TBD

0.4

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

Transition Noise

32

LSB

Offset drift over temperature

Gain error

TBD

0.83

TBD

LSB/ºC

%FSR

ppm/ºC

%FSR

dB

External 1.6V Reference

Internal Reference

TBD

10

Gain drift over temperature

Gain error

TBD

Gain drift over temperature

Internal Reference

LSB

ADC3663 - 65 MSPS: DC ACCURACY

DNL

Differential nonlinearity

Integral nonlinearity

Offset error

F_IN= 5 MHz

± 0.7

± 3

± 0.85

± 5

LSB

INL

V_{OS_ERR}

V_{OS_DRIFT}

GAIN_ERR

GAIN_DRIFT

GAIN_ERR

GAIN_DRIFT

Transition Noise

± 33

0.05

± 2.3

68

± 135

LSB

Offset drift over temperature

Gain error

LSB/ºC

%FSR

ppm/ºC

%FSR

ppm/ºC

LSB

External 1.6V Reference

Internal Reference

Gain drift over temperature

Gain error

± 3.5

242

1.3

Gain drift over temperature

Internal Reference

Submit Document Feedback

7

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.6 Electrical Characteristics - DC Specifications (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC ANALOG INPUT (AINP/M, BINP/M)

FS

Input full scale

Differential

3.2

0.95

8

Vpp

V

V_CM

R_IN

Input common model voltage

Differential input resistance

Differential input Capacitance

Output common mode voltage

Analog Input Bandwidth (-3dB)

0.9

1.0

F_IN= 100 kHz

kΩ

pF

C_IN

7

V_OCM

BW

0.95

900

V

MHz

Internal Voltage Reference

V_REF

Internal reference voltage

1.6

8

V

Ω

V

V_REFOutput Impedance

External reference voltage

Reference Input Buffer (REFBUF)

V_REF

1.2

1.6

0.3

5.3

V

Input Current

mA

kΩ

Input impedance

External voltage reference (VREF)

Input clock

Input clock frequency

frequency

0.5

65

MHz

V_ID

Differential input voltage

1

3.6

Vpp

V

V_CM

Input common mode voltage

0.9

Clock Input (CLKP/M)

R_IN

5

1.5

50

kΩ

pF

%

C_IN

Single ended input capacitance

Clock duty cycle

V_IH

40

60

High level input voltage

1.4

V

Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)

V_IL

I_IH

I_IL

Low level input voltage

High level input current

Low level input current

Input capacitance

0.4

V

90

-90

1.5

150

uA

pF

-150

C_I

IOVDD

– 0.1

V_OH

High level output voltage

IOVDD

V

Digital Output (SDOUT)

V_OL

Low level output voltage

I_LOAD= 400 uA

0.1

V

Output data rate

per differential SLVDS output pair

1000

Mbps

SLVDS Interface

V_ID

Differential input voltage

DCLKIN

200

1

350

1.2

650

1.3

mVpp

V

V_CM

V_OD

V_CM

Input common mode voltage

Differential output voltage

Output common mode voltage

500

700

1.0

850

mVpp

V

8

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.7 Electrical Characteristics - AC Specifications

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,

external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

dBFS/Hz

dBFS

ADC3661: 10 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

No input signal

-150.0

82.0

81.9

TBD

13.3

TBD

90

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

f_IN= 1.1 MHz

f_IN= 4.9 MHz

f_IN= 9.9 MHz

TBD

SINAD

ENOB

Signal to noise and distortion ratio

Effective number of bits

dBFS

bit

Total Harmonic Distortion (First five

harmonics)

THD

dBc

Spur free dynamic range including

second and third harmonic distortion

SFDR

90

dBc

90

100

95

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

dBFS

f₁= 1 MHz, f₂= 2 MHz, A_IN= -7 dBFS/

tone

TBD

IMD3

Two tone inter-modulation distortion

dBc

f₁= 10 MHz, f₂= 12 MHz, A_IN= -7

dBFS/tone

Submit Document Feedback

9

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.7 Electrical Characteristics - AC Specifications (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,

external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3662: 25 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

No input signal

-154.0

82.0

81.9

81.6

80.5

TBD

13.3

13.1

TBD

90

dBFS/Hz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

TBD

dBFS

bit

TBD

SINAD

ENOB

THD

Signal to noise and distortion ratio

Effective number of bits

Total Harmonic Distortion (First five

harmonics)

dBc

90

Spur free dynamic range including

second and third harmonic distortion

SFDR

90

dBc

88

83

100

95

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

dBFS

dBc

90

f₁= 1 MHz, f₂= 2 MHz, A_IN= -7 dBFS/

tone

TBD

IMD3

Two tone inter-modulation distortion

f₁= 10 MHz, f₂= 12 MHz, A_IN= -7

dBFS/tone

10

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.7 Electrical Characteristics - AC Specifications (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 10-65 MSPS, external reference, 50% clock duty cycle, AVDD = IOVDD = 1.8 V,

external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC3663: 65 MSPS

NSD

SNR

Noise Spectral Density

Signal to noise ratio

No input signal

-158.0

82.0

81.9

81.6

80.5

76.9

80.0

78.5

75.5

13.0

12.7

12.3

81

dBFS/Hz

f_IN= 1.1 MHz

f_IN= 5 MHz

80

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

dBFS

bit

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

SINAD

ENOB

THD

Signal to noise and distortion ratio

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

Effective number of bits

81

82

91

88

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

89

Total Harmonic Distortion (First five

harmonics)

dBc

83

82

80

82

89

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

f_IN= 1.1 MHz

f_IN= 5 MHz

92

Spur free dynamic range including

second and third harmonic distortion

SFDR

dBc

84

82

100

99

f_IN= 10 MHz

f_IN= 20 MHz

f_IN= 40 MHz

f_IN= 70 MHz

99

Spur free dynamic range (excluding

HD2 and HD3)

Non HD2,3

dBFS

dBc

96

91

86

f₁= 1 MHz, f₂= 2 MHz, A_IN= -7 dBFS/

tone

100

104

IMD3

Two tone inter-modulation distortion

f₁= 10 MHz, f₂= 12 MHz, A_IN= -7

dBFS/tone

Submit Document Feedback

11

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

ADC Timing Specifications

t_ADAperture Delay

t_A

TEST CONDITIONS

MIN NOM MAX

UNIT

0.85

180

ns

fs

Aperture Jitter

square wave clock with fast edges

t_J

Jitter on DCLKIN

± 50

-T_S/4

-T_S/2

ps

F_S= 65 Msps

F_S= 25 Msps

F_S= 10 Msps

Sampling

Clock

Period

Signal acquisition period, referenced to

sampling clock falling edge

t_ACQ

+T_S×

5/8

F_S= 65 Msps

F_S= 25 Msps

F_S= 10 Msps

Sampling

Clock

Period

Signal conversion period, referenced to

sampling clock falling edge

+T_S×

3/8

t_CONV

+T_S×

1/5

Bandgap reference enabled, single ended

clock

17.6

12.9

2.2

us

ms

us

Bandgap reference enabled, differential clock

Time to valid data after coming out of power

down. Internal reference.

Bandgap reference disabled, single ended

clock

Bandgap reference disabled, differential clock

2.2

Wake up

time

Bandgap reference enabled, single ended

clock

15.9

12.9

1.7

Bandgap reference enabled, differential clock

Time to valid data after coming out of power

down. External 1.6V reference.

Bandgap reference disabled, single ended

clock

ms

ps

Bandgap reference disabled, differential clock

1.7

t_S,SYNC

t_H,SYNC

Setup time for SYNC input signal

Hold time for SYNC input signal

500

600

2

Referenced to sampling clock rising edge

2-wire SLVDS

1-wire SLVDS

1/2-wire SLVDS

ADC

Latency

Clock

cycles

Signal input to data output

1

Real decimation by 2

21

22

23

Output

clock

cycles

Add.

Latency

Complex decimation by 2

Real or complex decimation by 4, 8, 16, 32

Interface Timing: Serial LVDS Interface

Delay between sampling clock falling edge to

DCLKIN falling edge < 2.5ns.

T_DCLK= DCLK period

t_CDCLK= Sampling clock falling edge to

DCLKIN falling edge

2 +

3 +

4 +

T_DCLKT_DCLKT_DCLK

+

t_CDCLKt_CDCLKt_CDCLK

Propagation delay: sampling clock falling

edge to DCLK rising edge

t_PD

ns

Delay between sampling clock falling edge to

DCLKIN falling edge >= 2.5ns.

T_DCLK= DCLK period

t_CDCLK= Sampling clock falling edge to

DCLKIN falling edge

2 +

3 +

4 +

t_CDCLKt_CDCLKt_CDCLK

12

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.8 Timing Requirements (continued)

Typical values are over the operating free-air temperature range, at T_A= 25°C, full temperature range is T_MIN= –40°C to

T_MAX= 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN NOM MAX

UNIT

Fout = 10 MSPS, DA/B0,1 = 80 MBPS

Fout = 25 MSPS, DA/B0,1 = 200 MBPS

Fout = 65 MSPS, DA/B0,1 = 520 MBPS

Fout = 10 MSPS, DA/B0 = 160 MBPS

Fout = 25 MSPS, DA/B0 = 400 MBPS

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

Fout = 5 MSPS, DA0 = 160 MBPS

Fout = 10 MSPS, DA0 = 320 MBPS

Fout = 25 MSPS, DA0 = 800 MBPS

Fout = 10 MSPS, DA/B0,1 = 80 MBPS

Fout = 25 MSPS, DA/B0,1 = 200 MBPS

Fout = 65 MSPS, DA/B0,1 = 520 MBPS

Fout = 10 MSPS, DA/B0 = 160 MBPS

Fout = 25 MSPS, DA/B0 = 400 MBPS

Fout = 62.5 MSPS, DA/B0= 1000 MBPS

Fout = 5 MSPS, DA0 = 160 MBPS

Fout = 10 MSPS, DA0 = 320 MBPS

Fout = 25 MSPS, DA0 = 800 MBPS

0.0

-0.6

0.0

11.9

4.5

1.4

5.7

2.0

0.5

5.7

2.7

0.8

0.1

12.1

4.6

1.5

5.8

2.1

0.6

5.8

2.8

0.9

DCLK rising edge to output data delay,

2-wire SLVDS

DCLK rising edge to output data delay,

1-wire SLVDS

t_CD

ns

DCLK rising edge to output data delay,

1/2-wire SLVDS

Data valid, 2-wire SLVDS

Data valid, 1-wire SLVDS

Data valid, 1/2-wire SLVDS

t_DV

ns

SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input

f_CLK(SCLK)Serial clock frequency

20

MHz

ns

t_SU(SEN)

t_H(SEN)

t_SU(SDIO)

t_H(SDIO)

SEN to rising edge of SCLK

SEN from rising edge of SCLK

SDIO to rising edge of SCLK

SDIO from rising edge of SCLK

10

9

ns

17

9

ns

SERIAL PROGRAMMING INTERFACE (SDIO) - Output

t_(OZD)

t_(ODZ)

t_(OD)

SDIO tri-state to driven

3.9

3.4

3.9

10.8

14

ns

SDIO data to tri-state

SDIO valid from falling edge of SCLK

10.8

Submit Document Feedback

13

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

6.9 Typical Characteristics - ADC3663

Typical values at T_A= 25 °C, ADC sampling rate = 65 MSPS, A_IN= –1 dBFS differential input, AVDD = IOVDD =

1.8 V, external 1.6 V voltage reference, unless otherwise noted.

SNR = 82.0 dBFS, SFDR = 81 dBc, Non HD23 = 100 dBFS

SNR = 82.0 dBFS, SFDR = 90 dBc, Non HD23 = 100 dBFS

Figure 6-1. Single Tone FFT at F_IN= 1 MHz

Figure 6-2. Single Tone FFT at F_IN= 5 MHz

A_IN= -20 dBFS, SNR = 82.0 dBFS, SFDR = 83 dBc, Non HD23

= 102 dBFS

SNR = 82.0 dBFS, SFDR = 87 dBc, Non HD23 = 97 dBFS

Figure 6-4. Single Tone FFT at F_IN= 10 MHz

Figure 6-3. Single Tone FFT at F_IN= 5 MHz

14

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

SNR = 82.0 dBFS, SFDR = 82 dBc, Non HD23 = 93 dBFS

SNR = 82.0 dBFS, SFDR = 87 dBc, Non HD23 = 92 dBFS

Figure 6-5. Single Tone FFT at F_IN= 40 MHz

Figure 6-6. Single Tone FFT at F_IN= 64 MHz

SNR = 82.0 dBFS, SFDR = 87 dBc, Non HD23 = 92 dBFS

A_IN= -7 dBFS/tone, IMD3 =

Figure 6-7. Single Tone FFT at F_IN= 100 MHz

Figure 6-8. Two Tone FFT at F_IN= 10/12 MHz

A_IN= -20 dBFS/tone, IMD3 =

A_IN= -7 dBFS/tone, IMD3 =

Figure 6-9. Two Tone FFT at F_IN= 10/12 MHz

Figure 6-10. Two Tone FFT at F_IN= 40/45 MHz

Submit Document Feedback

15

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 6-11. AC Performance vs Input Frequency

Figure 6-12. ENOB vs Input Frequency

F_IN= 5 MHz

Figure 6-13. AC Performance vs Input Amplitude

Figure 6-14. AC Performance vs Sampling Rate

Figure 6-15. AC Performance vs Clock Amplitude

Single Ended Clock Input

Figure 6-16. AC Performance vs Clock Amplitude

16

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

F_IN= 5 MHz

Figure 6-17. AC Performance vs AVDD

Figure 6-18. AC Performance vs VCM vs

Temperature

F_IN= 5 MHz

Figure 6-19. AC Performance vs Clock Duty Cycle

Figure 6-20. INL vs Code

F_IN= 5 MHz

Figure 6-22. DC Offset Histogram

Figure 6-21. DNL vs Code

Submit Document Feedback

17

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

F_IN= 5 MHz, 2-wire

F_IN= 5 MHz, DDC Bypass

Figure 6-24. Current vs Decimation

Figure 6-23. Current vs Sampling Rate

F_IN= 5 MHz, Complex Decimation by 32

Figure 6-25. Current vs Output Interface

18

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

7 Parameter Measurement Information

Sample N

Sample N+1

Input Signal

t_AD

t_PD

Sampling

Clock

t_ACQ

t_Conversion

t_CDCLK

DCLKIN

DCLK

T_DCLK

t_CD

FCLK

t_DV

DA1/DB1

(MSB)

D15 D13 D11 D9

D7 D5 D3 D1 D15 D13 D11 D9

D6 D4 D2 D0 D14 D12 D10 D8

D7

D6

D5

D4

D3

D2

D1

D0

DA0/DB0

D14 D12 D10 D8

(LSB)

Sample N-2

Sample N-1

Figure 7-1. Timing diagram: 2-wire SLVDS

Sample N

t_AD

Sample N+1

Input Signal

t_PD

Sampling

Clock

t_ACQ

t_Conversion

t_CDCLK

DCLKIN

DCLK

FCLK

t_CD

T_DCLK

t_DV

DA0

DB0

D2

D1

D0 D15 D14 D13 D12 D11 D10 D9 D8

D7

D6

D5 D4

D3

D2

D1

D0

D2

D1

Sample N-2

Sample N-1

Figure 7-2. Timing diagram: 1-wire SLVDS

Submit Document Feedback

19

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Sample N

t_AD

Sample N+1

Input Signal

t_PD

Sampling

Clock

t_ACQ

t_Conversion

t_CDCLK

DCLKIN

DCLK

FCLK

t_CD

T_DCLK

t_DV

Channel A

Channel B

D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA0

Sample N-2

Sample N-1

Figure 7-3. Timing diagram:1/2-wire SLVDS

20

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8 Detailed Description

8.1 Overview

The ADC366x is a low noise, ultra-low power 16-bit high-speed dual channel ADC supporting sampling rates up

to 65 Msps. It offers very good DC precision together with IF sampling support which makes it ideally suited for a

wide range of applications. The ADC366x is equipped with an on-chip internal reference option but it also

supports the use of an external, high precision 1.6 V voltage reference or an external 1.2 V reference which is

buffered and gained up internally. Because of the inherent low latency architecture, the digital output result is

available after only one to two clock cycles. Single ended as well as differential input signaling is supported.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output

data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex

decimation.

The ADC366x uses a serial LVDS (SLVDS) interface to output the data which minimizes the number of digital

interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half-lane (1/2-wire) option. The

ADC366x includes a digital output formatter which supports output resolutions from 14 to 20-bit.

The device features and control options can be set up either through pin configurations or via SPI register writes.

8.2 Functional Block Diagram

REFBUF

1.2V REF

Digital Downconverter

NCO

VREF

Crosspoint

Switch

ADC

16bit

N

AIN

DCLKIN

DCLK

0.95V

VCM

FCLK

Dig I/F

SLVDS

NCO

DA0/1

DB0/1

ADC

16bit

N

BIN

CLK

Control

Submit Document Feedback

21

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3 Feature Description

8.3.1 Analog Input

The analog inputs of ADC366x are intended to be driven differentially. Both AC coupling and DC coupling of the

analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which

must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that

meets the device input common mode voltage range.

The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, with on-resistance

shown in red, are in same position (open or closed) simultaneously.

AVDD

Sampling Switch

0.32 pF

1 ꢀ

125 ꢀ

2 nH

xINP/

xINM

24 ꢀ

1.4 pF

0.15 pF

0.6 pF

GND

0.6 pF

GND

6.4 pF

7 ꢀ

GND

5 ꢀ

0.7 pF

1.6 pF

GND

Figure 8-1. Equivalent Input Network

8.3.1.1 Analog Input Bandwidth

Figure 8-2 shows the analog full power input bandwidth of the ADC366x with a 50 Ω differential termination. The

-3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is

approximately 120 MHz.

The equivalent differential input resistance R_INand input capacitance C_INvs frequency are shown in Figure 8-3.

0

-1

-2

-3

-4

-5

-6

10

100

Input Frequency (MHz)

1000

ADC3

Figure 8-3. Equivant R_IN, C_INvs Input Frequency

Figure 8-2. ADC Analog Input bandwidth response

22

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.1.2 Analog Front End Design

The ADC366x is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch

from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low

output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-

coupled applications which can be combined with the termination network.

8.3.1.2.1 Sampling Glitch Filter Design

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter

performance is dependent on input frequency and therefore the following filter designs are recommended for

different input frequency ranges as shown in Figure 8-4 and Figure 8-5.

33 ꢀ

10 ꢀ

180nH

100 pF

Termination

33 ꢀ

180nH

10 ꢀ

Figure 8-4. Sampling glitch filter example for input frequencies from DC to 30 MHz

33 ꢀ

10 ꢀ

100pF

120nH

82 pF

Termination

33 ꢀ

10 ꢀ

100pF

120nH

Figure 8-5. Sampling glitch filter example for input frequencies from 30 to 70 MHz

Submit Document Feedback

23

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.1.2.2 Analog Input Termination and DC Bias

Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.

8.3.1.2.2.1 AC-Coupling

The ADC366x requires external DC bias using the common mode output voltage (VCM) of the ADC together

with the termination network as shown in Figure 8-6. The termination is located within the glitch filter network.

When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of

the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier

performance.

Glitch Filter

Termination

33 ꢀ

1 uF

10 ꢀ

180nH

25 ꢀ

100 pF

VCM

0.1 …F

25 ꢀ

33 ꢀ

1 uF

VCM

180nH

10 ꢀ

Figure 8-6. AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)

8.3.1.2.2.2 DC-Coupling

In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using

VCM output of the ADC as shown in Figure 8-7. The glitch filter in this case is located between the anti-alias filter

and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part

of the anti-alias filter.

Glitch Filter

33 ꢀ

10 ꢀ

180nH

100 pF

AAF (Anti

Alias Filter)

33 ꢀ

VCM

180nH

10 ꢀ

Figure 8-7. DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)

24

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.1.3 Auto-Zero Feature

The ADC366x includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This

auto-zero feature is enabled by default for the ADC3661/2 and can be enabled using SPI register writes for the

ADC3663 (register 0x11, D0).

0

-20

-80

-90

Auto-zero DIS

Auto-zero EN

Auto-zero DIS

Auto-zero EN

-40

-100

-110

-120

-130

-140

-150

-160

-60

-80

-100

-120

-140

-160

0

2.5

5

7.5

10

12.5

0.01

0.1

1

10

100

1000

Frequency (MHz)

Frequency (kHz)

adc3

Figure 8-8. FFT at 25 MSPS with input frequency of Figure 8-9. FFT at 25 MSPS with input frequency of

3 MHz (auto-zero feature enable vs disable, 4M

point FFT)

3 MHz (auto-zero feature enable vs disable, 4M

point FFT)

Figure 8-11. FFT at 65 MSPS with input frequency

of 5 MHz (auto-zero feature enabled vs disabled,

4M point FFT)

Figure 8-10. FFT at 65 MSPS with input frequency

of 3 MHz (auto-zero feature enable vs disable, 4M

point FFT)

Submit Document Feedback

25

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.2 Clock Input

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications (Figure 8-12 and Figure

8-13). For less jitter sensitive applications, the ADC368x provides the option to operate with single ended

signaling which saves additional power consumption.

Figure 8-12. AC Performance vs Clock Amplitude

(Differential Clock Input)

Figure 8-13. AC Performance vs Clock Amplitude

(Single Ended Clock Input)

8.3.2.1 Single Ended vs Differential Clock Input

The ADC366x can be operated using a differential or a single ended clock input where the single ended clock

consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently

the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

•

Differential Clock Input: The clock input can be AC coupled externally. The ADC366x provides internal bias.

Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with

the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC

coupled around a 0.9V center. The unused input needs to be AC coupled to ground.

1.8V

CLKP

0.9V

0V

+

-

5kO

VCM

0.9V

5kO

CLKM

Figure 8-14. External and internal connection using differential (left) and single ended (right) clock input

8.3.2.2 Signal Acquisition Time Adjust

The ADC366x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for

clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer

time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. This

register should only be used for the 65 MSPS speed grade (ADC3663) For the 10 and 25 MSPS device speed

grades the sampling time is already set to T_S/2. When powering down the DLL, the acquisition time will track the

clock duty cycle (50% is recommended).

Table 8-1. Acquisition time vs DLL PDN setting

SAMPLING CLOCK F_S(MSPS)

DLL PDN (0x11, D2)

ACQUISITION TIME (t_ACQ)

65

0

1

T_S/ 4

T_S/ 2

≤ 40

26

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.3 Voltage Reference

The ADC366x provides three different options for supplying the voltage reference to the ADC. An external 1.6 V

reference can be directly connected to the VREF input; a voltage 1.2 V reference can be connected to the

REFBUF input using the internal gain buffer or the internal 1.2 V reference can be enabled to generate a 1.6 V

reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1

uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC366x is shown in Figure

8-15.

Note

The voltage reference mode can be selected using SPI writes or by using the REFBUF pin (default) as

a control pin (Section 8.5.1). If the REFBUF pin is not used for configuration, the REFBUF pin should

be connected to AVDD (even though the REFBUF pin has a weak internal pullup to AVDD) and the

voltage reference option has to be selected using the SPI interface.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

x1.33

REFBUF

(1.2V)

VREF1.2

REFGND

Figure 8-15. Different voltage reference options for ADC366x

8.3.3.1 Internal voltage reference

The 1.6 V reference for the ADC can be generated internal using the on-chip 1.2V reference along with the

internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) should be connected between the

VREF and REFGND pins as close to the pins as possible.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

X1.33

C_VREF

REFBUF

(1.2V)

VREF1.2

REFGND

Figure 8-16. Internal reference

Submit Document Feedback

27

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.3.2 External voltage reference (VREF)

For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6 V

reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) connected between the VREF and REFGND

pins and placed as close to the pins as possible is recommended. The load current from the external reference

is about 1 mA.

Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier

should only be powered down in power down state but not during normal operation.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

Reference

1.6V

REFBUF

(1.2V)

x1.33

C_VREF

VREF1.2

REFGND

Figure 8-17. External 1.6V reference

8.3.3.3 External voltage reference with internal buffer (REFBUF)

The ADC366x is equipped with an on-chip reference buffer that also includes gain to generate the 1.6 V

reference voltage from an external 1.2 V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF

)

between the VREF and REFGND pins and a 10 uF and a 0.1 uF ceramic bypass capacitor between the

REFBUF and REFGND pins are recommended. Both capacitors should be placed as close to the pins as

possible. The load current from the external reference is less than 100 uA.

xINP

xINM

0.95V

VCM

VREF

(1.6V)

x1.33

REFBUF

(1.2V)

Reference

1.2V

VREF1.2

C_REFBUF

C_VREF

REFGND

Figure 8-18. External 1.2V reference using internal reference buffer

28

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.4 Digital Down Converter

The ADC366x includes an optional on-chip digital down conversion (DDC) decimation filter that can be enabled

via SPI register settings. It supports complex decimation by 2, 4, 8, 16 and 32 using a digital mixer and a 32-bit

numerically controlled oscillator (NCO) as shown in Figure 8-19. Furthermore it supports a mode with real

decimation where the complex mixer is bypassed (NCO should be set to 0 for lowest power consumption) and

the digital filter acts as a low pass filter.

Internally the decimation filter calculations are performed with a 20-bit resolution in order to avoid any SNR

degradation due to quantization noise. The Section 8.3.5.1 truncates to the selected resolution prior to outputting

the data on the digital interface.

NCO

32bit

Filter

I

Q

I

Q

Digital

Interface

N

ADC

SYNC

Figure 8-19. Internal Digital Decimation Filter

8.3.4.1 DDC MUX

The ADC366x family contains a MUX in front of the digital decimation filter which allows the ADC channel A

input to be connected to the DDC of channel B and vice versa.

Digital Downconverter

NCO

DDC MUX

N

ADC

NCO

N

ADC

Figure 8-20. DDC MUX

Submit Document Feedback

29

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.4.2 Digital Filter Operation

The complex decimation operation is illustrated with an example in Figure 8-21. First the input signal (and the

negative image) are frequency shifted by the NCO frequency as shown on the left. Next a digital filter is applied

(centered around 0 Hz) and the output data rate is decimated - in this example the output data rate F_S,OUT= F_S/8

with a Nyquist zone of F_S/16. During the complex mixing the spectrum (signal and noise) is split into real and

complex parts and thus the amplitude is reduced by 6-dB. In order to compensate this loss, there is a 6-dB

digital gain option in the decimation filter block that can be enabled via SPI write.

Input Signal

(Alias)

Shifted Input

Signal (Alias)

-F_IN+ F_NCO

Shifted Input Signal

Negative Image

Input Signal

Negative Image

Decimation

by 8

F_IN+ F_NCO

0

-FS/16

FS/16

FS/2

-FS/2

FS/2

F_NCO

NCO Tuning Range

Figure 8-21. Complex decimation illustration

The real decimation operation is illustrated with an example in Figure 8-22. There is no frequency shift

happening and only the real portion of the complex digital filter is exercised. The output data rate is decimated -

a decimation of 8 would result in an output data rate F_S,OUT= F_S/8 with a Nyquist zone of F_S/16.

During the real mixing the spectrum (signal and noise) amplitude is reduced by 3-dB. In order to compensate this

loss, there is a 3-dB digital gain option in the decimation filter block that can be enabled via SPI write.

Input Signal

Decimation by

32

Decimation by

16

Decimation by 2

Decimation by 4

Decimation by 8

FS/2

FS/16

FS/8

FS/4

FS/32

FS/64

Figure 8-22. Real decimation illustration

30

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.4.3 FS/4 Mixing with Real Output

In this mode, the output after complex decimation gets mixed with FS/4 (FS = output data rate in this case).

Instead of a complex output with the input signal centered around 0 Hz, the output is transmitted as a real output

at twice the data rate and the signal is centered around FS/4 (Fout/4) as illustrated in Figure 8-23.

In this example, complex decimation by 8 is used. The output data is transmitted as a real output with an output

rate of Fout = FS'/4 (FS' = ADC sampling rate). The input signal is now centered around FS/4 (Fout/4) or FS'/16.

F_IN

F_NCO

- F_IN+ F_NCO

-F_IN+ F_NCO+ FS/4

/8

FS/4 mix

Fout/4 mix

Complex

Decimation /8

0

FS‘/2

FS/16

FS‘/2

FS/8

0

FS/2

Figure 8-23. FS/4 Mixing with real output

8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer

The decimation block is equipped with a 32-bit NCO and a digital mixer to fine tune the frequency placement

prior to the digital filtering. The oscillator generates a complex exponential sequence of:

e^jωn(default) or e^–jωn

(1)

where: frequency (ω) is specified as a signed number by the 32-bit register setting

The complex exponential sequence is multiplied with the real input from the ADC to mix the desired carrier to a

frequency equal to f_IN+ f_NCO. The NCO frequency can be tuned from –F_S/2 to +F_S/2 and is processed as a

signed, 2s complement number. After programming a new NCO frequency, the MIXER RESTART register bit or

SYNC pin has to be toggled for the new frequency to get active. Additionally the ADC366x provides the option

via SPI to invert the mixer phase.

The NCO frequency setting is set by the 32-bit register value given and calculated as:

NCO frequency = 0 to + F_S/2: NCO = f_NCO× 2³²/ F_S

NCO frequency = -F_S/2 to 0: NCO = (f_NCO+ F_S) × 2³²/ F_S

where:

•

NCO = NCO register setting (decimal value)

f_NCO= Desired NCO frequency (MHz)

F_S= ADC sampling rate (MSPS)

The NCO programming is further illustrated with this example:

•

ADC sampling rate F_S= 65 MSPS

Input signal f_IN= 10 MHz

Desired output frequency f_OUT= 0 MHz

For this example there are actually four ways to program the NCO and achieve the desired output frequency as

shown in Table 8-2.

Table 8-2. NCO value calculations example

Alias or negative image

f_IN= –10 MHz

f_NCO

NCO Value

660764199

3634203097

660764199

3634203097

Mixer Phase

Frequency translation for f_OUT

f_NCO= 10 MHz

f_NCO= –10 MHz

f_NCO= 10 MHz

f_NCO= –10 MHz

f_OUT= f_IN+ f_NCO= –10 MHz +10 MHz = 0 MHz

f_OUT= f_IN+ f_NCO= 10 MHz + (–10 MHz) = 0 MHz

f_OUT= f_IN– f_NCO= 10 MHz – 10 MHz = 0 MHz

f_OUT= f_IN– f_NCO= –10 MHz – (–10 MHz) = 0 MHz

as is

f_IN= 10 MHz

inverted

f_IN= –10 MHz

Submit Document Feedback

31

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.4.5 Decimation Filter

The ADC366x supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and a

stopband rejection of at least 85 dB. Table 8-3 gives an overview of the pass-band bandwidth of the different

decimation settings with respect to ADC sampling rate F_S. In real decimation mode the output bandwidth is half

of the complex bandwidth.

Table 8-3. Decimation Filter Summary and Maximum Available Output Bandwidth

REAL/COMPLEX

DECIMATION

SETTING N

OUTPUT

BANDWIDTH

OUTPUT RATE

(F_S= 65 MSPS)

OUTPUT BANDWIDTH

(F_S= 65 MSPS)

OUTPUT RATE

2

4

F_S/ 2 complex

F_S/ 4 complex

F_S/ 8 complex

F_S/ 16 complex

F_S/ 32 complex

F_S/ 2 real

0.8 × F_S/ 2

0.8 × F_S/ 4

0.8 × F_S/ 8

0.8 × F_S/ 16

0.8 × F_S/ 32

0.4 × F_S/ 2

0.4 × F_S/ 4

0.4 × F_S/ 8

0.4 × F_S/ 16

0.4 × F_S/ 32

32.5 MSPS complex

16.25 MSPS complex

8.125 MSPS complex

4.0625 MSPS complex

2.03125 MSPS complex

32.5 MSPS

26 MHz

13 MHz

Complex

8

6.5 MHz

16

32

2

3.25 MHz

1.625 MHz

13 MHz

4

F_S/ 4 real

16.25 MSPS

6.5 MHz

Real

8

F_S/ 8 real

8.125 MSPS

3.25 MHz

1.625 MHz

0.8125 MHz

16

32

F_S/ 16 real

4.0625 MSPS

F_S/ 32 real

2.03125 MSPS

The decimation filter responses normalized tot he ADC sampling clock frequency are illustrated in Figure 8-25 to

Figure 8-34. They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-24.

The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate F_S.

For example, in the divide-by-4 complex setup, the output data rate is F_S/ 4 complex with a Nyquist zone of F_S/

8 or 0.125 × F_S. The transition band (colored in blue) is centered around 0.125 × F_Sand the alias transition band

is centered at 0.375 × F_S. The stop-bands (colored in red), which alias on top of the pass-band, are centered at

0.25 × F_Sand 0.5 × F_S. The stop-band attenuation is greater than 85 dB.

0

Passband

Transition Band

-20

Alias Band

Attn Spec

Filter

-40

-60

Transition

Bands

Bands that alias on top

of signal band

Pass Band

-80

-100

-120

0

0.1

0.2

0.3

0.4

0.5

Normalized Frequency (Fs)

Figure 8-24. Interpretation of the Decimation Filter Plots

32

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

0

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

Passband

Transition Band

Alias Band

Attn Spec

Transition Band

Alias Band

Attn Spec

-20

-40

-60

-0.01

-0.02

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.1

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.025 0.05 0.075

0.1

0.125 0.15 0.175

0.2

0.225 0.25

Normalized Frequency (Fs)

Decb

Figure 8-25. Decimation by 2 complex frequency

response

Figure 8-26. Decimation by 2 complex passband

ripple response

0

Passband

Transition Band

Alias Band

Passband

Transition Band

Alias Band

Attn Spec

-0.01

-0.02

-20

-40

Attn Spec

-0.03

-0.04

-0.05

-0.06

-0.07

-0.08

-0.09

-0.1

-60

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12

Normalized Frequency (Fs)

Decb

Figure 8-27. Decimation by 4 complex frequency

response

Figure 8-28. Decimation by 4 complex passband

ripple response

0

-0.08

Passband

Transition Band

Alias Band

Passband

-0.081

-0.082

-0.083

-0.084

-0.085

-0.086

-0.087

-0.088

-0.089

-0.09

Transition Band

Alias Band

Attn Spec

-20

-40

Attn Spec

-60

-0.091

-0.092

-0.093

-0.094

-0.095

-0.096

-0.097

-0.098

-0.099

-0.1

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.006 0.012 0.018 0.024 0.03 0.036 0.042 0.048 0.054 0.06

Normalized Frequency (Fs)

Decb

Figure 8-29. Decimation by 8 complex frequency

response

Figure 8-30. Decimation by 8 complex passband

ripple response

Submit Document Feedback

33

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

0

-20

-0.1

-0.11

-0.12

-0.13

-0.14

-0.15

-0.16

-0.17

-0.18

-0.19

-0.2

Passband

Transition Band

Alias Band

Attn Spec

Transition Band

Alias Band

Attn Spec

-40

-60

-80

-100

-120

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.003 0.006 0.009 0.012 0.015 0.018 0.021 0.024 0.027 0.03

Normalized Frequency (Fs)

Decb

Figure 8-31. Decimation by 16 complex frequency Figure 8-32. Decimation by 16 complex passband

response ripple response

0

-0.2

-0.205

-0.21

Passband

Transition Band

Alias Band

Attn Spec

Transition Band

Alias Band

Attn Spec

-20

-0.215

-0.22

-40

-60

-0.225

-0.23

-80

-0.235

-0.24

-100

-120

-0.245

-0.25

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Normalized Frequency (Fs)

Decb

Figure 8-33. Decimation by 32 complex frequency Figure 8-34. Decimation by 32 complex passband

response ripple response

8.3.4.6 SYNC

The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/

SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality and is

latched in by the rising edge of the sampling clock as shown in Figure 8-35.

CLK

t_S,SYNC

t_H,SYNC

SYNC

Figure 8-35. External SYNC timing diagram

The synchronization signal is only required when using the decimation filter - either using the SPI SYNC register

or the PDN/SYNC pin. It resets internal clock dividers used in the decimation filter and aligns the internal clocks

as well as I and Q data within the same sample. If no SYNC signal is given the internal clock dividers will not be

synchronized, which can lead to a fractional delay across different devices. The SYNC signal also resets the

NCO phase and loads the new NCO frequency (same as the MIXER RESTART bit).

When trying to resynchronize during operation, the SYNC toggle should occur at 64*K clock cycles, where K is

an integer. This ensures phase continuity of the clock divider.

34

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.4.7 Output Formatting with Decimation

When using decimation, the output data is formatted as shown in Figure 8-36 and Figure 8-37. The examples

are shown for 16-bit output for 2-wire (8x serialization), 1-wire (16x serialization) and 1/2-wire (32x serialization).

FCLK

A_I

D9

A_I

D7

A_I

D5

A_I

D3

A_I

D1

A_Q

D9

A_Q

D7

A_Q

D5

A_Q

D3

A_Q

D1

DA1

DA0

DB1

D15 D13 D11

ChA

ChB

A_I

D8

A_I

D6

A_I

D4

A_I

D2

A_I

D0

A_Q

D8

A_Q

D6

A_Q

D4

A_Q

D2

A_Q

D0

D14 D12 D10

Serial LVDS

2-Wire

(8x Serialization)

B_I

D9

B_I

D7

B_I

D5

B_I

D3

B_I

D1

B_Q

D9

B_Q

D7

B_Q

D5

B_Q

D3

B_Q

D1

D15 D13 D11

B_I

D8

B_I

D6

B_I

D4

B_I

D2

B_I

D0

B_Q

D8

B_Q

D6

B_Q

D4

B_Q

D2

B_Q

D0

DB0

D14 D12 D10

DCLK

FCLK

DA0

DB0

A_I<15:0>

B_I<15:0>

A_Q<15:0>

B_Q<15:0>

Serial LVDS

1-Wire

(16x Serialization)

DCLK

FCLK

DA0

Serial LVDS

1/2-Wire

A_I<15:0>

B_I<15:0>

A_Q<15:0>

B_Q<15:0>

(32x Serialization)

DCLK

Figure 8-36. Output Data Format in Complex Decimation

Table 8-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK

frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).

Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output

resolution and complex decimation by 4.

Table 8-4. Serial LVDS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution

DECIMATION

SETTING

ADC SAMPLING

RATE

OUTPUT

RESOLUTION

# of WIRES

FCLK

DCLKIN, DCLK

DA/B0,1

N

F_S

R

L

2

F_S/ N

[DA/B0,1] / 2

130 MHz

F_Sx 2 x R / L / N

260 MHz

65 MSPS

62.5 MSPS

16.25 MHz

4

16

1

260 MHz

520 MHz

1/2

15.625 MHz

500 MHz

1000 MHz

Submit Document Feedback

35

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

FCLK

DA1

DA0

DB1

DB0

DCLK

A₀

D9

A₀

D7

A₀

D5

A₀

D3

A₀

D1

A₁

D9

A₁

D7

A₁

D5

A₁

D3

A₁

D1

D15 D13 D11

ChA

A₀

D8

A₀

D6

A₀

D4

A₀

D2

A₀

D0

A₁

D8

A₁

D6

A₁

D4

A₁

D2

A₁

D0

D14 D12 D10

Serial LVDS

2-Wire

(8x Serialization)

B₀

D9

B₀

D7

B₀

D5

B₀

D3

B₀

D1

B₁

D9

B₁

D7

B₁

D5

B₁

D3

B₁

D1

D15 D13 D11

ChB

B₀

D8

B₀

D6

B₀

D4

B₀

D2

B₀

D0

B₁

D8

B₁

D6

B₁

D4

B₁

D2

B₁

D0

D14 D12 D10

FCLK

DA0

DB0

A₀<15:8>

B₀<15:8>

A₀<7:0>

B₀<7:0>

Serial LVDS

1-Wire

(16x Serialization)

DCLK

FCLK

DA0

Serial LVDS

1/2-Wire

A₀<15:0>

B₀<15:0>

(32x Serialization)

DCLK

Figure 8-37. Output Data Format in Real Decimation

Table 8-5 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK

frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).

Furthermore the table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output

resolution and real decimation by 4.

Table 8-5. Serial LVDS Lane Rate Examples with Real Decimation and 16-bit Output Resolution

DECIMATION

SETTING

ADC SAMPLING

RATE

OUTPUT

RESOLUTION

# of WIRES

FCLK

DCLKIN, DCLK

DA/B0,1

F_S/ M / 2 (L = 2)

F_S/ M (L = 1, 1/2)

M

F_S

R

L

[DA/B0,1] / 2

F_Sx R / L / M

2

1

8.125 MHz

65 MHz

130 MHz

260 MHz

130 MHz

260 MHz

520 MHz

4

65 MSPS

16

16.25 MHz

1/2

36

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.5 Digital Interface

The serial LVDS interface supports the data output with 2-wire, 1-wire and 1/2-wire operation. The actual data

output rate depends on the output resolution and number of lanes used.

The ADC366x requires an external serial LVDS clock input (DCLKIN), which is used to transmit the data out of

the ADC along with the data clock (DCLK). The phase relationship between DCLKIN and the sampling clock is

irrelevant but both clocks need to be frequency locked. The SLVDS interface is configured using SPI register

writes.

8.3.5.1 Output Formatter

The digital output interface utilizes a flexible output bit mapper as shown in Figure 8-38. The bit mapper takes

the 16bit output directly from the ADC or from digital filter block and reformats it to a resolution of 14, 18 or 20-

bit. The output serialization factor gets adjusted accordingly for 2-, 1- and 1/2-wire interface mode. The

maximum output data rate can not be exceeded independently of output resolution and serialization factor.

For 14-bit output resolution the LSBs simply get truncated during the reformatting. With 18 and 20-bit output, in

bypass mode 0s are added while in decimation mode and the digital averaging mode the full 20-bit output is

utilized.

Output Bit

Mapping

14 Bit

16 Bit

18 Bit

20 Bit

NCO

16-Bit

Output

SLVDS

Interface

16-Bit ADC

N

Figure 8-38. Interface output bit mapper

Table 8-6 provides an overview for the resulting serialization factor depending on output resolution and output

modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output

resolution to 14-bit, 2-wire mode for example would result in DCLKIN = F_S* 3.5 instead of * 4.

Table 8-6. Serialization factor vs output resolution for different output modes

OUTPUT

RESOLUTION

Interface SERIALIZATION

FCLK

DCLKIN

DCLK

D0/D1

2-Wire

1-Wire

7x

F_S/2

F_S

F_S* 3.5

F_S* 7

F_S* 3.5

F_S* 7

F_S* 14

F_S* 28

F_S* 8

14-bit

14x

28x

8x

1/2-Wire

2-Wire

F_S

F_S* 14

F_S* 4

F_S* 14

F_S* 4

F_S/2

F_S

16-bit (default)

18-bit

1-Wire

16x

32x

9x

F_S* 8

F_S* 16

F_S* 32

F_S* 9

1/2-Wire

2-Wire

F_S

F_S* 16

F_S* 4.5

F_S* 9

F_S* 16

F_S* 4.5

F_S* 9

F_S/2

F_S

1-Wire

18x

36x

10x

20x

40x

F_S* 18

F_S* 36

F_S* 10

F_S* 20

F_S* 40

1/2-Wire

2-Wire

F_S

F_S* 18

F_S* 5

F_S* 18

F_S* 5

F_S/2

F_S

20-bit

1-Wire

F_S* 10

F_S* 20

F_S* 10

F_S* 20

1/2-Wire

F_S

The programming sequence to change the output interface and/or resolution from default settings is shown in

Table 8-7.

Submit Document Feedback

37

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.5.2 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling

the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining

steps can come in any order.

Table 8-7. Configuration steps for changing interface or decimation

STEP

FEATURE

ADDRESS

DESCRIPTION

1

0x07

Select the output interface bit mapping depending on resolution and output interface.

Output Resolution

14-bit

2-wire

0x2B

0x4B

0x2B

0x4B

1-wire

1/2-wire

0x8D

16-bit

0x6C

18-bit

20-bit

Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to

0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00

2

3

0x13

0x19

Configure the FCLK frequency based on bypass/decimation and number of lanes used.

FCLK SRC

(D7)

FCLK DIV

(D4)

TOG FCLK

(D0)

Bypass/Dec

SLVDS

2-wire

1-wire

0

1

0

1

0

1

Bypass/ Real

Decimation

1/2-wire

2-wire

Output

Interface

Complex

Decimation

1-wire

1/2-wire

4

5

0x1B

Select the output interface resolution using the bit mapper (D5-D3).

Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.

Output Resolution

14-bit

2-wire

1-wire

1/2-wire

0xFE000

0xFF000

0xFF800

0xFFC00

16-bit

Real Decimation

use default

0x20

0x21

0x22

18-bit

20-bit

use default

14-bit

16-bit

Complex

Decimation

0xFFFFF

18-bit

20-bit

6

7

0x24

0x25

Enable the decimation filter

Configure the decimation filter

0x2A/B/C/D

0x31/2/3/4

8

Program the NCO frequency for complex decimation (can be skipped for real decimation)

Configure the complex output data stream (set both bits to 0 for real decimation)

Decimation

Filter

SLVDS

2-wire

OP-Order (D4)

Q-Delay (D3)

0x27

0x2E

9

1

0

1

0

1

1-wire

1/2-wire

10

0x26

Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.

38

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.3.5.2.1 Configuration Example

The following is a step by step programming example to configure the ADC366x to complex decimation by 8 with

1-wire SLVDS and 16-bit output.

1. 0x07 (address) 0x6C (load bit mapper configuration for 16-bit output with 1-wire SLVDS)

2. 0x13 0x01, wait 1 ms, 0x13 0x00 (load e-fuse)

3. 0x19 0x80 (configure FCLK)

4. 0x1B 0x88 (select 16-bit output resolution)

5. 0x20 0xFF, 0x21 0xFF, 0x22 0x0F (configure FCLK pattern)

6. 0x24 0x06 (enable decimation filter)

7. 0x25 0x30 (configure complex decimation by 8)

8. 0x2A/B/C/D and 0x31/32/33/34 (program NCO frequency)

9. 0x27/0x2E 0x08 (configure Q-delay register bit)

10.0x26 0xAA, 0x26 0x88 (set digital mixer gain to 6-dB and toggle the mixer update)

8.3.5.3 Output Data Format

The output data can be configured to two's complement (default) or offset binary formatting using SPI register

writes (register 0x8F and 0x92). Table 8-8 provides an overview for minimum and maximum output codes for the

two formatting options. The actual output resolution is set by the output bit mapper.

Table 8-8. Overview of minimum and maximum output codes vs output resolution for different formatting

Two's Complement (default)

Offset Binary

RESOLUTION (BIT)

14

16

18

20

14

16

18

20

V_IN,MAX

0

0x1FFF

0x7FFF

0x1FFFF

0x7FFFF

0x3FFF

0x2000

0xFFFF

0x8000

0x3FFFF

0x20000

0xFFFFF

0x80000

0x0000

0x00000

V_IN,MIN

0x2000

0x8000

0x20000

0x80000

0x0000

0x00000

8.3.6 Test Pattern

In order to enable in-circuit testing of the digital interface, the following test patterns are supported and enabled

via SPI register writes (0x14/0x15/0x16). In decimation mode (real and complex), the test patterns replace the

output data of the DDC - however channel A controls the test patterns for both channels.

•

RAMP Pattern: The step size needs to be configured in the CUSTOM PAT register according to the native

resolution of the ADC. When selecting a higher output resolution then the additional LSBs will still be 0 in

RAMP pattern mode.

– 00001: 18-bit output resolution

– 00100: 16-bit output resolution

– 10000: 14-bit output resolution

•

Custom Pattern: Configured in the CUSTOM PAT register

Submit Document Feedback

39

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.4 Device Functional Modes

8.4.1 Normal operation

In normal operating mode, the entire ADC full scale range gets converted to a digital output with 16-bit

resolution. The output is available in as little as 1 clock cycle on the digital outputs.

8.4.2 Power Down Options

A global power down mode can be enabled via SPI as well as using the power down pin (PDN/SYNC). There is

an internal pull-down 21 kΩ resistor on the PDN/SYNC input pin and the pin is active high - so the pin needs to

be pulled high externally to enter global power down mode.

The SPI register map provides the capability to enable/disable individual blocks directly or via PDN pin mask in

order to trade off power consumption vs wake up time as shown in Table 8-9.

REFBUF

1.2V REF

Digital Downconverter

NCO

VREF

AIN

Crosspoint

Switch

N

ADC

NCO

Dig I/F

N

BIN

CLK

ADC

Figure 8-39. Power Down Configurations

Table 8-9. Overview of Power Down Options

PDN

via SPI

Mask for

Global PDN

Feature -

Default

Power

Impact

Wake-up

time

Function/ Register

ADC

Comment

Both ADC channels are included in

Global PDN automatically

Yes

-

Enabled

Should only be powered down in power

down state.

Reference gain amplifier

Internal 1.2V reference

~ 0.4 mA

~3 us

Internal/external reference selection is

available through SPI and REFBUF pin.

External ref

~ 1-3.5 mA

~3 ms

Yes

Single ended clock input saves ~ 1mA

compared to differential.

Some programmability is available

through the REFBUF pin.

Differential

clock

Clock buffer

Yes

~ 1 mA

varies

n/a

Depending on output interface mode,

unused output drivers can be powered

down for maximum power savings

Output interface drivers

Decimation filter

Yes

-

Enabled

Disabled

n/a

see electrical

table

40

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.4.3 Digital Channel Averaging

The ADC366x includes a digital channel averaging feature which enables improvement of the ADC dynamic

range (see Figure 8-40). The same input signal is given to both ADC inputs externally and the output of the two

ADCs is averaged internally. By averaging, uncorrelated noise (e.g. ADC thermal noise) improves 3-dB while

correlated noise (e.g. jitter in the clock path, reference noise) is unaffected. Therefore the averaging gives close

to 3-dB improvement at low input frequencies but less at high input frequencies where clock jitter dominates the

SNR.

The output from the digital averaging block is given out on the digital outputs of channel A or alternatively can be

routed to the digital decimation filters using the digital mux.

NCO

MUX

N

ADC

AVG

NCO

N

ADC

External

Internal

Figure 8-40. Digital Channel Averaging Diagram

Submit Document Feedback

41

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI) however it can

operate in a default configuration without requiring the SPI interface. Furthermore the power down function as

well as internal/external reference configuration is possible via pin control (PDN/SYNC and REFBUF pin).

Note

The power down command (via PIN or SPI) only goes in effect with the ADC sampling clock present.

8.5.1 Configuration using PINs only

The ADC voltage reference can be selected using the REFBUF pin. Even though there is an internal 100 kΩ

pull-up resistor to AVDD, the REFBUF pin should be set to a voltage externally and not left floating. When using

a voltage divider to set the REFBUF voltage (R1 and R2 in Figure 8-41), resistor values < 5 kΩ should be used.

AVDD

R1

AVDD

100 k

REFBUF

R2

Figure 8-41. Configuration of external voltage on REFBUF pin

Table 8-10. REFBUF voltage levels control voltage reference selection

REFBUF VOLTAGE

VOLTAGE REFERENCE OPTION

CLOCKING OPTION

> 1.7 V (Default)

1.2 V (1.15-1.25V)

0.5 - 0.7V

External reference

Differential clock input

Single ended clock input

External 1.2V input on REFBUF pin using internal gain buffer

Internal reference

< 0.1V

Internal reference

8.5.2 Configuration using the SPI interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting

bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when

SEN is active (low). The serial data are loaded into the register at every 24th SCLK rising edge when SEN is low.

When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples

of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 12 MHz

down to very low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

8.5.2.1 Register Write

The internal registers can be programmed following these steps:

1. Drive the SEN pin low

2. Set the R/W bit to 0 (bit A15 of the 16-bit address) and bits A[14:12] in address field to 0.

3. Initiate a serial interface cycle by specifying the address of the register (A[11:0]) whose content is written and

4. Write the 8-bit data that are latched in on the SCLK rising edges

Figure 8-42 show the timing requirements for the serial register write operation.

42

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Register Address <11:0>

A7 A6 A5 A4

Register Data <7:0>

R/W

0

SDIO

0

A11 A10

A9

A8

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

t_DH

D0

t_SCLK

t_DSU

SCLK

SEN

t_SLOADS

t_SLOADH

RESET

Figure 8-42. Serial Register Write Timing Diagram

8.5.2.2 Register Read

The device includes a mode where the contents of the internal registers can be read back using the SDIO pin.

This readback mode can be useful as a diagnostic check to verify the serial interface communication between

the external controller and the ADC. The procedure to read the contents of the serial registers is as follows:

1. Drive the SEN pin low

2. Set the R/W bit (A15) to 1. This setting disables any further writes to the registers. Set A[14:12] in address

field to 0.

3. Initiate a serial interface cycle specifying the address of the register (A[11:0]) whose content must be read

4. The device launches the contents (D[7:0]) of the selected register on the SDIO pin on SCLK falling edge

5. The external controller can capture the contents on the SCLK rising edge

Register Address <11:0>

Register Data <7:0>

R/W

1

t_OZD

A0

t_OD

SDIO

0

A11 A10

A9

A8

A7 A6 A5 A4

A3

A2

A1

D7

D6

D5 D4 D3

D2

D1

D0

SCLK

SEN

t_ODZ

Figure 8-43. Serial Register Read Timing Diagram

Submit Document Feedback

43

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.6 Register Map

Table 8-11. Register Map Summary

REGISTER

ADDRESS

REGISTER DATA

A[11:0]

0x00

D7

D6

D5

D4

0

D3

0

D2

D1

0

D0

0

RESET

0x07

OP IF MAPPER

0

OP IF EN

OP IF SEL

PDN

REFAMP

PDN

GLOBAL

0x08

0x09

0x0D

0x0E

0

PDN CLKBUF

0

PDN A

PDN B

PDN

FCLKOUT

PDN

DCLKOUT

PDN DA1

PDN DA0

PDN DB1

PDN DB0

0

MASK

CLKBUF

MASK

REFAMP

MASK BG

DIS

0

SYNC PIN

EN

SPI SYNC SPI SYNC EN

REF CTRL

REF SEL

SE CLK EN

0x11

0x13

0x14

0x15

0x16

0x19

0

SE A

0

SE B

0

DLL PDN

0

AZ EN

E-FUSE LD

CUSTOM PAT [7:0]

CUSTOM PAT [15:8]

TEST PAT A

TEST PAT B

0

CUSTOM PAT [17:16]

FCLK SRC

0

FCLK DIV

0

TOG FCLK

LVDS ½

SWING

0x1A

0

0x1B

0x1E

0x20

0x21

0x22

0x24

0x25

0x26

MAPPER EN

0

20B EN

0

BIT MAPPER RES

0

LVDS DATA DEL

LVDS DCLK DEL

FCLK PAT [7:0]

FCLK PAT [15:8]

0

FCLK PAT [19:16]

0

CH AVG EN

DECIMATION

MIX RES A

DDC MUX

DIG BYP

0

DDC EN

0

DDC MUX EN

REAL OUT

MIX PHASE

FS/4 MIX B

MIX GAIN A

FS/4 MIX A

MIX GAIN B

MIX RES B

FS/4 MIX PH

A

0x27

0

OP ORDER A

Q-DEL A

0

0x2A

0x2B

0x2C

0x2D

NCO A [7:0]

NCO A [15:8]

NCO A [23:16]

NCO A [31:24]

FS/4 MIX PH

B

0x2E

0

OP ORDER B

Q-DEL B

0

0x31

0x32

0x33

0x34

0x8F

0x92

NCO B [7:0]

NCO B [15:8]

NCO B [23:16]

NCO B [31:24]

0

FORMAT A

FORMAT B

0

44

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

8.6.1 Detailed Register Description

Figure 8-44. Register 0x00

7

0

6

0

5

0

4

3

2

0

1

0

RESET

R/W-0

Table 8-12. Register 0x00 Field Descriptions

Bit

Field

0

Type

R/W

Reset

Description

7-1

0

Must write 0

RESET

This bit resets all internal registers to the default values and self

clears to 0.

Figure 8-45. Register 0x07

7

6

5

4

3

2

1

0

OP IF MAPPER

R/W-0

0

OP IF EN

R/W-0

OP IF SEL

R/W-0

Table 8-13. Register 0x07 Field Descriptions

Bit

Field

Type

Reset

Description

7-5

OP IF MAPPER

R/W

000

Output interface mapper. This register contains the proper

output interface bit mapping for the different interfaces. The

interface bit mapping is internally loaded from e-fuses and also

requires a fuse load command to go into effect (0x13, D0).

Register 0x07 along with the E-Fuse Load (0x13, D0) needs to

be loaded first in the programming sequence since the E-Fuse

load resets the SPI writes.

After initial reset the default output interface variant is loaded

automatically from fuse internally. However when reading back

this register reads 000 until a value is written using SPI.

001: 2-wire, 18 and 14-bit

010: 2-wire, 16-bit

011: 1-wire

100: 0.5-wire

others: not used

4

3

0

R/W

0

Must write 0

OP IF EN

OP IF SEL

0

Enables changing the default output interface mode (D2-D0).

2-0

000

Selection of the output interface mode. OP IF EN (D3) needs to

be enabled also.

After initial reset the default output interface is loaded

automatically from fuse internally. However when reading back

this register reads 000 until a value is written using SPI.

011: 2-wire

100: 1-wire

101: 0.5-wire

others: not used

Submit Document Feedback

45

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-46. Register 0x08

7

0

6

0

5

4

3

2

1

0

PDN CLKBUF PDN REFAMP

R/W-0 R/W-0

0

PDN A

R/W-0

PDN B

R/W-0

PDN GLOBAL

R/W-0

Table 8-14. Register 0x08 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

0

Must write 0

PDN CLKBUF

Powers down sampling clock buffer

0: Clock buffer enabled

1: Clock buffer powered down

4

PDN REFAMP

R/W

0

Powers down internal reference gain amplifier

0: REFAMP enabled

1: REFAMP powered down

3

2

0

R/W

0

Must write 0

PDN A

Powers down ADC channel A

0: ADC channel A enabled

1: ADC channel A powered down

1

0

PDN B

R/W

0

Powers down ADC channel B

0: ADC channel B enabled

1: ADC channel B powered down

PDN GLOBAL

Global power down via SPI

0: Global power disabled

1: Global power down enabled. Power down mask (register

0x0D) determines which internal blocks are powered down.

Figure 8-47. Register 0x09

7

0

6

0

5

4

3

2

1

0

PDN FCLKOUT PDN DCLKOUT

R/W-0 R/W-0

PDN DA1

R/W-0

PDN DA0

R/W-0

PDN DB1

R/W-0

PDN DB0

R/W-0

Table 8-15. Register 0x09 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

0

Must write 0

PDN FCLKOUT

Powers down frame clock (FCLK) LVDS output buffer

0: FCLK output buffer enabled

1: FCLK output buffer powered down

4

3

PDN DCLKOUT

PDN DA1

R/W

0

Powers down DCLK LVDS output buffer

0: DCLK output buffer enabled

1: DCLK output buffer powered down

Powers down LVDS output buffer for channel A, lane 1.

NOT powered down automatically in 1-wire and 1/2-wire mode.

0: DA1 LVDS output buffer enabled

1: DA1 LVDS output buffer powered down

2

1

PDN DA0

PDN DB1

R/W

0

Powers down LVDS output buffer for channel A, lane 0.

0: DA0 LVDS output buffer enabled

1: DA0 LVDS output buffer powered down

Powers down LVDS output buffer for channel B, lane 1.

NOT powered down automatically in 1-wire and 1/2-wire mode.

0: DB1 LVDS output buffer enabled

1: DB1 LVDS output buffer powered down

0

PDN DB0

R/W

0

Powers down LVDS output buffer for channel B, lane 0.

NOT powered down automatically in 1/2-wire mode.

0: DB0 LVDS output buffer enabled

1: DB0 LVDS output buffer powered down

46

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-48. Register 0x0D (PDN GLOBAL MASK)

7

0

6

0

5

4

3

2

1

0

MASK CLKBUF MASK REFAMP MASK BG DIS

R/W-0 R/W-0 R/W-0

0

R/W-0

Table 8-16. Register 0x0D Field Descriptions

Bit

7-4

3

Field

Type

R/W

Reset

Description

0

Must write 0

MASK CLKBUF

MASK REFAMP

MASK BG DIS

Global power down mask control for sampling clock input buffer.

0: Clock buffer will get powered down when global power down

is exercised.

1: Clock buffer will NOT get powered down when global power

down is exercised.

2

1

R/W

0

Global power down mask control for reference amplifier.

0: Reference amplifier will get powered down when global power

down is exercised.

1: Reference amplifier will NOT get powered down when global

power down is exercised.

Global power down mask control for internal 1.2V bandgap

voltage reference. Setting this bit reduces power consumption in

global power down mode but increases the wake up time. See

the power down option overview.

0: Internal 1.2V bandgap voltage reference will NOT get

powered down when global power down is exercised.

1: Internal 1.2V bandgap voltage reference will get powered

down when global power down is exercised.

0

R/W

0

Must write 0

Submit Document Feedback

47

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-49. Register 0x0E

7

6

5

4

3

2

1

0

SYNC PIN EN

R/W-0

SPI SYNC

R/W-0

SPI SYNC EN

R/W-0

0

REF CTL

R/W-0

REF SEL

SE CLK EN

R/W-0

Table 8-17. Register 0x0E Field Descriptions

Bit

Field

SYNC PIN EN

Type

Reset

Description

7

R/W

0

This bit controls the functionality of the SYNC/PDN pin.

0: SYNC/PDN pin exercises global power down mode when pin

is pulled high.

1: SYNC/PDN pin issues the SYNC command when pin is

pulled high.

6

5

SPI SYNC

R/W

0

Toggling this bit issues the SYNC command using the SPI

register write. SYNC using SPI must be enabled as well (D5).

This bit doesn't self reset to 0.

0: Normal operation

1: SYNC command issued.

SPI SYNC EN

This bit enables synchronization using SPI instead of the

SYNC/PDN pin.

0: Synchronization using SPI register bit disabled.

1: Synchronization using SPI register bit enabled.

4

3

0

R/W

0

Must write 0

REF CTL

This bit determines if the REFBUF pin controls the voltage

reference selection or the SPI register (D2-D1).

0: The REFBUF pin selects the voltage reference option.

1: Voltage reference is selected using SPI (D2-D1) and single

ended clock using D0.

2-1

REF SEL

R/W

00

Selects of the voltage reference option. REF CTRL (D3) must be

set to 1.

00: Internal reference

01: External voltage reference (1.2V) using internal reference

buffer (REFBUF)

10: External voltage reference

11: not used

0

SE CLK EN

0

Selects single ended clock input and powers down the

differential sampling clock input buffer. REF CRTL (D3) must be

set to 1.

0: Differential clock input

1: Single ended clock input

48

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-50. Register 0x11

7

0

6

0

5

4

3

2

1

0

SE A

R/W-0

SE B

R/W-0

0

DLL PDN

R/W-0

AZ EN

R/W-0

Table 8-18. Register 0x11 Field Descriptions

Bit

7-6

5

Field

0

Type

R/W

Reset

Description

0

Must write 0

SE A

This bit enables single ended analog input, channel A. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input

4

SE B

R/W

0

This bit enables single ended analog input, channel B. In this

mode the SNR reduces by 3-dB.

0: Differential input

1: Single ended input

3

2

0

R/W

0

Must write 0

DLL PDN

This register applies ONLY to the ADC3663. It powers down the

internal DLL, which is used to adjust the sampling time. This

register must only be enabled when operating at sampling rates

below 40 MSPS. When DLL PDN bit is enabled the sampling

time is directly dependent on sampling clock duty cycle (with a

50/50 duty the sampling time is T_S/2).

0: Sampling time is T_S/ 4

1: Sampling time is T_S/2 (only for sampling rates below 40

MSPS).

1

0

R/W

0

Must write 0

AZ EN

0/1

This bit enables the internal auto-zero circuitry. It is enabled by

default for the ADC3661/82 and disabled for the ADC3663.

0: Auto-zero disabled

1: Auto-zero enabled

Submit Document Feedback

49

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-51. Register 0x13

7

0

6

0

5

0

4

3

2

0

1

0

E-FUSE LD

R/W-0

Table 8-19. Register 0x13 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-1

0

Must write 0

E-FUSE LD

This register bit loads the internal bit mapping for different

interfaces. After setting the interface in register 0x07, this E-

FUSE LD bit needs to be set to 1 and reset to 0 for loading to go

into effect. Register 0x07 along with the E-Fuse Load (0x12, D0)

needs to be loaded first in the programming sequence since the

E-Fuse load resets the SPI writes.

0: E-FUSE LOAD set

1: E-FUSE LOAD reset

Figure 8-52. Register 0x14/15/16

7

6

5

4

3

2

1

0

CUSTOM PAT [7:0]

CUSTOM PAT [15:8]

TEST PAT B

R/W-0

TEST PAT A

R/W-0

CUSTOM PAT [17:16]

R/W-0 R/W-0

R/W-0

Table 8-20. Register 0x14/15/16 Field Descriptions

Bit

Field

CUSTOM PAT [17:0]

Type

Reset

Description

7-0

R/W

00000000 This register is used for two purposes:

•

It sets the constant custom pattern starting from MSB

It sets the RAMP pattern increment step size.

00001: Ramp pattern for 18-bit ADC

00100: Ramp pattern for 16-bit ADC

10000: Ramp pattern for 14-bit ADC

7-5

TEST PAT B

R/W

000

Enables test pattern output mode for channel B (NOTE: The test

pattern is set prior to the bit mapper and is based on native

resolution of the ADC starting from the MSB). These work in

either output format.

000: Normal output mode (test pattern output disabled)

010: Ramp pattern: need to set proper increment using

CUSTOM PAT register

011: Constant Pattern using CUSTOM PAT [17:0] in register

0x14/15/16.

others: not used

4-2

TEST PAT A

R/W

000

Enables test pattern output mode for channel A (NOTE: The test

pattern is set prior to the bit mapper and is based on native

resolution of the ADC starting from the MSB). These work in

either output format.

000: Normal output mode (test pattern output disabled)

010: Ramp pattern: need to set proper increment using

CUSTOM PAT register

011: Constant Pattern using CUSTOM PAT [17:0] in register

0x14/15/16.

others: not used

50

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-53. Register 0x19

7

6

0

5

0

4

3

2

0

1

0

FCLK SRC

R/W-0

FCLK DIV

R/W-0

0

TOG FCLK

R/W-0

Table 8-21. Register 0x19 Field Descriptions

Bit

Field

FCLK SRC

Type

Reset

Description

7

R/W

0

User has to select if FCLK signal comes from ADC or from DDC

block. Here real decimation is treated same as bypass mode

0: FCLK generated from ADC. FCLK SRC set to 0 for DDC

bypass, real decimation mode and 1/2-w complex decimation

mode.

1: FCLK generated from DDC block. In complex decimation

mode only this bit needs to be set for 2-w and 1-w output

interface mode but NOT for 1/2-w mode.

6-5

4

0

R/W

0

Must write 0

FCLK DIV

This bit needs to be set to 1 for 2-w output mode in bypass/real

decimation mode only .

0: All output interface modes except 2-w decimation bypass and

real decimation mode.

1: 2-w output interface mode for decimation bypass and real

decimation.

3-1

0

R/W

0

Must write 0

TOG FCLK

This bit adjusts the FCLK signal appropriately for 1/2-wire mode

where FCLK is stretched to cover channel A and channel B.

This bit ONLY needs to be set in 1/2-wire mode with complex

decimation mode.

0: all other modes.

1: FCLK for 1/2-wire complex decimation mode.

Table 8-22. Configuration of FCLK SRC and FCLK DIV Register Bits vs Serial Interface

BYPASS/DECIMATION

SERIAL INTERFACE

FCLK SRC

FCLK DIV

TOG FCLK

2-wire

0

1

0

1

0

1

Decimation Bypass/ Real Decimation

Complex Decimation

1-wire

1/2-wire

2-wire

1-wire

1/2-wire

Figure 8-54. Register 0x1A

7

0

6

5

0

4

3

2

0

1

0

LVDS ½

SWING

0

R/W-0

Table 8-23. Register 0x1A Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7

6

0

Must write 0

LVDS ½ SWING

This bit reduces the LVDS output current from 3.5 mA to 1.75

mA which reduces power consumption.

0: Normal output current 3.5 mA

1: Reduced LVDS output current 1.75 mA

5-0

0

R/W

0

Must write 0

Submit Document Feedback

51

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-55. Register 0x1B

7

6

5

4

3

2

0

1

0

MAPPER EN

R/W-0

20B EN

R/W-0

BIT MAPPER RES

R/W-0

Table 8-24. Register 0x1B Field Descriptions

Bit

Field

MAPPER EN

Type

Reset

Description

7

R/W

0

This bit enables changing the resolution of the output (including

output serialization factor) in bypass mode only. This bit does

not need to be set for 20-bit resolution output.

0: Output bit mapper disabled.

1: Output bit mapper enabled.

6

20B EN

R/W

0

This bit enables 20-bit output resolution which can be useful for

very high decimation settings so that quantization noise doesn't

impact the ADC performance.

0: 20-bit output resolution disabled.

1: 20-bit output resolution enabled.

5-3

BIT MAPPER RES

000

Sets the output resolution using the bit mapper. MAPPER EN bit

(D6) needs to be enabled when operating in bypass mode..

000: 18 bit

001: 16 bit

010: 14 bit

all others, n/a

2-0

0

R/W

0

Must write 0

Table 8-25. Register Settings for Output Bit Mapper vs Operating Mode

BYPASS/DECIMATION

Decimation Bypass

Real Decimation

OUTPUT RESOLUTION

MAPPER EN (D7)

BIT MAPPER RES (D5-D3)

Resolution Change

1

0

000: 18-bit

001: 16-bit

010: 14-bit

Resolution Change (default 18-bit)

Complex Decimation

Figure 8-56. Register 0x1E

7

0

6

0

5

0

4

3

2

1

0

LVDS DATA DEL

LVDS DCLK DEL

R/W-0

Table 8-26. Register 0x1E Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-4

3-2

0

Must write 0

LVDS DATA DEL

00

These bits adjust the output timing of the SLVDS output data.

00: no delay

01: Data advanced by 50 ps

10: Data delayed by 50 ps

11: Data delayed by 100 ps

1-0

LVDS DCLK DEL

R/W

00

These bits adjust the output timing of the SLVDS DCLK output.

00: no delay

01: DCLK advanced by 50 ps

10: DCLK delayed by 50 ps

11: DCLK delayed by 100 ps

52

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-57. Register 0x20/21/22

7

6

5

4

3

2

1

0

FCLK PAT [7:0]

FCLK PAT [15:8]

0

FCLK PAT [19:16]

R/W-0 R/W-0

R/W-0

Table 8-27. Register 0x20/21/22 Field Descriptions

Bit

Field

FCLK PAT [19:0]

Type

Reset

Description

7-0

R/W

0xFFC00

These bits can adjust the duty cycle of the FCLK. In decimation

bypass mode the FCLK pattern gets adjusted automatically for

the different output resolutions. Table 8-28 shows the proper

FCLK pattern values for 1-wire and 1/2-wire in real/complex

decimation.

Table 8-28. FCLK Pattern for different resolution based on interface

DECIMATION

OUTPUT RESOLUTION

2-WIRE

1-WIRE

0xFE000

0xFF000

0xFF800

0xFFC00

1/2-WIRE

14-bit

16-bit

18-bit

20-bit

14-bit

16-bit

18-bit

20-bit

REAL DECIMATION

Use Default

COMPLEX

DECIMATION

0xFFFFF

Submit Document Feedback

53

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-58. Register 0x24

7

0

6

0

5

4

3

2

1

0

CH AVG EN

R/W-0

DDC MUX

DIG BYP

R/W-0

DDC EN

R/W-0

Table 8-29. Register 0x24 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-6

5

0

Must write 0

CH AVG EN

Averages the output of ADC channel A and channel B together.

The DDC MUX has to be enabled and set to '11'. The

decimation filter needs to be enabled and set to bypass (fullrate

output) or decimation and DIG BYP set to 1.

0: Channel averaging feature disabled

1: Output of channel A and channel B are averaged: (A+B)/2.

4-3

DDC MUX

R/W

0

Configures DDC MUX in front of the decimation filter.

00: ADC channel A connected to DDC A; ADC Channel B

connected to DDC B

01: ADC channel A connected to DDC A and DDC B.

10: ADC channel B connected to DDC A and DDC B.

11: Output of ADC averaging block (see CH AVG EN) given to

DDC A and DDC B.

2

DIG BYP

This bit needs to be set to enable digital features block which

includes decimation and scrambling.

0: Digital feature block bypassed - lowest latency

1: Data path includes digital features

1

0

DDC EN

0

R/W

0

Enables internal decimation filter for both channels

0: DDC disabled.

1: DDC enabled.

Must write 0

To output

interface

DDC

N

CH

Average

DECIMATION

DIG BYP

DDC

DDC MUX

To output

interface

Figure 8-59. Register control for digital features

54

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-60. Register 0x25

7

6

5

4

3

2

0

1

0

DDC MUX EN

R/W-0

DECIMATION

R/W-0

REAL OUT

R/W-0

MIX PHASE

R/W-0

Table 8-30. Register 0x25 Field Descriptions

Bit

Field

DDC MUX EN

Type

Reset

Description

7

R/W

0

Enables the digital mux between ADCs and decimation filters.

This bit is required for DDC mux settings in register 0x24 (D4,

D3) to go into effect.

0: DDC mux disabled

1: DDC mux enabled

6-4

DECIMATION

R/W

000

Complex decimation setting. This applies to both channels.

000: Bypass mode (no decimation)

001: Decimation by 2

010: Decimation by 4

011: Decimation by 8

100: Decimation by 16

101: Decimation by 32

others: not used

3

REAL OUT

R/W

0

This bit selects real output decimation. This mode applies to

both channels. In this mode, the decimation filter is a low pass

filter and no complex mixing is performed to reduce power

consumption. For maximum power savings the NCO in this case

should be set to 0.

0: Complex decimation

1: Real decimation

2-1

0

R/W

0

Must write 0

MIX PHASE

This bit used to invert the NCO phase

0: NCO phase as is.

1: NCO phase inverted.

Figure 8-61. Register 0x26

7

6

5

4

3

2

1

0

MIX GAIN A

MIX RES A

R/W-0

FS/4 MIX A

R/W-0

MIX GAIN B

MIX RES B

R/W-0

FS/4 MIX B

R/W-0

Table 8-31. Register 0x26 Field Descriptions

Bit

Field

Type

Reset

Description

7-6

MIX GAIN A

R/W

00

This bit applies a 0, 3 or 6-dB digital gain to the output of digital

mixer to compensate for the mixing loss for channel A.

00: no digital gain added

01: 3-dB digital gain added (should be enabled with real

decimation)

10: 6-dB digital gain added (should be enabled with complex

decimation)

11: not used

5

4

MIX RES A

FS/4 MIX A

R/W

0

Toggling this bit resets the NCO phase of channel A and loads

the new NCO frequency. This bit does not self reset.

Enables FS/4 mixing for DDC A (complex decimation only).

0: FS/4 mixing disabled.

1: FS/4 mixing enabled.

3-2

MIX GAIN B

R/W

00

This bit applies a 0, 3 or 6-dB digital gain to the output of digital

mixer to compensate for the mixing loss for channel B.

00: no digital gain added

01: 3-dB digital gain added (should be enabled with real

decimation)

10: 6-dB digital gain added (should be enabled with complex

decimation)

11: not used

Submit Document Feedback

55

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Table 8-31. Register 0x26 Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

MIX RES B

R/W

0

Toggling this bit resets the NCO phase of channel B and loads

the new NCO frequency. This bit does not self reset.

0

FS/4 MIX B

R/W

0

Enables FS/4 mixing for DDC B (complex decimation only).

0: FS/4 mixing disabled.

1: FS/4 mixing enabled.

Figure 8-62. Register 0x27

7

0

6

0

5

0

4

3

2

1

0

OP ORDER A

R/W-0

Q-DEL A

R/W-0

FS/4 MIX PH A

R/W-0

Table 8-32. Register 0x27 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-5

4

0

Must write 0

OP ORDER A

Swaps the I and Q output order for channel A. See Table 8-33

for recommended settings. Only used with complex decimation.

Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Output order is swapped: Q[n], I[n]

3

Q-DEL A

R/W

0

This delays the Q-sample output of channel A by one. See Table

8-33 for recommended settings. Only used with complex

decimation. Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]

2

FS/4 MIX PH A

0

R/W

0

Inverts the mixer phase for channel A when using FS/4 mixer

0: Mixer phase is non-inverted

1: Mixer phase is inverted

1-0

Must write 0

Table 8-33. OP-ORDER and Q-DELAY Register Settings for Complex Decimation

SLVDS INTERFACE

OP-ORDER

Q-DELAY

2-wire

1

0

1

0

1

1-wire

1/2-wire

Figure 8-63. Register 0x2A/B/C/D

7

6

5

4

3

2

1

0

NCO A [7:0]

NCO A [15:8]

NCO A [23:16]

NCO A [31:24]

R/W-0

Table 8-34. Register 0x2A/2B/2C/2D Field Descriptions

Bit

7-0

Field

Type

Reset

Description

NCO A [31:0]

R/W

0

Sets the 32 bit NCO value for decimation filter channel A. The

NCO value is f_NCO× 2³²/F_S

In real decimation mode these registers are automatically set to

0.

56

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-64. Register 0x2E/2F/30

7

0

6

0

5

0

4

3

2

1

0

OP ORDER B

R/W-0

Q-DEL B

R/W-0

FS/4 MIX PH B

R/W-0

Table 8-35. Register 0x2E/2F/30 Field Descriptions

Bit

7-5

4

Field

Type

R/W

Reset

Description

0

Must write 0

OP ORDER B

Swaps the I and Q output order for channel B. See Table 8-33

for recommended settings. Only used with complex decimation.

Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Output order is swapped: Q[n], I[n]

3

Q-DEL B

R/W

0

This delays the Q-sample output of channel B by one. See Table

8-33 for recommended settings. Only used with complex

decimation. Set to 0 with real decimation.

0: Output order is I[n], Q[n]

1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]

2

FS/4 MIX PH B

0

R/W

0

Inverts the mixer phase for channel B when using FS/4 mixer

0: Mixer phase is non-inverted

1: Mixer phase is inverted

1-0

Must write 0

Figure 8-65. Register 0x31/32/33/34

7

6

5

4

3

2

1

0

NCO B [7:0]

NCO B [15:8]

NCO B [23:16]

NCO B [31:24]

R/W-0

Table 8-36. Register 0x31/32/33/34 Field Descriptions

Bit

Field

Type

Reset

Description

7-0

NCO B [31:0]

R/W

0

Sets the 32 bit NCO value for decimation filter channel B. The

NCO value is f_NCO× 2³²/F_S

In real decimation mode these registers are automatically set to

0.

Figure 8-66. Register 0x8F

7

0

6

0

5

0

4

3

2

0

1

0

FORMAT A

R/W-0

Table 8-37. Register 0x8F Field Descriptions

Bit

7-2

1

Field

Type

R/W

Reset

Description

0

Must write 0

FORMAT A

This bit sets the output data format for channel A.

0: 2s complement

1: Offset binary

0

R/W

0

Must write 0

Submit Document Feedback

57

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

Figure 8-67. Register 0x92

7

0

6

0

5

0

4

3

2

0

1

0

FORMAT B

R/W-0

Table 8-38. Register 0x92 Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7-2

1

0

Must write 0

FORMAT B

This bit sets the output data format for channel B.

0: 2s complement

1: Offset binary

0

R/W

0

Must write 0

58

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

9 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Typical Application

A spectrum analyzer is a typical frequency domain application for the ADC366x and its front end circuitry is very

similar to several other systems such as software defined radio (SDR), sonar, radar or communications. Some

applications require frequency coverage including DC or near DC (e.g. sonar) so it’s included in this example.

0.6V

10 uF

VREF

10 kꢀ

REFBUF

1.2V REF

Glitch Filter

33 ꢀ

Low Pass Filter

100 pF

10 ꢀ

NCO

180nH

AMP

AIN

ADC

N

33 ꢀ

DCLKIN

180nH

VCM

DCLK

FCLK

0.95V

FPGA

Dig I/F

33 ꢀ

C_VCM

DA0/1

DB0/1

Low Pass Filter

NCO

100 pF

10 ꢀ

180nH

N

AMP

BIN

CLK

ADC

33 ꢀ

180nH

Glitch Filter

Device Clock

Control

Figure 9-1. Typical configuration for a spectrum analyzer with DC support

9.1.1 Design Requirements

Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in

the 1st Nyquist zone to undersampling in higher Nyquist zones. If very low input frequency is supported then the

input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is

not needed then AC coupling and use of a balun may be more suitable.

The internal reference is used since DC precision is not needed. However the ADC AC performance is highly

dependent on the quality of the external clock source. If in-band interferers can be present then the ADC SFDR

performance will be a key care about as well. A higher ADC sampling rate is desirable in order to relax the

external anti-aliasing filter – an internal decimation filter can be used to reduce the digital output rate afterwards.

Table 9-1. Design key care-abouts

FEATURE

DESCRIPTION

Signal Bandwidth

Input Driver

DC to 20 MHz

Single ended to differential signal conversion and DC coupling

External clock with low jitter

Clock Source

Submit Document Feedback

59

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC366x input full-scale is 3.2Vpp. When factoring in ~ 1 dB for insertion loss

of the filter, then the amplifier needs to deliver close to 3.6Vpp. The amplifier distortion performance will degrade

with a larger output swing and considering the ADC common mode input voltage the amplifier may not be able to

deliver the full swing. The ADC366x provides an output common mode voltage of 0.95V and the THS4541 for

example can only swing within 250 mV of its negative supply. A unipolar 3.3 V amplifier power supply will thus

limit the maximum voltage swing to ~ 2.8Vpp. Hence if a larger output swing is required (factoring in filter

insertion loss) then a negative supply for the amplifier is needed in order to eliminate that limitation. Additionally

input voltage protection diodes may be needed to protect the ADC from over-voltage events.

Table 9-2. Output voltage swing of THS4541 vs power supply

DEVICE

MIN OUTPUT VOLTAGE

MAX SWING WITH 3.3 V/ 0 V SUPPLY

MAX SWING WITH 3.3 V/ -1.0 V SUPPLY

THS4541

VS- + 250 mV

2.8 Vpp

6.8 Vpp

9.1.2 Detailed Design Procedure

9.1.2.1 Input Signal Path

Depending on desired input signal frequency range the THS4551 and THS4541 provide very good low power

options to drive the ADC inputs. Table 9-3 provides a comparison between the THS4551 and THS4541 and the

power consumption vs usable frequency trade off.

Table 9-3. Fully Differential Amplifier Options

DEVICE

THS4561

THS4551

THS4541

CURRENT (IQ) PER CHANNEL

USABLE FREQUENCY RANGE

0.8 mA

1.4 mA

10 mA

< 3 MHz

< 10 MHz

< 70 MHz

The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the

low pass filter, the optimum load impedance for the amplifier should be taken into consideration as well. Between

the low pass filter and the ADC input the sampling glitch filter needs to added as well as shown in Section

8.3.1.2.1. In this example the DC - 30 MHz glitch filter is selected.

9.1.2.2 Sampling Clock

Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to

performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall

times (i.e. square wave vs sine wave). Table 9-4 provides an overview of the estimated SNR performance of the

ADC366x based on different amounts of jitter of the external clock source. The SNR is estimated based on

ADC366x thermal noise of 82 dBFS and input signal at -1dBFS.

Table 9-4. ADC SNR performance across vs input frequency for different amounts of external clock jitter

INPUT FREQUENCY

T_J,EXT= 100 fs

T_J,EXT= 250 fs

T_J,EXT= 500 fs

T_J,EXT= 1 ps

5 MHz

82.0

81.9

81.6

81.9

81.8

81.2

81.8

81.4

80.1

81.5

10 MHz

80.2

20 MHz

77.2

Termination of the clock input should be considered for long clock traces.

9.1.2.3 Voltage Reference

The ADC366x is configured to internal reference operation by applying 0.6 V to the REFBUF pin.

60

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

9.1.3 Application Curves

The following FFT plots show the performance of THS4541 driving the ADC3663 operated at 65 MSPS with a

full-scale input at -1 dBFS and input frequencies of 5, 10 and 20 MHz.

SNR = 81.0 dBFS, HD23 = 88 dBc, Non HD23 = 95 dBFS

SNR = 80.4 dBFS, HD23 = 91 dBc, Non HD23 = 83 dBFS

Figure 9-2. Single Tone FFT at F_IN= 5 MHz

Figure 9-3. Single Tone FFT at F_IN= 10 MHz

SNR = 77.2 dBFS, HD23 = 76 dBc, Non HD23 = 93 dBFS

A_IN= -10 dBFS, SNR = 81.0 dBFS, HD23 = 87 dBc,

Non HD23 = 90 dBFS

Figure 9-4. Single Tone FFT at F_IN= 20 MHz

Figure 9-5. Single Tone FFT at F_IN= 20 MHz

Submit Document Feedback

61

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

9.2 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in Figure 9-6.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied the internal bandgap

reference will power up and settle out in ~ 2ms.

2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.

3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

4. Begin programming using SPI interface.

AVDD

IOVDD

t₁

REFBUF

Ext VREF

CLK

t₃

t₂

RESET

SEN

Figure 9-6. Initialization of serial registers after power up

Table 9-5. Power-up timing

MIN

TYP

MAX

UNIT

t₁

t₂

t₄

t₅

Power-on delay: delay from power up to logic level of REFBUF pin

Delay from REFBUF pin logic level to RESET rising edge

RESET pulse width

2

100

ms

ns

us

1

Delay from RESET disable to SEN active

~ 200000

clock cycles

9.2.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

•

through a hardware reset or

by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)

high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

After hardware or software reset the wait time is also ~ 200000 clock cycles before the SPI registers can be

programmed.

62

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

10 Power Supply Recommendations

The ADC366x requires two different power-supplies. The AVDD rail provides power for the internal analog

circuits and the ADC itself while the IOVDD rail powers the digital interface and the internal digital circuits like

decimation filter or output interface mapper. Power sequencing is not required.

The AVDD power supply must be low noise in order to achieve data sheet performance. In applications

operating near DC, the 1/f noise contribution of the power supply needs to be considered as well. The ADC is

designed for very good PSRR which aides with the power supply filter design.

55

50

45

40

35

30

0.05 0.1

1

10

Frequency of Signal on AVDD (MHz)

100

D42_

Figure 10-1. Power supply rejection ratio (PSRR) vs frequency

There are two recommended power-supply architectures:

1. 1. Step down using high-efficiency switching converters, followed by a second stage of regulation using a low

noise LDO to provide switching noise reduction and improved voltage accuracy.

2. 2. Directly step down the final ADC supply voltage using high-efficiency switching converters. This approach

provides the best efficiency, but care must be taken to ensure switching noise is minimized to prevent

degraded ADC performance.

TI WEBENCH® Power Designer can be used to select and design the individual power-supply elements

needed: see the WEBENCH® Power Designer

Recommended switching regulators for the first stage include the TPS62821, and similar devices.

Recommended low dropout (LDO) linear regulators include the TPS7A4701, TPS7A90, LP5901, and similar

devices.

For the switch regulator only approach, the ripple filter must be designed with a notch frequency that aligns with

the switching ripple frequency of the DC/DC converter. Note the switching frequency reported from WEBENCH®

and design the EMI filter and capacitor combination to have the notch frequency centered as needed. Figure

10-2 and Figure 10-3 illustrate the two approaches.

AVDD and IOVDD supply voltages should not be shared in order to prevent digital switching noise from coupling

into the analog signal chain.

Submit Document Feedback

63

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

FB

2.1V

1.8V

DC/DC

Regulator

5V-12V

LDO

AVDD

10uF 10uF 0.1uF

47uF

GND

FB

IOVDD

10uF 10uF 0.1uF

FB = Ferrite bead filter

GND

Figure 10-2. Example: LDO Linear Regulator Approach

EMI FILTER

FB

1.8V

DC/DC

Regulator

5V-12V

AVDD

10uF 10uF 10uF

10uF 10uF 0.1uF

GND

FB

IOVDD

10uF 10uF 0.1uF

GND

Ripple filter notch frequency to match switching frequency of the DC/DC regulator

FB = Ferrite bead filter

Figure 10-3. Example Switcher-Only Approach

64

Submit Document Feedback

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

11 Layout

11.1 Layout Guidelines

There are several critical signals which require specific care during board design:

1. Analog input and clock signals

•

Traces should be as short as possible and vias should be avoided where possible to minimize impedance

discontinuities.

•

Traces should be routed using loosely coupled 100-Ω differential traces.

Differential trace lengths should be matched as close as possible to minimize phase imbalance and HD2

degradation.

2. Digital output interface

Traces should be routed using tightly coupled 100-Ω differential traces.

3. Voltage reference

•

The bypass capacitor should be placed as close to the device pins as possible and connected between

VREF and REFGND – on top layer avoiding vias.

•

Depending on configuration an additional bypass capacitor between REFBUF and REFGND may be

recommended and should also be placed as close to pins as possible on top layer.

4. Power and ground connections

•

Provide low resistance connection paths to all power and ground pins.

Use power and ground planes instead of traces.

Avoid narrow, isolated paths which increase the connection resistance.

Use a signal/ground/power circuit board stackup to maximize coupling between the ground and power

plane.

11.2 Layout Example

The following screen shot shows the top layer of the ADC366x/368x EVM.

•

Signal and clock inputs are routed as differential signals on the top layer avoiding vias.

SLVDS output interface lanes are routed differential and length matched

Bypass caps are close to the VREF pin on the top layer avoiding vias.

SLVDS routed tightly

coupled and length matched

Bypass caps on VREF close

to the pins and no vias

Clock routing

without vias

Analog inputs on

top layer (no vias)

Figure 11-1. Layout example: top layer of ADC366x/368x EVM

Submit Document Feedback

65

Product Folder Links: ADC3663

ADC3663

SBAS991 – FEBRUARY 2021

www.ti.com

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.2 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.5 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

66

Submit Document Feedback

Product Folder Links: ADC3663

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADC3663IRSBR

ADC3663IRSBT

WQFN

RSB

40

3000

250

330.0

180.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Feb-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADC3663IRSBR

ADC3663IRSBT

WQFN

RSB

40

3000

250

350.0

210.0

350.0

185.0

43.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RSB0040E

WQFN - 0.8 mm max height

S

C

A

L

E

2

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

5.1

4.9

B

A

PIN 1 INDEX AREA

5.1

4.9

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.6

(0.2) TYP

EXPOSED

11

20

THERMAL PAD

36X 0.4

10

21

2X

41

SYMM

3.6

3.15 0.1

1

30

0.25

0.15

40X

40

31

PIN 1 ID

(OPTIONAL)

0.1

C A B

SYMM

0.5

0.3

0.05

40X

4219096/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

40

31

40X (0.6)

40X (0.2)

1

30

36X (0.4)

41

SYMM

(4.8)

(1.325)

(

0.2) TYP

VIA

10

21

(R0.05)

TYP

11

20

(1.325)

(4.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219096/A 11/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RSB0040E

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785)

4X ( 1.37)

40

31

40X (0.6)

1

30

40X (0.2)

36X (0.4)

SYMM

(0.785)

(4.8)

41

(R0.05) TYP

10

21

METAL

TYP

20

11

SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 41

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219096/A 11/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADC3663IRSBT
厂家：	TEXAS INSTRUMENTS
描述：	ADC366x 16-Bit, 0.5-MSPS to 65-MSPS, low-noise, low power, dual-channel ADC
文件：	总75页 (文件大小：4932K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADC3663IRSBT [TI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E