ADS1014-Q1_技术文档

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

ADS101x-Q1 具有内部基准、振荡器和可编程比较器且兼容I²C 的

汽车类、低功耗3.3kSPS、12 位ADC

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

– 温度等级1：–40°C 至+125°C，T_A

• 功能安全型

ADS1013-Q1 、 ADS1014-Q1 和

ADS1015-Q1

(ADS101x-Q1) 是采用 VSSOP-10 和 UQFN-10 封

装、兼容 I²C 的 12 位低功耗精密模数转换器 (ADC)。

ADS101x-Q1 采用了低漂移电压基准和振荡器。

ADS1014-Q1 和 ADS1015-Q1 还包含一个可编程增益

放大器 (PGA) 和一个数字比较器。除了这些特性，这

些器件还具有宽工作电源电压范围，因而非常适用于功

率受限型和空间受限型传感器测量应用。

– 可帮助进行功能安全系统设计的文档

• 无噪声分辨率：12 位

• 宽电源电压范围：2.0V 至5.5V

• 低电流消耗：150μA

（连续转换模式）

• 可编程数据速率：

128SPS 至3.3kSPS

• 单周期稳定

• 内部低漂移电压基准

• 内部振荡器

• I²C 接口：四个引脚可选地址

• 器件系列：

ADS101x-Q1 可在数据速率高达每秒 3300 个样本

(SPS) 的情况下执行转换。PGA 可提供从 ±256mV 到

±6.144V 的输入范围，从而实现精准的大小信号测量。

ADS1015-Q1 具有一个输入多路复用器 (MUX)，可实

现双路差分输入或四路单端输入测量。在 ADS1014-

Q1 和 ADS1015-Q1 中使用数字比较器可进行欠压和

过压检测。

– ADS1013-Q1：1 个单端(SE) 或差分输入(DE)

– ADS1014-Q1：1 个单端或差分输入，具有比较

器和PGA

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

DGS（VSSOP，

10）

– ADS1015-Q1：4 个单端输入或2 个差分输入，

具有比较器和PGA

3.00mm × 3.00mm

ADS101x-Q1

NKS（UQFN，10） 1.60 mm × 2.00 mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

• 不具有处理功能的摄像头模块

• 汽车中心信息显示屏

• 汽车仪表组显示屏

器件信息

输入通道

器件型号

特性⁽¹⁾

—

• 通用电压和电流监测

ADS1013-Q1

1 个差分（1 个单

端）

ADS1014-Q1

ADS1015-Q1

1 个差分（1 个单

端）

PGA、比较器

2 个差分（4 个单

端）

(1) 有关详细信息，请参阅Device Comparison Table。

VDD

Comparator

ALERT/

RDY

ALERT/

RDY

Voltage

Reference

Voltage

Reference

Voltage

Reference

AIN0

AIN1

ADDR

AIN0

AIN1

12-Bit

ADC

12-Bit

ADC

12-Bit

ADC

AIN0

AIN1

I²C

Interface

I²C

Interface

I²C

Interface

PGA

MUX

SCL

SDA

SCL

SDA

SCL

SDA

AIN2

AIN3

Oscillator

GND

Oscillator

ADS1013-Q1

ADS1014-Q1

ADS1015-Q1

GND

简化的方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................15

7.5 Programming............................................................ 16

7.6 Register Map.............................................................21

8 Application and Implementation..................................25

8.1 Application Information............................................. 25

8.2 Typical Application.................................................... 30

8.3 Power Supply Recommendations.............................34

8.4 Layout....................................................................... 35

9 Device and Documentation Support............................37

9.1 Documentation Support............................................ 37

9.2 接收文档更新通知..................................................... 37

9.3 支持资源....................................................................37

9.4 Trademarks...............................................................37

9.5 静电放电警告............................................................ 37

9.6 术语表....................................................................... 37

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................6

6.5 Electrical Characteristics.............................................6

6.6 Timing Requirements: I²C...........................................7

6.7 Timing Diagram...........................................................7

6.8 Typical Characteristics................................................8

7 Detailed Description........................................................9

7.1 Overview.....................................................................9

7.2 Functional Block Diagrams......................................... 9

7.3 Feature Description...................................................10

Information.................................................................... 37

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (January 2018) to Revision D (March 2023)

Page

• 将提到 I²C 的旧术语实例通篇更改为控制器和目标.......................................................................................... 1

• 向特性部分添加了功能安全型要点和器件系列信息，将ESD 分类信息从特性部分移至ESD 等级表............1

• 更改了应用部分中的应用...................................................................................................................................1

• 添加了NKS 封装和器件信息表并删除了说明部分的最后一段..........................................................................1

• Added NKS package to Pin Configuration and Functions section and changed Pin Functions table................ 4

• Added ESD classification levels and NKS package to ESD Ratings table.........................................................5

• Added NKS package to Thermal Information table............................................................................................ 6

• Changed V_IHmaximum value to 5.5 V in Electrical Characteristics table...........................................................6

• Added additional information to last paragraph in Multiplexer section..............................................................10

• Added additional information to Voltage Reference section............................................................................. 12

• Moved 图7-7 from Conversion Ready Pin section to Digital Comparator section........................................... 13

• Changed bit setting notation from hexadecimal to binary where beneficial for clarity throughout Register Map

section.............................................................................................................................................................. 21

• Added dedicated Config Register tables for ADS1013-Q1, ADS1014-Q1, and ADS1015-Q1 and changed bit

descriptions in Config Register Field Descriptions table in Config Register section.........................................22

• Changed first paragraph in Lo_threh and Hi_thresh Registers section............................................................24

• Changed Unused Inputs and Outputs section..................................................................................................26

Changes from Revision B (December 2016) to Revision C (January 2018)

Page

• Changed Digital input voltage max value from VDD + 0.3 V to 5.5 V in Absolute Maximum Ratings table....... 5

• Added "over temperature" to Offset drift parameter for clarity............................................................................6

• Added Long-term offset drift parameter in Electrical Characteristics table.........................................................6

• Added "over temperature" to Gain drift parameter for clarity..............................................................................6

• Added Long-term gain drift parameter in Electrical Characteristics table...........................................................6

• Added Output Data Rate and Conversion Time section for clarity....................................................................12

• Changed Figure 13, ALERT Pin Timing Diagram for clarity............................................................................. 14

• Changed Figure 24, Typical Connections of the ADS1015-Q1 for clarity.........................................................25

2

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Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

• Changed resistor values in Figure 28, Basic Hardware Configuration, from 10 Ωto 10 kΩ..........................29

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Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

Device Comparison Table

MAXIMUM SAMPLE

RATE

INPUT CHANNELS

Differential

(Single-Ended)

RESOLUTION

SPECIAL

FEATURES

DEVICE

(Bits)

PGA

INTERFACE

(SPS)

ADS1015-Q1

ADS1014-Q1

ADS1013-Q1

ADS1115-Q1

ADS1114-Q1

ADS1113-Q1

ADS1018-Q1

ADS1118-Q1

12

16

12

16

3300

860

2 (4)

1 (1)

2 (4)

1 (1)

2 (4)

Yes

No

I²C

SPI

Comparator

None

Yes

No

Comparator

None

860

3300

860

Yes

Temperature sensor

5 Pin Configuration and Functions

ADDR

1

9

SDA

ADDR

1

2

3

4

5

10

9

SCL

SDA

VDD

AIN3

AIN2

ALERT/RDY

GND

ALERT/RDY

GND

2

3

8

7

VDD

AIN3

8

AIN0

7

AIN1

6

AIN0

4

6

AIN2

Not to scale

图5-2. DGS Package,

图5-1. NKS Package,

10-Pin VSSOP (Top View)

10-Pin UQFN (Top View)

表5-1. Pin Functions

NAME

ADDR

AIN0

AIN1

AIN2

AIN3

ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

TYPE

DESCRIPTION⁽¹⁾

1

4

1

4

1

4

5

6

7

Digital input I²C target address select

Analog input Analog input 0

5

Analog input Analog input 1

Analog input Analog input 2 (ADS1015-Q1 only)

Analog input Analog input 3 (ADS1015-Q1 only)

—

Comparator output or conversion ready (ADS1014-Q1 and ADS1015-Q1 only)

Open-drain output. Connect to VDD using a pullup resistor.

ALERT/RDY

2

3

Digital output

—

GND

NC

3

2, 6, 7

10

3

6, 7

10

9

Analog

Ground

No connect. Leave pin floating or connect to GND.

—

10

9

—

SCL

SDA

VDD

Digital input Serial clock input. Connect to VDD using a pullup resistor.

9

Digital I/O

Analog

Serial data input and output. Connect to VDD using a pullup resistor.

8

Power supply. Connect a 0.1-μF, power-supply decoupling capacitor to GND.

(1) See the Unused Inputs and Outputs section for unused pin connections.

4

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English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

7

UNIT

V

Power-supply voltage

Analog input voltage

Digital input voltage

Input current, continuous

VDD to GND

AIN0, AIN1, AIN2, AIN3

SDA, SCL, ADDR, ALERT/RDY

Any pin except power supply pins

Operating ambient, T_A

Junction, T_J

VDD + 0.3

5.5

V

GND –0.3

–10

V

10

mA

125

–40

Temperature

150

°C

–40

Storage, T_stg

150

–60

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

HBM ESD classification level 2

±2000

Electrostatic

discharge

Corner pins

(DGS package: Pins 1, 5, 6, and 10)

(NKS package: Pins 1, 4, 5, 6, 9, and 10)

V_(ESD)

V

Charged-device model (CDM),

per AEC Q100-011

CDM ESD classification level C4B

±750

±500

All other pins

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

POWER SUPPLY

Power supply (VDD to GND)

ANALOG INPUTS⁽¹⁾

2

5.5

V

Full-scale input voltage range⁽²⁾(V_IN= V_(AINP)–V_(AINN)

)

FSR

±0.256

GND

±6.144

VDD

V

V_(AINx)

Absolute input voltage

DIGITAL INPUTS

V_DIG

Digital input voltage

GND

5.5

V

TEMPERATURE

T_A

Operating ambient temperature

125

°C

–40

(1) AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs.

(2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of

the device. See 表7-1 for more information.

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Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

UNIT

6.4 Thermal Information

DGS (VSSOP)

10 PINS

170.9

61.0

NKS (UQFN)

10 PINS

126.3

52.0

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

91.2

60.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

8.5

1.1

ψ_JT

89.8

60.5

ψ_JB

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

6.5 Electrical Characteristics

at VDD = 3.3 V, data rate = 128 SPS, and full-scale input-voltage range (FSR) = ±2.048 V (unless otherwise noted);

maximum and minimum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG INPUT

FSR = ±6.144 V⁽¹⁾

10

6

FSR = ±4.096 V⁽¹⁾, FSR = ±2.048 V

Common-mode input impedance

Differential input impedance

MΩ

FSR = ±1.024 V

3

FSR = ±0.512 V, FSR = ±0.256 V

FSR = ±6.144 V⁽¹⁾

100

22

FSR = ±4.096 V⁽¹⁾

15

MΩ

FSR = ±2.048 V

4.9

2.4

710

FSR = ±1.024 V

FSR = ±0.512 V, ±0.256 V

kΩ

SYSTEM PERFORMANCE

Resolution (no missing codes)

Data rate

12

Bits

DR

INL

128, 250, 490, 920, 1600, 2400, 3300

SPS

Data rate variation

Integral nonlinearity

All data rates

10%

–10%

DR = 128 SPS, FSR = ±2.048 V⁽²⁾

FSR = ±2.048 V, differential inputs

FSR = ±2.048 V, single-ended inputs

FSR = ±2.048 V

0.5

LSB

-0.5

0

±0.25

0.005

±1

Offset error

Offset drift over temperature

Long-term offset drift

Offset channel match

Gain error⁽³⁾

LSB/°C

LSB

FSR = ±2.048 V, T_A= 125°C, 1000 hrs

Match between any two inputs

FSR = ±2.048 V, T_A= 25°C

FSR = ±0.256 V

0.25

0.05%

7

LSB

0.25%

Gain drift over temperature⁽³⁾

FSR = ±2.048 V

5

40 ppm/°C

%

FSR = ±6.144 V⁽¹⁾

5

Long-term gain drift

Gain match⁽³⁾

FSR = ±2.048 V, T_A= 125°C, 1000 hrs

Match between any two gains

Match between any two inputs

±0.05

0.02%

0.05%

0.1%

Gain channel match

0.1%

DIGITAL INPUT/OUTPUT

V_IH

V_IL

High-level input voltage

0.7 VDD

GND

5.5

V

Low-level input voltage

0.3 VDD

6

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English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

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6.5 Electrical Characteristics (continued)

at VDD = 3.3 V, data rate = 128 SPS, and full-scale input-voltage range (FSR) = ±2.048 V (unless otherwise noted);

maximum and minimum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C

PARAMETER

Low-level output voltage

Input leakage current

TEST CONDITIONS

MIN

GND

–10

TYP

MAX UNIT

V_OL

I_OL= 3 mA

0.15

0.4

10

V

GND < V_DIG< VDD

μA

POWER-SUPPLY

T_A= 25°C

0.5

2

5

Power-down

Operating

I_VDD

Supply current

μA

150

200

300

VDD = 5.0 V

VDD = 3.3 V

VDD = 2.0 V

0.9

0.5

0.3

P_D

Power dissipation

mW

(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of

the device. See 表7-1 for more information.

(2) Best-fit INL; covers 99% of full-scale.

(3) Includes all errors from onboard PGA and voltage reference.

6.6 Timing Requirements: I²C

over operating ambient temperature range and VDD = 2.0 V to 5.5 V (unless otherwise noted)

FAST MODE

HIGH-SPEED MODE

MIN

MAX

MIN

MAX

UNIT

f_SCL

t_BUF

SCL clock frequency

0.01

0.4

0.01

3.4

MHz

Bus free time between START and STOP

condition

600

160

ns

Hold time after repeated START condition.

After this period, the first clock is generated.

t_HDSTA

t_SUSTA

t_SUSTO

t_HDDAT

t_SUDAT

t_LOW

t_HIGH

t_F

Setup time for a repeated START condition

Setup time for STOP condition

Data hold time

600

0

160

0

ns

Data setup time

100

1300

600

10

Low period of the SCL clock pin

High period for the SCL clock pin

Rise time for both SDA and SCL signals⁽¹⁾

Fall time for both SDA and SCL signals⁽¹⁾

160

60

300

160

t_R

(1) For high-speed mode maximum values, the capacitive load on the bus line must not exceed 400 pF.

6.7 Timing Diagram

t_LOW

t_R

t_F

t_HDSTA

SCL

t_SUSTO

t_HDSTA

t_HIGHt_SUSTA

t_HDDAT

t_SUDAT

SDA

t_BUF

P

S

P

图6-1. I²C Interface Timing

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Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

6.8 Typical Characteristics

at T_A= 25°C, VDD = 3.3 V, FSR = ±2.048 V, DR = 128 SPS (unless otherwise noted)

300

250

200

150

100

50

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

VDD = 5 V

VDD = 3.3 V

VDD = 2 V

VDD = 3.3 V

VDD = 2 V

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

图6-2. Operating Current vs Temperature

图6-3. Power-Down Current vs Temperature

150

60

50

40

30

20

10

0

FSR = 4ꢀ0ꢁ6 V

FSR = 2ꢀ048 V

FSR = 1ꢀ024 V

FSR = 0ꢀ512 V

100

50

VDD = 5 V

VDD = 2 V

0

-50

VDD = 4 V

-100

-150

-200

-250

-300

VDD = 3 V

VDD = 2 V

VDD = 5 V

-10

-20

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

图6-4. Single-Ended Offset Error vs Temperature

图6-5. Differential Offset Error vs Temperature

0.05

0.04

FSR = 0.256 ꢀ

0.03

FSR = 0.512 ꢀ

0.02

0.01

0

FSR = 1.024 ꢀ, 2.048 ꢀ,

4.096 ꢀ, and 6.144 ꢀ

-0.01

-0.02

-0.03

-0.04

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

图6-6. Gain Error vs Temperature

8

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Product Folder Links: ADS1013-Q1 ADS1014-Q1 ADS1015-Q1

English Data Sheet: SBAS511

ADS1013-Q1, ADS1014-Q1, ADS1015-Q1

ZHCSHA5D –JULY 2010 –REVISED MARCH 2023

www.ti.com.cn

7 Detailed Description

7.1 Overview

The ADS101x-Q1 are very small, low-power, noise-free, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters

(ADCs). The ADS101x-Q1 consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator and

an I²C interface. The ADS1014-Q1 and ADS1015-Q1 also integrate a programmable gain amplifier (PGA) and a

programmable digital comparator. 图7-1, 图7-2, and 图7-3 show the functional block diagrams of ADS1015-Q1,

ADS1014-Q1, and ADS1013-Q1, respectively.

The ADS101x-Q1 ADC core measures a differential signal, V_IN, that is the difference of V_(AINP)and V_(AINN). The

converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This

architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the

internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a

code proportional to the input voltage.

The ADS101x-Q1 have two available conversion modes: single-shot and continuous-conversion. In single-shot

mode, the ADC performs one conversion of the input signal upon request, stores the conversion value to an

internal conversion register, and then enters a power-down state. This mode is intended to provide significant

power savings in systems that only require periodic conversions or when there are long idle periods between

conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as

soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed

data rate. Data can be read at any time and always reflect the most recent completed conversion.

7.2 Functional Block Diagrams

VDD

Comparator

ADS1015-Q1

Voltage

Reference

ALERT/RDY

ADDR

MUX

AIN0

AIN1

I²C

Interface

12-Bit

ADC

PGA

SCL

SDA

AIN2

AIN3

Oscillator

GND

图7-1. ADS1015-Q1 Block Diagram

VDD

ADS1014-Q1

ADS1013-Q1

Voltage

Comparator

Voltage

Reference

ALERT/RDY

ADDR

Reference

ADDR

AIN0

AIN1

AIN0

AIN1

I²C

Interface

I²C

Interface

12-Bit

ADC

12-Bit

ADC

PGA

SCL

SDA

SCL

SDA

Oscillator

GND

图7-2. ADS1014-Q1 Block Diagram

图7-3. ADS1013-Q1 Block Diagram

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7.3 Feature Description

7.3.1 Multiplexer

The ADS1015-Q1 contains an input multiplexer (MUX), as shown in 图 7-4. Either four single-ended or two

differential signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The

multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the

negative input of the ADC is internally connected to GND by a switch within the multiplexer.

ADS1015-Q1

VDD

AIN0

VDD

GND

VDD

AIN

P

N

AIN1

AIN2

AIN

GND

VDD

GND

AIN3

GND

图7-4. Input Multiplexer

The ADS1013-Q1 and ADS1014-Q1 do not have an input multiplexer and can measure either one differential

signal or one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In

subsequent sections of this data sheet, AIN_Prefers to AIN0 and AIN_Nrefers to AIN1 for the ADS1013-Q1 and

ADS1014-Q1.

Electrostatic discharge (ESD) diodes connected to VDD and GND protect the ADS101x-Q1 analog inputs. Keep

the absolute voltage of any input within the range shown in 方程式1 to prevent the ESD diodes from turning on.

GND –0.3 V < V_(AINX)< VDD + 0.3 V

(1)

If the voltages on the input pins can potentially violate these conditions, use external Schottky diodes and series

resistors to limit the input current to safe values (see the Absolute Maximum Ratings table). Overdriving an input

on the ADS1015-Q1 can affect conversions taking place on other inputs. If overdriving an input is possible,

clamp the signal with external Schottky diodes.

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7.3.2 Analog Inputs

The ADS101x-Q1 use a switched-capacitor input stage where capacitors are continuously charged and then

discharged to measure the voltage between AIN_Pand AIN_N. The frequency at which the input signal is sampled

is called the sampling frequency or the modulator frequency (f_MOD). The ADS101x-Q1 has a 1-MHz internal

oscillator that is further divided by a factor of 4 to generate f_MODat 250 kHz. The capacitors used in this input

stage are small, and to external circuitry, the average loading appears resistive. 图 7-5 shows this structure. The

capacitor values set the resistance and switching rate. 图 7-6 shows the timing for the switches in 图 7-5. During

the sampling phase, switches S₁are closed. This event charges C_A1to V_(AINP), C_A2to V_(AINN), and C_Bto

(V_(AINP)– V_(AINN)). During the discharge phase, S₁is first opened and then S₂is closed. Both C_A1and C_A2then

discharge to approximately 0.7 V and C_Bdischarges to 0 V. This charging draws a very small transient current

from the source driving the ADS101x-Q1 analog inputs. The average value of this current can be used to

calculate the effective impedance (Z_eff), where Z_eff= V_IN/ I_AVERAGE

.

0.7 V

C

A1

Z

CM

Equivalent

Circuit

0.7 V

AIN

P

S₂

AIN

S

P

1

C

B

DIFF

S

1

N

AIN

N

Z

CM

f

= 250 kHz

MOD

C

A2

0.7 V

图7-5. Simplified Analog Input Circuit

t_SAMPLE

ON

S₁

OFF

ON

S₂

OFF

图7-6. S₁and S₂Switch Timing

The common-mode input impedance is measured by applying a common-mode signal to the shorted AIN_Pand

AIN_Ninputs and measuring the average current consumed by each pin. The common-mode input impedance

changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In 图 7-5,

the common-mode input impedance is Z_CM

.

The differential input impedance is measured by applying a differential signal to AIN_Pand AIN_Ninputs where one

input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and

scales with the full-scale range. In 图7-5, the differential input impedance is Z_DIFF

.

Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance,

the ADS101x-Q1 input impedance can affect the measurement accuracy. For sources with high-output

impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain

errors. Consider all of these factors in high-accuracy applications.

The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most

applications, this input impedance drift is negligible, and can be ignored.

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7.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the ADS1014-Q1 and ADS1015-

Q1. The full-scale range is configured by bits PGA[2:0] in the Config register and can be set to ±6.144 V, ±4.096

V, ±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V. 表 7-1 shows the FSR together with the corresponding LSB size.

方程式2 shows how to calculate the LSB size from the selected full-scale range.

LSB = FSR / 2¹²

(2)

表7-1. Full-Scale Range and Corresponding LSB

Size

FSR

LSB SIZE

3 mV

±6.144 V⁽¹⁾

±4.096 V⁽¹⁾

±2.048 V

±1.024 V

±0.512 V

±0.256 V

2 mV

1 mV

0.5 mV

0.25 mV

0.125 mV

(1) This parameter expresses the full-scale range of the ADC

scaling. Do not apply more than VDD + 0.3 V to the analog

inputs of the device.

The FSR of the ADS1013-Q1 is fixed at ±2.048 V.

Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings.

If a VDD supply voltage greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to extend

up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range), a full-

scale ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only differential

signals up to V_IN= ±3.3 V can be measured. The code range that represents voltages |V_IN| > 3.3 V is not used in

this case.

7.3.4 Voltage Reference

The ADS101x-Q1 have an integrated voltage reference. An external reference cannot be used with these

devices.

The ADS101x-Q1 does not use a traditional band-gap reference to generate the internal voltage reference. For

that reason, the reference does not have an actual specified voltage value. Instead of using the reference

voltage value and the gain setting to derive the full-scale range of the ADC, use the FSR values provided in 表

7-1 directly.

Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included

in the gain error and gain drift specifications in the Electrical Characteristics table.

7.3.5 Oscillator

The ADS101x-Q1 have an integrated oscillator running at 1 MHz. No external clock can be applied to operate

these devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally

with the oscillator frequency.

7.3.6 Output Data Rate and Conversion Time

The ADS101x-Q1 offer programmable output data rates. Use the DR[2:0] bits in the Config register to select

output data rates of 128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS, 2400 SPS, or 3300 SPS.

Conversions in the ADS101x-Q1 settle within a single cycle; thus, the conversion time is equal to 1 / DR.

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7.3.7 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only)

The ADS1015-Q1 and ADS1014-Q1 feature a programmable digital comparator that can issue an alert on the

ALERT/RDY pin. The COMP_MODE bit in the Config register configures the comparator as either a traditional

comparator or a window comparator. In traditional comparator mode, the ALERT/RDY pin asserts (active low by

default) when conversion data exceeds the limit set in the high-threshold register (Hi_thresh). The comparator

then deasserts only when the conversion data falls below the limit set in the low-threshold register (Lo_thresh).

In window comparator mode, the ALERT/RDY pin asserts when the conversion data exceed the Hi_thresh

register or fall below the Lo_thresh register value.

In either window or traditional comparator mode, the comparator can be configured to latch after being asserted

by the COMP_LAT bit in the Config register. This setting causes the assertion to remain even if the input signal

is not beyond the bounds of the threshold registers. This latched assertion can only be cleared by issuing an

SMBus alert response or by reading the Conversion register. The ALERT/RDY pin can be configured as active

high or active low by the COMP_POL bit in the Config register. Operational diagrams for both the comparator

modes are shown in 图7-7.

The comparator can also be configured to activate the ALERT/RDY pin only after a set number of successive

readings exceed the threshold values set in the threshold registers (Hi_thresh and Lo_thresh). The

COMP_QUE[1:0] bits in the Config register configures the comparator to wait for one, two, or four readings

beyond the threshold before activating the ALERT/RDY pin. The COMP_QUE[1:0] bits can also disable the

comparator function, and put the ALERT/RDY pin into a high state.

TH_H

TH_L

TH_H

TH_L

Input Signal

Time

Latching

Comparator

Output

Successful

SMBus Alert

Response

Latching

Comparator

Output

Successful

SMBus Alert

Response

Successful

SMBus Alert

Response

Time

Non-Latching

Comparator

Output

Non-Latching

Comparator

Output

Time

TRADITIONAL COMPARATOR MODE

WINDOW COMPARATOR MODE

图7-7. ALERT Pin Timing Diagram

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7.3.8 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only)

The ALERT/RDY pin can also be configured as a conversion ready pin. Set the most-significant bit of the

Hi_thresh register to 1b and the most-significant bit of Lo_thresh register to 0b to enable the pin as a conversion-

ready pin. The COMP_POL bit continues to function as expected. Set the COMP_QUE[1:0] bits to any 2-bit

value other than 11b to keep the ALERT/RDY pin enabled, and allow the conversion-ready signal to appear at

the ALERT/RDY pin output. The COMP_MODE and COMP_LAT bits no longer control any function. When

configured as a conversion-ready pin, ALERT/RDY continues to require a pullup resistor. The ADS101x-Q1

provide an approximately 8-µs, conversion-ready pulse on the ALERT/RDY pin at the end of each conversion in

continuous-conversion mode, as shown in 图 7-8. In single-shot mode, the ALERT/RDY pin asserts low at the

end of a conversion if the COMP_POL bit is set to 0b.

ADS1014/5-Q1

Status

Converting

Conversion Ready

Converting

Conversion Ready

8 µs

ALERT/RDY

(active high)

图7-8. Conversion Ready Pulse in Continuous-Conversion Mode

7.3.9 SMbus Alert Response

In latching comparator mode (COMP_LAT = 1b), the ALERT/RDY pin asserts when the comparator detects a

conversion that exceeds the upper or lower threshold value. This assertion is latched and can be cleared only by

reading conversion data, or by issuing a successful SMBus alert response and reading the asserting device I²C

address. If conversion data exceed the upper or lower threshold values after being cleared, the pin reasserts.

This assertion does not affect conversions that are already in progress. The ALERT/RDY pin is an open-drain

output. This architecture allows several devices to share the same interface bus. When disabled, the pin holds a

high state so that the pin does not interfere with other devices on the same bus line.

When the controller senses that the ALERT/RDY pin has latched, the controller issues an SMBus alert command

(00011001b) to the I²C bus. Any ADS1014-Q1 and ADS1015-Q1 data converters on the I²C bus with the

ALERT/RDY pins asserted respond to the command with the target address. If more than one ADS101x-Q1 on

the I²C bus assert the latched ALERT/RDY pin, arbitration during the address response portion of the SMBus

alert determines which device clears assertion. The device with the lowest I²C address always wins arbitration. If

a device loses arbitration, the device does not clear the comparator output pin assertion. The controller then

repeats the SMBus alert response until all devices have the respective assertions cleared. In window comparator

mode, the SMBus alert status bit indicates a 1b if signals exceed the high threshold, and a 0b if signals exceed

the low threshold.

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7.4 Device Functional Modes

7.4.1 Reset and Power-Up

The ADS101x-Q1 reset on power-up and set all the bits in the Config register to the respective default settings.

The ADS101x-Q1 enter a power-down state after completion of the reset process. The device interface and

digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS101x-

Q1 relieves systems with tight power-supply requirements from encountering a surge during power-up.

The ADS101x-Q1 respond to the I²C general-call reset command. When the ADS101x-Q1 receive a general-call

reset command (06h), an internal reset is performed as if the device is powered-up.

7.4.2 Operating Modes

The ADS101x-Q1 operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the

Config register selects the respective operating mode.

7.4.2.1 Single-Shot Mode

When the MODE bit in the Config register is set to 1b, the ADS101x-Q1 enter a power-down state, and operate

in single-shot mode. This power-down state is the default state for the ADS101x-Q1 when power is first applied.

Although powered down, the devices still respond to commands. The ADS101x-Q1 remain in this power-down

state until a 1b is written to the operational status (OS) bit in the Config register. When the OS bit is asserted, the

device powers up in approximately 25 μs, resets the OS bit to 0b, and starts a single conversion. When

conversion data are ready for retrieval, the device powers down again. Writing a 1b to the OS bit while a

conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0b to the MODE bit in the

Config register.

7.4.2.2 Continuous-Conversion Mode

In continuous-conversion mode (MODE bit set to 0b), the ADS101x-Q1 perform conversions continuously. When

a conversion is complete, the ADS101x-Q1 place the result in the Conversion register and immediately begin

another conversion. When writing new configuration settings, the currently ongoing conversion completes with

the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start.

To switch to single-shot conversion mode, write a 1b to the MODE bit in the configuration register or reset the

device.

7.4.3 Duty Cycling For Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more

samples of the internal modulator are averaged to yield one conversion result. In applications where power

consumption is critical, the improved noise performance at low data rates is not always required. For these

applications, the ADS101x-Q1 support duty cycling that yield significant power savings by periodically requesting

high data rate readings at an effectively lower data rate. For example, an ADS101x-Q1 in power-down state with

a data rate set to 3300 SPS can be operated by a microcontroller that instructs a single-shot conversion every

7.8 ms (128 SPS). A conversion at 3300 SPS only requires approximately 0.3 ms, so the ADS101x-Q1 enter

power-down state for the remaining 7.5 ms. In this configuration, the ADS101x-Q1 consume approximately

1/25th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely

arbitrary and is defined by the controller. The ADS101x-Q1 offer lower data rates that do not implement duty

cycling and also offer improved noise performance if required.

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7.5 Programming

7.5.1 I²C Interface

The ADS101x-Q1 communicate through an I²C interface. I²C is a two-wire open-drain interface that supports

multiple devices and controllers on a single bus. Devices on the I²C bus only drive the bus lines low by

connecting them to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by

pullup resistors, so the bus wires are always high when no device is driving them low. As a result of this

configuration, two devices cannot conflict. If two devices drive the bus simultaneously, there is no driver

contention.

Communication on the I²C bus always takes place between two devices, one acting as the controller and the

other as the target. Both the controller and target can read and write, but the target can only do so under the

direction of the controller. Some I²C devices can act as a controller or target, but the ADS101x-Q1 can only act

as a target device.

An I²C bus consists of two lines: SDA and SCL. SDA carries data; SCL provides the clock. All data are

transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, drive the SDA line to the

appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). After

the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the

receiver shift register. If the I²C bus is held idle for more than 25 ms, the bus times out.

The I²C bus is bidirectional; that is, the SDA line is used for both transmitting and receiving data. When the

controller reads from a target, the target drives the data line; when the controller writes to a target, the controller

drives the data line. The controller always drives the clock line. The ADS101x-Q1 cannot act as a controller, and

therefore can never drive SCL.

Most of the time the bus is idle; no communication occurs, and both lines are high. When communication takes

place, the bus is active. Only a controller device can start a communication and initiate a START condition on the

bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes

state while the clock line is high, this change is either a START condition or a STOP condition. A START

condition occurs when the clock line is high, and the data line goes from high to low. A STOP condition occurs

when the clock line is high, and the data line goes from low to high.

After the controller issues a START condition, the controller sends a byte that indicates with which target device

to communicate with. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address

that the device responds to. The controller sends an address in the address byte, together with a bit that

indicates whether the controller wishes to read from or write to the target device.

Every byte (address and data) transmitted on the I²C bus is acknowledged with an acknowledge bit. When the

controller finishes sending a byte (eight data bits) to a target, the controller stops driving SDA and waits for the

target to acknowledge the byte. The target acknowledges the byte by pulling SDA low. The controller then sends

a clock pulse to clock the acknowledge bit. Similarly, when the controller completes reading a byte, the controller

pulls SDA low to acknowledge this completion to the target. The controller then sends a clock pulse to clock the

bit. The controller always drives the clock line.

If a device is not present on the bus, and the controller attempts to address the device, the controller receives a

not-acknowledge because no device is present at that address to pull the line low. A not-acknowledge is

performed by simply leaving SDA high during an acknowledge cycle.

When the controller has finished communicating with a target, the controller can issue a STOP condition. When

a STOP condition is issued, the bus becomes idle again. The controller can also issue another START condition.

When a START condition is issued while the bus is active, this condition is called a repeated start condition.

The Timing Requirements section provides a timing diagram for the ADS101x-Q1 I²C communication.

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7.5.1.1 I²C Address Selection

The ADS101x-Q1 have one address pin, ADDR, that configures the I²C address of the device. This pin can be

connected to GND, VDD, SDA, or SCL, allowing for four different addresses to be selected with one pin, as

shown in 表 7-2. The state of address pin ADDR is sampled continuously. Use the GND, VDD, and SCL

addresses first. If SDA is used as the device address, hold the SDA line low for at least 100 ns after the SCL line

goes low to make sure the device decodes the address correctly during I²C communication.

表7-2. ADDR Pin Connection and Corresponding Target Address

ADDR PIN CONNECTION

TARGET ADDRESS

GND

VDD

SDA

SCL

1001000b

1001001b

1001010b

1001011b

7.5.1.2 I²C General Call

The ADS101x-Q1 respond to the I²C general call address (0000000b) if the eighth bit is 0b. The devices

acknowledge the general call address and respond to commands in the second byte. If the second byte is

00000110b (06h), the ADS101x-Q1 reset the internal registers and enter a power-down state.

7.5.1.3 I²C Speed Modes

The I²C bus operates at one of three speeds. Standard mode allows a clock frequency of up to 100 kHz; fast

mode permits a clock frequency of up to 400 kHz; and high-speed mode (also called Hs mode) allows a clock

frequency of up to 3.4 MHz. The ADS101x-Q1 are fully compatible with all three modes.

No special action is required to use the ADS101x-Q1 in standard or fast mode, but high-speed mode must be

activated. To activate high-speed mode, send a special address byte of 00001xxxb following the START

condition, where xxx are bits unique to the Hs-capable controller. This byte is called the Hs controller code, and

is different from normal address bytes; the eighth bit does not indicate read/write status. The ADS101x-Q1 do

not acknowledge this byte; the I²C specification prohibits acknowledgment of the Hs controller code. Upon

receiving a controller code, the ADS101x-Q1 switch on Hs mode filters, and communicate at up to 3.4 MHz. The

ADS101x-Q1 switch out of Hs mode with the next STOP condition.

For more information on high-speed mode, consult the I²C specification.

7.5.2 Target Mode Operations

The ADS101x-Q1 act as target receivers or target transmitters. The ADS101x-Q1 cannot drive the SCL line as

target devices.

7.5.2.1 Receive Mode

In target receive mode, the first byte transmitted from the controller to the target consists of the 7-bit device

address followed by a low R/W bit. The next byte transmitted by the controller is the Address Pointer register.

The ADS101x-Q1 then acknowledge receipt of the Address Pointer register byte. The next two bytes are written

to the address given by the register address pointer bits, P[1:0]. The ADS101x-Q1 acknowledge each byte sent.

Register bytes are sent with the most significant byte first, followed by the least significant byte.

7.5.2.2 Transmit Mode

In target transmit mode, the first byte transmitted by the controller is the 7-bit target address followed by the high

R/W bit. This byte places the target into transmit mode and indicates that the ADS101x-Q1 are being read from.

The next byte transmitted by the target is the most significant byte of the register that is indicated by the register

address pointer bits, P[1:0]. This byte is followed by an acknowledgment from the controller. The remaining least

significant byte is then sent by the target and is followed by an acknowledgment from the controller. The

controller can terminate transmission after any byte by not acknowledging or issuing a START or STOP

condition.

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7.5.3 Writing To and Reading From the Registers

To access a specific register from the ADS101x-Q1, the controller must first write an appropriate value to register

address pointer bits P[1:0] in the Address Pointer register. The Address Pointer register is written to directly after

the target address byte, low R/W bit, and a successful target acknowledgment. After the Address Pointer register

is written, the target acknowledges, and the controller issues a STOP or a repeated START condition.

When reading from the ADS101x-Q1, the previous value written to bits P[1:0] determines the register that is

read. To change which register is read, a new value must be written to P[1:0]. To write a new value to P[1:0], the

controller issues a target address byte with the R/W bit low, followed by the Address Pointer register byte. No

additional data has to be transmitted, and a STOP condition can be issued by the controller. The controller can

now issue a START condition and send the target address byte with the R/W bit high to begin the read. 图 7-9

details this sequence. If repeated reads from the same register are desired, there is no need to continually send

the Address Pointer register, because the ADS101x-Q1 store the value of P[1:0] until modified by a write

operation. However, for every write operation, the Address Pointer register must be written with the appropriate

values.

1

9

1

9

¼

SCL

A1⁽¹⁾A0⁽¹⁾

R/W

0

P1

P0

SDA

1

0

1

0

Start By

Controller

ACK By

ADS1013/4/5-Q1

ACK By Stop By

ADS1013/4/5-Q1 Controller

Frame 2: Address Pointer Register

Frame 1: Target Address Byte

1

9

1

9

SCL

¼

(Continued)

SDA

A1⁽¹⁾A0⁽¹⁾

¼

0

1

0

1

R/W

D15 D14 D13 D12 D11 D10 D9

From

ADS1013/4/5-Q1

D8

(Continued)

Start By

ACK By

ADS1013/4/5-Q1

ACK By

Controller⁽²⁾

Controller

Frame 3: Target Address Byte

Frame 4: Data Byte 1 Read Register

1

9

SCL

(Continued)

SDA

D7 D6

D5

D4

D3

D2

D1

D0

(Continued)

From

ADS1013/4/5-Q1

ACK By

Controller⁽³⁾

Stop By

Controller

Frame 5: Data Byte 2 Read Register

A. The values of A0 and A1 are determined by the ADDR pin.

B. The controller can leave SDA high to terminate a single-byte read operation.

C. The controller can leave SDA high to terminate a two-byte read operation.

图7-9. Timing Diagram for Reading From ADS101x-Q1

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1

9

1

9

SCL

¼

A1⁽¹⁾A0⁽¹⁾

SDA

1

0

1

0

R/W

0

P1

P0

¼

Start By

Controller

ACK By

ADS1013/4/5-Q1

ACK By

ADS1013/4/5-Q1

Frame 2: Address Pointer Register

Frame 1: Target Address Byte

1

9

1

9

SCL

(Continued)

SDA

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

(Continued)

ACK By

ADS1013/4/5-Q1

ACK By

ADS1013/4/5-Q1

Stop By

Controller

Frame 3: Data Byte 1

Frame 4: Data Byte 2

A. The values of A0 and A1 are determined by the ADDR pin.

图7-10. Timing Diagram for Writing to ADS101x-Q1

ALERT

SCL

1

9

1

9

SDA

0

1

0

R/W

1

0

1

A1

A0 Status

Start By

Controller

ACK By

ADS1013/4/5-Q1

From

ADS1013/4/5-Q1

NACK By Stop By

Controller Controller

Frame 1: SMBus ALERT Response Address Byte

Frame 2: Target Address

A. The values of A0 and A1 are determined by the ADDR pin.

图7-11. Timing Diagram for SMBus Alert Response

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7.5.4 Data Format

The ADS101x-Q1 provide 12 bits of data in binary two's-complement format that is left-justified within the 16-bit

data word. A positive full-scale (+FS) input produces an output code of 7FF0h and a negative full-scale (–FS)

input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. 表7-3

summarizes the ideal output codes for different input signals. 图 7-12 shows code transitions versus input

voltage.

表7-3. Input Signal Versus Ideal Output Code

INPUT SIGNAL

V_IN= (V_AINP–V_AINN

)

IDEAL OUTPUT CODE^{(1) (1)}

≥+FS (2¹¹–1) / 2¹¹

7FF0h

0010h

0000h

FFF0h

8000h

+FS / 2¹¹

0

–FS / 2¹¹

≤–FS

(1) Excludes the effects of noise, INL, offset, and gain errors.

7FF0h

7FE0h

0010h

0000h

FFF0h

8010h

8000h

. . .

-FS

0

+FS

Input Voltage V_IN

2¹¹- 1

2¹¹

2¹¹- 1

+FS

2¹¹

图7-12. Code Transition Diagram

备注

Single-ended signal measurements, where V_AINN= 0 V and V_AINP= 0 V to +FS, only use the positive

code range from 0000h to 7FF0h. However, because of device offset, the ADS101x-Q1 can still output

negative codes in case V_AINPis close to 0 V.

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7.6 Register Map

The ADS101x-Q1 have four registers that are accessible through the I²C interface using the Address Pointer

register. The Conversion register contains the result of the last conversion. The Config register is used to change

the ADS101x-Q1 operating modes and query the status of the device. The other two registers, Lo_thresh and

Hi_thresh, set the threshold values used for the comparator function, and are not available in the ADS1013-Q1.

7.6.1 Address Pointer Register (address = N/A) [reset = N/A]

All four registers are accessed by writing to the Address Pointer register; see 图7-9.

图7-13. Address Pointer Register

7

6

5

4

3

2

1

0

RESERVED

W-000000b

P[1:0]

W-00b

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

表7-4. Address Pointer Register Field Descriptions

Bit

7:2

1:0

Field

Type

Reset

000000b

00b

Description

Reserved

P[1:0]

W

Always write 000000b

W

Register address pointer

00b : Conversion register

01b : Config register

10b : Lo_thresh register

11b : Hi_thresh register

7.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary two's-complement format.

Following power-up, the Conversion register is cleared to 0000h, and remains 0000h until the first conversion

completes.

图7-14. Conversion Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

D[11:4]

R-00h

4

3

D[3:0]

R-0h

RESERVED

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-5. Conversion Register Field Descriptions

Bit

15:4

3:0

Field

Type

R

Reset

000h

0h

Description

D[11:0]

Reserved

12-bit conversion result

Always reads back 0h

R

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7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]

The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and

comparator modes.

图7-15. Config Register - ADS1013-Q1

15

OS

14

13

5

12

11

RESERVED

R/W-000010b

10

9

1

8

MODE

R/W-1b

0

R/W-1b

7

6

4

3

2

DR[2:0]

R/W-100b

RESERVED

R/W-00011b

图7-16. Config Register - ADS1014-Q1

15

OS

14

13

RESERVED

R/W-000b

5

12

11

10

PGA[2:0]

R/W-010b

2

9

1

8

MODE

R/W-1b

0

R/W-1b

7

6

4

3

DR[2:0]

R/W-100b

COMP_MODE

R/W-0b

COMP_POL

R/W-0b

COMP_LAT

R/W-0b

COMP_QUE[1:0]

R/W-11b

图7-17. Config Register - ADS1015-Q1

15

OS

14

13

MUX[2:0]

R/W-000b

5

12

11

10

PGA[2:0]

R/W-010b

2

9

1

8

MODE

R/W-1b

0

R/W-1b

7

6

4

3

DR[2:0]

R/W-100b

COMP_MODE

R/W-0b

COMP_POL

R/W-0b

COMP_LAT

R/W-0b

COMP_QUE[1:0]

R/W-11b

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-6. Config Register Field Descriptions

Bit

Field

Type

Reset

Description

Operational status or single-shot conversion start

This bit determines the operational status of the device. OS can only be written

when in power-down state and has no effect when a conversion is ongoing.

When writing:

15

OS

R/W

1b

0b : No effect

1b : Start a single conversion (when in power-down state)

When reading:

0b : Device is currently performing a conversion

1b : Device is not currently performing a conversion

Input multiplexer configuration (ADS1015-Q1 only)

These bits configure the input multiplexer.

These bits serve no function on the ADS1013-Q1 and ADS1014-Q1. ADS1013-

Q1 and ADS1014-Q1 always use inputs AIN_P= AIN0 and AIN_N= AIN1.

000b : AIN_P= AIN0 and AIN_N= AIN1 (default)

001b : AIN_P= AIN0 and AIN_N= AIN3

14:12

MUX[2:0]

R/W

000b

010b : AIN_P= AIN1 and AIN_N= AIN3

011b : AIN_P= AIN2 and AIN_N= AIN3

100b : AIN_P= AIN0 and AIN_N= GND

101b : AIN_P= AIN1 and AIN_N= GND

110b : AIN_P= AIN2 and AIN_N= GND

111b : AIN_P= AIN3 and AIN_N= GND

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表7-6. Config Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Programmable gain amplifier configuration

These bits set the FSR of the programmable gain amplifier.

These bits serve no function on the ADS1013-Q1. ADS1013-Q1 always uses

FSR = ±2.048 V.

000b : FSR = ±6.144 V⁽¹⁾

001b : FSR = ±4.096 V⁽¹⁾

010b : FSR = ±2.048 V (default)

011b : FSR = ±1.024 V

11:9

PGA[2:0]

R/W

010b

100b : FSR = ±0.512 V

101b : FSR = ±0.256 V

110b : FSR = ±0.256 V

111b : FSR = ±0.256 V

Device operating mode

This bit controls the operating mode.

0b : Continuous-conversion mode

1b : Single-shot mode or power-down state (default)

8

MODE

R/W

1b

Data rate

These bits control the data rate setting.

000b : 8 SPS

001b : 16 SPS

010b : 32 SPS

011b : 64 SPS

7:5

DR[2:0]

100b

100b : 128 SPS (default)

101b : 250 SPS

110b : 475 SPS

111b : 860 SPS

Comparator mode (ADS1014-Q1 and ADS1015-Q1 only)

This bit configures the comparator operating mode.

This bit serves no function on the ADS1013-Q1.

0b : Traditional comparator (default)

4

3

COMP_MODE

COMP_POL

R/W

0b

1b : Window comparator

Comparator polarity (ADS1014-Q1 and ADS1015-Q1 only)

This bit controls the polarity of the ALERT/RDY pin.

This bit serves no function on the ADS1013-Q1.

0b : Active low (default)

1b : Active high

Latching comparator (ADS1014-Q1 and ADS1015-Q1 only)

This bit controls whether the ALERT/RDY pin latches after being asserted or

clears after conversions are within the margin of the upper and lower threshold

values.

This bit serves no function on the ADS1013-Q1.

2

COMP_LAT

R/W

0b

0b : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted

(default).

1b : Latching comparator. The asserted ALERT/RDY pin remains latched until

conversion data are read by the controller or an appropriate SMBus alert

response is sent by the controller. The device responds with an address, and is

the lowest address currently asserting the ALERT/RDY bus line.

Comparator queue and disable (ADS1014-Q1 and ADS1015-Q1 only)

These bits perform two functions. When set to 11, the comparator is disabled and

the ALERT/RDY pin is set to a high-impedance state. When set to any other

value, the ALERT/RDY pin and the comparator function are enabled, and the set

value determines the number of successive conversions exceeding the upper or

lower threshold required before asserting the ALERT/RDY pin.

These bits serve no function on the ADS1013-Q1.

1:0

COMP_QUE[1:0] R/W

11b

00b : Assert after one conversion

01b : Assert after two conversions

10b : Assert after four conversions

11b : Disable comparator and set ALERT/RDY pin to high-impedance (default)

(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the

device.

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7.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers

These two registers are applicable to the ADS1015-Q1 and ADS1014-Q1. These registers serve no purpose in

the ADS1013-Q1. The upper and lower threshold values used by the comparator are stored in two 16-bit

registers in two's-complement format. The comparator is implemented as a digital comparator; therefore, the

values in these registers must be updated whenever the PGA settings are changed.

The conversion-ready function of the ALERT/RDY pin is enabled by setting the Hi_thresh register MSB to 1b and

the Lo_thresh register MSB to 0b. To use the comparator function of the ALERT/RDY pin, the Hi_thresh register

value must always be greater than the Lo_thresh register value. The threshold register formats are shown in 图

7-18. When set to RDY mode, the ALERT/RDY pin outputs the OS bit when in single-shot mode, and provides a

continuous-conversion ready pulse when in continuous-conversion mode.

图7-18. Lo_thresh Register

15

7

14

6

13

5

12

Lo_thresh[11:4]

R/W-80h

11

10

2

9

1

8

0

4

3

Lo_thresh[3:0]

R/W-0h

RESERVED

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-7. Hi_thresh Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

Hi_thresh[11:4]

R/W-7Fh

4

3

Hi_thresh[3:0]

R/W-Fh

RESERVED

R-Fh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表7-8. Lo_thresh and Hi_thresh Register Field Descriptions

Bit

Field

Type

R/W

Reset

800h

7FFh

Description

15:4

Lo_thresh[11:0]

Hi_thresh[11:0]

Low threshold value

High threshold value

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The following sections give example circuits and suggestions for using the ADS101x-Q1 in various situations.

8.1.1 Basic Connections

The principle I²C connections for the ADS1015-Q1 are shown in 图8-1.

10

ADS1015-Q1

VDD

SCL

VDD

1

2

ADDR

9

8

SDA

VDD

AIN3

1-k to 10-k (typ)

Pullup Resistors

ALERT/RDY

GND

0.1 μF (typ)

3

4

7

6

Microcontroller or

Microprocessor

with I²C Port

AIN0

AIN2

AIN1

5

SCL

SDA

GPIO

Inputs Selected

from Configuration

Register

图8-1. Typical Connections of the ADS1015-Q1

The fully differential voltage input of the ADS101x-Q1 is ideal for connection to differential sources with

moderately low source impedance, such as thermocouples and thermistors. Although the ADS101x-Q1 can read

bipolar differential signals, these devices cannot accept negative voltages on either input.

The ADS101x-Q1 draw transient currents during conversion. A 0.1-μF power-supply bypass capacitor supplies

the momentary bursts of extra current required from the supply.

The ADS101x-Q1 interface directly to standard mode, fast mode, and high-speed mode I²C controllers. Any

microcontroller I²C peripheral, including controller-only and single-controller I²C peripherals, operates with the

ADS101x-Q1. The ADS101x-Q1 does not perform clock-stretching (that is, the device never pulls the clock line

low), so this function does not need to be provided for unless other clock-stretching devices are on the same I²C

bus.

Pullup resistors are required on both the SDA and SCL lines because I²C bus drivers are open drain. The size of

these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors

consume less power, but increase the transition times on the bus, thus limiting the bus speed. Lower-value

resistors allow higher speed, but at the expense of higher power consumption. Long bus lines have higher

capacitance and require smaller pullup resistors to compensate. Do not use resistors that are too small to avoid

bus drivers being unable to pull the bus lines low.

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8.1.2 Single-Ended Inputs

The ADS1013-Q1 and ADS1014-Q1 can measure one, and the ADS1015-Q1 up to four, single-ended signals.

The ADS1013-Q1 and ADS1014-Q1 can measure single-ended signals by connecting AIN1 to GND externally.

The ADS1015-Q1 measures single-ended signals by appropriate configuration of the MUX[2:0] bits in the Config

register. 图 8-2 shows a single-ended connection scheme for ADS1015-Q1. The single-ended signal ranges

from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to these devices

because the ADS101x-Q1 can only accept positive voltages with respect to ground. The ADS101x-Q1 do not

lose linearity within the input range.

The ADS101x-Q1 offer a differential input voltage range of ±FSR. Single-ended configurations use only one-half

of the full-scale input voltage range. Differential configurations maximize the dynamic range of the ADC, and

provide better common-mode noise rejection than single-ended configurations.

VDD

10

Output Codes

0-2047

ADS1015-Q1

SCL

SDA

VDD

AIN3

AIN2

9

8

7

6

1

2

3

4

ADDR

ALERT/RDY

GND

0.1 F (typ)

AIN0

AIN1

5

Inputs Selected

from Configuration

Register

NOTE: Digital pin connections omitted for clarity.

图8-2. Measuring Single-Ended Inputs

The ADS1015-Q1 also allows AIN3 to serve as a common point for measurements by appropriate setting of the

MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the

ADS1015-Q1 operates with inputs, where AIN3 serves as the common point. This ability improves the usable

range over the single-ended configuration because negative differential voltages are allowed when

GND < V_(AIN3)< VDD; however, common-mode noise attenuation is not offered.

8.1.3 Input Protection

The ADS101x-Q1 are fabricated in a small-geometry, low-voltage process. The analog inputs feature protection

diodes to the supply rails. However, the current-handling ability of these diodes is limited, and the ADS101x-Q1

can be permanently damaged by analog input voltages that exceed approximately 300 mV beyond the rails for

extended periods. One way to protect against overvoltage is to place current-limiting resistors on the input lines.

The ADS101x-Q1 analog inputs can withstand continuous currents as large as 10 mA.

8.1.4 Unused Inputs and Outputs

Follow the guidelines below for the connection of unused device pins:

• Either float unused analog inputs, or tie unused analog inputs to GND

• Either float NC (not connected) pins, or tie the NC pins to GND

• If the ALERT/RDY output pin is not used, leave the pin unconnected or tie the pin to VDD using a weak

pullup resistor

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8.1.5 Analog Input Filtering

Analog input filtering serves two purposes:

1. Limits the effect of aliasing during the sampling process

2. Reduces external noise from being a part of the measurement

Aliasing occurs when frequency components are present in the input signal that are higher than half the

sampling frequency of the ADC (also known as the Nyquist frequency). These frequency components fold back

and show up in the actual frequency band of interest below half the sampling frequency. The filter response of

the digital filter repeats at multiples of the sampling frequency, also known as the modulator frequency (f_MOD), as

shown in 图 8-3. Signals or noise up to a frequency where the filter response repeats are attenuated to a certain

amount by the digital filter depending on the filter architecture. Any frequency components present in the input

signal around the modulator frequency, or multiples thereof, are not attenuated and alias back into the band of

interest, unless attenuated by an external analog filter.

Magnitude

Sensor

Signal

Unwanted

Signals

Unwanted

Signals

Output

Data Rate

f_MOD/ 2

f_MOD

Frequency

Magnitude

Digital Filter

Aliasing of

Unwanted Signals

Output

Data Rate

f_MOD/ 2

Magnitude

External

Antialiasing Filter

Roll-Off

Output

Data Rate

f_MOD/ 2

图8-3. Effect of Aliasing

Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of

change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC.

However, any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass

band. Power line-cycle frequency and harmonics are one common noise source. External noise can also be

generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as

nearby motors and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) in

the form of clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting

the measurement result.

A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to

reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f_MOD/ 2 is

attenuated to a level below the noise floor of the ADC. The digital filter of the ADS101x-Q1 attenuate signals to a

certain degree. In addition, noise components are usually smaller in magnitude than the actual sensor signal.

Therefore, use a first-order RC filter with a cutoff frequency set at the output data rate or 10x higher as a

generally good starting point for a system design.

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8.1.6 Connecting Multiple Devices

Up to four ADS101x-Q1 devices can be connected to a single I²C bus using different address pin configurations

for each device. Use the address pin to set the ADS101x-Q1 to one of four different I²C addresses. Use the

GND, VDD, and SCL addresses first. If SDA is used as the device address, hold the SDA line low for at least

100 ns after the SCL line goes low to make sure the device decodes the address correctly during I²C

communication. An example showing four ADS101x-Q1 devices on the same I²C bus is shown in 图 8-4. One

set of pullup resistors is required per bus. The pullup resistor values may need to be lowered to compensate for

the additional bus capacitance presented by multiple devices and increased line length.

VDD

GND

10

ADS1015-Q1

SCL

1

2

ADDR

9

8

SDA

VDD

AIN3

1-k to 10-k (typ)

I²C Pullup Resistors

ALERT/RDY

GND

VDD

3

4

7

6

AIN0

AIN2

Microcontroller or

Microprocessor

With I²C Port

AIN1

5

SCL

SDA

10

ADS1015-Q1

SCL

1

2

ADDR

9

8

SDA

VDD

AIN3

ALERT/RDY

GND

3

4

7

6

AIN0

AIN2

AIN1

5

10

ADS1015-Q1

SCL

1

2

ADDR

9

8

SDA

VDD

AIN3

ALERT/RDY

GND

3

4

7

6

AIN0

AIN2

AIN1

5

10

ADS1015-Q1

SCL

1

2

ADDR

9

8

SDA

VDD

AIN3

ALERT/RDY

GND

3

4

7

6

AIN0

AIN2

AIN1

5

NOTE: ADS101x-Q1 power and input connections omitted for clarity. The ADDR pin selects the I²C address.

图8-4. Connecting Multiple ADS101x-Q1 Devices

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8.1.7 Quick-Start Guide

This section provides a brief example of ADS101x-Q1 communications. Hardware for this design includes: one

ADS101x-Q1 configured with an I²C address of 1001000b; a microcontroller with an I²C interface; discrete

components such as resistors, capacitors, and serial connectors; and a 2-V to 5-V power supply. 图 8-5 shows

the basic hardware configuration.

The ADS101x-Q1 communicate with the controller (microcontroller) through an I²C interface. The controller

provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS101x-Q1 never

drive the SCL pin. For information on programming and debugging the microcontroller being used, see the

device-specific product data sheet.

The first byte sent by the controller is the ADS101x-Q1 address, followed by the R/W bit that instructs the

ADS101x-Q1 to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and

fourth bytes sent from the controller are written to the register indicated in register address pointer bits P[1:0].

See 图7-9 and 图7-10 for read and write operation timing diagrams, respectively. All read and write transactions

with the ADS101x-Q1 must be preceded by a START condition, and followed by a STOP condition.

For example, to write to the configuration register to set the ADS101x-Q1 to continuous-conversion mode and

then read the conversion result, send the following bytes in this order:

1. Write to Config register:

• First byte: 10010000b (first 7-bit I²C address followed by a low R/W bit)

• Second byte: 00000001b (points to Config register)

• Third byte: 10000100b (MSB of the Config register to be written)

• Fourth byte: 10000011b (LSB of the Config register to be written)

2. Write to Address Pointer register:

• First byte: 10010000b (first 7-bit I²C address followed by a low R/W bit)

• Second byte: 00000000b (points to Conversion register)

3. Read Conversion register:

• First byte: 10010001b (first 7-bit I²C address followed by a high R/W bit)

• Second byte: the ADS101x-Q1 responds with the MSB of the Conversion register

• Third byte: the ADS101x-Q1 responds with the LSB of the Conversion register

3.3 V

ADS101x-Q1

VDD

0.1 µF

3.3 V

10 k

I²C-Capable Controller

(MSP430F2002)

GND

AIN0

AIN1

3.3 V

ADDR

SCL

10 k

AIN2 (ADS1015-Q1 Only)

AIN3 (ADS1015-Q1 Only)

VDD

GND

SCL (P1.6)

SDA (P1.7)

0.1 µF

SDA

ALERT

(ADS1014/5-Q1 Only)

JTAG

Serial/UART

图8-5. Basic Hardware Configuration

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8.2 Typical Application

Shunt-based, current-measurement solutions are widely used to monitor load currents. Low-side, current-shunt

measurements are independent of the bus voltage because the shunt common-mode voltage is near ground. 图

8-6 shows an example circuit for a bidirectional, low-side, current-shunt measurement system. The load current

is determined by measuring the voltage across the shunt resistor that is amplified and level-shifted by a low-drift

operational amplifier, OPA333-Q1. The OPA333-Q1 output voltage is digitized with ADS1015-Q1 and sent to the

microcontroller using the I²C interface. This circuit is capable of measuring bidirectional currents flowing through

the shunt resistor with great accuracy and precision.

High-Voltage Bus

VDD

V_CM

VDD

C_CM2

LOAD

R₆

AINN

I²C

I_LOAD

R₄

OPA333-Q1

R₅

ADS1015-Q1

AINP

C_DIFF

R₃

+

V_INX

V_OUT

œ

C_CM1

V_SHUNT

R₁

R₂

图8-6. Low-Side Current Shunt Monitoring

8.2.1 Design Requirements

表8-1 shows the design parameters for this application.

表8-1. Design Parameters

DESIGN PARAMETER

VALUE

Supply voltage (VDD)

5 V

±50 mV

Voltage across shunt resistor (V_SHUNT

Output data rate (DR)

)

≥200 readings per second

±0.25%

Typical measurement accuracy at T_A= 25°C⁽¹⁾

(1) Does not account for inaccuracy of shunt resistor and the precision resistors used in the

application.

8.2.2 Detailed Design Procedure

The first stage of the application circuit consists of an OPA333-Q1 in a noninverting summing amplifier

configuration and serves two purposes:

1. To level-shift the ground-referenced signal to allow bidirectional current measurements while running off a

unipolar supply. The voltage across the shunt resistor, V_SHUNT, is level-shifted by a common-mode voltage,

V_CM, as shown in 图8-6. The level-shifted voltage, V_INX, at the noninverting input is given by 方程式3.

V_INX= (V_CM· R₃+ V_SHUNT· R₄) / (R₃+ R₄)

(3)

2. To amplify the level-shifted voltage (V_INX). The OPA333-Q1 is configured in a noninverting gain configuration

with the output voltage, V_OUT, given by 方程式4.

V_OUT= V_INX· (1 + R₂/ R₁)

(4)

Using 方程式3 and 方程式4, V_OUTis given as a function of V_SHUNTand V_CMby 方程式5.

V_OUT= (V_CM· R₃+ V_SHUNT· R₄) / (R₃+ R₄) · (1 + R₂/ R₁)

(5)

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Using 方程式5 the ADC differential input voltage, before the first-order RC filter, is given by 方程式6.

V

_OUT–V_CM= V_SHUNT· (1 + R₂/ R₁) / (1 + R₄/ R₃) + V_CM· (R₂/ R₁–R₃/ R₄) / (1 + R₃/ R₄)

(6)

(7)

If R₁= R₄and R₂= R₃, 方程式6 is simplified to 方程式7.

V

_OUT–V_CM= V_SHUNT· (1 + R₂/ R₁) / (1 + R₄/ R₃)

8.2.2.1 Shunt Resistor Considerations

A shunt resistor (R_SHUNT) is an accurate resistance inserted in series with the load as described in 图 8-6. If the

absolute voltage drop across the shunt, |V_SHUNT|, is a larger percentage of the bus voltage, the voltage drop can

reduce the overall efficiency and system performance. If |V_SHUNT| is too low, measuring the small voltage drop

requires careful design attention and proper selection of the ADC, operation amplifier, and precision resistors.

Make sure that the absolute voltage at the shunt terminals does not result in violation of the input common-mode

voltage range requirements of the operational amplifier. The power dissipation on the shunt resistor increases

the temperature because of the current flowing through the resistor. To minimize the measurement errors

resulting from variation in temperature, select a low-drift shunt resistor. To minimize the measurement gain error,

select a shunt resistor with a low tolerance value. To remove the errors caused by stray ground resistance, use a

four-wire Kelvin-connected shunt resistor; see 图8-6.

8.2.2.2 Operational Amplifier Considerations

The operational amplifier used for this design example requires the following features:

• Unipolar supply operation (5 V)

• Low input offset voltage (< 10 µV) and input offset voltage drift (< 0.5 µV/°C)

• Rail-to-rail input and output capability

• Low thermal and flicker noise

• High common-mode rejection (> 100 dB)

The OPA333-Q1 offers all these benefits and is selected for this application.

8.2.2.3 ADC Input Common-Mode Considerations

V_CMsets the V_OUTcommon-mode voltage by appropriate selection of precision resistors R₁, R₂, R₃, and R₄.

If R₁= R₃, R₂= R₄, and V_SHUNT= 0 V, V_OUTis given by 方程式8.

V_OUT= V_CM

(8)

If V_OUTis connected to the ADC positive input (AINP) and V_CMis connected to the ADC negative input (AINN),

V_CMappears as a common-mode voltage to the ADC. This configuration allows pseudo-differential

measurements and uses the maximum dynamic range of the ADC if V_CMis set at midsupply (VDD / 2). A resistor

divider from VDD to GND followed by a buffer amplifier can be used to generate V_CM

.

8.2.2.4 Resistor (R₁, R₂, R₃, R₄) Considerations

Proper selection of resistors R₁, R₂, R₃, and R₄is critical for meeting the overall accuracy requirements.

Using 方程式 6, the offset term, V_OUT-OS, and the gain term, A_OUT, of the differential ADC input are represented

by 方程式9 and 方程式10 respectively. The error contributions from the first-order RC filters are ignored.

V_OUT-OS= V_CM· (R₂/ R₁- R₃/ R₄) / (1 + R₃/ R₄)

A_OUT= (1 + R₂/ R₁) / (1 + R₄/ R₃)

(9)

(10)

The tolerance, drift, and linearity performance of these resistors is critical to meeting the overall accuracy

requirements. In 方程式9, if R₁= R₃and R₂= R₄, V_OUT-OS= 0 V and therefore, the common-mode voltage, V_CM

,

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only contributes to level-shift V_SHUNTand does not introduce any error at the differential ADC inputs. High-

precision resistors provide better common-mode rejection from V_CM

.

8.2.2.5 Noise and Input Impedance Considerations

If v_{n_res}represents the input-referred rms noise from all the resistors, v_{n_op}represents the input-referred rms

noise of the OPA333-Q1, and v_{n_ADC}represents the input-referred rms noise of the ADS1015-Q1, the total input-

referred noise of the entire system, v_N, can be approximated by 方程式11.

v_N²= v_{n_res}²+ v_{n_op}²+ v_{n_ADC}/ (1 + R₂/ R₁)²

(11)

The ADC noise contribution, v_{n_ADC}, is attenuated by the noninverting gain stage.

If the gain of the noninverting gain stage is high (≥ 5), a good approximation for v_{n_res}²is given by 方程式 12.

The noise contribution from resistors R₂, R₄, R₅, and R₆when referred to the input is smaller in comparison to R₁

and R₃and can be neglected for approximation purposes.

v_{n_res}²= 4 · k · T · (R₁+ R₃) · Δf

(12)

where

• k = Boltzmann constant

• T = Temperature (in kelvins)

• Δf = Noise bandwidth

An approximation for the input impedance, R_IN, of the application circuit is given by 方程式 13. R_INcan be

modeled as a resistor in parallel with the shunt resistor, and can contribute to additional gain error.

R_IN= R₃+ R₄

(13)

From 方程式 12 and 方程式 13, a trade-off exists between v_Nand R_IN. If R₃increases, v_{n_res}increases, and

therefore, the total input-referred rms system noise, v_N, increases. If R₃decreases, the input impedance, R_IN,

drops, and causes additional gain error.

8.2.2.6 First-Order RC Filter Considerations

Although the device digital filter attenuates high-frequency noise, use a first-order, low-pass RC filter at the ADC

inputs to further reject out-of-bandwidth noise and avoid aliasing. A differential low-pass RC filter formed by R5,

R6, and the differential capacitor C_DIFFsets the –3-dB cutoff frequency, f_C, given by 方程式 14. These filter

resistors produce a voltage drop because of the input currents flowing into and out of the ADC. This voltage drop

can contribute to an additional gain error. Limit the filter resistor values to below 1 kΩ.

f_C= 1 / [2π· (R₅+ R₆) · C_DIFF

]

(14)

Two common-mode filter capacitors (C_CM1and C_CM2) are also added to offer attenuation of high-frequency,

common-mode noise components. Select a differential capacitor, C_DIFF, that is at least an order of magnitude

(10x) larger than these common-mode capacitors because mismatches in these common-mode capacitors can

convert common-mode noise into differential noise.

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8.2.2.7 Circuit Implementation

表8-2 shows the chosen values for this design.

表8-2. Parameters

PARAMETER

V_CM

VALUE

2.5 V

FSR of ADC

Output data rate

R₁, R₃

±0.256 V

250 SPS

1 kΩ⁽¹⁾

5 kΩ⁽¹⁾

R₂, R₄

100 Ω⁽¹⁾

0.22 µF

0.022 µF

R₅, R₆

C_DIFF

C_CM1, C_CM2

(1) 1% precision resistors are used.

Using 方程式 5, if V_SHUNTranges from –50 mV to +50 mV, the application circuit produces a differential voltage

ranging from –0.250 V to +0.250 V across the ADC inputs. The ADC is therefore configured at a FSR of ±0.256

V to maximize the dynamic range of the ADC.

The –3-dB cutoff frequencies of the differential low-pass filter and the common-mode low-pass filters are set at

3.6 kHz and 0.36 kHz, respectively.

R_SHUNTtypically ranges from 0.01 mΩ to 100 mΩ. Therefore, if R₁= R₃= 1 kΩ, a good trade-off exists

between the circuit input impedance and input-referred resistor noise as explained in the Noise and Input

Impedance Considerations section.

A simple resistor divider followed by a buffer amplifier is used to generate V_CMof 2.5 V from a 5-V supply.

8.2.2.8 Results Summary

A precision voltage source is used to sweep V_SHUNTfrom –50 mV to +50 mV. The application circuit produces a

differential voltage of –250 mV to +250 mV across the ADC inputs. 图 8-7 and 图 8-8 show the measurement

results. The measurements are taken at T_A= 25°C. Although 1% tolerance resistors are used, the exact value of

these resistors are measured with a Fluke 4.5 digit multimeter to exclude the errors due to inaccuracy of these

resistors. In 图 8-7, the x-axis represents V_SHUNTand the black line represents the measured digital output

voltage in mV. In 图 8-8, the x-axis represents V_SHUNT, the black line represents the total measurement error in

%, the blue line represents the total measurement error in % after excluding the errors from precision resistors

and the green line represents the total measurement error in % after excluding the errors from precision resistors

and performing a system offset calibration with V_SHUNT= 0 V. 表8-3 shows a results summary.

表8-3. Results Summary⁽¹⁾

PARAMETER

VALUE

1.89%

0.17%

0.11%

Total error, including errors from 1% precision resistors

Total error, excluding errors from 1% precision resistors

Total error, after offset calibration, excluding errors from 1% precision resistors

(1) T_A= 25°C, not accounting for inaccuracy of shunt resistor.

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8.2.3 Application Curves

2

1.75

1.5

1.25

1

0.75

0.5

0.25

0

250

200

150

100

50

0

-0.25

-0.5

-0.75

-1

-1.25

-1.5

-1.75

-2

-50

-100

-150

-200

-250

Including all errors

Excluding resistor errors

Excluding resistor errors, after offset calibration

-60 -50 -40 -30 -20 -10

0

Shunt Voltage (mV)

10 20 30 40 50 60

-50 -40 -30 -20 -10

0

Shunt Voltage (mV)

10

20

30

40

50

D004

D005

图8-7. Measured Output vs Shunt Voltage (V_SHUNT

)

图8-8. Measurement Error vs Shunt Voltage

(V_SHUNT

)

8.3 Power Supply Recommendations

The device requires a single unipolar supply, VDD, to power both the analog and digital circuitry of the device.

8.3.1 Power-Supply Sequencing

Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up

reset process to complete.

8.3.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at

least a 0.1-µF capacitor, as shown in 图 8-9. The 0.1-μF bypass capacitor supplies the momentary bursts of

extra current required from the supply when the device is converting. Place the bypass capacitor as close to the

power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip

capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for

power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments,

avoid the use of vias for connecting the capacitors to the device pins for better noise immunity. The use of

multiple vias in parallel lowers the overall inductance, and is beneficial for connections to ground planes.

VDD

10

TI Device

DIN

ADDR

1

2

9

8

SDA

VDD

AIN3

AIN2

ALERT/RDY

GND

3

4

7

6

0.1 µF

AIN0

AIN1

5

图8-9. ADS1015-Q1 Power-Supply Decoupling

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8.4 Layout

8.4.1 Layout Guidelines

Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital

components. For optimal performance, separate the analog components [such as ADCs, amplifiers, references,

digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers,

complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF)

transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component

placement is shown in 图 8-10. Although 图 8-10 provides a good example of component placement, the best

placement for each application is unique to the geometries, components, and PCB fabrication capabilities

employed. That is, there is no single layout that is perfect for every design and careful consideration must always

be used when designing with any analog component.

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Supply

Generation

Signal

Conditioning

(RC Filters

and

Interface

Transceiver

Device

Microcontroller

Connector

or Antenna

Amplifiers)

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

图8-10. System Component Placement

The following outlines some basic recommendations for the layout of the ADS101x-Q1 to get the best possible

performance of the ADC. A good design can be ruined with a bad circuit layout.

• Separate analog and digital signals. To start, partition the board into analog and digital sections where the

layout permits. Route digital lines away from analog lines. This placement prevents digital noise from

coupling back into analog signals.

• Fill void areas on signal layers with ground fill.

• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground

plane is cut or has other traces that block the current from flowing right next to the signal trace, the current

must find another path to return to the source and complete the circuit. A longer return current path increases

the chance that the signal radiates. Sensitive signals are more susceptible to EMI interference.

• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass

capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active

device yields the best results.

• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react

with the input bias current and cause an added error voltage. Reduce the loop area enclosed by the source

signal and the return current in order to reduce the inductance in the path. Reduce the inductance to reduce

the EMI pickup, and reduce the high frequency impedance observed by the device.

• Differential inputs must be matched for both the inputs going to the measurement source.

• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best

input combinations for differential measurements use adjacent analog input lines such as AIN0, AIN1 and

AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G

(NPO), which have stable properties and low-noise characteristics.

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8.4.2 Layout Example

VDD

AIN3

1

2

3

4

5

10

9

ADDR

ALERT/RDY

GND

SCL

SDA

VDD

AIN3

AIN2

AIN0

8

TI Device

7

AIN0

6

AIN1

AIN2

AIN1

Vias connect to either bottom layer or

an internal plane. The bottom layer or

internal plane are dedicated GND planes

图8-11. ADS1015-Q1 VSSOP Package

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, OPA333-Q1 Automotive, 1.8-V, Micropower, CMOS, Zero-Drift Operational Amplifier data

sheet

• Texas Instruments, MSP430F20x3, MSP430F20x2, MSP430F20x1 Mixed-Signal Microcontrollers data sheet

9.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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English Data Sheet: SBAS511

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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型号：	ADS1014-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有 PGA、振荡器、电压基准、比较器和 I2C 的汽车类 12 位、3.3kSPS、单通道 Δ-Σ ADC 比较器振荡器
文件：	总45页 (文件大小：1900K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1014-Q1 [TI]

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