ADS1112IDRCR [TI]

具有 PGA、振荡器、电压基准和 I2C 的 16 位 240SPS 4 通道 Δ-Σ ADC | DRC | 10 | -40 to 85;


型号：	ADS1112IDRCR
厂家：	TEXAS INSTRUMENTS
描述：	具有 PGA、振荡器、电压基准和 I2C 的 16 位 240SPS 4 通道 Δ-Σ ADC \| DRC \| 10 \| -40 to 85 振荡器
文件：	总27页 (文件大小：1676K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1112

SBAS282D − JUNE 2003 − REVISED MARCH 2004

16-Bit Analog-to-Digital Converter with

Input Multiplexer and Onboard Reference

FEATURES

DESCRIPTION

COMPLETE DATA ACQUISITION SYSTEM IN

THE MSOP-10 AND LEADLESS QFN-STYLE

PACKAGES

The ADS1112 is a precision, continuously self-calibrating

Analog-to-Digital (A/D) converter with two differential or three

single-ended channels and up to 16 bits of resolution in the

small MSOP-10 and leadless QFN-style (small-outline,

no-lead) packages. The onboard 2.048V reference provides

an input range of 2.048V differentially. The ADS1112 uses

an I²C-compatible serial interface and has two address pins

that allow a user to select one of the eight I²C Slave

addresses. The ADS1112 operates from a single power

supply ranging from 2.7V to 5.5V.

MEASUREMENTS FROM TWO DIFFERENTIAL

CHANNELS OR THREE SINGLE-ENDED

CHANNELS

I CINTERFACE—EIGHT ADDRESSES PIN-

SELECTABLE

ONBOARD REFERENCE:

Accuracy: 2.048V 0.05%

Drift: 5ppm/°C

The ADS1112 can perform conversions at rates of 15, 30, 60,

or 240 samples per second (SPS). The onboard

programmable gain amplifier (PGA), which offers gains of up

to eight, allows smaller signals to be measured with high

resolution. In single-conversion mode, the ADS1112

automatically powers down after a conversion, greatly

reducing current consumption during idle periods.

ONBOARD PGA

ONBOARD OSCILLATOR

16 BITS, NO MISSING CODES

INL: 0.01% of FSR max

The ADS1112 is designed for applications requiring

high-resolution measurement, where space and power

consumption are major considerations. Typical applications

include portable instrumentation, industrial process control,

and smart transmitters.

CONTINUOUS SELF-CALIBRATION

SINGLE-CYCLE CONVERSION

PROGRAMMABLE DATA RATE: 15SPS to

240SPS

POWER SUPPLY: 2.7V to 5.5V

LOW CURRENT CONSUMPTION: 240µA

APPLICATIONS

PORTABLE INSTRUMENTATION

INDUSTRIAL PROCESS CONTROL

SMART TRANSMITTERS

CONSUMER GOODS

FACTORY AUTOMATION

TEMPERATURE MEASUREMENT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

This integrated circuit can be damaged by ESD.

Texas Instruments recommends that all

integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and

installation procedures can cause damage.

(1)

ABSOLUTE MAXIMUM RATINGS

VDD to GND

−0.3V to +6V

Input Current

100mA, Momentary

10mA, Continuous

−0.3V to VDD + 0.3V

−0.5V to 6V

Input Current

Analog Inputs, A0, A1, Voltage to GND

SDA, SCL Voltage to GND

Maximum Junction Temperature

Operating Temperature Range

Storage Temperature Range

Lead Temperature (soldering, 10s)

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

+150°C

−40°C to +125°C

−60°C to +150°C

+300°C

(1)

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to

absolute maximum conditions for extended periods may affect

device reliability.

PACKAGE/ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

TRANSPORT MEDIA,

QUANTITY

PRODUCT

PACKAGE-LEAD

ORDERING NUMBER

(1)

ADS1112IDGST

ADS1112IDGSR

ADS1112IDRCT

ADS1112IDRCR

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 3000

ADS1112

MSOP-10

SON-10

DGS

−40°C to +85°C

BHU

BHV

DRC

(1)

For the most current specification and package information, refer to our web site at www.ti.com.

Terminal Functions

MSOP-10

Top View

TERMINAL

NAME

NO.

DESCRIPTION

AIN0

DifferentialChannel 1; Positive Input

Single-ended Channel 1 Input

AIN1

Differential Channel 1; Negative Input

Single-ended Channel 2 Input

GND

AIN2

Ground

Differential Channel 2; Positive Input

Single-ended Channel 3 Input

AIN3

Differential Channel 2; Negative Input

Single-ended Common Input

SON-10

Top View

VDD

SDA

Power Supply: 2.7V to 5.5V

Serial Data: Transmits and receives

data

SCL

Serial Clock Input: Clocks output

data on SDA

I C Slave Address Select

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS

All specifications at −40°C to +85°C, VDD = 5V, and all PGAs, unless otherwise noted.

ADS1112

MIN

TYP

MAX

PARAMETER

CONDITIONS

UNIT

ANALOG INPUT

Full-Scale Input Voltage

) − (V

)

2.048/PGA

2.8/PGA

IN+

IN−

Analog Input Voltage

to GND or V

IN−

to GND

GND − 0.2

VDD + 0.2

Differential Input Impedance

Common-Mode Input Impedance

MΩ

PGA = 1

PGA = 2

PGA = 4

PGA = 8

3.5

1.8

0.9

MΩ

SYSTEM PERFORMANCE

Resolution and No Missing Codes

DR = 00

DR = 01

DR = 10

DR = 11

Bits

Data Rate

DR = 00

DR = 01

DR = 10

DR = 11

180

240

308

SPS

Output Noise

See Typical Characteristic Curves

(1)

(2)

Integral Nonlinearity

Offset Error

DR = 11, PGA = 1, End Point Fit

0.004

0.010

% of FSR

PGA = 1

PGA = 2

PGA = 4

PGA = 8

1.2

0.7

0.5

0.4

2.5

1.5

Offset Drift

PGA = 1

PGA = 2

PGA = 4

PGA = 8

1.2

0.6

0.3

µV/°C

Offset vs VDD

PGA = 1

PGA = 2

PGA = 4

PGA = 8

800

400

200

150

µV/V

Channel Offset Match

Match between any two channels

µV

(3)

Gain Error

0.05

0.02

0.40

0.10

(3)

PGA Gain Error Match

Match between any two PGA gains

(3)

Gain Error Drift

ppm/°C

Gain vs VDD

ppm/V

Channel Gain Match

Match between any two channels

At DC and PGA = 8

0.01

105

100

Common-Mode Rejection

At DC and PGA = 1

DIGITAL INPUT/OUTPUT

Logic Level

0.7 • VDD

GND − 0.5

GND

0.3 • VDD

0.4

= 3mA

Input Leakage

= 5.5V

= GND

µA

−10

2.7

POWER-SUPPLY REQUIREMENTS

Power-Supply Voltage

VDD

5.5

Supply Current

Power-Down

Active Mode

0.05

240

µA

350

Power Dissipation

VDD = 5.0V

VDD = 3.0V

1.2

1.75

0.675

(1)

(2)

(3)

99% of full-scale.

FSR = full-scale range = 2 × 2.048V/PGA = 4.096V/PGA.

Includes all errors from onboard PGA and reference.

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

TYPICAL CHARACTERISTICS

At T = 25°C and VDD = 5V, unless otherwise noted.

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

TYPICAL CHARACTERISTICS (continued)

At T = 25°C and VDD = 5V, unless otherwise noted.

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

TYPICAL CHARACTERISTICS (continued)

At T = 25°C and VDD = 5V, unless otherwise noted.

THEORY OF OPERATION

The ADS1112 is a 16-bit, self-calibrating, delta-sigma A/D

converter with an input multiplexer. Extremely easy to de-

sign with and configure, the ADS1112 allows precise mea-

surements to be obtained with a minimum of effort.

The onboard reference specifications are part of the over-

all gain and drift specifications of the ADS1112. The con-

verter drift and gain error specifications reflect the perfor-

mance of the onboard reference as well as the

performance of the A/D converter core. There are no sepa-

rate specifications for the onboard reference itself.

The ADS1112 consists of a delta-sigma A/D converter

core with adjustable gain, a 2.048V reference, a clock os-

cillator, and an I²C interface. Each of these blocks are de-

scribed in detail in the sections that follow.

OUTPUT CODE CALCULATION

The output code is a scaled value that is proportional, ex-

cept for clipping, to the voltage difference between the two

analog inputs. The output code is confined to a finite range

of numbers; this range depends on the number of bits

needed to represent the code. The number of bits needed

to represent the output code for the ADS1112 depends on

the data rate, as shown in Table 1.

ANALOG-TO-DIGITAL CONVERTER

The ADS1112 A/D converter core consists of a differential

switched-capacitor delta-sigma modulator followed by a

digital filter. The modulator measures the voltage differ-

ence between the positive and negative analog inputs se-

lected by the input multiplexer and compares it to a refer-

ence voltage, which, in the ADS1112, is 2.048V. The digital

filter receives a high-speed bitstream from the modulator

and outputs a code, which is a number proportional to the

input voltage.

NUMBER OF

BITS

MINIMUM

CODE

MAXIMUM

CODE

DATA RATE

15SPS

−32,768

−16,384

−8192

32,767

16,383

8191

30SPS

60SPS

MULTIPLEXER

240SPS

−2048

2047

The ADS1112 has an input multiplexer that provides for

two differential or three single-ended input channels. Two

bits in the configuration register control the multiplexer

setting.

Table 1. Minimum and Maximum Codes

For a minimum output code of Min Code, gain setting of the

PGA, and positive and negative input voltages of V_IN+and

V_IN−, the output code is given by the expression:

VOLTAGE REFERENCE

(V_IN)) * (V_IN*

)

The ADS1112 contains an onboard 2.048V voltage refer-

ence. This reference is always used as the ADC voltage

reference; an external reference cannot be connected.

The ADS1112 voltage reference is internal only, and can-

not be measured directly or used by external circuitry.

Output Code + −1 Min Code PGA

2.048V

In the previous expression, it is important to note that the

negated minimum output code is used. The ADS1112

outputs codes in binary two’s complement format, so the

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

absolute values of the minima and maxima are not the

same; the maximum n-bit code is 2ⁿ⁻¹− 1, while the

values depend on the PGA setting. The switching clock is

generated by the onboard clock oscillator, so its frequency

(nominally 275kHz) is dependent on supply voltage and

temperature.

minimum n-bit code is −1 × 2ⁿ⁻¹

For example, the ideal expression for output codes with a

data rate of 16SPS and PGA = 2 is:

The common-mode and differential input impedances are

different. For a gain setting of the PGA, the differential

input impedance is typically:

(V_IN)) * (V_IN*

)

Output Code + 16384 2

2.048V

2.8MΩ/PGA

The ADS1112 outputs all codes right-justified and

sign-extended. This feature makes it possible to perform

averaging on the higher data rate codes using only a 16-bit

accumulator.

The common-mode impedance also depends on the PGA

setting. See the Electrical Characteristics for details.

The typical value of the input impedance often cannot be

neglected. Unless the input source has a low impedance,

the ADS1112 input impedance may affect the

measurement accuracy. For sources with high output

impedance, buffering may be necessary. Bear in mind,

however, that active buffers introduce noise, and also

introduce offset and gain errors. All of these factors should

be considered in high-accuracy applications.

Table 2 shows the output codes for various input levels.

SELF-CALIBRATION

The previous expressions for the ADS1112 output code do

not account for the gain and offset errors in the modulator.

To compensate for these, the ADS1112 incorporates

self-calibration circuitry.

Because the clock oscillator frequency drifts slightly with

temperature, the input impedances will also drift. For many

applications, this input impedance drift can be neglected,

and the expression given above for typical input

impedance can be used.

The self-calibration system operates continuously and

requires no user intervention. No adjustments can be

made to the self-calibration system, and none need to be

made. The self-calibration system cannot be deactivated.

The offset and gain error figures shown in the Electrical

Characteristics include the effects of calibration.

ALIASING

If frequencies are input to the ADS1112 that exceed half

the data rate, aliasing will occur. To prevent aliasing, the

input signal must be bandlimited. Some signals are

inherently bandlimited. For example, the output of a

thermocouple, which has a limited rate of change, may

nevertheless contain noise and interference components.

These nuisance factors can fold back into the sampling

band just as with any other signal.

CLOCK OSCILLATOR

The ADS1112 features an onboard clock oscillator, which

drives the operation of the modulator and digital filter. The

Typical Characteristics show variations in data rate over

supply voltage and temperature.

It is not possible to operate the ADS1112 with an external

system clock.

The ADS1112 digital filter provides some attenuation of

high-frequency noise, but the digital filter Sinc¹frequency

response cannot completely replace an anti-aliasing filter.

For a few applications, some external filtering may be

needed; in such instances, a simple RC filter will suffice.

INPUT IMPEDANCE

The ADS1112 uses a switched-capacitor input stage. To

external circuitry, it looks roughly like a resistance. The

resistance value depends on the capacitor values and the

rate at which they are switched. The switching frequency

is the same as the modulator frequency; the capacitor

When designing an input filter circuit, remember to take

into account the interaction between the filter network and

the input impedance of the ADS1112.

DIFFERENTIAL INPUT SIGNAL

DATA RATE

(1)

−2.048V

−1LSB

ZERO

+1LSB

+2.048V

15SPS

30SPS

60SPS

240SPS

8000

FFFF

0000

0001

7FFF

3FFF

1FFF

07FF

C000

E000

F800

(1)

Differential input only; do not drive the ADS1112 inputs below −200mV.

Table 2. Output Codes for Different Input Signals

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An I²C bus consists of two lines, SDA and SCL. SDA

carries data; SCL provides the clock. All data is

transmitted across the I²C bus in groups of eight bits. To

send a bit on the I²C bus, the SDA line is driven to the

appropriate level while SCL is LOW (a LOW on SDA

indicates the bit is zero; a HIGH indicates the bit is one).

Once the SDA line has settled, the SCL line is brought

HIGH, then LOW. This pulse on SCL clocks the SDA bit

into the receiver’s shift register.

USING THE ADS1112

OPERATING MODES

The ADS1112 operates in one of two modes: continuous-

conversion or single-conversion.

In continuous-conversion mode, the ADS1112 continu-

ously performs conversions. Once a conversion has been

completed, the ADS1112 places the result in the output

The I²C bus is bidirectional: the SDA line is used both for

transmitting and receiving data. When a master reads from

a slave, the slave drives the data line; when a master

sends to a slave, the master drives the data line. The

master always drives the clock line. The ADS1112 never

drives SCL, because it cannot act as a master. On the

ADS1112, SCL is an input only.

In single-conversion mode, the ADS1112 waits until the

ST/DRDY bit in the conversion register is set to 1. When

this happens, the ADS1112 powers up and performs a

single conversion. After the conversion completes, the

ADS1112 places the result in the output register, resets the

ST/DRDY bit to 0, and powers down. Writing a 1 to

ST/DRDY while a conversion is in progress has no effect.

Most of the time the bus is idle; no communication occurs

place, and both lines are HIGH. When communication is

taking place, the bus is active. Only master devices can

start a communication and initiate a START condition on

the bus. Normally, the data line is only allowed to change

state while the clock line is LOW. If the data line changes

state while the clock line is HIGH, it is either a START

condition or its counterpart, a STOP condition. A START

condition occurs when the clock line is HIGH and the data

line goes from HIGH to LOW. A STOP condition occurs

when the clock line is HIGH and the data line goes from

LOW to HIGH.

When switched from continuous-conversion mode to

single conversion mode, the ADS1112 completes the

current conversion, resets the ST/DRDY bit to 0, and

powers down.

RESET AND POWER-UP

When the ADS1112 powers up, it automatically performs

a reset. As part of the reset process, the ADS1112 sets all

of the bits in the configuration register to their default

settings.

The ADS1112 responds to the I²C General Call Reset

command. When the ADS1112 receives a General Call

Reset, it performs an internal reset, exactly as though it

had just been powered on.

After the master issues a START condition, it sends a byte

that indicates which slave device it wants to communicate

with. This byte is called the address byte. Each device on

an I²C bus has a unique 7-bit address to which it responds.

(Slaves can also have 10-bit addresses; see the I²C

specification for details.) The master sends an address in

the address byte, together with a bit that indicates whether

it wishes to read from or write to the slave device.

I C INTERFACE

The ADS1112 communicates through an I²C

(inter-integrated circuit) interface. I²C is a two-wire

open-drain interface supporting multiple devices and

masters on a single bus. Devices on the I²C bus only drive

the bus lines LOW by connecting them to ground; they

never drive the bus lines HIGH. Instead, the bus wires are

pulled HIGH by pull-up resistors, so the bus wires are

HIGH when no device is driving them LOW. This way, two

devices cannot conflict; if two devices drive the bus

simultaneously, there is no driver contention.

Every byte transmitted on the I²C bus, whether it is

address or data, is acknowledged with an acknowledge

bit. When a master has finished sending a byte (eight data

bits) to a slave, it stops driving SDA and waits for the slave

to acknowledge the byte. The slave acknowledges the

byte by pulling SDA LOW. The master then sends a clock

pulse to clock the acknowledge bit. Similarly, when a

master has finished reading a byte, it pulls SDA LOW to

acknowledge this to the slave. It then sends a clock pulse

to clock the bit. (The master always drives the clock line.)

Communication on the I²C bus always takes place

between two devices, one acting as the master and the

other as the slave. Both masters and slaves can read and

write, but slaves can only do so under the direction of the

master. Some I²C devices can act as masters or slaves,

but the ADS1112 can only act as a slave device.

A not-acknowledge is performed by simply leaving SDA

HIGH during an acknowledge cycle. If a device is not

present on the bus, and the master attempts to address it,

it will receive a not-acknowledge because no device is

present at that address to pull the line LOW.

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When a master has finished communicating with a slave,

it may issue a STOP condition. When a STOP condition is

issued, the bus becomes idle again. A master may also

issue another START condition. When a START condition

is issued while the bus is active, it is called a repeated

START condition.

addresses to be selected with only two pins as shown in

Table 4. The state of pins A0 and A1 is sampled on

power-up or after an I²C general call, and should be set

prior to any activity on the interface.

I C GENERAL CALL

A timing diagram for an ADS1112 I²C transaction is shown

in Figure 1. The parameters for this diagram are given in

Table 3.

The ADS1112 responds to the I²C General Call address

(0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to

commands in the second byte. If the second byte is

00000100 (04h), the ADS1112 will latch the status of the

address pins, A0 and A1, but not perform a reset. If the

second byte is 00000110 (06h), the ADS1112 will latch the

status of the address pins and reset the internal registers.

SERIAL BUS ADDRESS

To program the ADS1112, the master must first address

slave devices via a slave address byte. The slave address

byte consists of seven address bits, and a direction bit

indicating the intent of executing a read or write operation.

The ADS1112 features two address pins, A0 and A1, that

set the I²C address. These pins can be set to a logic low,

logic high, or left unconnected (floating), allowing eight

Figure 1. I C Timing Diagram

FAST MODE

HIGH-SPEED MODE

MIN

MAX

MIN

MAX

PARAMETER

UNITS

SCLK operating frequency

0.4

3.4

MHz

(SCLK)

Bus free time between START and STOP condition

600

160

(BUF)

Hold time after repeated START condition.

After this period, the first clock is generated.

(HDSTA)

Repeated START condition setup time

Stop condition setup time

Data hold time

600

160

(SUSTA)

(SUSTO)

(HDDAT)

Data setup time

100

1300

600

(SUDAT)

SCLK clock LOW period

SCLK clock HIGH period

Clock/data fall time

160

(LOW)

(HIGH)

300

160

Clock/data rise time

Table 3. Timing Diagram Definitions

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SLAVE ADDRESS

1001000

1001001

1001010

1001100

1001101

1001110

from normal address bytes; the low bit does not indicate

read/write status.) The ADS1112 will not acknowledge this

byte; the I²C specification prohibits acknowledgment of

the Hs master code. On receiving a master code, the

ADS1112 will switch on its Hs mode filters, and

communicate at up to 3.4MHz. The ADS1112 will switch

out of Hs mode with the next STOP condition.

Float

1001011

For more information on high-speed mode, consult the I²C

specification.

1001111

Float

Invalid

Table 4. Address Pins and Slave Address for the

ADS1112.

REGISTERS

The ADS1112 has two registers that are accessible via its

I²C port. The output register contains the result of the last

conversion; the configuration register allows the user to

change the ADS1112 operating mode and query the status

of the device.

I C DATA RATES

The I²C bus operates in one of three speed modes.

Standard mode allows a clock frequency of up to 100kHz;

fast mode permits a clock frequency of up to 400kHz; and

high-speed mode (also called Hs mode), which allows a

clock frequency of up to 3.4MHz. The ADS1112 is fully

compatible with all three modes.

OUTPUT REGISTER

No special action needs to be taken to use the ADS1112

in standard or fast modes, but high-speed mode must be

activated. To activate high-speed mode, send a special

address byte of 00001xxx following the START condition,

where xxx are bits unique to the Hs-capable master. This

byte is called the Hs master code. (Note that this is different

The 16-bit output register contains the result of the last

conversion in binary two’s complement format. Following

reset or power-up, the output register is cleared to zero,

and remains zero until the first conversion is completed.

The output register format is shown in Table 5.

BIT

NAME

D15

D14

D13

D12

D11

D10

Table 5. Output Register

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

Bits 6-5: INP

CONFIGURATION REGISTER

INP controls which two of the four analog inputs are used

to measure data in the ADC. This is shown in Table 7. By

selecting these bits, the ADS1112 can be used to measure

two differential channels or three single ended channels

referenced to AIN3.

The 8-bit configuration register can be used to control the

ADS1112 operating mode, input selection, data rate, and

PGA settings. The configuration register format is shown

in Table 6. The default setting is 8C_H.

BIT

ST/DRDY

INP1

INP0

PGA1

PGA0

INP1

INP0

IN−

IN+

NAME

DR1 DR0

(1)

AIN0

AIN2

AIN0

AIN1

AIN3

DEFAULT

Table 6. Configuration Register

(1)

Default setting.

Bit 7: ST/DRDY

Table 7. INP Bits.

The meaning of the ST/DRDY bit depends on whether it is

being written to or read from.

Bit 4: SC

In single conversion mode, writing a 1 to the ST/DRDY bit

causes a conversion to start, and writing a 0 has no effect.

In continuous conversion mode, the ADS1112 ignores the

value written to ST/DRDY.

SC controls whether the ADS1112 is in continuous

conversion or single conversion mode. When SC is 1, the

ADS1112 is in single conversion mode; when SC is 0, it is

in continuous conversion mode. The default setting is 0.

When read, ST/DRDY indicates whether the data in the

output register is new data. If ST/DRDY is 0, the data just

read from the output register is new, and has not been read

before. If ST/DRDY is 1, the data just read from the output

Bits 3-2: DR

Bits 3 and 2 control the ADS1112 data rate, as shown in

Table 8.

DR1

DR0

DATA RATE

240SPS

60SPS

RESOLUTION

12 Bits

The ADS1112 sets ST/DRDY to 0 when it writes data into

the output register. It sets ST/DRDY to 1 after any of the

bits in the configuration register have been read. (Note that

the read value of the bit is independent of the value written

to this bit.)

14 Bits

30SPS

15 Bits

(1)

15SPS

16 Bits

(1)

Default setting.

In continuous-conversion mode, use ST/DRDY to

determine when new conversion data is ready. If

ST/DRDY is 1, the data in the output register has already

been read, and is not new. If it is 0, the data in the output

Table 8. INP Bits.

Bits 1-0: PGA

Bits 1 and 0 control the ADS1112 gain setting, as shown

in Table 9.

In single-conversion mode, use ST/DRDY to determine

when a conversion has completed. If ST/DRDY is 1, the

output register data is old, and the conversion is still in

process; if it is 0, the output register data is the result of the

new conversion.

PGA1

PGA0

GAIN

(1)

Note that the output register is returned from the ADS1112

before the configuration register. The state of the

ST/DRDY bit applies to the data just read from the output

(1)

Default setting.

Table 9. PGA Bits

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

it will return the same data each time. New data will be

returned only when the output register has been updated.

READING FROM THE ADS1112

To read the output register and the configuration register

from the ADS1112, first address the ADS1112 for reading,

then read three bytes. The first two bytes will be the output

A timing diagram of a typical ADS1112 read operation is

shown in Figure 2.

WRITING TO THE ADS1112

It is not required to read the configuration register byte. It

is permissible to read fewer than three bytes during a read

operation.

To write to the configuration register, first address the

ADS1112 for writing, and send one byte. The byte will be

written to the configuration register. Note that data cannot

be written to the output register.

Reading more than three bytes from the ADS1112 has no

effect. All bytes following the third will be FF_H.

Writing more than one byte to the ADS1112 has no effect.

The ADS1112 will ignore any bytes sent to it after the first

one, and it will only acknowledge the first byte.

It is possible to ignore the ST/DRDY bit and read data from

the ADS1112 output register at any time, without regard to

whether a new conversion is complete. If the output

A timing diagram of a typical ADS1112 write operation is

shown in Figure 3.

Figure 2. Timing Diagram for Reading From the ADS1112

Figure 3. Timing Diagram for Writing To the ADS1112

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

Pull-up resistors are required on both the SDA and SCL

lines because I²C bus drivers are open-drain. The size of

these resistors depends on the bus operating speed and

capacitance of the bus lines. Higher-value resistors

consume less power, but increase the transition times on

the bus, limiting the bus speed. Lower-value resistors

allow higher speed at the expense of higher power

consumption. Long bus lines have higher capacitance and

require smaller pull-up resistors to compensate. The

resistors should not be too small; if they are, the bus drivers

may not be able to pull the bus lines low.

APPLICATIONS INFORMATION

The sections that follow give example circuits and tips for

using the ADS1112 in various situations.

BASIC CONNECTIONS

For many applications, connecting the ADS1112 is

extremely simple. A basic connection diagram for the

ADS1112 is shown in Figure 4.

CONNECTING MULTIPLE DEVICES

Connecting multiple ADS1112s to a single bus is trivial.

Using pins A1 and A0, the ADS1112 can be set to one of

eight different I²C addresses. An example showing three

ADS1112s is given in Figure 5. Up to eight ADS1112s

(using different states of pins A1 and A0) can be connected

to a single bus.

Figure 4. Typical Connections of the ADS1112

The fully differential voltage input of the ADS1112 is ideal

for connection to differential sources with moderately low

source impedance, such as bridge sensors and

thermistors. Although the ADS1112 can read bipolar

differential signals, it cannot accept negative voltages on

either input. It may be helpful to think of the ADS1112

positive voltage input as non−inverting, and of the negative

input as inverting.

When the ADS1112 is converting, it draws current in short

spikes. The 0.1µF bypass capacitor supplies the

momentary bursts of extra current needed from the supply.

The ADS1112 interfaces directly to standard mode, fast

mode, and high-speed mode I²C controllers. Any

microcontroller’s I²C peripheral, including master-only

and non-multiple-master I²C peripherals, will work with the

ADS1112.

The

ADS1112

does

not

perform

clock-stretching (that is, it never pulls the clock line low),

so it is not necessary to provide for this unless

clock-stretching devices are on the same I²C bus.

Figure 5. Connecting Multiple ADS1112s

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ꢢ

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

Note that only one set of pull-up resistors is needed per

bus. The pull-up resistor values may need to be lowered

slightly to compensate for the additional bus capacitance

presented by multiple devices and increased line length.

Figure 7. Using GPIO with a Single ADS1112

Bit-banging I²C with GPIO pins can be done by setting the

GPIO line to zero and toggling it between input and output

modes to apply the proper bus states. To drive the line

LOW, the pin is set to output a zero; to let the line go HIGH,

the pin is set to input. When the pin is set to input, the state

of the pin can be read; if another device is pulling the line

low, this will read as a zero in the port’s input register.

Note that no pull-up resistor is shown on the SCL line. In

this simple case, the resistor is not needed; the

microcontroller can simply leave the line on output, and set

it to one or zero as appropriate. It can do this because the

ADS1112 never drives its clock line LOW. This technique

can also be used with multiple devices, and has the

advantage of lower current consumption due to the

absence of a resistive pull-up.

If there are any devices on the bus that may drive their

clock lines LOW, the above method should not be used;

the SCL line should be high-Z or zero and a pull-up resistor

provided as usual. Note also that this cannot be done on

the SDA line in any case, because the ADS1112 does drive

the SDA line LOW from time to time, as do all I²C devices.

Figure 6. Connecting Multiple Device Types

Some microcontrollers have selectable strong pull-up

circuits built in to their GPIO ports. In some cases, these

can be switched on and used in place of an external pull-up

resistor. Weak pull-ups are also provided on some

microcontrollers, but usually these are too weak for I²C

communication. If there is any doubt about the matter, test

the circuit before committing it to production.

The TMP100 and DAC8574 devices detect their I²C bus

addresses based on the states of pins. In the example, the

TMP100 has the address 1001111, and the DAC8574 has

the address 1001100. Consult the DAC8574 and TMP100

data sheets, located at www.ti.com, for further details.

USING GPIO PORTS FOR I C

Most microcontrollers have programmable input/output

pins that can be set in software to act as inputs or outputs.

If an I²C controller is not available, the ADS1112 can be

connected to GPIO pins and the I²C bus protocol

simulated, or “bit-banged,” in software. An example of this

for a single ADS1112 is shown in Figure 7.

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SBAS282D − JUNE 2003 − REVISED MARCH 2004

SINGLE-ENDED INPUTS

Although the ADS1112 has two differential inputs, it can

easily measure three single-ended signals. A single-

ended connection scheme is shown in Figure 8. The

ADS1112 is configured for single-ended measurement by

grounding the AIN3 pin and applying the input signals to

any of AIN0, AIN1, or AIN2. Then the data is read out of

one of the inputs based on the selection on the

configuration register. The single-ended signal can range

from 0V to 2.048V. The ADS1112 loses no linearity

anywhere in its input range. Negative voltages cannot be

applied to this circuit because the ADS1112 can only

accept positive voltages.

Figure 9. Low-Side Current Measurement

It is suggested that the ADS1112 be operated at a gain of

8. The gain of the OPA335 can then be set lower. For a gain

of 8, the op amp should be set up to give a maximum output

voltage of no greater than 0.256V. If the shunt resistor is

sized to provide a maximum voltage drop of 50mV at

full-scale current, the full-scale input to the ADS1112 is

0.2V.

The ADS1112 is fabricated in

a small-geometry,

low-voltage process. The analog inputs feature protection

diodes to the supply rails. However, the current-handling

ability of these diodes is limited, and the ADS1112 can be

permanently damaged by analog input voltages that

remain more than approximately 300mV beyond the rails

for extended periods. One way to protect against

overvoltage is to place current-limiting resistors on the

input lines. The ADS1112 analog inputs can withstand

momentary currents of as large as 10mA.

Figure 8. Measuring Single-Ended Inputs

The ADS1112 input range is bipolar differential with

respect to the reference, that is, 2.048V. The single-ended

circuit shown in Figure 8 covers only half the ADS1112

input scale because it does not produce differentially

negative inputs; therefore, one bit of resolution is lost. If

AIN3 is set to a higher voltage, negative single-ended

voltage can be measured.

The previous paragraph does not apply to the I²C ports,

which can both be driven to 6V regardless of the supply.

If the ADS1112 is driven by an op amp with high-voltage

supplies, such as 12V, protection should be provided,

even if the op amp is configured so that it does not output

out-of-range voltages. Many op amps seek to one of the

supply rails immediately when power is applied, usually

before the input has stabilized; this momentary spike can

damage the ADS1112. This incremental damage results in

slow, long-term failure—which can be disastrous for

permanently installed, low-maintenance systems.

LOW-SIDE CURRENT MONITOR

Figure 9 shows a circuit for a low-side shunt-type current

monitor. The circuit reads the voltage across a shunt

resistor, which is sized as small as possible while still

giving a readable output voltage. This voltage is amplified

by an OPA335 low-drift op amp, and the result is read by

the ADS1112.

If an op amp or other front-end circuitry is used with the

ADS1112, its performance characteristics must be taken

into account.

PACKAGE OPTION ADDENDUM

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14-Oct-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ADS1112IDGSR

ADS1112IDGSRG4

ADS1112IDGST

ADS1112IDGSTG4

ADS1112IDRCR

ADS1112IDRCRG4

ADS1112IDRCT

ACTIVE

VSSOP

VSON

DGS

DRC

2500 RoHS & Green Call TI | NIPDAUAG

2500 RoHS & Green Call TI

RoHS & Green Call TI | NIPDAUAG

Level-2-260C-1 YEAR

-40 to 85

BHU

BHV

Samples

250

RoHS & Green

Call TI

2500 RoHS & Green

NIPDAU

VSON

250

RoHS & Green

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

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Addendum-Page 1

PACKAGE OPTION ADDENDUM

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14-Oct-2022

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1112IDRCR

ADS1112IDRCT

VSON

DRC

2500

250

330.0

180.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS1112IDRCR

ADS1112IDRCT

VSON

DRC

2500

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

8X 0.5

3.1

2.9

NOTE 3

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

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EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

SYMM

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

SYMM

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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GENERIC PACKAGE VIEW

DRC 10

3 x 3, 0.5 mm pitch

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226193/A

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PACKAGE OUTLINE

DRC0010J

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

SYMM

2.4 0.1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

0.5

0.3

10X

4218878/B 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

10X (0.24)

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218878/B 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DRC0010J

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

10X (0.6)

(1.53)

10X (0.24)

(1.06)

SYMM

(0.63)

8X (0.5)

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4218878/B 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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ADS1112IDRCR [TI]

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