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ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

ADS1118-Q1 具有内部基准和温度传感器的汽车类、低功耗、兼容 SPI 的

16 位模数转换器

1 特性

3 说明

1

•

符合汽车类应用标准

具有符合 AEC-Q100 的下列结果：

ADS1118-Q1 是一款精密的低功耗 16 位模数转换器

(ADC)，其具备测量最常见传感器信号所需的全部功

能。 ADS1118-Q1 集成了可编程增益放大器 (PGA)、

电压基准、振荡器和高精度温度传感器。凭借这些功

能以及 2V 至 5.5V 的宽电源电压范围，

–

温度等级 1：-40°C 至 +125°C

人体放电模式 (HBM) 静电放电 (ESD) 分类等级

2

–

组件充电模式 (CDM) ESD 分类等级 C6

ADS1118-Q1 非常适用于功率及空间受限型传感器测

量应用。

•

宽电源电压范围：2V 至 5.5V

低流耗：

ADS1118-Q1 以高达 860 次/秒 (SPS) 的采样数据传

输速率进行转换。 PGA 的输入范围为 ±256mV 至 ±

6.144V，支持以高分辨率测量大信号和小信号。该器

件通过输入复用器 (MUX) 测量双路差分输入或四路单

端输入。高精度温度传感器用于监控系统级温度或对

热电偶进行冷结点补偿。

–

连续模式时：只有 150μA

单次模式：自动断电

•

可编程数据传输速率范围：8SPS 至 860SPS

单周期稳定

内部低漂移电压基准

内部温度传感器：

2°C 误差（最大值）

ADS1118-Q1 可选择以连续转换模式或单次模式运

行。该器件在单次模式下完成一次转换后便会自动断

电。在空闲状态下，单次模式会显著降低流耗。所有

数据均通过串行外设接口 (SPI™) 进行传输。

ADS1118-Q1 的额定工作温度范围 -40°C 至 +125°

C。

•

内部振荡器

内部可编程增益放大器 (PGA)

四个单端或两个差分输入

2 应用

•

电池管理系统

车用传感器

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

–

热电偶

ADS1118-Q1

VSSOP (10)

3.00mm × 3.00mm

电阻式温度检测器 (RTD)

压力和应力计传感器

电化学气体传感器

颗粒物传感器

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS740

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

K 型热电偶测量

使用集成温度传感器进行冷结点补偿

3.3 V

0.1 ꢁF

AIN0

VDD

ADS1118-Q1

Voltage

Reference

AIN1

SCLK

Digital Filter

and

Interface

16-bit

ûꢀ

ADC

CS

PGA

Mux

DOUT/DRDY

DIN

3.3 V

AIN2

AIN3

Temperature

Sensor

Oscillator

GND

2

ADS1118-Q1

www.ti.com.cn

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

9.3 Feature Description................................................. 16

9.4 Device Functional Modes........................................ 20

9.5 Programming........................................................... 21

9.6 Register Maps......................................................... 24

10 Application and Implementation........................ 26

10.1 Application Information.......................................... 26

10.2 Typical Application ............................................... 31

11 Power-Supply Recommendations ..................... 34

11.1 Power-Supply Sequencing.................................... 34

11.2 Power-Supply Decoupling..................................... 34

12 Layout................................................................... 35

12.1 Layout Guidelines ................................................. 35

12.2 Layout Example .................................................... 36

13 器件和文档支持 ..................................................... 37

13.1 文档支持................................................................ 37

13.2 社区资源................................................................ 37

13.3 商标....................................................................... 37

13.4 静电放电警告......................................................... 37

13.5 Glossary................................................................ 37

14 机械、封装和可订购信息....................................... 37

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 3

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Electrical Characteristics........................................... 6

7.6 Timing Requirements: Serial Interface...................... 8

7.7 Switching Characteristics: Serial Interface................ 8

7.8 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 14

8.1 Noise Performance ................................................. 14

Detailed Description ............................................ 15

9.1 Overview ................................................................. 15

9.2 Functional Block Diagram ....................................... 15

8

9

4 修订历史记录

Changes from Original (October 2015) to Revision A

Page

•

已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1

3

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

5 Device Comparison Table

MAXIMUM SAMPLE

INPUT CHANNELS

Differential

(Single-Ended)

RESOLUTION

(Bits)

SPECIAL

FEATURES

DEVICE

RATE

(SPS)

PGA

INTERFACE

ADS1118-Q1

ADS1018-Q1

ADS1115-Q1

ADS1015-Q1

16

12

16

12

860

3300

860

2 (4)

Yes

SPI

I²C

Temperature sensor

Comparator

3300

Comparator

6 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

DIN

SCLK

1

2

3

4

5

10 DIN

DOUT/

9

8

7

6

CS

GND

AIN0

AIN1

DRDY

VDD

AIN3

AIN2

AIN1

Pin Functions

NAME

TYPE

DESCRIPTION

NO.

1

SCLK

CS

Digital input

Supply

Serial clock input

2

Chip select; active low. Connect to GND if not used.

Ground

3

GND

4

AIN0

Analog input

Supply

Analog input 0. Leave unconnected or tie to VDD if not used.

Analog input 1. Leave unconnected or tie to VDD if not used.

Analog input 2. Leave unconnected or tie to VDD if not used.

Analog input 3. Leave unconnected or tie to VDD if not used.

5

AIN1

6

AIN2

7

AIN3

8

VDD

Power supply. Connect a 0.1-µF power supply decoupling capacitor to GND.

Serial data output combined with data ready; active low

Serial data input

9

DOUT/DRDY

DIN

Digital output

Digital input

10

4

ADS1118-Q1

www.ti.com.cn

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

5.5

UNIT

V

Power-supply voltage

Analog input voltage

Digital input voltage

Input current, continuous

VDD to GND

AIN0, AIN1, AIN2, AIN3

DIN, DOUT/DRDY, SCLK, CS

Any pin except power supply pins

Junction, T_J

GND – 0.3

–10

VDD + 0.3

10

V

mA

–40

150

Temperature

°C

Storage, T_stg

–60

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

Charged device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

VDD

Power supply

VDD to GND

2

5.5

V

ANALOG INPUTS⁽¹⁾

FSR

Full-scale input voltage⁽²⁾

V_IN= V_(AINP)- V_(AINN)

See Table 3

V_(AINx)

Absolute input voltage

GND

–40

VDD

125

V

DIGITAL INPUTS

Input voltage

TEMPERATURE

T_AOperating ambient temperature

°C

(1) AINP and AINN denote the selected positive and negative inputs. AINx denotes one of the four available analog inputs.

(2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be

applied to this device.

7.4 Thermal Information

ADS1118-Q1

THERMAL METRIC⁽¹⁾

DGS (VSSOP)

10 PINS

186.8

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

51.5

108.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.7

ψ_JB

106.5

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

5

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

7.5 Electrical Characteristics

Maximum and minimum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at VDD = 3.3 V, data rate = 8 SPS, and FSR = ±2.048 V (unless otherwise noted).

PARAMETER

ANALOG INPUTS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FSR = ±6.144 V⁽¹⁾

FSR = ±4.096 V⁽¹⁾, FSR = ±2.048 V

FSR = ±1.024 V

8

6

Common-mode input impedance

Differential input impedance

MΩ

3

FSR = ±0.512 V, FSR = ±0.256 V

FSR = ±6.144 V⁽¹⁾

FSR = ±4.096 V⁽¹⁾

100

22

15

MΩ

kΩ

FSR = ±2.048 V

4.9

2.4

710

FSR = ±1.024 V

FSR = ±0.512 V, FSR = ±0.256 V

SYSTEM PERFORMANCE

Resolution (no missing codes)

Data rate

16

Bits

DR

INL

8, 16, 32, 64, 128, 250, 475, 860

–10%

SPS

Data rate variation

Output noise

All data rates

10%

See Noise Performance section

Integral nonlinearity

DR = 8 SPS, FSR = ±2.048 V⁽²⁾

FSR = ±2.048 V, differential inputs

FSR = ±2.048 V, single-ended inputs

FSR = ±2.048 V

1

LSB

±0.1

±0.25

0.002

0.2

±2

Offset error

Offset drift

LSB/°C

LSB/V

LSB

Offset power-supply rejection

Offset channel match

Gain error⁽³⁾

FSR = ±2.048 V, dc supply variation

Match between any two inputs

FSR = ±2.048 V, T_A= 25°C

FSR = ±0.256 V

0.6

0.01%

7

0.15%

Gain drift⁽³⁾⁽⁴⁾

FSR = ±2.048 V

FSR = ±6.144 V⁽¹⁾

5

40 ppm/°C

ppm/V

5

Gain power-supply rejection

Gain match⁽³⁾

10

Match between any two gains

Match between any two inputs

At DC, FSR = ±0.256 V

0.01%

105

100

90

0.1%

Gain channel match

At DC, FSR = ±2.048 V

CMRR Common-mode rejection ratio

At DC, FSR = ±6.144 V⁽¹⁾

f_CM= 50 Hz, DR = 860 SPS

f_CM= 60 Hz, DR = 860 SPS

dB

105

TEMPERATURE SENSOR

Temperature range

–40

125

°C

Temperature resolution

0.03125

0.2

°C/LSB

T_A= 0°C to 70°C

T_A= –40°C to +125°C

vs supply

±1

±2

°C

Accuracy

0.4

0.03125

±0.25

°C/V

(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be

applied to this device.

(2) Best-fit INL; covers 99% of full-scale.

(3) Includes all errors from onboard PGA and voltage reference.

(4) Maximum value specified by characterization.

6

ADS1118-Q1

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ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

Electrical Characteristics (continued)

Maximum and minimum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at VDD = 3.3 V, data rate = 8 SPS, and FSR = ±2.048 V (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS/OUTPUTS

V_IH

V_IL

V_OH

V_OL

I_H

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

Input leakage, high

0.7 VDD

GND

VDD

V

0.2 VDD

I_OH= 1 mA

0.8 VDD

GND

V

I_OL= 1 mA

V_IH= 5.5 V

V_IL= GND

0.2 VDD

10

V

–10

μA

I_L

Input leakage, low

–10

10

POWER SUPPLY

Power-down, T_A= 25°C

Power-down

0.5

2

5

I_VDD

Supply current

μA

Operating, T_A= 25°C

Operating

150

200

300

VDD = 5 V

0.9

0.5

0.3

P_D

Power dissipation

VDD = 3.3 V

mW

VDD = 2 V

7

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

7.6 Timing Requirements: Serial Interface

over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted)

MIN

100

200

250

100

MAX

UNIT

ns

t_CSSC

t_SCCS

t_CSH

Delay time, CS falling edge to first SCLK rising edge⁽¹⁾

Delay time, final SCLK falling edge to CS rising edge

Pulse duration, CS high

ns

t_SCLK

t_SPWH

SCLK period

ns

Pulse duration, SCLK high

ns

t_SPWL

Pulse duration, SCLK low⁽²⁾

28

ms

ns

t_DIST

Setup time, DIN valid before SCLK falling edge

Hold time, DIN valid after SCLK falling edge

Hold time, SCLK rising edge to DOUT invalid

50

0

t_DIHD

t_DOHD

ns

(1) CS can be tied low permanently in case the serial bus is not shared with any other device.

(2) Holding SCLK low longer than 28 ms resets the SPI interface.

7.7 Switching Characteristics: Serial Interface

over operating ambient temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time,

CS falling edge to DOUT driven

t_CSDOD

t_DOPD

DOUT load = 20 pF || 100 kΩ to GND

100

ns

Propagation delay time,

SCLK rising edge to valid new DOUT

DOUT load = 20 pF || 100 kΩ to GND

0

50

ns

Propagation delay time,

CS rising edge to DOUT high impedance

t_CSDOZ

100

t_CSH

CS

t_SCLK

t_CSSC

t_SPWH

t_SCCS

SCLK

t_DIHD

t_SPWL

t_SCSC

t_DIST

DIN

t_DOHD

t_CSDOD

t_CSDOZ

Hi-Z

t_DOPD

Hi-Z

DOUT

Figure 1. Serial Interface Timing

8

ADS1118-Q1

www.ti.com.cn

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

7.8 Typical Characteristics

at T_A= 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted)

4

3

4

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

3

2

1

0

-1

-2

-3

-4

−1

−2

−3

−4

−60 −40 −20

0

20

40

60

80 100 120 140

-2.048

-1.024

0

1.024

2.048

Temperature (°C)

G028

Input Signal (V)

DR = 860 SPS, diff Inputs; includes noise, offset, and gain errors

Figure 3. Data Rate vs Temperature

Figure 2. Total Error vs Input Signal

15

5

4

3

2

1

0

FSR = 0.25ꢀ V

FSR = 0.512 V

12.5

T_A= −40°C

T_A= 25°C

T_A= 125°C

FSR = 2.04ꢁ V

FSR = ꢀ.144 V

10

7.5

5

−1

−2

−3

−4

−5

2.5

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

−2

−1.5

−1

−0.5

0

0.5

1

1.5

2

Supply Voltage (V)

Input Signal (V)

G010

FSR = ±2.048 V, DR = 8 SPS, VDD = 3.3 V, best fit

Figure 4. INL vs Supply Voltage

Figure 5. INL vs Input Signal

10

8

5

T_A= −40°C

T_A= 25°C

T_A= 125°C

T_A= −40°C

T_A= 25°C

T_A= 125°C

4

6

3

2

4

2

1

0

−2

−4

−6

−8

−10

−1

−2

−3

−4

−5

−0.5 −0.4 −0.2 −0.1

0

0.1

0.2

0.4

0.5

−2

−1.5

−1

−0.5

0

0.5

1

1.5

2

Input Signal (V)

FSR = ±0.512 V, DR = 8 SPS, VDD = 3.3 V, best fit

FSR = ±2.048 V, DR = 8 SPS, VDD = 5 V, best fit

Figure 6. INL vs Input Signal

Figure 7. INL vs Input Signal

9

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

at T_A= 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted)

10

12

10

8

T_A= −40°C

T_A= 25°C

T_A= 125°C

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

8

6

4

2

0

6

−2

−4

−6

−8

−10

4

2

0

−0.5 −0.4 −0.2 −0.1

0

0.1

0.2

0.4

0.5

−60 −40 −20

0

20

40

60

80 100 120 140

Input Signal (V)

Temperature (°C)

G015

FSR = ±0.512 V, DR = 8 SPS, VDD = 5 V, best fit

FSR = ±2.048 V, DR = 8 SPS, best fit

Figure 8. INL vs Input Signal

Figure 9. INL vs Temperature

60

16

AIN0 to GND

AIN1 to GND

AIN2 to GND

AIN3 to GND

T_A= −40°C

T_A= 25°C

T_A= 125°C

14

12

10

8

40

20

0

6

−20

−40

−60

4

2

0

−40

−20

0

20

40

60

80

100

120

8

16

32

64

128

250

475

860

Temperature (°C)

Data Rate (SPS)

G004

FSR = ±2.048 V, best fit

Figure 11. Single-Ended Offset Voltage vs Temperature

Figure 10. INL vs Data Rate

60

40

AIN0 to GND

AIN1 to GND

AIN2 to GND

AIN3 to GND

AIN0 to AIN1

30

20

AIN0 to AIN3

AIN1 to AIN3

AIN2 to AIN3

20

10

0

−10

−20

−30

−40

−20

−40

−60

2

2.5

3

3.5

4

4.5

5

−40

−20

0

20

40

60

80

100

120

Supply Voltage (V)

Temperature (°C)

G005

G006

Figure 12. Single-Ended Offset Voltage vs Supply

Figure 13. Differential Offset Voltage vs Temperature

10

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ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

Typical Characteristics (continued)

at T_A= 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted)

15

10

5

40

AIN0 to AIN1

AIN0 to AIN3

AIN1 to AIN3

AIN2 to AIN3

30

20

10

0

−10

−20

−30

−40

0

2

2.5

3

3.5

4

4.5

5

Supply Voltage (V)

G007

G046

Offset Drift (LSB/°C)

FSR = ±2.048 V, T_A= –40°C to +125°C, mux = AIN0 to AIN3,

540 units from 3 production lots

Figure 14. Differential Offset Voltage vs Supply

Figure 15. Offset Drift Histogram

0.05

0.04

0.03

0.02

0.01

0

200

150

100

50

−0.01

−0.02

−0.03

−0.04

−0.05

FSR = 0.256 ꢀ

FSR = 0.512 ꢀ

FSR = 1.024 ꢀ

FSR = 2.048 ꢀ

FSR = 4.0ꢁ6 ꢀ

FSR = 6.144 ꢀ

0

−40 −20

0

20

40

60

80

100 120 140

Temperature (°C)

Offset (µV)

G000

FSR = ±2.048 V,

540 units from 3 production lots

Figure 17. Gain Error vs Temperature

Figure 16. Offset Histogram

0.15

0.1

200

150

100

50

0.05

0

FSR = ±256 mV

FSR = ±2.048 V

-0.05

-0.1

-0.15

0

2

2.5

3

3.5

4

4.5

5

5.5

Supply Voltage (V)

Gain Error (%)

G000

FSR = ±2.048 V, 540 units from 3 production lots

Figure 19. Gain Error Histogram

Figure 18. Gain Error vs Supply

11

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ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

Typical Characteristics (continued)

at T_A= 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted)

1

40

Average Temperature Error

Average ± 3 sigma

Average ± 6 sigma

0.8

35

30

25

20

15

10

5

0.6

0.4

0.2

0

−0.2

−0.4

−0.6

−0.8

−1

0

−40

−20

0

20

40

60

80

100

120

Temperature (°C)

G023

Temperature Error (èC)

T_A= –40°C, 48 units from 3 production lots

Figure 21. Temperature Sensor Error Histogram

Figure 20. Temperature Sensor Error vs Temperature

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

0

Temperature Error (èC)

T_A= 0°C, 48 units from 3 production lots

T_A= 25°C, 48 units from 3 production lots

Figure 22. Temperature Sensor Error Histogram

Figure 23. Temperature Sensor Error Histogram

40

35

30

25

20

15

10

5

35

30

25

20

15

10

5

0

Temperature Error (èC)

T_A= 70°C, 48 units from 3 production lots

T_A= 125°C, 48 units from 3 production lots

Figure 24. Temperature Sensor Error Histogram

Figure 25. Temperature Sensor Error Histogram

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Typical Characteristics (continued)

at T_A= 25°C, VDD = 3.3 V, and FSR = ±2.048 V (unless otherwise noted)

300

250

200

150

100

50

5

4.5

4

VDD = 2.0 V

VDD = 3.3 V

VDD = 5.0 V

VDD = 5 V

3.5

3

2.5

2

VDD = 3.3 V

VDD = 2 V

1.5

1

0.5

0

-40 -20

0

20

40

60

80

100 120 140

−40 −20

0

20

40

60

80

100 120 140

Temperature (°C)

G003

Figure 26. Operating Current vs Temperature

Figure 27. Power-Down Current vs Temperature

0

-10

-20

-30

-40

-50

-60

-70

-80

1

10

100

1k

10k

Input Frequency (Hz)

DR = 8 SPS

Figure 28. Digital Filter Frequency Response

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8 Parameter Measurement Information

8.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converter (ADC) architecture is based on the principle of oversampling. The

input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency), and subsequently filtered and

decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between

modulator frequency and output data rate is called the oversampling ratio (OSR). Increasing the OSR, and thus

reducing the output data rate, optimizes the noise performance of the ADC. That is, the input-referred noise

reduces when the output data rate is reduced because more samples of the internal modulator are averaged to

yield one conversion result. Increasing the gain also reduces the input-referred noise, and is particularly useful

when measuring low-level signals.

Table 1 and Table 2 summarize the device noise performance. Data are representative of typical noise

performance at T_A= 25°C with the inputs shorted together externally. Table 1 show the input-referred noise in

units of μV_RMSfor the conditions shown. Note that µV_PPvalues are shown in parenthesis. Table 2 shows the

corresponding data in effective number of bits (ENOB) calculated from μV_RMSvalues using Equation 1. The

noise-free bits calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

ENOB = ln (FSR / V_RMS-Noise) / ln(2)

(1)

(2)

Noise-Free Bits = ln (FSR / V_PP-Noise) / ln(2)

Table 1. Noise in μV_RMS(μV_PP) at VDD = 3.3 V

FULL-SCALE RANGE (FSR)

DATA RATE

(SPS)

±6.144 V

±4.096 V

±2.048 V

62.5 (62.5)

62.5 (84.03)

62.5 (79.08)

62.5 (118.63)

±1.024 V

±0.512 V

±0.256 V

7.81 (7.81)

7.81 (12.35)

7.81 (18.53)

7.81 (25.95)

7.81 (35.83)

8

187.5 (187.5)

187.5 (252.09)

187.5 (266.92)

187.5 (430.06)

125.0 (125.0)

125.0 (148.28)

125.0 (227.38)

125.0 (266.93)

31.25 (31.25)

31.25 (39.54)

31.25 (56.84)

31.25 (64.26)

15.62 (15.62)

15.62 (16.06)

15.62 (32.13)

15.62 (40.78)

16

32

64

128

250

475

860

Table 2. ENOB from RMS Noise (Noise-Free Bits from Peak-to-Peak Noise) at VDD = 3.3 V

FULL-SCALE RANGE (FSR)

DATA RATE

(SPS)

±6.144 V

16 (16)

±4.096 V

16 (16)

±2.048 V

16 (16)

±1.024 V

16 (16)

±0.512 V

16 (16)

±0.256 V

16 (16)

8

16

16 (16)

32

16 (16)

64

16 (16)

128

250

475

860

16 (16)

16 (15.33)

16 (14.75)

16 (14.26)

16 (13.8)

16 (15.57)

16 (15.49)

16 (14.8)

16 (15.75)

16 (15.13)

16 (14.9)

16 (15.57)

16 (15.66)

16 (15.07)

16 (15.66)

16 (15.13)

16 (14.95)

16 (15.96)

16 (14.95)

16 (14.61)

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9 Detailed Description

9.1 Overview

The ADS1118-Q1 is a very small, low-power, 16-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC). The

ADS1118-Q1 consists of a ΔΣ ADC core with adjustable gain, an internal voltage reference, a clock oscillator,

and an SPI. This device is also a highly linear and accurate temperature sensor. All of these features are

intended to reduce required external circuitry and improve performance. The Functional Block Diagram section

shows the ADS1118-Q1 functional block diagram.

The ADS1118-Q1 ADC core measures a differential signal, V_IN, that is the difference of V_(AINP)and V_(AINN). The

converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This

architecture results in a very strong attenuation in any common-mode signals. Input signals are compared to the

internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a

code proportional to the input voltage.

The ADS1118-Q1 has two available conversion modes: single-shot and continuous-conversion. In single-shot

mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal

conversion register. The device then enters a power-down state. This mode is intended to provide significant

power savings in systems that require only periodic conversions or when there are long idle periods between

conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input signal as

soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed

data rate. Data can be read at any time and always reflect the most recently completed conversion.

9.2 Functional Block Diagram

VDD

Device

Voltage

Reference

Mux

CS

AIN0

SCLK

Serial

Peripheral

Interface

16-Bit ΔΣ

ADC

PGA

AIN1

DIN

DOUT/DRDY

AIN2

AIN3

Temperature

Sensor

Oscillator

GND

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9.3 Feature Description

9.3.1 Multiplexer

The ADS1118-Q1 contains an input multiplexer (mux), as shown in Figure 29. Either four single-ended or two

differential signals can be measured. Additionally, AIN0, AIN1, and AIN2 can be measured differentially to AIN3.

The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured,

the negative input of the ADC is internally connected to GND by a switch within the multiplexer.

VDD

Device

AIN0

VDD

GND

AIN_P

AIN_N

AIN1

VDD

GND

AIN2

VDD

GND

AIN3

GND

Figure 29. Input Multiplexer

When measuring single-ended inputs, the device does not output negative codes. These negative codes indicate

negative differential signals; that is, (V_(AINP)– V_(AINN)) < 0. Electrostatic discharge (ESD) diodes to VDD and GND

protect the ADS1118-Q1 inputs. To prevent the ESD diodes from turning on, keep the absolute voltage on any

input within the range given in Equation 3:

GND – 0.3 V < V_(AINx)< VDD + 0.3 V

(3)

If the voltages on the input pins can possibly violate these conditions, use external Schottky diodes and series

resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).

Also, overdriving one unused input on the ADS1118-Q1 may affect conversions currently taking place on other

input pins. If overdriving unused inputs is possible, clamp the signal with external Schottky diodes.

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Feature Description (continued)

9.3.2 Analog Inputs

The ADS1118-Q1 uses a switched-capacitor input stage where capacitors are continuously charged and then

discharged to measure the voltage between AIN_Pand AIN_N. This frequency at which the input signal is sampled

is called the sampling frequency or the modulator frequency (f_(MOD)). The ADS1118-Q1 has a 1 MHz internal

oscillator which is further divided by a factor of 4 to generate the modulator frequency at 250 kHz. The capacitors

used in this input stage are small, and to external circuitry, the average loading appears resistive. This structure

is shown in Figure 30. The resistance is set by the capacitor values and the rate at which they are switched.

Figure 31 shows the setting of the switches illustrated in Figure 30. During the sampling phase, switches S₁are

closed. This event charges C_A1to V_(AINP), C_A2to V_(AINN), and C_Bto (V_(AINP)– V_(AINN)). During the discharge phase,

S₁is first opened and then S₂is closed. Both C_A1and C_A2then discharge to approximately 0.7 V and C_B

discharges to 0 V. This charging draws a very small transient current from the source driving the ADS1118-Q1

analog inputs. The average value of this current can be used to calculate the effective impedance (Z_eff), where

Z_eff= V_IN/ I_AVERAGE

.

0.7 V

C_A1

Z_CM

Equivalent

Circuit

AIN_P

AIN_N

0.7 V

AIN_P

AIN_N

S₁

S₂

C_B

Z_DIFF

Z_CM

C_A2

f_(MOD)= 250 kHz

0.7 V

Figure 30. Simplified Analog Input Circuit

t_SAMPLE

ON

S₁

OFF

ON

S₂

OFF

Figure 31. S₁and S₂Switch Timing

Common-mode input impedance is measured by applying a common-mode signal to the shorted AIN_Pand AIN_N

inputs and measuring the average current consumed by each pin. The common-mode input impedance changes

depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 30, the

common-mode input impedance is Z_CM

.

The differential input impedance is measured by applying a differential signal to AIN_Pand AIN_Ninputs where one

input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and

scales with the full-scale range. In Figure 30, the differential input impedance is Z_DIFF

.

Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance,

the ADS1118-Q1 input impedance may affect the measurement accuracy. For sources with high output

impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain

errors. Consider all of these factors in high-accuracy applications.

The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most

applications, this input impedance drift is negligible, and can be ignored.

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Feature Description (continued)

9.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented in front of the ADS1118-Q1 ΔΣ ADC core. The full-scale

range is configured by bits PGA[2:0] in the Config register, and can be set to ±6.144 V, ±4.096 V, ±2.048 V,

±1.024 V, ±0.512 V, or ±0.256 V.

Table 3 shows the FSR together with the corresponding LSB size. Calculate the LSB size from the full-scale

voltage by the formula shown in Equation 4. However, make sure that the analog input voltage never exceeds

the analog input voltage range limit given in the Electrical Characteristics. If VDD greater than 4 V is used, the

±6.144-V full-scale range allows input voltages to extend up to the supply. Note though that in this case, or

whenever the supply voltage is less than the full-scale range (for example, VDD = 3.3 V and full-scale range =

±4.096 V), a full-scale ADC output code cannot be obtained. This inability means that some dynamic range is

lost.

LSB = FSR / 2¹⁶

(4)

Table 3. Full-Scale Range and Corresponding LSB Size

FSR

LSB SIZE

187.5 μV

125 μV

±6.144 V⁽¹⁾

±4.096 V⁽¹⁾

±2.048 V

±1.024 V

±0.512 V

±0.256 V

62.5 μV

31.25 μV

15.625 μV

7.8125 μV

(1) This parameter expresses the full-scale range of the ADC scaling.

Do not apply more than VDD + 0.3 V to this device.

9.3.4 Voltage Reference

The ADS1118-Q1 has an integrated voltage reference. An external reference cannot be used with this device.

Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included

in the gain error and gain drift specifications in the Electrical Characteristics.

9.3.5 Oscillator

The ADS1118-Q1 has an integrated oscillator running at 1 MHz. No external clock is required to operate the

device. Note that the internal oscillator drifts over temperature and time. The output data rate scales

proportionally with the oscillator frequency.

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9.3.6 Temperature Sensor

The ADS1118-Q1 offers an integrated precision temperature sensor. To enable the temperature sensor mode,

set bit TS_MODE = 1 in the Config register. Temperature data are represented as a 14-bit result that is left-

justified within the 16-bit conversion result. Data are output starting with the most significant byte (MSB). When

reading the two data bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit

LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format, as shown in

Table 4.

Table 4. 14-Bit Temperature Data Format

TEMPERATURE (°C)

DIGITAL OUTPUT (BINARY)

01 0000 0000 0000

00 1111 1111 1111

00 1100 1000 0000

00 1001 0110 0000

00 0110 0100 0000

00 0011 0010 0000

00 0000 0000 1000

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1000

11 1100 1110 0000

11 1011 0000 0000

HEX

1000

0FFF

0C80

0960

0640

0320

0008

0001

0000

3FF8

3CE0

3B00

128

127.96875

100

75

50

25

0.25

0.03125

0

–0.25

–25

–40

9.3.6.1 Converting from Temperature to Digital Codes

For positive temperatures:

Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary

code in a 14-bit, left justified format with the MSB = 0 to denote the positive sign.

Example: 50°C / (0.03125°C/count) = 1600 = 0640h = 00 0110 0100 0000

For negative temperatures:

Generate the twos complement of a negative number by complementing the absolute binary number and

adding 1. Then, denote the negative sign with the MSB = 1.

Example: |–25°C| / (0.03125°C/count) = 800 = 0320h = 00 0011 0010 0000

Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000

9.3.6.2 Converting from Digital Codes to Temperature

To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0,

simply multiply the decimal code by 0.03125°C to obtain the result. If the MSB = 1, subtract 1 from the result

and complement all of the bits. Then, multiply the result by –0.03125°C.

Example: The device reads back 0960h: 0960h has an MSB = 0.

0960h × 0.03125°C = 2400 × 0.03125°C = 75°C

Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.

Subtract 1 and complement the result: 3CE0h → 0320h

0320h × (–0.03125°C) = 800 × (–0.03125°C) = –25°C

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9.4 Device Functional Modes

9.4.1 Reset and Power-Up

When the ADS1118-Q1 powers up, the device resets. As part of the reset process, the ADS1118-Q1 sets all bits

in the Config register to the respective default settings. By default, the ADS1118-Q1 enters a power-down state

at start-up. The device interface and digital blocks are active, but no data conversions are performed. The initial

power-down state of the ADS1118-Q1 relieves systems with tight power-supply requirements from encountering

a surge during power-up.

9.4.2 Operating Modes

The ADS1118-Q1 operates in one of two modes: continuous-conversion or single-shot. The MODE bit in the

Config register selects the respective operating mode.

9.4.2.1 Single-Shot Mode and Power-Down

When the MODE bit in the Config register is set to 1, the ADS1118-Q1 enters a power-down state, and operates

in single-shot mode. This power-down state is the default state for the ADS1118-Q1 when power is first applied.

Although powered down, the device still responds to commands. The ADS1118-Q1 remains in this power-down

state until a 1 is written to the single-shot (SS) bit in the Config register. When the SS bit is asserted, the device

powers up, resets the SS bit to 0, and starts a single conversion. When conversion data are ready for retrieval,

the device powers down again. Writing a 1 to the SS bit while a conversion is ongoing has no effect. To switch to

continuous-conversion mode, write a 0 to the MODE bit in the Config register.

9.4.2.2 Continuous-Conversion Mode

In continuous-conversion mode (MODE bit set to 0), the ADS1118-Q1 continuously performs conversions. When

a conversion completes, the ADS1118-Q1 places the result in the Conversion register and immediately begins

another conversion. To switch to single-shot mode, write a 1 to the MODE bit in the Config register, or reset the

device.

9.4.3 Duty Cycling for Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more

samples of the internal modulator are averaged to yield one conversion result. In applications where power

consumption is critical, the improved noise performance at low data rates may not be required. For these

applications, the ADS1118-Q1 supports duty cycling that can yield significant power savings by periodically

requesting high data-rate readings at an effectively lower data rate.

For example, an ADS1118-Q1 in power-down state with a data rate set to 860 SPS can be operated by a

microcontroller that instructs a single-shot conversion every 125 ms (8 SPS). A conversion at 860 SPS only

requires approximately 1.2 ms; therefore, the ADS1118-Q1 enters power-down state for the remaining 123.8 ms.

In this configuration, the ADS1118-Q1 consumes approximately 1/100th the power that is otherwise consumed in

continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the master

controller. The ADS1118-Q1 offers lower data rates that do not implement duty cycling and also offers improved

noise performance, if required.

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9.5 Programming

9.5.1 Serial Interface

The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three

signals (SCLK, DIN, and DOUT/DRDY, with CS tied low). The interface is used to read conversion data, read

from and write to registers, and control device operation.

9.5.2 Chip Select (CS)

The chip select pin (CS) selects the ADS1118-Q1 for SPI communication. This feature is useful when multiple

devices share the same serial bus. Keep CS low for the duration of the serial communication. When CS is taken

high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state,

DOUT/DRDY cannot provide data-ready indication. In situations where multiple devices are present and

DOUT/DRDY must be monitored, lower CS periodically. At this point, the DOUT/DRDY pin either immediately

goes high to indicate that no new data are available, or immediately goes low to indicate that new data are

present in the Conversion register and are available for transfer. New data can be transferred at any time without

concern of data corruption. When a transmission starts, the current result is locked into the output shift register

and does not change until the communication completes. This system avoids any possibility of data corruption.

9.5.3 Serial Clock (SCLK)

The serial clock pin (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and

DOUT/DRDY pins into and out of the ADS1118-Q1. Even though the input has hysteresis, keep SCLK as clean

as possible to prevent glitches from accidentally shifting the data. To reset the serial interface, hold SCLK low for

28 ms, and the next SCLK pulse starts a new communication cycle. Use this time-out feature to recover

communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK

low.

9.5.4 Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data to the ADS1118-Q1. The device latches data on

DIN at the SCLK falling edge. The ADS1118-Q1 never drives the DIN pin.

9.5.5 Data Output and Data Ready (DOUT/DRDY)

The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from

the ADS1118-Q1. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY is also used to

indicate that a conversion is complete and new data are available. This pin transitions low when new data are

ready for retrieval. DOUT/DRDY is also able to trigger a microcontroller to start reading data from the ADS1118-

Q1. In continuous-conversion mode, DOUT/DRDY transitions high again 8 µs before the next data ready signal

(DOUT/DRDY low) if no data are retrieved from the device. This transition is shown in Figure 32. Complete the

data transfer before DOUT/DRDY returns high.

CS⁽¹⁾

SCLK

8 µs

Hi-Z

DOUT/DRDY

DIN

(1) CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low

indicating new data are available.

Figure 32. DOUT/DRDY Behavior Without Data Retrieval in Continuous-Conversion Mode

When CS is high, DOUT/DRDY is configured by default with a weak internal pullup resistor. This feature reduces

the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master device. To disable

this pullup resistor and place the device into a high-impedance state, set the PULL_UP_EN bit to 0 in the Config

register.

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Programming (continued)

9.5.6 Data Format

The ADS1118-Q1 provides 16 bits of data in binary twos complement format. A positive full-scale (+FS) input

produces an output code of 7FFFh and a negative full-scale (–FS) input produces an output code of 8000h. The

output clips at these codes for signals that exceed full-scale. Table 5 summarizes the ideal output codes for

different input signals. Figure 33 shows code transitions versus input voltage.

Table 5. Input Signal versus Ideal Output Code

INPUT SIGNAL, V_IN

IDEAL OUTPUT CODE⁽¹⁾

(AIN_P– AIN_N)

≥ +FS (2¹⁵– 1) / 2¹⁵

7FFFh

0001h

0

+FS / 2¹⁵

0

–FS / 2¹⁵

≤ –FS

FFFFh

8000h

(1) Excludes the effects of noise, INL, offset, and gain errors.

0x7FFF

0x7FFE

0x0001

0x0000

0xFFFF

0x8001

0x8000

¼

-FS

0

FS

Input Voltage (AIN_P- AIN_N)

2¹⁵- 1

FS

2¹⁵

Figure 33. Code Transition Diagram

9.5.7 Data Retrieval

Data is written to and read from the ADS1118-Q1 in the same manner for both single-shot and continuous

conversion modes, without having to issue any commands. The operating mode for the ADS1118-Q1 is selected

by the MODE bit in the Config register.

Set the MODE bit to 0 to put the device in continuous-conversion mode. In continuous-conversion mode, the

device is constantly starting new conversions even when CS is high.

Set the MODE bit to 1 for single-shot mode. In single-shot mode, a new conversion only starts by writing a 1 to

the SS bit.

The conversion data are always buffered, and retain the current data until replaced by new conversion data.

Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low,

indicating that new conversion data are ready, the conversion data are read by shifting the data out on

DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the

same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN

on the SCLK falling edge.

The ADS1118-Q1 also offers the possibility of direct readback of the Config register settings in the same data

transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register

data readback is used) or 16 bits (only used when the CS line can be controlled and is not permanently tied low).

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9.5.7.1 32-Bit Data Transmission Cycle

The data in a 32-bit data transmission cycle consist of four bytes: two bytes for the conversion result, and an

additional two bytes for the Config register readback. The device always reads the MSB first.

Write the same Config register setting twice during one transmission cycle as shown in Figure 34. If convenient,

write the Config register setting once during the first half of the transmission cycle, and then hold the DIN pin

either low (as shown in Figure 35) or high during the second half of the cycle. If no update to the Config register

is required, hold the DIN pin either low or high during the entire transmission cycle. The Config register setting

written in the first two bytes of a 32-bit transmission cycle is read back in the last two bytes of the same cycle.

CS⁽¹⁾

1

9

17

25

SCLK

DOUT/DRDY

DIN

Hi-Z

DATA MSB

DATA LSB

CONFIG MSB CONFIG LSB

Next Data Ready

CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB

(1) CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low

indicating new data are available.

Figure 34. 32-Bit Data Transmission Cycle With Config Register Readback

CS⁽¹⁾

1

9

17

25

SCLK

DOUT/DRDY

DIN

Hi-Z

DATA MSB

DATA LSB

CONFIG MSB CONFIG LSB

Next Data Ready

CONFIG MSB CONFIG LSB

(1) CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low

indicating new data are available.

Figure 35. 32-Bit Data Transmission Cycle: DIN Held Low

9.5.7.2 16-Bit Data Transmission Cycle

If Config register data are not required to be read back, the ADS1118-Q1 conversion data can be clocked out in

a short 16-bit data transmission cycle, as shown in Figure 36. Take CS high after the 16th SCLK cycle to reset

the SPI interface. The next time CS is taken low, data transmission starts with the currently buffered conversion

result on the first SCLK rising edge. If DOUT/DRDY is low when data retrieval starts, the conversion buffer is

already updated with a new result. Otherwise, if DOUT/DRDY is high, the same result from the previous data

transmission cycle is read.

CS

1

9

1

9

SCLK

DOUT/DRDY

DIN

Hi-Z

DATA MSB

DATA LSB

DATA MSB

DATA LSB

CONFIG MSB CONFIG LSB

Figure 36. 16-Bit Data Transmission Cycle

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9.6 Register Maps

The ADS1118-Q1 has two registers that are accessible through the SPI. The Conversion register contains the

result of the last conversion. The Config register allows the user to change the ADS1118-Q1 operating modes

and query the status of the devices.

9.6.1 Conversion Register [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary twos complement format.

Following power up, the Conversion register is cleared to 0, and remains 0 until the first conversion is complete.

The register format is shown in Figure 37.

Figure 37. Conversion Register

15

D15

R-0h

7

14

D14

R-0h

6

13

D13

R-0h

5

12

D12

R-0h

4

11

D11

R-0h

3

10

D10

R-0h

2

9

D9

8

D8

R-0h

1

R-0h

0

D7

D6

D5

D4

D3

D2

D1

D0

R-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Conversion Register Field Descriptions

Bit

Field

Type

Reset

Description

15:0

D[15:0]

R

0000h

16-bit conversion result

9.6.2 Config Register [reset= 058Bh]

The 16-bit Config register can be used to control the ADS1118-Q1 operating mode, input selection, data rate,

full-scale range, and temperature sensor mode. The register format is shown in Figure 38.

Figure 38. Config Register

15

SS

14

13

MUX[2:0]

R/W-0h

5

12

11

10

PGA[2:0]

R/W-2h

2

9

1

8

MODE

R/W-1h

0

R/W-0h

7

6

4

3

DR[2:0]

R/W-4h

TS_MODE

R/W-0h

PULL_UP_EN

R/W-1h

NOP[1:0]

R/W-1h

Reserved

R-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. Config Register Field Descriptions

Bit

Field

Type

Reset

Description

Single-shot conversion start

This bit is used to start a single conversion. SS can only be written when in

power-down state and has no effect when a conversion is ongoing.

15

SS

R/W

0h

When writing:

0 = No effect

1 = Start a single conversion (when in power-down state)

Always reads back as 0 (default).

Input multiplexer configuration

These bits configure the input multiplexer.

000 = AIN_Pis AIN0 and AIN_Nis AIN1 (default)

001 = AIN_Pis AIN0 and AIN_Nis AIN3

010 = AIN_Pis AIN1 and AIN_Nis AIN3

011 = AIN_Pis AIN2 and AIN_Nis AIN3

100 = AIN_Pis AIN0 and AIN_Nis GND

101 = AIN_Pis AIN1 and AIN_Nis GND

110 = AIN_Pis AIN2 and AIN_Nis GND

111 = AIN_Pis AIN3 and AIN_Nis GND

14:12

MUX[2:0]

R/W

0h

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Table 7. Config Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

Programmable gain amplifier configuration

These bits configure the programmable gain amplifier.

000 = FSR is ±6.144 V⁽¹⁾

001 = FSR is ±4.096 V⁽¹⁾

010 = FSR is ±2.048 V (default)

011 = FSR is ±1.024 V

100 = FSR is ±0.512 V

101 = FSR is ±0.256 V

110 = FSR is ±0.256 V

111 = FSR is ±0.256 V

11:9

PGA[2:0]

R/W

2h

Device operating mode

This bit controls the ADS1118-Q1 operating mode.

8

MODE

R/W

1h

4h

0 = Continuous-conversion mode

1 = Power-down and single-shot mode (default)

Data rate

These bits control the data-rate setting.

000 = 8 SPS

001 = 16 SPS

010 = 32 SPS

011 = 64 SPS

7:5

DR[2:0]

100 = 128 SPS (default)

101 = 250 SPS

110 = 475 SPS

111 = 860 SPS

Temperature sensor mode

This bit configures the ADC to convert temperature or input signals.

4

3

TS_MODE

R/W

0h

1h

0 = ADC mode (default)

1 = Temperature sensor mode

Pullup enable

This bit enables a weak internal pullup resistor on the DOUT/DRDY pin only

when CS is high. When enabled, an internal 400-kΩ resistor connects the bus

line to supply. When disabled, the DOUT/DRDY pin floats.

PULL_UP_EN

0 = Pullup resistor disabled on DOUT/DRDY pin

1 = Pullup resistor enabled on DOUT/DRDY pin (default)

No operation

The NOP[1:0] bits control whether data are written to the Config register or not.

For data to be written to the Config register, the NOP[1:0] bits must be 01. Any

other value results in a NOP command. DIN can be held high or low during SCLK

pulses without data being written to the Config register.

2:1

NOP[1:0]

Reserved

R/W

1h

00 = Invalid data; do not update the contents of the Config register

01 = Valid data; update the Config register (default)

10 = Invalid data; do not update the contents of the Config register

11 = Invalid data; do not update the contents of the Config register

Reserved

0

R

Always write 1h

Reads back either 0h or 1h

(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device.

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ADS1118-Q1 is a precision, 16-bit ΔΣ ADC that offers many integrated features to ease the measurement of

the most common sensor types including various type of temperature and bridge sensors. The following sections

give example circuits and suggestions for using the ADS1118-Q1 in various situations.

10.1.1 Serial Interface Connections

The principle serial interface connections for the ADS1118-Q1 are shown in Figure 39.

10

Device

DIN

VDD

1

2

3

4

SCLK

9

8

7

6

DOUT/DRDY

VDD

CS

GND

AIN0

AIN3

0.1 µF

AIN2

Microcontroller or

Microprocessor

with SPI Port

AIN1

5

50 W

DOUT

DIN

Inputs Selected

from Configuration

Register

CS

SCLK

Figure 39. Typical Connections

Most microcontroller SPI peripherals operate with the ADS1118-Q1. The interface operates in SPI mode 1 where

CPOL = 0 and CPHA = 1, SCLK idles low, and data are launched or changed only on SCLK rising edges; data

are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol

employed by the ADS1118-Q1 can be found in the Timing Requirements: Serial Interface section.

It is a good practice to place 50-Ω resistors in the series path to each of the digital pins to provide some short-

circuit protection. Take care to still meet all SPI timing requirements because these additional series resistors

along with the bus parasitic capacitances present on the digital signal lines slews the signals.

The fully-differential input of the ADS1118-Q1 is ideal for connecting to differential sources (such as

thermocouples and thermistors) with a moderately low source impedance. Although the ADS1118-Q1 can read

fully-differential signals, the device cannot accept negative voltages on either of its inputs because of ESD

protection diodes on each pin. When an input exceeds supply or drops below ground, these diodes turn on to

prevent any ESD damage to the device.

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Application Information (continued)

10.1.2 GPIO Ports for Communication

Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or

outputs. If an SPI controller is not available, the ADS1118-Q1 can be connected to GPIO pins and the SPI bus

protocol can be simulated. Using GPIO pins to generate the SPI interface requires only that the pins be

configured as push or pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28 ms,

communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses

with no more than 28 ms between pulses.

10.1.3 Analog Input Filtering

Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and

second, to reduce external noise from being a part of the measurement.

As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when

frequency components are present in the input signal that are higher than half the sampling frequency of the

ADC (also known as the Nyquist frequency). These frequency components fold back and show up in the actual

frequency band of interest below half the sampling frequency. The filter response of the digital filter repeats at

multiples of the sampling frequency, also known as modulator frequency f_(MOD), as shown in Figure 40. Signals or

noise up to a frequency where the filter response repeats are attenuated to a certain amount by the digital filter

depending on the filter architecture. Any frequency components present in the input signal around the modulator

frequency or multiples thereof are not attenuated and alias back into the band of interest, unless attenuated by

an external analog filter.

Magnitude

Sensor

Signal

Unwanted

Signals

Unwanted

Signals

Output

Data Rate

f_(MOD)/2

f_(MOD)

Frequency

Magnitude

Digital Filter

Aliasing of

Unwanted Signals

Output

Data Rate

f_(MOD)/2

f_(MOD)

Magnitude

External

Antialiasing Filter

Roll-Off

Output

f_(MOD)/2

f_(MOD)

Data Rate

Figure 40. Effect of Aliasing

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Application Information (continued)

Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of

change. In this case the sensor signal does not alias back into the pass-band when using a ΔΣ ADC. However,

any noise pickup along the sensor wiring or the application circuitry can potentially alias into the pass band.

Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated

from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors

and cellular phones. Another noise source typically exists on the printed-circuit-board (PCB) itself in the form of

clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the

measurement result.

A first-order, resistor-capacitor (RC) filter is, in most cases, sufficient to either totally eliminate aliasing, or to

reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond f_(MOD)/ 2 is

attenuated to a level below the noise floor of the ADC. The digital filter of the ADS1118-Q1 attenuates signals to

a certain degree, as shown in Figure 28. In addition, noise components are usually smaller in magnitude than the

actual sensor signal. Therefore, using a first-order RC filter with a cutoff frequency set at the output data rate or

ten times higher is generally a good starting point for a system design.

10.1.4 Single-Ended Inputs

Although the ADS1118-Q1 has two differential inputs, the device can measure four single-ended signals.

Figure 41 shows a single-ended connection scheme. The ADS1118-Q1 is configured for single-ended

measurement by configuring the mux to measure each channel with respect to ground. Data are then read out of

one input based on the selection in the Config register. The single-ended signal can range from 0 V up to

positive supply or +FS, whichever is lower. Negative voltages cannot be applied to this circuit because the

ADS1118-Q1 can only accept positive voltages with respect to ground. The ADS1118-Q1 does not loose linearity

within the input range.

The ADS1118-Q1 offers a differential input voltage range of ±FS. The single-ended circuit shown in Figure 41,

however, only uses the positive half of the ADS1118-Q1 FS input voltage range because differentially negative

inputs are not produced. Because only half of the FS range is used, one bit of resolution is lost. For optimal noise

performance, use differential configurations whenever possible. Differential configurations maximize the dynamic

range of the ADC and provide strong attenuation of common-mode noise.

VDD

10

Device

DIN

1

2

3

4

SCLK

9

8

7

6

DOUT/DRDY

VDD

CS

GND

AIN0

AIN3

0.1 µF

AIN2

AIN1

5

Inputs Selected

from Configuration

Register

NOTE: Digital pin connections omitted for clarity.

Figure 41. Measuring Single-Ended Inputs

The ADS1118-Q1 also allows AIN3 to serve as a common point for measurements by adjusting the mux

configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the

ADS1118-Q1 operates with inputs where AIN3 serves as the common point. This ability improves the usable

range over the single-ended configuration because negative differential voltages are allowed when GND < V_(AIN3)

< VDD; however, common-mode noise attenuation is not offered.

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Application Information (continued)

10.1.5 Connecting Multiple Devices

When connecting multiple ADS1118-Q1 devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely

shared by using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for

the ADS1118-Q1, DOUT/DRDY is pulled up to VDD by a weak pullup resistor. This feature prevents

DOUT/DRDY from floating near midrail and causing excess current leakage on a microcontroller input. If the

PULL_UP_EN bit in the Config register is set to 0, the DOUT/DRDY pin enters a 3-state mode when CS

transitions high. The ADS1118-Q1 cannot issue a data-ready pulse on DOUT/DRDY when CS is high. To

evaluate when a new conversion is ready from the ADS1118-Q1 when using multiple devices, the master can

periodically drop CS to the ADS1118-Q1. When CS goes low, the DOUT/DRDY pin immediately drives either

high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at

any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1118-Q1 returns the last

read conversion result. Valid data can be retrieved from the ADS1118-Q1 at anytime without concern of data

corruption. If a new conversion becomes available during data transmission, that conversion is not available for

readback until a new SPI transmission is initiated.

Microcontroller or

Microprocessor

Device

10

DIN

50 W

SCLK

DIN

1

2

3

4

SCLK DOUT/DRDY

9

8

7

6

VDD

CS

GND

AIN0

AIN3

AIN2

DOUT

CS

1

2

AIN1

5

CS

10

Device

DIN

1

2

3

4

SCLK DOUT/DRDY

9

8

7

6

VDD

CS

GND

AIN0

AIN3

AIN2

AIN1

5

NOTE: Power and input connections omitted for clarity.

Figure 42. Connecting Multiple ADS1118-Q1s

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Application Information (continued)

10.1.6 Pseudo Code Example

The flow chart in Figure 43 shows a pseudo-code sequence with the required steps to set up communication

between the device and a microcontroller to take subsequent readings from the ADS1118-Q1. As an example,

the default Config register settings are changed to set up the device for FSR = ±0.512 V, continuous-conversion

mode, and a 64-SPS data rate.

INITIALIZE

DATA CAPTURE

POWER DOWN

Power-up; Wait for supplies to settle to

nominal to ensure power-up reset is complete;

Wait for 50 µs

Take CS low

Wait for DOUT/

DRDY to transition

low

NO

YES

Conﬁgure microcontroller SPI interface to SPI

mode 1 (CPOL = 0, CPHA = 1);

Delay for minimum t_d(CSSC)

Take CS low

Set MODE bit in conﬁg register to '1'

to enter power-down and single-shot

mode

If the CS pin is not tied low permanently,

conﬁgure the microcontroller GPIO connected

to CS as an output;

Conﬁgure the microcontroller GPIO connected

to the DRDY pin as a falling edge triggered

interrupt input;

Delay for minimum td(CSSC)

Clear CS to high

Read out conversion result

and clear CS to high before

DOUT/DRDY goes low again

Set CS to the device low;

Delay for minimum td(CSSC)

Write the conﬁg register to set the device to

FSR = 0.512 V, continuous conversion

mode, data rate = 64 SPS

Clear CS to high to reset the serial interface

Figure 43. Pseudo-Code Example Flowchart

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10.2 Typical Application

Figure 44 shows the basic connections for an independent, two-channel thermocouple measurement system

when using the internal high-precision temperature sensor for cold-junction compensation. Apart from the

thermocouples, the only external circuitry required are biasing resistors; first-order, low-pass, antialiasing filters;

and a power-supply decoupling capacitor.

3.3 V

GND

0.1 ꢁF

3.3 V

R_PU

C_CMA

0.1 ꢁF

R_DIFFA

500 ꢂ

1 Mꢂ

AIN0

AIN1

VDD

ADS1118-Q1

1 ꢁF

Voltage Reference

R_DIFFB

500 ꢂ

R_PD

1 Mꢂ

C_CMB

0.1 ꢁF

±256-mV FSR

PGA

SCLK

GND

3.3 V

R_PU

GND

Digital Filter

and

Interface

CS

16-bit

ûꢀ ADC

Mux

DOUT/DRDY

DIN

C_CMA

0.1 ꢁF

R_DIFFA

500 ꢂ

1 Mꢂ

AIN2

AIN3

Temperature

Sensor

1 ꢁF

Oscillator

GND

R_DIFFB

500 ꢂ

R_PD

1 Mꢂ

C_CMB

0.1 ꢁF

Figure 44. Two-Channel Thermocouple Measurement System

10.2.1 Design Requirements

Table 8 shows the design parameters for this application.

Table 8. Design Parameters

DESIGN PARAMETER

Supply voltage

VALUE

3.3 V

±0.256 V

Full-scale range

Update rate

≥ 100 readings per second

K

Thermocouple type

Temperature measurement range

Measurement accuracy at T_A= 25°C⁽¹⁾

–200°C to +1250°C

±1.2°C

(1) With offset calibration, and no gain calibration. Measurement does not account for thermocouple

inaccuracy.

10.2.2 Detailed Design Procedure

The biasing resistors (R_PUand R_PD) serve two purposes. The first purpose is to set the common-mode voltage of

the thermocouple to within the specified voltage range of the device. The second purpose is to offer a weak

pullup and pulldown to detect an open thermocouple lead. When one of the thermocouple leads fails open, the

positive input is pulled to VDD and the negative input is pulled to GND. The ADC consequently reads a full-scale

value that is outside the normal measurement range of the thermocouple voltage to indicate this failure condition.

When choosing the values of the biasing resistors, take care so that the biasing current does not degrade

measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and

additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ

to 50 MΩ.

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Although the device digital filter attenuates high-frequency components of noise, provide a first-order, passive RC

filter at the inputs to further improve performance. The differential RC filter formed by R_DIFFA, R_DIFFB, and the

differential capacitor C_DIFFoffers a cutoff frequency that is calculated using Equation 5. While the digital filter of

the ADS1118-Q1 strongly attenuates high-frequency components of noise, provide a first-order, passive RC filter

to further suppress high-frequency noise and avoid aliasing. Care must be taken when choosing the filter resistor

values because the input currents flowing into and out of the device cause a voltage drop across the resistors.

This voltage drop shows up as an additional offset error at the ADC inputs. Limit the filter resistor values to below

1 kΩ for best performance.

f_C= 1 / [2π · (R_DIFFA+ R_DIFFB) · C_DIFF

]

(5)

Two common-mode filter capacitors (C_CMAand C_CMB) are also added to offer attenuation of high-frequency,

common-mode noise components. Differential capacitor C_DIFFmust be at least an order of magnitude (10x)

larger than these common-mode capacitors because mismatches in the common-mode capacitors can convert

common-mode noise into differential noise.

The highest measurement resolution is achieved when the largest potential input signal is slightly lower than the

FSR of the ADC. From the design requirement, the maximum thermocouple voltage (V_TC) occurs at a

thermocouple temperature (T_TC) of 1250°C. At this temperature, V_TC= 50.644 mV, as defined in the tables

published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature (T_CJ)

of 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the

thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple

produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating

temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type

thermocouple at T_TC= 1250°C produces an output voltage of V_TC= 50.644 mV – (–1.527 mV) = 52.171 mV

when referenced to a cold-junction temperature of T_CJ= –40°C. The device offers a full-scale range of ±0.256 V

and that is what is used in this application example.

The device integrates a high-precision temperature sensor that can be used to measure the temperature of the

cold junction. The temperature sensor mode is enabled by setting bit TS_MODE = 1 in the Config register. The

accuracy of the overall temperature sensor depends on how accurately the ADS1118-Q1 can measure the cold

junction, and hence, careful component placement and PCB layout considerations must be employed for

designing an accurate thermocouple system. The ADS1118 Evaluation Module provides a good starting point

and offers an example to achieve good cold-junction compensation performance. The ADS1118 Evaluation

Module uses the same schematic as shown in Figure 44, except with only one thermocouple channel connected.

Refer to the application note, Precision Thermocouple Measurement With the ADS1118, SBAA189, for details on

how to optimize your component placement and layout to achieve good cold-junction compensation performance.

The calculation procedure to achieve cold-junction compensation can be done in several ways. A typical way is

to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one on-chip

temperature result, T_CJ, for every thermocouple ADC voltage measured, V_TC. To account for the cold junction,

first convert the temperature sensor reading within the ADS1118-Q1 to a voltage (V_CJ) that is proportional to the

thermocouple currently being used. This process is generally accomplished by performing a reverse lookup on

the table used for the thermocouple voltage-to-temperature conversion. Adding these two voltages yields the

thermocouple-compensated voltage (V_Actual), where V_Actual= V_CJ+ V_TC. V_Actualis then converted to a temperature

(T_Actual) using the same NIST lookup table. A block diagram showing this process is given in Figure 45. Refer to

the application note, Precision Thermocouple Measurement With the ADS1118, SBAA189, for a detailed

explanation of this method.

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Device

MCU

V_TC

Thermocouple

Voltage

T_Actual

T_CJ

V_CJ

V_Actual

On-chip

Temperature

Result

T ‰ V

ꢀ

V ‰ T

Figure 45. Software-Flow Block Diagram

Figure 46 and Figure 47 show the measurement results. The measurements are taken at T_A= T_CJ= 25°C. A

system offset calibration is performed at T_TC= 25°C that equates to V_TC= 0 V when T_CJ= 25°C. No gain

calibration was performed during the measurements. The data in Figure 46 are taken using a precision voltage

source as the input signal instead of a thermocouple. The solid black line in Figure 47 is the respective

temperature measurement error and is calculated from the data in Figure 46 using the NIST tables. The solid

black line in Figure 47 is the measurement error due to the ADC gain and nonlinearity error. The dashed blue

lines in Figure 47 include the guard band for the temperature sensor inaccuracy (±1°C), in addition to the device

gain and nonlinearity error. Note that the measurement results in Figure 46 and Figure 47 do not account for the

thermocouple inaccuracy that must also be considered while designing a thermocouple measurement system.

10.2.3 Application Curves

1.5

1

0.01

0.005

0

0.5

0

-0.5

-1

-0.005

-1.5

-0.01

-200

0

200

400

600

800 1000 1200 1400

-10

0

10

20

30

40

50

60

Temperature (°C)

Thermocouple Voltage (mV)

Figure 47. Temperature Measurement Error vs T_TC

Figure 46. Voltage Measurement Error vs V_TC

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11 Power-Supply Recommendations

The device requires a single power supply, VDD, to power both the analog and digital circuitry of the device.

11.1 Power-Supply Sequencing

Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up

reset process to complete.

11.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at

least a 0.1-µF capacitor, as shown in Figure 48. The 0.1-μF bypass capacitor supplies the momentary bursts of

extra current required from the supply when the ADS1118-Q1 is converting. Place the bypass capacitor as close

to the power-supply pin of the device as possible using low-impedance connections. For best performance, use

multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance

(ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh

noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior

noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections

to ground planes.

VDD

10

Device

DIN

1

2

3

4

SCLK

9

8

7

6

DOUT/DRDY

VDD

CS

GND

AIN0

AIN3

0.1 µF

AIN2

AIN1

5

Figure 48. Power Supply Decoupling

34

ADS1118-Q1

www.ti.com.cn

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

12 Layout

12.1 Layout Guidelines

Use best design practices when laying out a printed-circuit-board (PCB) for both analog and digital components.

This recommendation generally means that the layout separates analog components [such as ADCs, amplifiers,

references, digital-to-analog converters (DACs), and analog muxes] from digital components [such as

microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio

frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of

good component placement is shown in Figure 49. Although Figure 49 provides a good example of component

placement, the best placement for each application is unique to the geometries, components, and PCB

fabrication capabilities employed. That is, there is no single layout that is perfect for every design and careful

consideration must always be used when designing with any analog component.

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Supply

Generation

Signal

Conditioning

(RC Filters

and

Interface

Transceiver

Device

Microcontroller

Connector

or Antenna

Amplifiers)

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Figure 49. System Component Placement

The use of split analog and digital ground planes is not necessary for improved noise performance (although for

thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground

fill in PCB areas with no components is essential for optimum performance. If the system being used employs a

split digital and analog ground plane, TI generally recommends that the ground planes be connected together as

close to the device as possible. A two-layer board is possible using common grounds for both analog and digital

grounds. Additional layers can be added to simplify PCB trace routing. Ground fill may also reduce EMI and RFI

issues.

For best system performance, keep digital components, especially RF portions, as far as practically possible

from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run through

analog areas and avoid placing these traces near sensitive analog components. Digital return currents usually

flow through a ground path that is as close to the digital path as possible. If a solid ground connection to a plane

is not available, these currents may find paths back to the source that interfere with analog performance. The

implications that layout has on the temperature-sensing functions are much more significant than for ADC

functions.

Bypass supply pins to ground with a low-ESR ceramic capacitor. The optimum placement of the bypass

capacitors is as close as possible to the supply pins. The ground-side connections of the bypass capacitors must

be low-impedance connections for optimum performance. The supply current flows through the bypass capacitor

terminal first and then to the supply pin to make the bypassing most effective.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Use

high-quality differential capacitors. The best ceramic-chip capacitors are C0G (NPO), with stable properties and

low-noise characteristics. Thermally isolate a copper region around the thermocouple input connections to create

a thermally-stable cold junction. Obtaining acceptable performance with alternate layout schemes is possible as

long as the above guidelines are followed.

35

ADS1118-Q1

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

www.ti.com.cn

12.2 Layout Example

SCLK

CS

VDD

1

2

3

4

5

SCLK

CS

10

9

DIN

DOUT/

DRDY

Device

GND

AIN0

AIN1

8

VDD

AIN3

AIN2

7

AIN3

AIN2

AIN0

AIN1

6

Figure 50. VSSOP Package

36

ADS1118-Q1

www.ti.com.cn

ZHCSEB1A –OCTOBER 2015–REVISED NOVEMBER 2015

13 器件和文档支持

13.1 文档支持

13.1.1 相关文档ꢀ

•

《使用 ADS1118 进行精密热电偶测量》，SBAA189

《ADS1118EVM 用户指南》，SBAU184

《430BOOST-ADS1118 BoosterPack 用户指南》，SBAU207

《ADS1118 Boosterpack》，SLYU013

《模数转换规范及性能特性术语表》，SBAA147

13.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范和

标准且不一定反映 TI 的观点；请见 TI 的使用条款。

TI E2E™ 在线社区 TI 工程师 (E2E) 社区。此社区的创建目的是为了促进工程师之间协作。在 e2e.ti.com 中，您

可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。

E2E 精密数据转换器论坛 TI 面向精密数据转换器建立的工程师 (E2E) 社区。创建该社区旨在促进工程师之间的交

流和协作。用户可在该社区中进行实时问答。

13.3 商标

E2E is a trademark of Texas Instruments.

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

13.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

14 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不

对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

37

重要声明

德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改，并有权根据

JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售

都遵循在订单确认时所提供的TI 销售条款与条件。

TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为有必要时才会使

用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。

TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应用相关的风险，

客户应提供充分的设计与操作安全措施。

TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予的直接或隐含权

限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服务的许可、授权、或认可。使用

此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它知识产权方面的许可。

对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况下才允许进行

复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。

在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件或服务的所有明

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客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品相关的所有法

律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见故障的危险后果、监测故障

及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因在此类安全关键应用中使用任何 TI 组件而

对 TI 及其代理造成的任何损失。

在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特有的可满足适用

的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。

TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使用的特别协议。

只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同意，对并非指定面

向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独力负责满足与此类使用相关的所有

法律和法规要求。

TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要

求，TI不承担任何责任。

产品

应用

www.ti.com.cn/telecom

数字音频

www.ti.com.cn/audio

www.ti.com.cn/amplifiers

www.ti.com.cn/dataconverters

www.dlp.com

通信与电信

计算机及周边

消费电子

能源

放大器和线性器件

数据转换器

DLP® 产品

DSP - 数字信号处理器

时钟和计时器

接口

www.ti.com.cn/computer

www.ti.com/consumer-apps

www.ti.com/energy

www.ti.com.cn/dsp

工业应用

医疗电子

安防应用

汽车电子

视频和影像

www.ti.com.cn/industrial

www.ti.com.cn/medical

www.ti.com.cn/security

www.ti.com.cn/automotive

www.ti.com.cn/video

www.ti.com.cn/clockandtimers

www.ti.com.cn/interface

www.ti.com.cn/logic

逻辑

电源管理

www.ti.com.cn/power

www.ti.com.cn/microcontrollers

www.ti.com.cn/rfidsys

www.ti.com/omap

微控制器 (MCU)

RFID 系统

OMAP应用处理器

无线连通性

www.ti.com.cn/wirelessconnectivity

德州仪器在线技术支持社区

www.deyisupport.com

IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1118QDGSRQ1

VSSOP

DGS

10

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Jul-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSSOP DGS 10

SPQ

Length (mm) Width (mm) Height (mm)

366.0 364.0 50.0

ADS1118QDGSRQ1

2500

Pack Materials-Page 2

PACKAGE OUTLINE

DGS0010A

VSSOP - 1.1 mm max height

S

C

A

L

E

3

.

2

0

SMALL OUTLINE PACKAGE

C

SEATING PLANE

0.1 C

5.05

4.75

TYP

PIN 1 ID

AREA

A

8X 0.5

10

1

3.1

2.9

NOTE 3

2X

2

5

6

0.27

0.17

10X

3.1

2.9

1.1 MAX

0.1

C A

B

NOTE 4

0.23

0.13

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.7

0.4

0 - 8

DETAIL A

TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

(R0.05)

TYP

SYMM

10X (0.3)

1

5

10

SYMM

6

8X (0.5)

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A

VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

10X (1.45)

SYMM

(R0.05) TYP

10X (0.3)

8X (0.5)

1

5

10

SYMM

6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221984/A 05/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	ADS1118QDGSRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有 PGA、振荡器、基准电压、温度传感器和 SPI 的汽车类 16 位、860SPS、4 通道 Δ-Σ ADC \| DGS \| 10 \| -40 to 125 温度传感光电二极管传感器温度传感器振荡器转换器
文件：	总45页 (文件大小：1679K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1118QDGSRQ1 [TI]

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