ADS112U04 [TI]
具有 PGA、VREF、2 个 IDAC 和 UART 接口的 16 位 2kSPS 4 通道低功耗小型 Δ-Σ ADC;
| 型号： | ADS112U04 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 PGA、VREF、2 个 IDAC 和 UART 接口的 16 位 2kSPS 4 通道低功耗小型 Δ-Σ ADC |
| 文件： | 总77页 (文件大小：2919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS112U04
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
具有 UART 接口的 ADS112U04 16 位 4 通道 2kSPS Δ-Σ ADC
1 特性
3 说明
1
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电流消耗低至 315µA（典型值）
ADS112U04 是一款 16 位精密模数转换器 (ADC)，集
成了多种 特性， 能够降低系统成本并减少小型传感器
信号测量 应用 中的组件数量。该器件 具有 通过灵活
的输入多路复用器 (MUX) 实现的两个差分输入或四个
单端输入、一个低噪声可编程增益放大器 (PGA)、两
个可编程激励电流源、一个电压基准、一个振荡器以及
一个精密温度传感器。
宽电源电压范围：2.3V 至 5.5V
可编程增益：1 至 128
可编程数据速率：高达 2kSPS
16 位无噪声分辨率（20SPS 时）
采用单周期稳定数字滤波器，在 20SPS 时实现同
步 50Hz 和 60Hz 抑制
•
•
两个差分输入或四个单端输入
此器件能够以高达 2000 次/秒 (SPS) 采样数据速率执
行转换，并且能够在单周期内稳定。针对噪声环境中的
工业应用，当采样频率为 20SPS 时，数字滤波器可同
时提供 50Hz 和 60Hz 抑制。内部 PGA 提供高达 128
的增益。此 PGA 使得 ADS112U04 非常适合可测量小
传感器信号的 应用 ，例如电阻式温度检测器 (RTD)、
热电偶、热敏电阻和阻性桥式传感器。
双匹配可编程电流源：
10μA 至 1.5mA
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•
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集成 2.048V 基准电压：漂移 5ppm/°C（典型值）
集成 2% 精准振荡器
集成温度传感器：精度 0.5°C（典型值）
三个通用输入/输出
2 线 UART 兼容接口（8-N-1 格式），具有高达
120kBaud 的波特率和
自动波特率检测功能
ADS112U04 具有 一个 2 线 UART 兼容接口。在需要
电隔离的 应用 中，这种通用异步接收器/发送器
(UART) 接口可最大限度地减少数字隔离通道的数量，
从而节省成本、减小布板空间和降低功耗。
•
封装：3.0mm × 3.0mm × 0.75mm WQFN
2 应用
ADS112U04 采用无引线的 16 引脚 WQFN 或 16 引脚
TSSOP 封装，额定工作温度范围为 –40°C 至 +125°
C。
•
传感器和变送器：
温度、压力、应力，流量
•
可编程逻辑控制器 (PLC) 和分布式控制系统 (DCS)
模拟输入模块
器件信息(1)
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•
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温度控制器
器件编号
ADS112U04
封装
WQFN (16)
TSSOP (16)
封装尺寸（标称值）
3.00mm × 3.00mm
5.00mm × 4.40mm
人工气候室，工业烘箱
患者监护系统：
体温、血压
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
K 型热电偶测量
3.3 V
3.3 V
0.1 ꢀF
0.1 ꢀF
3.3 V
REFP
REFN
AVDD
DVDD
10 ꢀA to
1.5 mA
Isothermal Block
2.048-V
Reference
Reference
Mux
AIN0
ADS112U04
TX
AIN1
RX
Digital Filter
and
UART Interface
GPIO0
GPIO1
GPIO2/DRDY
RESET
16-Bit
ûꢁ ADC
Thermocouple
3.3 V
PGA
Mux
AIN2
VDD
LM94022
GS1
AIN3
Precision
Temperature
Sensor
OUT
GND
Low Drift
Oscillator
GS0
AVSS
DGND
Cold-Junction
Compensation
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS838
ADS112U04
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 31
8.5 Programming........................................................... 34
8.6 Register Map........................................................... 40
Application and Implementation ........................ 46
9.1 Application Information............................................ 46
9.2 Typical Applications ................................................ 51
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 UART Timing Requirements ..................................... 8
6.7 UART Switching Characteristics ............................... 8
6.8 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 17
7.1 Noise Performance ................................................. 17
Detailed Description ............................................ 20
8.1 Overview ................................................................. 20
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
9
10 Power Supply Recommendations ..................... 61
10.1 Power-Supply Sequencing.................................... 61
10.2 Power-Supply Decoupling..................................... 61
11 Layout................................................................... 62
11.1 Layout Guidelines ................................................. 62
11.2 Layout Example .................................................... 63
12 器件和文档支持 ..................................................... 64
12.1 文档支持................................................................ 64
12.2 接收文档更新通知 ................................................. 64
12.3 社区资源................................................................ 64
12.4 商标....................................................................... 64
12.5 静电放电警告......................................................... 64
12.6 术语表 ................................................................... 64
13 机械、封装和可订购信息....................................... 64
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (January 2018) to Revision A
Page
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•
Changed Noise parameter typical specification from 110 nVRMS to 490 nVRMS ..................................................................... 5
Changed Internal Voltage Reference, Accuracy parameter: added TSSOP package to test conditions of first row
and added second row for the WQFN package .................................................................................................................... 6
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•
•
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已添加 TSSOP package to conditions of Internal Reference Voltage Histogram figure ..................................................... 13
已更改 Digital Supply Current vs Temperature figure ......................................................................................................... 16
已更改 description of power-on reset procedure in Power-On Reset section...................................................................... 32
已更改 50 µs to 600 µs and changed (MUX[3:1] = 1110) to (MUX[3:0] = 1110) in Pseudo Code Example section .......... 50
已更改 50 µs to 600 µs in Power-Supply Sequencing section ............................................................................................ 61
2
Copyright © 2018, Texas Instruments Incorporated
ADS112U04
www.ti.com.cn
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
PW Package
16-Pin TSSOP
Top View
GPIO1
GPIO0
RESET
DGND
AVSS
AIN3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RX
TX
GPIO2/DRDY
DVDD
AVDD
AIN0
RESET
DGND
AVSS
AIN3
1
2
3
4
12
11
10
9
GPIO2/DRDY
DVDD
Thermal pad
AVDD
AIN0
AIN2
AIN1
REFN
REFP
Not to scale
Not to scale
Pin Functions
PIN
NO.
ANALOG OR DIGITAL
INPUT/OUTPUT
NAME
RTE
9
PW
11
10
7
DESCRIPTION(1)
AIN0
Analog input
Analog input
Analog input
Analog input
Analog supply
Analog supply
Digital supply
Digital supply
Digital input/output
Digital input/output
Digital input/output
Analog input
Analog input
Digital input
Analog input 0
Analog input 1
Analog input 2
Analog input 3
AIN1
8
AIN2
5
AIN3
4
6
AVDD
AVSS
10
3
12
5
Positive analog power supply. Connect a 100-nF (or larger) capacitor to AVSS.
Negative analog power supply
DGND
DVDD
GPIO0
GPIO1
GPIO2/DRDY
REFN
REFP
2
4
Digital ground
11
16
15
12
6
13
2
Positive digital power supply. Connect a 100-nF (or larger) capacitor to DGND.
General-purpose input/output 0
1
General-purpose input/output 1
14
8
General-purpose input/output 2 or data ready; active low.
Negative reference input
7
9
Positive reference input
RESET
RX
1
3
Reset; active low
14
13
Pad
16
15
—
Digital input
Serial data input
TX
Digital output
—
Serial data output
Thermal pad
Thermal power pad. Connect to AVSS.
(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.
Copyright © 2018, Texas Instruments Incorporated
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ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
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6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
MAX
UNIT
AVDD to AVSS
7
Power-supply voltage
DVDD to DGND
–0.3
7
0.3
V
AVSS to DGND
–2.8
Analog input voltage
Digital input voltage
Input current
AIN0, AIN1, AIN2, AIN3, REFP, REFN
TX, RX, GPIO0, GPIO1, GPIO2/DRDY, RESET
Continuous, any pin except power-supply pins
Junction, TJ
AVSS – 0.3
DGND – 0.3
–10
AVDD + 0.3
DVDD + 0.3
10
V
V
mA
150
Temperature
°C
Storage, Tstg
–60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Unipolar analog power supply
AVDD to AVSS
AVSS to DGND
AVDD to DGND
AVSS to DGND
DVDD to DGND
2.3
–0.1
2.3
5.5
0.1
V
0
2.5
2.75
–2.3
5.5
Bipolar analog power supply
Digital power supply
V
V
–2.75
2.3
–2.5
ANALOG INPUTS(1)
PGA disabled, gain = 1 to 4
PGA enabled, gain = 1 to 4
AVSS – 0.1
AVSS + 0.2
AVDD + 0.1
AVDD – 0.2
V(AINx)
Absolute input voltage(2)
Differential input voltage
V
V
AVSS + 0.2 +
|VINMAX|·(Gain – 4) / 8
AVDD – 0.2 –
|VINMAX|·(Gain – 4) / 8
PGA enabled, gain = 8 to 128
(3)
VIN
VIN = VAINP – VAINN
–VREF / Gain
VREF / Gain
VOLTAGE REFERENCE INPUTS
VREF
Differential reference input voltage
VREF = V(REFP) – V(REFN)
0.75
AVSS – 0.1
2.5
AVDD – AVSS
V(REFP) – 0.75
AVDD + 0.1
V
V
V
V(REFN)
V(REFP)
Absolute negative reference voltage
Absolute positive reference voltage
V(REFN) + 0.75
DIGITAL INPUTS
Input voltage
RX, GPIO0, GPIO1,
GPIO2/DRDY, RESET
DGND
–40
DVDD
125
V
TEMPERATURE RANGE
TA Operating ambient temperature
°C
(1) AINP and AINN denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs.
PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Low-Noise Programmable Gain Stage section for more information.
(2) VINMAX denotes the maximum differential input voltage, VIN, that is expected in the application. |VINMAX| can be smaller than VREF / Gain.
(3) Excluding the effects of offset and gain error.
4
Copyright © 2018, Texas Instruments Incorporated
ADS112U04
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ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
6.4 Thermal Information
ADS112U04
THERMAL METRIC(1)
WQFN (RTE)
16 PINS
57.7
TSSOP (PW)
16 PINS
90.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.0
31.7
19.9
41.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
1.8
ψJB
19.8
41.2
RθJC(bot)
11.8
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
PGA disabled, gain = 1 to 4, normal mode, VIN = 0 V
PGA disabled, gain = 1 to 4, turbo mode, VIN = 0 V
Gain = 1 to 128, VIN = 0 V
±5
±10
±1
Absolute input current
nA
PGA disabled, gain = 1 to 4, VIN = 0 V
Gain = 1 to 128, VIN = 0 V
10
5
Absolute input current drift
pA/°C
PGA disabled, gain = 1 to 4, normal mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±5
±10
±1
PGA disabled, gain = 1 to 4, turbo mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
Differential input current
nA
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
PGA disabled, gain = 1 to 4,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
10
2
Differential input current drift
pA/°C
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
SYSTEM PERFORMANCE
Resolution (no missing codes)
16
Bits
Normal mode
20, 45, 90, 175, 330, 600, 1000
40, 90, 180, 350, 660, 1200, 2000
490
DR
Data rate
SPS
Turbo mode
Noise (input-referred)(1)
Integral nonlinearity
Normal mode, gain = 128, DR = 20 SPS
nVRMS
AVDD = 3.3 V, gain = 1 to 128, VCM = AVDD / 2,
external VREF, normal mode, best fit
INL
VIO
–15
±6
15
ppmFSR
PGA disabled, gain = 1 to 4, differential inputs
Gain = 1, differential inputs, TA = 25°C
Gain = 2 to 128, differential inputs
PGA disabled, gain = 1 to 4
Gain = 1 to 128
±4
±5
Input offset voltage
Offset drift
–150
150
µV
±4
0.02
0.1
µV/°C
0.6
PGA disabled, gain = 1 to 4
Gain = 1 to 32, TA = 25°C
Gain = 64 to 128, TA = 25°C
PGA disabled, gain = 1 to 4
Gain = 1 to 32
±0.01%
±0.01%
±0.015%
0.5
Gain error(2)
–0.05%
–0.1%
0.05%
0.1%
Gain drift(2)
0.5
2
4
ppm/°C
Gain = 64 to 128
1
(1) See the Noise Performance section for more information.
(2) Excluding error of voltage reference.
Copyright © 2018, Texas Instruments Incorporated
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
dB
dB
dB
V
SYSTEM PERFORMANCE (continued)
50 Hz ±1 Hz, DR = 20 SPS
78
80
88
88
NMRR Normal-mode rejection ratio
60 Hz ±1 Hz, DR = 20 SPS
At dc, gain = 1, AVDD = 3.3 V
90
105
115
110
105
115
CMRR Common-mode rejection ratio fCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V
fCM = 50 Hz or 60 Hz, DR = 2 kSPS, AVDD = 3.3 V
105
95
AVDD at dc, VCM = AVDD / 2
85
PSRR
Power-supply rejection ratio
DVDD at dc, VCM = AVDD / 2
95
INTERNAL VOLTAGE REFERENCE
VREF
Reference voltage
Accuracy
2.048
±0.01%
±0.04%
5
TA = 25°C, TSSOP package
TA = 25°C, WQFN package
–0.15%
–0.25%
0.15%
0.25%
30
Temperature drift
Long-term drift
ppm/°C
ppm
1000 hours
110
VOLTAGE REFERENCE INPUTS
Reference input current
REFP = VREF, REFN = AVSS, AVDD = 3.3 V
±10
nA
INTERNAL OSCILLATOR
Normal mode
Turbo mode
Normal mode
Turbo mode
1.024
2.048
±1%
fCLK
Frequency
Accuracy
MHz
–2%
–4%
2%
4%
±2%
EXCITATION CURRENT SOURCES (IDACs) (AVDD = 3.3 V to 5.5 V)
Current settings
10, 50, 100, 250, 500, 1000, 1500
µA
V
Compliance voltage
All IDAC settings
AVDD – 0.9
6%
Accuracy (each IDAC)
IDAC = 50 µA to 1.5 mA
–6%
±1%
0.3%
50
Current matching between
IDACs
IDAC = 50 µA to 1.5 mA, TA = 25°C
2%
Temperature drift (each IDAC) IDAC = 50 µA to 1.5 mA
ppm/°C
ppm/°C
Temperature drift matching
IDAC = 50 µA to 1.5 mA
between IDACs
8
40
BURN-OUT CURRENT SOURCES (BOCS)
Magnitude
Accuracy
Sink and source
10
µA
±5%
TEMPERATURE SENSOR
Conversion resolution
Temperature resolution
14
0.03125
±0.25
Bits
°C
TA = 0°C to +85°C
–1
1
Accuracy
°C
TA = –40°C to +125°C
–1.5
±0.5
1.5
Accuracy vs analog supply
voltage
0.0625
0.25
°C/V
DIGITAL INPUTS/OUTPUTS
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
Input current
DGND
0.3 DVDD
DVDD
V
V
VIH
VOL
VOH
0.7 DVDD
IOL = 1 mA
0.2 DVDD
V
IOH = 1 mA
0.8 DVDD
–1
V
DGND ≤ VDigital Input ≤ DVDD
1
µA
6
Copyright © 2018, Texas Instruments Incorporated
ADS112U04
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ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V, IDACs Turned Off)
Power-down mode
0.1
250
360
455
550
370
580
765
955
3
Normal mode, PGA disabled, gain = 1 to 4
Normal mode, gain = 1 to 16
510
Normal mode, gain = 32
IAVDD
Analog supply current
Normal mode, gain = 64, 128
Turbo mode, PGA disabled, gain = 1 to 4
Turbo mode, gain = 1 to 16
Turbo mode, gain = 32
µA
Turbo mode, gain = 64, 128
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
External reference selected
60
IAVDD
Analog supply current
µA
µA
IDAC overhead (excludes the actual IDAC current)
195
DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, UART Not Active)
Power-down mode
0.3
65
5
IDVDD
Digital supply current
Normal mode
Turbo mode
100
100
POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, UART Not Active)
Normal mode, gain = 1 to 16
1.4
2.2
PD
Power dissipation
mW
Turbo mode, gain = 1 to 16
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6.6 UART Timing Requirements
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V (unless otherwise noted)
MIN
NOM
MAX
120
UNIT
1/tBAUD
tr(RX)
Bus baud rate
2
kBaud
Rise time
10-pF load
10-pF load
15 % of tBAUD
tf(RX)
Fall time
15 % of tBAUD
tJITTER
tw(RSL)
Edge timing variance
Pulse duration, RESET low
–1%
250
1%
ns
Delay time, start of communication after RESET rising edge
td(RSRX)
80
µs
(or RESET command decoded(1)
)
Normal mode
Turbo mode
32760
Timeout(2)
tMOD
65520
(1) The UART baud rate affects the command latch timing; see the Command Latching section for more details.
(2) See the Timeout section for more information.
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode).
6.7 UART Switching Characteristics
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT(1)
Propagation delay time, RDATA command
decoded to DRDY rising edge(2)
tp(RDDR)
tp(RDTX)
tp(DRTX)
Manual data read mode
7
tCLK
Propagation delay time, RDATA command
decoded to TX falling edge(2)
Manual data read mode
2
2
tBAUD
tBAUD
Propagation delay time, DRDY rising edge to TX
falling edge(2)
Automatic data read mode
tw(DRH)
tw(DRL)
Pulse duration, DRDY high
Pulse duration, DRDY low
2
4
tMOD
tCLK
Automatic data read mode
Propagation delay time, RREG command
decoded to TX falling edge(2)
tp(RREG)
2
tBAUD
(1) tCLK = 1 / fCLK. Oscillator frequency fCLK = 1.024 MHz (normal mode) and 2.048 MHz (turbo mode).
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode).
(2) The UART baud rate affects the command latch timing; see the Command Latching section for more details.
ttBAUD
t
tr(RX)
VIH
tJITTER
tf(RX)
RX/TX
VIL
ttBAUD
t
tJITTER
图 1. UART Timing Requirements
tw(RSL)
RESET
ttd(RSRX)
t
RX
Synchronization word
RESET command
Synchronization word
New command
图 2. RESET Pin and RESET Command Timing Requirements
8
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tw(DRH)
DRDY
tp(RDDR)
RX
Synchronization word
RDATA command
tp(RDTX)
TX
Data 1
图 3. Manual Data Read Mode DRDY Switching Characteristics
DRDY
tw(DRL)
TX
Data 1
tp(DRTX)
图 4. Automatic Data Read Mode DRDY Switching Characteristics
RX
Synchronization word
RREG command
tp(RREG)
TX
Register data
图 5. Register Read Switching Characteristics
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
15
10
5
15
10
5
0
0
-5
-5
-10
-15
-10
-15
-40èC
25èC
85èC
125èC
3.5
-40èC
25èC
85èC
125èC
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
V(AINx) (V)
V(AINx) (V)
Normal mode, PGA disabled, VIN = 0 V
Normal mode, PGA enabled, VIN = 0 V
图 6. Absolute Input current vs Absolute Input Voltage
图 7. Absolute Input Current vs Absolute Input Voltage
15
15
10
5
10
5
0
0
-5
-5
-10
-10
-40èC
25èC
85èC
125èC
3.5
-40èC
25èC
85èC
125èC
3 3.5
-15
-15
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
V(AINx) (V)
V(AINx) (V)
Turbo mode, PGA disabled, VIN = 0 V
Turbo mode, PGA enabled, VIN = 0 V
图 8. Absolute Input Current vs Absolute Input Voltage
图 9. Absolute Input Current vs Absolute Input Voltage
20
20
15
10
5
15
10
5
0
0
-5
-5
-10
-15
-10
-15
-40èC
25èC
85èC
125èC
-40èC
25èC
85èC
125èC
-20
-2.5 -2 -1.5 -1 -0.5
-20
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
VIN (V)
VIN (V)
Normal mode, PGA disabled, VCM = 1.65 V
Normal mode, PGA enabled, VCM = 1.65 V
图 10. Differential Input Current vs
图 11. Differential Input Current vs
Differential Input Voltage
Differential Input Voltage
10
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
20
15
10
5
20
15
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
-20
-40èC
25èC
85èC
125èC
-40èC
25èC
85èC
125èC
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
VIN (V)
VIN (V)
Turbo mode, PGA disabled, VCM = 1.65 V
Turbo mode, PGA enabled, VCM = 1.65 V
图 12. Differential Input Current vs
图 13. Differential Input Current vs
Differential Input Voltage
Differential Input Voltage
15
10
5
60
40
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain =64
Gain = 128
20
0
0
-5
-20
-40
-60
-10
-15
-100 -80 -60 -40 -20
0
20
40
60
80 100
-100 -80 -60 -40 -20
0
20
40
60
80 100
VIN (% of FS)
VIN (% of FS)
PGA enabled, external reference, best fit
PGA enabled, internal reference, best fit
图 15. INL vs Differential Input Voltage
图 14. INL vs Differential Input Voltage
300
250
200
150
100
50
10
8
Gain = 1
Gain = 2
Gain = 4
6
4
2
0
0
-50
-25
0
25
50
75
100
125
Offset Voltage (ꢀV)
Temperature (èC)
PGA enabled, gain = 1, 620 samples
PGA disabled
图 16. Offset Voltage Histogram
图 17. Input Offset Voltage vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
20
16
12
8
300
250
200
150
100
50
Gain = 1
Gain = 128
4
0
-50
0
-25
0
25
50
75
100
125
Temperature (èC)
PGA enabled
Gain Error (%)
PGA disabled, gain = 1, 620 samples
图 18. Input Offset Voltage vs Temperature
图 19. Gain Error Histogram
300
250
200
150
100
50
300
250
200
150
100
50
0
0
Gain Error (%)
Gain Error (%)
PGA enabled, gain = 1, 620 samples
PGA enabled, gain = 128, 620 samples
图 20. Gain Error Histogram
图 21. Gain Error Histogram
0
0
-0.005
-0.01
-0.005
-0.01
-0.015
-0.02
-0.015
-0.02
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 1
Gain = 2
Gain = 4
-0.025
-0.025
-0.03
-0.03
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
PGA disabled
PGA enabled
图 22. Gain Error vs Temperature
图 23. Gain Error vs Temperature
12
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
125
120
115
110
105
100
125
120
115
110
105
100
Gain = 1, DR = 20 SPS
Gain = 1, DR = 2000 SPS
Gain = 128, DR = 20 SPS
Gain = 128, DR = 2000 SPS
DR = 20 SPS
25 50
DR = 2000 SPS
75 100 125
-50
-25
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
PGA disabled
PGA enabled
图 24. DC CMRR vs Temperature
图 25. DC CMRR vs Temperature
2000
1500
1000
500
0
2.051
2.05
AVDD = 3.3 V
AVDD = 5.0 V
2.049
2.048
2.047
2.046
2.045
-50
-25
0
25
50
75
100
125
Temperature (èC)
Internal Reference Voltage (V)
5940 samples, TSSOP package
图 27. Internal Reference Voltage vs Temperature
图 26. Internal Reference Voltage Histogram
2.0486
2.0484
2.0482
2.048
0
-5
VREF = 1 V
VREF = 1.5 V
VREF = 2 V
VREF = 2.5 V
-10
-15
-20
2.0478
2
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
125
AVDD (V)
Temperature (èC)
图 28. Internal Reference Voltage vs AVDD
图 29. External Reference Input Current vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
300
250
200
150
100
50
1.026
1.025
1.024
1.023
1.022
1.021
1.02
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Internal Oscillator Frequency (MHz)
Normal mode
Normal mode
图 30. Internal Oscillator Frequency Histogram
图 31. Internal Oscillator Frequency vs Temperature
1.026
1.025
1.024
1.023
1.022
1.021
1.02
6
IDAC = 1000 µA
IDAC = 500 µA
IDAC = 100 µA
4
2
0
œ2
œ4
œ6
0.5
0.6
0.7
0.8
0.9
1.0
2
2.5
3
3.5
DVDD (V)
4
4.5
5
5.5
C006
Compliance Voltage (V)
Normal mode
图 33. IDAC Accuracy vs Compliance Voltage
图 32. Internal Oscillator Frequency vs DVDD
1
0.75
0.5
6
4
IDAC = 1000 mA
IDAC = 500 mA
IDAC = 100 mA
2
0.25
0
0
-0.25
-0.5
-0.75
-1
-2
-4
-6
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
图 34. IDAC Accuracy vs Temperature
图 35. IDAC Matching vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
1.25
3.3
3.2
3.1
3
Mean
Mean + 6s
Mean - 6s
1
0.75
0.5
2.9
2.8
2.7
2.6
2.5
2.4
0.25
0
-0.25
-0.5
-0.75
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
6
7
8
9
10
Temperature (èC)
Sourcing Current (mA)
DVDD = 3.3 V
图 36. Internal Temperature Sensor Accuracy vs
图 37. Digital Pin Output Voltage vs Sourcing Current
Temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
8
9
10
-50
-25
0
25
50
75
100
125
Sinking Current (mA)
Temperature (èC)
DVDD = 3.3 V
Power-down mode
图 39. Analog Supply Current vs Temperature
图 38. Digital Pin Output Voltage vs Sinking Current
700
600
500
400
300
200
100
0
700
600
500
400
300
200
100
0
PGA disabled
Gain = 1
Gain = 32
Gain = 128
PGA disabled
Gain = 1
Gain = 32
Gain = 128
-50
-25
0
25
50
75
100
125
2
2.5
3
3.5
4
4.5
5 5.5
Temperature (èC)
AVDD (V)
Normal mode
Normal mode
图 40. Analog Supply Current vs Temperature
图 41. Analog Supply Current vs AVDD
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
100
90
80
70
60
50
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
Power-down mode
Normal mode
图 42. Digital Supply Current vs Temperature
图 43. Digital Supply Current vs Temperature
100
90
80
70
60
50
2
2.5
3
3.5
4
4.5
5
5.5
DVDD (V)
Normal mode
图 44. Digital Supply Current vs DVDD
16
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7 Parameter Measurement Information
7.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus
reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-
referred noise drops when reducing the output data rate because more samples of the internal modulator are
averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
表 1 to 表 8 summarize the device noise performance. Data are representative of typical noise performance at TA
= 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single
device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted
together. 表 1, 表 3, 表 5, and 表 7 list the input-referred noise in units of μVRMS for the conditions shown. Values
in µVPP are shown in parenthesis. 表 2, 表 4, 表 6, and 表 8 list the corresponding data in effective resolution
calculated from μVRMS values using 公式 1. Noise-free resolution calculated from peak-to-peak noise values
using 公式 2 are shown in parenthesis.
The input-referred noise (表 1, 表 3, 表 5, and 表 7) only changes marginally when using an external low-noise
reference, such as the REF5020. Use 公式 1 and 公式 2 to calculate effective resolution numbers and noise-free
resolution when using a reference voltage other than 2.048 V:
Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2)
Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2)
(1)
(2)
表 1. Noise in μVRMS (μVPP
)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
20
45
62.50 (62.50)
62.50 (62.50)
62.50 (62.50)
62.50 (63.79)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (37.30)
15.63 (15.63)
15.63 (15.63)
15.63 (15.63)
15.63 (17.00)
15.63 (28.25)
15.63 (38.94)
7.81 (7.81)
7.81 (7.81)
7.81 (7.81)
7.81 (9.81)
7.81 (14.47)
7.81 (22.30)
7.81 (31.55)
3.91 (3.91)
3.91 (3.91)
3.91 (3.91)
3.91 (5.27)
3.91 (8.06)
3.91 (12.07)
3.91 (17.41)
1.95 (1.95)
1.95 (1.95)
1.95 (2.06)
1.95 (3.32)
1.95 (4.64)
1.95 (6.69)
1.95 (10.23)
0.98 (0.98)
0.98 (0.98)
0.98 (1.20)
0.98 (1.93)
0.98 (2.93)
0.98 (4.49)
1.04 (6.21)
0.49 (0.49)
0.49 (0.57)
0.49 (0.91)
0.49 (1.49)
0.49 (1.91)
0.51 (3.14)
0.73 (4.69)
90
175
330
600
1000
62.50 (107.88) 31.25 (48.95)
62.50 (153.77) 31.25 (76.01)
62.50 (228.90) 31.25 (108.90) 15.63 (58.24)
表 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
20
45
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.78)
16 (15.10)
16 (14.39)
16 (14.03)
15.83 (13.32)
90
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.92)
16 (15.23)
16 (14.75)
16 (14.22)
16 (13.61)
16 (15.70)
16 (15.02)
16 (14.41)
16 (13.80)
175
330
600
1000
16 (15.97)
16 (15.21)
16 (14.70)
16 (14.13)
16 (15.74)
16 (15.35)
16 (14.72)
16 (14.20)
16 (15.88)
16 (15.12)
16 (14.68)
16 (14.10)
16 (15.48)
16 (15.15)
16 (14.70)
16 (13.99)
16 (15.57)
16 (14.96)
16 (14.37)
16 (13.99)
15.91 (13.33) 15.49 (12.74)
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表 3. Noise in μVRMS (μVPP
)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
20
62.50 (62.50)
62.50 (62.50)
62.50 (62.50)
62.50 (65.71)
62.50 (106.06)
62.50 (150.81)
62.50 (221.61)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (35.00)
31.25 (52.59)
31.25 (79.15)
31.25 (111.61)
15.63 (15.63)
15.63 (15.63)
15.63 (15.63)
15.63 (16.83)
15.63 (26.30)
15.63 (36.87)
15.63 (55.07)
45
90
175
330
600
1000
表 4. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
20
1
2
4
16 (16)
16 (16)
16 (16)
45
16 (16)
16 (16)
16 (16)
90
16 (16)
16 (16)
16 (16)
175
330
600
1000
16 (15.93)
16 (15.24)
16 (14.73)
16 (14.17)
16 (15.84)
16 (15.25)
16 (14.66)
16 (14.16)
16 (15.89)
16 (15.25)
16 (14.76)
16 (14.18)
表 5. Noise in μVRMS (μVPP
)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
40
90
62.50 (62.50)
62.50 (62.50)
62.50 (62.50)
62.50 (71.04)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (37.00)
15.63 (15.63)
15.63 (15.63)
15.63 (15.63)
15.63 (19.17)
15.63 (27.74)
15.63 (39.68)
7.81 (7.81)
7.81 (7.81)
7.81 (7.81)
7.81 (10.76)
7.81 (16.98)
7.81 (23.84)
7.81 (32.97)
3.91 (3.91)
3.91 (3.91)
3.91 (4.11)
3.91 (5.91)
3.91 (8.45)
3.91 (13.19)
3.91 (18.73)
1.95 (1.95)
1.95 (1.95)
1.95 (2.49)
1.95 (3.54)
1.95 (5.07)
1.95 (7.46)
1.95 (11.12)
0.98 (0.98)
0.98 (0.98)
0.98 (1.51)
0.98 (2.13)
0.98 (3.32)
0.98 (5.17)
1.12 (7.06)
0.49 (0.51)
0.49 (0.76)
0.49 (1.05)
0.49 (1.64)
0.49 (2.38)
0.58 (3.50)
0.83 (5.41)
180
350
660
1200
2000
62.50 (105.64) 31.25 (54.97)
62.50 (153.74) 31.25 (78.75)
62.50 (226.39) 31.25 (112.98) 15.63 (59.37)
表 6. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
40
90
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.94)
16 (15.36)
16 (14.90)
16 (14.25)
16 (13.71)
15.75 (13.16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
180
350
660
1200
2000
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.93)
16 (15.40)
16 (14.89)
16 (14.24)
16 (13.74)
16 (15.65)
16 (15.14)
16 (14.62)
16 (14.07)
16 (13.49)
16 (15.37)
16 (14.87)
16 (14.23)
16 (13.60)
16 (15.82)
16 (15.24)
16 (14.70)
16 (14.14)
16 (15.76)
16 (15.19)
16 (14.67)
16 (14.15)
16 (15.71)
16 (15.17)
16 (14.66)
16 (14.07)
16 (15.55)
16 (14.88)
16 (14.39)
16 (13.92)
15.80 (13.15) 15.23 (12.53)
18
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表 7. Noise in μVRMS (μVPP
)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
40
62.50 (62.50)
62.50 (62.50)
62.50 (62.50)
62.50 (72.79)
62.50 (103.97)
62.50 (149.07)
62.50 (224.19)
31.25 (31.25)
31.25 (31.25)
31.25 (31.25)
31.25 (33.34)
31.25 (51.15)
31.25 (76.35)
31.25 (113.98)
15.63 (15.63)
15.63 (15.63)
15.63 (15.63)
15.63 (18.31)
15.63 (24.69)
15.63 (37.48)
15.63 (56.87)
90
180
350
660
1200
2000
表 8. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
40
1
2
4
16 (16)
16 (16)
16 (16)
90
16 (16)
16 (16)
16 (16)
180
350
660
1200
2000
16 (16)
16 (16)
16 (16)
16 (15.78)
16 (15.27)
16 (14.75)
16 (14.16)
16 (15.91)
16 (15.29)
16 (14.71)
16 (14.13)
16 (15.77)
16 (15.34)
16 (14.74)
16 (14.14)
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8 Detailed Description
8.1 Overview
The ADS112U04 is a small, low-power, 16-bit, ΔΣ ADC that offers many integrated features to reduce system
cost and component count in applications measuring small sensor signals.
In addition to the ΔΣ ADC core and single-cycle settling digital filter, the device offers a low-noise, high input
impedance, programmable gain amplifier (PGA), an internal 2.048-V voltage reference, and a clock oscillator.
The device also integrates a highly linear and accurate temperature sensor as well as two matched
programmable current sources (IDACs) for sensor excitation. All of these features are intended to reduce the
required external circuitry in typical sensor applications and improve overall system performance. The device is
fully configured through five registers and controlled by six commands through a universal asynchronous
receiver/transmitter (UART)-compatible interface. The Functional Block Diagram section shows the device
functional block diagram.
The ADS112U04 ADC measures a differential signal, VIN, which is the difference in voltage between nodes AINP
and AINN. The converter core consists of a differential, switched-capacitor, ΔΣ modulator followed by a digital
filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the
input voltage. This architecture results in a very strong attenuation of any common-mode signal.
The device has two available conversion modes: single-shot conversion and continuous conversion mode. In
single-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores the
value in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversion
mode is intended to provide significant power savings in systems that require only periodic conversions, or when
there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins
a conversion of the input signal as soon as the previous conversion is completed. New data are available at the
programmed data rate. Data can be read at any time without concern of data corruption and always reflect the
most recently completed conversion.
8.2 Functional Block Diagram
REFP
REFN
AVDD
DVDD
10 ꢀA to
1.5 mA
2.048-V
Reference
Reference
Mux
ADS112U04
AIN0
AIN1
AIN2
AIN3
TX
RX
Digital Filter
and
UART Interface
GPIO0
GPIO1
GPIO2/
RESET
16-bit
ûꢁ ADC
Mux
PGA
DRDY
Precision
Temperature
Sensor
Low Drift
Oscillator
AVSS
DGND
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8.3 Feature Description
8.3.1 Multiplexer
图 45 shows the flexible input multiplexer of the device. Either four single-ended signals, two differential signals,
or a combination of two single-ended signals and one differential signal can be measured. The multiplexer is
configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are measured, the
negative ADC input (AINN) is internally connected to AVSS by a switch within the multiplexer. For system-
monitoring purposes, the analog supply [(AVDD – AVSS) / 4] or the currently selected external reference voltage
[(VREFP – VREFN) / 4] can be selected as inputs to the ADC. The multiplexer also offers the possibility to route any
of the two programmable current sources to any analog input (AINx) or to the dedicated reference pins (REFP,
REFN).
System Monitors
(VREFP œ VREFN) / 4
(AVDD œ AVSS) / 4
AVDD
IDAC1
AVDD
IDAC2
(AVDD + AVSS) / 2
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AIN0
AIN1
AVDD
Burnout Current Source (10 µA)
AIN2
AINP
PGA
To ADC
AINN
AIN3
Burnout Current Source (10 µA)
REFP
REFN
AVSS
AVSS
图 45. Analog Input Multiplexer
Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. The absolute voltage on any input
must stay within the range provided by 公式 3 to prevent the ESD diodes from turning on:
AVSS – 0.3 V < V(AINx) < AVDD + 0.3 V
(3)
If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or
series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings
table). Overdriving an unused input on the device can affect conversions taking place on other input pins.
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Feature Description (接下页)
8.3.2 Low-Noise Programmable Gain Stage
The device features programmable gains of 1, 2, 4, 8, 16, 32, 64, and 128. Three bits (GAIN[2:0]) in the
configuration register are used to configure the gain. Gains are achieved in two stages. The first stage is a low-
noise, low-drift, high input impedance, programmable gain amplifier (PGA). The second gain stage is
implemented by a switched-capacitor circuit at the input to the ΔΣ modulator. 表 9 shows how each gain is
implemented.
表 9. Gain Implementation
GAIN SETTING
PGA GAIN
SWITCHED-CAPACITOR GAIN
1
2
1
1
1
2
4
4
4
4
4
4
4
1
8
2
16
32
64
128
4
8
16
32
The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the
PGA gain. The input is equipped with an electromagnetic interference (EMI) filter. 图 46 shows a simplified
diagram of the PGA.
200 ꢀ
AINP
+
-
A1
25 pF
RF
OUTP
OUTN
VOUT = PGA Gain·VIN
VIN
RG
RF
-
A2
200 ꢀ
AINN
+
25 pF
图 46. Simplified PGA Diagram
VIN denotes the differential input voltage VIN = VAINP – VAINN. Use 公式 4 to calculate the gain of the PGA. Gain is
changed inside the device using a variable resistor, RG.
PGA Gain = 1 + 2 · RF / RG
(4)
The switched-capacitor gain is changed using variable capacitors at the input to the ΔΣ modulator. Gains 1, 2,
and 4 are implemented by using only the switched-capacitor circuit, which allows these gains to be used even
when the PGA is bypassed; see the Bypassing the PGA section for more information about bypassing the PGA.
公式 5 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain setting
and the reference voltage used:
FSR = ±VREF / Gain
(5)
22
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表 10 shows the corresponding full-scale ranges when using the internal 2.048-V reference.
表 10. Full-Scale Range
GAIN SETTING
FSR
1
2
±2.048 V
±1.024 V
±0.512 V
±0.256 V
±0.128 V
±0.064 V
±0.032 V
±0.016 V
4
8
16
32
64
128
8.3.2.1 PGA Input Voltage Requirements
As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded.
The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA
output. The specified minimum and maximum absolute input voltages (VAINP and VAINN) depend on the PGA gain,
the maximum differential input voltage (VINMAX), and the tolerance of the analog power-supply voltages (AVDD
and AVSS). Because gain on the ADS112U04 is implemented by both the PGA and a switched-capacitor gain
circuit, there are two formulas that define the absolute input voltages. Use 公式 6 when the device gain is
configured to less than or equal to 4. Use 公式 7 when the device gain is greater than 4. Use the maximum
differential input voltage expected in the application for VINMAX
.
AVSS + 0.2 V ≤ VAINP, VAINN ≤ AVDD – 0.2 V
(6)
(7)
AVSS + 0.2 V + |VINMAX| · (Gain – 4) / 8 ≤ VAINP, VAINN ≤ AVDD – 0.2 V – |VINMAX| · (Gain – 4) / 8
图 47 graphically shows the relationship between the PGA input voltages to the PGA output voltages for gains
larger than 4. The PGA output voltages (VOUTP, VOUTN) depend on the PGA gain and the differential input voltage
magnitudes. For linear operation, the PGA output voltages must not exceed AVDD – 0.2 V or AVSS + 0.2 V. 图
47 depicts an example of a positive differential input voltage that results in a positive differential output voltage.
PGA Input
PGA Output
AVDD
AVDD œ 0.2 V
VOUTP = VAINP + VIN ‡ (Gain œ 4) / 8
VAINP
VIN = VAINP œ VAINN
VAINN
VOUTN = VAINN œ VIN ‡ (Gain œ 4) / 8
AVSS + 0.2 V
AVSS
图 47. PGA Input/Output Voltage Relationship
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8.3.2.2 Bypassing the PGA
At gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise PGA by setting the
PGA_BYPASS bit in the configuration register. Disabling the PGA lowers the overall power consumption and
also removes the restrictions of 公式 6 and 公式 7 for the absolute input voltage range. The usable absolute input
voltage range is (AVSS – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V) when the PGA is disabled.
In order to measure single-ended signals that are referenced to AVSS (AINP = VIN, AINN = AVSS), the PGA must
be bypassed. Configure the device for single-ended measurements by either connecting one of the analog inputs
to AVSS externally or by using the internal AVSS connection of the multiplexer (MUX[3:0] settings 1000 through
1011). When configuring the internal multiplexer for settings where AINN = AVSS (MUX[3:0] = 1000 through
1011), the PGA is automatically bypassed and disabled irrespective of the PGA_BYPASS setting and gain is
limited to 1, 2, and 4. In case gain is set to greater than 4, the device limits gain to 4.
When the PGA is disabled, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An
internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from
the capacitor charging and discharging is minimal. See the Electrical Characteristics table for the typical values
of absolute input currents (current flowing into or out of each input) and differential input currents (difference in
absolute current between the positive and negative input) when the PGA is disabled.
For signal sources with high output impedance, external buffering may still be necessary. Active buffers can
introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.
8.3.3 Voltage Reference
The device offers an integrated, low-drift, 2.048-V reference. For applications that require a different reference
voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFP
and REFN). In addition, the analog supply (AVDD – AVSS) can be used as a reference.
The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal
reference is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when
coming out of power-down mode, or when switching from an external reference source to the internal reference.
The differential reference input allows freedom in the reference common-mode voltage. The reference inputs are
internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required
when using an external reference. When used in ratiometric applications, the reference inputs do not load the
external circuitry; however, the analog supply current increases when using an external reference because the
reference buffers are enabled.
In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and
drift of the voltage reference is reflected in the conversion result.
24
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8.3.4 Modulator and Internal Oscillator
A ΔΣ modulator is used in the ADS112U04 to convert the analog input voltage into a pulse code modulated
(PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 4, where fCLK is provided
by the internal oscillator. The oscillator frequency, and therefore also the modulator frequency, depend on the
selected operating mode. 表 11 shows the oscillator and modulator frequencies for the different operating modes.
表 11. Oscillator and Modulator Clock Frequencies for Different Operating Modes
OPERATING MODE
Normal mode
fCLK
fMOD
1.024 MHz
2.048 MHz
256 kHz
512 kHz
Turbo mode
8.3.5 Digital Filter
The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and
decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the
different data rates and always settles within a single cycle. The frequency responses of the digital filter are
illustrated in 图 48 to 图 56 for different output data rates. The filter notches and output data rate scale
proportionally with the clock frequency. The internal oscillator can vary over temperature as specified in the
Electrical Characteristics table. The data rate or conversion time, respectively, and consequently also the filter
notches vary proportionally.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
46
48
50
52
54
56
58
60
62
64
Frequency (Hz)
D002
D001
图 48. Filter Response
(Normal Mode, DR = 20 SPS)
图 49. Detailed View of the Filter Response
(Normal Mode, DR = 20 SPS)
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
0
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
filt
D004
图 50. Filter Response
图 51. Filter Response
(Normal Mode, DR = 45 SPS)
(Normal Mode, DR = 90 SPS)
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0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
100 200 300 400 500 600 700 800 900 1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Frequency (Hz)
D005
D006
图 52. Filter Response
图 53. Filter Response
(Normal Mode, DR = 175 SPS)
(Normal Mode, DR = 330 SPS)
0
-20
-40
-60
-80
0
-20
-40
-60
-80
0
500 1000 1500 2000 2500 3000 3500 4000
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Frequency (kHz)
D007
D008
图 54. Filter Response
(Normal Mode, DR = 600 SPS)
图 55. Filter Response
(Normal Mode, DR = 1 kSPS)
0
-20
-40
-60
-80
0
1
2
3
4
5
6
7
8
9
10
Frequency (kHz)
D009
图 56. Filter Response
(Turbo Mode, DR = 2 kSPS)
26
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8.3.6 Conversion Times
表 12 shows the actual conversion times for each data rate setting. The values provided are in terms of tCLK
cycles and in milliseconds.
Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.
The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command
is latched.
Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to the
DRDY falling edge and rounded to the next tCLK. The exact time that a command is latched in relation to the
rising edge of the stop bit depends on the baud rate; see the Command Latching section for details about
command latch timing.
表 12. Conversion Times
CONTINUOUS CONVERSION MODE(1)
SINGLE-SHOT CONVERSION MODE
NOMINAL
DATA RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
ACTUAL
ACTUAL
CONVERSION TIME
(ms)
ACTUAL
ACTUAL
CONVERSION TIME
(ms)
CONVERSION TIME
CONVERSION TIME
(2)
(2)
(tCLK
)
(tCLK)
NORMAL MODE
20
13.1
20.0
51192
22780
11532
5916
49.99
22.5
11.26
5.78
3.04
1.68
1.01
51213
22805
11557
5941
50.01
22.27
11.29
5.80
45
90
39.6
175
77.8
330
150.1
279.0
483.8
3116
3141
3.07
600
1724
1749
1.71
1000
1036
1061
1.04
TURBO MODE
40
90
17.1
39.9
51192
22780
11532
5916
25.00
11.12
5.63
2.89
1.52
0.84
0.51
51217
22809
11561
5945
25.01
11.14
5.65
2.90
1.54
0.86
0.52
180
350
660
1200
2000
79.2
155.6
300.3
558.1
967.6
3116
3145
1724
1753
1036
1065
(1) The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command is latched. The times
listed in this table do not include that time.
(2) tCLK = 1 / fCLK. fCLK = 1.024 MHz in normal mode and 2.048 MHz in turbo mode.
Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not
affect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in the
Electrical Characteristics table for oscillator accuracy.
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8.3.7 Excitation Current Sources
The device provides two matched programmable excitation current sources (IDACs) for resistance temperature
detector (RTD) applications. The output current of the current sources can be programmed to 10 µA, 50 µA,
100 µA, 250 µA, 500 µA, 1000 µA, or 1500 µA using the respective bits (IDAC[2:0]) in the configuration register.
Each current source can be connected to any of the analog inputs (AINx) as well as to the dedicated reference
inputs (REFP and REFN). Both current sources can also be connected to the same pin. Routing of the IDACs is
configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the
compliance voltage of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to
≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD
applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see
the 3-Wire RTD Measurement section for more details).
The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using
the IDAC[2:0] bits. Set the IDAC current to the respective value using the IDAC[2:0] bits and then select the
routing for each IDAC (I1MUX[2:0], I2MUX[2:0]) thereafter.
In single-shot conversion mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are
set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is
issued.
Keep in mind that the analog supply current increases when enabling the IDACs (that is, when the IDAC[2:0] bits
are set to a value other than 000). The IDAC circuit needs this bias current to operate even when the IDACs are
not routed to any pin (I1MUX[2:0] = I2MUX[2:0] = 000). In addition, the selected output current is drawn from the
analog supply when I1MUX[2:0] or I2MUX[2:0] are set to a value other than 000.
8.3.8 Sensor Detection
To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources.
When enabled by setting the respective bit (BCS) in the configuration register, one current source provides
current to the positive analog input (AINP) currently selected and the other current source sinks current from the
selected negative analog input (AINN).
In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and
the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the
sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor.
The absolute value of the burn-out current sources typically varies by ±5% and the internal multiplexer adds a
small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be
difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage
drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read
a value higher than zero.
Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are
enabled. Disable the burn-out current sources when preforming the precision measurement, and only enable
these sources to test for sensor fault conditions.
8.3.9 System Monitor
The device provides some means for monitoring the analog power supply and the external voltage reference. To
select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the
configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the
configuration register settings when the monitoring feature is used. The system monitor function only provides a
coarse result and is not meant to be a precision measurement.
When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD –
AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference
source is selected in the configuration register (VREF[1:0]).
When monitoring the external reference voltage source (MUX[3:0] = 1100), the result is approximately (V(REFP)
V(REFN)) / 4. The device automatically uses the internal reference for the measurement.
–
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8.3.10 Temperature Sensor
The ADS112U04 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by
setting bit TS = 1 in the configuration register. When in temperature sensor mode, the settings of configuration
register 0 have no effect and the device uses the internal reference for measurement, regardless of the selected
voltage reference source. Temperature readings follow the same process as the analog inputs for starting and
reading conversion results. Temperature data are represented as a 14-bit effective result that is left-justified
within the 16-bit conversion result. Data are output starting with the least significant bit (LSB). When reading the
two data bytes, the last 14 bits (MSBs) are used to indicate the temperature measurement result. The LSBs of
the data output do not indicate temperature. Only the 14 MSBs are relevant. One 14-bit LSB equals 0.03125°C.
Negative numbers are represented in binary two's complement format. 表 13 shows the mapping between
temperature and digital codes.
表 13. 14-Bit Temperature Data Format
DIGITAL OUTPUT
TEMPERATURE (°C)
BINARY
HEX
1000
0FFF
0C80
0960
0640
0320
0008
0001
0000
3FF8
3CE0
3B00
128
127.96875
100
01 0000 0000 0000
00 1111 1111 1111
00 1100 1000 0000
00 1001 0110 0000
00 0110 0100 0000
00 0011 0010 0000
00 0000 0000 1000
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1000
11 1100 1110 0000
11 1011 0000 0000
75
50
25
0.25
0.03125
0
–0.25
–25
–40
8.3.10.1 Converting From Temperature to Digital Codes
8.3.10.1.1 For Positive Temperatures (For Example, 50°C):
Two's complement is not performed on positive numbers. Therefore, simply convert the number to binary code in
a 14-bit, left-justified format with the MSB = 0 to denote the positive sign.
Example: 50°C / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000
8.3.10.1.2 For Negative Temperatures (For Example, –25°C):
Generate the two's complement of a negative number by complementing the absolute binary number and adding
1. Then, denote the negative sign with the MSB = 1.
Example: |–25°C| / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000
Two's complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000
8.3.10.2 Converting From Digital Codes to Temperature
To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply
multiply the decimal code by 0.03125°C to obtain the result. If the MSB is a 1, subtract 1 from the result and
complement all bits. Then, multiply the result by –0.03125°C.
Example: The device reads back 0960h: 0960h has an MSB = 0.
0960h · 0.03125°C = 2400 · 0.03125°C = 75°C
Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.
Subtract 1 and complement the result: 3CE0h → 0320h
0320h · (–0.03125°C) = 800 · (–0.03125°C) = –25°C
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8.3.11 Offset Calibration
The internal multiplexer offers the option to short both PGA inputs (AINP and AINN) to mid-supply (AVDD +
AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the
shorted input voltage reading in a microcontroller and consequently subtracting the result from each following
reading. Take multiple readings with the inputs shorted and average the result to reduce the effect of noise.
8.3.12 Conversion Data Counter
The ADS112U04 offers an optional data counter word to help the host determine if the conversion data are new.
The DCNT bit in the configuration register enables the conversion data counter. The data counter appears as an
8-bit word that precedes the conversion data each time a conversion result is read. The reset value of the
counter is 00h. The word increments each time the ADC completes a conversion. The counter rolls over to 00h
after reaching FFh.
When the host reads a conversion result, the host can determine if the data being read are new by comparing
the counter value with the counter value obtained with the last data read. If the counter values are the same,
then this result indicates that no new conversion data are available from the ADC. The counter can also help the
host determine if a conversion result was missed.
Reset the conversion data counter by clearing the DCNT bit to 0 and then setting DCNT back to 1. A device
reset also resets the conversion data counter.
8.3.13 Data Integrity
There are two methods for ensuring data integrity for data output on the ADS112U04. Output data can be
register contents or conversion results. The optional data counter word that precedes conversion data is covered
by both data integrity options. The data integrity modes are configured using the CRC[1:0] bits in the
configuration register. When CRC[1:0] = 01, a bitwise-inverted version of the data is output immediately following
the most significant byte (MSB) of the data.
When CRC[1:0] = 10, a 16-bit CRC word is output immediately following the MSB of the data. In CRC mode, the
checksum bytes are the 16-bit remainder of the bitwise exclusive-OR (XOR) of the data bytes with a CRC
polynomial. The CRC is based on the CRC-16-CCITT polynomial: x16 + x12 + x5 + 1 with an initial value of
FFFFh.
The 17 binary coefficients of the polynomial are: 1 0001 0000 0010 0001. To calculate the CRC, divide (XOR
operation) the data bytes (excluding the CRC) with the polynomial and compare the calculated CRC values to
the ADC CRC value. If the values do not match, a data transmission error has occurred. In the event of a data
transmission error, read the data again.
The following list shows a general procedure to compute the CRC value:
1. Left-shift the initial data value by 16 bits, with zeros padded to the right.
2. Align the MSB of the CRC polynomial to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation creates a
new, shorter-length value. The bits of the data values that are not in alignment with the CRC polynomial drop
down and append to the right of the new XOR result.
4. When the XOR result is less than 1 0000 0000 0000 0000, the procedure ends, yielding the 16-bit CRC
value. Otherwise, continue with the XOR operation shown in step 2 using the current data value. The number
of loop iterations depends on the value of the initial data.
8.3.14 General-Purpose Digital Inputs/Outputs
The ADS112U04 offers three dedicated general-purpose input/output (GPIO) pins. Use the GPIOnDIR (where n
= 0, 1, 2) bits in the configuration register to configure the pin as either an input or an output. The GPIOnDAT
bits in the configuration register contain the input or output GPIO data. If a GPIO pin is configured as an input,
the respective GPIOnDAT bit reads the status of the pin; if the GPIO pin is configured as an output, write the
output status to the respective GPIOnDAT bit.
GPIO2 shares a pin with the DRDY signal. When the pin is configured as an output by the GPIO2DIR bit, the
GPIO2SEL bit in the configuration register selects the function of the GPIO2/DRDY pin. If the GPIO2SEL bit is
cleared, GPIO2 is routed to the pin. If the bit is set, the pin is driven with the DRDY signal.
See the Register Descriptions section for more information regarding the configuration of the GPIO pins.
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8.4 Device Functional Modes
图 57 shows a flow chart of the different operating modes and how the device transitions from one mode to
another.
Power-On Reset or
RESET pin high or
RESET command(1)
Reset device to
default settings
Low-power state
No
No
START/SYNC
Command?
POWERDOWN
Command?
Yes
Yes
Conversion
Mode
Power-down Mode(3)
Yes
No
Start new
conversion
START/SYNC
Command?
No
0 = Single-Shot
1 = Continuous
conversion mode
conversion mode
Yes
Conversion
POWERDOWN
Command?
mode selection(2)
(1) Any reset (power-on, command, or pin) immediately resets the device.
(2) The conversion mode is selected with the CM bit in the configuration register.
(3) The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down
mode.
图 57. Operating Flow Chart
8.4.1 Power-Up and Reset
The ADS112U04 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESET
command.
When a reset occurs, the configuration registers reset to the default values and the device enters a low-power
state. The device then waits for the START/SYNC command to enter conversion mode; see the UART Timing
Requirements section for reset timing information.
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Device Functional Modes (接下页)
8.4.1.1 Power-On Reset
During power up, the device is held in reset. The power-on reset releases approximately 600 µs after both
supplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (including
the voltage reference) are stable and communication with the device is possible. As part of the reset process, the
device sets all bits in the configuration registers to the respective default settings. After power-up, the device
enters a low-power state. The power-up behavior is intended to prevent systems with tight power-supply
requirements from encountering a current surge during power-up.
8.4.1.2 RESET Pin
Reset the ADC by taking the RESET pin low for a minimum of tw(RSL) and then returning the pin high. After the
rising edge of the RESET pin, a delay time of td(RSTX) is required before sending the first serial interface
command or starting a conversion; see the UART Timing Requirements table for reset timing information.
8.4.1.3 Reset by Command
Reset the ADC by using the RESET command (06h or 07h). After the RESET command is latched, a delay time
of td(RSTX) is required before sending the first serial interface command or starting a conversion; see the UART
Timing Requirements table for reset timing information. The exact time that a command is latched in relation to
the rising edge of the stop bit depends on the baud rate; see the Command Latching section for details about
command latch timing.
8.4.2 Conversion Modes
The device operates in one of two conversion modes that are selected by the CM bit in the configuration register.
These conversion modes are single-shot conversion and continuous conversion mode. A START/SYNC
command must be issued each time the CM bit is changed.
8.4.2.1 Single-Shot Conversion Mode
In single-shot conversion mode, the device only performs a conversion when a START/SYNC command is
issued. The device consequently performs one single conversion and returns to a low-power state afterwards.
The internal oscillator and all analog circuitry (except for the excitation current sources) are turned off while the
device waits in this low-power state until the next conversion is started. Writing to any configuration register
besides register 04h when a conversion is ongoing functions as a new START/SYNC command that stops the
current conversion and restarts a single new conversion. Each conversion is fully settled (assuming the analog
input signal settles to the final value before the conversion starts) because the device digital filter settles within a
single cycle.
8.4.2.2 Continuous Conversion Mode
In continuous conversion mode, the device continuously performs conversions. When a conversion completes,
the device places the result in the output buffer and immediately begins another conversion.
In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.
The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command
is latched. The exact time that a command is latched in relation to the rising edge of the stop bit depends on the
baud rate; see the Command Latching section for details about command latch timing. Writing to any
configuration register besides register 04h during an ongoing conversion restarts the current conversion. Send a
START/SYNC command immediately after the CM bit is set to 1.
Stop continuous conversions by sending the POWERDOWN command.
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Device Functional Modes (接下页)
8.4.3 Operating Modes
In addition to the different conversion modes, the device can also be operated in different operating modes that
can be selected to trade-off power consumption, noise performance, and output data rate. These modes are:
normal mode, turbo mode, and power-down mode.
8.4.3.1 Normal Mode
Normal mode is the default mode of operation after power-up. In this mode, the internal modulator of the ΔΣ ADC
runs at a modulator clock frequency of fMOD = fCLK / 4 = 256 kHz, where the system clock (fCLK) is provided by the
internal oscillator. Normal mode offers output data rate options ranging from 20 SPS to 1 kSPS. The data rate is
selected by the DR[2:0] bits in the configuration register.
8.4.3.2 Turbo Mode
Applications that require higher data rates up to 2 kSPS can operate the device in turbo mode. In this mode, the
internal modulator runs at a higher frequency of fMOD = fCLK / 4 = 512 kHz. Compared to normal mode, the device
power consumption increases because the modulator runs at a higher frequency. Running the ADS112U04 in
turbo mode at a comparable output data rate as in normal mode yields better noise performance. For example,
the input-referred noise at 90 SPS in turbo mode is lower than the input-referred noise at 90 SPS in normal
mode.
8.4.3.3 Power-Down Mode
When the POWERDOWN command is issued, the device enters power-down mode after completing the current
conversion. In this mode, all analog circuitry (including the voltage reference and both IDACs) are powered down
and the device typically only uses 400 nA of current. When in power-down mode, the device holds the
configuration register settings and responds to commands, but does not perform any data conversions.
Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous
conversion mode, depending on the conversion mode selected by the CM bit.
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8.5 Programming
8.5.1 UART Interface
The serial data and control interface on the ADS112U04 is universal asynchronous receiver transmitter (UART)
compatible. Commands from the host are received by the device through the RX pin. Data are transmitted from
the device to the host through the TX pin. The ADS112U04 actively synchronizes to the baud rate of the host
each time the host transmits a command. The interface is half duplex; meaning only either the host or the device
can communicate at any given time.
8.5.1.1 Receive (RX)
The UART receive pin (RX) is used to send data (commands and register data) to the device. The device never
drives the RX pin.
8.5.1.2 Transmit (TX)
The UART transmit pin (TX) is used to read conversion and register data from the device. The TX pin is held at
logic high when not transmitting data.
8.5.1.3 Data Ready (DRDY)
DRDY indicates when a new conversion result is ready for retrieval. The DRDY signal appears on the
GPIO2/DRDY pin only when GPIO2 is configured as an output and the GPIO2SEL bit in the configuration
register is set. When DRDY falls low, new conversion data are ready. DRDY transitions back high when the
conversion result is latched for output transmission. In case a conversion result in continuous conversion mode is
not read (only applies to manual data read mode), DRDY pulses high for tw(DRH) before the next conversion
completes; see the UART Switching Characteristics section for more details.
8.5.1.4 Protocol
Serial data transfer using the UART interface is performed in byte increments. For each byte that is sent by
either the host or the device, a start bit (logic low) is transmitted first, followed by eight bits of data in LSB-first
format. A stop bit (logic high) is transmitted at the end of each byte. By using a start and stop bit for each byte,
the ADS112U04 can latch each byte and maintain synchronous communication throughout the process.
The ADS112U04 actively synchronizes to the baud rate of the host each time the host transmits a command.
Baud rate synchronization occurs when the host transmits the synchronization word (55h) preceding any
command sent to the ADS112U04. The host must always transmit the synchronization word first followed by the
command byte or bytes. Each byte begins with a start bit and ends with a stop bit, including the synchronization
word.
图 58 shows the timing sequence for the UART communication. In 图 58, as an example, there is only one byte
for the command and one byte for the readback data. There may be multiple bytes for a command or the data
that is read from the device. The protocol takes the 8-N-1 format: eight (8) data bits, no (N) parity bit, and one (1)
stop bit.
tfrom the hostt
Synchronization Word
Command Word
S
1
0
1
0
1
0
1
0
P
S
C0
C1
C2
C3
C4
C5
C6
C7
P
RX
TX
tfrom the devicet
S
D0
D1
D2
D3
D4
D5
D6
D7
P
图 58. Example ADS112U04 UART Protocol
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Programming (接下页)
8.5.1.5 Timeout
The ADS112U04 offers a UART timeout feature that can be used to recover communication when a serial
interface transmission is interrupted. If the host initiates contact with the ADS112U04 but subsequently remains
idle for 32760 · tMOD in normal mode and 65520 · tMOD in turbo mode before completing a command, the
ADS112U04 interface is reset. If the ADS112U04 interface has reset because of a timeout condition, the host
must abort the transaction and restart the communication again by sending the synchronization word first
followed by the command byte or bytes.
8.5.2 Data Format
The device provides 16 bits of data in binary two's complement format. Use 公式 8 to calculate the size of one
code (LSB).
1 LSB = (2 · VREF / Gain) / 216 = +FS / 215
(8)
A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a
negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these
codes for signals that exceed full-scale.
表 14 summarizes the ideal output codes for different input signals.
表 14. Ideal Output Code versus Input Signal
INPUT SIGNAL,
VIN = VAINP – VAINN
≥ FS (215 – 1) / 215
FS / 215
IDEAL OUTPUT CODE(1)
7FFFh
0001h
0000h
FFFFh
8000h
0
–FS / 215
≤ –FS
(1) Excludes the effects of noise, INL, offset, and gain errors.
图 59 shows the mapping of the analog input signal to the output codes.
7FFFh
7FFEh
0001h
0000h
FFFFh
8001h
8000h
. . .
. . .
-FS
-FS
0
+FS
Input Voltage VIN
215 - 1
215
215 - 1
+FS
215
图 59. Code Transition Diagram
注
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 0000h to 7FFFh. However, because of device offset, the
ADS112U04 can still output negative codes when VAINP is close to 0 V.
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8.5.3 Commands
As 表 15 shows, the device offers six different commands to control device operation. Four commands are stand-
alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG) and
write (WREG) configuration register data from and to the device require additional information as part of the
instruction. For clarity, 表 15 shows the command bits MSB first, but data are always transmitted byte-wise LSB
first on the ADS112U04.
表 15. Command Definitions
COMMAND
DESCRIPTION
COMMAND BYTE(1)
0000 011x
0000 100x
0000 001x
0001 xxxx
RESET
Reset the device
START/SYNC
POWERDOWN
RDATA
Start or restart conversions
Enter power-down mode
Read data by command
RREG
Read register at address rrr
Write register at address rrr
0010 rrrx
WREG
0100 rrrx
(1) Operands: rrr = register address (000 to 100), x = don't care.
8.5.3.1 RESET (0000 011x)
Resets the device to the default states. Wait at least td(RSRX) after the RESET command is sent before sending
any other command.
8.5.3.2 START/SYNC (0000 100x)
In single-shot conversion mode, the START/SYNC command is used to start a single conversion, or (when sent
during an ongoing conversion) to reset the digital filter and then restart a single new conversion. When the
device is set to continuous conversion mode, the START/SYNC command must be issued one time to start
converting continuously. Sending the START/SYNC command when converting in continuous conversion mode
resets the digital filter and restarts continuous conversions.
8.5.3.3 POWERDOWN (0000 001x)
The POWERDOWN command places the device into power-down mode. The command shuts down all internal
analog components and turns off both IDACs, but holds all register values. In case the POWERDOWN command
is issued when a conversion is ongoing, the conversion completes before the ADS112U04 enters power-down
mode. As soon as a START/SYNC command is issued, all analog components return to their previous states.
8.5.3.4 RDATA (0001 xxxx)
The RDATA command loads the output shift register with the most recent conversion result right after the
command is received. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY
pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,
DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is
high.
注
UART transmissions take place byte-wise. Bytes are transmitted least significant bit first.
Data words are transmitted least significant byte first.
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8.5.3.5 RREG (0010 rrrx)
The RREG command reads the value of the register at address rrr. If the register pointed to by rrr does not exist,
the read back data are 00h. 图 60 shows the sequence for reading a register. The synchronization word must be
sent by the host before the RREG command is sent.
RX
TX
10101010
0010 0100
REG 2h DATA
图 60. Read Register Sequence
8.5.3.6 WREG (0100 rrrx dddd dddd)
The WREG command writes dddd dddd to the register at address rrr. If the register pointed to by rrr does not
exist, the WREG command is ignored. 图 61 shows the sequence for writing a register. The synchronization word
must be sent by the host before the WREG command is sent. Writing to any register besides register 04h forces
the digital filter to reset and any ongoing ADC conversion to restart.
RX
TX
10101010
0010 0010
REG 2h DATA
图 61. Write Register Sequence
8.5.3.7 Command Latching
The ADS112U04 interface automatically synchronizes to the baud rate of the host, meaning that the time
required for commands to be latched by the interface varies with baud rate. Commands are not processed until
after being latched by the ADS112U04.
Commands are latched by the ADS112U04 when the device detects the stop bit. Stop bit detection generally
occurs in the middle of the stop bit where the middle of the stop bit is defined as tBAUD / 2 after the rising edge of
the stop bit. However, this timing is not exact because of the asynchronous nature between the host baud
clocking and the ADS112U04 internal oscillator as well as jitter in the ADS112U04 internal oscillator. The stop bit
detection timing error can be as large as 4 · tCLK in normal mode and 8 · tCLK in turbo mode.
8.5.4 Reading Data
There are two ways to read data from the ADS112U04: manual data read mode and automatic data read mode.
In manual data read mode, the host retrieves data by issuing the RDATA command. In automatic data read
mode, the ADS112U04 automatically outputs conversion data on the TX pin as soon as a conversion completes.
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8.5.4.1 Manual Data Read Mode
In manual data read mode, data are read by issuing the RDATA command. The ADS112U04 responds to the
RDATA command with the latest conversion data. There are three ways to monitor for new conversion data.
One way is to monitor for the falling edge of the DRDY signal. To configure the GPIO2/DRDY pin to output the
DRDY signal, the pin must be configured as an output by setting the GPIO2DIR bit in the configuration register,
and DRDY must be multiplexed to the pin by setting the GPIO2SEL bit in the configuration register.
图 62 shows the timing diagram for collecting data in manual data read mode using DRDY to indicate new data.
DRDY
RX
TX
55h
RDATA
DATA LSB
DATA MSB
图 62. Manual Data Read Mode Using DRDY (Continuous Conversion Mode)
Another way to monitor for a new conversion result is to periodically read the DRDY bit in the configuration
register. If set, the DRDY bit indicates that a new conversion result is ready for retrieval. The host can
subsequently issue an RDATA command to retrieve the data. The rate at which the host polls the ADS112U04
for new data must be at least as fast as the data rate in continuous conversion mode to prevent the host from
missing a conversion result.
If a new conversion result becomes ready during a UART transmission, the transmission is not corrupted. The
new data are loaded into the output shift register upon the following RDATA command.
图 63 shows the timing diagram for collecting data in manual data read mode using the DRDY bit in the
configuration register to indicate new data.
RX
TX
55h
RREG 2h
55h
RDATA
REGISTER 2h
DATA LSB
DATA MSB
图 63. Manual Data Read Mode Using the RREG Command (Continuous Conversion Mode)
The last way to detect if new conversion data are available is through the use of the conversion data counter
word. In this mode, the host periodically requests data from the device using the RDATA command and checks
the conversion data counter word against the conversion data counter word read for the previous data received.
If the counter values are the same, the host can disregard the data because that data has already been
gathered. If the counter has incremented, the host records the data. The rate at which the host polls the
ADS112U04 for new data must be at least as fast as the data rate in continuous conversion mode to prevent the
host from missing a conversion result.
If a new conversion result becomes ready during a UART transmission, the transmission is not corrupted. The
new data are loaded into the output shift register after the following RDATA command.
图 64 shows the timing diagram for collecting data in manual data read mode using the conversion data counter
word to indicate new data.
RX
TX
55h
RDATA
COUNTER
DATA LSB
DATA MSB
图 64. Manual Data Read Mode Using the Conversion Data Counter (Continuous Conversion Mode)
The conversion data counter can be used in conjunction with the previously discussed methods of detecting new
data to ensure that the host did not miss a conversion result.
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8.5.4.2 Automatic Data Read Mode
In automatic data read mode, the ADS112U04 automatically outputs the latest conversion data on the TX pin
without the host sending an RDATA command. The DRDY signal does not have to be monitored in this mode;
thus making this mode useful for applications that require the number of digital lines to be minimized. Using
automatic data read mode requires the least amount of communication between the host and device when
compared to monitoring the DRDY bit of the configuration register or the conversion data counter in manual data
read mode. The conversion data counter can also be used in this mode to verify that the host has not missed a
conversion result. The host must not send commands to the ADS112U04 while data are being output in
automatic data read mode to avoid data corruption.
图 65 shows the timing diagram for collecting data in automatic data read mode.
DRDY
RX
TX
DATA0 LSB
DATA0 MSB
DATA1 LSB
DATA1 MSB
图 65. Automatic Data Read Mode (Continuous Conversion Mode)
8.5.5 Data Integrity
The optional data integrity checks can be configured using the CRC[1:0] bits in the configuration register. When
one of the data integrity options is enabled, the data integrity check is output on the TX pin immediately following
the conversion or register data; see the Data Integrity section for detailed description of the data integrity
functionality. Additional words are always two bytes when CRC16 is enabled. The number of additional words in
the inverted data mode when reading conversion data varies from two to three depending on whether the
conversion data counter is enabled. 图 66 and 图 67 show register and conversion data retrieval when CRC is
enabled, respectively. 图 68 shows data retrieval when inverted data output is enabled.
RX
TX
55h
RREG
REG DATA
CRC0
CRC1
图 66. Register Data Output With CRC Enabled
RX
55h
RDATA
TX
DATA LSB
DATA MSB
CRC0
CRC1
图 67. Conversion Data Output With CRC Enabled
RX
TX
55h
RDATA
DATA LSB
DATA MSB
DATA LSB
DATA MSB
图 68. Conversion Data Output With Inverted Data Output Enabled
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8.6 Register Map
8.6.1 Configuration Registers
The device has five 8-bit configuration registers that are accessible through the UART interface using the RREG
and WREG commands. After power-up or reset, all registers are set to the default values (which are all 0). All
register values are retained during power-down mode. 表 16 shows the register map of the configuration
registers.
表 16. Configuration Register Map
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(Hex)
00h
01h
02h
03h
04h
MUX[3:0]
GAIN[2:0]
PGA_BYPASS
TS
DR[2:0]
DCNT
MODE
CM
VREF[1:0]
DRDY
0
CRC[1:0]
BCS
IDAC[2:0]
0
I1MUX[2:0]
GPIO2DIR
I2MUX[2:0]
GPIO2SEL
AUTO
GPIO1DIR
GPIO0DIR
GPIO2DAT
GPIO1DAT
GPIO0DAT
8.6.2 Register Descriptions
表 17 lists the access codes for the ADS112U04 registers.
表 17. Register Access Type Codes
Access Type
Code
Description
Read
R
R
R/W
W
R/W
W
Read-Write
Write
-n
Value after reset or the default value
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8.6.2.1 Configuration Register 0 (address = 00h) [reset = 00h]
图 69. Configuration Register 0
7
6
5
4
3
2
1
0
MUX[3:0]
R/W-0h
GAIN[2:0]
R/W-0h
PGA_BYPASS
R/W-0h
表 18. Configuration Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUX[3:0]
R/W
0h
Input multiplexer configuration.
These bits configure the input multiplexer.
For settings where AINN = AVSS, the PGA must be disabled (PGA_BYPASS = 1)
and only gains 1, 2, and 4 can be used.
0000 : AINP = AIN0, AINN = AIN1 (default)
0001 : AINP = AIN0, AINN = AIN2
0010 : AINP = AIN0, AINN = AIN3
0011 : AINP = AIN1, AINN = AIN0
0100 : AINP = AIN1, AINN = AIN2
0101 : AINP = AIN1, AINN = AIN3
0110 : AINP = AIN2, AINN = AIN3
0111 : AINP = AIN3, AINN = AIN2
1000 : AINP = AIN0, AINN = AVSS
1001 : AINP = AIN1, AINN = AVSS
1010 : AINP = AIN2, AINN = AVSS
1011 : AINP = AIN3, AINN = AVSS
1100 : (V(REFP) – V(REFN)) / 4 monitor (PGA bypassed)
1101 : (AVDD – AVSS) / 4 monitor (PGA bypassed)
1110 : AINP and AINN shorted to (AVDD + AVSS) / 2
1111 : Reserved
3:1
GAIN[2:0]
R/W
0h
Gain configuration.
These bits configure the device gain.
Gains 1, 2, and 4 can be used without the PGA. In this case, gain is obtained by
a switched-capacitor structure.
000 : Gain = 1 (default)
001 : Gain = 2
010 : Gain = 4
011 : Gain = 8
100 : Gain = 16
101 : Gain = 32
110 : Gain = 64
111 : Gain = 128
0
PGA_BYPASS
R/W
0h
Disables and bypasses the internal low-noise PGA.
Disabling the PGA reduces overall power consumption and allows the absolute
input voltage range to span from AVSS – 0.1 V to AVDD + 0.1 V.
The PGA can only be disabled for gains 1, 2, and 4.
The PGA is always enabled for gain settings 8 to 128, regardless of the
PGA_BYPASS setting.
0 : PGA enabled (default)
1 : PGA disabled and bypassed
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8.6.2.2 Configuration Register 1 (address = 01h) [reset = 00h]
图 70. Configuration Register 1
7
6
5
4
3
2
1
0
DR[2:0]
R/W-0h
MODE
R/W-0h
CM
VREF[1:0]
R/W-0h
TS
R/W-0h
R/W-0h
表 19. Configuration Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
7:5
DR[2:0]
R/W
0h
Data rate.
These bits control the data rate setting depending on the selected operating
mode. 表 20 lists the bit settings for normal and turbo mode.
4
3
MODE
CM
R/W
R/W
R/W
0h
0h
0h
Operating mode.
These bits control the operating mode that the device operates in.
0 : Normal mode (256-kHz modulator clock, default)
1 : Turbo mode (512-kHz modulator clock)
Conversion mode.
This bit sets the conversion mode for the device.
0 : Single-shot conversion mode (default)
1 : Continuous conversion mode
2:1
VREF[1:0]
Voltage reference selection.
These bits select the voltage reference source that is used for the conversion.
00 : Internal 2.048-V reference selected (default)
01 : External reference selected using the REFP and REFN inputs
10 : Analog supply (AVDD – AVSS) used as reference
11 : Analog supply (AVDD – AVSS) used as reference
0
TS
R/W
0h
Temperature sensor mode.
This bit enables the internal temperature sensor and puts the device in
temperature sensor mode.
The settings of configuration register 0 have no effect and the device uses the
internal reference for measurement when temperature sensor mode is enabled.
0 : Temperature sensor mode disabled (default)
1 : Temperature sensor mode enabled
表 20. DR Bit Settings
NORMAL MODE
000 = 20 SPS
001 = 45 SPS
010 = 90 SPS
011 = 175 SPS
100 = 330 SPS
101 = 600 SPS
110 = 1000 SPS
111 = Reserved
TURBO MODE
000 = 40 SPS
001 = 90 SPS
010 = 180 SPS
011 = 350 SPS
100 = 660 SPS
101 = 1200 SPS
110 = 2000 SPS
111 = Reserved
42
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8.6.2.3 Configuration Register 2 (address = 02h) [reset = 00h]
图 71. Configuration Register 2
7
6
5
4
3
2
1
0
DRDY
R-0h
DCNT
R/W-0h
CRC[1:0]
R/W-0h
BCS
IDAC[2:0]
R/W-0h
R/W-0h
表 21. Configuration Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
DRDY
R
0h
Conversion result ready flag.
This bit flags if a new conversion result is ready. This bit is reset when conversion
data are read.
0 : No new conversion result available (default)
1 : New conversion result ready
6
DCNT
R/W
R/W
0h
0h
Data counter enable.
The bit enables the conversion data counter.
0 : Conversion counter disabled (default)
1 : Conversion counter enabled
5:4
CRC[1:0]
Data integrity check enable.
These bits enable and select the data integrity checks.
00 : Disabled (default)
01 : Inverted data output enabled
10 : CRC16 enabled
11 : Reserved
3
BCS
R/W
R/W
0h
0h
Burn-out current sources.
This bit controls the 10-μA, burn-out current sources. The burn-out current
sources can be used to detect sensor faults such as wire breaks and shorted
sensors.
0 : Current sources off (default)
1 : Current sources on
2:0
IDAC[2:0]
IDAC current setting.
These bits set the current for both IDAC1 and IDAC2 excitation current sources.
000 : Off (default)
001 : 10 µA
010 : 50 µA
011 : 100 µA
100 : 250 µA
101 : 500 µA
110 : 1000 µA
111 : 1500 µA
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8.6.2.4 Configuration Register 3 (address = 03h) [reset = 00h]
图 72. Configuration Register 3
7
6
5
4
3
2
1
0
0
I1MUX[2:0]
R/W-0h
I2MUX[2:0]
R/W-0h
AUTO
R/W-0h
R-0h
表 22. Configuration Register 3 Field Descriptions
Bit
Field
I1MUX[2:0]
Type
Reset
Description
7:5
R/W
0h
IDAC1 routing configuration.
These bits select the channel that IDAC1 is routed to.
000 : IDAC1 disabled (default)
001 : IDAC1 connected to AIN0
010 : IDAC1 connected to AIN1
011 : IDAC1 connected to AIN2
100 : IDAC1 connected to AIN3
101 : IDAC1 connected to REFP
110 : IDAC1 connected to REFN
111 : Reserved
4:2
I2MUX[2:0]
R/W
0h
IDAC2 routing configuration.
These bits select the channel that IDAC2 is routed to.
000 : IDAC2 disabled (default)
001 : IDAC2 connected to AIN0
010 : IDAC2 connected to AIN1
011 : IDAC2 connected to AIN2
100 : IDAC2 connected to AIN3
101 : IDAC2 connected to REFP
110 : IDAC2 connected to REFN
111 : Reserved
1
0
RESERVED
AUTO
R
0h
0h
Reserved.
Always write 0
R/W
ADC data output mode.
The bit controls the UART data output mode for the conversion result.
0 : Manual data read mode (default)
1 : Automatic data read mode
44
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8.6.2.5 Configuration Register 4 (address = 04h) [reset = 00h]
图 73. Configuration Register 4
7
0
6
5
4
3
2
1
0
GPIO2DIR
R/W-0h
GPIO1DIR
R/W-0h
GPIO0DIR
R/W-0h
GPIO2SEL
R/W-0h
GPIO2DAT
R/W-0h
GPIO1DAT
R/W-0h
GPIO0DAT
R/W-0h
R-0h
表 23. Configuration Register 4 Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
Reserved.
Always write 0
6
GPIO2DIR
R/W
R/W
R/W
R/W
0h
0h
0h
0h
GPIO2 direction control.
This bit configures GPIO2 as an input or output.
0 : Input (default)
1 : Output
5
4
3
GPIO1DIR
GPIO0DIR
GPIO2SEL
GPIO1 direction control.
This bit configures GPIO1 as an input or output.
0 : Input (default)
1 : Output
GPIO0 direction control.
This bit configures GPIO0 as an input or output.
0 : Input (default)
1 : Output
GPIO2/DRDY control.
This bit controls which source controls the state of the GPIO2/DRDY pin when
GPIO2 is configured as an output.
0 : GPIO2DAT (default)
1 : DRDY
2
1
0
GPIO2DAT
GPIO1DAT
GPIO0DAT
R/W
R/W
R/W
0h
0h
0h
GPIO2 input/output level.
This bit controls the state of GPIO2 when configured as an output or holds the
value of GPIO2 when configured as an input.
0 : Logic low (default)
1 : Logic high
GPIO1 input/output level.
This bit controls the state of GPIO1 when configured as an output or holds the
value of GPIO1 when configured as an input.
0 : Logic low (default)
1 : Logic high
GPIO0 input/output level.
This bit controls the state of GPIO0 when configured as an output or holds the
value of GPIO0 when configured as an input.
0 : Logic low (default)
1 : Logic high
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS112U04 is a precision, 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that offers many
integrated features to ease the measurement of the most common sensor types, including various types of
temperature and bridge sensors. Primary considerations when designing an application with the ADS112U04
include analog input filtering, establishing an appropriate external reference for ratiometric measurements, and
setting the absolute input voltage range for the internal PGA. Connecting and configuring the interface
appropriately is another concern. These considerations are discussed in the following sections.
9.1.1 Interface Connections
图 74 shows the principle interface connections for the ADS112U04.
Microcontroller with UART Interface
0.1 mF
3.3 V
1
2
3
4
5
6
7
8
GPIO1
GPIO0
RESET
DGND
AVSS
AIN3
RX 16
TX 15
3.3 V
3.3 V
14
GPIO2/ DRDY
DVDD 13
AVDD 12
AIN0 11
AIN1 10
Device
3.3 V
0.1 mF
0.1 mF
AIN2
REFN
REFP
9
图 74. Interface Connections
Most microcontroller UART peripherals can operate with the ADS112U04. The baud rate is determined by the
host via a synchronization word that must be sent to the ADS112U04 before each command. Details of the
UART communication protocol of the device can be found in the Programming section.
TI recommends placing 47-Ω resistors in series with all digital input and output pins (TX, RX, and GPIO2/DRDY).
This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care
must be taken to meet all UART timing requirements because the additional resistors interact with the bus
capacitances present on the digital signal lines.
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Application Information (接下页)
9.1.2 Analog Input Filtering
Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process, and
second, to reduce external noise from being a part of the measurement.
As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when
frequency components are present in the input signal that are higher than half the sampling frequency of the
ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the
actual frequency band of interest below half the sampling frequency. Inside a ΔΣ ADC, the input signal is
sampled at the modulator frequency fMOD and not at the output data rate. 图 75 shows that the filter response of
the digital filter repeats at multiples of the sampling frequency (fMOD). Signals or noise up to a frequency where
the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter
architecture. Any frequency components present in the input signal around the modulator frequency or multiples
thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.
Magnitude
Sensor
Signal
Unwanted Signals
Unwanted Signals
Output
Data Rate
fMOD/2
f(MOD)
f(MOD)
f(MOD)
Frequency
Frequency
Frequency
Magnitude
Digital Filter
Aliasing of Unwanted
Signals
Output
Data Rate
fMOD/2
Magnitude
External
Antialiasing Filter
Roll-Off
Output
fMOD/2
Data Rate
图 75. Effect of Aliasing
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Application Information (接下页)
Many sensor signals are inherently band limited; for example, the output of a thermocouple has a limited rate of
change. In this case the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However,
any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band.
Power-line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to
reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is
attenuated to a level below the noise floor of the ADC. The digital filter of the ADS112U04 attenuates signals to a
certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components
are usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a
cutoff frequency set at the output data rate or 10 times higher is generally a good starting point for a system
design.
Internal to the device, prior to the PGA inputs, is an EMI filter; see 图 46. The cutoff frequency of this filter is
approximately 31.8 MHz, which helps reject high-frequency interferences.
9.1.3 External Reference and Ratiometric Measurements
The full-scale range (FSR) of the ADS112U04 is defined by the reference voltage and the PGA gain (FSR =
±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to
the specific system needs. An external reference must be used if VIN is greater than 2.048 V. For example, an
external 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing
between 0 V and 5 V.
The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric
measurement the same excitation source that is used to excite the sensor is also used to establish the reference
for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite
both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with
the element being measured. The voltage that develops across the reference element is used as the reference
source for the ADC. These components cancel out in the ADC transfer function because current noise and drift
are common to both the sensor measurement and the reference. The output code is only a ratio of the sensor
element and the value of the reference resistor. The value of the excitation current source itself is not part of the
ADC transfer function.
9.1.4 Establishing Proper Limits on the Absolute Input Voltage
The ADS112U04 can be used to measure various types of input signal configurations: single-ended, pseudo-
differential, and fully differential signals (which can be either unipolar or bipolar). However, configuring the device
properly for the respective signal type is important.
Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonly
called single-ended signals. If the PGA is disabled and bypassed, the absolute input voltages of the ADS112U04
can be as low as 100 mV below AVSS and as large as 100 mV above AVDD. Therefore, the PGA_BYPASS bit
must be set in order to measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V).
Gains of 1, 2, and 4 are still possible in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal
across a load resistor of 100 Ω referenced to GND is a typical example. The ADS112U04 can directly measure
the signal across the load resistor using a unipolar supply, the internal 2.048-V reference, and gain = 1 when the
PGA is bypassed.
If gains larger than 4 are needed to measure a single-ended signal, the PGA must be enabled. In this case, a
bipolar supply is required for the ADS112U04 to meet the absolute input voltage requirement of the PGA.
Signals where the negative analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudo-
differential signals.
Fully differential signals in contrast are defined as signals having a constant common-mode voltage where the
positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.
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Application Information (接下页)
The ADS112U04 can measure pseudo-differential and fully differential signals with the PGA enabled or
bypassed. However, the PGA must be enabled in order to use gains greater than 4. The absolute input voltages
of the input signal must meet the absolute input voltage restrictions of the PGA (as explained in the PGA Input
Voltage Requirements section) when the PGA is enabled. Setting the common-mode voltage at or near (AVSS +
AVDD) / 2 in most cases satisfies the PGA absolute input voltage requirements.
Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals
can in general be measured with the ADS112U04 using a unipolar analog supply (AVSS = 0 V). As mentioned
previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar
supply.
A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply
(such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS112U04. A
typical application task is measuring a single-ended, bipolar, ±10-V signal where AINN is fixed at 0 V and AINP
swings between –10 V and 10 V. The ADS112U04 cannot directly measure this signal because the 10 V
exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD
= 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS112U04. The resistor divider must
divide the voltage down to ≤ ±2.048 V in order to measure the voltage using the internal 2.048-V reference.
9.1.5 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or
connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AVSS is possible
as well, but can yield higher leakage currents on other analog inputs than the previously mentioned options.
Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital
inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. Connections for unused
digital inputs are:
•
•
Tie the RESET pin to DVDD if the RESET pin is not used
Leave the GPIO0 or GPIO1 pins configured in the default states as GPIO inputs and tie GPIO0 or GPIO1,
respectively, to either DVDD or DGND if unused
•
Leave the GPIO2/DRDY pin configured in the default state as a GPIO input and tie to either DVDD or DGND
if both the DRDY output and GPIO2 are unused
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Application Information (接下页)
9.1.6 Pseudo Code Example
The following list shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS112U04 in
continuous conversion mode. The dedicated GPIO2/DRDY pin is used to indicate availability of new conversion
data. The default configuration register settings are changed to gain = 16, continuous conversion mode. This
example shows data collection using manual data read mode.
Power-up;
Delay to allow power supplies to settle and power-on reset to complete; minimum of 600 µs;
Configure the UART interface of the microcontroller to 8-N-1 format;
Configure the microcontroller GPIO connected to the GPIO2/DRDY pin as a falling edge triggered
interrupt input;
Send the synchronization word to the device (55h);
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Delay for a minimum of td(RSRX)
;
Write the respective register configurations with the WREG command, sending the synchronization word
each time (55h, 40h, 08h, 55h, 42h, 08h, 55h, 48h, 48h);
As an optional sanity check, send the synchronization word then read back all configuration registers
with the RREG command (55h, 2xh);
Send the synchronization word to the device (55h);
Send the START/SYNC command (08h) to start converting in continuous conversion mode;
Loop
{
Wait for GPIO2/DRDY to transition low;
Send the synchronization word (55h);
Send the RDATA command (10h);
Receive 2 bytes of data from TX;
}
Send the synchronization word (55h);
Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;
TI recommends running an offset calibration before performing any measurements or when changing the gain of
the PGA. The internal offset of the device can, for example, be measured by shorting the inputs to mid-supply
(MUX[3:0] = 1110). The microcontroller then takes multiple readings from the device with the inputs shorted and
stores the average value in the microcontroller memory. When measuring the sensor signal, the microcontroller
then subtracts the stored offset value from each device reading to obtain an offset compensated result; the offset
can be either positive or negative in value.
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9.2 Typical Applications
9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
图 76 shows the basic connections of a thermocouple measurement system when using an external high-
precision temperature sensor for cold-junction compensation. Apart from the thermocouple itself, the only
external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply
decoupling capacitors.
3.3 V
3.3 V
0.1 mF
0.1 mF
3.3 V
REFP
REFN
10 ꢀA to
1.5 mA
AVDD
DVDD
RB2
CCM2
Isothermal Block
RF2
AIN0
AIN1
2.048-V
Reference
Reference
Mux
TI Device
CDIF
RF1
TX
AINP
AINN
RX
Digital Filter
and
UART
Thermocouple
GPIO0
16-Bit
ûꢁ ADC
RB1
CCM1
Mux
PGA
GPIO1
Interface
3.3 V
GPIO2/DRDY
RESET
AIN2
AIN3
VDD
LM94022
Precision
Temperature
Sensor
GS1
OUT
GS0
Low-Drift
Oscillator
GND
AVSS
DGND
Cold-Junction
Compensation
图 76. Thermocouple Measurement
表 24. Design Requirements
9.2.1.1 Design Requirements
DESIGN PARAMETER
Supply voltage
VALUE
3.3 V
Reference voltage
Internal 2.048-V reference
Update rate
≥10 readings per second
Thermocouple type
K
Temperature measurement range
Measurement accuracy at TA = 25°C(1)
–200°C to +1250°C
0.5°C
(1) Not accounting for error of the thermocouple and cold-junction temperature measurement;
offset calibration at T(TC) = T(CJ) = 25°C; no gain calibration.
9.2.1.2 Detailed Design Procedure
The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple such that the
input voltages do not exceed the absolute input voltage range of the PGA (in this example, to mid-supply AVDD /
2). If the application requires the thermocouple to be biased to GND, either a bipolar supply (for example, AVDD
= 2.5 V and AVSS = –2.5 V) must be used for the device to meet the absolute input voltage requirement of the
PGA, or the PGA must be bypassed. When choosing the values of the biasing resistors, care must be taken so
that the biasing current does not degrade measurement accuracy. The biasing current flows through the
thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical
values for the biasing resistors range from 1 MΩ to 50 MΩ.
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In addition to biasing the thermocouple, RB1 and RB2 are also useful for detecting an open thermocouple lead.
When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to
AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal
measurement range of the thermocouple voltage, to indicate this failure condition.
Although the device digital filter attenuates high-frequency components of noise, performance can be further
improved by providing a first-order, passive RC filter at the inputs. 公式 9 calculates the cutoff frequency that is
created by the differential RC filter formed by RF1, RF2, and the differential capacitor CDIF
.
fC = 1 / [2π · (RF1 + RF2) · CDIF
]
(9)
Two common-mode filter capacitors (CM1 and CM2) are also added to offer attenuation of high-frequency,
common-mode noise components. Choose a differential capacitor CDIF that is at least an order of magnitude (10
times) larger than the common-mode capacitors (CM1 and CM2) because mismatches in the common-mode
capacitors can convert common-mode noise into differential noise.
The filter resistors RF1 and RF2 also serve as current-limiting resistors. These resistors limit the current into the
analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occur. Care must be
taken when choosing the filter resistor values because the input currents flowing into and out of the device cause
a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs.
TI therefore recommends limiting the filter resistor values to below 1 kΩ.
The filter component values used in this design are: RF1 = RF2 = 1 kΩ, CDIF = 100 nF, and CCM1 = CCM2 = 10 nF.
The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of
the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple
voltage occurs at T(TC) = 1250°C and is V(TC) = 50.644 mV as defined in the tables published by the National
Institute of Standards and Technology (NIST) using a cold-junction temperature of T(CJ) = 0°C. A thermocouple
produces an output voltage that is proportional to the temperature difference between the thermocouple tip and
the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger
than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device.
Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at T(TC) = 1250°C
produces an output voltage of V(TC) = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction
temperature of T(CJ) = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference
is then calculated as (2.048 V / 52.171 mV) = 39.3. The next smaller PGA gain setting that the device offers is
32.
The device integrates a high-precision temperature sensor that can be used to measure the temperature of the
cold junction. To measure the internal temperature of the ADS112U04, the device must be set to internal
temperature sensor mode by setting the TS bit to 1 in the configuration register. For best performance, careful
board layout is critical to achieve good thermal conductivity between the cold junction and the device package.
However, the device does not perform automatic cold-junction compensation of the thermocouple. This
compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one
or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature
sensor mode (TS = 1) to acquire the temperature of the cold junction. An algorithm similar to the following must
be implemented on the microcontroller to compensate for the cold-junction temperature:
1. Measure the thermocouple voltage, V(TC), between AIN0 and AIN1
2. Measure the temperature of the cold junction, T(CJ), using the temperature sensor mode of the ADS112U04
3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V(CJ), using the tables or
equations provided by NIST
4. Add V(TC) and V(CJ) and translate the summation back into a thermocouple temperature using the NIST tables
or equations again
In some applications, the integrated temperature sensor of the ADS112U04 cannot be used (for example, if the
accuracy is not high enough or if the device cannot be placed close enough to the cold junction). The additional
analog input channels of the device can be used in this case to measure the cold-junction temperature with a
thermistor, RTD, or an analog temperature sensor. 图 76 illustrates the LM94022 temperature sensor being used
for cold-junction compensation.
52
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ADS112U04
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As shown in 公式 10, the rms noise of the ADS112U04 at gain = 32 and DR = 20 SPS (1.95 µVrms) is divided by
the average sensitivity of a K-type thermocouple (41 µV/°C) to obtain an approximation of the achievable
temperature resolution.
Temperature Resolution = 1.95 µV / 41 µV/°C = 0.05°C
(10)
表 25 shows the register settings for this design.
表 25. Register Settings
REGISTER
SETTING
DESCRIPTION
00h
0Ah
AINP = AIN0, AINN = AIN1, gain = 32, PGA enabled(1)
DR = 20 SPS, normal mode, continuous conversion mode, internal
reference
01h
02h
08h
00h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDACs off
03h
04h
00h
48h
No IDACs used, manual data read mode
GPIO2/DRDY pin configured as a DRDY output
(1) To measure the cold junction temperature using the LM90422, change register 00h to B1h (AINP
AIN3, AINN = AVSS, gain = 1, PGA disabled).
=
9.2.1.3 Application Curves
图 77 and 图 78 show the measurement results. The measurements are taken at TA = T(CJ) = 25°C. A system
offset calibration is performed at T(TC) = 25°C, which translates to a V(TC) = 0 V when T(CJ) = 25°C. No gain
calibration is implemented. The data in 图 77 are taken using a precision voltage source as the input signal
instead of a thermocouple. The respective temperature measurement error in 图 78 is calculated from the data in
图 77 using the NIST tables.
The design meets the required temperature measurement accuracy given in 表 24. The measurement error
shown in 图 78 does not include the error of the thermocouple itself nor the measurement error of the cold-
junction temperature. Those two error sources are in general larger than 0.2°C and therefore, in many cases,
dominate the overall system measurement accuracy.
0.01
0.005
0
0.2
0.1
0
-0.005
-0.1
-0.01
-0.2
-10
0
10
20
30
40
50
-200
0
200
400
600
800
1000
1200
Thermocouple Voltage (mV)
Temperature (°C)
D002
D001
图 77. Voltage Measurement Error vs V(TC)
图 78. Temperature Measurement Error vs T(TC)
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9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
The ADS112U04 integrates all necessary features (such as dual-matched programmable current sources,
buffered reference inputs, and a PGA) to ease the implementation of ratiometric 2-, 3-, and 4-wire RTD
measurements. 图 79 shows a typical implementation of a ratiometric 3-wire RTD measurement using the
excitation current sources integrated in the device to excite the RTD as well as to implement automatic RTD
lead-resistance compensation.
RREF
IIDAC1 + IIDAC2
3.3 V
3.3 V
RF3
CDIF2
RF4
0.1 mF
0.1 mF
10 ꢀA to
1.5 mA
RLEAD3
RLEAD2
AVDD
DVDD
REFN
REFP
CCM2
CDIF1
CCM1
RF2
AIN0
AIN1
2.048-V
Reference
Reference
Mux
TI Device
3-Wire RTD
RLEAD1
RF1
TX
AINP
AINN
RX
Digital Filter
and
UART
GPIO0
16-Bit
Mux
PGA
ûꢁ ADC
GPIO1
Interface
AIN2
GPIO2/DRDY
RESET
(IDAC1)
Precision
Temperature
Sensor
AIN3
Low-Drift
Oscillator
(IDAC2)
AVSS
DGND
图 79. 3-Wire RTD Measurement
表 26. Design Requirements
9.2.2.1 Design Requirements
DESIGN PARAMETER
Supply voltage
VALUE
3.3 V
Update rate
20 readings per second
3-wire Pt100
15 Ω
RTD type
Maximum RTD lead resistance
RTD excitation current
Temperature measurement range
Measurement accuracy at TA = 25°C(1)
500 µA
–200°C to +850°C
±0.2°C
(1) Not accounting for error of RTD;
offset calibration is performed with RRTD = 100 Ω; no gain calibration.
9.2.2.2 Detailed Design Procedure
The circuit in 图 79 employs a ratiometric measurement approach. In other words, the sensor signal (that is, the
voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same excitation
source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out because
these errors are common to both the sensor signal and the reference.
54
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In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the
leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is
programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both
IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision,
low-drift reference resistor, RREF. The voltage, VREF, generated across the reference resistor (as shown in 公式
11) is used as the ADC reference voltage. 公式 11 reduces to 公式 12 because IIDAC1 = IIDAC2
.
VREF = (IIDAC1 + IIDAC2) · RREF
VREF = 2 · IIDAC1 · RREF
(11)
(12)
To simplify the following discussion, the individual lead resistance values of the RTD (RLEADx) are set to zero. As
公式 13 shows, only IDAC1 excites the RTD to produce a voltage (VRTD) proportional to the temperature-
dependent RTD value and the IDAC1 value.
VRTD = RRTD (at temperature) · IIDAC1
(13)
The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage
against the reference voltage to produce a digital output code proportional to 公式 14 through 公式 16:
Code ∝ VRTD · Gain / VREF
(14)
(15)
(16)
Code ∝ (RRTD (at temperature) · IIDAC1 · Gain) / (2 · IIDAC1 · RREF
)
Code ∝ (RRTD (at temperature) · Gain) / (2 · RREF
)
As shown in 公式 16, the output code only depends on the value of the RTD, the PGA gain, and the reference
resistor (RREF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the excitation current
therefore does not matter. However, because the value of the reference resistor directly affects the measurement
result, choosing a reference resistor with a very low temperature coefficient is important to limit errors introduced
by the temperature drift of RREF
.
The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of
the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance.
Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, use 公式 17 to calculate
the differential voltage (VIN) across the ADC inputs (AIN0 and AIN1):
VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2
(17)
公式 17 reduces to 公式 18 when RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2
:
VIN = IIDAC1 · RRTD
(18)
In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is
compensated, as long as the lead resistance values and the IDAC values are well matched.
A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC
inputs, as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The same guidelines for designing
the input filter apply as described in the K-Type Thermocouple Measurement section. Match the corner
frequencies of the input and reference filter for best performance. For more detailed information on matching the
input and reference filter, see the RTD Ratiometric Measurements and Filtering Using the ADS1148 and
ADS1248 application report.
The reference resistor RREF not only serves to generate the reference voltage for the device, but also sets the
voltages at the leads of the RTD to within the specified absolute input voltage range of the PGA.
When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs.
The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal to or
less than AVDD – 0.9 V in order to operate accurately. This requirement means that 公式 19 must be met at all
times.
AVSS + IIDAC1 · (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) · (RLEAD3 + RREF) ≤ AVDD – 0.9 V
(19)
The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter
resistor values RF1 and RF2 in 图 79 are small enough and well matched, then IDAC1 can be routed to AIN1 and
IDAC2 to AIN0. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured with
a single device.
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As stated in 表 26, this design example discusses the implementation of a 3-wire Pt100 measurement to be used
to measure temperatures ranging from –200°C to +850°C. The excitation current for the Pt100 is chosen as
IIDAC1 = 500 µA, which means a combined current of 1 mA is flowing through the reference resistor, RREF. As
mentioned previously, besides creating the reference voltage for the ADS112U04, the voltage across RREF also
sets the absolute input voltages for the RTD measurement. In general, choose the largest reference voltage
possible that maintains the compliance voltage of the IDACs and meets the absolute input voltage requirement of
the PGA. Setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V) in
most cases satisfies the absolute input voltage requirements of the PGA. 公式 20 is then used to calculate the
value for RREF
:
RREF = VREF / (IIDAC1 + IIDAC2) = 1.65 V / 1 mA = 1.65 kΩ
(20)
The stability of RREF is critical to achieve good measurement accuracy over temperature and time. Choosing a
reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65-kΩ value is not
readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.
As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the
ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured
(VINMAX) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of
approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to 公式 21:
VINMAX = VRTD (at 850°C) = RRTD (at 850°C) · IIDAC1 = 391 Ω · 500 µA = 195.5 mV
(21)
The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV)
= 8.4. The next smaller PGA gain setting available in the ADS112U04 is 8. At a gain of 8, the ADS112U04 offers
an FSR value as described in 公式 22:
FSR = ±VREF / Gain = ±1.65 V / 8 = ±206.25 mV
(22)
This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.
After selecting the values for the IDACs, RREF, and PGA gain, make sure to double check that the settings meet
the absolute input voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the
true absolute input voltages at the ADC inputs (AIN0 and AIN1), the lead resistance must be taken into account
as well.
The smallest absolute input voltage occurs on AIN0 at the lowest measurement temperature (–200°C) with
RLEADx = 0 Ω, and is equal to VREF = 1.65 V.
The minimum absolute input voltage must not exceed the limit set in 公式 7 to meet 公式 23:
VAIN0 (MIN) ≥ AVSS + 0.2 V + |VINMAX| · (Gain – 4) / 8 = 0 V + 0.2 V + 97.75 mV = 297.75 mV
(23)
The restriction is satisfied with VAIN0 = 1.65 V.
The largest absolute input voltage (calculated using 公式 24 and 公式 25) occurs on AIN1 at the highest
measurement temperature (850°C).
VAIN1 (MAX) = VREF + (IIDAC1 + IIDAC2) · RLEAD3 + IIDAC1 · (RLEAD1 + RRTD (at 850°C)
)
(24)
(25)
VAIN1 (MAX) = 1.65 V + 1 mA · 15 Ω + 500 µA · (15 Ω + 391 Ω) = 1.868 V
VAIN1 (MAX) meets the requirement given by 公式 7 and equates to 公式 26 in this design:
VAINP (MAX) ≤ AVDD – 0.2 V – |VINMAX| · (Gain – 4) / 8 = 3.3 V – 0.2 V – 97.75 mV = 3.002 V
(26)
The restriction on the compliance voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met as well.
表 27 shows the register settings for this design.
表 27. Register Settings
REGISTER
SETTING
DESCRIPTION
00h
36h
AINP = AIN1, AINN = AIN0, gain = 8, PGA enabled
DR = 20 SPS, normal mode, continuous conversion mode, external
reference
01h
02h
0Ah
55h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDAC = 500 µA
03h
04h
70h
48h
IDAC1 = AIN2, IDAC2 = AIN3, manual data read mode
GPIO2/DRDY pin configured as a DRDY output
56
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ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement illustrated in 图
79, except that only one IDAC is required.
图 80 shows a typical circuit implementation of a 2-wire RTD measurement. The main difference compared to a
3-wire RTD measurement is with respect to the lead resistance compensation. The voltage drop across the lead
resistors, RLEAD1 and RLEAD2, in this configuration is directly part of the measurement (as shown in 公式 27)
because there is no means to compensate the lead resistance by use of the second current source. Any
compensation must be done by calibration.
VIN = IIDAC1 · (RLEAD1 + RRTD + RLEAD2
)
(27)
RREF
IIDAC1
3.3 V
3.3 V
RF3
RF4
CDIF2
0.1 mF
0.1 mF
10 ꢀA to
1.5 mA
AVDD
DVDD
REFP
REFN
CCM2
RLEAD2
RF2
AIN0
2.048-V
Reference
Reference
Mux
TI Device
2-Wire RTD
CDIF1
TX
RLEAD1
RF1
AIN1
AIN2
RX
AINP
AINN
Digital Filter
and
UART
CCM1
GPIO0
GPIO1
GPIO2/DRDY
RESET
16-Bit
ûꢁ ADC
Mux
PGA
Interface
Precision
Temperature
Sensor
AIN3
Low-Drift
Oscillator
(IDAC1)
AVSS
DGND
图 80. 2-Wire RTD Measurement
图 81 shows a typical circuit implementation of a 4-wire RTD measurement. Similar to the 2-wire RTD
measurement, only one IDAC is required for exciting and measuring a 4-wire RTD in a ratiometric manner. The
main benefit of using a 4-wire RTD is that the ADC inputs are connected to the RTD in the form of a Kelvin
connection. Apart from the input leakage currents of the ADC, there is no current flow through the lead resistors
RLEAD2 and RLEAD3 and therefore no voltage drop is created across them. The voltage at the ADC inputs
consequently equals the voltage across the RTD and the lead resistance is of no concern.
RREF
IIDAC1
3.3 V
3.3 V
RF3
CDIF2
RF4
0.1 mF
0.1 mF
10 ꢀA to
1.5 mA
RLEAD4
RLEAD3
AVDD
DVDD
REFP
REFN
CCM2
CDIF1
CCM1
RF2
AIN0
AIN1
2.048-V
Reference
Reference
Mux
TI Device
4-Wire RTD
RLEAD2
RF1
TX
AINP
AINN
RX
Digital Filter
and
UART
GPIO0
16-Bit
ûꢁ ADC
Mux
PGA
RLEAD1
GPIO1
Interface
GPIO2/DRDY
RESET
AIN2
Precision
Temperature
Sensor
AIN3
Low-Drift
Oscillator
(IDAC1)
AVSS
DGND
图 81. 4-Wire RTD Measurement
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As shown in 公式 28, the transfer function of a 2- and 4-wire RTD measurement differs compared to the one of a
3-wire RTD measurement by a factor of 2 because only one IDAC is used and only one IDAC flows through the
reference resistor, RREF
.
Code ∝ (RRTD (at Temperature) · Gain) / RREF
(28)
In addition, the input common-mode voltage and reference voltage is reduced compared to the 3-wire RTD
configuration. Therefore, some further modifications may be required in case the 3-wire RTD design is used to
measure 2- and 4-wire RTDs as well. If the decreased absolute input voltages does not meet the minimum
absolute voltage requirements of the PGA anymore, either increase the value of RREF by switching in a larger
resistor or, alternatively, increase the excitation current and decrease the gain at the same time.
9.2.2.3 Application Curves
图 82 and 图 83 show the measurement results. The measurements are taken at TA = 25°C. A system offset
calibration is performed using a reference resistor of 100 Ω. No gain calibration is implemented. The data in 图
82 are taken using precision resistors instead of a 3-wire Pt100. The respective temperature measurement error
in 图 83 is calculated from the data in 图 82 using the NIST tables.
The design meets the required temperature measurement accuracy given in 表 26. However, the measurement
error shown in 图 83 does not include the error of the RTD itself.
0.1
0.05
0
0.2
0.1
0
-0.05
-0.1
-0.1
-0.2
0
50
100
150
200
250
300
350
400
-200
0
200
400
600
800
1000
RTD Value (W)
Temperature (°C)
D003
D004
图 82. Resistance Measurement Error vs RRTD
图 83. Temperature Measurement Error vs T(RTD)
58
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ADS112U04
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ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
9.2.3 Resistive Bridge Measurement
The device offers several features to ease the implementation of ratiometric bridge measurements (such as a
PGA with gains up to 128, buffered, and differential reference inputs).
5.0 V
5.0 V
3.3 V
CDIF2
0.1 mF
0.1 mF
REFP(1)
REFN(1)
10 ꢀA to
1.5 mA
AVDD
DVDD
2.048-V
Reference
Reference
Mux
AIN0
AIN1
TI Device
5.0 V
CCM2
CDIF1
CCM1
TX
RF2
RX
AINP
AINN
Digital Filter
and
UART
GPIO0
GPIO1
GPIO2/DRDY
RESET
16-Bit
ûꢁ ADC
Mux
PGA
RF1
Interface
AIN2
AIN3
Precision
Temperature
Sensor
Low-Drift
Oscillator
AVSS
DGND
(1) Connect reference inputs directly to the bridge excitation voltage through Kelvin connections.
图 84. Resistive Bridge Measurement
9.2.3.1 Design Requirements
表 28. Design Requirements
DESIGN PARAMETER
Analog supply voltage
Digital supply voltage
Load cell type
VALUE
5.0 V
3.3 V
4-wire load cell
1 kg
Load cell maximum capacity
Load cell sensitivity
Excitation voltage
3 mV/V
5 V
Noise-free counts
8000
9.2.3.2 Detailed Design Procedure
As shown in 图 84, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC to
implement a ratiometric bridge measurement. With this configuration, any drift in excitation voltage also shows up
on the reference voltage, consequently canceling out drift error. Either the dedicated reference inputs can be
used, or the analog supply can be used as the reference if the supply is used to excite the bridge.
The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal
use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply
voltage of the device ensures that the output signal of the bridge meets the absolute input voltage requirement of
the PGA.
Using a 3-mV/V load cell with a 5-V excitation yields a maximum differential voltage at the ADC inputs of VINMAX
= 15 mV at maximum load. 公式 29 then calculates the maximum gain that can be used.
Gain ≤ VREF / VINMAX = 5 V / 15 mV = 333.3
(29)
Accordingly Gain = 128 is used in this example.
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A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC
inputs. The reference has an additional capacitor CDIF2 to limit reference noise. Care must be taken to maintain a
limited amount of filtering or the measurement is no longer ratiometric.
The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference
voltage. Accordingly, the device is able to resolve signals as small as one LSB. Use 公式 30 to calculate the LSB
size:
1 LSB = (2 · VREF / Gain) / 216 = (2 · 5.0 V / 128) / 216 = 1.192 µV
(30)
To find the total number of counts available for the bridge measurement, the maximum output voltage is divided
by the LSB value. Dividing 10 mV by 1.192 µV equates to 8389 total counts available, which meets the design
parameter of 8000 counts.
表 29 shows the register settings for this design.
表 29. Register Settings
REGISTER
SETTING
DESCRIPTION
00h
4Eh
AINP = AIN1, AINN = AIN2, gain = 128, PGA enabled
DR = 20 SPS, normal mode, continuous conversion mode, external
reference
01h
02h
0Ah
98h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDACs off
03h
04h
00h
48h
No IDACs used, manual data read mode
GPIO2/DRDY pin configured as a DRDY output
60
版权 © 2018, Texas Instruments Incorporated
ADS112U04
www.ti.com.cn
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
10 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power
supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V,
AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels.
10.1 Power-Supply Sequencing
The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the
respective analog or digital power-supply voltage and current limits. Wait approximately 600 µs after all power
supplies are stabilized before communicating with the device to allow the power-on reset process to complete.
10.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. As shown in 图 85 and 图 86,
AVDD, AVSS (when using a bipolar supply), and DVDD must be decoupled with at least a 0.1-µF capacitor.
Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance
connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series
resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive
systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to
the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall
inductance and is beneficial for connections to ground planes. Connect analog and digital grounds together as
close to the device as possible.
1
2
3
4
5
6
7
8
GPIO1
GPIO0
RESET
DGND
AVSS
AIN3
RX 16
TX 15
1
2
3
4
5
6
7
8
GPIO1
GPIO0
RESET
DGND
AVSS
AIN3
RX 16
TX 15
3.3 V
3.3 V
GPIO2/DRDY 14
DVDD 13
GPIO2/ DRDY 14
DVDD 13
Device
Device
AVDD 12
3.3 V
-2.5 V
AVDD 12
2.5 V
0.1 mF
0.1 µF
AIN0 11
AIN0 11
0.1 mF
0.1 µF
0.1 µF
AIN2
AIN1 10
AIN2
AIN1 10
REFN
REFP
9
REFN
REFP
9
图 85. Unipolar Analog Power Supply
图 86. Bipolar Analog Power Supply
版权 © 2018, Texas Instruments Incorporated
61
ADS112U04
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout separates analog components
[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital
components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate
arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching
regulators]. 图 87 shows an example of good component placement. Although 图 87 provides a good example of
component placement, the best placement for each application is unique to the geometries, components, and
PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and
careful consideration must always be used when designing with any analog component.
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Supply
Generation
Signal
Conditioning
(RC Filters
and
Interface
Transceiver
Device
Microcontroller
Connector
or Antenna
Amplifiers)
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
图 87. System Component Placement
The following basic recommendations for layout of the ADS112U04 help achieve the best possible performance
of the ADC. A good design can be ruined with a bad circuit layout.
•
Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Routing digital lines away from analog lines prevents digital noise from coupling back into
analog signals.
•
The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.
Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the
layout, the split between the analog and digital grounds must be connected to together at the ADC.
•
•
Fill void areas on signal layers with ground fill.
Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, another path
must be found to return to the source and complete the circuit. If forced into a larger path, the chance that the
signal radiates increases. Sensitive signals are more susceptible to EMI interference.
•
•
Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source
signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI
pickup and reduces the high-frequency impedance at the input of the device.
•
•
Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor
can create a parasitic thermocouple that can add an offset to the measurement. Differential inputs must be
matched for both the inputs going to the measurement source.
Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and
AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO) that have stable properties and low noise characteristics.
62
版权 © 2018, Texas Instruments Incorporated
ADS112U04
www.ti.com.cn
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
11.2 Layout Example
Vias connect to either the bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
(GND = DGND = AVSS).
AIN1
AIN2
AIN3
AIN0
9: REFP
8: REFN
10: AIN1
11: AIN0
7: AIN2
6: AIN3
12: AVDD
13: DVDD
14: GPIO2/DRDY
15: TX
5: AVSS
4: DGND
3: RESET
AVDD
DVDD
2: GPIO0
1: GPIO1
16: RX
图 88. Layout Example
版权 © 2018, Texas Instruments Incorporated
63
ADS112U04
ZHCSHD5A –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表
德州仪器 (TI)，《使用 ADS1148 和 ADS1248 进行 RTD 比例测量和滤波》 应用报告
德州仪器 (TI)，《使用 ADS122U04 减小隔离式数据采集系统的系统成本、大小和功耗》 技术手册
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
64
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS112U04IPW
ADS112U04IPWR
ADS112U04IRTER
ADS112U04IRTET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
WQFN
WQFN
PW
PW
16
16
16
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS112U
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ADS112U
112U
RTE
RTE
250
RoHS & Green
112U
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS112U04IPWR
ADS112U04IRTER
ADS112U04IRTET
TSSOP
WQFN
WQFN
PW
RTE
RTE
16
16
16
2000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
6.9
3.3
3.3
5.6
3.3
3.3
1.6
1.0
1.0
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS112U04IPWR
ADS112U04IRTER
ADS112U04IRTET
TSSOP
WQFN
WQFN
PW
RTE
RTE
16
16
16
2000
3000
250
367.0
367.0
213.0
367.0
367.0
191.0
35.0
38.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS112U04IPW
16
90
530
10.2
3600
3.5
Pack Materials-Page 3
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
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SI9137DB
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