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ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

具有 PGA 和电压基准的 ADS114S0xB 低功耗、低噪声、高集成度、

6 通道和 12 通道、4kSPS、16 位 Δ-Σ ADC

1 特性

3 说明

1

•

低功耗：低至 280µA

ADS114S06B 和 ADS114S08B 均为高精度 16 位 Δ-Σ

模数转换器 (ADC)，兼具低功耗特性与多种集成特

性，能够降低系统成本并减少小型传感器信号测量应

用中的组件数。

•

可编程增益：1 至 128

可编程数据速率：2.5SPS 至 4kSPS

借助低延迟数字滤波器，在 ≤ 20SPS 时实现 50Hz

和 60Hz 同步抑制

这些 ADC 均配有数字滤波器，能够在嘈杂的工业环境

中提供低延迟转换结果和 50Hz 或 60Hz 噪声抑制。可

编程增益放大器 (PGA) 具备低噪声特性，并且可提供

1 到 128 的增益，能够为电阻桥或热电偶应用放大低

幅值信号。此外，这两款器件还集成有一个低漂移

2.5V 电压基准，减小了印刷电路板 (PCB) 面积。最后

还有两个可编程的激励电流源 (IDAC)，便于提供准确

的电阻式温度检测器 (RTD) 偏置。

•

具有 12 路 (ADS114S08B) 或 6 路 (ADS114S06B)

独立可选输入的模拟多路复用器

•

双匹配可编程传感器激励电流源：10µA 至 2000µA

内部基准：2.5V，8ppm/°C（典型值）温漂

内部振荡器：4.096MHz，精度为 2%

内部温度传感器

自偏移校准和系统校准

四个通用 I/O

输入多路复用器支持适用于 ADS114S08B 的 12 路输

入和适用于 ADS114S06B 的 6 路输入。这些输入能够

以任意组合形式连接到 ADC，从而提高设计灵活性。

此外，这两款器件还具有传感器烧毁检测、热电偶电

压偏置、系统监控等功能和四个通用 I/O (GPIO)。

与 SPI 兼容的接口

模拟电源：单极（2.7V 至 5.25V）或双极 (±2.5V)

数字电源：2.7V 至 3.6V

工作温度：–40°C 至 +125°C

与 ADS114S0x 引脚兼容

这类器件采用无引线 VQFN-32 或 TQFP-32 封装。

2 应用

•

现场发送器：

器件信息

温度、压力、应变、流量

PLC 和 DCS 模拟输入模块

温度控制器

订货编号

封装（引脚）

TQFP (32)

VQFN (32)

封装尺寸

•

5.0mm × 5.0mm

ADS114S0xB

人工气候室，工业烘箱

功能方框图

AVDD

Burnout

Detect

2.5-V

Reference

ADS114S06B

Reference

Mux

Excitation

Current

Sources

ADS114S08B

AINCOM

AIN0

Reference

Detection

AIN1

Reference

Buffers

AIN2

VBIAS

START/SYNC

RESET

CS

AIN3

AIN4

Configurable

Digital

Filter

Serial

Interface

and

16-Bit ûꢀ

ADC

Input

Mux

PGA

AIN5

SCLK

AIN6 / REFP1

AIN7 / REFN1

AIN8 / GPIO0

AIN9 / GPIO1

Control

DIN

DOUT/DRDY

DRDY

System-, Self-

Calibration

Power Supplies

AIN10 / GPIO2

AIN11 / GPIO3

Temperature

Sensor

4.096-MHz

Oscillator

CLK

ADS114S08B

Only

Burnout

Detect

AVSS

DGND

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS852

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

9.6 Register Map........................................................... 54

10 Application and Implementation........................ 68

10.1 Application Information.......................................... 68

10.2 Typical Application ................................................ 73

10.3 What To Do and What Not To Do......................... 78

11 Power Supply Recommendations ..................... 80

11.1 Power Supplies ..................................................... 80

11.2 Power-Supply Sequencing.................................... 80

11.3 Power-On Reset.................................................... 80

11.4 Power-Supply Decoupling..................................... 80

12 Layout................................................................... 81

12.1 Layout Guidelines ................................................. 81

12.2 Layout Example .................................................... 82

13 器件和文档支持 ..................................................... 83

13.1 器件支持................................................................ 83

13.2 文档支持................................................................ 83

13.3 相关链接................................................................ 83

13.4 接收文档更新通知 ................................................. 83

13.5 社区资源................................................................ 83

13.6 商标....................................................................... 83

13.7 静电放电警告......................................................... 83

13.8 Glossary................................................................ 83

14 机械、封装和可订购信息....................................... 84

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ..................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Timing Requirements.............................................. 10

7.7 Switching Characteristics........................................ 10

7.8 Typical Characteristics............................................ 13

Parameter Measurement Information ................ 19

8.1 Noise Performance ................................................. 19

Detailed Description ............................................ 21

9.1 Overview ................................................................. 21

9.2 Functional Block Diagram ....................................... 22

9.3 Feature Description................................................. 23

9.4 Device Functional Modes........................................ 42

9.5 Programming........................................................... 46

8

9

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (August 2017) to Revision A

Page

•

已添加向功能方框图图像添加了基准探测块 ......................................................................................................................... 1

Added External Reference Monitor section in Electrical Characteristics table....................................................................... 8

Added Reference monitor circuit row to I_AVDDparameter in Additional Analog Supply Currents Per Function (AVDD =

3.3 V) section.......................................................................................................................................................................... 9

•

已添加 with low reference voltage level detection to Two sets of buffered external reference inputs bullet in

Overview section .................................................................................................................................................................. 21

•

已添加 discussion on how external reference inputs can be monitored in Overview section ............................................. 21

已添加 reference detection block to Functional Block Diagram image ................................................................................ 22

已删除 last sentence from Burn-Out Current Sources section............................................................................................. 38

已更改 Status Register section............................................................................................................................................. 39

已添加 External Reference Monitor section.......................................................................................................................... 39

已删除 sentence discussing global chop from Offset Calibration section ........................................................................... 41

已更改 description for filter reset for clarification.................................................................................................................. 53

已更改 bit 0 from 0 to FL_REF in register 01h and changed bit 6 from 0 to FL_REF_EN in register 05h in

Configuration Register Map table......................................................................................................................................... 54

•

已更改 bit 0 from 0 to FL_REF and added FL_REF to field descriptions table in Device Status Register.......................... 56

已更改 bit 6 from 0 to FL_REF_EN and added FL_REF_EN to field descriptions table in Reference Control Register..... 60

已更改 bit setting description for bits 4 and 5 in Reference Control Register for clarification.............................................. 60

2

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

5 Device Comparison Table

PRODUCT

ADS114S08B

ADS114S06B

RESOLUTION (Bits)

NUMBER OF INPUTS

12 analog inputs

6 analog inputs

16

6 Pin Configuration and Functions

RHB Package

32-Pin VQFN

Top View

PBS Package

32-Pin TQFP

Top View

AINCOM

AIN5

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

REFCOM

AINCOM

AIN5

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

REFCOM

REFOUT

AIN4

GPIO0/AIN8

GPIO1/AIN9

GPIO2/AIN10

GPIO3/AIN11

RESET

AIN4

GPIO0/AIN8

GPIO1/AIN9

GPIO2/AIN10

GPIO3/AIN11

RESET

AIN3

Thermal Pad

AIN2

AIN1

AIN0

START/SYNC

CLK

START/SYNC

CLK

Not to scale

NOTE: The analog input functions (AIN6–AIN11) are not available on pins 19 to 22, 31, and 32 for the ADS114S06B.

3

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

Pin Functions

NO.

NAME

AINCOM

AIN5

FUNCTION

Analog input

Digital input

Digital output

Digital ground

DESCRIPTION⁽¹⁾

1

2

3

4

5

6

7

8

9

Common analog input for single-ended measurements

Analog input 5

AIN4

Analog input 4

AIN3

Analog input 3

AIN2

Analog input 2

AIN1

Analog input 1

AIN0

Analog input 0

START/SYNC

CS

Start conversion

Chip select; active low

Serial data input

10

11

12

13

14

DIN

SCLK

Serial clock input

DOUT/DRDY

DRDY

DGND

Serial data output combined with data ready; active low

Data ready; active low

Digital ground

Digital I/O power supply. In case IOVDD is not tied to DVDD, connect a 100-nF (or larger) capacitor to

DGND.

15

IOVDD

Digital supply

16

17

18

19

20

21

22

DVDD

CLK

Digital supply

Digital input

Digital core power supply. Connect a 100-nF (or larger) capacitor to DGND.

External clock input. Connect to DGND to use the internal oscillator.

Reset; active low

General-purpose I/O⁽²⁾; analog input 11 (ADS114S08B only)

General-purpose I/O⁽²⁾; analog input 10 (ADS114S08B only)

General-purpose I/O⁽²⁾; analog input 9 (ADS114S08B only)

General-purpose I/O⁽²⁾; analog input 8 (ADS114S08B only)

RESET

Digital input

GPIO3/AIN11

GPIO2/AIN10

GPIO1/AIN9

GPIO0/AIN8

Analog input/output

Positive voltage reference output. Connect a 1-µF to 47-µF capacitor to REFCOM if the internal

voltage reference is enabled.

23

REFOUT

Analog output

24

25

26

27

28

29

30

31

32

Pad

REFCOM

NC

Analog output

—

Negative voltage reference output. Connect to AVSS.

Leave unconnected or connect to AVSS

AVDD

Analog supply

Analog input

—

Positive analog power supply. Connect a 330-nF (or larger) capacitor to AVSS.

Negative analog power supply

AVSS

Negative analog power supply

REFN0

Negative external reference input 0

REFP0

Positive external reference input 0

REFN1/AIN7

REFP1/AIN6

Thermal Pad

Negative external reference input 1; analog input 7 (ADS114S08B only)

Positive external reference input 1; analog input 6 (ADS114S08B only)

RHB package only. Thermal power pad. Connect to AVSS.

(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.

(2) General-purpose inputs and outputs use logic levels based on the analog supply.

4

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

5.5

UNIT

AVDD to AVSS

AVSS to DGND

Power-supply voltage

–2.8

0.3

V

DVDD to DGND

–0.3

3.9

IOVDD to DGND

–0.3

5.5

Analog input voltage

Digital input voltage

AINx, GPIOx, REFPx, REFNx, REFCOM

AVSS – 0.3

AVDD + 0.3

V

CS, SCLK, DIN, DOUT/DRDY, DRDY,

START, RESET, CLK

DGND – 0.3

IOVDD + 0.3

Continuous, REFN0, REFOUT

Continuous, all other pins except power-supply pins

Junction, T_J

–100

–10

100

10

Input current

Temperature

mA

°C

150

Storage, T_stg

–60

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVDD to AVSS

2.7

–2.625

1.5

5.25

0.05

5.25

3.6

Analog power supply

AVSS to DGND

AVDD to DGND

DVDD to DGND

IOVDD to DGND

0

V

Digital core power supply

Digital IO power supply

2.7

V

DVDD

5.25

ANALOG INPUTS⁽¹⁾

PGA bypassed

AVSS – 0.05

AVDD + 0.05

AVSS + 0.15 +

|V_INMAX|·(Gain – 1) / 2

AVDD – 0.15 –

|V_INMAX|·(Gain –1) / 2

PGA enabled, gain = 1 to 16

V_(AINx)

Absolute input voltage⁽²⁾

Differential input voltage

V

AVSS + 0.15 +

AVDD – 0.15 –

15.5·|V_INMAX|

PGA enabled, gain = 32 to 128

V_IN= V_AINP– V_AINN

15.5·|V_INMAX

|

V_IN

–V_REF/ Gain

V_REF/ Gain

V

VOLTAGE REFERENCE INPUTS⁽³⁾

Differential reference input

voltage

V_REF

V_REF= V_(REFPx)– V_(REFNx)

0.5

AVDD – AVSS

Negative reference buffer disabled

Negative reference buffer enabled

Positive reference buffer disabled

Positive reference buffer enabled

AVSS – 0.05

AVSS

V_(REFPx)– 0.5

AVDD + 0.05

AVDD

V

Absolute negative reference

V_(REFNx)

voltage

V_(REFNx)+ 0.5

Absolute positive reference

V_(REFPx)

voltage

EXTERNAL CLOCK SOURCE⁽⁴⁾

f_CLK

External clock frequency

Duty cycle

2

4.096

50%

4.5

MHz

40%

60%

GENERAL-PURPOSE INPUTS (GPIOs)

Input voltage

AVSS – 0.05

DGND

AVDD + 0.05

IOVDD

V

DIGITAL INPUTS (Other than GPIOs)

Input voltage

TEMPERATURE RANGE

T_A

Operating ambient temperature

–40

125

°C

(1) AIN_Pand AIN_Ndenote the positive and negative inputs of the PGA. Any of the available analog inputs (AINx) can be selected as either

AIN_Por AIN_Nby the input multiplexer.

(2) V_INMAXdenotes the maximum differential input voltage, V_IN, that is expected in the application. |V_INMAX| can be smaller than V_REF/ Gain.

(3) REFPx and REFNx denote one of the two available external differential reference input pairs.

(4) An external clock is not required when the internal oscillator is used.

7.4 Thermal Information

ADS114S06B, ADS114S08B

THERMAL METRIC

VQFN (RHB)

32 PINS

45.2

TQFP (PBS)

32 PINS

75.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

28.3

17.1

15.8

28.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

15.7

28.3

R_θJC(bot)

2.3

n/a

6

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

7.5 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C;

all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal

oscillator, and all data rates (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

PGA bypassed,

AVSS + 0.1 V ≤ V_(AINx)≤ AVDD – 0.1 V

±0.5

±0.1

±1

Absolute input current

Differential input current

nA

PGA enabled, gain 1 to 128,

–10

10

V_(AINx)MIN≤ V_(AINx)≤ V_(AINx)MAX

PGA bypassed,

V_CM= AVDD / 2, –V_REF≤ V_IN≤ V_REF

nA/V

nA

PGA enabled, gain 1 to 128,

V_CM= AVDD / 2, –V_REF/ Gain ≤ V_IN≤ V_REF/ Gain

±0.02

PGA

1, 2, 4, 8, 16,

32, 64, 128

Gain settings

Startup time

Enabling the PGA in conversion mode

190

µs

SYSTEM PERFORMANCE

Resolution (no missing codes)

16

Bits

SPS

2.5, 5, 10, 16.6,

20, 50, 60, 100,

200, 400, 800,

DR

INL

Data rate

1000, 2000, 4000

PGA bypassed, V_CM= AVDD / 2

PGA enabled, gain = 1 to 128, V_CM= AVDD / 2

PGA bypassed

1

Integral nonlinearity (best fit)

Input offset voltage

ppm_FSR

2

25

20

20 / Gain

2

PGA enabled, gain = 1 to 8

PGA enabled, gain = 16 to 128

V_IO

µV

On the order of noise_PPat the

set DR and gain

PGA bypassed, after internal offset calibration

PGA enabled, gain = 1 to 128, after internal offset

calibration

On the order of noise_PPat the

set DR and gain

PGA bypassed

10

Offset drift

nV/°C

PGA enabled, gain = 1 to 128

T_A= 25°C, PGA bypassed

T_A= 25°C, PGA enabled, gain = 1 to 128

PGA bypassed

15

0.01%

0.1%

0.2%

Gain error⁽¹⁾

0.025%

0.5

Gain drift⁽¹⁾

ppm/°C

PGA enabled, gain = 1 to 128

1

Noise (input-referred)

See the Noise Performance section

f_IN= 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS

75

95

NMRR Normal-mode rejection ratio⁽²⁾

dB

f_IN= 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,

external f_CLK= 4.096 MHz

At dc

120

125

CMRR Common-mode rejection ratio

f_CM= 50 Hz or 60 Hz (±1 Hz),

DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS

AVDD at dc

105

115

PSRR Power-supply rejection ratio

AVDD at 50 Hz or 60 Hz

DVDD at dc

dB

(1) Excluding error of voltage reference.

(2) See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.

7

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C;

all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal

oscillator, and all data rates (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE REFERENCE INPUTS

Reference buffers disabled, external V_REF= 2.5 V,

REFP1/REFN1 inputs

4

5

µA/V

nA

Absolute input current

Reference buffers enabled, external V_REF= 2.5 V,

REFP1/REFN1 inputs

INTERNAL VOLTAGE REFERENCE

V_REF

Output voltage

Accuracy

2.5

±0.01%

8

V

T_A= 25°C

–0.2%

0.2%

Temperature drift

40 ppm/°C

AVDD = 2.7 V to 3.3 V, sink and source

AVDD = 3.3 V to 5.25 V, sink and source

Sink and source

–5

5

Output current

mA

10

–10

Short-circuit current limit

70

85

100

mA

dB

PSRR Power-supply rejection ratio

AVDD at dc

AVDD = 2.7 V to 3.3 V,

load current = –5 mA to 5 mA

8

Load regulation

µV/mA

AVDD = 3.3 V to 5.25 V,

load current = –10 mA to 10 mA

8

Startup time

Capacitive load stability

Reference noise

1-µF capacitor on REFOUT, 0.001% settling

Capacitor on REFOUT

5.9

ms

µF

1

47

f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT

9

µV_PP

INTERNAL OSCILLATOR

f_CLK

Frequency

Accuracy

4.096

MHz

–2%

2%

EXCITATION CURRENT SOURCES (IDACS)

10, 50, 100,

250, 500, 750,

1000, 1500, 2000

Current settings

µA

V

10 µA to 750 µA, 0.1% deviation

AVSS

–6%

AVDD – 0.4

AVDD – 0.6

6%

Compliance voltage⁽³⁾

Accuracy (each IDAC)

1 mA to 2 mA, 0.1% deviation

T_A= 25°C, 10 µA to 2 mA

±1%

0.2%

100

10

Current mismatch between

IDACs

T_A= 25°C, 10 µA to 2 mA

Temperature drift (each IDAC) 10 µA to 2 mA

ppm/°C

Temperature drift matching

10 µA to 2 mA

between IDACs

With internal reference already settled. From end of

WREG command to current flowing out of pin.

Startup time

BIAS VOLTAGE

22

µs

V_BIAS

Output voltage

(AVDD + AVSS) / 2

350

V

Output impedance

Ω

Combined capacitive load on all selected analog

inputs C_LOAD= 1 µF, 0.1% settling

Startup time

2.8

ms

µA

BURNOUT CURRENT SOURCES (BOCS)

Current settings

0.2, 1, 10

±8%

0.2 µA, sinking or sourcing

1 µA, sinking or sourcing

10 µA, sinking or sourcing

Accuracy

±4%

±2%

EXTERNAL REFERENCE MONITOR

Threshold

0.3

V

(3) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage.

8

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www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C;

all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal

oscillator, and all data rates (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE MONITORS

(AVDD – AVSS) / 4 monitor

±1%

Accuracy

DVDD / 4 monitor

TEMPERATURE SENSOR

Output voltage

T_A= 25°C

129

403

mV

Temperature coefficient

µV/°C

GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)

V_IL

Logic input level, low

Logic input level, high

Logic output level, low

Logic output level, high

AVSS – 0.05

0.7 AVDD

AVSS

0.3 AVDD

AVDD + 0.05

0.2 AVDD

AVDD

V

V_IH

V_OL

V_OH

I_OL= 1 mA

I_OH= 1 mA

0.8 AVDD

DIGITAL INPUT/OUTPUTS

V_IL

Logic input level, low

Logic input level, high

Logic output level, low

Logic output level, high

Input current

DGND

0.7 IOVDD

DGND

0.3 IOVDD

IOVDD

0.2 IOVDD

IOVDD

1

V

V_IH

V_OL

V_OH

I_OL= 1 mA

V

I_OH= 1 mA

0.8 IOVDD

–1

V

DGND ≤ V_{Digital Input}≤ IOVDD

µA

ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS

Disabled, Internal Oscillator, All Data Rates, V_IN= 0 V)

Power-down mode

0.1

70

Standby mode, PGA bypassed

Conversion mode, PGA bypassed

85

Conversion mode, PGA enabled, gain = 1, 2

Conversion mode, PGA enabled, gain = 4, 8

Conversion mode, PGA enabled, gain = 16, 32

Conversion mode, PGA enabled, gain = 64

Conversion mode, PGA enabled, gain = 128

120

140

165

200

250

I_AVDD

Analog supply current

µA

ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)

Internal 2.5-V reference, no external load

Positive reference buffer

185

35

25

10

20

30

40

50

65

10

Negative reference buffer

VBIAS buffer, no external load

IDAC overhead, 10 µA to 250 µA

I_AVDD

Analog supply current

µA

IDAC overhead, 500 µA to 750 µA

IDAC overhead, 1 mA

IDAC overhead, 1.5 mA

IDAC overhead, 2 mA

Reference monitor circuit

DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active)

Power-down mode, internal oscillator

0.1

185

225

195

Standby mode, internal oscillator

I_DVDD

I_IOVDD

+

Digital supply current

µA

Conversion mode, internal oscillator

Conversion mode, external f_CLK= 4.096 MHz

POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled,

Internal Oscillator, All Data Rates, V_IN= 0 V, SPI Not Active)

P_D

Power dissipation

Conversion mode, PGA enabled, gain = 1

1.75

mW

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7.6 Timing Requirements

over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and

DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)

MIN

MAX

UNIT⁽¹⁾

SERIAL INTERFACE

t_d(CSSC)

t_d(SCCS)

t_w(CSH)

t_c(SC)

Delay time, first SCLK rising edge after CS falling edge

Delay time, CS rising edge after final SCLK falling edge

Pulse duration, CS high

20

30

100

40

15

20

0

ns

SCLK period

t_w(SCH)

t_w(SCL)

t_su(DI)

Pulse duration, SCLK high

Pulse duration, SCLK low

Setup time, DIN valid before SCLK falling edge

Hold time, DIN valid after SCLK falling edge

Delay time, between bytes or commands

t_h(DI)

t_d(CMD)

RESET PIN

t_w(RSL)

Pulse duration, RESET low

4

t_CLK

Delay time, first SCLK rising edge after RESET rising edge (or 7th SCLK

falling edge of RESET command)

t_d(RSSC)

4096

START/SYNC PIN

t_w(STH)Pulse duration, START/SYNC high

t_w(STL)

4

t_CLK

Pulse duration, START/SYNC low

Setup time, START/SYNC falling edge (or 7th SCLK falling edge of STOP

command) before DRDY falling edge to stop further conversions

(continuous conversion mode)

t_su(STDR)

32

t_CLK

(1) t_CLK= 1 / f_CLK

.

7.7 Switching Characteristics

over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and

DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT⁽¹⁾

Propagation delay time, CS falling edge to DOUT

driven

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

0

25

ns

Propagation delay time, SCLK rising edge to valid

new DOUT

3

0

30

25

ns

Propagation delay time, CS rising edge to DOUT high

impedance

Propagation delay time, START/SYNC rising edge (or

first SCLK rising edge of any command or data read)

to DRDY rising edge

t_p(STDR)

2

t_CLK

t_w(DRH)

t_p(GPIO)

Pulse duration, DRDY high

24

3

t_CLK

ns

Propagation delay time, last SCLK falling edge of

WREG command to GPIOx output valid

100

SPI timeout per 8 bits⁽²⁾

2¹⁵

t_CLK

(1) t_CLK= 1 / f_CLK

(2) The SPI interface resets when an entire byte is not sent within the specified timeout time.

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t_w(CSH)

CS

SCLK

DIN

tt_d(CSSC)

t

tt_c(SC)

t

t_w(SCH)

tt_d(SCCS)t

t_su(DI)

t_h(DI)

t_w(SCL)

NOTE: Single-byte communication is shown. Actual communication can be multiple bytes.

图 1. Serial Interface Timing Requirements

CS

SCLK

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

Hi-Z

DOUT/DRDY

NOTE: Single-byte communication is shown. Actual communication can be multiple bytes.

图 2. Serial Interface Switching Characteristics

t_w(RSL)

RESET

SCLK

DIN

t_d(RSSC)

RESET command

New command

图 3. RESET Pin and RESET Command Timing Requirements

t_w(STL)

START/SYNC

DRDY

t_w(STH)

t_p(STDR)

t_w(DRH)

t_p(STDR)

t_su(STDR)

图 4. START/SYNC Pin Timing Requirements

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SCLK

DIN

START command

STOP command

t_p(STDR)

DRDY

t_su(STDR)

图 5. START Command Timing Requirements

SCLK

DIN

WREG

01h

GPIO0 set as output

GPIO0 set high

GPIO0 enabled

Write two registers

WREG GPIODAT

GPIO0

t_p(GPIO)

图 6. GPIO Switching Characteristics

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7.8 Typical Characteristics

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

2000

1000

0

2000

1000

0

-40èC

25èC

85èC

125èC

-40èC

25èC

85èC

125èC

-1000

-2000

-3000

-4000

-1000

-2000

-3000

-4000

0

0.5

1

1.5 2

V_(AINx)(V)

2.5

3

3.5

0

0.5

1

1.5 2

V_(AINx)(V)

2.5

3

3.5

PGA bypassed, DR = 20 SPS, V_IN= 0 V

PGA bypassed, DR = 4 kSPS, V_IN= 0 V

图 7. Absolute Input Current vs Absolute Input Voltage

图 8. Absolute Input Current vs Absolute Input Voltage

2000

1500

1000

500

2000

1500

1000

500

-40èC

25èC

85èC

125èC

-40èC

25èC

85èC

125èC

0

-500

-1000

-1500

-2000

-500

-1000

-1500

-2000

0

0.5

1

1.5 2

V_(AINx)(V)

2.5

3

3.5

0

0.5

1

1.5 2

V_(AINx)(V)

2.5

3

3.5

PGA enabled, gain = 1, DR = 20 SPS, V_IN= 0 V

PGA enabled, gain = 1, DR = 4 kSPS, V_IN= 0 V

图 9. Absolute Input Current vs Absolute Input Voltage

图 10. Absolute Input Current vs Absolute Input Voltage

2000

1500

1000

500

2000

-40èC

25èC

85èC

125èC

-40èC

25èC

85èC

125èC

1500

1000

500

0

-500

-1000

-1500

-2000

-500

-1000

-1500

-2000

-2.5 -2 -1.5 -1 -0.5

0

V_IN(V)

0.5

1

1.5

2

2.5

-2.5 -2 -1.5 -1 -0.5

0

V_IN(V)

0.5

1

1.5

2

2.5

PGA bypassed, DR = 20 SPS, V_CM= 1.65 V

PGA bypassed, DR = 4 kSPS, V_CM= 1.65 V

图 11. Differential Input Current vs Differential Input Voltage

图 12. Differential Input Current vs Differential Input Voltage

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Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

200

150

100

50

400

300

200

100

0

-40èC

25èC

85èC

125èC

-40èC

25èC

85èC

125èC

0

-50

-100

-200

-300

-400

-100

-150

-200

-2.5 -2 -1.5 -1 -0.5

0

V_IN(V)

0.5

1

1.5

2

2.5

-2.5 -2 -1.5 -1 -0.5

0

V_IN(V)

0.5

1

1.5

2

2.5

PGA enabled, DR = 20 SPS, V_CM= 1.65 V

PGA enabled, DR = 4 kSPS, V_CM= 1.65 V

图 13. Differential Input Current vs Differential Input Voltage

图 14. Differential Input Current vs Differential Input Voltage

3

2

1

2

1

0

-1

-2

-3

-1

-2

-3

-100 -80 -60 -40 -20

0

V_IN(% of FSR)

20

40

60

80 100

-100 -80 -60 -40 -20

0

V_IN(% of FSR)

20

40

60

80 100

PGA enabled, gain = 1

PGA bypassed, gain = 1

图 15. INL vs Differential Input Voltage

图 16. INL vs Differential Input Voltage

16

14

12

10

8

10

8

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 32

Gain = 64

Gain = 128

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 32

Gain = 64

Gain = 128

6

4

6

4

2

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

图 17. INL vs Temperature

图 18. Offset Voltage vs Temperature

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Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

2.502

2.501

2.5

0.03

0.025

0.02

0.015

0.01

0.005

0

2.499

2.498

2.497

PGA disabled

Gain = 1

Gain = 4

Gain = 32

Gain = 128

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

28 units, TQFP package

图 20. Internal Reference Voltage vs Temperature

图 19. Gain Error vs Temperature

2.5002

2.5001

2.5

10

8

6

4

2

0

2.4999

2.4998

2.4997

-2

-4

-6

-8

-10

2.7

3

3.3

3.6

3.9 4.2

AVDD (V)

4.5

4.8

5.1

5.4

Time (1 s/div)

图 22. Internal Reference Voltage Noise

图 21. Internal Reference Voltage vs AVDD

250

200

150

100

50

4.12

4.11

4.1

4.09

4.08

4.07

4.06

0

-50

-25

0

25 50

Temperature (C)

75

100

125

Internal Oscillator Frequency (MHz)

28 units

图 23. Internal Oscillator Frequency Histogram

图 24. Internal Oscillator Frequency vs Temperature

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Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

0

-1

-2

-3

-4

-5

0

-10

-20

-30

-40

-50

10 µA

50 µA

100 µA

250 µA

500 µA

750 µA

1 mA

1.5 mA

2 mA

10 µA

50 µA

100 µA

250 µA

500 µA

750 µA

1 mA

1.5 mA

2 mA

2.5

2.6

2.7

2.8

2.9

IDAC Output Voltage (V)

3

3.1

3.2

0

0.5

1

1.5

2

IDAC Output Voltage (V)

2.5

3

3.5

图 26. IDAC Accuracy vs Compliance Voltage

图 25. IDAC Accuracy vs Compliance Voltage

3

2

0.3

0.25

0.2

10 mA

750 mA

1 mA

1.5 mA

2 mA

50 mA

100 mA

250 mA

500 mA

1

0

0.15

0.1

-1

-2

-3

10 mA

750 mA

1 mA

1.5 mA

2 mA

50 mA

100 mA

250 mA

500 mA

0.05

0

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

IDAC output voltage = 1.65 V

图 27. IDAC Accuracy vs Temperature

图 28. IDAC Matching vs Temperature

180

160

140

120

100

80

0.501

0.5005

0.5

AVDD = 2.7 V

AVDD = 5.25 V

0.4995

0.499

0.4985

0.498

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

图 30. Temperature Sensor Voltage vs Temperature

图 29. VBIAS Voltage [(AVDD – AVSS) / 2] vs Temperature

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Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

3.3

3.2

3.1

3

0.6

0.5

0.4

0.3

0.2

0.1

0

-40èC

25èC

85èC

125èC

2.9

2.8

2.7

-40èC

25èC

85èC

125èC

0

1

2

3

Sourcing Current (mA)

4

5

6

7

8

0

1

2

3

Sinking Current (mA)

4

5

6

7

8

AVDD = 3.3 V

图 31. GPIO Pin Output Voltage vs Sourcing Current

图 32. GPIO Pin Output Voltage vs Sinking Current

0.6

0.5

0.4

0.3

0.2

0.1

0

3.3

-40èC

25èC

85èC

125èC

3.2

3.1

3

2.9

2.8

2.7

-40èC

25èC

85èC

125èC

0

1

2

3

4

5

Sinking Current (mA)

6

7

8

0

1

2

3

4

5

Sourcing Current (mA)

6

7

8

DVDD = 3.3 V

图 34. Digital Pin Output Voltage vs Sinking Current

图 33. Digital Pin Output Voltage vs Sourcing Current

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

Standby mode

PGA bypassed

Gain = 1

Gain = 4

Gain = 16

Gain = 64

Gain = 128

PGA bypassed

Gain = 1

Gain = 4

Gain = 16

Gain = 64

Gain = 128

0

-50

-25

0

25

50

75

100

125

2.7

3

3.3

3.6

3.9 4.2

AVDD (V)

4.5

4.8

5.1

5.4

Temperature (èC)

Standby and conversion mode, external V_REF

Conversion mode, external V_REF

图 35. Analog Supply Current vs Temperature

图 36. Analog Supply Current vs AVDD

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Typical Characteristics (接下页)

at T_A= 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF= 2.5 V, internal 4.096-MHz oscillator,

and PGA enabled (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

260

240

220

200

180

160

140

120

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature (èC)

Power-down mode

图 37. Analog Supply Current vs Temperature

图 38. Internal Reference AVDD Current vs Temperature

260

240

220

200

180

160

140

120

240

220

200

180

160

140

120

Standby mode

Conversion mode

-50

-25

0

25

50

75 100 125

2.7

2.8

2.9

3

3.1 3.2

DVDD (V)

3.3

3.4

3.5

3.6

Temperature (èC)

Standby and conversion mode

Conversion mode

图 40. Digital Supply Current vs DVDD

图 39. Digital Supply Current vs Temperature

5

4

3

2

1

0

-50

-25

0

25

50

75

100

125

Temperature (èC)

Power-down mode

图 41. Digital Supply Current vs Temperature

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8 Parameter Measurement Information

8.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input

signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and

decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between

modulator frequency and output data rate is called the oversampling ratio (OSR). By increasing the OSR, and

thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the

input-referred noise drops when reducing the output data rate because more samples of the internal modulator

are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is

particularly useful when measuring low-level signals.

表 1 and 表 2 summarize the device noise performance. Data are representative of typical noise performance at

T_A= 25°C using the internal 2.5-V reference. Data shown are based on 512 consecutive samples from a single

device with inputs internally shorted. 表 1 lists the input-referred root mean square noise in units of μV_RMSfor the

conditions shown. Peak-to-peak (µV_PP) values are shown in parentheses. 表 2 lists the corresponding data in

effective resolution calculated from μV_RMSvalues using 公式 1. Noise-free resolution is calculated from µV_PP

values using 公式 2.

The input-referred noise (表 1) only changes marginally when using an external low-noise reference, such as the

REF5025. To calculate effective resolution and noise-free resolution when using a reference voltage other than

2.5 V, use 公式 1 and 公式 2:

Effective Resolution = ln[(2 · V_REF/ Gain) / V_RMS-Noise] / ln(2)

Noise-Free Resolution= ln[(2 · V_REF/ Gain) / V_PP-Noise] / ln(2)

(1)

(2)

Noise performance with the PGA bypassed are identical to the noise performance of the device with gain = 1.

表 1. Noise in μV_RMS(μV_PP) at AVDD = 3.3 V, AVSS = 0 V,

PGA Enabled, and Internal 2.5-V Reference

DATA

RATE

(SPS)

GAIN

1

2

4

8

16

32

64

128

2.5

5

76.3 (76.3)

76.3 (83)

38.1 (38.1)

38.1 (80)

19.1 (19.1)

19.1 (32)

9.5 (9.5)

9.5 (17)

12 (70)

4.8 (4.8)

4.8 (11)

6.4 (39)

2.4 (2.4)

2.4 (2.8)

2.4 (4.0)

2.4 (5.1)

2.4 (6.7)

3.3 (21)

1.2 (1.2)

1.2 (1.4)

1.2 (1.9)

1.2 (2.9)

1.2 (3.8)

1.2 (4.3)

1.2 (6.6)

3.1 (21)

0.60 (0.60)

0.60 (0.90)

0.60 (1.3)

0.60 (1.7)

0.60 (2.3)

0.60 (3.2)

0.60 (3.8)

1.0 (6.5)

10

16.6

20

50

60

100

200

400

800

1000

2000

4000

103 (629)

38.1 (404)

24 (160)

2.6 (20)

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表 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)

at AVDD = 3.3 V, AVSS = 0 V, PGA Enabled, and Internal 2.5-V Reference

DATA

RATE

(SPS)

GAIN

1

2

4

8

16

32

64

128

2.5

5

16 (16)

16 (15.9)

16 (13.0)

16 (16)

16 (14.9)

16 (12.6)

16 (16)

16 (15.3)

15.7 (12.9)

16 (16)

16 (15.2)

16 (13.1)

16 (16)

16 (15.8)

16 (14.8)

15.6 (13.0)

16 (16)

10

16 (16)

16.6

20

16 (16)

50

16 (16)

16 (15.5)

16 (15.4)

16 (14.9)

16 (14.5)

16 (14.0)

16 (13.6)

16 (13.3)

15.2 (12.6)

13.6 (10.9)

60

16 (16)

100

200

400

800

1000

2000

4000

16 (16)

16 (15.8)

16 (15.3)

16 (14.7)

16 (14.3)

16 (14.2)

16 (13.5)

14.4 (11.9)

16 (16)

16 (15.8)

16 (15.2)

16 (14.9)

16 (14.5)

15.5 (12.9)

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9 Detailed Description

9.1 Overview

The ADS114S06B and ADS114S08B are precision 16-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs)

with an integrated analog front-end (AFE) to simplify precision sensor connections. The ADC provides output

data rates from 2.5 SPS to 4000 SPS for flexibility in resolution and data rates over a wide range of applications.

The low-noise and low-drift architecture make these devices suitable for precise measurement of low-voltage

sensors, such as load cells and temperature sensors.

The ADS114S0xB incorporates several features that simplify precision sensor measurements. Key integrated

features include:

•

Low-noise, CMOS PGA

Low-drift, 2.5-V voltage reference

Two sets of buffered external reference inputs with low reference voltage level detection

Dual, matched, sensor-excitation current sources (IDACs)

Internal 4.096-MHz oscillator

Temperature sensor

Four general-purpose input/output pins (GPIOs)

As described in the Functional Block Diagram section, these devices provide 12 (ADS114S08B) or six

(ADS114S06B) analog inputs that are configurable as either single-ended inputs, differential inputs, or any

combination of the two. Many of the analog inputs have additional features as programmed by the user. The

analog inputs can be programmed to enable the following extended features:

•

Two sensor excitation current sources: all analog input pins (and REFP1 and REFN1 on the ADS114S06B)

Sensor biasing voltage (VBIAS): pins AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AINCOM

Four GPIO pins: AIN8, AIN9, AIN10, AIN11 (ADS114S08B only, the ADS114S06B has dedicated GPIOs)

Sensor burn-out current sources: analog input pins selected for ADC input

Following the input multiplexer (MUX), the ADC features a high input-impedance, low-noise, programmable gain

amplifier (PGA), eliminating the need for an external amplifier. The PGA gain is programmable from 1 to 128 in

binary steps. The PGA can be bypassed to allow the input range to extend 50 mV below ground or above

supply.

An inherently stable ΔΣ modulator measures the ratio of the input voltage to the reference voltage to provide the

ADC result. The ADC operates with the internal 2.5-V reference, or with up to two external reference inputs. The

external reference inputs can be continuously monitored for low voltage. The REFOUT pin provides the buffered

2.5-V internal voltage reference output that can be used to bias external circuitry.

The digital filter provides settled data with 50-Hz and 60-Hz line-cycle rejection at data rates of 2.5 SPS, 5 SPS,

10 SPS, and 20 SPS, 50-Hz rejection at data rates of 16.6 SPS and 50 SPS, and 60-Hz rejection at a data rate

of 60 SPS.

Two programmable excitation current sources provide bias to resistive sensors [such as resistance temperature

detectors (RTDs) or thermistors]. The ADC integrates several system monitors for read back, such as

temperature sensor and supply monitors. Four GPIO pins are available as either dedicated pins (ADS114S06B)

or combined with analog input pins (ADS114S08B).

The ADS114S0xB system clock is either provided by the internal low-drift, 4.096-MHz oscillator or an external

clock source on the CLK input.

The SPI-compatible serial interface is used to read the conversion data and also to configure and control the

ADC. The serial interface consists of four signals: CS, SCLK, DIN, and DOUT/DRDY. The dual function

DOUT/DRDY output indicates when conversion data are ready and also provides the data output. The serial

interface can be implemented with as little as three connections by tying CS low. Start ADC conversions with

either the START/SYNC pin or with commands. The ADC can be programmed for a continuous conversion mode

or to perform single-shot conversions.

21

REFN0 REFP0 REFCOM REFOUT

DVDD

ADS114S06B, ADS114S08B

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Overview (接下页)

The AVDD analog supply operates with bipolar supplies from ±1.5 V to ±2.625 V or with a unipolar supply from

2.7 V to 5.25 V. For unipolar-supply operation, use the VBIAS voltage to bias isolated (floating) sensors. The

digital supplies operate with unipolar supplies only. The DVDD digital power supply operates from 2.7 V to 3.6 V

and the IOVDD supply operates from DVDD to 5.25 V.

9.2 Functional Block Diagram

AVDD

IOVDD

Burnout

Detect

2.5-V

Reference

ADS114S06B

ADS114S08B

Reference

Mux

Excitation

Current

Sources

AINCOM

AIN0

Reference

Detection

AIN1

Reference

Buffers

AIN2

VBIAS

START/SYNC

RESET

CS

AIN3

AIN4

Configurable

Digital

Filter

Serial

Interface

and

16-Bit ûꢀ

ADC

Input

Mux

PGA

AIN5

SCLK

AIN6 / REFP1

AIN7 / REFN1

AIN8 / GPIO0

AIN9 / GPIO1

Control

DIN

DOUT/DRDY

DRDY

System-, Self-

Calibration

Power Supplies

AIN10 / GPIO2

AIN11 / GPIO3

Temperature

Sensor

4.096-MHz

Oscillator

CLK

ADS114S08B

Only

Burnout

Detect

AVSS

DGND

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9.3 Feature Description

9.3.1 Multiplexer

The ADS114S0xB contains a flexible input multiplexer; see 图 42. Select any of the six (ADS114S06B) or 12

(ADS114S08B) analog inputs as the positive or negative input for the PGA using the MUX_P[3:0] and

MUX_N[3:0] bits in the input multiplexer register (02h). In addition, AINCOM can be selected as the positive or

negative PGA input. AINCOM is treated as a regular analog input, as is AINx. Use AINCOM in single-ended

measurement applications as the common input for the other analog inputs.

The multiplexer also routes the excitation current sources to drive resistive sensors (bridges, RTDs, and

thermistors) and can provide bias voltages for unbiased sensors (unbiased thermocouples for example) to analog

input pins.

The ADS114S0xB also contains a set of system monitor functions measured through the multiplexer. The inputs

can be shorted together at mid-supply [(AVDD + AVSS) / 2] to measure and calibrate the input offset of the

analog front-end and the ADC. The system monitor also includes a temperature sensor that provides a

measurement of the device temperature. The system monitor can also measure the analog and digital supplies,

measuring [(AVDD – AVSS) / 4] for the analog supply or DVDD / 4 for the digital supply. Finally, the system

monitor contains a set of burn-out current sources that pull the inputs to either supply if the sensor has burned

out and has a high impedance so that the ADC measures a full-scale reading.

The multiplexer implements a break-before-make circuit. When changing the multiplexer channels using the

MUX_P[3:0] and MUX_N[3:0] bits, the device first disconnects the PGA inputs from the analog inputs and

connects them to mid-supply for 2 · t_CLK. In the next step, the PGA inputs connect to the selected new analog

input channels. This break-before-make behavior ensures the ADC always starts from a known state and that the

analog inputs are not momentarily shorted together.

Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. The absolute voltage on any input

must stay within the range provided by 公式 3 to prevent the ESD diodes from turning on:

AVSS – 0.3 V < V_(AINx)< AVDD + 0.3 V

(3)

External Schottky clamp diodes or series resistors may be required to limit the input current to safe values (see

the Absolute Maximum Ratings table). Overdriving an unselected input on the device can affect conversions

taking place on other input pins.

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ADS114S06B, ADS114S08B

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Feature Description (接下页)

AVDD

IDAC2

AVDD

IDAC1

(1)

VBIAS

AVSS

AVDD

(AVDD + AVSS) / 2

AINCOM

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AVDD

Temperature

Diode

(2)

(AVDD Þ AVSS) • (5 / 8)

(AVDD Þ AVSS) • (3 / 8)

(3)

DVDD • (4 / 12)

DVDD • (1 / 12)

AVDD

Burn-Out Current Source

AIN_P

To ADC

PGA

AIN_N

Burn-Out Current Source

AVSS

ADS114S08B Only

(1) AIN_Pand AIN_Nare connected together to (AVDD + AVSS) / 2 for offset measurement.

(2) Measurement for the analog supply equivalent to (AVDD – AVSS) / 4.

(3) Measurement for the analog supply equivalent to DVDD / 4.

图 42. Analog Input Multiplexer

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Feature Description (接下页)

9.3.2 Low-Noise Programmable Gain Amplifier

The ADS114S06B and ADS114S08B feature a low-drift, low-noise, high input impedance programmable gain

amplifier (PGA). 图 43 shows a simplified diagram of the PGA. The PGA consists of two chopper-stabilized

amplifiers (A1 and A2) and a resistor feedback network that sets the gain of the PGA. The PGA input is equipped

with an electromagnetic interference (EMI) filter and an antialiasing filter on the output.

250 ꢀ

+

AIN_P

A1

R_F

16 pF

2.5 kꢀ

320 pF

R_G

ADC

R_F

A2

2.5 kꢀ

250 ꢀ

+

AIN_N

16 pF

图 43. Simplified PGA Diagram

The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128 using the GAIN[2:0] bits in the gain setting register

(03h). Gain is changed inside the device using a variable resistor, R_G. The differential full-scale input voltage

range (FSR) of the PGA is defined by the gain setting and the reference voltage used, as shown in 公式 4:

FSR = ±V_REF/ Gain

(4)

表 3 shows the corresponding full-scale ranges when using the internal 2.5-V reference.

表 3. PGA Full-Scale Range

GAIN SETTING

FSR

1

2

±2.5 V

±1.25 V

±0.625 V

±0.313 V

±0.156 V

±0.078 V

±0.039 V

±0.020 V

4

8

16

32

64

128

The PGA must be enabled with the PGA_EN[1:0] bits of the gain setting register (03h). Setting these bits to 00

powers down and bypasses the PGA. A setting of 01 enables the PGA. The 10 and 11 settings are reserved and

must not be written to the device.

With the PGA enabled, gains 64 and 128 are established in the digital domain. When the device is set to 64 or

128, the PGA is set to a gain of 32, and additional gain is established with digital scaling. The input-referred

noise does still improve compared to the gain = 32 setting because the PGA is biased with a higher supply

current to reduce noise.

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9.3.2.1 PGA Input-Voltage Requirements

As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded.

The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA

output. The specified minimum and maximum absolute input voltages (V_AINPand V_AINN) depend on the PGA gain,

the maximum differential input voltage (V_INMAX), and the tolerance of the analog power-supply voltages (AVDD

and AVSS). Use the maximum voltage expected in the application for V_INMAX. As shown in 公式 5, the absolute

positive and negative input voltages must be within the specified range:

AVSS + 0.15 V + |V_INMAX| · (Gain – 1) / 2 < V_AINP, V_AINN< AVDD – 0.15 V – |V_INMAX| · (Gain – 1) / 2

where

•

V_AINP, V_AINN= absolute input voltage

V_INMAX= V_AINP– V_AINN= maximum differential input voltage

(5)

As mentioned in the previous section, PGA gain settings of 64 and 128 are scaled in the digital domain and are

not implemented with the amplifier. When using the PGA in gains of 64 and 128, set the gain in 公式 5 to 32 to

calculate the absolute input voltage range.

图 44 graphically shows the relationship between the PGA input to the PGA output. The PGA output voltages

(V_OUTP, V_OUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the PGA output

voltages must not exceed AVDD – 0.15 V or AVSS + 0.15 V. The diagram depicts a positive differential input

voltage that results in a positive differential output voltage.

PGA Input

PGA Output

AVDD

AVDD œ 0.15 V

V_OUTP= V_AINP+ V_IN‡ (Gain œ 1) / 2

V_AINP

V_IN= V_AINPœ V_AINN

V_AINN

V_OUTN= V_AINNœ V_IN‡ (Gain œ 1) / 2

AVSS + 0.15 V

AVSS

图 44. PGA Input/Output Range

Download the ADS1x4S0x design calculator from www.ti.com. This calculator can be used to determine the input

voltage range of the PGA.

9.3.2.2 Bypassing the PGA

At a gain of 1, the device can be configured to disable and bypass the low-noise PGA. Disabling the PGA lowers

the overall power consumption and also removes the restrictions of 公式 5 for the input voltage range. If the PGA

is bypassed, the ADC absolute input voltage range extends beyond the AVDD and AVSS power supplies,

allowing input voltages at or below ground. 公式 6 shows the absolute input voltage range when the PGA is

bypassed:

AVSS – 0.05 V < V_AINP, V_AINN< AVDD + 0.05 V

(6)

In order to measure single-ended signals that are referenced to AVSS (AIN_P= V_IN, AIN_N= AVSS), the PGA must

be bypassed. The PGA is bypassed and powered down by setting the PGA_EN[1:0] bits to 00 in the gain setting

register (03h).

For signal sources with high output impedance, external buffering may still be necessary. Active buffers introduce

noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.

26

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9.3.3 Voltage Reference

The devices require a reference voltage for operation. The ADS114S0xB offers an integrated low-drift 2.5-V

reference. For applications that require a different reference voltage value or a ratiometric measurement

approach, the ADS114S08B offers two differential reference input pairs (REFP0, REFN0 and REFP1, REFN1).

The differential reference inputs allow freedom in the reference common-mode voltage. REFP0 and REFN0 are

dedicated reference inputs, whereas REFP1 and REFN1 are shared with inputs AIN6 and AIN7 (respectively) on

the ADS114S08B. The specified external reference voltage range is 0.5 V to AVDD. The reference voltage is

shown in 公式 7, where V_(REFPx)and V_(REFNx)are the absolute positive and absolute negative reference voltages.

V_REF= V_(REFPx)– V_(REFNx)

(7)

The polarity of the reference voltage internal to the ADC must be positive. The magnitude of the reference

voltage together with the PGA gain establishes the ADC full-scale differential input range as defined by

FSR = ±V_REF/ Gain.

图 45 shows the block diagram of the reference multiplexer. The ADC reference multiplexer selects between the

internal reference and two external references (REF0 and REF1). The reference multiplexer is programmed with

the REFSEL[1:0] bits in the reference control register (05h). By default, the external reference pair REFP0,

REFN0 is selected.

REFSEL[1:0] bits of REF register

00 = REFP0, REFN0

01 = REFP1, REFN1

10 = Internal 2.5-V reference

11 = Reserved

REFP_BUF bit of REF register

0 = Enabled

00

REFP0

1 = Disabled

01

REFP1

10

REFOUT

V_REFP

Internal

2.5-V

Reference

1 mF⁽¹⁾

V_REFN

00

REFN0

01

10

ADC

REFN1

REFN_BUF bit of REF register

0 = Enabled

1 = Disabled

REFCOM

REFCON[1:0] bits of REF register

00 = Internal reference off

01 = Internal reference on;

off in power-down mode

10 = Internal reference always on

11 = Reserved

(1) The internal reference requires a minimum 1-µF capacitor connected from REFOUT to REFCOM.

图 45. Reference Multiplexer Block Diagram

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9.3.3.1 Internal Reference

The ADC integrates a precision, low-drift, 2.5-V reference. The internal reference is enabled by setting

REFCON[1:0] to 10 (reference is always on) or 01 (reference is on, but powers down in power-down mode) in

the reference control register (05h). By default, the internal voltage reference is powered down. To select the

internal reference for use with the ADC, set the REFSEL[1:0] bits to 10. The REFOUT pin provides a buffered

reference output voltage when the internal reference voltage is enabled. The negative reference output is the

REFCOM pin; see 图 45. Connect a capacitor in the range of 1 μF to 47 μF between REFOUT and REFCOM.

Larger capacitor values help filter more noise at the expense of a longer reference start-up time.

The capacitor is not required if the internal reference is not used. However, the internal reference must be

powered on if using the IDACs.

The internal reference requires a start-up time, as shown in 表 4, that must be accounted for before starting a

conversion.

表 4. Internal Reference Settling Time

REFOUT CAPACITOR

SETTLING ERROR

0.01%

SETTLING TIME (ms)

4.5

5.9

4.9

6.3

5.5

7.0

1 µF

0.001%

0.01%

10 µF

47 µF

0.001%

0.01%

0.001%

9.3.3.2 External Reference

The ADS114S0xB provides two external reference inputs selectable through the reference multiplexer. The

reference inputs are differential with independent positive and negative inputs. REFP0 and REFN0 or REFP1

and REFN1 can be selected as the ADC reference. REFP1 and REFN1 are shared inputs with analog pins AIN6

and AIN7 in the ADS114S08B.

Without buffering, the reference input impedance is approximately 250 kΩ. The reference input current can lead

to possible errors from either high reference source impedance or through reference input filtering. To reduce the

input current, use either internal or external reference buffers. In most applications external reference buffering is

not necessary.

Connect a bypass capacitor across the external reference input pins if an external reference is used. Follow the

specified absolute and differential reference voltage requirements.

9.3.3.3 Reference Buffers

The device has two individually selectable reference input buffers to lower the reference input current. Use the

REFP_BUF and REFN_BUF bits in the reference control register (05h) to enable or disable the positive and

negative reference buffers respectively. These bits are active low. Writing a 1 to REFP_BUF or REFN_BUF

disables the reference buffers.

The reference buffers are recommended to be disabled when the internal reference is selected for

measurements. The positive reference buffer is recommended to be disabled when REFPx is at AVDD and the

negative reference buffer is recommended to be disabled when REFNx is at AVSS.

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9.3.4 Clock Source

The ADS114S0xB system clock is either provided by the internal low-drift 4.096-MHz oscillator or an external

clock source on the CLK input. Use the CLK bit within the data rate register (04h) to select the internal

4.096-MHz oscillator or an external clock source.

The device defaults to using the internal oscillator. If the device is reset (from either the RESET pin, or the

RESET command), then the clock source returns to using the internal oscillator.

9.3.5 Delta-Sigma Modulator

A delta-sigma (ΔΣ) modulator is used in the devices to convert the analog input voltage into a pulse code

modulated (PCM) data stream. The modulator runs at a modulator clock frequency of f_MOD= f_CLK/ 16, where f_CLK

is either provided by the internal 4.096-MHz oscillator or the external clock source.

9.3.6 Digital Filter

The devices offer digital filter options for decimation of the digital data stream coming from the delta-sigma

modulator. The implementation of the digital filter is determined by the data rate setting. 图 46 shows the digital

filter implementation.

The low-latency digital filter is a finite impulse response (FIR) filter that provides settled data, given that the

analog input signal has settled to the final value before the conversion is started. This digital filter implementation

is especially useful when multiple channels must be scanned in minimal time.

f_CLK= 4.096 MHz

f_CLK/ 16

Low-Latency Filter

f_MOD= 256 kHz

20, 10, 5, 2.5 SPS

LL2

Filter

SINC1

Filter

SINC3

Filter

ADC

400, 200, 100, 60, 50, 16.6 SPS

4000, 2000, 1000, 800 SPS

LL1

Filter

SINC1

Filter

ADC data

output

DR[3:0] bits of

DATARATE Register

0000 = 2.5 SPS

0001 = 5 SPS

1000 = 200 SPS

1001 = 400 SPS

1010 = 800 SPS

1011 = 1000 SPS

1100 = 2000 SPS

1101 = 4000 SPS

1110 = 4000 SPS

1111 = Reserved

0010 = 10 SPS

0011 = 16.6 SPS

0100 = 20 SPS

0101 = 50 SPS

0110 = 60 SPS

0111 = 100 SPS

NOTE: LL filter = low-latency filter.

图 46. Digital Filter Architecture

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The device requires a set number of modulator clocks to output a single ADC conversion data. This number is

known as the oversampling ratio (OSR). The OSR of the digital filter is set using the DR[3:0] bits in the data rate

register. 公式 8 determines the data rate.

Data Rate = f_MOD/ OSR

(8)

表 5 shows the relationship between the data rate and oversampling ratio.

表 5. ADC Data Rates and Digital Filter Oversampling Ratios

NOMINAL DATA RATE

(SPS)⁽¹⁾

DATA RATE REGISTER

DR[3:0]

OVERSAMPLING

RATIO⁽²⁾

2.5

5

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

102400

51200

25600

15360

12800

5120

4264

2560

1280

640

10

16.6

20

50

60

100

200

400

800

1000

2000

4000

320

256

128

64

(1) Valid for the internal oscillator or an external 4.096-MHz clock. The data rate scales with internal

oscillator or external clock frequency.

(2) The oversampling ratio is f_MODdivided by the data rate; f_MOD= f_CLK/ 16.

9.3.6.1 Digital Filter Frequency Response

The digital filter provides many data rate options for rejecting 50-Hz and 60-Hz line cycle noise. At data rates of

2.5 SPS, 5 SPS, 10 SPS, and 20 SPS, the filter rejects both 50-Hz and 60-Hz line frequencies. At data rates of

16.6 SPS and 50 SPS, the filter has a notch at 50 Hz. At a 60-SPS data rate, the filter has a notch at 60 Hz.

For detailed frequency response plots showing line cycle noise rejection, download the ADS1x4S0x design

calculator from www.ti.com.

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图 47 to 图 61 illustrate the frequency response of the digital filter for different data rates. 表 6 lists the bandwidth

of the digital filter for each data rate.

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

0

10

20

30 40

Frequency (Hz)

50

60

70

0

10

20

30 40

Frequency (Hz)

50

60

70

160

70

f_CLK= 4.096 MHz

图 47. Digital Filter Frequency Response,

图 48. Digital Filter Frequency Response,

Data Rate = 2.5 SPS

Data Rate = 5 SPS

0

-20

-40

-60

0

-20

-40

-60

-80

-100

-120

10

20

30

40

Frequency (Hz)

50

60

70

80

90 100

0

20

40

60

80

Frequency (Hz)

100

120

140

f_CLK= 4.096 MHz

图 49. Digital Filter Frequency Response,

图 50. Digital Filter Frequency Response,

Data Rate = 10 SPS

Data Rate = 16.6 SPS

0

-20

0

-20

-40

-60

-80

-100

-120

-100

-120

20

40

60

80 100 120 140 160 180 200

Frequency (Hz)

40

45

50

55

Frequency (Hz)

60

65

f_CLK= 4.096 MHz

图 51. Digital Filter Frequency Response,

图 52. Digital Filter Frequency Response,

Data Rate = 20 SPS, Zoomed to 50 Hz and 60 Hz

Data Rate = 20 SPS

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0

-20

-40

-60

0

-20

-40

-60

0

50

100

150

200

Frequency (Hz)

250

300

350

400

0

100

200

Frequency (Hz)

300

400

f_CLK= 4.096 MHz

图 53. Digital Filter Frequency Response,

图 54. Digital Filter Frequency Response,

Data Rate = 50 SPS

Data Rate = 60 SPS

0

-20

-40

-60

0

-20

-40

-60

400

800 1200

Frequency (Hz)

1600

2000

0

200

400 600

Frequency (Hz)

800

1000

f_CLK= 4.096 MHz

图 56. Digital Filter Frequency Response,

图 55. Digital Filter Frequency Response,

Data Rate = 200 SPS

Data Rate = 100 SPS

0

-20

-40

-60

-80

0

-20

-40

-60

-80

0

500 1000 1500 2000 2500 3000 3500 4000

Frequency (Hz)

1000 2000 3000 4000 5000 6000 7000 8000

Frequency (Hz)

f_CLK= 4.096 MHz

图 57. Digital Filter Frequency Response,

图 58. Digital Filter Frequency Response,

Data Rate = 400 SPS

Data Rate = 800 SPS

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0

-20

-40

-60

-40

-60

-80

-100

-80

0

4000

8000 12000

Frequency (Hz)

16000

20000

2000

4000 6000

Frequency (Hz)

8000

10000

f_CLK= 4.096 MHz

图 60. Digital Filter Frequency Response,

图 59. Digital Filter Frequency Response,

Data Rate = 2 kSPS

Data Rate = 1 kSPS

0

-20

-40

-60

-80

-100

0

8000

16000 24000

Frequency (Hz)

32000

40000

f_CLK= 4.096 MHz

图 61. Digital Filter Frequency Response,

Data Rate = 4 kSPS

表 6. Digital Filter Bandwidth

NOMINAL DATA RATE (SPS)⁽¹⁾

–3-dB BANDWIDTH (Hz)⁽¹⁾

2.5

5

1.1

2.2

10

4.7

16.6

20

7.4

13.2

22.1

26.6

44.4

89.9

190

574

717

1434

2868

50

60

100

200

400

800

1000

2000

4000

(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with f_CLK

.

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The digital filter notches and output data rate scale proportionally with the clock frequency. For example, a notch

that appears at 20 Hz when using a 4.096-MHz clock appears at 10 Hz if a 2.048-MHz clock is used. The

internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate,

conversion time, and filter notches consequently vary by the same percentage. Consider using an external

precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.

9.3.6.2 Data Conversion Time

The amount of time required to receive data from the ADC depends on more than just the nominal data rate of

the device. The data period also depends on the mode of operation and other configurations of the device. In

normal operation, the data settles in one data period. However, a small amount of latency exists to set up the

device, calculate the conversion data from the modulator samples, and other overhead that adds time to the

conversion. For this reason, the first conversion data takes longer than subsequent data conversions.

表 7 shows the conversion times for the digital filter for each ADC data rate and various conversion modes.

表 7. Data Conversion Time

FIRST DATA

SECOND AND SUBSEQUENT

CONVERSIONS FOR CONTINUOUS

CONVERSION MODE

FOR CONTINUOUS CONVERSION MODE

NOMINAL

DATA RATE⁽¹⁾

(SPS)

OR SINGLE-SHOT CONVERSION MODE⁽²⁾

NUMBER OF

t_MODPERIODS

NUMBER OF

t_MODPERIODS

ms

2.5

5

406.559

206.559

106.559

60.309

56.559

20.211

16.965

10.211

5.211

104079

52879

27279

15439

14479

5174

4343

2614

1334

694

400

200

100

60

102400

51200

25600

15360

12800

5120

4264

2560

1280

640

10

16.6

20

50

20

60

16.66

10

100

200

400

800

1000

2000

4000

5

2.711

2.5

1.25

1

1.461

374

320

1.211

310

256

0.711

182

0.5

0.25

128

0.461

118

64

(1) Valid for the internal oscillator or an external 4.096-MHz clock. Scales proportional with f_CLK

.

(2) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.

9.3.6.3 Note on Conversion Time

Each data period consists of time required for the modulator to sample the analog inputs. However, there is

additional time required before the samples become an ADC conversion result.

When a new conversion is started, there is a configuration delay time of 14 · t_MOD(where t_MOD= 16 · t_CLK) that is

added before the conversion starts. This delay allows for additional settling time for external RC filters on the

analog inputs and for the antialiasing filter after the PGA. The configuration delay occurs at the start of a new

conversion after a START command is sent, the START/SYNC pin is taken high, or a WREG command is sent

to change any configuration register from address 03h to 07h (as described in the WREG section).

Also, overhead time is needed to convert the modulator samples into an ADC conversion result. This overhead

time includes any necessary offset or gain compensation after the digital filter accumulates a data result. The first

conversion when the device is in continuous conversion mode (just as in single-shot conversion mode) includes

the configuration delay, the modulator sampling time, and the overhead time. The second and subsequent

conversions are the normal data period (period as given by the inverse of the data rate).

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图 62 shows the time sequence for the ADC in both continuous conversion and single-shot conversion modes.

Single-shot conversion mode

Conversion

start⁽¹⁾

Data

ready

Configuration delay

Modulator sampling

ADC overhead

Sampling for

first data

DRDY

Continuous conversion mode

Conversion

start⁽¹⁾

First

data ready

Second

data ready

Third data

ready

Sampling for

first data

Sampling for

second data

Sampling for

third data

Continued

sampling

DRDY

(1) Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START

command.

图 62. Single-Shot Conversion Mode and Continuous Conversion Mode Sequences

9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection

If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and

60-Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and can lead to

inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line-coupled noise for

data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired

level of line cycle rejection. 表 8 summarizes the ADC 50-Hz and 60-Hz line-cycle rejection based on ±1-Hz and

±2-Hz tolerance of power-line frequency. The best possible power-line rejection is provided by using an accurate

ADC clock.

表 8. 50-Hz and 60-Hz Line Cycle Rejection

DIGITAL FILTER LINE CYCLE REJECTION (dB)

DATA RATE (SPS)⁽¹⁾

50 Hz ± 1 Hz

–113.7

–111.9

–111.5

–33.8

60 Hz ± 1 Hz

–95.4

50 Hz ± 2 Hz

–97.7

60 Hz ± 2 Hz

–92.4

2.5

5

–95.4

–87.6

–81.8

10

–95.4

–85.7

–81.0

16.6

20

–20.9

–27.8

–20.8

–95.4

–75.5

–80.5

50

–33.8

–15.5

–27.6

–15.1

60

–13.4

–35.0

–12.6

–29.0

(1) f_CLK= 4.096 MHz.

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9.3.7 Excitation Current Sources (IDACs)

The ADS114S0xB incorporates two integrated, matched current sources (IDAC1, IDAC2). The current sources

provide excitation current to resistive temperature devices (RTDs), thermistors, diodes, and other resistive

sensors that require constant current biasing. The current sources are programmable to output values between

10 μA to 2000 μA using the IMAG[3:0] bits in the excitation current register 1 (06h). Each current source can be

connected to any of the analog inputs AINx as well as the REFP1 and REFN1 inputs for the ADS114S06B. Both

current sources can also be connected to the same pin. The routing of the IDACs is configured by the

I1MUX[3:0] and I2MUX[3:0] bits in the excitation current register 2 (07h). In three-wire RTD applications, the

matched current sources can be used to cancel errors caused by sensor lead resistance (see the Typical

Application section for more details). 图 63 details the IDAC connection through the input multiplexer.

I1MUX[3:0] bits of the IDACMUX register.

IDAC routing to AIN8 œ AIN11 is available

only on the ADS114S08B.

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

AIN0

AIN1

AIN2

AVDD

AIN3

AIN4

AIN5

AIN6/REFP1

AIN7/REFN1

AIN8

AIN6 / REFP1

AIN7 / REFN1

AIN8

IDAC1

Mux

IDAC1

AIN9

ADS114S08B AIN9

Only

IMAG[3:0] bits of the IDACMAG register.

0000 = Off

0001 = 10 µA

AIN10

AIN11

AINCOM

0010 = 50 µA

0011 = 100 µA

AINCOM

No Connection 1101-1111

0100 = 250 µA

0101 = 500 µA

0110 = 750 µA

0111 = 1000 µA

1000 = 1500 µA

1001 = 2000 µA

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

AVDD

AIN6/REFP1

AIN7/REFN1

AIN8

IDAC2

Mux

IDAC2

AIN9

AIN10

AIN11

AINCOM

No Connection 1101-1111

I2MUX[3:0] bits of the IDACMUX register.

IDAC routing to AIN8 œ AIN11 is available

only on the ADS114S08B.

图 63. IDAC Block Diagram

The internal reference must be enabled for IDAC operation. As with any current source, the IDAC requires

voltage headroom to the positive supply to operate. This voltage headroom is the compliance voltage. When

driving resistive sensors and biasing resistors, take care not to exceed the compliance voltage of the IDACs,

otherwise the specified accuracy of the IDAC current may not be met. For IDAC compliance voltage

specifications, see the Electrical Characteristics table.

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9.3.8 Bias Voltage Generation

The ADS114S0xB provides an internal bias voltage generator, VBIAS, that is set to (AVDD + AVSS) / 2. The

bias voltage is internally buffered and can be established on the analog inputs AIN0 to AIN5 and AINCOM using

the VB_AINx bits in the sensor biasing register (08h). A typical use case for VBIAS is biasing unbiased

thermocouples to within the common-mode voltage range of the PGA. 图 64 shows a block diagram of the

VBIAS voltage generator and connection diagram.

AVDD

AIN0

AIN1

AIN2

Input

Mux

AIN3

AIN4

AIN5

R

AINCOM

(AVDD + AVSS) / 2

R

VB_AINx bits of VBIAS register

0 = VBIAS not connected to AINx

1 = VBIAS connected to AINx

AVSS

图 64. VBIAS Block Diagram

The start-up time of the VBIAS voltage depends on the pin load capacitance. The total capacitance includes any

capacitance connected from VBIAS to AVDD, AVSS, and ground. 表 9 lists the VBIAS voltage settling times for

various external load capacitances. Ensure the VBIAS voltage is fully settled before starting a conversion.

表 9. VBIAS Settling Time

LOAD CAPACITANCE

SETTLING TIME

280 µs

0.1 µF

1 µF

2.8 ms

10 µF

28 ms

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9.3.9 System Monitor

The ADS114S0xB provides a set of system monitor functions. These functions measure the device temperature,

analog power supply, digital power supply, or use current sources to detect sensor malfunction. System monitor

functions are enabled through the SYS_MON[2:0] bits of the system control register (09h).

9.3.9.1 Internal Temperature Sensor

On-chip diodes provide temperature-sensing capability. Enable the internal temperature sensor by setting

SYS_MON[2:0] = 010 in the system control register (09h). The temperature sensor outputs a voltage proportional

to the device temperature as specified in the Electrical Characteristics table.

When measuring the internal temperature sensor, the analog inputs are disconnected from the ADC and the

output voltage of the temperature sensor is routed to the ADC for measurement using the selected PGA gain,

data rate, and voltage reference. If enabled, PGA gain must be limited to 4 for the temperature sensor

measurement to remain within the allowed absolute input voltage range of the PGA. As a result of the low device

junction-to-PCB thermal resistance (R_θJB), the internal device temperature closely tracks the printed circuit board

(PCB) temperature.

9.3.9.2 Power Supply Monitors

The ADS114S0xB provides a means for monitoring both the analog and digital power supply (AVDD and DVDD).

The power-supply voltages are divided by a resistor network to reduce the voltages to within the ADC input

range. The reduced power-supply voltage is routed to the ADC input multiplexer. The analog (V_ANLMON) and

digital (V_DIGMON) power-supply readings are scaled by 公式 9 and 公式 10, respectively:

V_ANLMON= (AVDD – AVSS) / 4

V_DIGMON= (DVDD – DGND) / 4

(9)

(10)

Enable the supply voltage monitors using the SYS_MON[2:0] bits in the system control register (09h). Setting

SYS_MON[2:0] to 011 measures V_ANLMON, and setting SYS_MON[2:0] to 100 measures V_DIGMON

.

When the supply voltage monitor is enabled, the analog inputs are disconnected from the ADC and the PGA gain

is set to 1, regardless of the GAIN[2:0] bit values in the gain setting register (03h). Supply voltage monitor

measurements can be done with either the PGA enabled or PGA disabled via the PGA_EN[1:0] register. The

reference voltage must be larger than the power-supply measurements shown in 公式 9 and 公式 10 to obtain

valid power-supply monitor readings.

9.3.9.3 Burn-Out Current Sources

To help detect a possible sensor malfunction, the ADS114S0xB provides selectable current sources to function

as burn-out current sources (BOCS) using the SYS_MON[2:0] bits in the system control register (09h). Current

sources are set to values of 0.2 µA, 1 µA, and 10 µA with SYS_MON[2:0] settings of 101, 110, and 111,

respectively.

When enabled, one BOCS sources current to the selected positive analog input (AIN_P) and the other BOCS

sinks current from the selected negative analog input (AIN_N). With an open-circuit in a burned out sensor, these

BOCSs pull the positive input towards AVDD and the negative input towards AVSS, resulting in a full-scale

reading. A full-scale reading can also indicate that the sensor is overloaded or that the reference voltage is

absent. A near-zero reading can indicate a shorted sensor. Distinguishing a shorted sensor condition from a

normal reading can be difficult, especially if an RC filter is used at the inputs. The voltage drop across the

external filter resistance and the residual resistance of the multiplexer can cause the output to read a value

higher than zero.

The ADC readings of a functional sensor can be corrupted when the burn-out current sources are enabled. The

burn-out current sources are recommended to be disabled when performing the precision measurement, and are

recommended to be enabled only when testing for sensor fault conditions.

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9.3.10 Status Register

The ADS114S0xB has a one-byte status register (01h) that contains a POR flag to indicate if a start-up or power-

on reset condition has occurred, a RDY flag to indicate when a device has started up and is ready for

communication, and a low reference voltage level flag to indicate when the voltage level of the selected external

reference falls below the specified threshold.

The status register data field and field descriptions are located in the device status register. The following

sections describe the various flags that are indicated in the STATUS byte.

9.3.10.1 POR Flag

After the power supplies are turned on, the ADC remains in reset until DVDD, IOVDD, and the analog power

supply (AVDD – AVSS) voltages exceed the respective power-on reset (POR) voltage thresholds. If a POR event

has occurred, the FL_POR flag (bit 7 of the status register) is set. This flag indicates that a POR event has

occurred and has not been cleared. This flag is cleared with a user register write to set the bit to 0. The power-on

reset is described further in the Power-On Reset section.

9.3.10.2 RDY Flag

The RDY flag indicates that the device has started up and is ready to receive a configuration change. During a

reset or POR event, the device is resetting the register map and may not be available. The RDY flag is shown

with bit 6 of the status register.

9.3.10.3 External Reference Monitor

The selected external ADC reference inputs can be continuously monitored for a low reference voltage. The

reference detection circuit has a threshold of 300 mV. The reference detection circuit measures the differential

reference voltage and sets a flag latched after each conversion in the STATUS byte if the voltage is below the

threshold. A reference voltage less than 300 mV can indicate a potential short on the reference inputs or, in case

of a ratiometric RTD measurement, a broken wire between the RTD and the reference resistor.

The reference monitor must be enabled with the FL_REF_EN bit in the reference control register (05h). The

FL_REF flag (bit 0 of the STATUS byte) indicates if the select external reference voltage is lower than 0.3 V. A

reference monitor fault is latched at each conversion cycle and the FL_REF flag in the status register is updated

at the falling edge of DRDY.

9.3.11 General-Purpose Inputs and Outputs (GPIOs)

The ADS114S06B offers four dedicated general-purpose input and output (GPIO) pins, and the ADS114S08B

offers four pins (AIN8 to AIN11) that serve a dual purpose as either analog inputs or GPIOs.

Two registers control the function of the GPIO pins. Use the CON[3:0] bits of the GPIO configuration register

(11h) to configure a pin as a GPIO pin. The upper four bits (DIR[3:0]) of the GPIO data register (10h) configure

the GPIO pin as either an input or an output. The lower four bits (DAT[3:0]) of the GPIO data register contain the

input or output GPIO data. If a GPIO pin is configured as an input, the respective DAT[x] bit reads the status of

the pin; if a GPIO pin is configured as an output, write the output status to the respective DAT[x] bit. For more

information about the use of GPIO pins, see the Configuration Registers section.

图 65 depicts a diagram of how these functions are combined onto a single pin. When the pin is configured as a

GPIO, the corresponding logic is powered from AVDD and AVSS. When the devices are operated with bipolar

analog supplies, the GPIO outputs bipolar voltages. Care must be taken to not load the GPIO pins when used as

outputs because large currents can cause droop or noise on the analog supplies. GPIO pins use Schmitt

triggered inputs with hysteresis to make the input more resistance to noise; see the Electrical Characteristics

table for GPIO thresholds.

For connections of unused GPIO pins, see the Unused Inputs and Outputs section.

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AVDD

CON[3:0] bits of GPIOCON register

0 = no connect

1 = connect

DAT[3:0] bits of GPIODAT register

0 = V_GPIOis low

1 = V_GPIOis high

GPIO

1 of 4

Write

0

Read

GPIO[0]

GPIO[1]

GPIO[2]

0

1

AIN8

AIN9

AIN10

AIN11

GPIO Read Select

GPIO[3]

DIR[7:4] bits of GPIODAT register

0 = Output

1 = Input

GPIO logic is powered from

AVDD to AVSS

AVSS

图 65. GPIO Block Diagram

9.3.12 Calibration

The ADC incorporates offset and gain calibration commands, as well as user-offset and full-scale (gain)

calibration registers to calibrate the ADC. The ADC calibration registers are 16 bits wide. Use calibration to

correct internal ADC errors or overall system errors. Calibrate by sending calibration commands to the ADC, or

by direct user calibration. In user calibration, the user calculates and writes the correction values to the

calibration registers. The ADC performs self or system-offset calibration, or a system gain calibration. Perform

offset calibration before system gain calibration. After power-on, wait for the power supplies and reference

voltage to fully settle before calibrating.

As shown in 图 66, the value of the offset calibration register is subtracted from the filter output and then

multiplied by the full-scale register value divided by 4000h. The data are then clipped to a 16-bit value to provide

the final output.

AIN_P

C A D

+

Output Data

Clipped to 16 bits

Digital

Filter

Final

Output

ADC

AIN_N

-

1/4000h

OFCAL[1:0] registers

(register addresses = 0Ch, 0Bh)

> 0000h: negative offset

= 0000h: no offset

< 0000h: positive offset

FSCAL[1:0] registers

(register addresses = 0Fh, 0Eh)

< 4000h: Gain > 1

= 4000h: Gain = 1

> 4000h: Gain < 1

图 66. ADC Calibration Block Diagram

Calibration commands cannot be used when the device is in standby mode (when the START/SYNC pin is low,

or when the STOP command is issued).

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9.3.12.1 Offset Calibration

The offset calibration word is 16 bits, consisting of two 8-bit registers, as shown in the two registers starting with

offset calibration register 1. The offset value is twos complement format with a maximum positive value equal to

7FFFh, and a maximum negative value equal to 8000h. This value is subtracted from each output reading as an

offset correction. A register value equal to 0000h has no offset correction. 表 10 shows example settings of the

offset register.

表 10. Offset Calibration Register Values

OFC REGISTER VALUE

OFFSET CALIBRATED OUTPUT CODE⁽¹⁾

0001h

0000h

FFFFh

0000h

0001h

(1) Ideal output code with shorted input, excluding ADC noise and offset voltage error.

The user can select how many samples (1, 4, 8, or 16) to average for self or system offset calibration using the

CAL_SAMP[1:0] bits in the system control register (09h). Fewer readings shorten the calibration time but also

provide less accuracy. Averaging more readings takes longer but yields a more accurate calibration result by

reducing the noise level.

Two commands can be used to perform offset calibration. SFOCAL is a self offset calibration that internally sets

the input to mid-scale using the SYS_MON[2:0] = 001 setting and takes a measurement of the offset. SYOCAL is

a system offset calibration where the user must input a null voltage to calibrate the system offset. After either

command is issued, the OFC register is updated.

After an offset calibration is performed, the device starts a new conversion and DRDY falls to indicate a new

conversion has completed.

9.3.12.2 Gain Calibration

The full-scale (gain) calibration word is 16 bits consisting of two 8-bit registers, as shown in the two registers

starting with gain calibration register 1. The gain calibration value is straight binary, normalized to a unity-gain

correction factor at a register value equal to 4000h. 表 11 shows register values for selected gain factors. Do not

exceed the PGA input range limits during gain calibration.

表 11. Gain Calibration Register Values

FSC REGISTER VALUE

GAIN FACTOR

4333h

4000h

3CCCh

1.05

1.00

0.95

All gains of the ADS114S0xB are factory trimmed to meet the gain error specified in the Electrical Characteristics

table at T_A= 25°C. When the gain drift of the devices over temperature is very low, there is typically no need for

self gain calibration.

The SYGCAL command initiates a system gain calibration, where the user sets the input to full-scale to remove

gain error. After the SYGCAL is issued, the FSC register is updated. As with the offset calibration, the

CAL_SAMP[1:0] bits determine the number of samples used for a gain calibration.

As with an offset calibration, the device starts a new conversion after a gain calibration and DRDY falls to

indicate a new conversion has completed.

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9.4 Device Functional Modes

The device operates in three different modes: power-down mode, standby mode, and conversion mode. 图 67

shows a flow chart of the different operating modes and how the device transitions from one mode to another.

Power-On Reset or

Power-down

RESET pin high or

Mode⁽²⁾

RESET command?⁽¹⁾

No

Reset device to

default settings

WAKEUP

Command?

Yes

Standby

Mode

Complete current

conversion⁽⁴⁾

No

START/SYNC

rising edge or START

Command?

Yes

START/SYNC

pin low or STOP

Command?

No

Conversion

Mode

Start new

conversion

1 = Single-Shot

conversion mode

0 = Continuous

conversion mode

Conversion

mode selection⁽³⁾

(1) Any reset (power-on, command, or pin), immediately resets the device.

(2) A POWERDOWN command aborts an ongoing conversion and immediately puts the device into power-down mode.

(3) The conversion mode is selected with the MODE bit in the data rate register.

(4) The rising edge of the START/SYNC pin or the START command starts a new conversion without completing the

current conversion.

图 67. Operating Flow Chart

9.4.1 Reset

The ADS114S0xB is reset in one of three ways:

•

Power-on reset

RESET pin

RESET command

When a reset occurs, the configuration registers reset to default values and the device enters standby mode. The

device then waits for the rising edge of the START/SYNC pin or a START command to enter conversion mode. If

the device had been using an external clock, the reset sets the device to use the internal oscillator as a default

configuration. See the Timing Requirements table for reset timing information.

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Device Functional Modes (接下页)

9.4.1.1 Power-On Reset

The ADS114S0xB incorporates a power-on reset circuit that holds the device in reset until all supplies reach

approximately 1.65 V. The power-on reset also ensures that the device starts operating in a known state in case

a brown-out event occurs, when the supplies have dipped below the minimum operating voltages. When the

device completes a POR sequence, the FL_POR flag in the status register is set high to indicate that a POR has

occurred.

Begin communications with the device 2.2 ms after the power supplies reach minimum operating voltages. The

only exception is polling the status register for the RDY bit. If the user polls the RDY bit, then use an SCLK rate

of half the maximum-specified SCLK rate to get a proper reading when the device is making internal

configurations. This 2.2-ms POR time is required for the internal oscillator to start up and the device to properly

set internal configurations. After the internal configurations are set, the device sets the RDY bit in the device

status register (01h). When this bit is set to 0, user configurations can be programmed into the device. 图 68

shows the power-on reset timing sequence for the device.

V_POR

DVDD, IOVDD

V_POR

All supplies reach

minimum operating voltage

AVDD - AVSS

Internal

Oscillator Startup

Internal

Configuration

Standby

Mode

FL_POR bit of

STATUS register is set to 1

RDY bit of

STATUS register is set to 0

2.2 ms

If polling for RDY during this period, SCLK

must be less than half maximum rate

图 68. Power-On Reset Timing Sequence

9.4.1.2 RESET Pin

Reset the ADC by taking the RESET pin low for a minimum of 4 · t_CLK·cycles, and then returning the pin high.

After the rising edge of the RESET pin, a delay time of t_d(RSSC)is required before sending the first serial interface

command or starting a conversion. See the Timing Requirements table for reset timing information.

9.4.1.3 Reset by Command

Reset the ADC by using the RESET command (06h or 07h). The command is decoded on the seventh SCLK

falling edge. After sending the RESET command, a delay time of t_d(RSSC)is required before sending the first serial

interface command or starting a conversion. See the Timing Requirements table for reset timing information.

9.4.2 Power-Down Mode

Power-down mode is entered by sending the POWERDOWN command. In this mode, all analog and digital

circuitry is powered down for lowest power consumption regardless of the register settings. Only the internal

voltage reference can be configured to stay on during power-down mode in case a faster start-up time is

required. All register values retain the current settings during power-down mode. The configuration registers can

be read and written in power-down mode. A WAKEUP command must be issued in order to exit power-down

mode and to enter standby mode.

When the POWERDOWN command is issued, the device enters power-down mode 2 · t_CLKafter the seventh

SCLK falling edge of the command. For lowest power consumption (on DVDD and IOVDD), stop the external

clock when in power-down mode. TI recommends selecting the internal oscillator before sending the

POWERDOWN command to avoid issues with the command decoding.

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Device Functional Modes (接下页)

To release the device from POWERDOWN, issue the WAKEUP command to enter standby mode. The device

then waits for the rising edge of the START/SYNC pin or a START command to go into conversion mode.

When in power-down mode, the device responds to the RREG, RDATA, and WAKEUP commands. The WREG

and RESET commands can also be sent, but are ignored until a WAKEUP command is sent and the internal

oscillator resumes operation.

9.4.3 Standby Mode

The device powers up in standby mode and automatically enters this mode whenever there is no ongoing

conversion. When the STOP command is sent (or the START/SYNC pin is taken low) in continuous conversion

mode, or when a conversion completes in single-shot conversion mode, the device enters standby mode.

Standby mode offers several different options and features to lower the power consumption:

•

The PGA can be powered down by setting PGA_EN[1:0] to 00 in the gain setting register (03h).

The internal voltage reference can be powered down by setting REFCON[1:0] to 00 in the reference control

register (05h). This setting also turns off the IDACs.

•

The digital filter is held in reset state.

The clock to the modulator and digital core is gated to decrease dynamic switching losses.

If powered down in standby mode, the PGA and internal reference can require extra time to power up. Extra

delay may be required between power up of the PGA or the internal reference, and the start of conversions. In

particular, the reference power up time is dependent on the capacitance between REFOUT and REFCOM.

Calibration commands are not decoded when the device is in standby mode.

9.4.4 Conversion Modes

The ADS114S0xB offers two conversion modes: continuous conversion and single-shot conversion mode.

Continuous-conversion mode converts indefinitely until stopped by the user. Single-shot conversion mode

performs one conversion after the START/SYNC pin is taken high or after the START command is sent. Use the

MODE bit in the data rate register (04h) to program the conversion mode. 图 69 shows how the START/SYNC

pin and the START command are used to control ADC conversions.

(2)

(1)

(2)

DRDY

START/SYNC Pin

SCLK

START

Command

START⁽³⁾

STOP

DIN

Conversion Mode

Standby Mode

(1) DRDY rises at the first SCLK rising edge or the rising edge of the START/SYNC pin.

(2) START and STOP commands take effect 2 · t_CLKafter the seventh SCLK falling edge. The conversion starts 2 · t_CLK

after the START/SYNC rising edge.

(3) To synchronize a conversion, the STOP command must be issued prior to the START command. STOP and START

commands can be issued without a delay between the commands.

图 69. Conversion Start and Stop Timing

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Device Functional Modes (接下页)

ADC conversions are controlled by the START/SYNC pin or by serial commands. For the device to start

converting in continuous conversion or single-shot conversion mode, a START command must be sent or the

START/SYNC pin must be taken high. If using commands to control conversions, keep the START/SYNC pin low

to avoid possible contentions between the START/SYNC pin and commands.

Conversions can be synchronized to perform a conversion at a particular time. To synchronize the conversion

with the START/SYNC pin, take the pin low. The rising edge of the START/SYNC pin starts a new conversion.

Similarly, a conversion can be synchronized using the START command. If the device is in standby mode, issue

a START command. If the device is in conversion mode, issue a STOP command followed by a START

command. The STOP and START commands can be consecutive. A new conversion starts on the seventh

SCLK falling edge of the START command.

9.4.4.1 Continuous Conversion Mode

The device is configured for continuous conversion mode by setting the MODE bit to 0 in the data rate register

(04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start

converting continuously. When controlling the device with commands, hold the START/SYNC pin low. Taking the

START/SYNC pin low or sending the STOP command stops the device from converting after the currently

ongoing conversion completes, indicated by the falling edge of DRDY. The device enters standby mode

thereafter.

For information on the exact timing of continuous conversion mode data, see 表 7.

9.4.4.2 Single-Shot Conversion Mode

The device is configured for single-shot conversion mode by setting the MODE bit to 1 in the data rate register

(04h). A START command must be sent or the START/SYNC pin must be taken high for the device to start a

single conversion. After the conversion completes, the device enters standby mode again. To start a new

conversion, the START command must be sent again or the START/SYNC pin must be taken low and then high

again.

For information on the exact timing of single-shot conversion mode data, see 表 7.

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9.5 Programming

9.5.1 Serial Interface

The ADC has an SPI-compatible, bidirectional serial interface that is used to read the conversion data as well as

to configure and control the ADC. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The serial interface

consists of five control lines: CS, SCLK, DIN, DOUT/DRDY, and DRDY but can be used with only four or even

three control signals. If the ADS114S08B or ADS114S06B is the only device connected to the SPI bus, then the

CS input can be tied low so that only SCLK, DIN, and DOUT/DRDY are required to communicate with the device.

9.5.1.1 Chip Select (CS)

The CS pin is an active low input that enables the ADC serial interface for communication and is useful when

multiple devices share the same serial bus. CS must be low during the entire data transaction. When CS is high,

the serial interface is reset, SCLK input activity is ignored (blocking input commands), and the DOUT/DRDY

output enters a high-impedance state. ADC conversions are not affected by the state of CS. In situations where

multiple devices are present on the bus, the dedicated DRDY pin can provide an uninterrupted monitor of the

conversion status and is not affected by CS. If the serial bus is not shared with another peripheral, CS can be

tied to DGND to permanently enable the ADC interface and DOUT/DRDY can be used to indicate conversion

status. These changes reduce the serial interface from five I/Os to three I/Os.

9.5.1.2 Serial Clock (SCLK)

The serial interface clock is a noise-filtered, Schmidt-triggered input used to clock data into and out of the ADC.

Input data to the ADC are latched on the falling SCLK edge and output data from the ADC are updated on the

rising SCLK edge. Return SCLK low after the data sequence is complete. Even though the SCLK input has

hysteresis, keep SCLK as clean as possible to prevent unintentional SCLK transitions. Avoid ringing and voltage

overshoot on the SCLK input. Place a series termination resistor at the SCLK drive pin to help reduce ringing.

9.5.1.3 Serial Data Input (DIN)

The serial data input pin (DIN) is used with SCLK to send data (commands and register data) to the device. The

device latches data on DIN on the SCLK falling edge. The device never drives the DIN pin. During data

readback, when no command is intended, keep DIN low.

9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin is a dual-function output. The pin functions as the digital data output and the ADC data-

ready indication.

First, this pin is used with SCLK to read conversion and register data from the device. Conversion or register

data are shifted out on DOUT/DRDY on the SCLK rising edge. DOUT/DRDY goes to a high-impedance state

when CS is high.

Second, the DOUT/DRDY pin indicates availability of new conversion data. DOUT/DRDY transitions low at the

same time that the DRDY pin goes low to indicate new conversion data are available. Both signals can be used

to detect if new data are ready. However, because DOUT/DRDY is disabled when CS is high, use the dedicated

DRDY pin when monitoring conversions on multiple devices on the SPI bus.

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Programming (接下页)

9.5.1.5 Data Ready (DRDY)

The DRDY pin is an output that transitions low to indicate when conversion data are ready for retrieval. Initially,

DRDY is high at power-on. When converting, the state of DRDY depends on whether the conversion data are

retrieved or not. In continuous conversion mode after DRDY goes low, DRDY is driven high on the first SCLK

rising edge. If data are not read, DRDY remains low and then pulses high 24 · t_CLKbefore the next DRDY falling

edge. The data must be retrieved before the next DRDY update, otherwise the data are overwritten by new data

and any previous data are lost. 图 70 shows the DRDY operation without data retrieval. 图 71 shows the DRDY

operation with data retrieval after each conversion completes.

DRDY

START/SYNC Pin

SCLK

START

Command

DIN

START

(1) DRDY returns high with the rising edge of the first SCLK after a data ready indication.

图 70. DRDY Operation Without Data Retrieval

DRDY

START/SYNC

SCLK

START

Command

START⁽³⁾

RDATA

DIN

Don‘t

Care

Don‘t

Care

DOUT/DRDY

Conversion

Data 1

Conversion

Data 2

(1) DRDY returns high with the rising edge of the first SCLK after a data ready indication.

图 71. DRDY Operation With Data Retrieval

9.5.1.6 Timeout

The ADS114S0xB offers a serial interface timeout feature that is used to recover communication when a serial

interface transmission is interrupted. This feature is especially useful in applications where CS is permanently

tied low and is not used to frame a communication sequence. The SPI interface resets when no valid 8 bits are

received within 2¹⁵· t_CLK. The timeout feature is enabled by setting the TIMEOUT bit to 1 in the system control

register (09h).

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Programming (接下页)

9.5.2 Data Format

The devices provide 16 bits of data in binary twos complement format. 公式 11 calculates the size of one code

(LSB).

1 LSB = (2 · V_REF/ Gain) / 2¹⁶= +FS / 2¹⁵

(11)

A positive full-scale input [V_IN≥ (+FS – 1 LSB) = (V_REF/ Gain – 1 LSB)] produces an output code of 7FFFh and a

negative full-scale input (V_IN≤ –FS = –V_REF/ Gain) produces an output code of 8000h. The output clips at these

codes for signals that exceed full-scale.

表 12 summarizes the ideal output codes for different input signals.

表 12. Ideal Output Code vs Input Signal

INPUT SIGNAL,

V_IN= V_AINP– V_AINN

≥ FS (2¹⁵– 1) / 2¹⁵

FS / 2¹⁵

IDEAL OUTPUT CODE⁽¹⁾

7FFFh

0001h

0000h

FFFFh

8000h

0

–FS / 2¹⁵

≤ –FS

(1) Excludes the effects of noise, INL, offset, and gain errors.

图 72 shows the mapping of the analog input signal to the output codes.

7FFFh

7FFEh

0001h

0000h

FFFFh

8001h

8000h

¼

-FS

0

FS

Input Voltage (V_IN

)

2¹⁵- 1

FS

2¹⁵

图 72. Code Transition Diagram

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9.5.3 Commands

Commands are used to control the ADC, access the configuration registers, and retrieve data. Many of the

commands are stand-alone (that is, single-byte). The register write and register read commands, however, are

multibyte, consisting of two command bytes plus the register data byte or bytes. 表 13 lists the commands.

表 13. Command Definitions

FIRST

COMMAND BYTE

SECOND

COMMAND BYTE

COMMAND

DESCRIPTION

Control Commands

NOP

No operation

0000 0000 (00h)

—

WAKEUP

Wake-up from power-down mode

Enter power-down mode

Reset the device

0000 001x (02h, 03h)⁽¹⁾

0000 010x (04h, 05h)⁽¹⁾

0000 011x (06h, 07h)⁽¹⁾

0000 100x (08h, 09h)⁽¹⁾

0000 101x (0Ah, 0Bh)⁽¹⁾

POWERDOWN

RESET

START

Start conversions

STOP

Stop conversions

Calibration Commands

SYOCAL

System offset calibration

System gain calibration

Self offset calibration

0001 0110 (16h)

0001 0111 (17h)

0001 1001 (19h)

—

SYGCAL

SFOCAL

Data Read Command

RDATA

Read data

0001 001x (12h / 13h)⁽¹⁾

—

Register Read and Write Commands

RREG

WREG

Read nnnnn registers starting at address rrrrr

Write nnnnn registers starting at address rrrrr

001r rrrr⁽²⁾

010r rrrr⁽²⁾

000n nnnn⁽³⁾

(1) x = don't care.

(2) r rrrr = starting register address.

(3) n nnnn = number of registers to read or write – 1.

Commands can be sent at any time, either during a conversion or when conversions are stopped. However, if

register read or write commands are in progress when conversion data are ready, the ADC blocks loading of

conversion data to the output shift register. The CS input pin can be taken high between commands; or held low

between consecutive commands. CS must stay low for the entire command sequence. Complete the command,

or terminate the command before completion by taking CS high. Only send commands listed in 表 13.

9.5.3.1 NOP

NOP is a no-operation command. The NOP command is used to clock out data without clocking in a command.

9.5.3.2 WAKEUP

Issue the WAKEUP command to exit power-down mode and to place the device into standby mode.

When running off the external clock, the external clock must be running before sending the WAKEUP command,

otherwise the command is not decoded.

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9.5.3.3 POWERDOWN

Sending the POWERDOWN command aborts a currently ongoing conversion and puts the device into power-

down mode. The device goes into power-down mode 2 · t_CLKafter the seventh SCLK falling edge of the

command.

For lowest power consumption on DVDD and IOVDD, stop the external clock when in power-down mode. The

device does not gate the external clock. When running off the external clock, provide at a minimum two

additional t_CLKs after the POWERDOWN command is issued, otherwise the device does not enter power-down

mode. Alternatively, select the internal oscillator before sending the POWERDOWN command to avoid any

issues with decoding of the POWERDOWN and WAKEUP commands.

During power-down mode, the only commands that are available are RREG, RDATA, and WAKEUP.

9.5.3.4 RESET

The RESET command resets the digital filter and sets all configuration register values to default settings. A

RESET command also puts the device into standby mode. When in standby mode, the device waits for a rising

edge on the START/SYNC pin or a START command to resume conversions. After sending the RESET

command, a delay time of t_d(RSSC)is required before sending the first serial interface command or starting a

conversion. See the Timing Requirements table for reset timing information.

If the device had been using an external clock, the reset sets the device to use the internal oscillator as a default

configuration.

9.5.3.5 START

When the device is configured for continuous conversion mode, issue the START command for the device to

start converting. Every time a conversion completes, the device automatically starts a new conversion until the

STOP command is sent.

In single-shot conversion mode, the START command is used to start a single conversion. After the conversion

completes, the device enters standby mode.

Tie the START/SYNC pin low when the device is controlled through the START and STOP commands. The

START command is not decoded if the START/SYNC pin is high. If the device is already in conversion mode, the

START command has no effect.

9.5.3.6 STOP

The STOP command is used in continuous conversion mode to stop the device from converting. The current

conversion is allowed to complete. After DRDY transitions low, the device enters standby mode. The STOP

command has no effect in single-shot conversion mode.

Hold the START/SYNC pin low when the device is controlled through START and STOP commands.

9.5.3.7 SYOCAL

The SYOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be

externally shorted to a voltage within the input range, ideally near the mid-supply voltage of (AVDD + AVSS) / 2.

The OFC registers are updated when the command completes. Calibration commands must be issued in

conversion mode.

9.5.3.8 SYGCAL

The SYGCAL command initiates the system gain calibration. For a system gain calibration, the input must be

externally set to full-scale. The FSC registers are updated after this operation. Calibration commands must be

issued in conversion mode.

9.5.3.9 SFOCAL

The SFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply

and performs the calibration. The OFC registers are updated after this operation. Calibration commands must be

issued in conversion mode.

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9.5.3.10 RDATA

Read conversion data from the device with the RDATA command at any time. 图 73 shows the read data

sequence. The MSB of the conversion data is output on the first SCLK rising edge after the command. An

RDATA command must be sent for each read operation. The ADC does not respond to commands until the read

operation is complete, or terminated by taking CS high. New data indicated by the DRDY and DOUT/DRDY will

not corrupt a read of conversion data with RDATA.

After all bytes are read, the data-byte sequence is repeated by continuing SCLK.

(1)

CS

9

1

17

SCLK

DIN

RDATA

HI-Z

DOUT/DRDY

(2)

Don‘t Care

Data 1

Data 2

ADC Data Bytes

(1) CS can be tied low. If CS is low, DOUT/DRDY asserts low with DRDY.

(2) DOUT/DRDY is driven low with DRDY. If a read operation occurs after the DRDY falling edge, then DOUT/DRDY can

be high or low.

图 73. Read Data Sequence

9.5.3.11 RREG

Use the RREG command to read the device register data. Read the register data one register at a time, or read

a block of register data. The starting register address can be any register in the register map. The RREG

command consists of two bytes. The first byte specifies the starting register address: 001r rrrr, where r rrrr is the

starting register address. The second command byte is the number of registers to read (minus 1): 000n nnnn,

where n nnnn is the number of registers to read minus 1.

After the read command is sent, the ADC responds with one or more register data bytes, most significant bit

(MSB) first. If the byte count exceeds the last register address, the ADC begins to output zero data. During the

register read operation, any conversion data that becomes available is not loaded to the output shift register to

avoid data contention. However, the conversion data can be retrieved later by the RDATA command. After the

register read command has started, further commands are blocked until one of the following conditions are met:

•

The read operation is completed

The read operation is terminated by taking CS high

The read operation is terminated by a serial interface timeout

The ADC is reset by toggling the RESET pin

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图 74 shows a two-register read operation example. As shown, the commands required to read data from two

registers starting at register REF (address = 05h) are: command byte 1 = 25h and command byte 2 = 01h. Keep

DIN low after the two command bytes are sent.

(1)

CS

1

9

17

25

SCLK

DOUT/DRDY

DON‘T CARE

REG DATA 1

REG DATA 2

DIN

0010 0101

0000 0001

(1) CS can be set high or kept low between commands. If kept low, the command must be completed.

图 74. Read Register Sequence

9.5.3.12 WREG

Use the WREG command to write the device register data. The register data are written one register at a time or

as a block of register data. The starting register address is any register in the register map.

The WREG command consists of two bytes. The first byte specifies the starting register address: 010r rrrr, where

r rrrr is the starting register address The second command byte is the number of registers to write (minus 1):

000n nnnn, where n nnnn is the number of registers to write minus 1. The following byte (or bytes) is the register

data, most significant bit (MSB) first. If the byte count exceeds the last register address, the ADC ignores the

data. After the register write command has started, further commands are blocked until one of the following

conditions are met:

•

The write operation is completed

The write operation is terminated by taking CS high

The write operation is terminated by a serial interface timeout

The ADC is reset by toggling the RESET pin

图 75 shows a two-register write operation example. As shown, the required commands to write data to two

registers starting at register REF (address = 05h) are: command byte 1 = 45h and command byte 2 = 01h.

(1)

CS

1

9

17

25

SCLK

DOUT/DRDY

DIN

DON‘T CARE

0100 0101

0000 0001

REG DATA 1

REG DATA 2

(1) CS can be set high or kept low between commands. If kept low, the command must be completed.

图 75. Write Register Sequence

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Writing new data to certain configuration registers resets the digital filter. Resetting the digital filter clears the

output shift register and if a conversion is in progress, a new conversion starts. Writing to the following registers

triggers a new conversion:

•

Channel configuration register (02h)

Gain setting register (03h)

Data rate register (04h)

Reference control register (05h), bits [5:0]

Excitation current register 1 (06h), bits [3:0]

Excitation current register 2 (07h)

System control register (09h), bits [7:5]

When the device is configured with WREG, the first data ready indication occurs after the new conversion

completes with the configuration settings. The previous conversion data are cleared at restart; therefore read the

previous data before the register write operation. Again, a WREG to these registers only starts a new conversion

if a conversion is in progress. If the device is in standby mode, the device sets the configuration according to the

WREG data, but does not start a conversion until the START/SYNC pin is taken high or a START command is

issued.

9.5.4 Interfacing with Multiple Devices

When connecting multiple devices to a single SPI bus, SCLK, DIN, and DOUT/DRDY can be safely shared by

using a dedicated chip-select (CS) line for each SPI-enabled device. When CS transitions high for the respective

device, DOUT/DRDY enters a tri-state mode. Therefore, DOUT/DRDY cannot be used to indicate when new data

are available if CS is high. Only the dedicated DRDY pin indicates that new data are available because the

DRDY pin is actively driven even when CS is high.

In some cases, the DRDY pin cannot be interfaced to the microcontroller. This scenario can occur if there are

insufficient GPIO channels available on the microcontroller or if the serial interface must be galvanically isolated

and thus the amount of channels must be limited. In order to evaluate when a new conversion of one of the

devices is ready, the microcontroller can periodically drop CS to the respective device and poll the state of the

DOUT/DRDY pin.

When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives

low, new data are available. If the DOUT/DRDY line drives high, no new data are available. This procedure

requires that DOUT/DRDY is forced high after reading each conversion result and before taking CS high. To

make sure DOUT/DRDY is taken high, send a RREG command to read a register where the least significant bit

(LSB) is 1.

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9.6 Register Map

9.6.1 Configuration Registers

The ADS114S0xB register map consists of 18, 8-bit registers. These registers are used to configure and control

the device to the desired mode of operation. Access the registers through the serial interface by using the RREG

and WREG register commands. As shown in the Default column of 表 14, the registers default to the initial

settings after power-on or reset.

Data can be written as a block to multiple registers using a single WREG command. If data are written as a

block, the data of certain registers take effect immediately when data are shifted in. Writing new data to certain

registers results in a restart of conversions that are in progress. The registers that result in a conversion restart

are discussed in the WREG section.

表 14. Configuration Register Map

ADDR REGISTER

DEFAULT

xxh

BIT 7

BIT 6

BIT 5

RESERVED

0

BIT 4

BIT 3

BIT 2

BIT 1

DEV_ID[2:0]

0

BIT 0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

ID

STATUS

INPMUX

PGA

80h

01h

00h

14h

10h

00h

FFh

00h

10h

00h

40h

00h

FL_POR

RDY

0

FL_REF

MUXP[3:0]

MUXN[3:0]

GAIN[2:0]

DR[3:0]

0

MODE

REFP_BUF

0

PGA_EN[1:0]

DATARATE

REF

CLK

FL_REF_EN

0

1

REFN_BUF

0

REFSEL[1:0]

REFCON[1:0]

IDACMAG

IDACMUX

VBIAS

IMAG[3:0]

I2MUX[3:0]

I1MUX[3:0]

0

VB_AINC

VB_AIN5

VB_AIN4

VB_AIN3

VB_AIN2

TIMEOUT

VB_AIN1

0

VB_AIN0

0

SYS

SYS_MON[2:0]

CAL_SAMP[1:0]

RESERVED

OFCAL0

OFCAL1

RESERVED

FSCAL0

FSCAL1

GPIODAT

GPIOCON

RESERVED

OFC[7:0]

OFC[15:8]

RESERVED

FSC[7:0]

FSC[15:8]

DIR[3:0]

DAT[3:0]

CON[3:0]

0

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9.6.2 Register Descriptions

表 15 lists the access codes for the ADS114S0xB registers.

表 15. ADS114S0xB Access Type Codes

Access Type

Code

R

Description

R

Read

R-W

W

R/W

W

Read or Write

Write

-n

Value after reset or the default value

9.6.2.1 Device ID Register (address = 00h) [reset = xxh]

图 76. Device ID (ID) Register

7

6

5

4

3

2

1

0

RESERVED

R-xxh

DEV_ID[2:0]

R-xh

表 16. Device ID (ID) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

RESERVED

R

xxh

Reserved

Values are subject to change without notice

Device identifier

2:0

DEV_ID[2:0]

R

xh

Identifies the model of the device.

000 : Reserved

001 : Reserved

010 : Reserved

011 : Reserved

100 : ADS114S08B (12 channels, 16 bits)

101 : ADS114S06B (6 channels, 16 bits)

110 : Reserved

111 : Reserved

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9.6.2.2 Device Status Register (address = 01h) [reset = 80h]

图 77. Device Status (STATUS) Register

7

6

5

0

4

0

3

0

2

0

1

0

FL_POR

R/W-1h

RDY

R-0h

FL_REF

R-0h

表 17. Device Status (STATUS) Register Field Descriptions

Bit

Field

Type

Reset

Description

POR flag

7

FL_POR

R/W

1h

Indicates a power-on reset (POR) event has occurred.

0 : Register has been cleared and no POR event has occurred

1 : POR event occurred and has not been cleared. Flag must be cleared by

user register write (default).

6

RDY

R

0h

Device ready flag

Indicates the device has started up and is ready for communication.

0 : ADC ready for communication (default)

1 : ADC not ready

5:1

0

RESERVED

FL_REF

R

00h

0h

Reserved

Always write 00h

External reference voltage monitor flag

Indicates the selected external reference voltage is lower than 0.3 V. Can

be used to indicate

a

missing external reference voltage.

The reference monitor is enabled with the FL_REF_EN bit in the reference

control register (05h).

0 : Differential reference voltage ≥ 0.3 V (default)

1 : Differential reference voltage < 0.3 V

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9.6.2.3 Input Multiplexer Register (address = 02h) [reset = 01h]

图 78. Input Multiplexer (INPMUX) Register

7

6

5

4

3

2

1

0

MUXP[3:0]

R/W-0h

MUXN[3:0]

R/W-1h

表 18. Input Multiplexer (INPMUX) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

MUXP[3:0]

R/W

0h

Positive ADC input selection

Selects the ADC positive input channel.

0000 : AIN0 (default)

0001 : AIN1

0010 : AIN2

0011 : AIN3

0100 : AIN4

0101 : AIN5

0110 : AIN6 (ADS114S08B only)

0111 : AIN7 (ADS114S08B only)

1000 : AIN8 (ADS114S08B only)

1001 : AIN9 (ADS114S08B only)

1010 : AIN10 (ADS114S08B only)

1011 : AIN11 (ADS114S08B only)

1100 : AINCOM

1101 : Reserved

1110 : Reserved

1111 : Reserved

3:0

MUXN[3:0]

R/W

1h

Negative ADC input selection

Selects the ADC negative input channel.

0000 : AIN0

0001 : AIN1 (default)

0010 : AIN2

0011 : AIN3

0100 : AIN4

0101 : AIN5

0110 : AIN6 (ADS114S08B only)

0111 : AIN7 (ADS114S08B only)

1000 : AIN8 (ADS114S08B only)

1001 : AIN9 (ADS114S08B only)

1010 : AIN10 (ADS114S08B only)

1011 : AIN11 (ADS114S08B only)

1100 : AINCOM

1101 : Reserved

1110 : Reserved

1111 : Reserved

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9.6.2.4 Gain Setting Register (address = 03h) [reset = 00h]

图 79. Gain Setting (PGA) Register

7

0

6

0

5

0

4

3

2

1

0

PGA_EN[1:0]

R/W-0h

GAIN[2:0]

R/W-0h

表 19. Gain Setting (PGA) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

RESERVED

R/W

0h

Reserved

Always write 0h

PGA enable

4:3

2:0

PGA_EN[1:0]

R/W

0h

Enables or bypasses the PGA.

00 : PGA is powered down and bypassed. Enables single-ended

measurements with unipolar supply (Set gain = 1⁽¹⁾) (default)

01 : PGA enabled (gain = 1 to 128)

10 : Reserved

11 : Reserved

GAIN[2:0]

0h

PGA gain selection

Configures the PGA gain.

000 : 1 (default)

001 : 2

010 : 4

011 : 8

100 : 16

101 : 32

110 : 64

111 : 128

(1) When bypassing the PGA, the user must also set GAIN[2:0] to 000.

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9.6.2.5 Data Rate Register (address = 04h) [reset = 14h]

图 80. Data Rate (DATARATE) Register

7

0

6

5

4

1

3

2

1

0

CLK

MODE

R/W-0h

DR[3:0]

R/W-4h

R/W-0h

R/W-1h

表 20. Data Rate (DATARATE) Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0h

Reserved

Always write 0h

Clock source selection

6

5

CLK

R/W

0h

Configures the clock source to use either the internal oscillator or an

external clock.

0 : Internal 4.096-MHz oscillator (default)

1 : External clock

MODE

Conversion mode selection

Configures the ADC for either continuous conversion or single-shot

conversion mode.

0 : Continuous conversion mode (default)

1 : Single-shot conversion mode

4

RESERVED

DR[3:0]

R/W

1h

4h

Reserved

Always write 1h

3:0

Data rate selection

Configures the output data rate⁽¹⁾

0000 : 2.5 SPS

.

0001 : 5 SPS

0010 : 10 SPS

0011 : 16.6 SPS

0100 : 20 SPS (default)

0101 : 50SPS

0110 : 60 SPS

0111 : 100 SPS

1000 : 200 SPS

1001 : 400 SPS

1010 : 800 SPS

1011 : 1000 SPS

1100 : 2000 SPS

1101 : 4000 SPS

1110 : 4000 SPS

1111 : Reserved

(1) Data rates of 60 Hz or less can offer line-cycle rejection; see the 50-Hz and 60-Hz Line Cycle Rejection section for more information.

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9.6.2.6 Reference Control Register (address = 05h) [reset = 10h]

图 81. Reference Control (REF) Register

7

0

6

5

4

3

2

1

0

FL_REF_EN

R/W-0h

REFP_BUF

R/W-0h

REFN_BUF

R/W-1h

REFSEL[1:0]

R/W-0h

REFCON[1:0]

R/W-0h

表 21. Reference Control (REF) Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0h

Reserved

Always write 0h

6

5

FL_REF_EN

REFP_BUF

R/W

0h

External reference monitor enable

Enables the external reference monitor.

0 : Disabled (default)

1 : Enabled

Positive reference buffer bypass

Disables the positive reference buffer. Recommended when V_(REFPx)is

close to AVDD.

0 : Positive reference buffer enabled (default)

1 : Positive reference buffer bypassed

4

REFN_BUF

R/W

1h

0h

Negative reference buffer bypass

Disables the negative reference buffer. Recommended when V_(REFNx)is

close to AVSS.

0 : Negative reference buffer enabled

1 : Negative reference buffer bypassed (default)

3:2

REFSEL[1:0]

Reference input selection

Selects the reference input source for the ADC.

00 : REFP0, REFN0 (default)

01 : REFP1, REFN1

10 : Internal 2.5-V reference⁽¹⁾

11 : Reserved

1:0

REFCON[1:0]

R/W

0h

Internal voltage reference configuration⁽²⁾

Configures the behavior of the internal voltage reference.

00 : Internal reference off (default)

01 : Internal reference on, but powers down in power-down mode

10 : Internal reference is always on, even in power-down mode

11 : Reserved

(1) Disable the reference buffers when the internal reference is selected for measurements.

(2) The internal voltage reference must be turned on to use the IDACs.

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9.6.2.7 Excitation Current Register 1 (address = 06h) [reset = 00h]

图 82. Excitation Current Register 1 (IDACMAG)

7

0

6

0

5

0

4

0

3

2

1

0

IMAG[3:0]

R/W-0h

表 22. Excitation Current Register 1 (IDACMAG) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

RESERVED

R/W

0h

Reserved

Always write 0h

IDAC magnitude selection

3:0

IMAG[3:0]

R/W

0h

Selects the value of the excitation current sources. Sets IDAC1 and IDAC2

to the same value.

0000 : Off (default)

0001 : 10 µA

0010 : 50 µA

0011 : 100 µA

0100 : 250 µA

0101 : 500 µA

0110 : 750 µA

0111 : 1000 µA

1000 : 1500 µA

1001 : 2000 µA

1010–1111 : Off

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9.6.2.8 Excitation Current Register 2 (address = 07h) [reset = FFh]

图 83. Excitation Current Register 2 (IDACMUX)

7

6

5

4

3

2

1

0

I2MUX[3:0]

R/W-Fh

I1MUX[3:0]

R/W-Fh

表 23. Excitation Current Register 2 (IDACMUX) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

I2MUX[3:0]

R/W

Fh

IDAC2 output channel selection

Selects the output channel for IDAC2.

0000 : AIN0

0001 : AIN1

0010 : AIN2

0011 : AIN3

0100 : AIN4

0101 : AIN5

0110 : AIN6 (ADS114S08B), REFP1 (ADS114S06B)

0111 : AIN7 (ADS114S08B), REFN1 (ADS114S06B)

1000 : AIN8 (ADS114S08B only)

1001 : AIN9 (ADS114S08B only)

1010 : AIN10 (ADS114S08B only)

1011 : AIN11 (ADS114S08B only)

1100 : AINCOM

1101–1111 : Disconnected (default)

3:0

I1MUX[3:0]

R/W

Fh

IDAC1 output channel selection

Selects the output channel for IDAC1.

0000 : AIN0

0001 : AIN1

0010 : AIN2

0011 : AIN3

0100 : AIN4

0101 : AIN5

0110 : AIN6 (ADS114S08B only), REFP1 (ADS114S06B)

0111 : AIN7 (ADS114S08B only), REFN1 (ADS114S06B)

1000 : AIN8 (ADS114S08B only)

1001 : AIN9 (ADS114S08B only)

1010 : AIN10 (ADS114S08B only)

1011 : AIN11 (ADS114S08B only)

1100 : AINCOM

1101–1111 : Disconnected (default)

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9.6.2.9 Sensor Biasing Register (address = 08h) [reset = 00h]

图 84. Sensor Biasing (VBIAS) Register

7

0

6

5

4

3

2

1

0

VB_AINC

R/W-0h

VB_AIN5

R/W-0h

VB_AIN4

R/W-0h

VB_AIN3

R/W-0h

VB_AIN2

R/W-0h

VB_AIN1

R/W-0h

VB_AIN0

R/W-0h

表 24. Sensor Biasing (VBIAS) Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0h

Reserved

Always write 0h

6

5

4

3

2

1

0

VB_AINC

R/W

0h

AINCOM VBIAS selection⁽¹⁾

Enables VBIAS on the AINCOM pin.

0 : VBIAS disconnected from AINCOM (default)

1 : VBIAS connected to AINCOM

AIN5 VBIAS selection⁽¹⁾

VB_AIN5

VB_AIN4

VB_AIN3

VB_AIN2

VB_AIN1

VB_AIN0

Enables VBIAS on the AIN5 pin.

0 : VBIAS disconnected from AIN5 (default)

1 : VBIAS connected to AIN5

AIN4 VBIAS selection⁽¹⁾

Enables VBIAS on the AIN4 pin.

0 : VBIAS disconnected from AIN4 (default)

1 : VBIAS connected to AIN4

AIN3 VBIAS selection⁽¹⁾

Enables VBIAS on the AIN3 pin.

0 : VBIAS disconnected from AIN3 (default)

1 : VBIAS connected to AIN3

AIN2 VBIAS selection⁽¹⁾

Enables VBIAS on the AIN2 pin.

0 : VBIAS disconnected from AIN2 (default)

1 : VBIAS connected to AIN2

AIN1 VBIAS selection⁽¹⁾

Enables VBIAS on the AIN1 pin.

0 : VBIAS disconnected from AIN1 (default)

1 : VBIAS connected to AIN1

AIN0 VBIAS selection⁽¹⁾

Enables VBIAS on the AIN0 pin.

0 : VBIAS disconnected from AIN0 (default)

1 : VBIAS connected to AIN0

(1) The bias voltage can be selected for multiple analog inputs at the same time.

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9.6.2.10 System Control Register (address = 09h) [reset = 10h]

图 85. System Control (SYS) Register

7

6

5

4

3

2

1

0

SYS_MON[2:0]

R/W-0h

CAL_SAMP[1:0]

R/W-2h

TIMEOUT

R/W-0h

表 25. System Control (SYS) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

SYS_MON[2:0]

R/W

0h

System monitor configuration⁽¹⁾

Enables a set of system monitor measurements using the ADC.

000 : Disabled (default)

001 : PGA inputs shorted to (AVDD + AVSS) / 2 and disconnected from

AINx and the multiplexer; gain set by user

010 : Internal temperature sensor measurement; PGA must be enabled

(PGA_EN[1:0] = 01); gain set by user⁽²⁾

011 : (AVDD – AVSS) / 4 measurement; gain set to 1⁽³⁾

100 : DVDD / 4 measurement; gain set to 1⁽³⁾

101 : Burn-out current sources enabled, 0.2-µA setting

110 : Burn-out current sources enabled, 1-µA setting

111 : Burn-out current sources enabled, 10-µA setting

4:3

CAL_SAMP[1:0]

R/W

2h

Calibration sample size selection

Configures the number of samples averaged for self and system offset and

system gain calibration.

00 : 1 sample

01 : 4 samples

10 : 8 samples (default)

11 : 16 samples

2

TIMEOUT

R/W

0h

SPI timeout enable

Enables the SPI timeout function.

0 : Disabled (default)

1 : Enabled

1:0

RESERVED

Reserved

Always write 0h

(1) With system monitor functions enabled, the AINx multiplexer switches are open for the (AVDD + AVSS) / 2 measurement, the

temperature sensor, and the supply monitors.

(2) When using the internal temperature sensor, gain must be 4 or less to keep the measurement within the PGA input voltage range.

(3) The PGA gain is automatically set to 1 when the supply monitors are enabled, regardless of the setting in GAIN[2:0].

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9.6.2.11 Reserved Register (address = 0Ah) [reset = 00h]

图 86. Reserved Register

7

6

5

4

3

2

1

0

RESERVED

R-00h

表 26. Reserved Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:0

RESERVED

R

00h

Always write 00h

9.6.2.12 Offset Calibration Register 1 (address = 0Bh) [reset = 00h]

图 87. Offset Calibration Register 1 (OFCAL0)

7

6

5

4

3

2

1

0

OFC[7:0]

R/W-00h

表 27. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

OFC[7:0]

R/W

00h

Bits [7:0] of the offset calibration value.

9.6.2.13 Offset Calibration Register 2 (address = 0Ch) [reset = 00h]

图 88. Offset Calibration Register 2 (OFCAL1)

7

6

5

4

3

2

1

0

OFC[15:8]

R/W-00h

表 28. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

OFC[15:8]

R/W

00h

Bits [15:8] of the offset calibration value.

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9.6.2.14 Reserved Register (address = 0Dh) [reset = 00h]

图 89. Reserved Register

7

6

5

4

3

2

1

0

RESERVED

R-00h

表 29. Reserved Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

7:0

RESERVED

R

00h

Always write 00h

9.6.2.15 Gain Calibration Register 1 (address = 0Eh) [reset = 00h]

图 90. Gain Calibration Register 1 (FSCAL0)

7

6

5

4

3

2

1

0

FSC[7:0]

R/W-00h

表 30. Gain Calibration Register 1 (FSCAL0) Field Descriptions

Bit

Field

Type

Reset

Description

7:0

FSC[7:0]

R/W

00h

Bits [7:0] of the gain calibration value.

9.6.2.16 Gain Calibration Register 2 (address = 0Fh) [reset = 40h]

图 91. Gain Calibration Register 2 (FSCAL1)

7

6

5

4

3

2

1

0

FSC[15:8]

R/W-40h

表 31. Gain Calibration Register 2 (FSCAL1) Field Descriptions

Bit

Field

Type

Reset

Description

7:0

FSC[15:8]

R/W

40h

Bits [15:8] of the gain calibration value.

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9.6.2.17 GPIO Data Register (address = 10h) [reset = 00h]

图 92. GPIO Data (GPIODAT) Register

7

6

5

4

3

2

1

0

DIR[3:0]

R/W-0h

DAT[3:0]

R/W-0h

表 32. GPIO Data (GPIODAT) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

DIR[3:0]

R/W

0h

GPIO direction

Configures the selected GPIO as an input or output.

0 : GPIO[x] configured as output (default)

1 : GPIO[x] configured as input

3:0

DAT[3:0]

R/W

0h

GPIO data

Contains the data of the GPIO inputs or outputs.

0 : GPIO[x] is low (default)

1 : GPIO[x] is high

9.6.2.18 GPIO Configuration Register (address = 11h) [reset = 00h]

图 93. GPIO Configuration Register

7

0

6

0

5

0

4

0

3

2

1

0

CON[3:0]

R/W-0h

R-0h

表 33. GPIO Configuration (GPIOCON) Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

RESERVED

R

0h

Reserved

Always write 0h

GPIO pin configuration

3:0

CON[3:0]

R/W

0h

Configures the GPIO[x] pin as an analog input or GPIO. CON[x]

corresponds to the GPIO[x] pin.

0 : GPIO[x] configured as analog input (default)⁽¹⁾

1 : GPIO[x] configured as GPIO

(1) On the ADS114S06B, the GPIO pins default as disabled. Set the CON[3:0] bits to enable the respective GPIO pins.

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10 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ADS114S06B and ADS114S08B are precision, 16-bit, ΔΣ ADCs that offer many integrated features to

simplify the measurement of the most common sensor types (including various types of temperature, flow, and

bridge sensors). Primary considerations when designing an application with the ADS114S0xB include analog

input filtering, establishing an appropriate reference, and setting the absolute input voltage for the internal PGA.

Connecting and configuring the serial interface appropriately is another concern. These considerations are

discussed in the following sections.

10.1.1 Serial Interface Connections

图 94 shows the principle serial interface connections for the ADS114S0xB.

1 mF

24

23

22

21

20

19

18

17

3.3 V

47 ꢀ

GPIO

NC 25

DVDD

IOVDD

DGND

DRDY

16

15

14

13

12

11

10

9

5 V

26

27

28

AVDD

GPIO/IRQ

MISO

0.1 mF

330 nF

AVSS

SCLK

Microcontroller

with SPI

47 ꢀ

REFN0 29

REFP0 30

DOUT/DRDY

SCLK

MOSI

GPIO

REFN1/AIN7 31

REFP1/AIN6 32

DIN

GPIO

DVDD

DVSS

3.3 V

CS

1

2

3

4

5

6

7

8

0.1 mF

图 94. Serial Interface Connections

Most microcontroller SPI peripherals can interface with the ADS114S0xB. The interface operates in SPI mode 1

where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on

SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI

communication protocol employed by the devices are found in the Serial Interface section.

Place 47-Ω resistors in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, and DRDY).

This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care

must be taken to meet all SPI timing requirements because the additional resistors interact with the bus

capacitances present on the digital signal lines.

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Application Information (接下页)

10.1.2 Analog Input Filtering

Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process and

second, to reduce external noise from being a part of the measurement.

As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when

frequency components are present in the input signal that are higher than half the sampling frequency of the

ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the

actual frequency band of interest below half the sampling frequency. Inside a ΔΣ ADC, the input signal is

oversampled at the modulator frequency, f_MODand not at the output data rate. 图 95 shows that the filter

response of the digital filter repeats at multiples of f_MOD. Signals or noise up to a frequency where the filter

response repeats are attenuated to a certain amount by the digital filter depending on the filter architecture. Any

frequency components present in the input signal around the modulator frequency or multiples thereof are not

attenuated and alias back into the band of interest, unless attenuated by an external analog filter.

Magnitude

Sensor

Signal

Unwanted

Signals

Unwanted

Signals

Output

Data Rate

f_MOD/2

f_MOD

Frequency

Magnitude

Digital Filter

Aliasing of

Unwanted Signals

Output

Data Rate

f_MOD/2

f_MOD

Magnitude

External

Antialiasing Filter

Roll-Off

Output

Data Rate

f_MOD/2

f_MOD

图 95. Effect of Aliasing

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Application Information (接下页)

Many sensor signals are inherently band limited; for example, the output of a thermocouple has a limited rate of

change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However,

any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band.

Power line-cycle frequency and harmonics are one common noise source. External noise can also be generated

from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors

and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of

clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the

measurement result.

A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either eliminate aliasing, or to reduce the

effect of aliasing to a level below the noise floor of the sensor. Ideally, any signal beyond f_MOD/ 2 is attenuated to

a level below the noise floor of the ADC. The digital filter of the ADS114S0xB attenuates signals to a certain

degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components are

usually smaller in magnitude than the actual sensor signal. Therefore, using a first-order RC filter with a cutoff

frequency set at the output data rate or 10 times higher is generally a good starting point for a system design.

Internal to the device, prior to the PGA inputs, is an EMI filter; see 图 43. The cutoff frequency of this filter is

approximately 40 MHz and helps reject high-frequency interference.

10.1.3 External Reference and Ratiometric Measurements

The full-scale range of the ADS114S0xB is defined by the reference voltage and the PGA gain

(FSR = ±V_REF/ Gain). An external reference can be used instead of the integrated 2.5-V reference to adapt the

FSR to the specific system needs. An external reference must be used if V_IN> 2.5 V. For example, an external

5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing

between 0 V and 5 V.

The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric

measurement, the same excitation source that is used to excite the sensor is also used to establish the reference

for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite

both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with

the element being measured. The voltage that develops across the reference element is used as the reference

source for the ADC. Because current noise and drift are common to both the sensor measurement and the

reference, these components cancel out in the ADC transfer function. The output code is only a ratio of the

sensor element and the value of the reference resistor. The value of the excitation current source itself is not part

of the ADC transfer function.

The example in the Typical Application section describes a system that uses a ratiometric measurement. One

excitation current source is used to drive a reference resistor and an RTD. The ADC measurement represents a

ratiometric measurement between the RTD value and a known reference resistor value.

10.1.4 Establishing a Proper Input Voltage

The ADS114S0xB can be used to measure various types of input signal configurations: single-ended, pseudo-

differential, and fully-differential signals (which can be either unipolar or bipolar). However, configuring the device

properly for the respective signal type is important.

Signals where the negative analog input is fixed and referenced to analog ground (V_AINN= 0 V) are commonly

called single-ended signals. The input voltage of a single-ended signal consequently varies between 0 V and V_IN.

If the PGA is disabled and bypassed, the input voltage of the ADS114S0xB can be as low as 50 mV below AVSS

and as large as 50 mV above AVDD. Therefore, set the PGA_EN bits to 10 in the gain setting register (03h) to

measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V). Only a gain of 1 is possible

in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal across a load resistor of 100 Ω

referenced to GND is a typical example. The ADS114S0xB can directly measure the signal across the load

resistor using a unipolar supply, the internal 2.5-V reference, and gain = 1 when the PGA is bypassed.

If gain is needed to measure a single-ended signal, the PGA must be enabled. In this case, a bipolar supply is

required for the ADS114S0xB to meet the input voltage requirement of the PGA. Signals where the negative

analog input (AIN_N) is fixed at a voltage other the 0 V are referred to as pseudo-differential signals. The input

voltage of a pseudo-differential signal varies between V_AINNand V_AINN+ V_IN.

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Application Information (接下页)

Fully-differential signals in contrast are defined as signals having a constant common-mode voltage where the

positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.

The ADS114S0xB can measure pseudo-differential and fully-differential signals both with the PGA enabled or

bypassed. However, the PGA must be enabled in order to measure any input with a gain greater than 1. The

input voltage must meet the input and output voltage restrictions of the PGA, as explained in the PGA Input-

Voltage Requirements section when the PGA is enabled. Setting the input voltage at or near (AVSS + AVDD) / 2

in most cases satisfies the PGA input voltage requirements.

Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals

can in general be measured with the ADS114S0xB using a unipolar analog supply (AVSS = 0 V). As mentioned

previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar

supply.

A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply

(such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS114S0xB. A

typical application task is measuring a single-ended, bipolar, ±10-V signal where AIN_Nis fixed at 0 V and AIN_P

swings between –10 V and 10 V. The ADS114S0xB cannot directly measure this signal because the 10-V signal

exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD

= 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS114S0xB. The resistor divider must

divide the voltage down to ≤ ±2.5 V to be able to measure the voltage using the internal 2.5-V reference.

10.1.5 Unused Inputs and Outputs

To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or

connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AVSS is possible

as well, but can yield higher leakage currents than the previously mentioned options. REFN0 is an exception;

leave the REFN0 pin floating when not in use or tie the pin to AVSS.

GPIO pins operate on levels based on the analog supply. Do not float GPIO pins that are configured as digital

inputs. Tie unused GPIO pins that are configured as digital inputs to the appropriate levels, AVDD or AVSS,

including when in power-down mode. Tie unused GPIO output pins to AVSS through a pulldown resistor and set

the output to 0 in the GPIO data register. For unused GPIO pins on the ADS114S06B, leave the GPIOCON

register set to the default register values and connect these GPIO pins in the same manner as for an unused

analog input.

Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital

inputs to the appropriate levels, IOVDD or DGND, even when in power-down mode. Connections for unused

digital inputs are listed below.

•

Tie the CS pin to DGND if CS is not used

Tie the CLK pin to DGND if the internal oscillator is used

Tie the START/SYNC pin to DGND to control conversions by commands

Tie the RESET pin to IOVDD if the RESET pin is not used

If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to IOVDD using a weak

pullup resistor

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Application Information (接下页)

10.1.6 Pseudo Code Example

The following list shows a pseudo code sequence with the required steps to set up the device and the

microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS114S0xB in

continuous conversion mode. The dedicated DRDY pin is used to indicate availability of new conversion data.

Power-up so that all supplies reach minimum operating levels;

Delay for a minimum of 2.2 ms to allow power supplies to settle and power-up reset to complete;

Configure the SPI interface of the microcontroller to SPI mode 1 (CPOL = 0, CPHA =1);

If the CS pin is not tied low permanently, configure the microcontroller GPIO connected to CS as an

output;

Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt

input;

Set CS to the device low;

Delay for a minimum of t_d(CSSC)

Send the RESET command (06h) to make sure the device is properly reset after power-up; //Optional

Delay for a minimum of 4096 · t_CLK

;

Read the status register using the RREG command to check that the RDY bit is 0; //Optional

Clear the FL_POR flag by writing 00h to the status register; //Optional

Write the respective register configuration with the WREG command;

For verification, read back all configuration registers with the RREG command;

Send the START command (08h) to start converting in continuous conversion mode;

Delay for a minimum of t_d(SCCS)

;

Clear CS to high (resets the serial interface);

Loop

{

Wait for DRDY to transition low;

Take CS low;

Delay for a minimum of t_d(CSSC)

;

Send the RDATA command;

Send 16 SCLK rising edges to read out conversion data on DOUT/DRDY;

Delay for a minimum of t_d(SCCS)

;

Clear CS to high;

}

Take CS low;

Delay for a minimum of t_d(CSSC)

Send the STOP command (0Ah) to stop conversions and put the device in standby mode;

;

Delay for a minimum of t_d(SCCS)

;

Clear CS to high;

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10.2 Typical Application

图 96 shows a fault-protected, filtered, 3-wire RTD application circuit with hardware-based, lead-wire

compensation. Two IDAC current sources provide the lead-wire compensation. One IDAC current source

(IDAC1) provides excitation to the RTD element. The ADC reference voltage (pins AIN6 and AIN7) is derived

from the voltage across resistor R_REFsourcing the same IDAC1 current, providing ratiometric cancellation of

current-source drift. The other current source (IDAC2) has the same current setting, providing cancellation of

lead-wire resistance by generating a voltage drop across lead-wire resistance R_LEAD2equal to the voltage drop of

R_LEAD1. Because the R_RTDvoltage is measured differentially at ADC pins AIN1 and AIN2, the voltages across the

lead wire resistance cancel. Resistor R_BIASlevel-shifts the RTD signal to within the ADC specified input range.

The current sources are provided by two additional pins (AIN5 and AIN3) that connect to the RTD through

blocking diodes. The additional pins are used to route the RTD excitation currents around the input filter

resistors, avoiding the voltage drop otherwise caused by the filter resistors R_F1and R_F4. The diodes protect the

ADC inputs in the event of a miswired connection. The input filter resistors limit the input fault currents flowing

into the ADC.

5 V

3.3 V

0.1 mF

330 nF

AVDD

DVDD

IOVDD

AVDD

IDAC1

I_IDAC1

AIN5

(IDAC1)

500 ꢁA

ADS114S08B

C_CM4

R_F4

AIN6

REFOUT

1 mF

(REFP1)

Reference

Mux

2.5-V

Reference

R_REF

C_DIF2

R_F3

AIN7

(REFN1)

REFCOM

C_CM3

Reference

Buffers

3-Wire RTD

R_LEAD1

C_CM2

START/SYNC

RESET

CS

R_F2

AIN1

(AINP)

Serial

Digital

Filter

Input

Mux

16-Bit

ûꢀ ADC

C_DIF1

PGA

R_RTD

Interface

and

Control

DIN

R_LEAD2

R_F1

AIN2

DOUT/DRDY

SCLK

(AINN)

C_CM1

DRDY

AVDD

IDAC2

I_IDAC2

AIN3

4.096-MHz

Oscillator

(IDAC2)

CLK

500 ꢁA

AVSS

DGND

R_LEAD3

I_IDAC1+ I_IDAC2

R_BIAS

图 96. 3-Wire RTD Application

10.2.1 Design Requirements

表 34 shows the design requirements of the 3-wire RTD application.

表 34. Design Requirements

DESIGN PARAMETER

ADC supply voltage

RTD sensor type

VALUE

4.75 V (minimum)

3-wire Pt100

20 Ω to 400 Ω

0 Ω to 10 Ω

1 mW

RTD resistance range

RTD lead resistance range

RTD self heating

Accuracy⁽¹⁾

±0.1 Ω

(1) T_A= 25°C. After offset and full-scale calibration.

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10.2.2 Detailed Design Procedure

The key considerations in the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and

the sensor self-heating. As the design values of 表 35 show, several values of excitation currents are available.

The resolution is expressed in units of noise-free resolution (NFR). Noise-free resolution is resolution with no

code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general,

measurement resolution improves with increasing excitation current. Increasing the excitation current beyond

1000 µA results in no further improvement in resolution for this example circuit. The design procedure is based

on a 500-µA excitation current, because this level of current results in very low sensor self-heating (0.4 mW).

表 35. RTD Circuit Design Parameters

(1)

(2)

(3)

(4)

(5)

(6)

(7)

I_IDAC

(µA)

NFR

(Bits)

P_RTD

(mW)

V_RTD

(V)

Gain

(V/V)

V_REFMIN

(V)

V_REF

(V)

R_REF

(kΩ)

V_AINNLIM

(V)

V_AINPLIM

(V)

R_BIAS

(kΩ)

V_RTDN

(V)

V_RTDP

(V)

V_IDAC1

(V)

50

16.8

17.8

18.8

19.1

18.9

19.3

19.1

18.3

0.001

0.004

0.025

0.100

0.225

0.400

0.900

1.600

0.02

0.04

0.10

0.20

0.30

0.40

0.60

0.80

32

16

8

0.64

1.28

1.60

1.20

1.60

1.20

0.80

0.70

1.41

1.76

1.32

1.76

1.32

0.90

18

0.6

0.9

1.1

1.0

0.8

0.9

0.6

0.3

4.1

3.8

3.7

3.8

4.0

3.9

4.2

4.5

7.10

5.10

2.30

1.10

0.57

0.50

0.23

0.10

0.7

1.0

1.2

1.1

0.9

1.0

0.7

0.4

0.7

1.1

1.3

1.2

1.4

1.3

1.2

1.9

2.8

3.3

3.4

2.8

3.5

3.0

2.4

100

14.1

7.04

3.52

1.76

0.88

0.45

250

500

750

4

1000

1500

2000

4

2

1

(1) V_REFMINis the minimum reference voltage required by the design.

(2) V_REFis the design target reference voltage allowing for 10% overrange.

(3) V_AINNLIMis the absolute minimum input voltage required by the ADC.

(4) V_AINPLIMis the absolute maximum input voltage required by the ADC.

(5) V_RTDNis the design target negative input voltage.

(6) V_RTDPis the design target positive input voltage.

(7) V_IDAC1is the design target IDAC1 loop voltage.

Initially, R_LEAD1and R_LEAD2are considered to be 0 Ω. Route the IDAC1 current through the external reference

resistor, R_REF. IDAC1 generates the ADC reference voltage, V_REF, across the reference resistor. 公式 12 defines

this voltage:

V_REF= I_IDAC1· R_REF

(12)

Route the second current (IDAC2) to the second RTD lead.

Program the IDAC value by using the IDACMAG register; however, only the IDAC1 current flows through the

reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage proportional to the RTD

resistance. 公式 13 defines the RTD voltage:

V_RTD= R_RTD· I_IDAC1

(13)

As shown in 公式 14 through 公式 16, the ADC amplifies the RTD signal voltage (V_RTD) and measures the

resulting voltage against the reference voltage to produce a proportional digital output code.

Code ∝ V_RTD· Gain / V_REF

(14)

(15)

(16)

Code ∝ (R_RTD· I_IDAC1) · Gain / (I_IDAC1· R_REF

)

Code ∝ (R_RTD· Gain) / R_REF

As shown in 公式 16, the RTD measurement depends on the value of the RTD, the PGA gain, and the reference

resistor R_REF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of the

excitation current does not matter.

The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance,

R_LEAD2. The second voltage drop compensates the voltage drop caused by I_DAC1and R_LEAD1. The leads of a 3-

wire RTD typically have the same length; therefore, the lead resistance is typically identical. The differential

voltage (V_IN) across ADC inputs AIN8 and AIN9 is shown in 公式 17, with lead resistance taken into account

(R_LEADx≠ 0):

V_IN= I_IDAC1· (R_RTD+ R_LEAD1) – I_IDAC2· R_LEAD2

(17)

The expression for V_INreduces to 公式 18 if R_LEAD1= R_LEAD2and I_IDAC1= I_IDAC2

:

V_IN= I_IDAC1· R_RTD

(18)

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In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is

compensated as long as the lead resistance values and the IDAC values are matched.

Using 公式 13, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 µA) yields an RTD

voltage of V_RTD= 500 µA · 400 Ω = 0.2 V. Use the maximum gain of 8 in order to limit the corresponding loop

voltage of IDAC1. Gain = 8 requires a minimum reference voltage V_REFMIN= 0.2 V · 8 = 1.6 V. To provide margin

for the ADC operating range, increase the target reference voltage by 10% (V_REF= 1.6 V · 1.1 = 1.76 V). 公式 19

shows how to calculate the value of the reference resistor:

R_REF= V_REF/ I_IDAC1= 1.76 V / 500 µA = 3.52 kΩ

(19)

For this example application, 3.5 kΩ is chosen for R_REF. For best results, use a precision reference resistor R_REF

with a low temperature drift (< 10 ppm/°C). Any change in R_REFis reflected in the measurement as a gain error.

The next step in the design is determining the value of the R_BIASresistor, in order to level shift the RTD voltage to

meet the ADC absolute input-voltage specification. Calculate the minimum absolute voltage (V_AINNLIM), as shown

in 公式 20, to determine the required level-shift voltage:

AVSS + 0.15 + V_RTDMAX· (Gain – 1) / 2 ≤ V_AINNLIM

where

•

V_RTDMAX= maximum differential RTD voltage = 0.2 V

Gain = 8

AVSS = 0 V

(20)

The result of the equation requires a minimum absolute input voltage (V_RTDN) > 0.85 V. Therefore, the RTD

voltage must be level shifted by a minimum of 0.85 V. To meet this requirement, a target level-shift value of 1 V

is chosen to provide extra margin. 公式 21 calculates the value of R_BIAS

:

R_BIAS= V_AINN/ (I_IDAC1+ I_IDAC2) = 1 V / ( 2 · 500 µA) = 1 kΩ

(21)

Verify that the positive RTD voltage (V_RTDP) is less than the maximum absolute input voltage (V_AINPLIM), as shown

in 公式 22. after the level-shift voltage is determined:

V_AINPLIM≤ AVDD – 0.15 – V_RTDMAX· (Gain – 1) / 2

where

•

V_RTDMAX= maximum differential RTD voltage = 0.2 V

Gain = 8

AVDD = 4.75 V (minimum)

(22)

(23)

Solving 公式 22 results in a required V_RTDPof less than 3.9 V. 公式 23 calculates the V_RTDPinput voltage:

V_AINP= V_RTDN+ I_IDAC1· (R_RTD+ R_LEAD1) = 1 V + 500 µA · (400 Ω + 10 Ω) = 1.2 V

Because 1.2 V is less than the 3.9-V maximum input voltage limit, the absolute positive and negative RTD

voltages are within the ADC specified input range.

The next step in the design is to verify that the IDACs have enough voltage headroom (compliance voltage) to

operate. The loop voltage of the excitation current must be less than the supply voltage minus the specified IDAC

compliance voltage. Calculate the voltage drop developed across each IDAC current path to AVSS. In this circuit,

IDAC1 has the largest voltage drop developed across its current path. The IDAC1 calculation is sufficient to

satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1 voltage drop. 公式 24 shows the sum

of voltages in the IDAC1 loop:

V_IDAC1= [(I_IDAC1+ I_IDAC2) · (R_LEAD3+ R_BIAS)] + [I_IDAC1· (R_RTD+ R_LEAD1+ R_REF)] + V_D

where

•

V_D= external blocking diode voltage

(24)

公式 24 results in a loop voltage of V_IDAC1= 3.0 V. The worst-case current source compliance voltage is:

(AVDD – 0.4 V) = (4.75 V – 0.4 V) = 4.35 V. The V_IDAC1loop voltage is less than the specified current source

compliance voltage (3.0 V < 4.35 V).

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Many applications benefit from using an analog filter at the inputs to remove noise and interference from the

signal. Filter components are placed on the ADC inputs (R_F1, R_F2, C_DIF1, C_CM1, and C_CM2), as well as on the

reference inputs (R_F3, R_F4, C_DIF2, C_CM3, and C_CM4). The filters remove both differential and common-mode noise.

The application shows a differential input noise filter formed by R_F1, R_F2and C_DIF1, with additional differential

mode capacitance provided by the common-mode filter capacitors, C_CM1and C_CM2. 公式 25 calculates the

differential –3-dB cutoff frequency:

f_DIF= 1 / [2π · (R_F1+ R_F2) · (C_DIF1+ C_CM1|| C_CM2)]

(25)

The common-mode noise filter is formed by components R_F1, R_F2, C_CM1, and C_CM2. 公式 26 calculates the

common-mode signal –3-dB cutoff frequency:

f_CM= 1 / (2π · R_F1· C_CM1) = 1 / (2π · R_F2· C_CM2

)

(26)

Mismatches in the common-mode filter components convert common-mode noise into differential noise. To

reduce the effect of mismatch, use a differential mode filter with a corner frequency that is at least 10 times lower

than the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode

converted noise. The filter resistors (R_Fx) also serve as current-limiting resistors. These resistors limit the current

into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs.

Filter resistors lead to an offset voltage error because of the dc input current leakage flowing into and out of the

device. Remove this voltage error by system offset calibration. Resistor values that are too large generate

excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor

values is 100 Ω to 10 kΩ. The properties of the capacitors are important because the capacitors are connected to

the signal; use high-quality C0G ceramics or film-type capacitors.

For consistent noise performance across the full range of RTD measurements, match the corner frequencies of

the input and reference filter. See the RTD Ratiometric Measurements and Filtering Using the ADS1148 and

ADS1248 Application Report for detailed information on matching the input and reference filter.

10.2.2.1 Register Settings

表 36 shows the register settings for this design.

表 36. Register Settings

REGISTER

02h

NAME

INPMUX

PGA

SETTING

12h

DESCRIPTION

Select AIN_P= AIN1 and AIN_N= AIN2

03h

0Bh

PGA enabled, PGA Gain = 8

04h

DATARATE

14h

Continuous conversion mode, 20-SPS data rate

Positive and negative reference buffers enabled, REFP1 and

REFN1 reference inputs selected, internal reference always on

05h

REF

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

IDACMAG

IDACMUX

VBIAS

05h

35h

00h

10h

xxh

00h

IDAC magnitude set to 500 µA

IDAC2 set to AIN3, IDAC1 set to AIN5

SYS

OFCAL0⁽¹⁾

OFCAL1

OFCAL2

FSCAL0⁽¹⁾

FSCAL1

FSCAL2

GPIODAT

GPIOCON

(1) A two-point offset and gain calibration removes errors from the R_REFtolerance. The results are used for the OFC and FSC registers.

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10.2.3 Application Curves

To test the accuracy of the acquisition circuit, a series of calibrated high-precision discrete resistors are used as

an input to the system. Measurements are taken at T_A= 25°C. 图 97 displays the resistance measurement over

an input span from 20 Ω to 400 Ω. Any offset error is generally attributed to the offset of the ADC, and the gain

error can be attributed to the accuracy of the R_REFresistor and the ADC. The R_REFvalue is also calibrated to

reduce the gain error contribution.

Precision temperature measurement applications are typically calibrated to remove the effects of gain and offset

errors that generally dominate the total system error. The simplest calibration method is a linear, or two-point

calibration that applies an equal and opposite gain and offset term to cancel the measured system gain and

offset error. In this particular tested application, the gain and offset error was very small, and did not require

additional calibration other than the self offset and gain calibration provided by the device. 图 98 shows the

resulting measured resistance error.

The results in 图 98 are converted to temperature accuracy by dividing the results by the RTD sensitivity (α) at

the measured resistance. Over the full resistance input range, the maximum total measured error is ±0.0190 Ω.

公式 27 uses the measured resistance error and the RTD sensitivity at 0°C to calculate the measured

temperature accuracy.

Error (°C) = Error (Ω) / α_@0°C= ±0.0190 Ω / 0.39083 Ω / °C = ±0.049°C

(27)

图 99 displays the calculated temperature accuracy of the circuit assuming a linear RTD resistance to

temperature response. This figure does not include any linearity compensation of the RTD, but 图 99 does

remove offset and gain error, which can be calibrated with the OFC and FSC registers.

0.03

0.02

0.01

0

35000

30000

25000

20000

15000

10000

5000

0

-0.01

-0.02

-0.03

0

50

100 150 200 250 300 350 400 450

Resistance (W)

0

50

100 150 200 250 300 350 400 450

Resistance (W)

图 97. ADC Output Code vs Equivalent RTD Resistance

图 98. Measured Resistance Error vs Equivalent RTD

Resistance

0.06

0.04

0.02

0

-0.02

-0.04

-0.06

0

50

100 150 200 250 300 350 400 450

Resistance (W)

图 99. Equivalent Temperature Error vs Equivalent RTD Resistance

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10.3 What To Do and What Not To Do

•

Do partition the analog, digital, and power-supply circuitry into separate sections on the PCB.

Do use a single ground plane for analog and digital grounds.

Do place the analog components close to the ADC pins using short, direct connections.

Do keep the SCLK pin free of glitches and noise.

Do verify that the analog input voltages are within the specified PGA input voltage range under all input

conditions.

•

Do float unused analog input pins to minimize input leakage current on all other analog inputs. Connecting

unused pins to AVDD is the next best option.

•

Do provide current limiting to the analog inputs in case overvoltage faults occur.

Do use a low-dropout linear regulator (LDO) to reduce ripple voltage generated by switch-mode power

supplies. Reducing ripple is especially important for AVDD where the supply noise can affect the

performance.

•

Don't cross analog and digital signals.

Don't allow the analog and digital power supply voltages to exceed 5.5 V under any condition, including

during power-up and power-down.

78

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

What To Do and What Not To Do (接下页)

图 100 shows the do's and don'ts of the ADC circuit connections.

INCORRECT

CORRECT

5 V

AVDD

Device

AIN_P

AIN_N

16-bit

PGA

ûꢀ ADC

AIN_N

AVSS

0 V

Single-ended input, PGA enabled

Single-ended input, PGA bypassed

CORRECT

5 V

2.5 V

AVDD

Device

AIN_P

AIN_N

AIN_P

AIN_N

16-bit

PGA

PGA enabled

2.5 V

ûꢀ ADC

AVSS

0 V

-2.5 V

0 V

Single-ended input, PGA enabled

3.3 V

5 V

3.3 V

INCORRECT

AVDD

PGA

DVDD

AVDD

PGA

DVDD

16-bit

Device

16-bit

ûꢀ ADC

AVSS

DGND

AVSS

DGND

Inductive supply or ground connections

AGND/DGND isolation

CORRECT

3.3 V

5 V

2.5 V

CORRECT

AVDD

PGA

DVDD

16-bit

AVDD

DVDD

Device

16-bit

PGA

ûꢀ ADC

AVSS

DGND

AVSS

-2.5 V

DGND

Low impedance AGND/DGND connection

图 100. Do's and Don'ts Circuit Connections

79

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

11 Power Supply Recommendations

11.1 Power Supplies

The ADS114S0xB requires three power supplies: analog (AVDD, AVSS), digital core (DVDD, DGND), and digital

I/O (IOVDD, DGND). The analog power supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or

unipolar (for example, AVDD = 3.3 V, AVSS = 0 V) and is independent of the digital power supplies. DVDD is

used to power the digital circuits of the devices. IOVDD sets the digital I/O levels (with the exception of the GPIO

levels that are set by the analog supply of AVDD and AVSS). IOVDD must be equal to or larger than DVDD.

11.2 Power-Supply Sequencing

AVDD and DVDD may be powered up in any order. However, IOVDD is recommended to be powered up before

or at the same time as DVDD. If DVDD comes up before IOVDD, a reset of the device using the RESET pin or

the RESET command may be required.

11.3 Power-On Reset

An internal POR is released after all three supplies exceed approximately 1.65 V. Each supply has an individual

POR circuit. A brownout condition on any of the three supplies triggers a reset of the complete device.

11.4 Power-Supply Decoupling

Good power-supply decoupling is important to achieve best performance. AVDD must be decoupled with at least

a 330-nF capacitor to AVSS. DVDD and IOVDD (when not connected to DVDD) must be decoupled with at least

a 0.1-μF capacitor to DGND. 图 101 and 图 102 show typical power-supply decoupling examples for unipolar and

bipolar analog supplies, respectively. Place the bypass capacitors as close to the power-supply pins of the

device as possible using low-impedance connections. Use multi-layer ceramic chip capacitors (MLCCs) that offer

low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling

purposes. To reduce inductance on the supply pins, avoid the use of vias for connecting the capacitors to the

supply pins. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to

ground planes. Connect analog and digital grounds together as close to the device as possible.

1 mF

œ2.5 V

24

23

22

21

20

19

18

17

24

23

22

21

20

19

18

17

3.3 V

NC 25

DVDD

IOVDD

DGND

16

15

14

13

12

11

10

9

NC 25

DVDD

IOVDD

DGND

16

15

14

13

12

11

10

9

+2.5 V

5 V

26

AVDD

26

27

28

AVDD

0.1 mF

330 nF

27

28

AVSS

DRDY

œ2.5 V

REFN0 29

REFP0 30

DOUT/DRDY

SCLK

REFN0 29

REFP0 30

DOUT/DRDY

SCLK

REFN1/AIN7 31

REFP1/AIN6 32

DIN

REFN1/AIN7 31

REFP1/AIN6 32

DIN

CS

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

图 102. Bipolar Analog Power Supply

图 101. Unipolar Analog Power Supply

80

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

12 Layout

12.1 Layout Guidelines

Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog

and digital components. This recommendation generally means that the layout separates analog components

[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital

components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate

arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching

regulators]. 图 103 shows an example of good component placement. Although 图 103 provides a good example

of component placement, the best placement for each application is unique to the geometries, components, and

PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every design and

careful consideration must always be used when designing with any analog component.

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Supply

Generation

Signal

Conditioning

(RC Filters

and

Interface

Transceiver

Device

Microcontroller

Connector

or Antenna

Amplifiers)

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

图 103. System Component Placement

The following basic recommendations for layout of the ADS114S0xB help achieve the best possible performance

of the ADC. A good design can be ruined with a bad circuit layout.

•

Separate analog and digital signals. To start, partition the board into analog and digital sections where the

layout permits. Route digital lines away from analog lines. This prevents digital noise from coupling back into

analog signals.

•

The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this splitting is not

necessary. Place digital signals over the digital plane, and analog signals over the analog plane. As a final

step in the layout, the split between the analog and digital grounds must be connected to together at the

ADC.

•

Fill void areas on signal layers with ground fill.

Provide good ground return paths. Signal return currents will flow on the path of least impedance. If the

ground plane is cut or has other traces that block the current from flowing right next to the signal trace,

another path must be found to return to the source and complete the circuit. If forced into a larger path, the

chance that the signal radiates increases. Sensitive signals are more susceptible to EMI interference.

•

Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass

capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active

device yields the best results.

Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react

with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source

signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI

pickup and reduces the high-frequency impedance at the input of the device.

•

Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor

can create a parasitic themocouple that can add an offset to the measurement. Differential inputs must be

matched for both the inputs going to the measurement source.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best

input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and

AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G

(NPO) that have stable properties and low noise characteristics.

81

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

12.2 Layout Example

Reference

input

Differential

input or

Reference

input

Internal plane connected to GND

(DGND = AVSS)

Via connection to power plane

AIN5

Differential

input

AIN8

Differential

input

AIN4

AIN9

1: AINCOM

2: AIN5

24: REFCOM

23: REFOUT

AIN3

22: GPIO0/

AIN8

3: AIN4

Differential

input

21: GPIO1/

AIN9

4: AIN3

20: GPIO2/

AIN10

5: AIN2

AIN2

19: GPIO3/

AIN11

6: AIN1

AIN10

7: AIN0

18: RESET

17: CLK

Differential

input

8: START

AIN11

AIN1

Differential

input

AIN0

Digital

connections

图 104. ADS114S0xB Layout Example

82

ADS114S06B, ADS114S08B

www.ti.com.cn

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

13 器件和文档支持

13.1 器件支持

13.1.1 开发支持

德州仪器 (TI)，《ADS1x4S0x 设计计算器》

13.2 文档支持

13.2.1 相关文档

请参阅如下相关文档：

•

德州仪器 (TI)，《具有 PGA 和电压基准的 ADS114S0x 低功耗、低噪声、高集成度、6 通道和 12 通道 4kSPS

16 位 Δ-Σ ADC》数据表

•

德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表

德州仪器 (TI)，《使用 ADS1148 和 ADS1248 进行 RTD 比例测量和滤波》应用报告

德州仪器 (TI)，《3 线 RTD 测量系统参考设计（-200°C 至 850°C）》参考指南

13.3 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。

表 37. 相关链接

器件

产品文件夹

单击此处

立即订购

单击此处

技术文档

单击此处

工具与软件

单击此处

支持和社区

单击此处

ADS114S06B

ADS114S08B

13.4 接收文档更新通知

要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

13.5 社区资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

13.6 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

13.7 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

13.8 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

83

ADS114S06B, ADS114S08B

ZHCSGS4A –AUGUST 2017–REVISED FEBRUARY 2020

www.ti.com.cn

14 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

84

GENERIC PACKAGE VIEW

RHB 32

5 x 5, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224745/A

www.ti.com

PACKAGE OUTLINE

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

A

5.1

4.9

B

5.1

4.9

PIN 1 INDEX AREA

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X 3.5

(0.2) TYP

ꢀꢀꢀꢁꢂꢃꢄꢂꢃ

9

16

28X 0.5

8

17

SYMM

33

2X

3.5

1

24

0.3

0.2

32X

32

25

PIN 1 ID

(OPTIONAL)

SYMM

0.1

0.05

C A B

C

0.5

0.3

32X

4223725/A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

2.1)

(

32

25

32X (0.6)

32X (0.25)

1

24

28X (0.5)

33

SYMM

(4.8)

2X

(0.8)

ꢅꢄꢂꢁꢆ

VIA TYP

8

17

(R0.05) TYP

9

16

2X (0.8)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

METAL

SOLDER MASK

OPENING

SOLDER MASK

EXPOSED

METAL

OPENING

EXPOSED

METAL UNDER

SOLDER MASK

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4223725/A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RHB0032M

PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

4X ( 0.94)

32

25

32X (0.6)

32X (0.25)

1

24

28X (0.5)

33

SYMM

(4.8)

2X

(0.57)

METAL

TYP

8

17

(R0.05) TYP

9

16

2X (0.57)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

80% PRINTED COVERAGE BY AREA

SCALE: 15X

4223725/A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS114S06BIPBSR
厂家：	TEXAS INSTRUMENTS
描述：	适用于低成本应用且具有 PGA 和电压基准的 16 位、4kSPS、6 通道 Δ-Σ ADC \| PBS \| 32 \| -40 to 125
文件：	总96页 (文件大小：3455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS114S06BIPBSR [TI]

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