ADS1203IRGTT [TI]
Motor control, current measurement; 电机控制，电流测量
| 型号： | ADS1203IRGTT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Motor control, current measurement |
| 文件： | 总33页 (文件大小：783K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
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FEATURES
DESCRIPTION
D
D
D
D
D
D
16-Bit Resolution
The ADS1203 is a delta-sigma (∆Σ) modulator with a
95dB dynamic range, operating from a single +5V
supply. The differential inputs are ideal for direct
connection to transducers or low-level signals. With the
appropriate digital filter and modulator rate, the device
can be used to achieve 16-bit analog-to-digital (A/D)
conversion with no missing codes. An effective
resolution of 14 bits or SNR of 85dB (typical) can be
maintained with a digital filter bandwidth of 40kHz at a
modulator rate of 10MHz. The ADS1203 is designed for
use in medium- to high-resolution measurement
applications including current measurements, smart
transmitters, and industrial process control. The
ADS1203 is available in TSSOP-8 and QFN-16 (3x3)
packages.
14-Bit Linearity
250mV Input Range with Single +5V Supply
1% Internal Reference Voltage
1% Gain Error
Flexible Serial Interface with Four Different
Modes
D
Implemented Twinned Binary Coding as
Split-Phase or Manchester Coding for
One-Line Interfacing
D
Operating Temperature Range:
−40°C to +125°C
APPLICATIONS
D
D
D
D
D
Motor Control
VDD (AVDD
)
VDD (BVDD)
Current Measurement
Industrial Process Control
Instrumentation
MDAT
VIN
+
Second−Order
∆Σ
Modulator
MCLK
−
VIN
Smart Transmitters
CLKOUT
20MHz
RC Oscillator
Interface
Circuit
Buffer
M0
M1
Ω
20k
2.5V
REFIO
Reference
Voltage
GND (AGND)
GND (BGND)
NOTE: BOLD pins are available only in QFN package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢜꢝ ꢖ ꢗꢞ ꢄ ꢟꢠ ꢖꢡ ꢗ ꢚꢟꢚ ꢐꢅ ꢢꢁ ꢃ ꢌꢊ ꢂꢐꢁꢅ ꢐꢋ ꢣꢈ ꢃ ꢃ ꢉꢅꢂ ꢊꢋ ꢁꢢ ꢤꢈꢥ ꢆꢐꢣ ꢊꢂꢐ ꢁꢅ ꢕꢊ ꢂꢉꢦ ꢜꢃ ꢁꢕꢈ ꢣꢂꢋ
ꢣ ꢁꢅ ꢢꢁꢃ ꢌ ꢂꢁ ꢋ ꢤꢉ ꢣ ꢐ ꢢꢐ ꢣ ꢊ ꢂꢐ ꢁꢅꢋ ꢤ ꢉꢃ ꢂꢧꢉ ꢂꢉ ꢃ ꢌꢋ ꢁꢢ ꢟꢉꢨ ꢊꢋ ꢠꢅꢋ ꢂꢃ ꢈꢌ ꢉꢅꢂ ꢋ ꢋꢂ ꢊꢅꢕ ꢊꢃ ꢕ ꢩ ꢊꢃ ꢃ ꢊ ꢅꢂꢪꢦ
ꢜꢃ ꢁ ꢕꢈꢣ ꢂ ꢐꢁ ꢅ ꢤꢃ ꢁ ꢣ ꢉ ꢋ ꢋ ꢐꢅ ꢙ ꢕꢁ ꢉ ꢋ ꢅꢁꢂ ꢅꢉ ꢣꢉ ꢋꢋ ꢊꢃ ꢐꢆ ꢪ ꢐꢅꢣ ꢆꢈꢕ ꢉ ꢂꢉ ꢋꢂꢐ ꢅꢙ ꢁꢢ ꢊꢆ ꢆ ꢤꢊ ꢃ ꢊꢌ ꢉꢂꢉ ꢃ ꢋꢦ
Copyright 2004−2008, Texas Instruments Incorporated
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of
this data sheet, or see the TI website at www.ti.com.
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
ADS1203
−0.3 to 6
UNIT
V
Supply Voltage, AVDD to AGND or VDD to GND
Supply Voltage, BVDD to BGND
−0.3 to 6
V
Analog Input Voltage with Respect to AGND or GND
Reference Input Voltage with Respect to AGND
Digital Input Voltage with Respect to BGND or GND
Ground Voltage Difference, AGND to BGND
Voltage Differences, BVDD to AGND
AGND − 0.3 to AVDD + 0.3
AGND − 0.3 to AVDD + 0.3
BGND − 0.3 to BVDD + 0.3
0.3
V
V
V
V
−0.3 to 6
V
Input Current to Any Pin Except Supply
Power Dissipation
10
mA
See Dissipation Rating Table
−40 to +150
Operating Virtual Junction Temperature Range, TJ
Operating Free-Air Temperature Range, TA
Storage Temperature Range, TSTG
°C
°C
°C
−40 to +125
−65 to +150
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
NOM
MAX
UNIT
V
Supply Voltage, AVDD to AGND or VDD to GND
4.5
5
5.5
Low-Voltage Levels
2.7
3.6
V
Supply Voltage, BVDD to BGND
5V Logic Levels
4.5
5
5.5
V
Reference Input Voltage
0.5
2.5
2.6
V
Operating Common-Mode Signal
VIN+ − VIN− (TSSOP package)
0
5
+250
V
−250
mV
V
Analog Inputs
VIN+ − VIN− (QFN package)
−0.1 × REFIO
+0.1 × REFIO
24
(1)
External Clock
16
20
MHz
°C
Operating Junction Temperature Range, TJ
−40
+150
(1)
With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves.
DISSIPATION RATINGS
TA ≤ +25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
TA = +1255C
(1)
POWER RATING
102mW
PACKAGE
TSSOP-8
QFN-16
532mW
4.3mW/°C
338mW
274mW
2540mW
20.4mW/°C
1622mW
1316mW
500mW
(1)
This is the inverse of the traditional junction-to-ambient thermal resistance (RqJA). Thermal resistances are not production tested and are for
informational purposes only.
2
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV,
3
VIN− = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless otherwise noted.
ADS1203I
(1)
MIN
TYP
MAX
UNITS
PARAMETER
Resolution
TEST CONDITIONS
16
Bits
DC Accuracy
1
4
3
LSB
LSB
LSB
µV
(2)
INL
Integral linearity error
T
= −40°C to +85°C
A
(3)
DNL
Differential nonlinearity
1
(4)
VOS
Input offset
220
3.5
0.2
1000
8
TCVOS
Input offset drift
µV/°C
%
REFIO = internal 2.5V
REFIO = internal 2.5V, T = −40°C to +85°C
1.4
1
(4)
GERR
Gain error
−1
%
A
30
20
80
ppm/°C
ppm/°C
dB
TCGERR Gain error drift
T
= −40°C to +85°C
A
PSRR
Power-supply rejection ratio
4.5V < AVDD or VDD < 5.5V
Analog Input
FSR
Full-scale differential range
(VIN+) − (VIN−)
320
5
mV
V
Operating common-mode
−0.1
(3)
signal
Input capacitance
Common-mode
3
pF
nA
nA
kΩ
pF
dB
dB
16
1
Input leakage current
T
A
= −40°C to +85°C
Differential input resistance
Differential input capacitance
Equivalent
28
5
At DC
92
CMRR
Common-mode rejection ratio
VIN = 0V to 5V at 50kHz
105
Internal Clock for Modes 0, 1, and 2
Clock frequency
8.7
9
10
20
11
11
MHz
MHz
T
A
= −40°C to +85°C
External Clock for Mode 3
(5)
Clock frequency
16
24
MHz
(1)
(2)
All typical values are at TA = +25°C.
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the supported external clock frequency range is 1MHz up to 32MHz.
Available only for QFN package.
Applicable for 5.0V nominal supply: BVDD = 4.5V to 5.5V.
Applicable for 3.0V nominal supply: BVDD = 2.7V to 3.6V.
Measured with CLKOUT pin not loaded.
(3)
(4)
(5)
(6)
(7)
(8)
(9)
3
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV,
3
VIN− = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless otherwise noted.
ADS1203I
(1)
MIN
TYP
MAX
UNITS
PARAMETER
AC Accuracy
TEST CONDITIONS
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
=
=
=
=
=
=
=
=
250mVPP at 5kHz
81
82.5
81.5
83
85
85
dB
dB
dB
dB
dB
dB
dB
dB
SINAD
SNR
Signal-to-noise + distortion
250mVPP at 5kHz, T = −40°C to +85°C
A
250mVPP at 5kHz
Signal-to-noise ratio
250mVPP at 5kHz, T = −40°C to +85°C
A
250mVPP at 5kHz
−95
95
−87
−88
THD
Total harmonic distortion
250mVPP at 5kHz, T = −40°C to +85°C
A
250mVPP at 5kHz
88
90
SFDR
Spurious-free dynamic range
250mVPP at 5kHz, T = −40°C to +85°C
A
(6)
Voltage Reference Output
V
Reference voltage output
2.440
2.5
30
2.560
V
ppm/°C
ppm/°C
µVrms
µVrms
dB
OUT
Reference voltage temperature
drift
dVOUT/dT
T
= −40°C to +85°C
20
A
f = 0.1Hz to 10Hz, CL = 10µF
f =10Hz to 10kHz, CL = 10µF
10
Output voltage noise
12
PSRR
IOUT
ISC
Power-supply rejection ratio
Output current
60
10
µA
Short-circuit current
0.5
100
mA
Turn-on settling time
To 0.1% at CL = 0
µs
(6)
Voltage Reference Input
VIN
Reference voltage input
0.5
2.5
20
5
2.6
1
V
Reference input resistance
Reference input capacitance
kΩ
pF
µA
Reference input current
(7)
Digital Inputs
Logic family
CMOS with Schmitt Trigger
0.7×BVDD BVDD+0.3
VIH
VIL
IIN
High-level input voltage
Low-level input voltage
Input current
V
V
−0.3
0.3×BVDD
VIN = BVDD or GND
50
nA
pF
C
I
Input capacitance
5
(7)
Digital Outputs
Logic family
CMOS
VOH
VOL
CL
High-level output voltage
Low-level output voltage
Load capacitance
BVDD = 4.5V, IOH = −100µA
BVDD = 4.5V, IOL = +100µA
4.44
V
V
0.5
30
pF
Data format
Bit Stream
(1)
(2)
All typical values are at TA = +25°C.
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the supported external clock frequency range is 1MHz up to 32MHz.
Available only for QFN package.
Applicable for 5.0V nominal supply: BVDD = 4.5V to 5.5V.
Applicable for 3.0V nominal supply: BVDD = 2.7V to 3.6V.
Measured with CLKOUT pin not loaded.
(3)
(4)
(5)
(6)
(7)
(8)
(9)
4
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV,
3
VIN− = 0V, Mode 3, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless otherwise noted.
ADS1203I
(1)
MIN
TYP
MAX
UNITS
PARAMETER
Digital Inputs
TEST CONDITIONS
(6)(8)
Logic family
LVCMOS
VIH
VIL
IIN
High-level input Voltage
Low-level input voltage
Input current
BVDD = 3.6V
BVDD = 2.7V
2
BVDD+0.3
0.8
V
V
−0.3
V = BVDD or GND
I
50
nA
pF
CI
Input capacitance
5
(6)(8)
Digital Outputs
Logic family
LVCMOS
V
V
High-level output voltage
Low-level output voltage
Load capacitance
BVDD = 2.7V, I
BVDD = 2.7V, I
= −100µA
= +100µA
BVDD−0.2
V
V
OH
OH
OL
0.2
30
OL
C
pF
L
Data format
Bit Stream
Power Supply
V
Supply voltage
4.5
4.5
2.7
4.5
5.5
5.5
3.6
5.5
10.5
8.5
7.5
6.9
2.3
0.9
49
V
V
DD
(6)
(6)
AVDD
Analog supply voltage
Low-voltage levels
5V logic levels
Mode 0
V
BVDD
Buffer I/O supply voltage
Supply current
V
8.4
6.7
6.2
5.9
2.2
0.8
42
mA
mA
mA
mA
mA
mA
mW
mW
IDD
Mode 3
Mode 0
(6)
AIDD
Analog operating supply current
Mode 3
BVDD = 3V, Mode 0
BVDD = 3V, Mode 3
Mode 0
Buffer I/O operating supply
current
(6)
BIDD
(9)
Power dissipation
(9)
Mode 3
33.5
39
(1)
(2)
All typical values are at TA = +25°C.
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for VIN+ = −250mV to +250mV, expressed either as the number of LSBs or as a percent of measured input range (500mV).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
With reduced accuracy, the supported external clock frequency range is 1MHz up to 32MHz.
Available only for QFN package.
Applicable for 5.0V nominal supply: BVDD = 4.5V to 5.5V.
Applicable for 3.0V nominal supply: BVDD = 2.7V to 3.6V.
Measured with CLKOUT pin not loaded.
(3)
(4)
(5)
(6)
(7)
(8)
(9)
EQUIVALENT INPUT CIRCUIT
VDD
(AVDD
)
VDD
(BVDD)
C(SAMPLE) = 5pF
Ω
RON = 350
AIN
DIN
GND
(AGND)
GND
(BGND)
Diode Turn on Voltage: 0.4V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
5
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
PIN ASSIGNMENTS: PW (TSSOP) PACKAGE
PIN ASSIGNMENTS: RGT (QFN) PACKAGE
(1)
RGT PACKAGE
PW PACKAGE
TSSOP-8
(TOP VIEW)
QFN-16
(TOP VIEW)
M0
1
2
3
4
8
7
6
5
VDD
1
2
3
4
12 BVDD
11 MCLK
REFIO
VIN+
MCLK
MDAT
GND
VIN
VIN
+
ADS1203
ADS1203
10
9
CLKOUT
MDAT
−
−
VIN
NC
M1
(1)
The thermal pad is internally connected to the substrate. This pad
can be connected to the analog ground or left floating. Keep the
thermal pad separate from the digital ground, if possible.
Terminal Functions: PW (TSSOP) Package
Terminal Functions: RGT (QFN) Package
TERMINAL
TERMINAL
NAME
M0
NO. I/O
DESCRIPTION
NAME
REFIO
VIN+
NO.
I/O
DESCRIPTION
1
2
3
4
5
6
7
8
I
I
I
I
Mode input
1
I/O Reference voltage input/output
VIN+
VIN−
M1
Noninverting analog input
Inverting analog input
Mode input
2
I
I
I
I
Noninverting analog input
Inverting analog input
VIN−
3
NC
4, 6, 14, 15
Not connected
GND
MDAT
MCLK
VDD
Power supply ground
Modulator data output
M1
5
7
Mode input
O
AGND
BGND
MDAT
CLKOUT
MCLK
BVDD
AVDD
M0
Analog power-supply ground
Interface power-supply ground
Modulator data output
Modulator clock output (Mode 3 only)
I/O Modulator clock input or output
Power supply: +5V nominal
8
9
O
O
10
11
12
13
16
:
NOTE For the TSSOP package, BGND and AGND are internally
connected to the GND pin. Additionally, the AVDD and BVDD
I/O Modulator clock input or output
Interface power supply
Analog power supply
pins are connected to VDD
.
Mode input
6
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION
tC1
MCLK
tW1
tD1
MDAT
Figure 1. Mode 0 Operation
TIMING CHARACTERISTICS: MODE 0
(1)
(2)
(1)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or AVDD = +5V, BVDD = +3V or VDD = +5V
,
unless otherwise noted.
PARAMETER
MODE
MIN
91
MAX
111
UNIT
tC1
tW1
tD1
Clock period
0
0
0
ns
ns
ns
Clock high time
(tC1/2) − 5
−2
(tC1/2) + 5
2
Data delay after falling edge of clock
(1)
(2)
Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
Only for QFN package. Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
tC2
MCLK
tD2
tD3
tW2
MDAT
Figure 2. Mode 1 Operation
TIMING CHARACTERISTICS: MODE 1
(1)
(2)
(1)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or AVDD = +5V, BVDD = +3V or VDD = +5V
,
unless otherwise noted.
PARAMETER
MODE
MIN
182
MAX
222
UNIT
ns
tC2
tW2
tD2
tD3
Clock period
1
1
1
1
Clock high time
(tC2/2) − 5
(tW2/2) − 2
(tW2/2) − 2
(tC2/2) + 5
(tW2/2) + 2
(tW2/2) + 2
ns
Data delay after rising edge of clock
Data delay after falling edge of clock
ns
ns
(1)
(2)
Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
Only for QFN package. Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
7
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
tC 1
Internal
MCLK
tW 1
Internal
1
0
1
1
0
0
MDATA
MDATA
Figure 3. Mode 2 Operation
TIMING CHARACTERISTICS: MODE 2
(1)
(2)
(1)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or AVDD = +5V, BVDD = +3V or VDD = +5V
,
unless otherwise noted.
PARAMETER
MODE
MIN
91
MAX
111
UNIT
tC1
Clock period
2
2
ns
ns
tW1
Clock high time
(tC1/2) − 5
(tC1/2) + 5
(1)
(2)
Applicable for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
Only for QFN package. Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
tC1
MCLK
tC2
tW1
tD1
tD2
CLKOUT(1)
MDAT
tW2
tD4
tD3
NOTE: (1) CLKOUT availble only on QFN package.
Figure 4. Mode 3 Operation
TIMING CHARACTERISTICS: MODE 3
(1)
(2)
(1)
Over recommended operating free-air temperature range at −40°C to +125°C, AVDD = BVDD = +5V or AVDD = +5V, BVDD = +3V or VDD = +5V
,
unless otherwise noted.
PARAMETER
MIN
MAX UNIT
tC1
tW1
tC2
tW2
tD1
tD2
tD3
tD4
MCLK period
41.6
1000
tC1 − 10
2 × tC1
(tC2/2) + 5
10
ns
ns
ns
ns
ns
ns
ns
ns
MCLK high time
10
CLKOUT period
2 × tC1
CLKOUT high time
(tC2/2) − 5
CLKOUT rising edge delay after MCLK rising edge
CLKOUT falling edge delay after MCLK rising edge
Data valid delay after rising edge of CLKOUT
Data valid delay after rising edge of MCLK
0
0
10
−2
0
+2
10
:
NOTE Input signal is specified with tR = tF = 5ns (10% to 90% of BVDD or VDD) and timed from a voltage level of (VIL + VIH)/2. See timing diagram.
(1)
(2)
Applicablefor 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V.
Only for QFN package. Applicable for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V.
8
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TYPICAL CHARACTERISTICS
3
AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless
otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(Mode 3, MCLK = 20MHz)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(Mode 0)
4
3
2
1
0
4
3
2
1
0
1
2
3
4
5
_
+25 C
−
_
40 C
−
_
40 C
−
1
2
3
4
5
−
−
−
−
−
_
+85 C
_
+85 C
−
−
−
−
_
+25 C
−
−
−
−
80
320
240
160
0
80
160
240
320
−
−
−
−
80
320
240
160
0
80
160
240
320
Differential Input Voltage (mV)
Differential Input Voltage (mV)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(Mode 3, MCLK = 32MHz)
INTEGRAL NONLINEARITY vs TEMPERATURE
Mode 3 (MCLK = 32MHz)
5
4
3
2
1
0
0.0076
4
3
2
1
0
0.0061
0.0046
0.0031
0.0015
0
Mode 0
_
+85 C
−
1
2
3
4
5
−
_
40 C
−
−
−
−
Mode 3 (MCLK = 20MHz)
_
+25 C
−
−
20
40
0
20
40
60
80
100
−
−
−
−
80
320
240
160
0
80
160
240
320
_
Temperature ( C)
Differential Input Voltage (mV)
OFFSET vs TEMPERATURE
OFFSET vs POWER SUPPLY
0
0
100
Mode 0
−
−
−
−
−
−
−
−
−
100
200
300
400
500
600
700
800
Mode 3 (MCLK = 20MHz)
Mode 0
−
−
−
−
−
−
−
200
300
400
500
600
700
800
Mode 3 (MCLK = 20MHz)
Mode 3 (MCLK = 32MHz)
Mode 3 (MCLK = 32MHz)
−
−
20
40
0
20
40
60
80
100
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
_
Temperature ( C)
Power Supply (V)
9
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TYPICAL CHARACTERISTICS (continued)
3
AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless
otherwise noted.
GAIN vs TEMPERATURE
RMS NOISE vs INPUT VOLTAGE LEVEL
14
12
10
8
0.10
0
Mode 0
−
0.10
0.20
0.30
0.40
0.50
Mode 3 (MCLK = 20MHz)
−
−
−
−
6
4
Mode 3 (MCLK = 32MHz)
2
0
−
−
−
−
80
−
−
320
240
160
0
80
160
240
320
100
100
40
20
0
20
40
60
80
100
_
Temperature ( C)
Differential Input Voltage (mV)
SIGNAL−TO−NOISE + DISTORTION
vs TEMPERATURE
SIGNAL−TO−NOISE RATIO vs TEMPERATURE
Mode 3 (MCLK = 32MHz)
85.6
85.4
85.2
85.0
84.8
84.6
84.4
84.2
85.2
84.8
84.4
84.0
83.6
83.2
82.8
82.4
82.0
81.6
81.2
80.8
Mode 3 (MCLK = 20MHz)
Mode 3 (MCLK = 20MHz)
Mode 0
Mode 3 (MCLK = 32MHz)
Mode 0
20
−
−
20
40
0
40
60
80
100
−
−
20
40
0
20
40
60
80
_
Temperature ( C)
_
Temperature ( C)
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
POWER−SUPPLY CURRENT vs TEMPERATURE
Mode 3 (MCLK = 32MHz)
Mode 0
10
9
18
16
14
12
10
8
110
98
86
74
62
50
38
26
Sinc3 Filter
8
Mode 3 (MCLK = 20MHz)
Sinc2 Filter
7
6
6
5
4
−
−
20
40
0
20
40
60
80
10
100
1k
10k
_
Temperature ( C)
Decimation Ratio (OSR)
10
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TYPICAL CHARACTERISTICS (continued)
3
AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless
otherwise noted.
SPURIOUS−FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(Mode 0)
SPURIOUS−FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(Mode 3, MCLK = 20MHz)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
105
103
101
99
105
103
101
99
105
103
101
99
105
103
101
99
0.5VPP
5kHz
97
97
97
97
SFDR
THD
95
95
95
95
SFDR
THD
93
93
93
93
91
91
91
91
89
89
89
89
0.5VPP
5kHz
87
87
87
87
85
85
85
85
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Tem pe r at ur e ( C)
SPURIOUS−FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE (Mode 3, MCLK = 32MHz)
SPURIOUS−FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(Mode 0)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
105
103
101
99
105
103
101
99
110
100
90
110
100
90
SFDR
SFDR
THD
THD
97
97
80
80
95
95
93
93
70
70
91
91
89
89
60
60
0.5VPP
5kHz
87
87
50
50
85
85
−
−
40
20
0
20
40
60
80
100
1
10
20
_
Temperature ( C)
Frequency (kHz)
SPURIOUS−FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(Mode 3, MCLK = 20MHz)
SPURIOUS−FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(Mode 3, MCLK = 32MHz)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
110
100
90
110
100
90
110
100
90
110
100
90
SFDR
THD
THD
SFDR
80
80
80
80
70
70
70
70
60
60
60
60
OSR = 256
Sinc3 Filter
50
50
50
50
1
10
20
1
10
20
Frequency (kHz)
Frequency (kHz)
11
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TYPICAL CHARACTERISTICS (continued)
3
AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless
otherwise noted.
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 Point FFT, fIN = 1kHz, 0.5VPP
)
(4096 Point FFT, fIN = 5kHz, 0.5VPP)
0
20
40
60
80
0
20
40
60
80
−
−
−
−
−
−
−
−
−
−
−
−
−
−
100
120
140
100
120
140
0
5
10
15
20
0
5
10
15
20
Frequency (kHz)
Frequency (kHz)
CLOCK FREQUENCY vs TEMPERATURE
CLOCK FREQUENCY vs POWER SUPPLY
10.8
10.5
10.2
9.9
10.5
10.3
10.1
9.9
9.6
9.7
9.3
9.5
−
−
20
40
0
20
40
60
80
100
4.5
4.7
4.9
5.1
5.3
5.5
_
Temperature ( C)
Power Supply (V)
COMMON−MODE REJECTION RATIO
vs FREQUENCY
POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
110
105
100
95
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
1
10
100
0.1
1
10
100
Input Frequency (kHz)
Frequency of Power Supply (kHz)
12
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TYPICAL CHARACTERISTICS (continued)
3
AVDD = BVDD = +5V or VDD = +5V, VIN+ = −250mV to +250mV, VIN− = 0V, MCLK input = 20MHz, and 16-bit Sinc filter, with OSR = 256, unless
otherwise noted.
MCLK AND MDAT
MCLK AND MDAT
TYPICAL SOURCE CURRENT
TYPICAL SINK CURRENT
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
5.5V
4.5V
5.5V
5V
5V
4.5V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Output Voltage, VOH (V)
Output Voltage, VOL (V)
REFERENCE VOLTAGE vs TEMPERATURE
2.503
2.502
2.501
2.500
2.499
2.498
2.497
−
−
20
40
0
20
40
60
80
100
_
Temperature ( C)
13
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SBAS318C − JUNE 2004 − REVISED JANUARY 2008
this can only be used in mode 3). The analog input
signal is continuously sampled by the modulator and
compared to an internal voltage reference. A digital
stream, which accurately represents the analog input
voltage over time, appears at the output of the
converter.
GENERAL DESCRIPTION
The ADS1203 is a single-channel, 2nd-order, CMOS
delta-sigma modulator, designed for medium- to
high-resolution A/D conversions from DC to 39kHz with
an oversampling ratio (OSR) of 256. The output of the
converter (MDAT) provides a stream of digital ones and
zeros. The time average of this serial output is
proportional to the analog input voltage.
REFERENCE
Under normal operation, REFIO (pin 1) provides an
internal +2.5V reference to the ADS1203. However, the
ADS1203 can operate with an external reference in the
range of 0.5V to 2.6V, for a corresponding full-scale
range of 0.256 × REFIO, as long as the input does not
The modulator shifts the quantization noise to high
frequencies. A low-pass digital filter should be used at
the output of the delta-sigma modulator. The primary
purpose of the digital filter is to filter out high-frequency
noise. The secondary purpose is to convert the 1-bit
data stream at a high sampling rate into a higher-bit
data word at a lower rate (decimation). A digital signal
processor (DSP), microcontroller (µC), or field
programmable gate array (FPGA) could be used to
implement the digital filter. Figure 6 shows the
ADS1203 connected to a DSP.
exceed the AV + 0.3V value. The recommended input
DD
range is 0.1 × REFIO.
The ADS1203 reference is double-buffered. If the
internal reference is used to drive an external load, it
can only drive a high-impedance load because
R = 20kΩ. If an external reference voltage is used, the
I
external source must be capable of driving the 20kΩ
resistor. To minimize noise, a 0.1µF capacitor should be
connected to REFIO.
The overall performance (speed and accuracy)
depends on the selection of an appropriate OSR and
filter type. A higher OSR produces greater output
accuracy while operating at a lower refresh rate.
Alternatively, a lower OSR produces lower output
accuracy, but operates at a higher refresh rate. This
system allows flexibility with the digital filter design and
is capable of A/D conversion results that have a
dynamic range exceeding 95dB with an OSR = 256.
Reference
Buffer
Voltage
Ω
20k
THEORY OF OPERATION
The differential analog input of the ADS1203 is
implemented with a switched-capacitor circuit. This
circuit implements a 2nd-order modulator stage, which
digitizes the analog input signal into a 1-bit output
stream. The clock source can be internal as well as
external. Different frequencies for this clock allow for a
variety of solutions and signal bandwidths (however,
REFIO
Figure 5. REFIO Voltage Reference Connection
+5V
+3V
DSP
ADS1203
VDDO
M
AVDD
M0
µ
0.1 F
10nF
1nF
BVDD
MCLK
MDAT
BGND
Ω
Ω
27
VIN
VIN
M1
+
SPICLK
SPISIMO
VSSO
−
27
1nF
AGND
Figure 6. Connection Diagram for the ADS1203 Delta-Sigma Modulator Including DSP
14
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28kW
CLKń10MHz
ANALOG INPUT STAGE
Analog Input
ZIN
+
f
(1)
The input impedance becomes a consideration in
designs where the source impedance of the input signal
is high. This may cause a degradation in gain, linearity
and THD. The importance of this effect depends on the
desired system performance. There are two restrictions
The input design topology of the ADS1203 is based on
a fully differential switched-capacitor architecture. This
input stage provides the mechanism to achieve low
system noise, high common-mode rejection (92dB),
and excellent power-supply rejection.
on the analog input signals, V + and V −. If the input
IN
IN
voltage exceeds the range GND – 0.4V to V + 0.3V,
DD
The input impedance of the analog input depends on
the input current must be limited to 10mA because the
input protection diodes on the front end of the converter
will begin to turn on. In addition, the linearity and the
noise performance of the device are ensured only when
the differential analog voltage resides within 250mV;
however, the FSR input voltage is 320mV.
the modulator clock frequency (f
), which is also the
CLK
sampling frequency of the modulator. Figure 7 shows
the basic input structure of the ADS1203. The
relationship between the input impedance of the
ADS1203 and the modulator clock frequency is:
RSW
Ω
350 (typ)
High
Impedance
AIN+
Ω
> 1G
CINT
1.5pF
1.5pF
7pF (typ)
Switching Frequency
= CLK
VCM
CINT
7pF (typ)
RSW
Ω
350 (typ)
High
Impedance
−
AIN
Ω
> 1G
Figure 7. Input Impedance of the ADS1203
15
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Modulator
voltages at X and X . The voltages at X and X are
2 3 2 3
presented to the respective individual integrators. The
output of these integrators progresses in a negative or
The ADS1203 can be operated in four modes. Modes
0, 1, and 2 use the internal clock, which is fixed at
20MHz. The modulator can also be operated with an
external clock in mode 3. In all modes, the clock is
divided by 2 internally and is used as the modulator
clock. The frequency of the external clock can vary from
1MHz to 32MHz to adjust for the clock requirements of
the application.
positive direction. When the value of the signal at X
4
equals the comparator reference voltage, the output of
the comparator switches from negative to positive, or
positive to negative, depending on its original state.
When the output value of the comparator switches from
high to low or vice versa, the 1-bit DAC responds on the
next clock pulse by changing its analog output voltage
The modulator topology is fundamentally a 2nd-order,
switched-capacitor, delta-sigma modulator, such as the
one conceptualized in Figure 8. The analog input
voltage and the output of the 1-bit digital-to-analog
converter (DAC) are differentiated, providing analog
at X , causing the integrators to progress in the
6
opposite direction. The feedback of the modulator to the
front end of the integrators forces the value of the
integrator output to track the average of the input.
fCLK
X2
X3
X4
X(t)
fS
Integrator 1
Integrator 2
DATA
VREF
Comparator
X6
D/A Converter
Figure 8. Block Diagram of the 2nd-Order Modulator
16
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(each with an implemented filter), the two standard
signals (MCLK and MDAT) are provided from the
modulator. To reduce the wiring (for example, for
galvanic isolation), a single line is preferred. Therefore,
in mode 2, the data stream is Manchester-encoded.
DIGITAL OUTPUT
A differential input signal of 0V ideally produces a
stream of ones and zeros that is high 50% of the time
and low 50% of the time. A differential input of +256mV
produces a stream of ones and zeros that is high 80%
of the time. A differential input of –256mV produces a
stream of ones and zeros that is high 20% of the time.
The input voltage versus the output modulator signal is
shown in Figure 9.
MODES OF OPERATION
The system clock of the ADS1203 is 20MHz by default.
The system clock can be provided either from the
internal 20MHz RC oscillator or from an external clock
source. For this purpose, the MCLK pin is bidirectional
and controlled by the mode setting.
DIGITAL INTERFACE
INTRODUCTION
The system clock is divided by 2 for the modulator
clock. Therefore, the default clock frequency of the
modulator is 10MHz. With a possible external clock
range of 1MHz to 32MHz, the modulator operates
between 500kHz and 16MHz.
The analog signal that is connected to the input of the
delta-sigma modulator is converted using the clock
signal applied to the modulator. The result of the
conversion, or modulation, is the output signal DATA
from the delta-sigma modulator. In most applications
where a direct connection is realized between the
delta-sigma modulator and an ASIC, FPGA, DSP, or µC
The four modes of operation for the digital data interface
are shown in Table 1.
Modulator Output
+FS (Analog Input)
−
FS (Analog Input)
Analog Input
Figure 9. Analog Input vs Modulator Output of the ADS1203
Table 1. Digital Data Interface Modes of Operation
MODE
DEFINITION
M1
M0
0
1
2
3
Internal clock, synchronous data output
Low
Low
High
High
Low
High
Low
High
Internal clock, synchronous data output, half output clock frequency
Internal clock, Manchester-encoded data output
External clock, synchronous data output
17
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Mode 0
This filter provides the best output performance at the
lowest hardware size (for example, count of digital
gates). For oversampling ratios in the range of 16 to
256, this is a good choice. All the characterizations in
the data sheet are also done using a sinc filter with an
oversampling ratio of OSR = 256 and an output word
width of 16 bits.
In mode 0, the internal RC oscillator is running. The data
are provided at the MDAT output pin, and the modulator
clock at the MCLK pin. The data change at the falling
edge of MCLK; therefore, the data can safely be
strobed with the rising edge. See Figure 1 on page 7.
3
Mode 1
3
In a sinc filter response (shown in Figure 10 and
In mode 1, the internal RC oscillator is running. The data
are provided at the MDAT output pin. The MCLK pin
provides the half modulator clock. The data must be
strobed at both the rising and falling edges of MCLK.
The data at MDAT change in the middle, between the
rising and falling edge. In this mode the frequency of
both MCLK and MDAT is only 5MHz. See Figure 2 on
page 7.
Figure 11), the location of the first notch occurs at the
frequency of output data rate f
= f
/OSR. The
CLK
DATA
–3dB point is located at half the Nyquist frequency or
/4. For some applications, it may be necessary to
f
DATA
use another filter type for better frequency response.
This performance can be improved, for example, by a
cascaded filter structure. The first decimation stage can
3
be a sinc filter with a low OSR and the second stage
Mode 2
a high-order filter.
In mode 2, the internal RC oscillator is running. The data
are Manchester-encoded and are provided at the
MDAT pin. The MCLK output is set to low. There is no
clock output provided in this mode. The Manchester
coding allows the data transfer with only a single line.
See Figure 3 on page 8.
0
OSR = 32
fDATA = 10MHz/32 = 312.5kHz
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
−
3dB: 81.9kHz
Mode 3
In mode 3, the internal RC oscillator is disabled. The
system clock must be provided externally at the input
MCLK. The system clock must have twice the
frequency of the chosen modulator clock. The data are
provided at the MDAT output pin. Because the
modulator runs with the half system clock, the data
change at every other falling edge of the external clock.
The data can safely be strobed at every other rising
edge of MCLK. This mode allows synchronous
operation to any digital system or the use of clocks
different from 10MHz. See Figure 4 on page 8. On the
QFN package, the modulator clock is provided as the
CLKOUT signal. Output data can be strobed at each
rising edge of CLKOUT.
0
200
400
600
800 1000 1200 1400 1600
Frequency (kHz)
3
Figure 10. Frequency Response of Sinc Filter
30k
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
25k
Settling Time =
20k
×
µ
1/fDATA = 9.6 s
3
FILTER USAGE
15k
10k
5k
The modulator generates only a bitstream, which does
not output a digital word like an analog-to-digital
converter (ADC). In order to output a digital word
equivalent to the analog input voltage, the bitstream
must be processed by a digital filter.
0
0
5
10
15
20
25
30
35
40
A very simple filter built with minimal effort and
hardware is the sinc filter:
Number of Output Clocks
3
3
3
Figure 11. Pulse Response of Sinc Filter
(f = 10MHz)
1 * z−OSR
H(z) + ǒ 1 * z−1
Ǔ
MOD
(2)
18
ꢚ ꢗꢘ ꢍꢔ ꢑꢛ
www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
The effective number of bits (ENOB) can be used to
compare the performance of ADCs and delta-sigma
modulators. Figure 12 shows the ENOB of the
ADS1203 with different filter types. In this data sheet,
the ENOB is calculated from the SNR:
clocks. The data clock is equal to the modulator clock
divided by the OSR. For overcurrent protection, filter
3
types other than sinc might be a better choice. A simple
2
example is a sinc filter. Figure 13 compares the settling
time of different filter types. The sincfast is a modified
2
sinc filter:
SNR = 1.76dB + 6.02dB × ENOB
(3)
2
1 * z−OSR
ǒ
−2 OSRǓ
H(z) + ǒ 1 * z−1
Ǔ
1 ) z
(4)
16
sinc3
10
9
8
7
6
5
4
3
2
1
0
sinc3
14
sincfast
12
sinc2
sincfast
10
8
sinc2
6
sinc
sinc
4
2
0
1
10
100
1000
0
1
2
3
4
5
6
7
8
9
10
OSR
µ
Settling Time ( s)
Figure 12. Measured ENOB vs OSR
Figure 13. Measured ENOB vs Settling Time
In motor control applications, a very fast response time
for overcurrent detection is required. There is a
constraint between 1µs and 5µs with 3 bits to 7 bits
resolution. The time for full settling depends on the filter
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications,
available for download at www.ti.com.
3
order. Therefore, the full settling of the sinc filter needs
2
three data clocks and the sinc filter needs two data
19
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www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
The DSP (such as a C28x or C24x) can be directly
connected at the output of two channels of the
optocoupler. In this configuration, the signals arriving at
C28x or C24x are standard delta-sigma modulator
signals and are connected directly to the SPICLK and
SPISIMO pins. Being a delta-sigma converter, there is
no need to have word sync on the serial data, so an SPI
is ideal for connection. McBSP would work as well in
SPI mode.
APPLICATIONS
Operating the ADS1203 in a typical application using
mode 0 is shown in Figure 14. Measurement of the
motor phase current is done through the shunt resistor.
For better performance, both signals are filtered. R2 and
C2 filter noise on the noninverting input signal, R3 and C3
filter noise on the inverting input signal, and C4 in
combination with R2 and R3 filter the differential input
signal. In this configuration, the shunt resistor is
connected via three wires with the ADS1203.
When component reduction is necessary, the ADS1203
can operate in mode 2, as shown in Figure 15. M1 is
high and M0 is low. Only the noninverting input signal
is filtered. R2 and C2 filter noise on the input signal. The
inverting input is directly connected to the GND pin,
which is simultaneously connected to the shunt resistor.
The power supply is taken from the upper gate driver
power supply. A decoupling capacitor of 0.1µF is
recommended for filtering the power supply. If better
filtering is required, an additional 1µF to 10µF capacitor
can be added.
The output signal from the ADS1203 is
Manchester-encoded. In this case, only one signal is
transmitted. For that reason, one optocoupler channel
is used instead of two channels, as in the previous
example of Figure 14. Another advantage of this
configuration is that the DSP will use only one line per
channel instead of two. That permits the use of smaller
DSP packages in the application.
The control lines M0 and M1 are both low while the part
is operating in mode 0. Two output signals, MCLK and
MDAT, are connected directly to the optocoupler. The
optocoupler can be connected to transfer a direct or
inverse signal because the output stage has the
capacity to source and sink the same current. The
discharge resistor is not needed in parallel with
optocoupler diodes because the output driver has
push-pull capability to keep the LED diode out of the
charge.
Floating
Power Supply
HV+
Gate
Drive
R1
Circuit
C28x
or
C24x
R5
Optocoupler
D1
5.1V
C1
µ
0.1 F
ADS1203
M0 VDD
R4
C4
10nF
R2
Ω
27
SPICLK
VIN
VIN
M1
+
MCLK
MDAT
GND
−
SPISIMO
RSENSE
R3
C2
1nF
C3
1nF
Ω
27
Power Supply
Gate
Drive
Circuit
−
HV
Figure 14. Application Diagram in Mode 0
20
ꢚ ꢗꢘ ꢍꢔ ꢑꢛ
www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
Floating
Power Supply
HV+
Gate
Drive
Circuit
R1
D1
5.1V
C1
µ
0.1 F
ADS1203
M0 VDD
R4
R2
Optocoupler
Ω
27
C28x
or
C24x
VIN
VIN
M1
+
MCLK
MDAT
GND
−
C2
0.1 F
RSENSE
µ
Power
Supply
Gate
Drive
Circuit
−
HV
Figure 15. Application Diagram in Mode 2
Floating
Power Supply
HV+
C28x
or
C24x
Gate Drive
Circuit
CVDD
C1
0.1 F
ADS1203
µ
R2
VDD
MCLK
MDAT
GND
M0
VIN
VIN
M1
Ω
27
SPICLK
+
+
SPISIMO
−
C2
0.1 F
RSENSE
µ
−
DVDD
Figure 16. Application Diagram without Galvanic Isolation in Mode 0
21
ꢚ
ꢗ
ꢘ
ꢍ
ꢔ
ꢑ
ꢛ
www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
ADS1203
+5V
C4
0.1 F
BVDD
AVDD
R1
µ
M0
VIN
VIN
M1
REFIO
MCLK
MDAT
BGND
Ω
27
+
+
−
C1
0.1 F
RSENSE
µ
AGND
−
ADS1203
+5V
C5
0.1 F
BVDD
AVDD
M0
R2
µ
REFIO
Ω
27
VIN
VIN
M1
+
MCLK
MDAT
BGND
+
−
C2
0.1 F
RSENSE
µ
−
AGND
C28x
or
+3V
C24x
CVDD
ADS1203
C6
+5V
µ
0.1 F
SPICLK
AVDD
M0
BVDD
REFIO
MCLK
MDAT
BGND
SPISIMO
SPISIMO
SPISIMO
R3
Ω
27
VIN
VIN
M1
+
+
−
C3
0.1 F
RSENSE
µ
−
CLK
AGND
DVDD
Figure 17. Application Diagram without Galvanic Isolation in Mode 3
22
ꢚ ꢗꢘ ꢍꢔ ꢑꢛ
www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
is on, series resistors should be used to limit the input
current. Experimentation may be the best way to
determine the appropriate connection between the
ADS1203 and different power supplies.
LAYOUT CONSIDERATIONS
Power Supplies
The ADS1203 requires only one power supply (V ). If
DD
there are separate analog and digital power supplies on
the board, a good design approach is to have the
ADS1203 connected to the analog power supply.
Another possible approach to control noise is the use of
a resistor on the power supply. The connection can be
made between the ADS1203 power-supply pins via a
10Ω resistor. The combination of this resistor and the
decoupling capacitors between the power-supply pins
on the ADS1203 provide some filtering. The analog
supply that is used must be well-regulated and generate
low noise. For designs requiring higher resolution from
the ADS1203, power-supply rejection will be a concern.
The digital power supply has high-frequency noise that
can be capacitively coupled into the analog portion of
the ADS1203. This noise can originate from switching
power supplies, microprocessors, or DSPs.
High-frequency noise will generally be rejected by the
external digital filter at integer multiples of MCLK. Just
below and above these frequencies, noise will alias
back into the passband of the digital filter, affecting the
Grounding
Analog and digital sections of the design must be
carefully and cleanly partitioned. Each section should
have its own ground plane with no overlap between
them. Do not join the ground planes; instead, connect
the two with a moderate signal trace underneath the
converter. For multiple converters, connect the two
ground planes as close as possible to one central
location for all of the converters. In some cases,
experimentation may be required to find the best point
to connect the two planes together.
Decoupling
Good decoupling practices must be used for the
ADS1203 and for all components in the design. All
decoupling capacitors, specifically the 0.1µF ceramic
capacitors, must be placed as close as possible to the
pin being decoupled. A 1µF and 10µF capacitor, in
parallel with the 0.1µF ceramic capacitor, can be used
to decouple V to GND. At least one 0.1µF ceramic
capacitor must be used to decouple V
well as for the digital supply on each digital component.
DD
conversion result. Inputs to the ADS1203, such as V +,
IN
to GND, as
DD
V −, and MCLK should not be present before the power
IN
supply is on. Violating this condition could cause
latch-up. If these signals are present before the supply
23
ꢚꢗ ꢘꢍ ꢔ ꢑ ꢛ
www.ti.com
SBAS318C − JUNE 2004 − REVISED JANUARY 2008
Revision History
DATE
REV
PAGE
SECTION
Features
DESCRIPTION
1
Changed upper Operating Temperature Range from +85°C to +125°C.
Absolute Maximum
Ratings
Changed upper Operating Free−Air Temperature Range from +85°C to +125°C.
Recommended Operating
Conditions
Changed upper Operating Junction Temperature Range from +105°C to +150°C.
2
Deleted R
θJA
column.
Dissipation Ratings
Changed values.
1/08
C
Changed condition; upper temperature range from +85°C to +125°C.
Added rows with values for updated temperature range.
Changed values throughout table.
3
Electrical Characteristics
Changed notes 5, 7, and 8.
Parameter Measurement
Information
Changed upper temperature range for all four timing characteristics tables from
+85°C to +125°C.
7, 8
5
6
Equivalent Input Circuit
Pin Assignments
Moved Equivalent Input Circuit figure to bottom of page 5.
Added note to QFN package.
8/07
B
:
NOTE Page numbers for previous revisions may differ from page numbers in the current version.
24
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS1203IPWR
ADS1203IPWRG4
ADS1203IPWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
8
8
2000
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
PW
8
Green (RoHS
& no Sb/Br)
ADS1203IPWTG4
ADS1203IRGTT
ADS1203IRGTTG4
PW
8
250
Green (RoHS
& no Sb/Br)
RGT
RGT
16
16
250
Green (RoHS
& no Sb/Br)
QFN
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1203IPWR
ADS1203IPWT
ADS1203IRGTT
TSSOP
TSSOP
QFN
PW
PW
8
8
2000
250
330.0
330.0
330.0
12.4
12.4
12.4
7.0
7.0
3.3
3.6
3.6
3.3
1.6
1.6
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q2
RGT
16
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1203IPWR
ADS1203IPWT
ADS1203IRGTT
TSSOP
TSSOP
QFN
PW
PW
8
8
2000
250
340.5
340.5
338.1
338.1
338.1
338.1
20.6
20.6
20.6
RGT
16
250
Pack Materials-Page 2
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