ADS1204 [TI]
FOUR 1-BIT, 10MHZ, 2ND-ORDER, DELTA-SIGMA MODULATORS; 四个1位， 10MHZ ， 2阶Δ-Σ调制器
| 型号： | ADS1204 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FOUR 1-BIT, 10MHZ, 2ND-ORDER, DELTA-SIGMA MODULATORS |
| 文件： | 总21页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢚ
ꢓ
ꢖ
ꢄ
ꢎ
ꢊ
ꢛ
SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢄꢊ ꢋꢌ ꢍꢉ ꢎꢏ ꢐꢅ ꢑꢃ ꢐ ꢒꢃꢉ
ꢓ ꢒ ꢔꢈ ꢕ ꢅ ꢖꢇ ꢗꢘ ꢕ ꢋ ꢁꢐꢂꢔ ꢕ ꢈꢁ ꢃꢙ
FEATURES
DESCRIPTION
D
D
D
16-Bit Resolution
The ADS1204 is a four-channel, high-performance device,
with four delta-sigma (∆Σ) modulators with 100dB dynamic
range, operating from a single +5V supply. The differential
inputs are ideal for direct connection to transducers in an
industrial environment. With the appropriate digital filter
and modulator rate, the device can be used to achieve
16-bit analog-to-digital (A/D) conversion with no missing
code. Effective resolution of 12 bits can be obtained with
a digital filter data rate of 160kHz at a modulator rate of
10MHz. The ADS1204 is designed for use in medium- to
high-resolution measurement applications including
current measurements, smart transmitters, industrial
process control, weight scales, chromatography, and
portable instrumentation. It is available in a QFN-32 (5x5)
package.
14-Bit Linearity
Resolution/Speed Trade-Off:
10-Bit Effective Resolution with 10µs Signal
Delay (12-Bit with 19µs)
D
D
D
D
D
D
D
D
2.5V Input Range at 2.5V
Internal Reference Voltage: 2%
Gain Error: 0.5%
Four Independent Delta-Sigma Modulators
Four Input Reference Buffers
Onboard 20MHz Oscillator
Selectable Internal or External Clock
Operating Temperature Range:
−40°C to +85°C
QFN-32 (5x5) Package
AVDD
BVDD
D
OUT A
OUT B
OUT C
OUT D
CH A+
2nd−Order
APPLICATIONS
Output
Interface
Circuit
∆Σ
Modulator
−
CH A
D
D
D
D
D
D
D
D
Motor Control
Current Measurement
Industrial Process Control
Instrumentation
REFIN A
CLKOUT
CH B+
2nd−Order
∆Σ
Modulator
−
CH B
Smart Transmitters
Portable Instruments
Weight Scales
REFIN B
Divider
CH C+
2nd−Order
Pressure Transducers
∆Σ
Modulator
−
CH C
CLKIN
Clock
Select
REFIN C
CLKSEL
CH D+
2nd−Order
∆Σ
Modulator
−
CH D
Out EN
RC
Oscillator
20MHz
REFIN D
REFOUT
Reference
Voltage
2.5V
AGND
BGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢜꢝ ꢑ ꢓꢞ ꢟ ꢠꢡ ꢑꢢ ꢓ ꢚꢠꢚ ꢇꢏ ꢣꢁ ꢃ ꢘꢕ ꢈꢇꢁꢏ ꢇꢙ ꢤꢂ ꢃ ꢃ ꢒꢏꢈ ꢕꢙ ꢁꢣ ꢥꢂꢦ ꢔꢇꢤ ꢕꢈꢇ ꢁꢏ ꢐꢕ ꢈꢒꢧ ꢜꢃ ꢁꢐꢂ ꢤꢈꢙ
ꢤ ꢁꢏ ꢣꢁꢃ ꢘ ꢈꢁ ꢙ ꢥꢒ ꢤ ꢇ ꢣꢇ ꢤ ꢕ ꢈꢇ ꢁꢏꢙ ꢥ ꢒꢃ ꢈꢨꢒ ꢈꢒ ꢃ ꢘꢙ ꢁꢣ ꢠꢒꢩ ꢕꢙ ꢡꢏꢙ ꢈꢃ ꢂꢘ ꢒꢏꢈ ꢙ ꢙꢈ ꢕꢏꢐ ꢕꢃ ꢐ ꢪ ꢕꢃ ꢃ ꢕ ꢏꢈꢫꢧ
ꢜꢃ ꢁ ꢐꢂꢤ ꢈ ꢇꢁ ꢏ ꢥꢃ ꢁ ꢤ ꢒ ꢙ ꢙ ꢇꢏ ꢗ ꢐꢁ ꢒ ꢙ ꢏꢁꢈ ꢏꢒ ꢤꢒ ꢙꢙ ꢕꢃ ꢇꢔ ꢫ ꢇꢏꢤ ꢔꢂꢐ ꢒ ꢈꢒ ꢙꢈꢇ ꢏꢗ ꢁꢣ ꢕꢔ ꢔ ꢥꢕ ꢃ ꢕꢘ ꢒꢈꢒ ꢃ ꢙꢧ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
ꢚꢓ ꢖꢄ ꢎ ꢊ ꢛ
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR
MAXIMUM
GAIN
ERROR (%)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
(1)
(LSB)
ADS1204IRHBT
ADS1204IRHBR
Tape and Reel, 250
Tape and Reel, 3000
ADS1204
3
0.5
QFN-32
RHB
−40°C to +85°C
ADS1204I
(1)
For the most current specification and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
ADS1204
−0.3 to 6
−0.3 to 6
UNIT
V
Supply Voltage, AV
Supply Voltage, BV
to AGND
to BGND
DD
DD
V
Analog Input Voltage with Respect to AGND
Reference Input Voltage with Respect to AGND
Digital Input Voltage with Respect to BGND
Ground Voltage Difference, AGND to BGND
AGND − 0.3 to AV
AGND − 0.3 to AV
+ 0.3
V
V
DD
+ 0.3
+ 0.3
DD
BGND − 0.3 to BV
V
DD
0.3
−0.3 to 6
10
V
Voltage Differences, BV
DD
to AGND
V
Input Current to Any Pin Except Supply
mA
Power Dissipation
See Dissipation Rating Table
−40 to +150
Operating Virtual Junction Temperature Range, T
°C
°C
°C
°C
J
Operating Free-Air Temperature Range, T
−40 to +85
A
Storage Temperature Range, T
STG
Lead Temperature (1.6mm or 1/16″ from case for 10s)
−65 to +150
260
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
4.75
2.7
4.5
0.5
0
NOM
MAX
5.25
3.6
UNIT
V
Supply Voltage, AV
to AGND
to BGND
5
DD
DD
Low-Voltage Levels
5V Logic Levels
V
Supply Voltage, BV
5
5.5
V
Reference Input Voltage
Operating Common-Mode Signal
Analog Inputs
2.5
2.6
V
AV
DD
REFIN
V
+IN − (−IN)
0
V
(1)
External Clock
16
20
24
MHz
°C
Operating Junction Temperature Range, T
−40
105
J
(1)
With reduced accuracy, clock can go from 1MHz up to 32MHz; see Typical Characteristic curves.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
(1)
T
= 70°C
T = 85°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
A
QFN-32 (5x5)
2725mW
27.25mW/°C
1499mW
1090mW
(1)
This is the inverse of the traditional junction-to-ambient thermal resistance (R
informational purposes only.
). Thermal resistances are not production tested and are for
qJA
2
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1204I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
Resolution
TEST CONDITIONS
16
Bits
DC Accuracy
1
3
LSB
(2)
Integral linearity error
INL
0.001
0.005 % FSR
LSB
0.009 % FSR
6
Integral linearity match
(3)
DNL
Differential nonlinearity
Input offset error
1
3
2
8
LSB
mV
V
OS
−1.4
Input offset error match
Input offset error drift
mV
TCV
OS
2
0.08
0.185
2
µV/°C
(4)
Gain error
G
Referenced to V
0.5 % FSR
0.5 % FSR
ppm/°C
ERR
REF
Gain error match
TCG
ERR
Gain error drift
PSRR
Power-supply rejection ratio
4.75V < AV
DD
< 5.25V
78
dB
Analog Input
FSR
Full-scale differential range
Specified differential range
Maximum operating input range
Input capacitance
(CH x+) − (CH x−); CH x− = 2.5V
(CH x+) − (CH x−); CH x− = 2.5V
2.5
2
V
V
(3)
0
AV
V
DD
Common-mode
CLK turned off
3
pF
nA
kΩ
pF
dB
dB
MHz
Input leakage current
1
Differential input resistance
Differential input capacitance
100
2.5
100
110
50
At DC
CMRR
BW
Common-mode rejection ratio
Bandwidth
V
IN
=
1.25V at 40kHz
PP
FS sine wave, −3dB
Sampling Dynamics
Internal clock frequency
CLKSEL = 1
CLKSEL = 0
8
1
10
20
12
24
MHz
MHz
CLKIN
AC Accuracy
THD
External clock frequency
Total harmonic distortion
Spurious-free dynamic range
Signal-to-noise ratio
V
IN
V
IN
V
IN
V
IN
V
IN
=
=
=
=
=
2V
PP
2V
PP
2V
PP
2V
PP
2V
PP
at 5kHz
at 5kHz
at 5kHz
at 5kHz
at 50kHz
−96
100
89
−88
dB
dB
dB
dB
dB
Bits
SFDR
92
86
85
SNR
SINAD
Signal-to-noise + distortion
89
(3)
Channel-to-channel isolation
Effective number of bits
85
ENOB
(1)
14
14.5
All typical values are at T = +25°C.
A
(2)
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
(3)
(4)
(5)
(6)
Maximum values, including temperature drift, are ensured over the full specified temperature range.
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
3
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV
DD
= 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1204I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
TEST CONDITIONS
−40°C to +85°C
f = 0.1Hz to 10Hz, C = 10µF
Voltage Reference Output
V
Reference voltage output
2.450
2.5
20
2.550
V
ppm/°C
µVrms
µVrms
dB
OUT
dV
/dT Output voltage temperature drift
OUT
10
L
Output voltage noise
f =10Hz to 10kHz, C = 10µF
12
L
PSRR
Power-supply rejection ratio
Output current
60
I
I
10
µA
OUT
SC
Short-circuit current
Turn-on settling time
0.5
100
mA
to 0.1% at C = 0
µs
L
Voltage Reference Input
V
IN
Reference voltage input
0.5
2.5
100
5
2.6
1
V
Reference input resistance
Reference input capacitance
MΩ
pF
µA
Reference input current
(5)
Digital Inputs
Logic family
CMOS with Schmitt Trigger
0.7×BV BV +0.3
V
IH
V
IL
High-level input voltage
Low-level input voltage
Input current
V
V
DD DD
−0.3
0.3×BV
DD
50
I
V = BV
I DD
or GND
nA
pF
IN
C
Input capacitance
5
I
(5)
Digital Outputs
Logic family
CMOS
V
V
High-level output voltage
Low-level output voltage
Output capacitance
Load capacitance
Data format
BV
BV
= 4.5V, I
= 4.5V, I
= −100µA
= +100µA
4.44
V
V
OH
OL
DD
DD
OH
OL
0.5
30
C
5
pF
pF
O
L
C
Bit Stream
(1)
(2)
All typical values are at T = +25°C.
A
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(3)
(4)
(5)
(6)
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
4
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, BV = 3V, CH x+ = 0.5V to 4.5V, CH x− = 2.5V,
DD
DD
3
REFIN = REFOUT = internal +2.5V, CLKIN = 20MHz, and 16-bit Sinc filter with decimation by 256, unless otherwise noted.
ADS1204I
(1)
TYP
MIN
MAX
UNITS
PARAMETER
Digital Inputs
TEST CONDITIONS
(6)
Logic family
LVCMOS
V
V
High-level input Voltage
Low-level input voltage
Input current
BV
BV
= 3.6V
2
BV +0.3
DD
V
V
IH
IL
DD
DD
= 2.7V
or GND
−0.3
0.8
I
IN
V = BV
I DD
50
nA
pF
C
Input capacitance
5
I
(6)
Digital Outputs
Logic family
LVCMOS
V
V
High-level output voltage
Low-level output voltage
Output capacitance
Load capacitance
Data format
BV
BV
= 2.7V, I
= 2.7V, I
= −100µA
= +100µA
BV −0.2
DD
V
V
OH
DD
DD
OH
OL
0.2
30
OL
C
C
5
pF
pF
O
L
Bit Stream
Power Supply
AV
DD
Analog supply voltage
4.5
2.7
4.5
5.5
3.6
5.5
30
V
Low-voltage levels
5V logic levels
CLKSEL = 1
V
BV
DD
Buffer I/O supply voltage
V
22.5
22.4
mA
mA
mA
mA
mW
mW
AI
DD
Analog operating supply current
Buffer I/O operating supply current
Power dissipation
CLKSEL = 0
29
BV
BV
= 3V, CLKOUT = 10MHz
= 5V, CLKOUT = 10MHz
4
DD
BI
DD
4
DD
CLKSEL = 0
CLKSEL = 1
122
145
150
112.5
(1)
(2)
All typical values are at T = +25°C.
A
Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve
for CH x+ = −2V to +2V at 2.5V, expressed either as the number of LSBs or as a percent of measured input range (4V).
Ensured by design.
Maximum values, including temperature drift, are ensured over the full specified temperature range.
Applicable for 5.0V nominal supply: BV
Applicable for 3.0V nominal supply: BV
(3)
(4)
(5)
(6)
(min) = 4.5V and BV
(min) = 2.7V and BV
(max) = 5.5V.
(max) = 3.6V.
DD
DD
DD
DD
EQUIVALENT INPUT CIRCUIT
BVDD
AVDD
C(SAMPLE)
1pF
RON
Ω
650
AIN
DIN
Diode Turn−On Voltage: 0.35V
AGND
Equivalent Analog Input Circuit
BGND
Equivalent Digital Input Circuit
5
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
PIN ASSIGNMENTS
QFN PACKAGE
(TOP VIEW)
1
24
23
22
CH A+
OUT A
OUT B
OUT C
−
2
3
4
5
6
7
8
CH A
CH B+
−
−
CH B
21 OUT D
20
19 BGND
ADS1204
CH C
CLKOUT
CH C+
−
18
17
CH D
BVDD
CH D+
CLKIN
Terminal Functions
TERMINAL
TERMINAL
NAME
NAME
NO. I/O
DESCRIPTION
NO. I/O
DESCRIPTION
CH A+
CH A−
CH B+
CH B−
CH C−
CH C+
CH D−
CH D+
REFIN D
1
2
3
4
5
6
7
8
9
AI
AI
AI
AI
AI
AI
AI
AI
AI
Analog input of channel A: noninverting input
CLKIN
17
18
19
20
21
22
23
24
25
26
27
28
I
External clock input
Analog input of channel A: inverting input
Analog input of channel B: noninverting input
Analog input of channel B: inverting input
Analog input of channel C: inverting input
Analog input of channel C: noninverting input
Analog input of channel D: inverting input
Analog input of channel D: noninverting input
BV
DD
P
Digital interface power supply; from 2.7V to 5.5V
Interface ground
BGND
CLKOUT
OUT D
OUT C
OUT B
OUT A
NC
O
O
O
O
O
System clock output
Bit stream from channel D modulator
Bit stream from channel C modulator
Bit stream from channel B modulator
Bit stream from channel A modulator
No connection; this pin is left unconnected
Analog ground
Reference voltage input of channel D:
pin for external reference voltage
AGND
REFIN C
10
AI
Reference voltage input of channel C:
pin for external reference voltage
AV
DD
P
Analog power supply; nominal 5V
REFOUT
AO Reference voltage output: output pin of the
internal reference source; nominal 2.5V
AGND
11
12
13
14
15
16
Analog ground
AV
DD
P
P
I
Analog power supply; nominal 5V
No connection; this pin is left unconnected
Analog power supply; nominal 5V
Analog ground
AV
DD
29
30
31
P
Analog power supply; nominal 5V
Analog ground
NC
AV
AGND
DD
REFIN B
AI
AI
Reference voltage input of channel B:
pin for external reference voltage
AGND
CLKSEL
Clock select between internal clock (CLKSEL = 1)
or external clock (CLKSEL = 0)
REFIN A
32
Reference voltage input of channel A:
pin for external reference voltage
:
NOTE AI = Analog Input; AO = Analog Output; I = Input; O = Output; P = Power Supply.
6
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PARAMETER MEASUREMENT INFORMATION
tC1
CLKIN
tW1
tD1
tD2
tC2
CLKOUT
OUT x
tW2
tD3
tD4
Figure 1. ADS1204 Timing Diagram
TIMING REQUIREMENTS: 5.0V
over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, and BV = 5V, unless otherwise noted.
DD
DD
PARAMETER
MIN
41.6
10
MAX UNIT
t
t
t
CLKIN period
1000
− 10
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
C1
W1
C2
CLKIN high time
t
C1
CLKOUT period using internal oscillator (CLKSEL = 1)
CLKOUT period using external clock (CLKSEL = 0)
CLKOUT high time
83
2 × t
C1
t
t
t
t
t
(t /2) − 5 (t /2) + 5
C2 C2
W2
D1
D2
D3
D4
CLKOUT rising edge delay after CLKIN rising edge
CLKOUT falling edge delay after CLKIN rising edge
Data valid delay after rising edge of CLKOUT (CLKSEL = 1)
Data valid delay after rising edge of CLKOUT (CLKSEL = 0)
0
0
10
10
(t /4) − 8 (t /4) + 8
C2 C2
t
− 3
t
+ 7
W1
W1
:
NOTE Applicablefor 5.0V nominal supply: BV
DD
(min) = 4.5V and BV (max) = 5.5V. All input signals are specified with t = t = 5ns (10% to
DD R F
90% of BV ) and timed from a voltage level of (V + V )/2. See timing diagram.
DD
IL
IH
TIMING REQUIREMENTS: 3.0V
over recommended operating free-air temperature range at −40°C to +85°C, AV
= 5V, and BV = 3V, unless otherwise noted.
DD
DD
PARAMETER
MIN
41.6
10
MAX UNIT
t
t
t
CLKIN period
1000
− 10
125
ns
ns
ns
ns
ns
ns
ns
ns
ns
C1
W1
C2
CLKIN high time
t
C1
CLKOUT period using internal oscillator (CLKSEL = 1)
CLKOUT period using external clock (CLKSEL = 0)
CLKOUT high time
83
2 × t
C1
t
t
t
t
t
(t /2) − 5 (t /2) + 5
C2 C2
W2
D1
D2
D3
D4
CLKOUT rising edge delay after CLKIN rising edge
CLKOUT falling edge delay after CLKIN rising edge
Data valid delay after rising edge of CLKOUT (CLKSEL = 1)
Data valid delay after rising edge of CLKOUT (CLKSEL = 0)
0
0
10
10
(t /4) − 8 (t /4) + 8
C2 C2
t
− 3
t
+ 7
W1
W1
:
NOTE Applicablefor 3.0V nominal supply: BV
DD
(min) = 2.7V and BV (max) = 3.6V. All input signals are specified with t = t = 5ns (10% to
DD R F
90% of BV ) and timed from a voltage level of (V + V )/2. See timing diagram.
DD IL IH
7
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TYPICAL CHARACTERISTICS
3
= 5V, BV = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc filter, with OSR = 256, unless
DD
AV
DD
otherwise noted.
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(CLKIN = 20MHz)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
(CLKIN = 32MHz)
1.5
1.0
0.5
0
1.5
1.0
0.5
0
−
_
40 C
_
+85 C
_
+85 C
_
+25 C
−
_
40 C
_
+25 C
−
−
−
−
−
−
0.5
1.0
1.5
0.5
1.0
1.5
−
−
−
−
−
−
−
−
−
−
2.5 2.0 1.5 1.0 0.5
0
0.5 1.0 1.5 2.0 2.5
2.5 2.0 1.5 1.0 0.5
0
0.5 1.0 1.5 2.0 2.5
Differential Input Voltage (V)
Differential Input Voltage (V)
INTEGRAL LINEARITY MATCH OF CHANNELS
vs INPUT SIGNAL
INTEGRAL LINEARITY vs TEMPERATURE
0.4
0.3
0.2
0.1
0
0.00061
0.00046
0.00031
0.00015
0
1.5
1.2
0.9
0.6
0.3
0
0.0023
0.0018
0.0014
0.0009
0.0005
0
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 20MHz
−
−
−
−
0.1
0.2
0.3
0.00015
0.00031
0.00046
CLKIN = 32MHz
−
−
−0.4
−0.00061
0.5 1.0 1.5 2.0 2.5
−
−
−
−
−
2.5 2.0 1.5 1.0 0.5
0
−40
−20
0
20
40
60
80
100
Differential Input Voltage (V)
Temperature (_C)
OFFSET vs TEMPERATURE
OFFSET MATCH vs TEMPERATURE
−
−
−
−
−
−
−
1.30
1.35
1.40
1.45
1.50
1.55
1.60
0.45
0.44
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
0.35
CLKIN = 20MHz
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 32MHz
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
8
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TYPICAL CHARACTERISTICS (continued)
3
= 5V, BV = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc filter, with OSR = 256, unless
DD
AV
DD
otherwise noted.
OFFSET vs POWER SUPPLY
REFERENCE VOLTAGE vs TEMPERATURE
−
−
−
−
−
−
1.2
1.3
1.4
1.5
1.6
1.7
2.530
2.528
2.526
2.524
2.522
2.520
2.518
2.516
2.514
2.512
2.510
CLKIN = 20MHz
CLKIN = 32MHz
−
−
20
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Power Supply (V)
40
0
20
40
60
80
100
_
Temperature ( C)
GAIN vs TEMPERATURE
GAIN MATCH vs TEMPERATURE
0.5
0.20
0.19
0.18
0.17
0.16
0.15
0.4
0.3
0.2
0.1
0
CLKIN = 32MHz
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 20MHz
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
SIGNAL−TO−NOISE RATIO
vs TEMPERATURE
SIGNAL−TO−NOISE + DISTORTION
vs TEMPERATURE
89.5
89.4
89.3
89.2
89.1
89.0
88.9
88.8
88.7
88.6
88.5
89.2
89.0
88.8
88.6
88.4
88.2
88.0
87.8
87.6
CLKIN = 32MHz
CLKIN = 32MHz
CLKIN = 20MHz
CLKIN = 20MHz
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
9
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TYPICAL CHARACTERISTICS (continued)
3
= 5V, BV = 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc filter, with OSR = 256, unless
DD
AV
DD
otherwise noted.
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(CLKIN = 20MHz)
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs TEMPERATURE
(CLKIN = 32MHz)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
105
103
101
99
105
103
101
99
105
103
101
99
105
103
101
99
SFDR
SFDR
THD
97
97
97
97
95
95
95
95
THD
93
93
93
93
91
91
91
91
89
89
89
89
4VPP
5kHz
4VPP
5kHz
87
87
87
87
85
85
85
85
−
−
−
−
20
40
20
0
20
40
60
80
100
40
0
20
40
60
80
100
_
_
Temperature ( C)
Temperature ( C)
SPURIOUS FREE DYNAMIC RANGE AND
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(CLKIN = 20MHz)
TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
(CLKIN = 32MHz)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
120
110
100
90
120
110
100
90
120
110
100
90
120
110
100
90
SFDR
SFDR
THD
THD
80
80
80
80
70
70
70
70
OSR = 256
Sinc3 Filter
OSR = 256
Sinc3 Filter
60
60
60
60
1
10
100
1
10
100
Frequency (kHz)
Frequency (kHz)
FREQUENCY SPECTRUM
FREQUENCY SPECTRUM
(4096 point FFT fIN = 1kHz, 4VPP
)
(4096 point FFT fIN = 5kHz, 4VPP
)
0
0
−
−
−
−
20
40
60
80
−
−
−
−
20
40
60
80
−
−
−
−
−
100
120
140
160
180
−
−
−
−
−
100
120
140
160
180
0
2
4
6
8
10
12
14
16
18 19
0
2
4
6
8
10
12
14
16
18 19
Frequency (kHz)
Frequency (kHz)
10
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TYPICAL CHARACTERISTICS (continued)
3
= 3V, CH x+ = +0.5V to +4.5V, CH x− = +2.5V, REFIN = external, CLKSEL = 0, and 16-bit Sinc filter, with OSR = 256, unless
DD
AV
DD
= 5V, BV
otherwise noted.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
POWER−SUPPLY CURRENT
vs TEMPERATURE
18
16
14
12
10
8
110
98
86
74
62
50
38
26
30
27
24
21
18
15
Sinc3 Filter
CLKSEL = 0, CLKIN = 32MHz
Sinc2 Filter
CLKSEL = 0, CLKIN = 20MHz
CLKSEL = 1
6
4
−
−
20
10
100
1k
10k
40
0
20
40
60
80
100
_
Decimation Ratio (OSR)
Temperature ( C)
COMMON−MODE REJECTION RATIO
vs FREQUENCY
POWER−SUPPLY REJECTION RATIO
vs FREQUENCY
110
105
100
95
110
100
90
90
85
80
80
70
75
70
60
65
60
1
50
10
100
0.1
1
10
100
Input Frequency (kHz)
Frequency of Power Supply (kHz)
CLOCK FREQUENCY vs TEMPERATURE
CLOCK FREQUENCY vs POWER SUPPLY
10.0
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
8.0
9.8
9.7
9.6
9.5
9.4
9.3
9.2
−
−
20
40
0
20
40
60
80
100
4.5
4.7
4.9
5.1
5.3
5.5
_
Temperature ( C)
Power Supply (V)
11
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
An application-specific integrated circuit (ASIC), or
field-programmable gate array (FPGA) could be used to
implement the digital filter. Figure 2 and Figure 3 show
typical application circuits with the ADS1204 connected to
an FPGA.
GENERAL DESCRIPTION
The ADS1204 is a four-channel, 2nd-order, CMOS device
with four delta-sigma modulators, designed for medium- to
high-resolution A/D signal conversions from DC to 39kHz
(filter response −3dB) if an oversampling ratio (OSR) of 64
is chosen. The output of the converter (OUTX) provides a
stream of digital ones and zeros. The time average of this
serial output is proportional to the analog input voltage.
The overall performance (that is, speed and accuracy)
depends on the selection of an appropriate OSR and filter
type. A higher OSR produces greater output accuracy
while operating at a lower refresh rate. Alternatively, a
lower OSR produces lower output accuracy, but operates
at a higher refresh rate. This system allows flexibility with
the digital filter design and is capable of A/D conversion
results that have a dynamic range exceeding 100dB with
an OSR = 256.
The modulator shifts the quantization noise to high
frequencies. A low-pass digital filter should be used at the
output of the delta-sigma modulator. The filter serves two
functions. First, it filters out high-frequency noise. Second,
the filter converts the 1-bit data stream at a high sampling
rate into a higher-bit data word at a lower rate (decimation).
2 kΩ
AVDD
BVDD
+5V
Ω
5k
5V
27Ω
OUT A
OUT B
OUT C
OUT D
0.1µF
5kΩ
OPA4350
CH A+
2nd−Order
Output
Interface
Circuit
0.1nF
∆Σ
Modulator
−
CH A
2kΩ
FPGA
or
ASIC
REFIN A
CLKOUT
+3V
Ω
2k
CH B+
2nd−Order
∆Σ Modulator
BVDD
CH B−
0.1µF
+5V
BGND
5kΩ
5V
Ω
27
REFIN B
µ
0.1
5k
F
OPA4350
Divider
0.1nF
CH C+
2nd−Order
Ω
Ω
2k
∆Σ Modulator
CH C−
+3V
CLKIN
Clock
REFIN C
Select
Ω
2k
CLKSEL
+5V
CH D+
+5V
2nd−Order
AVDD
AVDD
AVDD
AVDD
Ω
5k
∆Σ
Modulator
−
CH D
+5V
Out EN
0.1µF
5V
27Ω
µ
0.1
F
OPA4350
RC
Oscillator
20MHz
+5V
REFIN D
REFOUT
µ
0.1
F
0.1nF
5kΩ
2kΩ
Reference
Voltage
2.5V
+5V
µ
0.1
F
µ
0.1
F
AGND AGND AGND AGND
2kΩ
0.1µF
+5V
Ω
5k
5V
Ω
27
µ
0.1
F
OPA4350
+5V
0.1nF
Ω
Ω
2k
5k
OPA336
µ
0.1
F
Figure 2. Single-Ended Connection Diagram for the ADS1204 Delta-Sigma Modulator
12
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+5V
Ω
Ω
27
OPA4354
R1
IN+
0.1nF
0.1nF
0.1nF
0.1nF
R2
+5V
27
OPA4354
R1
IN−
R2
AVDD
BVDD
+5V
27Ω
OUT A
CH A+
OPA4354
R1
2nd−Order
OUT B
OUT C
Output
Interface
Circuit
IN+
∆Σ
Modulator
−
CH A
R2
FPGA
or
ASIC
OUT D
REFIN A
CLKOUT
+5V
+3V
CH B+
2nd−Order
BVDD
Ω
27
∆Σ
Modulator
−
CH B
µ
F
OPA4354
0.1
R1
BGND
IN−
REFIN B
R2
Divider
CH C+
2nd−Order
+5V
∆Σ
Modulator
−
CH C
27Ω
+3V
CLKIN
OPA4354
Clock
R1
REFIN C
Select
IN+
CLKSEL
R2
+5V
CH D+
2nd−Order
AVDD
AVDD
AVDD
AVDD
∆Σ Modulator
CH D−
+5V
Out EN
0.1µF
+5V
RC
Oscillator
20MHz
+5V
REFIN D
REFOUT
µ
0.1 F
Ω
27
OPA4354
R1
Reference
Voltage
2.5V
+5V
IN−
µ
F
0.1
R2
µ
0.1 F
AGND AGND AGND AGND
+5V
µ
0.1
F
Ω
Ω
27
OPA4354
R1
IN+
R2
+5V
27
OPA4354
+5V
R1
−
IN
R2
OPA336
µ
0.1
F
Figure 3. Differential Connection Diagram for the ADS1204 Delta-Sigma Modulator
13
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on the desired system performance. There are two
restrictions on the analog input signals, CH x+ and CH x−.
If the input voltage exceeds the range (GND – 0.3V) to
(VDD + 0.3V), the input current must be limited to 10mA
because the input protection diodes on the front end of the
converter will begin to turn on. In addition, the linearity and
the noise performance of the device is ensured only when
the differential analog voltage resides within 2V (with
VREF as a midpoint); however, the FSR input voltage is
2.5V.
THEORY OF OPERATION
The differential analog input of the ADS1204 is
implemented with a switched-capacitor circuit. This circuit
implements a 2nd-order modulator stage, which digitizes
the analog input signal into a 1-bit output stream. The clock
source can be internal as well as external. Different
frequencies for this clock allow for a variety of solutions
and signal bandwidths. Every analog input signal is
continuously sampled by the modulator and compared to
a reference voltage that is applied to the REFINx pin. A
digital stream, which accurately represents the analog
input voltage over time, appears at the output of the
corresponding converter.
Modulator
The ADS1204 can be operated in two modes. When
CKLSEL = 1, the four modulators operate using the internal
clock, which is fixed at 20MHz. When CKLSEL = 0, the
modulators operate using an external clock . In both modes,
the clock is divided by two internally and functions as the
modulator clock. The frequency of the external clock can vary
from 1MHz to 32MHz to adjust for the clock requirements of
the application.
ANALOG INPUT STAGE
Analog Input
The topology of the analog inputs of ADS1204 is based on
fully differential switched−capacitor architecture. This
input stage provides the mechanism to achieve low
system noise, high common-mode rejection (100dB), and
excellent power-supply rejection.
The modulator topology is fundamentally a 2nd-order,
switched-capacitor, delta-sigma modulator, such as the one
conceptualized in Figure 5. The analog input voltage and the
output of the 1-bit digital-to-analog converter (DAC) are
differentiated, providing analog voltages at X2 and X3. The
voltages at X2 and X3 are presented to their individual
integrators. The output of these integrators progresses in a
negative or positive direction. When the value of the signal
at X4 equals the comparator reference voltage, the output of
the comparator switches from negative to positive, or positive
to negative, depending on its original state. When the output
value of the comparator switches from high to low or vice
versa, the 1-bit DAC responds on the next clock pulse by
changing its analog output voltage at X6, causing the
integrators to progress in the opposite direction. The
feedback of the modulator to the front end of the integrators
forces the value of the integrator output to track the average
of the input.
The input impedance of the analog input is dependent on
the modulator clock frequency (fCLK), which is also the
sampling frequency of the modulator. Figure 4 shows the
basic input structure of one channel of the ADS1204. The
relationship between the input impedance of the ADS1204
and the modulator clock frequency is:
100kW
MODń10MHz
ZIN
+
f
(1)
The input impedance becomes a consideration in designs
where the source impedance of the input signal is high.
This high impedance may cause degradation in gain,
linearity, and THD. The importance of this effect depends
Ω
650
High
Impedance
AIN+
Ω
> 1G
1.2pF
1.2pF
0.4pF
0.4pF
VCM
Switching Frequency = CLK
Ω
650
High
Impedance
−
AIN
Ω
> 1G
Figure 4. Input Impedance of the ADS1204
14
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SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
fCLK
X2
X3
X4
X(t)
fS
Integrator 1
Integrator 2
DATA
VREF
Comparator
X6
D/A Converter
Figure 5. Block Diagram of the 2nd-Order Modulator
connection is realized between the delta-sigma modulator
DIGITAL OUTPUT
and an ASIC or FPGA (each with an implemented filter),
the two standard signals per modulator (CLKOUT and
OUTx) are provided from the modulator. The output clock
signal is equal for all four modulators. If CLKSEL = 1,
CLKIN must always be set either high or low.
A differential input signal of 0V will ideally produce a
stream of ones and zeros that are high 50% of the time and
low 50% of the time. A differential input of +2V produces
a stream of ones and zeros that are high 80% of the time.
A differential input of –2V produces a stream of ones and
zeros that are high 20% of the time. The input voltage
versus the output modulator signal is shown in Figure 6.
MODES OF OPERATION
The system clock of the ADS1204 is 20MHz by default.
The system clock can be provided either from the internal
20MHz RC oscillator or from an external clock source. For
this purpose, the CLKIN pin is provided; it is controlled by
the mode setting, CLKSEL.
DIGITAL INTERFACE
INTRODUCTION
The analog signal connected to the input of the
delta-sigma modulator is converted using the clock signal
applied to the modulator. The result of the conversion, or
modulation, is generated and sent to the OUTx pin from the
delta-sigma modulator. In most applications where a direct
The system clock is divided by two for the modulator clock.
Therefore, the default clock frequency of the modulator is
10MHz. With a possible external clock range of 1MHz to
32MHz, the modulator operates between 500kHz and
16MHz.
Modulator Output
+FS (Analog Input)
−
FS (Analog Input)
Analog Input
Figure 6. Analog Input vs Modulator Output of the ADS1204
15
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FILTER USAGE
0
10
20
30
40
50
60
70
80
OSR = 32
fDATA = 10MHz/32 = 312.5kHz
The modulator generates only a bitstream, which does
not output a digital word like an A/D converter. In order
to output a digital word equivalent to the analog input
voltage, the bitstream must be processed by a digital
filter.
−
−
−
−
−
−
−
−
−
3dB: 81.9kHz
A very simple filter, built with minimal effort and
hardware, is the Sinc filter:
3
3
1 * z−OSR
H(z) + ǒ 1 * z−1
Ǔ
(2)
0
200
400
600
800 1000 1200 1400 1600
This filter provides the best output performance at the
lowest hardware size (for example, a count of digital
gates). For oversampling ratios in the range of 16 to
256, this is a good choice. All the characterizations in
Frequency (kHz)
3
Figure 7. Frequency Response of Sinc Filter
3
the data sheet are also done using a Sinc filter with an
oversampling ratio of OSR = 256 and an output word
width of 16 bits.
30k
OSR = 32
FSR = 32768
ENOB = 9.9 Bits
3
25k
In a Sinc filter response (shown in Figure 7 and
Figure 8), the location of the first notch occurs at the
Settling Time =
20k
×
µ
1/fDATA = 9.6 s
3
frequency of output data rate f
= f
/OSR. The
DATA
CLK
–3dB point is located at half the Nyquist frequency or
/4. For some applications, it may be necessary to
use another filter type for better frequency response.
15k
10k
5k
f
DATA
This performance can be improved, for example, by a
cascaded filter structure. The first decimation stage can
3
be a Sinc filter with a low OSR and the second stage
0
0
5
10
15
20
25
30
35
40
a high-order filter.
Number of Output Clocks
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications,
available for download at www.ti.com.
3
Figure 8. Pulse Response of Sinc Filter
(f = 10MHz)
MOD
16
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The effective number of bits (ENOB) can be used to
compare the performance of ADCs and delta-sigma
modulators. Figure 9 shows the ENOB of the ADS1204
with different filter types. In this data sheet, the ENOB
is calculated from the SNR:
data clocks. The data clock is equal to the modulator
clock divided by the OSR. For overcurrent protection,
3
filter types other than Sinc might be a better choice. A
2
simple example is a Sinc filter. Figure 10 compares the
settling time of different filter types. The Sincfast is a
2
modified Sinc filter:
SNR = 1.76dB + 6.02dB × ENOB
(3)
2
1 * z−OSR
ǒ
−2 OSRǓ
H(z) + ǒ 1 * z−1
Ǔ
1 ) z
(4)
16
10
9
8
7
6
5
4
3
2
1
0
Sinc3
Sinc3
14
12
10
8
Sincfast
Sinc2
Sinc2
Sinc
6
Sinc
Sincfast
4
2
0
1
10
100
1000
0
2
4
6
8
10
OSR
µ
Settling Time ( s)
Figure 9. Measured ENOB vs OSR
Figure 10. Measured ENOB vs Settling Time
In motor control applications, a very fast response time
for overcurrent detection is required. There is a
constraint between 1µs and 5µs with 3 bits to 7 bits
resolution. The time for full settling is dependent on the
For more information, see application note SBAA094,
Combining the ADS1202 with an FPGA Digital Filter for
Current Measurement in Motor Control Applications,
available for download at www.ti.com.
3
filter order. Therefore, the full settling of the Sinc filter
2
needs three data clocks and the Sinc filter needs two
17
ꢚꢓ ꢖꢄ ꢎ ꢊ ꢛ
www.ti.com
SBAS301A − OCTOBER 2003 − REVISED JUNE 2004
For multiple converters, connect the two ground planes as
close as possible to one central location for all of the
converters. In some cases, experimentation may be
required to find the best point to connect the two planes
together.
LAYOUT CONSIDERATIONS
POWER SUPPLIES
An applied external digital filter rejects high-frequency
noise. PSRR and CMRR improve at higher frequencies
because the digital filter suppresses high-frequency noise.
DECOUPLING
Good decoupling practices must be used for the ADS1204
and for all components in the design. All decoupling
capacitors, specifically the 0.1µF ceramic capacitors,
must be placed as close as possible to the pin being
decoupled. A 1µF and 10µF capacitor, in parallel with the
0.1µF ceramic capacitor, can be used to decouple AVDD
to AGND as well as BVDD to BGND. At least one 0.1µF
ceramic capacitor must be used to decouple every AVDD
to AGND and BVDD to BGND, as well as for the digital
supply on each digital component.
However, the suppression of the filter is not infinite, so
high-frequency noise still influences the conversion result.
Inputs to the ADS1204, such as CH x+, CH x−, and CLKIN,
should not be present before the power supply is on.
Violating this condition could cause latch-up. If these
signals are present before the supply is on, series resistors
should be used to limit the input current to a maximum of
10mA. Experimentation may be the best way to determine
the appropriate connection between the ADS1204 and
different power supplies.
The digital supply sets the I/O voltage for the interface and
can be set within a range of 2.7V to 5.5V.
GROUNDING
In cases where both the analog and digital I/O supplies
share the same supply source, an RC filter of 10Ω and
0.1µF can be used to help reduce the noise in the analog
supply.
Analog and digital sections of the design must be carefully
and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. Do not join
the ground planes; instead, connect the two with a
moderate signal trace underneath the converter. However,
for different applications with DSPs and switching power
supplies, this process might be different.
18
PACKAGE OPTION ADDENDUM
www.ti.com
28-Jun-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1204IRHBR
ADS1204IRHBT
ACTIVE
ACTIVE
QFN
QFN
RHB
RHB
32
32
3000
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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