ADS1219IRTET [TI]
具有 I2C 接口和外部基准输入电压的 24 位 1kSPS 4 通道、通用 Δ-Σ ADC | RTE | 16 | -40 to 125;
| 型号： | ADS1219IRTET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 接口和外部基准输入电压的 24 位 1kSPS 4 通道、通用 Δ-Σ ADC | RTE | 16 | -40 to 125 转换器 |
| 文件： | 总57页 (文件大小：2553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1219
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
具有 I2C 接口的 ADS1219 4 通道、1kSPS、24 位 Δ-Σ ADC
1 特性
3 说明
1
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易于使用，仅通过一个寄存器进行编程
ADS1219 是一款 24 位精密模数转换器 (ADC)，集成
了 实施 常见系统监控功能（如电源电压、电流和温度
监控）所需的所有特性。该器件 通过 灵活的输入多路
复用器 (MUX)、轨至轨输入缓冲器、可编程增益级、
电压基准和振荡器实现两个差分输入或四个单端输入。
电流消耗可以低至 315µA（典型值）
宽电源电压范围：2.3V 至 5.5V
轨至轨输入缓冲区，可实现高输入阻抗
可编程增益：1 和 4
可编程数据速率：高达 1kSPS
高达 20 位的有效分辨率
该器件配备缓冲器，可直接连接高阻抗源。缓冲器可以
提供增益级，可选增益有 1 和 4。ADS1219 可在数据
速率高达每秒 1000 个样本 (SPS) 的情况下通过单周
期稳定执行转换。针对噪声环境中的工业应用，当采样
频率为 20SPS 时，数字滤波器可同时提供 50Hz 和
60Hz 抑制的需求。
采用单周期稳定数字滤波器，在 20SPS 时实现同
步 50Hz 和 60Hz 抑制
•
•
•
•
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两个差分输入或四个单端输入
集成 2.048V 基准电压：漂移 5ppm/°C（典型值）
集成 2% 精准振荡器
与 I2C 兼容的接口
支持的 I2C 总线速度模式：
标准模式、快速模式、超快速模式
ADS1219 具有 一个与 I2C 兼容的 2 线接口，支持高
达 1Mbps 的 I2C 总线速度。可通过两个地址引脚为器
件选择 16 个不同的 I2C 地址。
•
•
16 引脚可配置 I2C 地址
ADS1219 采用无引线的 16 引脚 WQFN 或 16 引脚
TSSOP 封装，额定工作温度范围为 –40°C 至 +125°
C。
封装：3.0mm × 3.0mm × 0.75mm WQFN
2 应用
器件信息(1)
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•
•
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电池测试设备
器件型号
ADS1219
封装
WQFN (16)
TSSOP (16)
封装尺寸（标称值）
3.00mm × 3.00mm
5.00mm × 4.40mm
气体检测器
热量计
光学模块
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
可穿戴健身和活动跟踪器
电压、电流和温度监控应用
3.3 V
3.3 V
3.3 V
0.1 mF
0.1 mF
0.1 mF
3.3 V
REFP
REFN
AVDD
DVDD
RREF
2.048-V
Reference
Reference
MUX
RF0
ADS1219
AIN0
3.3 V
Thermistor
CF0
SCL
SDA
A0
3.3 V
0.1 mF
AIN1
AIN2
AIN3
Digital Filter
and
Gain
1 or 4
24-bit
ûꢀ ADC
MUX
I2C Interface
A1
RF2
RShunt
INA180
DRDY
RESET
CF2
Buffers
RF3
Low Drift
Oscillator
0 V to 2 V
Load
CF3
DGND
AGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS924
ADS1219
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
目录
8.5 Programming........................................................... 22
8.6 Register Map........................................................... 27
Application and Implementation ........................ 30
9.1 Application Information............................................ 30
9.2 Typical Application .................................................. 34
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 I2C Timing Requirements.......................................... 7
6.7 I2C Switching Characteristics.................................... 8
6.8 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 14
7.1 Noise Performance ................................................. 14
Detailed Description ............................................ 15
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 16
8.4 Device Functional Modes........................................ 20
9
10 Power Supply Recommendations ..................... 37
10.1 Power-Supply Sequencing.................................... 37
10.2 Power-Supply Decoupling..................................... 37
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 39
12 器件和文档支持 ..................................................... 40
12.1 器件支持................................................................ 40
12.2 文档支持................................................................ 40
12.3 接收文档更新通知 ................................................. 40
12.4 社区资源................................................................ 40
12.5 商标....................................................................... 40
12.6 静电放电警告......................................................... 40
12.7 术语表 ................................................................... 40
13 机械、封装和可订购信息....................................... 41
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (July 2018) to Revision A
Page
•
Changed Internal Voltage Reference, Accuracy parameter: added TSSOP package to test conditions of first row
and added second row to Internal Voltage Reference, Accuracy parameter......................................................................... 5
•
•
已添加 TSSOP package to conditions of Internal Reference Voltage Histogram figure ...................................................... 11
已更改 976.56 nV to 61.04 nV in LSB SIZE column of Full-Scale Range and LSB Size table............................................ 17
2
Copyright © 2018, Texas Instruments Incorporated
ADS1219
www.ti.com.cn
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
PW Package
16-Pin TSSOP
Top View
A0
A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCL
SDA
RESET
DGND
AGND
AIN3
DRDY
DVDD
AVDD
AIN0
AIN1
REFP
RESET
DGND
AGND
AIN3
1
2
3
4
12
11
10
9
DRDY
DVDD
AVDD
AIN0
Thermal
Pad
AIN2
REFN
Not to scale
Not to scale
Pin Functions
PIN
NO.
ANALOG OR DIGITAL
INPUT/OUTPUT
NAME
RTE
15
16
9
PW
DESCRIPTION(1)
I2C slave address select pin 0. See the I2C Address section for details.
A0
A1
1
2
Digital input
Digital input
Analog input
Analog input
Analog input
Analog input
Analog supply
Analog supply
Digital supply
Digital output
Digital supply
Analog input
Analog input
Digital input
Digital input
Digital input/output
—
I2C slave address select pin 1. See the I2C Address section for details.
AIN0
11
10
7
Analog input 0
AIN1
8
Analog input 1
AIN2
5
Analog input 2
AIN3
4
6
Analog input 3
AGND
AVDD
DGND
DRDY
DVDD
REFN
REFP
RESET
SCL
3
5
Negative analog power supply
10
2
12
4
Positive analog power supply. Connect a 100-nF (or larger) capacitor to AGND.
Digital ground
12
11
6
14
13
8
Data ready, active low. Connect to DVDD using a pullup resistor.
Positive digital power supply. Connect a 100-nF (or larger) capacitor to DGND.
Negative reference input
7
9
Positive reference input
1
3
Reset, active low
14
13
Pad
16
15
—
Serial clock input. Connect to DVDD using a pullup resistor.
Serial data input and output. Connect to DVDD using a pullup resistor.
Thermal power pad. Connect to AGND.
SDA
Thermal pad
(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.
Copyright © 2018, Texas Instruments Incorporated
3
ADS1219
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
(1)
see
MIN
–0.3
MAX
UNIT
AVDD to AGND
7
Power-supply voltage
DVDD to DGND
–0.3
7
V
AGND to DGND
–2.8
0.3
Analog input voltage
Digital input voltage
Input current
AIN0, AIN1, AIN2, AIN3, REFP, REFN
SCL, SDA, A0, A1, DRDY, RESET
Continuous, any pin except power-supply pins
Junction, TJ
AGND – 0.3
DGND – 0.3
–10
AVDD + 0.3
V
V
7
10
mA
150
150
Temperature
°C
Storage, Tstg
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Analog power supply
AVDD to AGND
AGND to DGND
DVDD to DGND
2.3
–0.1
2.3
5.5
0.1
5.5
V
V
0
Digital power supply
ANALOG INPUTS(1)
V(AINx)
VIN
Absolute input voltage
Differential input voltage
Gain = 1 and 4
AGND – 0.1
–VREF / Gain
AVDD + 0.1
VREF / Gain
V
V
(2)
VIN = VAINP – VAINN
VOLTAGE REFERENCE INPUTS
VREF
Differential reference input voltage
VREF = V(REFP) – V(REFN)
0.75
AGND – 0.1
V(REFN) + 0.75
2.5
AVDD
V(REFP) – 0.75
AVDD + 0.1
V
V
V
V(REFN)
V(REFP)
Absolute negative reference voltage
Absolute positive reference voltage
DIGITAL INPUTS
SCL, SDA, A0, A1, DRDY,
2.3 V ≤ DVDD < 3.0 V
DGND
DVDD + 0.5
Input voltage
SCL, SDA, A0, A1, DRDY,
3.0 V ≤ DVDD ≤ 5.5 V
V
DGND
DGND
5.5
RESET
DVDD
TEMPERATURE RANGE
TA Operating ambient temperature
–40
125
°C
(1) AINx denotes one of the four available analog inputs. AINP and AINN denote the positive and negative inputs selected by the MUX.
(2) Excluding the effects of offset and gain error.
4
Copyright © 2018, Texas Instruments Incorporated
ADS1219
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ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
6.4 Thermal Information
ADS1219
THERMAL METRIC(1)
WQFN (RTE)
16 PINS
57.7
TSSOP (PW)
16 PINS
90.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
29.0
31.7
19.9
41.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
1.8
ψJB
19.8
41.2
RθJC(bot)
11.8
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Absolute input current
VIN = 0 V
VIN = 0 V
±5
10
±5
10
nA
pA/°C
nA
Absolute input current drift
Differential input current
Differential input current drift
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
pA/°C
SYSTEM PERFORMANCE
Resolution (no missing codes)
Data rate
24
Bits
SPS
DR
20, 90, 330, 1000
Noise (input-referred)(1)
Integral nonlinearity
Input offset voltage
Offset drift vs temperature
Gain error(2)
Gain = 1, DR = 20 SPS
5.04
4
µVRMS
ppmFSR
µV
INL
VIO
AVDD = 3.3 V, VCM = AVDD / 2, best fit
Differential inputs
–15
15
0.1
2
±4
0.02
±0.01%
0.3
µV/°C
Gain drift vs temperature(2)
ppm/°C
dB
50 Hz ±1 Hz, DR = 20 SPS
78
80
88
NMRR Normal-mode rejection ratio
CMRR Common-mode rejection ratio
60 Hz ±1 Hz, DR = 20 SPS
88
At dc, gain = 1, AVDD = 3.3 V
fCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V
AVDD at dc, VCM = AVDD / 2
90
105
115
105
115
dB
dB
105
85
PSRR
Power-supply rejection ratio
DVDD at dc, VCM = AVDD / 2
95
INTERNAL VOLTAGE REFERENCE
VREF
Reference voltage
Accuracy
2.048
±0.01%
±0.04%
5
V
TA = 25°C, TSSOP package
TA = 25°C, WQFN package
–0.15%
–0.25%
0.15%
0.25%
30
Temperature drift
Long-term drift
ppm/°C
ppm
1000 hours
110
VOLTAGE REFERENCE INPUTS
Reference input current
REFP = VREF, REFN = AGND, AVDD = 3.3 V
±10
nA
INTERNAL OSCILLATOR
fCLK
Frequency
Accuracy
1.024
±1%
MHz
–2%
2%
(1) See the Noise Performance section for more information.
(2) Excluding error of voltage reference.
Copyright © 2018, Texas Instruments Incorporated
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, DVDD = 3.3 V, all data rates, all gains, and internal reference enabled (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VIL
Logic input level, low
Logic input level, high
DGND
0.3 DVDD
V
2.3 V ≤ DVDD < 3.0 V,
SCL, SDA, A0, A1, DRDY
0.7 DVDD
DVDD + 0.5
VIH
3.0 V ≤ DVDD ≤ 5.5 V,
SCL, SDA, A0, A1, DRDY
V
0.7 DVDD
0.7 DVDD
0.05 DVDD
5.5
RESET
DVDD
Hysteresis of Schmitt-trigger
inputs
Vhys
VOL
Fast-mode, fast-mode plus
V
V
Logic output level, low
IOL = 3 mA
DGND
0.15
0.4
VOL = 0.4 V, standard-mode, fast-mode
VOL = 0.4 V, fast-mode plus
VOL = 0.6 V, fast-mode
3
20
IOL
Low-level output current
mA
6
Ii
Input current
Capacitance
DGND + 0.1 V < VDigital Input < DVDD – 0.1 V
Each pin
–10
10
10
µA
pF
Ci
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V)
Power-down mode
0.1
250
310
3
IAVDD
Analog supply current
Conversion mode, internal reference selected
Conversion mode, external reference selected
µA
DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, I2C Not Active)
Power-down mode
0.3
65
5
IDVDD
Digital supply current
µA
Conversion mode
POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, I2C Not Active)
PD Power dissipation Conversion mode, internal reference selected
100
1.04
mW
6
Copyright © 2018, Texas Instruments Incorporated
ADS1219
www.ti.com.cn
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
6.6 I2C Timing Requirements
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
STANDARD-MODE
fSCL
SCL clock frequency
0
4
100
kHz
µs
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
tLOW
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, repeated START condition
Hold time, data
4.7
4.0
4.7
0
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Setup time, data
250
Rise time, SCL, SDA
1000
250
tf
Fall time, SCL, SDA
tSU;STO
tBUF
Setup time, STOP condition
Bus free time, between STOP and START condition
Valid time, data
4.0
4.7
tVD;DAT
tVD;ACK
FAST-MODE
fSCL
3.45
3.45
Valid time, acknowledge
SCL clock frequency
0
400
kHz
µs
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
0.6
tLOW
Pulse duration, SCL low
1.3
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Pulse duration, SCL high
0.6
Setup time, repeated START condition
Hold time, data
0.6
0
Setup time, data
100
Rise time, SCL, SDA
20
300
250
tf
Fall time, SCL, SDA
20 · (DVDD / 5.5 V)
tSU;STO
tBUF
Setup time, STOP condition
Bus free time, between STOP and START condition
Valid time, data
0.6
1.3
tVD;DAT
tVD;ACK
tSP
0.9
0.9
50
Valid time, acknowledge
Pulse width of spikes that must be suppressed by the input filter
0
FAST-MODE PLUS
fSCL
SCL clock frequency
0
1000
kHz
µs
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
0.26
tLOW
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, repeated START condition
Hold time, data
0.5
0.26
0.26
0
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
µs
ns
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
Setup time, data
50
Rise time, SCL, SDA
120
120
tf
Fall time, SCL, SDA
Pullup resistor = 350 Ω
20 · (DVDD / 5.5 V)
tSU;STO
tBUF
Setup time, STOP condition
Bus free time, between STOP and START condition
Valid time, data
0.26
0.5
tVD;DAT
tVD;ACK
tSP
0.45
0.45
50
Valid time, acknowledge
Pulse duration of spikes that must be suppressed by the input filter
0
Copyright © 2018, Texas Instruments Incorporated
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I2C Timing Requirements (continued)
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
RESET PIN
tw(RSL)
Pulse duration, RESET low
Delay time, START condition after RESET rising edge(1)
250
100
ns
ns
td(RSSTA)
DRDY PIN
td(DRSTA)
Delay time, START condition after DRDY falling edge
Timeout(2)
0
ns
TIMEOUT
14000
tMOD
(1) No delay time is required when using the RESET command as long as all I2C timing requirements for the (repeated) START and STOP
conditions are met.
(2) See the Timeout section for more information.
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.
6.7 I2C Switching Characteristics
over operating ambient temperature range, DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor =
1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tw(DRH)
Pulse duration, DRDY high(1)
2
tMOD
Propagation delay time, RDATA command latched to
DRDY rising edge
tp(RDDR)
2
tMOD
(1) tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.
tSU;DAT
tf
tr
70%
30%
. . .
cont.
SDA
SCL
tHD;DAT
tVD;DAT
tf
tHIGH
tr
70%
30%
70%
30%
. . .
cont.
tLOW
9th clock
tHD;STA
S
1 / fSCL
1st clock cycle
tBUF
SDA
tVD;ACK
tSU;STA
tHD;STA
tSP
tSU;STO
70%
30%
SCL
Sr
P
S
9th clock
图 1. I2C Timing Requirements
8
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tw(RSL)
RESET
ttd(RSSTA)
t
SDA
SCL
ADDRESS
S
START
Condition
图 2. RESET Pin Timing Requirements
tw(DRH)
DRDY
td(DRSTA)
ttp(RDDR)
t
RDATA
Command
SDA
SCL
ADDRESS
W
ACK
ACK
S
P
START
STOP
Condition
Condition
图 3. DRDY Pin Timing Requirements and Switching Characteristics
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
15
10
5
20
15
10
5
0
0
-5
-5
-10
-15
-20
-10
-15
-40èC
25èC
85èC
125èC
3 3.5
-40èC
25èC
85èC
125èC
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
V(AINx) (V)
VIN (V)
VIN = 0 V
VCM = 1.65 V
图 4. Absolute Input current vs Absolute Input Voltage
图 5. Differential Input Current vs
Differential Input Voltage
15
10
5
15
10
5
0
0
-5
-5
-10
-10
-15
-15
-100 -80 -60 -40 -20
0
20
40
60
80 100
-100 -80 -60 -40 -20
0
20
40
60
80 100
VIN (% of FS)
VIN (% of FS)
External reference, best fit
Internal reference, best fit
图 7. INL vs Differential Input Voltage
图 6. INL vs Differential Input Voltage
80
60
40
20
0
10
8
Gain = 1
Gain = 4
6
4
2
0
-50
-25
0
25
50
75
100
125
Offset Voltage (ꢀV)
Temperature (èC)
AVDD = 5 V, gain = 1, 110 samples
图 8. Offset Voltage Histogram
图 9. Input Offset Voltage vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
0
-0.005
-0.01
300
250
200
150
100
50
-0.015
-0.02
-0.025
Gain = 1
Gain = 4
-0.03
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Excluding error of voltage reference
Gain Error (%)
Gain = 1, 620 samples,
excluding error of voltage reference
图 10. Gain Error Histogram
图 11. Gain Error vs Temperature
2000
1500
1000
500
0
125
120
115
110
105
100
-50
-25
0
25
50
75
100
125
Temperature (èC)
Internal Reference Voltage (V)
5940 samples, TSSOP package
图 13. Internal Reference Voltage Histogram
图 12. DC CMRR vs Temperature
2.051
2.05
2.0486
2.0484
2.0482
2.048
AVDD = 3.3 V
AVDD = 5.0 V
2.049
2.048
2.047
2.046
2.045
2.0478
2
2.5
3
3.5
4
4.5
5
5.5
-50
-25
0
25
50
75
100
125
AVDD (V)
Temperature (èC)
图 15. Internal Reference Voltage vs AVDD
图 14. Internal Reference Voltage vs Temperature
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
300
250
200
150
100
50
0
VREF = 1 V
VREF = 1.5 V
VREF = 2 V
VREF = 2.5 V
-5
-10
-15
-20
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Internal Oscillator Frequency (MHz)
图 17. Internal Oscillator Frequency Histogram
图 16. External Reference Input Current vs Temperature
1.026
1.026
1.025
1.024
1.023
1.022
1.021
1.02
1.025
1.024
1.023
1.022
1.021
1.02
-50
-25
0
25
50
75
100
125
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (èC)
DVDD (V)
图 18. Internal Oscillator Frequency vs Temperature
图 19. Internal Oscillator Frequency vs DVDD
0.5
1
0.8
0.6
0.4
0.2
0
-40°C
25°C
125°C
0.4
0.3
0.2
0.1
0
0
2
4
6
8
10
12
14
16
18
20
-50
-25
0
25
50
75
100
125
Sinking Current (mA)
Temperature (èC)
DVDD = 3.3 V
Power-down mode
图 21. Analog Supply Current vs Temperature
图 20. Digital Pin Output Voltage vs Sinking Current
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 3.3 V, and using internal VREF = 2.048 V (unless otherwise noted)
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-50
-25
0
25
50
75
100
125
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (èC)
AVDD (V)
Conversion mode
图 22. Analog Supply Current vs Temperature
Conversion mode
图 23. Analog Supply Current vs AVDD
100
90
80
70
60
50
2
1.5
1
0.5
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
Power-down mode
Conversion mode
图 25. Digital Supply Current vs Temperature
图 24. Digital Supply Current vs Temperature
100
90
80
70
60
50
2
2.5
3
3.5
4
4.5
5
5.5
DVDD (V)
Conversion mode
图 26. Digital Supply Current vs DVDD
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7 Parameter Measurement Information
7.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus
reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-
referred noise drops when reducing the output data rate because more samples of the internal modulator are
averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
表 1 and 表 2 summarize the device noise performance. Data are representative of typical noise performance at
TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings from a single
device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted
together. 表 1 lists the input-referred noise in units of μVRMS for the conditions shown. Values in µVPP are shown
in parenthesis. 表 2 lists the corresponding data in effective resolution calculated from μVRMS values using 公式
1. Noise-free resolution calculated from peak-to-peak noise values using 公式 2 are shown in parenthesis.
The input-referred noise only changes marginally when using an external low-noise reference, such as the
REF5020. Use 公式 1 and 公式 2 to calculate effective resolution numbers and noise-free resolution when using
a reference voltage other than 2.048 V:
Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2)
Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2)
(1)
(2)
表 1. Noise in μVRMS (μVPP
)
at AVDD = 3.3 V and Internal VREF = 2.048 V
GAIN
DATA RATE
(SPS)
1
4
20
90
5.04 (19.71)
8.75 (42.59)
18.58 (106.06)
36.98 (221.61)
1.57 (5.68)
2.13 (10.52)
4.54 (26.30)
9.27 (55.07)
330
1000
表 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V and Internal VREF = 2.048 V
GAIN
DATA RATE
(SPS)
1
4
20
19.63 (17.66)
18.84 (16.55)
17.75 (15.24)
16.76 (14.17)
19.32 (17.46)
18.87 (16.57)
17.78 (15.25)
16.75 (14.18)
90
330
1000
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8 Detailed Description
8.1 Overview
The ADS1219 is a small, low-power, 24-bit, ΔΣ ADC. In addition to the ΔΣ ADC core and single-cycle settling
digital filter, the device offers a multiplexer (MUX), rail-to-rail input buffers, a programmable gain stage, an
internal 2.048-V voltage reference, and a clock oscillator. All of these features are intended to reduce the
required external circuitry in typical voltage, current, and temperature monitoring applications. The device is fully
configured through a single register and controlled by six commands through an I2C-compatible interface. The
Functional Block Diagram section shows the device functional block diagram.
The MUX selects the positive (AINP) and negative (AINN) signals that feed into the rail-to-rail input buffers. A gain
stage with selectable gains of 1 and 4 follows the input buffers. The 24-bit ADC measures the differential signal
provided after the gain stage. The converter core consists of a differential, switched-capacitor, ΔΣ modulator
followed by a digital filter. The digital filter receives a high-speed bitstream from the modulator and outputs a
code proportional to the input voltage. This architecture results in a very strong attenuation of any common-mode
signal.
The device has two available conversion modes: single-shot conversion and continuous conversion mode. In
single-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores the
value in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversion
mode is intended to provide significant power savings in systems that require only periodic conversions, or when
there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins
a conversion of the input signal as soon as the previous conversion is completed. New data are available at the
programmed data rate. Data can be read at any time without concern of data corruption and always reflect the
most recently completed conversion.
8.2 Functional Block Diagram
REFP
REFN
AVDD
DVDD
2.048-V
Reference
Reference
MUX
ADS1219
AIN0
AIN1
AIN2
AIN3
SCL
SDA
A0
Digital Filter
and
Gain
1 or 4
24-bit
ûꢀ ADC
MUX
I2C Interface
A1
DRDY
RESET
Buffers
Low Drift
Oscillator
DGND
AGND
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8.3 Feature Description
8.3.1 Multiplexer
图 27 shows the flexible input multiplexer of the device. Either four single-ended signals, two differential signals,
or a combination of two single-ended signals and one differential signal can be measured. The positive (AINP)
and negative (AINN) inputs selected for measurement are configured by three bits (MUX[2:0]) in the configuration
register. When single-ended signals need to be measured, the negative ADC input (AINN) can internally be
connected to AGND by a switch within the multiplexer.
AVDD / 2
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AIN0
AIN1
AIN2
AIN3
AINP
AINN
To ADC
Rail-to Rail
Buffers
AGND
图 27. Analog Input Multiplexer
Electrostatic discharge (ESD) diodes to AVDD and AGND protect the inputs. The absolute voltage on any input
must stay within the range provided by 公式 3 to prevent the ESD diodes from turning on:
AGND – 0.3 V < V(AINx) < AVDD + 0.3 V
(3)
If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or
series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings
table). Overdriving an unused input on the device can affect conversions taking place on other input pins.
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Feature Description (接下页)
8.3.2 Rail-to-Rail Input Buffers and Programmable Gain Stage
The ADS1219 integrates two rail-to-rail input buffers to ensure that the effect on the input loading resulting from
the capacitor charging and discharging of the ΔΣ ADC is minimal. The buffers therefore help to increase the input
impedance of the device. See the Electrical Characteristics table for the typical values of absolute input currents
(current flowing into or out of each input) and differential input currents (difference in absolute current between
the positive and negative input).
The usable absolute input voltage range of the buffers is (AGND – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V). VIN
denotes the differential input voltage VIN = VAINP – VAINN between the buffer inputs.
A programmable gain stage follows the buffers. The GAIN bit in the configuration register is used to configure the
gain to either 1 or 4.
公式 4 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain setting
and the reference voltage used:
FSR = ±VREF / Gain
(4)
表 3 shows the corresponding full-scale ranges and least significant bit (LSB) sizes when using the internal
2.048-V reference.
表 3. Full-Scale Range and LSB Size
GAIN SETTING
FSR
LSB SIZE
244.14 nV
61.04 nV
1
4
±2.048 V
±0.512 V
In order to measure single-ended signals that are referenced to AGND (AINP = VIN, AINN = AGND), connect one
of the analog inputs to AGND externally or use the internal AGND connection of the multiplexer (MUX[2:0]
settings 011 through 110). The device only uses the code range that represents positive differential voltages
when measuring single-ended signals. See the Data Format section for more details.
For signal sources with high output impedance, external buffering may still be necessary. Active buffers can
introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.
8.3.3 Voltage Reference
The device offers an integrated, low-drift, 2.048-V reference. For applications that require a different reference
voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFP
and REFN).
The reference source is selected by the VREF bit in the configuration register. By default, the internal reference
is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when coming
out of power-down mode, or when switching from the external reference source to the internal reference.
The differential reference input allows freedom in the reference common-mode voltage. The reference inputs are
internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required
when using an external reference. When used in ratiometric applications, the reference inputs do not load the
external circuitry; however, the analog supply current increases when using an external reference because the
reference buffers are enabled.
In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and
drift of the voltage reference is reflected in the conversion result.
8.3.4 Modulator and Internal Oscillator
A ΔΣ modulator is used in the ADS1219 to convert the differential signal provided by the gain stage into a pulse
code modulated (PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 4 =
256 kHz, where fCLK is provided by the internal 1.024-MHz oscillator.
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8.3.5 Digital Filter
The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and
decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the
different data rates and always settles within a single cycle. The frequency responses of the digital filter are
shown in 图 28 to 图 32 for different output data rates. The filter notches and output data rate scale proportionally
with the clock frequency. The internal oscillator can vary over temperature as specified in the Electrical
Characteristics table. The data rate or conversion time, respectively, and consequently also the filter notches
vary proportionally.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
46
48
50
52
54
56
58
60
62
64
Frequency (Hz)
D002
D001
图 28. Filter Response
图 29. Detailed View of the Filter Response
(DR = 20 SPS)
(DR = 20 SPS)
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
100 200 300 400 500 600 700 800 900 1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Frequency (Hz)
D004
D006
图 30. Filter Response
图 31. Filter Response
(DR = 90 SPS)
(DR = 330 SPS)
0
-20
-40
-60
-80
0
1
2
3
4
5
6
7
8
9
10
Frequency (kHz)
D008
图 32. Filter Response
(DR = 1 kSPS)
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8.3.6 Conversion Times
表 4 shows the actual conversion times for each data rate setting. The values provided are in terms of tCLK cycles
and in milliseconds.
Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.
The first conversion starts 28.5 · tCLK after the START/SYNC command is latched.
Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to the
DRDY falling edge and rounded to the next tCLK
.
Commands are latched on the eighth falling edge of SCL in the command byte.
表 4. Conversion Times
CONTINUOUS CONVERSION MODE(1)
SINGLE-SHOT CONVERSION MODE
NOMINAL
DATA RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
ACTUAL
ACTUAL
CONVERSION TIME
(ms)
ACTUAL
ACTUAL
CONVERSION TIME
(ms)
CONVERSION TIME
CONVERSION TIME
(2)
(2)
(tCLK
)
(tCLK)
20
90
13.1
39.6
51192
11532
3116
49.99
11.26
3.04
51213
11557
3141
50.01
11.29
3.07
330
1000
150.1
483.8
1036
1.01
1061
1.04
(1) The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. The times listed in this table do not include that time.
(2) tCLK = 1 / fCLK. fCLK = 1.024 MHz.
Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not
affect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in the
Electrical Characteristics table for oscillator accuracy.
8.3.7 Offset Calibration
The ADS1219 does not offer any self-calibration options. However the internal multiplexer offers the option to
short both inputs (AINP and AINN) to mid-supply AVDD / 2. This option can be used to measure and calibrate the
device offset voltage by storing the result of the shorted input voltage reading in a microcontroller and
consequently subtracting the result from each following reading. Take multiple readings with the inputs shorted
and average the result to reduce the effect of noise.
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8.4 Device Functional Modes
图 33 shows a flow chart of the different operating modes and how the device transitions from one mode to
another.
Power-On Reset or
RESET pin high or
RESET command(1)
Reset device to
default settings
Low-power state
No
No
START/SYNC
Command?
POWERDOWN
Command?
Yes
Yes
Conversion
Mode
Power-down Mode(3)
Yes
No
Start new
conversion
START/SYNC
Command?
No
0 = Single-Shot
1 = Continuous
conversion mode
conversion mode
Yes
Conversion
POWERDOWN
Command?
mode selection(2)
(1) Any reset (power-on, command, or pin) immediately resets the device.
(2) The conversion mode is selected with the CM bit in the configuration register.
(3) The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down
mode.
图 33. Operating Flow Chart
8.4.1 Power-Up and Reset
The ADS1219 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESET
command.
When a reset occurs, the configuration register resets to the default values and the device enters a low-power
state. The device then waits for the START/SYNC command to enter conversion mode; see the I2C Timing
Requirements table for reset timing information.
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Device Functional Modes (接下页)
8.4.1.1 Power-On Reset
During power up, the device is held in reset. The power-on reset releases approximately 500 µs after both
supplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (including
the voltage reference) are stable and communication with the device is possible. As part of the power-on reset
process, the device sets all bits in the configuration register to the respective default settings. After power-up, the
device enters a low-power state. This power-up behavior is intended to prevent systems with tight power-supply
requirements from encountering a current surge during power-up.
8.4.1.2 RESET Pin
Reset the ADC by taking the RESET pin low for a minimum of tw(RSL) and then returning the pin high. After the
rising edge of the RESET pin, a delay time of td(RSSTA) is required before communicating with the device; see the
I2C Timing Requirements table for reset timing information.
8.4.1.3 Reset by Command
Reset the ADC by using the RESET command (06h or 07h). No delay time is required after the RESET
command is latched before starting to communicate with the device as long as the timing requirements (see the
I2C Timing Requirements table) for the (repeated) START and STOP conditions are met. Alternatively, the device
also responds to the I2C general-call software reset.
8.4.2 Conversion Modes
The device operates in one of two conversion modes that are selected by the CM bit in the configuration register.
These conversion modes are single-shot conversion and continuous conversion mode. A START/SYNC
command must be issued each time the CM bit is changed.
8.4.2.1 Single-Shot Conversion Mode
In single-shot conversion mode, the device only performs a conversion when a START/SYNC command is
issued. The device consequently performs one single conversion and returns to a low-power state afterwards.
The internal oscillator and all analog circuitry are turned off while the device waits in this low-power state until the
next conversion is started. Writing to the configuration register when a conversion is ongoing functions as a new
START/SYNC command that stops the current conversion and restarts a single new conversion. Each
conversion is fully settled (assuming the analog input signal settles to the final value before the conversion starts)
because the device digital filter settles within a single cycle.
8.4.2.2 Continuous Conversion Mode
In continuous conversion mode, the device continuously performs conversions. When a conversion completes,
the device places the result in the output buffer and immediately begins another conversion.
In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.
The first conversion starts 28.5 · tCLK after the START/SYNC command is latched. Writing to the configuration
register during an ongoing conversion restarts the current conversion. Send a START/SYNC command
immediately after the CM bit is set to 1.
Stop continuous conversions by sending the POWERDOWN command.
8.4.3 Power-Down Mode
When the POWERDOWN command is issued, the device enters power-down mode after completing the current
conversion. In this mode, all analog circuitry (including the voltage reference) are powered down and the device
typically only uses 400 nA of current. When in power-down mode, the device holds the configuration register
settings and responds to commands, but does not perform any data conversions.
Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous
conversion mode, depending on the conversion mode selected by the CM bit.
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8.5 Programming
8.5.1 I2C Interface
The ADS1219 uses an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2-wire
communication interface that allows communication of a master device with multiple slave devices on the same
bus through the use of device addressing. Each slave device on an I2C bus must have a unique address.
Communication on the I2C bus always takes place between two devices: one acting as the master and the other
as the slave. Both the master and slave can receive and transmit data, but the slave can only read or write under
the direction of the master. The ADS1219 always acts as an I2C slave device.
An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the
I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high.
Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is
not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus
simultaneously, there is no driver contention.
See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
8.5.1.1 I2C Address
The ADS1219 has two address pins: A0 and A1. Each address pin can be tied to either DGND, DVDD, SDA, or
SCL, providing 16 possible unique addresses. This configuration allows up to 16 different ADS1219 devices to
be present on the same I2C bus. 表 5 shows the truth table for the I2C addresses for the possible address pin
connections.
At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first
falling SCL edge of the address byte, the ADS1219 decodes its address configuration again.
表 5. I2C Address Truth Table
A1
A0
I2C ADDRESS
100 0000
100 0001
100 0010
100 0011
100 0100
100 0101
100 0110
100 0111
100 1000
100 1001
100 1010
100 1011
100 1100
100 1101
100 1110
100 1111
DGND
DGND
DGND
DGND
DVDD
DVDD
DVDD
DVDD
SDA
DGND
DVDD
SDA
SCL
DGND
DVDD
SDA
SCL
DGND
DVDD
SDA
SDA
SDA
SDA
SCL
SCL
DGND
DVDD
SDA
SCL
SCL
SCL
SCL
8.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line.
The ADS1219 cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the
ADS1219 (the slave). When the master reads from a ADS1219, the ADS1219 drives the data line; when the
master writes to a ADS1219, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in
an idle state, the master should hold SCL high.
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8.5.1.3 Data Ready (DRDY)
DRDY is an open-drain output pin that indicates when a new conversion result is ready for retrieval. When DRDY
falls low, new conversion data are ready. DRDY transitions back high when the conversion result is latched for
output transmission. In case a conversion result in continuous conversion mode is not read, DRDY releases high
for tw(DRH) before the next conversion completes. See the I2C Timing Requirements table for more details.
8.5.1.4 Interface Speed
The ADS1219 supports I2C interface speeds up to 1 Mbps. Standard-mode (Sm) with bit rates up to 100 kbps,
fast-mode (Fm) with bit rates up to 400 kbps, and fast-mode plus (Fm+) with bit rates up to 1 Mbps are
supported. High-speed mode (Hs-mode) is not supported.
8.5.1.5 Data Transfer Protocol
图 34 shows the format of the data transfer. The master initiates all transactions with the ADS1219 by generating
a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START condition.
The bus is considered to be busy after the START condition.
Following the START condition, the master sends the 7-bit slave address corresponding to the address of the
ADS1219 that the master wants to communicate with. The master then sends an eighth bit that is a data
direction bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation.
After the R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the ADS1219 to
acknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does not
recognize the slave address, the ADS1219 holds SDA high to indicate a not acknowledge (NACK) signal.
Next follows the data transmission. If the transaction is a read (R/W = 1), the ADS1219 outputs data on SDA. If
the transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, most
significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte
must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK.
If the transaction is a write, the ADS1219 issues the ACK.
The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA
line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the
STOP condition.
SDA
SCL
A6 œ A0
D7 œ D0
D7 œ D0
1 - 7
8
9
1 - 8
9
1 - 8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
Condition
from slave
from receiver
from receiver Condition
图 34. I2C Data Transfer Format
8.5.1.6 I2C General Call (Software Reset)
The ADS1219 responds to the I2C general-call address (0000 000) if the R/W bit is 0. The device acknowledges
the general-call address and, if the next byte is 06h, performs a reset. The general-call software reset has the
same effect as the RESET command.
8.5.1.7 Timeout
The ADS1219 offers a I2C timeout feature that can be used to recover communication when a serial interface
transmission is interrupted. If the host initiates contact with the ADS1219 but subsequently remains idle for
14000 · tMOD before completing a command, the ADS1219 interface is reset. If the ADS1219 interface resets
because of a timeout condition, the host must abort the transaction and restart the communication again by
issuing a new START condition.
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8.5.2 Data Format
The device provides 24 bits of data in binary two's complement format. Use 公式 5 to calculate the size of one
code (LSB).
1 LSB = (2 · VREF / Gain) / 224 = +FS / 223
(5)
A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFFFh
and a negative full-scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 800000h. The output clips
at these codes for signals that exceed full-scale.
表 6 summarizes the ideal output codes for different input signals.
表 6. Ideal Output Code versus Input Signal
INPUT SIGNAL,
VIN = VAINP – VAINN
≥ FS (223 – 1) / 223
FS / 223
IDEAL OUTPUT CODE(1)
7FFFFFh
000001h
0
000000h
–FS / 223
FFFFFFh
≤ –FS
800000h
(1) Excludes the effects of noise, INL, offset, and gain errors.
图 35 shows the mapping of the analog input signal to the output codes.
7FFFFFh
7FFFFEh
000001h
000000h
FFFFFFh
800001h
800000h
¼
¼
-FS
-FS
0
FS
Input Voltage VIN
223 - 1
223 - 1
FS
223
223
图 35. Code Transition Diagram
注
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 000000h to 7FFFFFh. However, because of device offset,
the ADS1219 can still output negative codes when VAINP is close to 0 V.
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8.5.3 Commands
As 表 7 shows, the device offers six different commands to control device operation. Four commands are stand-
alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG) and
write (WREG) register data from and to the device require additional information as part of the instruction.
表 7. Command Definitions
COMMAND
DESCRIPTION
COMMAND BYTE(1)
0000 011x
RESET
Reset the device
START/SYNC
POWERDOWN
RDATA
Start or restart conversions
Enter power-down mode
Read data by command
Read register at address r
Write configuration register
0000 100x
0000 001x
0001 xxxx
RREG
0010 0rxx
WREG
0100 00xx
(1) Operands: r = register address (0 or 1), x = don't care.
8.5.3.1 Command Latching
Commands are not processed until latched by the ADS1219. Commands are latched on the eighth falling edge of
SCL in the command byte.
注
The legend for 图 36 to 图 40:
S = START condition
From master to slave
Sr = Repeated START condition
P = STOP condition
A = acknowledge (SDA low)
From slave to master
A = not acknowledge (SDA high)
8.5.3.2 RESET (0000 011x)
This command resets the device to the default states. No delay time is required after the RESET command is
latched before starting to communicate with the device as long as the timing requirements (see the I2C Timing
Requirements table) for the (repeated) START and STOP conditions are met.
8.5.3.3 START/SYNC (0000 100x)
In single-shot conversion mode, the START/SYNC command is used to start a single conversion, or (when sent
during an ongoing conversion) to reset the digital filter and then restart a single new conversion. When the
device is set to continuous conversion mode, the START/SYNC command must be issued one time to start
converting continuously. Sending the START/SYNC command when converting in continuous conversion mode
resets the digital filter and restarts continuous conversions.
8.5.3.4 POWERDOWN (0000 001x)
The POWERDOWN command places the device into power-down mode. This command shuts down all internal
analog components, but holds all register values. In case the POWERDOWN command is issued when a
conversion is ongoing, the conversion completes before the ADS1219 enters power-down mode. As soon as a
START/SYNC command is issued, all analog components return to their previous states.
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8.5.3.5 RDATA (0001 xxxx)
The RDATA command loads the output shift register with the most recent conversion result. Reading conversion
data must be performed as shown in 图 36 by using two I2C communication frames. The first frame is an I2C
write operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host
sends the RDATA command to the ADS1219. The second frame is an I2C read operation where the R/W bit at
the end of the address byte is 1 to indicate a read. The ADS1219 reports the latest ADC conversion data in this
second I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY pin
at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,
DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is
high.
S
SLAVE ADDRESS
W
A
RDATA
A
Sr
SLAVE ADDRESS
R
A
•••
•••
CONVERSION DATA (MSB)
A
CONVERSION DATA
A
CONVERSION DATA (LSB)
A
P
图 36. Read Conversion Data Sequence
8.5.3.6 RREG (0010 0rxx)
The RREG command reads the value of the register at address r. Reading a register must be performed as
shown in 图 37 by using two I2C communication frames. The first frame is an I2C write operation where the R/W
bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RREG command
including the register address to the ADS1219. The second frame is an I2C read operation where the R/W bit at
the end of the address byte is 1 to indicate a read. The ADS1219 reports the contents of the requested register
in this second I2C frame.
S
SLAVE ADDRESS
W
A
RREG
A
•••
•••
Sr
SLAVE ADDRESS
R
A
REGISTER DATA
A
P
图 37. Read Register Sequence
8.5.3.7 WREG (0100 00xx dddd dddd)
The WREG command writes dddd dddd to the configuration register. 图 38 shows the sequence for writing the
configuration register. The R/W bit at the end of the address byte is 0 to indicate a write. The WREG command
forces the digital filter to reset and any ongoing ADC conversion to restart.
S
SLAVE ADDRESS
W
A
WREG
A
REGISTER DATA
A
P
图 38. Write Register Sequence
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8.5.4 Reading Data and Monitoring for New Conversion Results
Conversion data are read by issuing the RDATA command. The ADS1219 responds to the RDATA command
with the latest conversion result. There are two ways to monitor for new conversion data.
One way is to monitor for the falling edge of the DRDY signal. When DRDY falls low, a new conversion result is
available for retrieval using the RDATA command. 图 39 shows the timing diagram for collecting data using the
DRDY signal to indicate new data.
DRDY
•••
•••
S
SLAVE ADDRESS
W
A
A
RDATA
A
A
Sr
SLAVE ADDRESS
R
A
A
P
•••
CONVERSION DATA (MSB)
CONVERSION DATA
CONVERSION DATA (LSB)
图 39. Using the DRDY Pin to Check for New Conversion Data
Another way to monitor for a new conversion result is to periodically read the DRDY bit in the status register. If
set, the DRDY bit indicates that a new conversion result is ready for retrieval. The host can subsequently issue
an RDATA command to retrieve the data. The rate at which the host polls the ADS1219 for new data must be at
least as fast as the data rate in continuous conversion mode to prevent the host from missing a conversion
result.
If a new conversion result becomes ready during an I2C transmission, the transmission is not corrupted. The new
data are loaded into the output shift register upon the following RDATA command.
图 40 shows the timing diagram for collecting data using the DRDY bit in the status register to indicate new data.
S
SLAVE ADDRESS
W
A
RREG (01h)
A
Sr
SLAVE ADDRESS
R
A
•••
•••
•••
•••
REGISTER DATA (01h)
SLAVE ADDRESS
A
R
A
Sr
A
SLAVE ADDRESS
W
A
A
RDATA
A
A
•••
•••
Sr
CONVERSION DATA (MSB)
CONVERSION DATA
CONVERSION DATA (LSB)
P
图 40. Using the DRDY Bit to Check for New Conversion Data
8.6 Register Map
8.6.1 Configuration and Status Registers
The device has two 8-bit registers (configuration and status) that are accessible through the I2C interface using
the RREG and WREG commands. After power-up or reset, both registers are set to the default values (which are
all 0). All register values are retained during power-down mode. 表 8 shows the register map of the two registers.
表 8. Register Map
REGISTER
(Hex)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0h
MUX[2:0]
GAIN
DR[1:0]
CM
VREF
1h
DRDY
ID[6:0]
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8.6.2 Register Descriptions
表 9 lists the access codes for the ADS1219 registers.
表 9. Register Access Type Codes
Access Type
Code
R
Description
R
Read
R/W
-n
R/W
Read-Write
Value after reset or the default value
8.6.2.1 Configuration Register (address = 0h) [reset = 00h]
图 41. Configuration Register
7
6
5
4
3
2
1
0
MUX[2:0]
R/W-0h
GAIN
R/W-0h
DR[1:0]
R/W-0h
CM
VREF
R/W-0h
R/W-0h
表 10. Configuration Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
MUX[2:0]
R/W
0h
Input multiplexer configuration
These bits configure the input multiplexer.
000 : AINP = AIN0, AINN = AIN1 (default)
001 : AINP = AIN2, AINN = AIN3
010 : AINP = AIN1, AINN = AIN2
011 : AINP = AIN0, AINN = AGND
100 : AINP = AIN1, AINN = AGND
101 : AINP = AIN2, AINN = AGND
110 : AINP = AIN3, AINN = AGND
111 : AINP and AINN shorted to AVDD / 2
4
GAIN
R/W
R/W
0h
0h
Gain configuration
This bit configures the device gain.
0 : Gain = 1 (default)
1 : Gain = 4
3:2
DR[1:0]
Data rate
These bits control the data rate setting.
00 : 20 SPS (default)
01 : 90 SPS
10 : 330 SPS
11 : 1000 SPS
1
0
CM
R/W
R/W
0h
0h
Conversion mode
This bit sets the conversion mode for the device.
0 : Single-shot conversion mode (default)
1 : Continuous conversion mode
VREF
Voltage reference selection
This bit selects the voltage reference source that is used for the conversion.
0 : Internal 2.048-V reference selected (default)
1 : External reference selected using the REFP and REFN inputs
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8.6.2.2 Status Register (address = 1h) [reset = 00h]
图 42. Status Register
7
6
5
4
3
2
1
0
DRDY
R-0h
RESERVED
R-xxh
表 11. Status Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DRDY
R
0h
Conversion result ready flag
This bit flags if a new conversion result is ready. This bit is reset when conversion
data are read.
0 : No new conversion result available (default)
1 : New conversion result ready
6:0
RESERVED
R
xxh
Reserved
Values are subject to change without notice.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1219 is a precision, 24-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that integrates all
features required to implement the most common system monitoring functions, such as supply voltage, current,
and temperature monitoring. Primary considerations when designing an application with the ADS1219 include
analog input filtering, and establishing an appropriate external reference for ratiometric measurements.
Connecting and configuring the interface appropriately is another concern. These considerations are discussed in
the following sections.
9.1.1 Interface Connections
图 43 shows the principle interface connections for the ADS1219.
Microcontroller with I2C Interface
0.1 mF
3.3 V
3.3 V
3.3 V
3.3 V
1
2
3
4
5
6
7
8
A0
SCL 16
SDA 15
A1
3.3 V
RESET
DGND
AGND
AIN3
AIN2
REFN
DRDY 14
DVDD 13
AVDD 12
AIN0 11
AIN1 10
3.3 V
0.1 mF
Device
3.3 V
0.1 mF
REFP
9
图 43. Interface Connections
The ADS1219 interfaces directly to standard-mode, fast-mode, or fast-mode plus I2C controllers. Any
microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the
ADS1219. Details of the I2C communication protocol of the device can be found in the Programming section. The
ADS1219 does not perform clock-stretching (that is, the device never pulls the clock line low), so this function
does not need to be provided for unless other clock-stretching devices are present on the same I2C bus.
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Application Information (接下页)
Pullup resistors are required on both the SDA and SCL lines, as well as on the open-drain DRDY output. The
size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value
resistors yield lower power consumption when the bus lines are pulled low, but increase the transition times on
the bus, which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense of
higher power consumption when the bus lines are pulled low. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers
may be unable to pull the bus lines low. See the I2C-Bus Specification and User Manual for details on pullup
resistor sizing.
9.1.2 Connecting Multiple Devices on the Same I2C Bus
Up to 16 ADS1219 devices can be connected to a single I2C bus by using different address pin configurations for
each device. Use the address pins, A0 and A1, to set the ADS1219 to one of 16 different I2C addresses. 图 44
shows an example with three ADS1219 devices on the same I2C bus. One set of pullup resistors is required per
bus line. If needed, decrease the pullup resistor values to compensate for the additional bus capacitance
presented by multiple devices and increased line length.
Microcontroller with I2C Interface
DVDD
DVDD
1
2
3
4
5
6
7
8
A0
SCL 16
SDA 15
DVDD
1
2
3
4
5
6
7
8
A0
SCL 16
SDA 15
DVDD
1
2
3
4
5
6
7
8
A0
SCL 16
SDA 15
A1
A1
A1
RESET
DGND
AGND
AIN3
AIN2
REFN
DRDY 14
DVDD 13
AVDD 12
AIN0 11
AIN1 10
RESET
DGND
AGND
AIN3
AIN2
REFN
DRDY 14
DVDD 13
AVDD 12
AIN0 11
AIN1 10
RESET
DGND
AGND
AIN3
AIN2
REFN
DRDY 14
DVDD 13
AVDD 12
AIN0 11
AIN1 10
Device 1
Device 2
Device 3
REFP
9
REFP
9
REFP 9
图 44. Connecting Multiple ADS1219 Devices on the Same I2C Bus
9.1.3 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or
connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AGND is possible
as well, but can yield higher leakage currents on other analog inputs than the previously mentioned options.
Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital
inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. Connections for unused
digital pins are:
•
•
Tie the RESET pin to DVDD if the RESET pin is not used
If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to DVDD using a weak
pullup resistor
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Application Information (接下页)
9.1.4 Analog Input Filtering
Analog input filtering serves two purposes:
•
•
Limits the effect of aliasing during the ADC sampling process
Attenuates unwanted noise components outside the bandwidth of interest
In most cases, a first-order resistor capacitor (RC) filter is sufficient to completely eliminate aliasing or to reduce
the effect of aliasing to a level within the noise floor of the sensor. A good starting point for a system design with
the ADS1219 is to use a differential RC filter with a cutoff frequency set somewhere between the selected output
data rate and 25 kHz. Make the series resistor values as small as possible to reduce voltage drops across the
resistors caused by the device input currents to a minimum. However, the resistors should be large enough to
limit the current into the analog inputs to less than 10 mA in the event of an overvoltage. Then choose the
differential capacitor value to achieve the target filter cutoff frequency. Common-mode filter capacitors to GND
can be added as well, but should always be at least ten times smaller than the differential filter capacitor.
Internal to the device, prior to the buffer inputs, is an EMI filter. The cutoff frequency of this filter is approximately
31.8 MHz, which helps reject high-frequency interferences.
9.1.5 External Reference and Ratiometric Measurements
The full-scale range (FSR) of the ADS1219 is defined by the reference voltage and the gain setting (FSR =
±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to
the specific system needs. An external reference must be used if VIN is greater than 2.048 V. For example, an
external 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing
between 0 V and 5 V.
The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric
measurement the same excitation source that is used to excite the sensor is also used to establish the reference
for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite
both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with
the element being measured. The voltage that develops across the reference element is used as the reference
source for the ADC. These components cancel out in the ADC transfer function because current noise and drift
are common to both the sensor measurement and the reference. The output code is only a ratio of the sensor
element and the value of the reference resistor. The value of the excitation current source itself is not part of the
ADC transfer function.
9.1.6 Establishing Proper Limits on the Absolute Input Voltage
The ADS1219 can be used to measure various types of input signal configurations: single-ended, pseudo-
differential, and fully differential signals. However, configuring the device properly for the respective signal type is
important.
Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonly
called single-ended signals. The absolute input voltages of the ADS1219 can be as low as 100 mV below AGND
and as large as 100 mV above AVDD. Using the gain of 4 is still possible in this configuration. Measuring a 0-mA
to 20-mA or 4-mA to 20-mA signal across a load resistor of 100 Ω referenced to GND is a typical example. The
ADS1219 can directly measure the signal across the load resistor using the internal 2.048-V reference and gain
= 1.
Signals where the negative analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudo-
differential signals.
Fully differential signals in contrast are defined as signals having a constant common-mode voltage where the
positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.
The ADS1219 can measure pseudo-differential and fully differential signals.
Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals
can in general be measured with the ADS1219. A signal is called bipolar when either the positive or negative
input can swing below 0 V. Bipolar signals cannot be measured with the ADS1219.
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Application Information (接下页)
9.1.7 Pseudo Code Example
The following list shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS1219 in continuous
conversion mode. The DRDY pin is used to indicate availability of new conversion data. The default configuration
register settings are changed to gain = 4 and continuous conversion mode.
Power-up;
Delay to allow power supplies to settle and power-on reset to complete; minimum of 500 µs;
Configure the I2C interface of the microcontroller;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt
input;
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Write the respective register configuration with the WREG command (40h, 12h);
As an optional sanity check, read back the configuration register with the RREG command (20h);
Send the START/SYNC command (08h) to start converting in continuous conversion mode;
Loop
{
Wait for DRDY to transition low;
Send the RDATA command (10h) to read 3 bytes of conversion data;
}
Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;
TI recommends running an offset calibration before performing any measurements or when changing the gain or
MUX settings. The internal offset of the device can, for example, be measured by shorting the inputs to mid-
supply (MUX[2:0] = 111). The microcontroller then takes multiple readings from the device with the inputs shorted
and stores the average value in the microcontroller memory. When measuring the sensor signal, the
microcontroller then subtracts the stored offset value from each device reading to obtain an offset compensated
result; the offset can be either positive or negative in value.
版权 © 2018, Texas Instruments Incorporated
33
ADS1219
ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
www.ti.com.cn
9.2 Typical Application
This application example describes how to use the ADS1219 for the most common system monitoring functions
(such as voltage measurement, high-side current measurement using a current sense amplifier, and temperature
measurement using a thermistor or 2-wire RTD). 图 45 shows a typical circuit implementation.
3.3 V
3.3 V
3.3 V
0.1 mF
0.1 mF
0.1 mF
3.3 V
REFP
REFN
AVDD
DVDD
RREF
2.048-V
Reference
Reference
MUX
RF0
ADS1219
AIN0
3.3 V
Thermistor
CF0
SCL
SDA
A0
3.3 V
0.1 mF
AIN1
AIN2
AIN3
Digital Filter
and
Gain
1 or 4
24-bit
ûꢀ ADC
MUX
I2C Interface
A1
RF2
RShunt
INA180
DRDY
RESET
CF2
Buffers
RF3
Low Drift
Oscillator
0 V to 2 V
Load
CF3
DGND
AGND
图 45. Typical System Monitoring Example Using the ADS1219
9.2.1 Design Requirements
表 12 lists the design requirements for this application.
表 12. Design Requirements
DESIGN PARAMETER
Supply voltage
VALUE
3.3 V
Voltage measurement range
Voltage measurement accuracy(1)
Current measurement range (unidirectonal)
Maximum voltage drop across shunt resistor
Current measurement accuracy(1)
Thermistor type
0 V to 2 V
±0.5 mV
0.5 A to 10 A
20 mV
±5 mA
NTC
Thermistor nominal resistance
Thermistor temperature range
Thermistor temperature measurement accuracy(1)
Update rate
10 kΩ
–40°C to +125°C
±0.1°C
100 ms
(1) After offset and gain calibration at TA = 25°C.
9.2.2 Detailed Design Procedure
In order to take one reading from each of the three input signals within 100 ms, the ADS1219 must use a data
rate of 90 SPS or faster. When using a data rate setting of 90 SPS, every conversion takes approximately
11.3 ms according to 表 4. Consequently, all three signals can be measured within approximately 34 ms when
also accounting for the time to read conversion results and to write new configuration register settings between
conversions.
34
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ADS1219
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All three signal measurements use a single-ended measurement implementation. The voltage and current
measurements use the GND connection within the MUX, whereas the thermistor measurement uses an external
GND connection through AIN1 to showcase the two different options for implementing a single-ended
measurement.
RC filters are provided on all three analog inputs of the device, which act as antialiasing filters and to limit the
current into the analog inputs in case of overvoltage events. The filter component values are chosen according to
the guidelines in the Analog Input Filtering section as RF = 1 kΩ and CF = 100 nF to create a filter corner
frequency of fC = 1 / (2π · RF · CF) = 1.6 kHz.
9.2.2.1 Voltage Monitoring
The ADS1219 can measure single-ended signals ranging from AGND to VREF / Gain. In order to monitor voltages
up to 2 V, the device is configured to use the internal 2.048-V reference and gain = 1.
公式 6 details the relationship between output codes of the ADS1219 and the input voltage on AIN3.
VAIN3 = (VREF / Gain) · (Code / 223) = 2.048 V · Code / 223
(6)
An external voltage reference must be provided on the external reference inputs of the device in case larger
voltages than 2.048 V are to be monitored. The device can measure input signals up to the positive analog
supply voltage in case AVDD is used as the positive reference input (REFP) and AGND as the negative
reference input (REFN). However the ADS1219 cannot monitor its own supply voltage in that case. As described
in 公式 6, when using VAIN3 = AVDD and VREF = AVDD, the device will always output a positive full-scale code
irrespective of the value of AVDD. To monitor the supply of the ADC, use a resistor divider instead to divide the
supply voltage down to below 2.048 V and measure the voltage using the internal reference.
The input-referred peak-to-peak noise of the ADC is ideally a factor smaller than the required measurement
accuracy of ±0.5 mV. At 90 SPS using gain = 1 the ADS1219 offers an input-referred noise of 43 µVPP, which
meets this requirement.
9.2.2.2 High-Side Current Measurement
The unidirectional, high-side load current measurement is implemented using a shunt resistor, RShunt, and a
current-sense amplifier, INA180, with a gain of 100. To meet the requirement of a maximum voltage drop across
RShunt of 20 mV at the maximum current of 10 A, the shunt resistor must be RShunt ≤ 20 mV / 10 A = 2 mΩ. The
output signal of the INA180 is fed single-endedly to input AIN2 of the ADS1219. Consequently, the voltage at
AIN2 ranges from 0 V to (2 mΩ · 10 A · 100) = 2 V, which can be measured using the internal 2.048-V reference
and gain = 1 of the ADC.
公式 7 through 公式 9 describe the relationship between output codes of the ADS1219 and the current across
the shunt resistor.
VAIN2 = (VREF / GainADC) · (Code / 223) = 2.048 V · Code / 223
(7)
(8)
(9)
VShunt = VAIN2 / GainINA = VAIN2 / 100
IShunt = VShunt / RShunt = (VREF · Code) / (GainADC· GainINA · RShunt · 223) = (2.048 V · Code) / (100 · 2 mΩ · 223)
9.2.2.3 Thermistor Measurement
The temperature measurement using a 10-kΩ thermistor is implemented using a ratiometric measurement
approach to achieve best accuracy. The analog supply voltage, AVDD, is used as the excitation voltage for the
thermistor in a resistor divider configuration, as well as the external reference voltage, VREF, for the ADS1219.
The relationship between output codes of the ADS1219 and the thermistor resistance, RThermistor, is derived using
the following equations. 公式 10 expresses the input voltage at input AIN0 as the voltage across RThermistor
,
whereas 公式 11 shows how the ADC converts the voltage at AIN0 into corresponding digital codes.
VAIN0 = RThermistor / (RThermistor + RREF) · VREF
VAIN0 = (VREF / Gain) · (Code / 223)
(10)
(11)
Setting 公式 10 equal to 公式 11 and solving for RThermistor yields the relationship between thermistor resistance
and ADC code.
RThermistor / (RThermistor + RREF) = Gain · (Code / 223)
RThermistor = RREF · Gain · (Code / 223) / [1 – Gain · (Code / 223)]
(12)
(13)
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公式 13 proves that the output code and thus the accuracy of the thermistor measurement is independent of the
excitation voltage. The accuracy of the reference resistor, RREF, is typically dominating the measurement
accuracy in such a ratiometric circuit implementation. A high-precision, low-drift resistor is therefore required for
RREF. For best performance, the value of RREF is chosen such that the ratio between RREF and RThermistor_Max
equals the ratio between RThermistor_Min and RREF. 公式 14 is therefore used to calculate RREF
.
RREF² = RThermistor_Min · RThermistor_Max
(14)
At the two temperature measurement extremes, –40°C and +125°C, a typical 10-kΩ NTC exhibits a resistance of
RThermistor_Max = 239.8 kΩ and RThermistor_Min = 425.3 Ω, respectively. Using 公式 14, RREF calculates to 10.1 kΩ. A
10-kΩ resistor is chosen for this example. Consequently, when using 公式 10, the voltage at the ADC input
ranges from 0.13 V to 3.17 V. Thus, an ADC gain = 1 must be used for the measurement.
The microcontroller interfacing to the ADS1219 converts RThermistor into a corresponding thermistor temperature
by either solving the Steinhart-Hart equation or leveraging a look-up table.
9.2.2.4 Register Settings
表 13 summarizes the configuration register bit settings used for the different measurements in this example.
表 13. Configuration Register Settings
MEASUREMENT
Voltage
BIT SETTINGS
1100 0100
DESCRIPTION
AIN3:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREF
AIN2:AGND, gain = 1, DR = 90 SPS, single-shot conversion mode, internal VREF
AIN0:AIN1, gain = 1, DR = 90 SPS, single-shot conversion mode, external VREF
Current
1010 0100
Thermistor
0000 0101
9.2.3 Application Curve
图 46 shows the measurement results for the voltage measurement on AIN3. The measurements are taken at TA
= 25°C. The black curve shows the measurement error in mV without any offset and gain calibration. The red
curve shows the measurement error after offset and gain calibration. The gain calibration removes both the gain
error and the error introduced by the initial inaccuracy of the internal voltage reference.
0.2
0
-0.2
-0.4
-0.6
-0.8
Before Calibration
After Calibration
-1
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VAIN3 (V)
图 46. Measurement Error of Voltage Measurement
36
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ADS1219
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ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
10 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AGND) and digital (DVDD, DGND). The analog power
supply is independent of the digital power supply. The digital supply sets the digital I/O levels.
10.1 Power-Supply Sequencing
The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the
respective analog or digital power-supply voltage and current limits. Wait approximately 500 µs after all power
supplies are stabilized before communicating with the device to allow the power-on reset process to complete.
10.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. As shown in 图 47, AVDD and
DVDD must be decoupled with at least a 0.1-µF capacitor. Place the bypass capacitors as close to the power-
supply pins of the device as possible using low-impedance connections. TI recommends using multi-layer
ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL)
characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise
environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise
immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to
ground planes. Connect analog and digital grounds together as close to the device as possible.
1
2
3
4
5
6
7
8
A0
SCL 16
SDA 15
A1
3.3 V
RESET
DGND
AGND
AIN3
AIN2
REFN
DRDY 14
DVDD 13
AVDD 12
AIN0 11
AIN1 10
Device
3.3 V
0.1 mF
0.1 mF
REFP
9
图 47. Power-Supply Decoupling
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11 Layout
11.1 Layout Guidelines
Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout separates analog components
[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital
components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate
arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching
regulators].
The following basic recommendations for layout of the ADS1219 help achieve the best possible performance of
the ADC. A good design can be ruined with a bad circuit layout.
•
Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Routing digital lines away from analog lines prevents digital noise from coupling back into
analog signals.
•
The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.
Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the
layout, the split between the analog and digital grounds must be connected together at the ADC.
•
•
Fill void areas on signal layers with ground fill.
Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, another path
must be found to return to the source and complete the circuit. If forced into a larger path, the chance that the
signal radiates increases. Sensitive signals are more susceptible to EMI interference.
•
•
Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source
signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI
pickup and reduces the high-frequency impedance at the input of the device.
•
•
Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor
can create a parasitic thermocouple that can add an offset to the measurement. Differential inputs must be
matched for both the inputs going to the measurement source.
Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and
AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO) that have stable properties and low noise characteristics.
38
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ADS1219
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ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
11.2 Layout Example
Vias connect to either the bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
(GND = AGND = DGND).
AIN1
AIN2
AIN3
AIN0
9: REFP
8: REFN
10: AIN1
11: AIN0
7: AIN2
6: AIN3
12: AVDD
13: DVDD
14: DRDY
15: SDA
5: AGND
4: DGND
3: RESET
AVDD
DVDD
2: A1
1: A0
16: SCL
图 48. Layout Example
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12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
•
德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表
德州仪器 (TI)，《INAx180 低侧和高侧电压输出，电流感应放大器》数据表
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
NXP Semiconductors is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
40
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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ADS1219
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ZHCSII0A –JULY 2018–REVISED NOVEMBER 2018
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44
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1219IPW
ADS1219IPWR
ADS1219IPWT
ADS1219IRTER
ADS1219IRTET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
WQFN
WQFN
PW
PW
16
16
16
16
16
90
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS1219
2000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS1219
ADS1219
1219
PW
RTE
RTE
1219
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1219IPWR
ADS1219IPWT
ADS1219IRTER
ADS1219IRTET
TSSOP
TSSOP
WQFN
WQFN
PW
PW
16
16
16
16
2000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
6.9
6.9
3.3
3.3
5.6
5.6
3.3
3.3
1.6
1.6
1.0
1.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q2
Q2
RTE
RTE
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1219IPWR
ADS1219IPWT
ADS1219IRTER
ADS1219IRTET
TSSOP
TSSOP
WQFN
WQFN
PW
PW
16
16
16
16
2000
250
367.0
210.0
367.0
213.0
367.0
185.0
367.0
191.0
35.0
35.0
38.0
35.0
RTE
RTE
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Feb-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
PW TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS1219IPW
16
90
530
10.2
3600
3.5
Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016D
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.15
2.85
A
B
PIN 1 INDEX AREA
3.15
2.85
C
0.8
0.7
SEATING PLANE
0.08 C
0.05
0.00
2X 1.5
SYMM
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
4
9
SYMM
17
2X 1.5
0.8 0.1
12X 0.5
1
12
PIN 1 ID
0.30
0.18
16X
16
13
0.5
0.3
0.1
C A B
16X
0.05
4219118/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.8)
SYMM
SEE SOLDER MASK
DETAIL
16
13
16X (0.6)
12
16X (0.24)
1
17
SYMM
(2.8)
12X (0.5)
(R0.05) TYP
4
9
(
0.2) TYP
VIA
5
8
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219118/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016D
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
0.76)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
12X (0.5)
(2.8)
9
4
(R0.05) TYP
5
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 17
90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4219118/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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