ADS1243IPWTG4 [TI]
24-Bit ANALOG-TO-DIGITAL CONVERTER; 24位模拟数字转换器
| 型号： | ADS1243IPWTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总32页 (文件大小：1103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1242
ADS1243
A
®
D
S
1
A
D
S
2
®
4
2
1
2
4
3
SBAS235H – DECEMBER 2001 – REVISED OCTOBER 2013
24-Bit
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● 24 BITS NO MISSING CODES
The ADS1242 and ADS1243 are precision, wide dynamic
range, delta-sigma, analog-to-digital (A/D) converters with
24-bit resolution operating from 2.7V to 5.25V supplies.
These delta-sigma, A/D converters provide up to 24 bits of no
missing code performance and effective resolution of 21 bits.
● SIMULTANEOUS 50Hz AND 60Hz REJECTION
(–90dB MINIMUM)
● 0.0015% INL
● 21 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
The input channels are multiplexed. Internal buffering can be
selected to provide a very high input impedance for direct
connection to transducers or low-level voltage signals. Burn-
out current sources are provided that allow for the detection
of an open or shorted sensor. An 8-bit digital-to-analog
converter (DAC) provides an offset correction with a range of
50% of the FSR (Full-Scale Range).
● PGA GAINS FROM 1 TO 128
● SINGLE-CYCLE SETTLING
● PROGRAMMABLE DATA OUTPUT RATES
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 5V
● ON-CHIP CALIBRATION
The Programmable Gain Amplifier (PGA) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a second-order
delta-sigma modulator and programmable FIR filter that pro-
vides a simultaneous 50Hz and 60Hz notch. The reference input
is differential and can be used for ratiometric conversion.
● SPI™ COMPATIBLE
● 2.7V TO 5.25V SUPPLY RANGE
● 600µW POWER CONSUMPTION
● UP TO EIGHT INPUT CHANNELS
● UP TO EIGHT DATA I/O
The serial interface is SPI compatible. Up to eight bits of data
I/O are also provided that can be used for input or output. The
ADS1242 and ADS1243 are designed for high-resolution
measurement applications in smart transmitters, industrial
process control, weight scales, chromatography, and portable
instrumentation.
APPLICATIONS
● INDUSTRIAL PROCESS CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
VDD
VREF+
VREF–
XIN
XOUT
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES
VDD
Clock Generator
2µA
Offset
DAC
AIN0/D0
AIN1/D1
AIN2/D2
AIN3/D3
AIN4/D4
AIN5/D5
AIN6/D6
A = 1:128
PGA
IN+
2nd-Order
Modulator
Digital
MUX
+
Controller
Registers
BUF
Filter
IN–
A
IN7/D7
ADS1243
Only
SCLK
DIN
Serial Interface
DRDY
2µA
DOUT
GND
CS
GND
PDWN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2001-2013, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
VDD to GND ........................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
A
IN .................................................................... GND – 0.5V to VDD + 0.5V
Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................... –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this document,
or see the TI website at www.ti.com.
DIGITAL CHARACTERISTICS: TMIN to TMAX, VDD 2.7V to 5.25V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Input/Output
Logic Family
CMOS
Logic Level: VIH
0.8 • VDD
GND
VDD
0.2 • VDD
V
V
(1)
VIL
VOH
VOL
IOH = 1mA
IOL = 1mA
VI = VDD
VI = 0
VDD – 0.4
GND
V
V
µA
µA
MHz
ns
GND + 0.4
10
Input Leakage: IIH
IIL
Master Clock Rate: fOSC
Master Clock Period: tOSC
–10
1
200
5
1/fOSC
1000
NOTE: (1) VIL for XIN is GND to GND + 0.05V.
ADS1242, 1243
2
SBAS235H
www.ti.com
ELECTRICAL CHARACTERISTICS: VDD = 5V
All specifications TMIN to TMAX, VDD = +5V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
ADS1242
ADS1243
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7)
Analog Input Range
Buffer OFF
Buffer ON
GND – 0.1
GND + 0.05
VDD + 0.1
VDD – 1.5
V
V
Full-Scale Input Range
(In+) – (In–), See Block Diagram, RANGE = 0
RANGE = 1
±VREF /PGA
±VREF /(2 • PGA)
V
V
Differential Input Impedance
Buffer OFF
Buffer ON
5/PGA
5
MΩ
GΩ
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
–3dB
–3dB
–3dB
1.65
3.44
14.6
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
Offset DAC Monotonicity
Offset DAC Gain Error
8
Bits
%
±10
Offset DAC Gain Error Drift
1
ppm/°C
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error(1)
Offset Drift(1)
Gain Error(1)
Gain Error Drift(1)
Common-Mode Rejection
No Missing Codes
End Point Fit
24
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
±0.0015
7.5
0.02
0.005
0.5
at DC
100
f
CM = 60Hz, fDATA = 15Hz
130
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 15Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 15Hz
SIG = 60Hz, fDATA = 15Hz
Output Noise
Power-Supply Rejection
See Typical Characteristics
95
(2)
at DC, dB = –20 log(∆VOUT /VDD
)
80
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
RANGE = 1
0
0.1
0.1
VDD
2.6
VDD
V
V
V
2.5
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
at DC
120
120
1.3
dB
dB
µA
fVREFCM = 60Hz, fDATA = 15Hz
VREF = 2.5V
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Current
VDD
4.75
5.25
375
800
425
1400
V
µA
µA
µA
µA
µA
µA
nA
mW
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
SLEEP Mode
Read Data Continuous Mode
PDWN
PGA = 1, Buffer OFF
240
450
290
960
60
230
0.5
1.2
Power Dissipation
1.9
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) Calibration can minimize these errors.
(2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1242, 1243
3
SBAS235H
www.ti.com
ELECTRICAL CHARACTERISTICS: VDD = 3V
All specifications TMIN to TMAX, VDD = +3V, fMOD = 19.2kHz, PGA = 1, Buffer ON, fDATA = 15Hz, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, unless otherwise specified.
ADS1242
ADS1243
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7)
Analog Input Range
Buffer OFF
Buffer ON
GND – 0.1
GND + 0.05
VDD + 0.1
VDD – 1.5
V
V
Full-Scale Input Voltage Range
Input Impedance
(In+) – (In–) See Block Diagram, RANGE = 0
RANGE = 1
±VREF /PGA
±VREF /(2 • PGA)
V
V
MΩ
GΩ
Buffer OFF
Buffer ON
5/PGA
5
Bandwidth
fDATA = 3.75Hz
fDATA = 7.50Hz
fDATA = 15.00Hz
–3dB
–3dB
–3dB
1.65
3.44
14.6
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User-Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
RANGE = 0
RANGE = 1
±VREF /(2 • PGA)
±VREF /(4 • PGA)
V
V
Offset DAC Monotonicity
Offset DAC Gain Error
8
Bits
%
±10
Offset DAC Gain Error Drift
2
ppm/°C
SYSTEM PERFORMANCE
Resolution
Integral Nonlinearity
Offset Error(1)
Offset Drift(1)
Gain Error(1)
Gain Error Drift(1)
Common-Mode Rejection
No Missing Codes
End Point Fit
24
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
±0.0015
15
0.04
0.01
1.0
at DC
100
f
CM = 60Hz, fDATA = 15Hz
130
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 15Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 15Hz
SIG = 60Hz, fDATA = 15Hz
Output Noise
Power-Supply Rejection
See Typical Characteristics
90
(2)
at DC, dB = –20 log(∆VOUT /VDD
)
75
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–), RANGE = 0
0
0.1
0.1
VDD
1.30
2.6
V
V
V
1.25
2.5
RANGE = 1
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
at DC
120
120
0.65
dB
dB
µA
fVREFCM = 60Hz, fDATA = 15Hz
VREF = 1.25
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
Current
VDD
2.7
3.3
375
700
375
1325
V
µA
µA
µA
µA
µA
µA
nA
mW
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
SLEEP Mode
Read Data Continuous Mode
PDWN = 0
PGA = 1, Buffer OFF
190
460
240
870
75
113
0.5
0.6
Power Dissipation
1.2
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) Calibration can minimize these errors.
(2) ∆VOUT is a change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1242, 1243
4
SBAS235H
www.ti.com
PIN CONFIGURATION (ADS1242)
PIN CONFIGURATION (ADS1243)
Top View
TSSOP
Top View
TSSOP
VDD
XIN
1
2
3
4
5
6
7
8
9
20 DRDY
19 SCLK
18 DOUT
17 DIN
VDD
XIN
1
2
3
4
5
6
7
8
16 DRDY
15 SCLK
14 DOUT
13 DIN
XOUT
XOUT
PDWN
VREF+
VREF–
AIN0/D0
PDWN
VREF+
VREF–
AIN0/D0
16 CS
ADS1243
ADS1242
12 CS
15 GND
11 GND
14
13
12
11
AIN3/D3
AIN2/D2
AIN7/D7
AIN6/D6
10
9
A
IN3/D3
IN2/D2
A
A
A
IN1/D1
A
IN1/D1
A
IN4/D4
IN5/D5 10
PIN DESCRIPTIONS (ADS1243)
PIN DESCRIPTIONS (ADS1242)
PIN
PIN
NUMBER
NAME
DESCRIPTION
NUMBER
NAME
DESCRIPTION
1
2
3
VDD
XIN
Power Supply
Clock Input
1
2
3
VDD
XIN
Power Supply
Clock Input
XOUT
Clock Output, used with crystal or ceramic
resonator.
XOUT
Clock Output, used with crystal or ceramic
resonator.
4
PDWN
Active LOW. Power Down. The power down func-
tion shuts down the analog and digital circuits.
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0/Data I/O 0
Analog Input 1/Data I/O 1
Analog Input 4/Data I/O 4
Analog Input 5/Data I/O 5
Analog Input 6/Data I/O 6
Analog Input 7/Data I/O 7
Analog Input 2/Data I/O 2
Analog Input 3/Data I/O 3
Ground
4
PDWN
Active LOW. Power Down. The power down func-
tion shuts down the analog and digital circuits.
5
6
7
8
VREF+
VREF–
AIN0/D0
AIN1/D1
5
6
VREF+
VREF–
Positive Differential Reference Input
Negative Differential Reference Input
Analog Input 0/Data I/O 0
Analog Input 1/Data I/O 1
Analog Input 2/Data I/O 2
Analog Input 3/Data I/O 3
Ground
7
A
IN0/D0
IN1/D1
IN2/D2
IN3/D3
GND
CS
9
AIN4/D4
10
11
12
13
14
15
16
17
18
19
20
AIN5/D5
AIN6/D6
AIN7/D7
AIN2/D2
AIN3/D3
GND
CS
DIN
DOUT
SCLK
DRDY
8
A
A
A
9
10
11
12
13
14
15
16
Active LOW, Chip Select
Serial Data Input, Schmitt Trigger
Serial Data Output
Active LOW, Chip Select
Serial Data Input, Schmitt Trigger
Serial Data Output
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
DIN
DOUT
SCLK
DRDY
Serial Clock, Schmitt Trigger
Active LOW, Data Ready
ADS1242, 1243
5
SBAS235H
www.ti.com
TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
DIN
t2
t4
t5
t6
t11
MSB
LSB
t7
t8
t9
(Command or Command and Data)
MSB(1)
LSB(1)
DOUT
NOTE: (1) Bit order = 0.
ADS1242 or ADS1243
Resets On
SCLK Reset Waveform
Falling Edge
300 • tOSC < t12 < 500 • tOSC
t13 : > 5 • tOSC
t13
t13
550 • tOSC < t14 < 750 • tOSC
SCLK
1050 • tOSC < t15 < 1250 • tOSC
t12
t14
t15
DIAGRAM 1.
t16
tDATA
DRDY
PDWN
t17
t18
SCLK
t19
DIAGRAM 2.
TIMING CHARACTERISTICS TABLE
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4
tOSC Periods
3
DRDY Periods
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS low to first SCLK Edge; Setup Time(2)
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
200
0
ns
ns
ns
ns
50
50
Delay between last SCLK edge for DIN and first SCLK edge for DOUT
:
RDATA, RDATAC, RREG, WREG
SCLK Edge to Valid New DOUT
50
tOSC Periods
ns
(1)
t7
50
10
(1)
t8
SCLK Edge to DOUT, Hold Time
0
6
ns
t9
Last SCLK Edge to DOUT Tri-State
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
CS LOW time after final SCLK edge.
Read from the device
0
8
tOSC Periods
tOSC Periods
Write to the device
t11
Final SCLK edge of one command until first edge SCLK
of next command:
RREG, WREG, DSYNC, SLEEP, RDATA, RDATAC, STOPC
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
4
2
4
16
4
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
RESET (also SCLK Reset)
t16
t17
t18
t19
Pulse Width
Allowed analog input change for next valid conversion.
DOR update, DOR data not valid.
First SCLK after DRDY goes LOW:
RDATAC Mode
5000
4
10
0
tOSC Periods
tOSC Periods
Any other mode
NOTES: (1) Load = 20pF 10kΩ to GND.
(2) CS may be tied LOW.
ADS1242, 1243
6
SBAS235H
www.ti.com
TYPICAL CHARACTERISTICS
All specifications VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS vs PGA SETTING
EFFECTIVE NUMBER OF BITS vs PGA SETTING
DR = 10
22
21
20
19
18
17
16
15
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
DR = 10
DR = 01
DR = 01
DR = 00
DR = 00
Buffer ON
Buffer OFF
1
2
4
8
16
32
64
128
1
2
4
8
16
32
64
128
PGA Setting
PGA Setting
NOISE vs INPUT SIGNAL
EFFECTIVE NUMBER OF BITS vs PGA SETTING
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
DR = 10
DR = 01
DR = 00
Buffer OFF, VREF = 1.25V
–2.5
–1.5
–0.5
0.5
1.5
2.5
1
2
4
8
16
32
64
128
VIN (V)
PGA Setting
COMMON-MODE REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
140
120
100
80
140
120
100
80
60
60
40
40
20
20
Buffer ON
10
Buffer ON
10
0
0
1
100
1k
10k
100k
1
100
1k
10k
100k
Frequency of Power Supply (Hz)
Frequency of Power Supply (Hz)
ADS1242, 1243
7
SBAS235H
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
GAIN vs TEMPERATURE
OFFSET vs TEMPERATURE
(Cal at 25°C)
(Cal at 25°C)
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
50
0
PGA16
PGA1
–50
PGA64
–100
–150
–200
PGA128
–50
–30
–10
10
30
50
70
90
–50
–30
–10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
CURRENT vs TEMPERATURE
(Buffer Off)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
260
250
240
230
220
210
200
190
10
8
–40°C
6
4
+85°C
2
0
–2
–4
–6
–8
–10
+25°C
–50
–30
–10
10
30
50
70
90
–2.5 –2.0 –1.5 –1.0 –0.5
0
0.5 1.0 1.5 2.0 2.5
Temperature (°C)
V
IN (V)
CURRENT vs VOLTAGE
SUPPLY CURRENT vs SUPPLY
350
300
250
200
150
100
50
300
250
200
150
100
50
Normal
4.91MHz
Normal
2.45MHz
Normal
2.45MHz
SLEEP
4.91MHz
Normal
4.91MHz
SLEEP
2.45MHz
SLEEP
4.91MHz
Power Down
SLEEP
2.45MHz
0
Power Down
3.5
0
–50
3.0
3.25
3.5
3.75
4.0
4.25
4.5
4.75
5.0
3.0
4.0
4.5
5.0
VDD (V)
VDD (V)
ADS1242, 1243
8
SBAS235H
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
All specification VDD = +5V, fOSC = 2.4576MHz, PGA = 1, fDATA = 15Hz, and VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
OFFSET DAC
OFFSET vs TEMPERATURE
(Cal at 25°C)
NOISE HISTOGRAM
200
170
140
110
80
3500
3000
2500
2000
1500
1000
500
10k Readings
IN = 0V
V
50
20
–10
–40
–70
–100
0
–50
–30
–10
10
30
50
70
90
–3.5 –3.0 –2.5 –2.0 –1.5 –1 –0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
Temperature (°C)
ppm of FS
OFFSET DAC
GAIN vs TEMPERATURE
(Cal at 25°C)
OFFSET DAC
NOISE vs SETTING
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–50
–30
–10
10
30
50
70
90
–128 –96
–64 –32
0
32
64
96
128
Temperature (°C)
Offset DAC Setting
ADS1242, 1243
9
SBAS235H
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channel. With this method, it is possible to have up to seven
single-ended input channels or four independent differential
input channels for the ADS1243, and three single-ended
input channels or two independent differential input channels
for the ADS1242.
OVERVIEW
INPUT MULTIPLEXER
The input multiplexer provides for any combination of differ-
ential inputs to be selected on any of the input channels, as
shown in Figure 1. For example, if AIN0 is selected as the
positive differential input channel, any other channel can be
selected as the negative terminal for the differential input
The ADS1242 and ADS1243 feature a single-cycle settling
digital filter that provides valid data on the first conversion
after a new channel selection. In order to minimize the
settling error, synchronize MUX changes to the conversion
beginning, which is indicated by the falling edge of DRDY. In
other words, issuing a MUX change through the WREG
command immediately after DRDY goes LOW minimizes the
settling error. Increasing the time between the conversion
beginning (DRDY goes LOW) and the MUX change com-
mand (tDELAY) results in a settling error in the conversion
data, as shown in Figure 2.
AIN0/D0
AIN1/D1
VDD
Burnout Current Source
AIN2/D2
BURNOUT CURRENT SOURCES
The Burnout Current Sources can be used to detect sensor
short-circuit or open-circuit conditions. Setting the Burnout
Current Sources (BOCS) bit in the SETUP register activates
two 2µA current sources called burnout current sources. One
of the current sources is connected to the converter’s nega-
tive input and the other is connected to the converter’s
positive input.
AIN3/D3
Input
Buffer
AIN4/D4
AIN5/D5
Burnout Current Source
Figure 3 shows the situation for an open-circuit sensor. This
is a potential failure mode for many kinds of remotely con-
nected sensors. The current source on the positive input acts
as a pull-up, causing the positive input to go to the positive
analog supply, and the current source on the negative input
acts as a pull-down, causing the negative input to go to
ground. The ADS1242/43 therefore outputs full-scale (7FFFFF
Hex).
AIN6/D6
GND
A
IN7/D7
ADS1243
Only
FIGURE 1. Input Multiplexer Configuration.
Figure 4 shows a short-circuited sensor. Since the inputs are
New Conversion Begins,
Complete Previous Conversion
Previous Conversion Data
New Conversion Complete
DRDY
tDELAY
SCLK
DIN
MSB
LSB
SETTLING ERROR vs DELAY TIME
CLK = 2.4576MHz
f
10
1
0.1
0.01
0.001
0.0001
0.00001
0.000001
0
2
4
6
8
10
12
14
16
Delay Time, tDELAY (ms)
FIGURE 2. Input Multiplexer Configuration.
10
ADS1242, 1243
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current required by the buffer depends on the PGA setting.
When the PGA is set to 1, the buffer uses approximately
50µA; when the PGA is set to 128, the buffer uses approxi-
VDD
mately 500µA.
2µA
VDD
PGA
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can improve the
effective resolution of the A/D converter. For instance, with a
PGA of 1 on a 5V full-scale signal, the A/D converter can
resolve down to 1µV. With a PGA of 128 and a full-scale signal
of 39mV, the A/D converter can resolve down to 75nV. VDD
current increases with PGA settings higher than 4.
ADC
OPEN CIRCUIT
CODE = 0x7FFFFFH
0V
2µA
FIGURE 3. Burnout detection while sensor is open-circuited.
OFFSET DAC
The input to the PGA can be shifted by half the full-scale input
range of the PGA using the Offset DAC (ODAC) register. The
ODAC register is an 8-bit value; the MSB is the sign and the
seven LSBs provide the magnitude of the offset. Using the
offset DAC does not reduce the performance of the A/D
converter. For more details on the ODAC in the ADS1242/43,
please refer to TI application report SBAA077 (available
through the TI website).
shorted and at the same potential, the ADS1242/43 signal
outputs are approximately zero. (Note that the code for
shorted inputs is not exactly zero due to internal series
resistance, low-level noise and other error sources.)
INPUT BUFFER
VDD
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register, as shown in
Table I.
2µA
VDD/2
SHORT
CIRCUIT
ADC
CODE
0
VDD/2
2µA
SPEED
BIT
DR BITS
01
1st NOTCH
FREQ.
fOSC
fMOD
00
10
2.4576MHz
0
1
0
1
19,200Hz 15Hz 7.5Hz 3.75Hz
9,600Hz 7.5Hz 3.75Hz 1.875Hz
50/60Hz
25/30Hz
100/120Hz
50/60Hz
4.9152MHz
38,400Hz 30Hz
15Hz
7.5Hz
FIGURE 4. Burnout detection while sensor is short-circuited.
19,200Hz 15Hz 7.5Hz 3.75Hz
TABLE I. Output Configuration.
The input impedance of the ADS1242/43 without the buffer
enabled is approximately 5MΩ/PGA. For systems requiring
very high input impedance, the ADS1242/43 provides a
chopper-stabilized differential FET-input voltage buffer. When
activated, the buffer raises the ADS1242/43 input impedance
to approximately 5GΩ.
CALIBRATION
The offset and gain errors can be minimized with calibration.
The ADS1242 and ADS1243 support both self and system
calibration.
Self-calibration of the ADS1242 and ADS1243 corrects inter-
nal offset and gain errors and is handled by three commands:
SELFCAL, SELFGAL, and SELFOCAL. The SELFCAL com-
mand performs both an offset and gain calibration. SELFGCAL
performs a gain calibration and SELFOCAL performs an
offset calibration, each of which takes two tDATA periods to
complete. During self-calibration, the ADC inputs are discon-
nected internally from the input pins. The PGA must be set to
1 prior to issuing a SELFCAL or SELFGCAL command. Any
PGA is allowed when issuing a SELFOCAL command. For
The buffer’s input range is approximately 50mV to
VDD – 1.5V. The buffer’s linearity will degrade beyond this
range. Differential signals should be adjusted so that both
signals are within the buffer’s input range.
The buffer can be enabled using the BUFEN pin or the
BUFEN bit in the ACR register. The buffer is on when the
BUFEN pin is high and the BUFEN bit is set to one. If the
BUFEN pin is low, the buffer is disabled. If the BUFEN bit is
set to zero, the buffer is also disabled.
The buffer draws additional current when activated. The
ADS1242, 1243
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SBAS235H
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example, if using PGA = 64, first set PGA = 1 and issue
SELFGCAL. Afterwards, set PGA = 64 and issue SELFOCAL.
For operation with a reference voltage greater than
(VDD – 1.5) volts, the buffer must also be turned off during
gain self-calibration to avoid exceeding the buffer input
range.
XIN
C1
C2
Crystal
XOUT
System calibration corrects both internal and external offset
and gain errors. While performing system calibration, the
appropriate signal must be applied to the inputs. The system
offset calibration command (SYSOCAL) requires a zero input
differential signal (see Table IV, page 18). It then computes
the offset that nullifies the offset in the system. The system
gain calibration command (SYSGCAL) requires a positive
full-scale input signal. It then computes a value to nullify the
gain error in the system. Each of these calibrations takes two
FIGURE 5. Crystal Connection.
CLOCK
PART
NUMBER
SOURCE FREQUENCY
C1
C2
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20pF 0-20pF ECS, ECSD 2.45 - 32
0-20pF 0-20pF
0-20pF 0-20pF
ECS, ECSL 4.91
ECS, ECSD 4.91
t
DATA periods to complete. System gain calibration is recom-
0-20pF 0-20pF CTS, MP 042 4M9182
mended for the best gain calibration at higher PGAs.
Calibration should be performed after power on, a change in
temperature, or a change of the PGA. The RANGE bit (ACR bit
2) must be zero during calibration.
TABLE II. Recommended Crystals.
DIGITAL FILTER
Calibration removes the effects of the ODAC; therefore, dis-
able the ODAC during calibration, and enable again after
calibration is complete.
The ADS1242 and ADS1243 have a 1279 tap linear phase
Finite Impulse Response (FIR) digital filter that a user can
configure for various output data rates. When a 2.4576MHz
crystal is used, the device can be programmed for an output
data rate of 15Hz, 7.5Hz, or 3.75Hz. Under these conditions,
the digital filter rejects both 50Hz and 60Hz interference. Figure
6 shows the digital filter frequency response for data output
rates of 15Hz, 7.5Hz, and 3.75Hz.
At the completion of calibration, the DRDY signal goes low,
indicating the calibration is finished. The first data after
calibration should be discarded since it may be corrupt from
calibration data remaining in the filter. The second data is
always valid.
If a different data output rate is desired, a different crystal
frequency can be used. However, the rejection frequencies
shift accordingly. For example, a 3.6864MHz master clock with
the default register condition has:
EXTERNAL VOLTAGE REFERENCE
The ADS1242 and ADS1243 require an external voltage
reference. The selection for the voltage reference value is
made through the ACR register.
(3.6864MHz/2.4576MHz) • 15Hz = 22.5Hz data output rate
and the first and second notch is:
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin, +VREF or
–VREF, can range from GND to VDD. However, the following
limitations apply:
1.5 • (50Hz and 60Hz) = 75Hz and 90Hz
DATA I/O INTERFACE
The ADS1242 has four pins and the ADS1243 has eight pins
that serve a dual purpose as both analog inputs and data
I/O. These pins are configured through the IOCON, DIR, and
DIO registers and can be individually configured as either
analog inputs or data I/O. See Figure 7 (page 14) for the
equivalent schematic of an Analog/Data I/O pin.
For VDD = 5.0V and RANGE = 0 in the ACR, the differential
V
REF must not exceed 2.5V.
For VDD = 5.0V and RANGE = 1 in the ACR, the differential
REF must not exceed 5V.
For VDD = 3.0V and RANGE = 0 in the ACR, the differential
REF must not exceed 1.25V.
V
V
The IOCON register defines the pin as either an analog input
or data I/O. The power-up state is an analog input. If the pin
is configured as an analog input in the IOCON register, the
DIR and DIO registers have no effect on the state of the pin.
For VDD = 3.0V and RANGE = 1 in the ACR, the differential
VREF must not exceed 2.5V.
CLOCK GENERATOR
If the pin is configured as data I/O in the IOCON register,
then DIR and DIO are used to control the state of the pin.
The DIR register controls the direction of the data pin, either
as an input or output. If the pin is configured as an input in
the DIR register, then the corresponding DIO register bit
reflects the state of the pin. Make sure the pin is driven to a
logic one or zero when configured as an input to prevent
The clock source for the ADS1242 and ADS1243 can be
provided from a crystal, oscillator, or external clock. When the
clock source is a crystal, external capacitors must be provided
to ensure start-up and stable clock frequency. This is shown in
both Figure 5 and Table II. XOUT is only for use with external
crystals and it should not be used as a clock driver for external
circuitry.
ADS1242, 1243
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SBAS235H
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ADS1242 AND ADS1243
FILTER RESPONSE WHEN fDATA = 15Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 15Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 7.5Hz
ADS1242 AND ADS1243
FILTER RESPONSE WHEN fDATA = 7.5Hz
–40
–50
0
–20
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
ADS1242 AND ADS1243
FILTER RESPONSE WHEN fDATA = 3.75Hz
FREQUENCY RESPONSE FROM 45Hz to 65Hz
WHEN fDATA = 3.75Hz
0
–20
–40
–50
–60
–40
–70
–60
–80
–80
–90
–100
–120
–140
–160
–180
–100
–110
–120
–130
–140
0
20
40 60
80 100 120 140 160 180 200
Frequency (Hz)
45
50
55
60
65
Frequency (Hz)
f
OSC = 2.4576MHz, SPEED = 0 or fOSC = 4.9152MHz, SPEED = 1
ATTENUATION
DATA
–3dB
OUTPUT RATE
BANDWIDTH
fIN = 50 ± 0.3Hz
fIN = 60 ± 0.3Hz
fIN = 50 ± 1Hz
fIN = 60 ± 1Hz
15Hz
7.5Hz
3.75Hz
14.6Hz
3.44Hz
1.65Hz
–80.8dB
–85.9dB
–93.8dB
–87.3dB
–87.4dB
–88.6dB
–68.5dB
–71.5dB
–86.8dB
–76.1dB
–76.2dB
–77.3dB
FIGURE 6. Filter Frequency Responses.
ADS1242, 1243
13
SBAS235H
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excess current dissipation. If the pin is configured as an
output in the DIR register, then the corresponding DIO
register bit value determines the state of the output pin
(0 = GND, 1 = VDD).
Data Input (DIN) and Data Output (DOUT)
The data input (DIN) and data output (DOUT) receive and send
data from the ADS1242 and ADS1243. DOUT is high imped-
ance when not in use to allow DIN and DOUT to be connected
together and driven by a bidirectional bus. Note: the Read
Data Continuous Mode (RDATAC) command should not be
issued when DIN and DOUT are connected. While in RDATAC
mode, DIN looks for the STOPC or RESET command. If
either of these 8-bit bytes appear on DOUT (which is con-
nected to DIN), the RDATAC mode ends.
It is still possible to perform A/D conversions on a pin
configured as data I/O. This may be useful as a test mode,
where the data I/O pin is driven and an A/D conversion is
done on the pin.
IOCON
DIR
DATA READY (DRDY) PIN
The DRDY line is used as a status signal to indicate when
data is ready to be read from the internal data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
DIO WRITE
AINx/Dx
To Analog Mux
DIO READ
FIGURE 7. Analog/Data Interface Pin.
The status of DRDY can also be obtained by interrogating bit
7 of the ACR register (address 2H). The serial interface can
operate in 3-wire mode by tying the CS input LOW. In this
case, the SCLK, DIN, and DOUT lines are used to communi-
cate with the ADS1242 and ADS1243. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port bit of
the microcontroller.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1242 and ADS1243.
The ADS1242 and ADS1243 operate in slave-only mode.
The serial interface is a standard four-wire SPI (CS, SCLK,
DIN and DOUT) interface.
Chip Select (CS
)
DSYNC OPERATION
The chip select (CS) input must be externally asserted
before communicating with the ADS1242 or ADS1243. CS
must stay LOW for the duration of the communication.
Whenever CS goes HIGH, the serial interface is reset. CS
may be hard-wired LOW.
Synchronization can be achieved through the DSYNC
command. When the DSYNC command is sent, the digital
filter is reset on the edge of the last SCLK of the DSYNC
command. The modulator is held in RESET until the next
edge of SCLK is detected. Synchronization occurs on the
next rising edge of the system clock after the first SCLK
Serial Clock (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock DIN and DOUT data. Make sure to have
a clean SCLK to prevent accidental double-shifting of the
data. If SCLK is not toggled within three DRDY pulses, the
serial interface resets on the next SCLK pulse and starts a
new communication cycle. A special pattern on SCLK resets
the entire chip; see the RESET section for additional informa-
tion.
following the DSYNC command.
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally.
ADS1242, 1243
14
SBAS235H
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ADS1242 AND ADS1243
REGISTERS
The operation of the device is set up through individual
registers. Collectively, the registers contain all the informa-
tion needed to configure the part, such as data format,
multiplexer settings, calibration settings, data rate, etc. The
16 registers are shown in Table III.
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
SETUP
MUX
ID
ID
ID
ID
BOCS
NSEL3
BIT ORDER
OSET3
DIO_3
PGA2
NSEL2
RANGE
OSET2
DIO_2
DIR_2
IO2
PGA1
NSEL1
DR1
PGA0
NSEL0
DR0
PSEL3
DRDY
SIGN
PSEL2
U/B
PSEL1
SPEED
OSET5
DIO_5
DIR_5
IO5
PSEL0
BUFEN
OSET4
DIO_4
DIR_4
IO4
ACR
ODAC
DIO
OSET6
DIO_6
DIR_6
IO6
OSET1
DIO_1
DIR_1
IO1
OSET0
DIO_0
DIR_0
IO0
DIO_7
DIR_7
IO7
DIR
DIR_3
IOCON
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
DOR2
DOR1
DOR0
IO3
OCR07
OCR15
OCR23
FSR07
FSR15
FSR23
DOR23
DOR15
DOR07
OCR06
OCR14
OCR22
FSR06
FSR14
FSR22
DOR22
DOR14
DOR16
OCR05
OCR13
OCR21
FSR05
FSR13
FSR21
DOR21
DOR13
FSR21
OCR04
OCR12
OCR20
FSR04
FSR12
FSR20
DOR20
DOR12
DOR04
OCR03
OCR11
OCR19
FSR03
FSR11
FSR19
DOR19
DOR11
DOR03
OCR02
OCR10
OCR18
FSR02
FSR10
FSR18
DOR18
DOR10
DOR02
OCR01
OCR09
OCR17
FSR01
FSR09
FSR17
DOR17
DOR09
DOR01
OCR00
OCR08
OCR16
FSR00
FSR08
FSR16
DOR16
DOR08
DOR00
TABLE III. Registers.
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iiii0000
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
NSEL1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL0
ID
ID
ID
ID
BOCS
PGA2
PGA1
PGA0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
bit 7-4 Factory Programmed Bits
bit 3 BOCS: Burnout Current Source
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1111 = Reserved
0 = Disabled (default)
1 = Enabled
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
010 = 4
011 = 8
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
100 = 16
101 = 32
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1111 = Reserved
110 = 64
111 = 128
ADS1242, 1243
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SBAS235H
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ACR (Address 02H) Analog Control Register
ODAC (Address 03 ) Offset DAC
Reset Value = X0H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
DR1
bit 0
DR0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SPEED
BUFEN BIT ORDER RANGE
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
U/ : Data Format
bit 7
Sign
0 = Positive
1 = Negative
bit 6
B
0 = Bipolar (default)
1 = Unipolar
VREF
OSET[6 : 0]
127
Offset =
•
RANGE = 0
RANGE = 1
2 • PGA
U/B
ANALOG INPUT
DIGITAL OUTPUT (Hex)
+FSR
Zero
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
VREF
OSET[6 : 0]
127
0
Offset =
•
4 • PGA
–FSR
+FSR
Zero
1
NOTE: The offset DAC must be enabled after calibration or the calibration
nullifies the effects.
–FSR
bit 5
bit 4
bit 3
SPEED: Modulator Clock Speed
0 = fMOD = fOSC/128 (default)
1 = fMOD = fOSC/256
DIO (Address 04H) Data I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BUFEN: Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
DIO 7
DIO 6
DIO 5
DIO 4
DIO 3
DIO 2
DIO 1
DIO 0
If the IOCON register is configured for data, a value written
to this register appears on the data I/O pins if the pin is
configured as an output in the DIR register. Reading this
register returns the value of the data I/O pins.
BIT ORDER: Data Output Bit Order
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted in or out MSB first.
Bits 4 to 7 are not used in ADS1242.
bit 2
RANGE: Range Select
0 = Full-Scale Input Range equal to ±VREF
(default).
DIR (Address 05H) Direction Control for Data I/O
Reset Value = FFH
1 = Full-Scale Input Range equal to ±1/2 VREF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
NOTE: This allows reference voltages as high as
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
V
DD, but even with a 5V reference voltage the
calibration must be performed with this bit set to 0.
bit 1-0 DR1: DR0: Data Rate
(fOSC = 2.4576MHz, SPEED = 0)
Each bit controls whether the corresponding data I/O pin is
an output (= 0) or input (= 1). The default power-up state is
as inputs.
00 = 15Hz (default)
01 = 7.5Hz
Bits 4 to 7 are not used in ADS1242.
10 = 3.75Hz
IOCON (Address 06H) I/O Configuration Register
11 = Reserved
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
IO4
bit 3
IO3
bit 2
IO2
bit 1
IO1
bit 0
IO0
IO7
IO6
IO5
bit 7-0 IO7: IO0: Data I/O Configuration
0 = Analog (default)
1 = Data
Configuring the pin as a data I/O pin allows it to be controlled
through the DIO and DIR registers.
Bits 4 to 7 are not used in ADS1242.
OCR0 (Address 07H) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
ADS1242, 1243
16
SBAS235H
www.ti.com
OCR1 (Address 08H) Offset Calibration Coefficient
(Middle Byte)
FSR2 (Address 0CH) Full-Scale Register
(Most Significant Byte)
Reset Value = 00H
Reset Value = 55H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
FSR23
FSR22
FSR21
FSR20
FSR19
FSR18
FSR17
FSR16
OCR2 (Address 09H) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
DOR2 (Address 0DH) Data Output Register
(Most Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
FSR0 (Address 0AH) Full-Scale Register
(Least Significant Byte)
DOR1 (Address 0EH) Data Output Register
(Middle Byte) (Read Only)
Reset Value = 59H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR09
DOR08
FSR1 (Address 0BH) Full-Scale Register
(Middle Byte)
Reset Value = 55H
DOR0 (Address 0FH) Data Output Register
(Least Significant Byte) (Read Only)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR11
FSR10
FSR09
FSR08
DOR07
DOR06
DOR05
DOR04
DOR03
DOR02
DOR01
DOR00
ADS1242, 1243
17
SBAS235H
www.ti.com
ADS1242 AND ADS1243 CONTROL COMMAND DEFINITIONS
The commands listed in Table IV control the operations of
the ADS1242 and ADS1243. Some of the commands are
stand-alone commands (for example, RESET) while others
require additional bytes (for example, WREG requires the
count and data bytes).
Operands:
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
COMMANDS
DESCRIPTION
OP CODE
2nd COMMAND BYTE
RDATA
RDATAC
STOPC
RREG
WREG
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
Read Data
Read Data Continuously
Stop Read Data Continuously
Read from REG “rrrr”
Write to REG “rrrr”
Offset and Gain Self Cal
Self Offset Cal
Self Gain Cal
Sys Offset Cal
Sys GainCal
Wakup from SLEEP Mode
Sync DRDY
0000 0001 (01H)
0000 0011 (03H)
0000 1111 (0FH)
0001 r r r r (1xH)
0101 r r r r (5xH)
1111 0000 (F0H)
1111 0001 (F1H)
1111 0010 (F2H)
1111 0011 (F3H)
1111 0100 (F4H)
1111 1011 (FBH)
1111 1100 (FCH)
1111 1101 (FDH)
1111 1110 (FEH)
—
—
—
xxxx_nnnn (# of regs-1)
xxxx_nnnn (# of regs-1)
—
—
—
—
—
—
—
—
—
SLEEP
RESET
Put in SLEEP Mode
Reset to Power-Up Values
NOTE: The received data format is always MSB first; the data out format is set by the BIT ORDER bit in the ACR register.
TABLE IV. Command Summary.
RDATA–Read Data
RDATAC–Read Data Continuous
Description:Readthemostrecentconversionresultfromthe
Data Output Register (DOR). This is a 24-bit value.
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOPC
command or the RESET command. Wait at least 10 fOSC after
Operands: None
Bytes:
1
Encoding: 0000 0001
DRDY falls before reading.
Data Transfer Sequence:
Operands: None
Bytes:
1
0000 0001
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
xxxx xxxx
LSB
DIN
Encoding: 0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC or
DOUT
RESET.
NOTE: (1) For wait time, refer to timing specification.
DRDY
DIN
0000 0011
• • •(1)
uuuu uuuu
MSB
uuuu uuuu
Mid-Byte
uuuu uuuu
LSB
• • •
DOUT
DRDY
DOUT
• • •
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
ADS1242, 1243
18
SBAS235H
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STOPC–Stop Continuous
SELFCAL–Offset and Gain Self Calibration
Description: Ends the continuous data output mode. Issue
after DRDY goes LOW.
Description: Starts the process of self calibration. The Offset
Calibration Register (OCR) and the Full-Scale Register (FSR)
are updated with new values after this operation.
Operands: None
Bytes:
1
Operands: None
Encoding: 0000 1111
Bytes:
1
Data Transfer Sequence:
Encoding: 1111 0000
Data Transfer Sequence:
DRDY
1111 0000
DIN
xxx
0000 1111
DIN
SELFOCAL–Offset Self Calibration
RREG–Read from Registers
Description: Starts the process of self-calibration for offset.
The Offset Calibration Register (OCR) is updated after this
operation.
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte
count. If the count exceeds the remaining registers, the ad-
dresses wrap back to the beginning.
Operands: None
Bytes:
1
Operands: r, n
Encoding: 1111 0001
Bytes:
2
Data Transfer Sequence:
Encoding: 0001 rrrr xxxx nnnn
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
1111 0001
DIN
0001 0001
0000 0001
• • •(1)
xxxx xxxx
MUX
xxxx xxxx
ACR
DIN
SELFGCAL–Gain Self Calibration
Description: Starts the process of self-calibration for gain.
TheFull-ScaleRegister(FSR)isupdatedwithnewvaluesafter
this operation.
DOUT
NOTE: (1) For wait time, refer to timing specification.
Operands: None
Bytes:
1
WREG–Write to Registers
Encoding: 1111 0010
Description: Write to the registers starting with the register
address specified as part of the instruction. The number of
registers that will be written is one plus the value of the second
byte.
Data Transfer Sequence:
1111 0010
DIN
Operands: r, n
Bytes:
2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 04H (DIO)
DIN
0101 0100
xxxx 0001
Data for DIO
Data for DIR
ADS1242, 1243
19
SBAS235H
www.ti.com
DSYNC–Sync DRDY
SYSOCAL–System Offset Calibration
Description: Synchronizes the ADS1242 and ADS1243 to an
external event.
Description: Initiates a system offset calibration. The input
should be set to 0V, and the ADS1242 and ADS1243 compute
the OCR value that compensates for offset errors. The Offset
CalibrationRegister(OCR)isupdatedafterthisoperation. The
user must apply a zero input signal to the appropriate analog
inputs. The OCR register is automatically updated afterwards.
Operands: None
Bytes:
1
Encoding: 1111 1100
Data Transfer Sequence:
Operands: None
Bytes:
1
1111 1100
DIN
Encoding: 1111 0011
Data Transfer Sequence:
SLEEP–Sleep Mode
1111 0011
DIN
Description: Puts the ADS1242 and ADS1243 into a low
power sleep mode. To exit sleep mode, issue the WAKEUP
command.
SYSGCAL–System Gain Calibration
Operands: None
Description: Starts the system gain calibration process. For
a system gain calibration, the input should be set to the
reference voltage and the ADS1242 and ADS1243 compute
the FSR value that will compensate for gain errors. The FSR
is updated after this operation. To initiate a system gain
calibration, the user must apply a full-scale input signal to the
appropriate analog inputs. FCR register is updated automati-
cally.
Bytes:
1
Encoding: 1111 1101
Data Transfer Sequence:
1111 1101
DIN
Operands: None
RESET–Reset to Default Values
Bytes:
1
Description: Restore the registers to their power-up values.
This command stops the Read Continuous mode.
Encoding: 1111 0100
Data Transfer Sequence:
Operands: None
Bytes:
1
1111 0100
DIN
Encoding: 1111 1110
Data Transfer Sequence:
WAKEUP
1111 1110
DIN
Description:WakestheADS1242andADS1243fromSLEEP
mode.
Operands: None
Bytes:
1
Encoding: 1111 1011
Data Transfer Sequence:
1111 1011
DIN
ADS1242, 1243
20
SBAS235H
www.ti.com
load cell output can be directly applied to the differential
inputs of ADS1242.
APPLICATION EXAMPLES
GENERAL-PURPOSE WEIGHT SCALE
HIGH PRECISION WEIGHT SCALE
Figure 8 shows a typical schematic of a general-purpose
weight scale application using the ADS1242. In this ex-
ample, the internal PGA is set to either 64 or 128 (depending
on the maximum output voltage of the load cell) so that the
Figure 9 shows the typical schematic of a high-precision
weight scale application using the ADS1242. The front-end
differential amplifier helps maximize the dynamic range.
2.7V ~ 5.25V
EMI Filter
VDD
ADS1242
GND
VDD
VREF+
EMI Filter
AIN0
DRDY
SCLK
DOUT
DOUT
CS
Load Cell
MSP430x4xx
or other
Microprocessor
SPI
EMI Filter
AIN1
MCLK
GND
XIN
XOUT
VREF–
EMI Filter
FIGURE 8. Schematic of a General-Purpose Weight Scale.
2.7V ~ 5.25V
EMI Filter
2.7V ~ 5.25V
VDD
VDD
VREF+
EMI Filter
RI
OPA2335
AIN0
Load Cell
RF
DRDY
SCLK
DOUT
DIN
MSP430x4xx
or other
Microprocessor
ADS1242
ADS1243
CI
SPI
RG
RF
CS
RI
OPA2335
EMI Filter
EMI Filter
AIN1
MCLK
GND
XIN
XOUT
VREF–
GND
G = 1 + 2 • RF/RG
FIGURE 9. Block Diagram for a High-Precision Weight Scale.
ADS1242, 1243
21
SBAS235H
www.ti.com
fosc
fosc
DEFINITION OF TERMS
An attempt has been made to be consistent with the termi-
nology used in this data sheet. In that regard, the definition
of each term is given as follows:
fMOD
=
=
128 • 2SPEED
mfactor
PGA SETTING
SAMPLING FREQUENCY
fOSC
1, 2, 4, 8
f SAMP
f SAMP
f SAMP
=
=
=
Analog Input Voltage—the voltage at any one analog input
relative to GND.
mfactor
fOSC • 2
16
32
mfactor
Analog Input Differential Voltage—given by the following
equation: (IN+) – (IN–). Thus, a positive digital output is
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
fOSC • 4
mfactor
fOSC • 8
64, 128
f SAMP
=
mfactor
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the GND to VDD range.
fSAMP—the frequency, or switching speed, of the input sam-
pling capacitor. The value is given by one of the following
equations:
f
DATA—the frequency of the digital output data produced by
the ADS1242 and ADS1243, fDATA is also referred to as the
Data Rate.
Conversion Cycle—the term conversion cycle usually refers
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1242 and ADS1243 is defined as
the input, that produces the positive full-scale digital output
minus the input, that produces the negative full-scale digital
output.
Data Rate—The rate at which conversions are completed.
See definition for fDATA
.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (negative
full-scale)] = 2.5V.
fosc
fDATA
=
128 • 2SPEED • 1280 • 2DR
SPEED = 0,1
DR = 0,1, 2
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input has to change in order to observe a change in the
output data of one least significant bit. It is computed as
follows:
fOSC—the frequency of the crystal oscillator or CMOS com-
patible input signal at the XIN input of the ADS1242 and
ADS1243.
f
MOD—the frequency or speed at which the modulator of the
ADS1242 and ADS1243 is running. This depends on the
SPEED bit as given by the following equation:
Full − ScaleRange
LSB Weight =
2N – 1
SPEED = 0
SPEED = 1
where N is the number of bits in the digital output.
mfactor
128
256
tDATA—the inverse of fDATA, or the period between each data
output.
+5V SUPPLY ANALOG INPUT(1)
GENERAL EQUATIONS
DIFFERENTIAL
FULL-SCALE RANGE INPUT VOLTAGES(2)
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA SHIFT
RANGE
GAIN SETTING
1
2
5V
±2.5V
±1.25V
±0.625V
2.5V
±1.25V
4
1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
±9.766mV
RANGE = 0
8
0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
16
32
64
128
312.5mV
156.25mV
78.125mV
39.0625mV
VREF
PGA
±V
±V
REF
REF
2 • PGA
4 • PGA
RANGE = 1
NOTES: (1) With a +2.5V reference. (2) Refer to electrical specification for analog input voltage range.
TABLE VI. Full-Scale Range versus PGA Setting.
ADS1242, 1243
22
SBAS235H
www.ti.com
Revision History
DATE
REVISION PAGE
SECTION
DESCRIPTION
10/13
H
21
10
15
14
Application Examples
Overview
Changed Figure 9; switched plus and minus in upper op amp.
Changed 1st paragraph of Input Multiplexer subsection.
Deleted 1xxx from Mux Register definition.
2/07
G
Registers
12/06
F
Overview
Added DSYNC Operation subsection.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
ADS1242, 1243
23
SBAS235H
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
ADS1242IPWR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
16
16
16
16
20
20
20
20
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
ADS
1242
ADS1242IPWRG4
ADS1242IPWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
PW
PW
PW
PW
PW
PW
2500
250
Green (RoHS
& no Sb/Br)
ADS
1242
Green (RoHS
& no Sb/Br)
ADS
1242
ADS1242IPWTG4
ADS1243IPWR
250
Green (RoHS
& no Sb/Br)
ADS
1242
2500
2500
250
Green (RoHS
& no Sb/Br)
ADS1243
ADS1243
ADS1243
ADS1243
ADS1243IPWRG4
ADS1243IPWT
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ADS1243IPWTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1243 :
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1242IPWR
ADS1242IPWT
ADS1243IPWR
ADS1243IPWT
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
20
20
2500
250
330.0
180.0
330.0
180.0
12.4
12.4
16.4
16.4
6.9
6.9
5.6
5.6
7.1
7.1
1.6
1.6
1.6
1.6
8.0
8.0
8.0
8.0
12.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
2500
250
6.95
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1242IPWR
ADS1242IPWT
ADS1243IPWR
ADS1243IPWT
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
20
20
2500
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
38.0
35.0
2500
250
Pack Materials-Page 2
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Copyright © 2013, Texas Instruments Incorporated
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