ADS125H02IRHBR [TI]
具有 ±20V 输入、PGA、IDAC、GPIO 和基准电压的 24 位、40kSPS、2 通道 Δ-Σ ADC | RHB | 32 | -40 to 125;
| 型号： | ADS125H02IRHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ±20V 输入、PGA、IDAC、GPIO 和基准电压的 24 位、40kSPS、2 通道 Δ-Σ ADC | RHB | 32 | -40 to 125 |
| 文件： | 总90页 (文件大小：3429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
具有 PGA 和电压基准的 ADS125H02 ±20V 输入、双通道、40kSPS、24
位 Δ-Σ ADC
1 特性
3 说明
1
•
•
•
±20V 输入、24 位 Δ-Σ ADC
ADS125H02 是一款 ±20V 输入、24 位、Δ-Σ 模数转
换器 (ADC)。该 ADC 配备 低噪声可编程增益放大器
(PGA)、内部基准电压、时钟振荡器和信号或基准电压
超范围监控器。
可编程数据速率：2.5SPS 至 40000SPS
高压高阻抗 PGA：
–
–
–
–
差分输入范围：高达 ±20V
可编程增益：0.125 至 128
共模输入电压：高达 ±15.5V
输入阻抗：1GΩ（最小值）
与分立的解决方案相比，该产品将一个宽输入电压范
围、±18V PGA 和 ADC 集成到单个封装中，可将电路
板面积减小最多 50%。
•
•
•
高性能 ADC：
具有 0.125 至 128 的可编程增益（相当于 ±20V 至
±20mV 的等效输入范围），因而无需外部衰减器或外
部增益级。1GΩ 的最低输入阻抗可减小由传感器负载
导致的误差。而且，由于具备低噪声和低漂移性能，因
而能直接连接桥、电阻式温度检测器 (RTD) 和热电偶
传感器。
–
–
–
–
–
–
输入噪声：45nVRMS (20SPS)
CMRR：105dB
在 50Hz、60Hz 下的常规模式抑制：95dB
温漂：5nV/°C
增益漂移：1ppm/°C
积分非线性 (INL)：2ppm
数字滤波器可减弱数据速率 ≤ 50SPS 或 60SPS 时的
50Hz 和 60Hz 线路周期噪声，以减小测量误差。滤波
器还可提供无延迟转换数据，从而在通道定序期间实现
高数据吞吐量。
集成 特性 和诊断功能：
–
–
–
–
–
–
2.5V 基准：3ppm/°C 漂移
时钟振荡器：2.5% 误差（最大值）
激励电流源
GPIO 可驱动外部多路复用器
信号和基准电压监控器
循环冗余校验 (CRC)
ADS125H02 采用 5mm × 5mm VQFN 封装，额定工
作温度范围为 –40°C 至 +125°C。
器件信息(1)
电源：
器件型号
ADS125H02
封装
VQFN (32)
封装尺寸（标称值）
–
–
–
AVDD：4.75V 至 5.25V
5.00mm × 5.00mm
DVDD：2.7V 至 5.25V
HVDD：±5V 至 ±18V
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
工作温度：–40°C 至 +125°C
5mm × 5mm VQFN 封装
功能方框图
15 V
5 V (A)
REFP0 REFN0
REFOUT
5 V (D)
2 应用
2.5-V
Ref
ADS125H02
•
PLC 模拟输入模块：
REFP1/GPIO0
REFN1/GPIO1
GPIO2
GPIO
(5 V)
START
RESET
DRDY
Ref
MUX
–
–
–
电压（例如 ±10V 或 0V 至 5V）
电流（例如 4mA 至 20mA，具有分流器）
温度（例如 RTD、热电偶）
Control
GPIO3
IDAC1
IDAC2
5 V
BUF
Monitor
CS1
CS2
Serial
Interface
(CRC)
AIN0
AIN1
DIN
•
测试和测量：
24-Bit
ûꢀ ADC
Digital
Filter
Input
MUX
DOUT/DRDY
SCLK
AINCOM
PGA
Supply
Read
–
–
–
高共模电压输入
电池测试
Monitor
Temp
Sensor
Internal
Oscillator
Clock
Mux
CLKIN
高侧电流测量
-15 V
(A)
(D)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS790
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
目录
9.5 Programming........................................................... 45
9.6 Register Map........................................................... 53
10 Application and Implementation........................ 68
10.1 Application Information.......................................... 68
10.2 Typical Applications .............................................. 69
10.3 Initialization Setup................................................. 73
11 Power Supply Recommendations ..................... 74
11.1 Power-Supply Decoupling..................................... 74
11.2 Analog Power-Supply Clamp ................................ 74
11.3 Power-Supply Sequencing.................................... 74
11.4 5-V to ±15-V DC-DC Converter ............................ 74
12 Layout................................................................... 75
12.1 Layout Guidelines ................................................. 75
12.2 Layout Example .................................................... 76
13 器件和文档支持 ..................................................... 77
13.1 文档支持................................................................ 77
13.2 接收文档更新通知 ................................................. 77
13.3 社区资源................................................................ 77
13.4 商标....................................................................... 77
13.5 静电放电警告......................................................... 77
13.6 Glossary................................................................ 77
14 机械、封装和可订购信息....................................... 78
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements................................................ 9
7.7 Switching Characteristics........................................ 10
7.8 Typical Characteristics............................................ 12
Parameter Measurement Information ................ 20
8.1 Noise Performance ................................................. 20
Detailed Description ............................................ 24
9.1 Overview ................................................................. 24
9.2 Functional Block Diagram ....................................... 25
9.3 Feature Description................................................. 26
9.4 Device Functional Modes........................................ 39
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (April 2019) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
已删除 从文档中删除了 ADS125H01...................................................................................................................................... 1
Changed Device Comparison Table....................................................................................................................................... 3
Added Effective resolution parameter to Electrical Characteristics table............................................................................... 7
已添加 Offset Voltage Long-Term Drift curves to Typical Characteristics ........................................................................... 15
已添加 Gain Long-Term Drift curves to Typical Characteristics .......................................................................................... 16
已添加 Internal Reference Voltage Long-Term Drift curve to Typical Characteristics ......................................................... 17
已添加 Oscillator Frequency Long-Term Drift curve to Typical Characteristics ................................................................... 19
已更改 Noise Performance section....................................................................................................................................... 20
已添加 effective resolution and noise-free resolution data in Noise Performance .............................................................. 23
已更改 sinc1, sinc3, sinc4, and sinc5 values and footnote in Conversion Latency Time table............................................ 40
已更改 start-conversion delay value from 0 µs to 50 µs in the Start-Conversion Delay section.......................................... 40
已更改 sinc mode values in Calibration Time table.............................................................................................................. 44
已更改 address 00h default value from xxh to 6xh in Register Map Summary table........................................................... 53
已更改 reset value from xxh to 6xh in Device Identification (ID) Register............................................................................ 54
Changes from Revision A (January 2019) to Revision B
Page
•
已更改 将 ADS125H02 的状态从“预告信息”更改成了“生产数据”............................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
ADS125H02
www.ti.com.cn
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
5 Device Comparison Table
PART
NUMBER
SINGLE-ENDED, DIFFERENTIAL
CHANNELS
INTERNAL
REFERENCE
SENSOR CURRENT
SOURCES
TEMPERATURE
SENSOR
GPIOs
ADS125H01
ADS125H02
1, 1
2, 1
No
0
4
0
2
No
Yes
Yes
Copyright © 2018–2019, Texas Instruments Incorporated
3
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
6 Pin Configuration and Functions
RHB Package: ADS125H02
32-Pin VQFN
Top View
REFP0
CAPP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
IDAC1
IDAC2
NC
CAPN
AVDD
NC
Thermal
pad
AGND
HV_AVDD
HV_AVSS
CLKIN
DVDD
REFOUT
RESET
START
Not to scale
Pin Functions
NO.
NAME
REFP0
CAPP
I/O
Analog input
DESCRIPTION
1
Reference input 0 positive
2
Analog output PGA output P; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN
Analog output PGA output N; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN
3
CAPN
4
AVDD
Analog
Analog
Low-voltage analog power supply (5 V)
5
AGND
REFOUT
RESET
START
CS2
Analog ground; connect to the ADC ground plane
6
Analog output 2.5-V reference output; connect a 10-µF capacitor to AGND
7
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital output
Digital output
Reset; active low
8
Conversion start, active high
9
Serial interface chip select 2 to select the PGA for communication
Serial interface chip select 1 to select the ADC for communication
Serial interface shift clock
10
11
12
13
14
15
16
17
18
CS1
SCLK
DIN
Serial interface data input
DRDY
Data-ready indicator; active low
DOUT/DRDY
BYPASS
DGND
DVDD
Serial interface data output and data-ready indicator (active low)
Analog output 2-V subregulator output; connect a 1-µF capacitor to DGND
Digital
Digital
Digital ground; connect to the ADC ground plane
Digital power supply (3 V to 5 V)
CLKIN
Digital input
External clock input. Connect to DGND for internal oscillator operation.
4
Copyright © 2018–2019, Texas Instruments Incorporated
ADS125H02
www.ti.com.cn
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
Pin Functions (continued)
NO.
19
NAME
HV_AVSS
HV_AVDD
NC
I/O
Analog
Analog
—
DESCRIPTION
High-voltage negative analog power supply
High-voltage positive analog power supply
20
21, 22
23
No connection; electrically float or tie to AGND
IDAC2
IDAC1
AINCOM
AIN0
Analog output Current source 2 output
Analog output Current source 1 output
24
25
Analog input
Analog input
Analog input
Analog input common (single-ended common input)
26
Analog input 0
Analog input 1
27
AIN1
Digital
input/output
28
29
30
GPIO3
GPIO2
General-purpose input/output 3
Digital
input/output
General-purpose input/output 2
Analog, digital
input/output
REFN1/GPIO1
Reference input 1 negative and general-purpose input/output 1
Analog, digital
input/output
31
REFP1/GPIO0
REFN0
Reference input 1 positive and general-purpose input/output 0
Reference input 0 negative
32
Analog input
Exposed thermal pad; connect to DGND; see the recommended PCB land pattern at the
end of the document.
Thermal pad
—
7 Specifications
7.1 Absolute Maximum Ratings
(1)
see
MIN
–0.3
MAX
UNIT
HV_AVDD to HV_AVSS
HV_AVSS to AGND
38
–19
0.3
Power-supply voltage
Analog input voltage
AVDD to AGND
–0.3
6
V
DVDD to DGND
–0.3
6
0.1
AGND to DGND
–0.1
AIN0, AIN1, AINCOM
GPIO[3:0], REFP[1:0], REFN[1:0], IDAC[2:1]
HV_AVSS – 0.3
AGND – 0.3
HV_AVDD + 0.3
AVDD + 0.3
V
CS1, CS2, SCLK, DIN, START, RESET, CLKIN,
DRDY, DOUT/DRDY
Digital input voltage
Input current
DGND – 0.3
–10
DVDD + 0.3
V
(2)
Continuous
10
150
150
mA
Junction, TJ
Storage, Tstg
Temperature
°C
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input and output pins are diode-clamped to the internal power supplies. Limit the input current to 10 mA in the event the analog input
voltage exceeds HV_AVDD + 0.3 V or HV_AVSS – 0.3 V, or if the reference input, GPIO, or IDAC voltage exceeds AVDD + 0.3 V or
AGND – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or DGND – 0.3 V.
7.2 ESD Ratings
VALUE
±2000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2018–2019, Texas Instruments Incorporated
5
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
POWER SUPPLY
HV_AVDD to HV_AVSS
10
–18
5
36
High-voltage analog power supplies HV_AVSS to AGND
HV_AVDD to AGND(1)
0
36
V
Low-voltage analog power supply
Digital power supply
AVDD to AGND
DVDD to DGND
4.75
2.7
5
5.25
5.25
V
V
SIGNAL INPUTS
V(AINX) Absolute input voltage
See the PGA Operating Range section
V
V
VIN
Differential input voltage range(2)
VIN = VAINP – VAINN
–20
±VREF / Gain
20
VOLTAGE REFERENCE INPUTS
VREF
Reference voltage input
VREF = V(REFPx) – V(REFNx)
0.9
AGND – 0.05
V(REFNx) + 0.9
AVDD
V(REFPx) – 0.9
AVDD + 0.05
V
V
V
V(REFNx) Negative reference voltage
V(REFPx) Positive reference voltage
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)
Input voltage
AGND
DGND
AVDD
DVDD
V
V
DIGITAL INPUTS (Other Than GPIOs)
Input voltage
EXTERNAL CLOCK
Data rate < 40000 SPS
Data rate = 40000 SPS
1
1
7.3728
10.24
8
10.75
60%
f(CLK)
Frequency
Duty cycle
MHz
°C
40%
TEMPERATURE RANGE
TA Operating ambient temperature
(1) HV_AVDD can be connected to AVDD if AVDD ≥ 5 V.
–45
125
(2) The full differential input voltage range is limited under certain conditions. See the PGA Operating Range section for details.
7.4 Thermal Information
ADS125H02
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
35.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
19.0
15.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
15.7
RθJC(bot)
8.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2018–2019, Texas Instruments Incorporated
ADS125H02
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ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz,
data rate = 20 SPS, and gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Absolute input current
V(AINx) = 0 V, TA ≤ 105°C
–15
±0.5
20
15
nA
pA/°C
nA
Absolute input current drift
VIN = 2.5 V
VIN = 2.5 V, auto-zero mode(1)
±0.1
±2
Differential input current
nA/V
pA/°C
GΩ
Differential input current drift
Differential input impedance
Crosstalk
VIN = 2.5 V
10
1
20
0.1
µV/V
PGA
Gain
0.125, 0.1875, 0.25, 0.5, 1, 2, 4, 8, 16, 32, 64,128
230
V/V
kHz
Antialias filter frequency
PERFORMANCE
Resolution
No missing codes
24
Bits
Data rate
2.5
40000
SPS
en
Noise performance
Effective resolution
See 表 1 and 表 2
See 图 52 and 图 53
Gain = 0.125 to 32
Gain = 64, 128
2
4
10
12
INL
VOS
Integral nonlinearity
Offset voltage(2)
ppmFSR
µV
TA = 25°C
–30 – 300 / Gain ±10 + 100 / Gain 30 + 300 / Gain
TA = 25°C, auto-zero mode
Gain = 0.125 to 8
Gain = 16 to 128
Auto-zero mode
TA = 25°C, all gains
All gains
–0.5 – 0.5 / Gain
±0.5 / Gain 0.5 + 0.5 / Gain
150 / Gain
10
700 / Gain
50
Offset voltage drift
nV/°C
5 / Gain
±0.1%
1
GE
Gain error(2)
–0.7%
0.7%
4
Gain drift
Normal-mode rejection ratio(3)
ppm/°C
dB
NMRR
CMRR
See 表 7
Data rate = 20 SPS
Data rate = 400 SPS
HV_AVDD, HV_AVSS
AVDD
130
105
2
Common-mode rejection ratio(4)
90
20
60
30
PSRR
Power-supply rejection ratio(5)
20
5
µV/V
DVDD
VOLTAGE REFERENCE INPUTS
Absolute input current
±250
15
nA
nA/V
nA/°C
MΩ
Input current vs reference voltage
Input current drift
Input impedance
0.2
30
Differential
(1) Auto-zero mode input current is proportional to the data rate.
(2) Offset and gain errors are reduced to the level of noise by calibration.
(3) Normal-mode rejection ratio performance is dependent on the digital filter configuration.
(4) Common-mode rejection ratio is specified at 60 Hz.
(5) Power-supply rejection ratio is specified at dc.
Copyright © 2018–2019, Texas Instruments Incorporated
7
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz,
data rate = 20 SPS, and gain = 1 (unless otherwise noted)
PARAMETER
INTERNAL VOLTAGE REFERENCE(6)
Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.5
±0.1%
3
V
Initial error
TA = 25°C
–0.2%
0.2%
10
TA = 0°C to 85°C
Temperature drift
ppm/°C
ppm
TA = –40°C to 125°C
First 0°C to 105°C cycle
Second 0°C to 105°C cycle
7
20
70
Thermal hysteresis
25
Output current
Load regulation
–10
10
mA
µV/mA
ms
20
Start-up time
Settling to ±0.001% final value
TA = 25°C
100
TEMPERATURE SENSOR
Voltage
120
390
mV
Temperature coefficient
EXCITATION CURRENT SOURCES (IDACS)
Currents
µV/°C
50, 100, 250, 500, 750, 1000, 1500, 2000, 2500, 3000
µA
V
Compliance range
All currents
AGND
–6%
AVDD – 1.1
6%
Absolute error
All currents
±0.7%
±0.1%
±1%
100
Equal values
Unequal values
Absolute
–1.5%
1.5%
Relative error
Temperature drift
ppm/°C
Equal values, I ≤ 750 µA
5
25
PGA MONITORS(7)
Input and output low threshold
Input and output high threshold
REFERENCE MONITOR
Low voltage threshold
HV_AVSS + 2
HV_AVDD – 2
V
V
0.4
0.6
V
INTERNAL OSCILLATOR
Data rate < 40000 SPS
Data rate = 40000 SPS
–2.5%
–3.5%
±0.5%
±0.5%
2.5%
3.5%
Accuracy
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)
VOH
VOL
VIH
VIL
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
Input hysteresis
IOH = 1 mA
IOL = –1 mA
0.8 × AVDD
0.7 × AVDD
V
V
V
V
V
0.2 × AVDD
AVDD
0.3 × AVDD
0.5
(6) Voltage reference specifications apply after the device is soldered on the PCB using the recommended PCB layout pattern and using
the reflow profile per JEDEC standard J-STD-020D1.
(7) See the PGA Monitor section for details.
8
Copyright © 2018–2019, Texas Instruments Incorporated
ADS125H02
www.ti.com.cn
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz,
data rate = 20 SPS, and gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS (OTHER THAN GPIOs)
IOH = 1 mA
0.8 × DVDD
VOH
High-level output voltage
Low-level output voltage
V
V
IOH = 8 mA
IOL = –1 mA
IOL = –8 mA
0.75 × DVDD
0.2 × DVDD
0.2 × DVDD
VOL
VIH
VIL
High-level input voltage
Low-level input voltage
Input hysteresis
0.7 × DVDD
–10
DVDD
V
V
0.3 × DVDD
0.1
1.1
V
Input leakage
10
µA
POWER SUPPLY
IHV_AVDD
IHV_AVSS
HV_AVDD, HV_AVSS supply current
1.8
4.6
mA
mA
AVDD supply current
2.8
Voltage reference enabled
When data rate = 40000 SPS
Current sources enabled
Internal oscillator active
Data rate = 40000 SPS
0.2
IAVDD
mA
µA
Additional AVDD supply current
0.8
As programmed
0.5
0.7
49
0.7
1
IDVDD
PD
DVDD supply current
Power dissipation
mA
mW
79
7.6 Timing Requirements
over operating the ambient temperature range and DVDD = 2.7 V to 5.25 V (unless otherwise noted)
MIN
MAX
UNIT
SERIAL INTERFACE
td(CSSC)
tsu(DI)
th(DI)
Delay time, first SCLK rising edge after CS1 or CS2 falling edge
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
SCLK period
50
25
25
97
ns
ns
ns
ns
tc(SC)
tw(SCH),
tw(SCL)
Pulse duration, SCLK high or low
40
ns
td(SCCS)
tw(CSH)
RESET
tw(RSTL)
Delay time, last SCLK falling edge before CS1 or CS2 rising edge
Pulse duration, CS1 or CS2 high to reset interface
50
25
ns
ns
Pulse duration, RESET low
4
1 / fCLK
CONVERSION CONTROL
tw(STH) Pulse duration, START high
tw(STL)
4
4
1 / fCLK
1 / fCLK
Pulse duration, START low
Setup time, START low or STOP command before DRDY falling edge to stop
the next conversion (continuous mode)
tsu(STDR)
th(DRSP)
100
1 / fCLK
1 / fCLK
Hold time, START low or STOP command after DRDY falling edge to
continue the next conversion (continuous mode)
150
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7.7 Switching Characteristics
over operating the ambient temperature range and DVDD = 2.7 V to 5.25 V, and DOUT/DRDY load = 20 pF || 100 kΩ to
DGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
SERIAL INTERFACE
tw(DRH)
Pulse duration, DRDY high
16
0
1 / fCLK
ns
Propagation delay time, CS1 or CS2 falling edge to DOUT/DRDY
driven
tp(CSDO)
50
40
tp(SCDO1) Propagation delay time, SCLK rising edge to valid DOUT/DRDY
th(SCDO1) Hold time, SCLK rising edge to invalid DOUT/DRDY
ns
ns
0
Hold time, last SCLK falling edge to invalid DOUT/DRDY data
output function
th(SCDO2)
15
ns
ns
ns
Propagation delay time, last SCLK falling edge to DOUT/DRDY
data-ready function
tp(SCDO2)
110
50
Propagation delay time, CS1 or CS2 rising edge to DOUT/DRDY
high impedance
tp(CSDOZ)
RESET
Propagation delay time, RESET rising edge or RESET command
to conversion start
tp(RSCN)
512
512
1 / fCLK
Propagation delay time, power-on threshold voltage to ADC
communication
tp(PRCM)
216
1 / fCLK
1 / fCLK
tp(CMCN)
CONVERSION CONTROL
Propagation delay time, START pin high or START command to
Propagation delay time, ADC communication to conversion start
tp(STDR)
2
1 / fCLK
DRDY high
tw(CSH)
CS1
CS2
td(CSSC)
td(SCCS)
tc(SC)
tw(SCH)
SCLK
DIN
tw(SCL)
tsu(DI)
th(DI)
图 1. Serial Interface Timing Requirements
tw(DRH)
DRDY
CS1
CS2
SCLK
tp(SCDO2)
DOUT
tp(CSDO)
tp(SCDO1)
tp(CSDOZ)
(1)
DRDY
th(SCDO2)
DOUT
DOUT
DOUT
DOUT
DRDY
DOUT
DOUT/DRDY
th(SCDO1)
(1) DRDY is the data-ready function in the interval between CS1 low and the first SCLK rising edge, and in the interval
between the last SCLK falling edge of the command to CS1 high. DOUT is the data output function during the data
read operation.
图 2. Serial Interface Switching Characteristics
10
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tw(STH)
START
tw(STL)
Serial
Command
START
STOP
tsu(DRST)
STOP
tp(STDR)
DRDY
th(DRSP)
图 3. Conversion Control Timing Requirements
DVDD
1 V (typ)
1 V (typ)
VBYPASS
AVDD - AVSS
3.5 V (typ)
All supplies reach thresholds
DRDY
Begin ADC Communication
DOUT/DRDY
tp(PRCM)
tp(CMCN)
Conversion
Status
Start of 1st Conversion
图 4. Power-Up Characteristics
tw(RSTL)
RESET
Reset
Command
tp(RSCN)
Reset
Conversion
Status
Start
图 5. RESET Pin and Reset Command Timing Requirements
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7.8 Typical Characteristics
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
-1
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D042
D043
V(AINx) = 0 V
VIN = 2.5 V
图 6. Absolute Analog Input Current vs Temperature
图 7. Differential Analog Input Current vs Temperature
15000
300
12500
10000
7500
5000
2500
0
250
200
150
100
50
0
D019
Conversion Data (mV)
D018
Conversion Data (mV)
Gain = 0.1875, data rate = 1200 SPS, sinc1 filter, calibrated offset,
en = 13.6 µVRMS
Gain = 1, data rate = 40000 SPS, calibrated offset,
en = 37 µVRMS
图 8. Noise Histogram
图 9. Noise Histogram
3.5
3
150
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
125
100
75
50
25
0
2.5
2
1.5
1
0.5
0
-40
-20
0
20
40
60
80
100
120
D020
Temperature (èC)
D024
Conversion Data (mV)
Gain = 0.125 to 2, data rate = 20 SPS
Gain = 32, data rate = 20 SPS, FIR filter, calibrated offset,
en = 0.076 µVRMS
图 11. Noise vs Temperature
图 10. Noise Histogram
12
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Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
0
500
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
300
200
40000 SPS
7200 SPS
400 SPS
20 SPS
100
50
30
20
10
5
3
2
1
-40
-20
0
20
40
60
80
100
120
0.5
1
1.5
2
Reference Voltage (V)
2.5
3
3.5
4
4.5
5
Temperature (èC)
D025
D015
Gain = 4 to 128, data rate = 20 SPS
Gain = 0.125
图 12. Noise vs Temperature
图 13. Noise vs Reference Voltage
100
70
5
40000 SPS
7200 SPS
400 SPS
20 SPS
3
2
50
30
20
1
0.7
0.5
10
7
0.3
0.2
5
3
2
0.1
0.07
0.05
1
0.7
0.5
40000 SPS
7200 SPS
400 SPS
20 SPS
0.03
0.02
0.5
1
1.5
2
Reference Voltage (V)
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
Reference Voltage (V)
2.5
3
3.5
4
4.5
5
D016
D017
Gain = 1
Gain = 16
图 14. Noise vs Reference Voltage
图 15. Noise vs Reference Voltage
4
3
5
4
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-100 -80 -60 -40 -20
0
20
Input Signal (% of Range)
40
60
80 100
-100 -80 -60 -40 -20
0
20
Input Signal (% of Range)
40
60
80 100
D026
D027
图 16. Nonlinearity vs Input Signal
图 17. Nonlinearity vs Input Signal
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Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
24
22
20
18
16
14
12
10
8
10
Gain = 0.125
Gain = 1
Gain = 32
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
8
6
4
6
2
4
2
0
0
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Integral Non-Linearity (ppm
)
D023
D021
FSR
图 18. Integral Nonlinearity Distribution
图 19. Integral Nonlinearity vs Temperature
10
8
10
8
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
6
6
4
4
2
2
0
0
-40
-20
0
20
40
60
80
100
120
1
1.5
2
2.5
Reference Voltage (V)
3
3.5
4
4.5
5
Temperature (èC)
D022
D009
Input range limited to: ±4 V / Gain when VREF > 4 V
图 20. Integral Nonlinearity vs Temperature
图 21. Integral Nonlinearity vs Reference Voltage
15
8
7
6
5
4
3
2
1
0
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
12.5
10
7.5
5
2.5
0
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
Offset Drift (mV/èC)
D010
D035
Input range limited to: ±4 V / Gain when VREF > 4 V
图 22. Integral Nonlinearity vs Reference Voltage
Gain = 0.125
图 23. Offset Voltage Drift Distribution
14
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ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
8
7
6
5
4
3
2
1
0
10
8
6
4
2
0
D036
D037
Offset Drift (mV/èC)
Offset Drift (mV/èC)
Gain = 1
Gain = 32
图 24. Offset Voltage Drift Distribution
图 25. Offset Voltage Drift Distribution
40
35
30
25
20
15
10
5
30
20
Gain = 0.125
Gain = 1
Gain = 32
10
0
-10
-20
-30
0
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
Offset Drift (nV/èC)
D039
D052
Auto-zero mode
32 units, gain = 0.1875, after calibration
图 26. Offset Voltage Drift Distribution
图 27. Offset Voltage Long-Term Drift
1.5
1
10
8
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
6
4
0.5
0
2
0
-2
-4
-6
-8
-10
-0.5
-1
-1.5
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
D053
D013
32 units, gain = 32, after calibration
Gain = 0.125 to 2, after calibration
图 29. Offset Voltage vs Reference Voltage
图 28. Offset Voltage Long-Term Drift
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Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
8
7
6
5
4
3
2
1
0
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 0.125
Gain = 1
Gain = 32
-0.2
-0.4
-0.6
-0.8
-1
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
D040
D014
Gain Error (%)
Gain = 4 to 128, after calibration
图 30. Offset Voltage vs Reference Voltage
图 31. Gain Error Distribution
16
14
12
10
8
0.35
0.3
Gain = 0.125
Gain = 1
Gain = 32
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 2
0.25
0.2
6
4
0.15
2
0
0.1
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Gain Drift (ppm/èC)
D038
D028
Gain = 0.125 to 2
图 33. Gain Error vs Temperature
图 32. Gain Drift Distribution
0.35
0.3
30
20
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
10
0.25
0.2
0
-10
-20
-30
0.15
0.1
-40
-20
0
20
40
60
80
100
120
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
Temperature (èC)
D029
D050
Gain = 4 to 128
32 units, gain = 0.1875, after calibration
图 34. Gain Error vs Temperature
图 35. Gain Long-Term Drift
16
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Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
40
0.3
0.2
0.1
0
30
20
10
0
-10
-20
-30
-40
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
-0.1
-0.2
-0.3
Gain = 2
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
D051
D011
32 units, gain = 32, after calibration
Measurement input range limited to: ±4 V / Gain when VREF > 4 V
图 36. Gain Long-Term Drift
图 37. Gain Error vs Reference Voltage
0.3
0.2
0.1
0
12
10
8
6
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
-0.1
-0.2
-0.3
4
2
0
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
Reference Drift (ppm/èC)
D012
D034
Measurement input range limited to: ±4 V / Gain when VREF > 4 V
TA = –40°C to +125°C
图 38. Gain Error vs Reference Voltage
图 39. Internal Reference Voltage Drift Distribution
2.5
80
2.499
2.498
2.497
2.496
2.495
2.494
60
40
20
0
-20
-40
-20
0
20
40
60
80
100
120
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
Temperature (èC)
D006
D048
32 units, normalized data
图 40. Internal Reference Voltage vs Temperature
图 41. Internal Reference Voltage Long-Term Drift
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Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
350
300
250
200
150
100
50
140
130
120
110
100
90
IREFN, TA = -40èC
IREFN, TA = 25èC
IREFN, TA = 85èC
IREFN, TA = 125èC
IREFP, TA = -40èC
IREFP, TA = 25èC
IREFP, TA = 85èC
IREFP, TA = 125èC
Gain = 0.125, 20 SPS
Gain = 1, 20 SPS
Gain = 0.125, 1200 SPS
Gain = 1, 1200 SPS
REFP
80
0
REFN
-50
70
0.5
1
1.5
2
Differential Reference Voltage (V)
2.5
3
3.5
4
4.5
5
1
10
100
1000 10000
Frequency (Hz)
100000 1000000
D024
D030
图 42. Reference Input Current vs Reference Voltage
图 43. Common-Mode Rejection Ratio vs Frequency
10
260
9
8
7
6
5
4
3
2
1
0
250
240
230
220
210
200
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0
0.5
1
1.5
2
2.5
3
IDAC Voltage (V)
3.5
4
4.5
5
D041
Temperature Sensor Reading (èC)
D019
IDAC = 250 µA
TA = 25°C
图 45. IDAC Current vs IDAC Voltage
图 44. Temperature Sensor Reading Distribution
1
0.2
0.15
0.1
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0.5
0
0.05
0
-0.5
-1
-0.05
-0.1
-0.15
-0.2
-1.5
-40
-20
0
20
40
60
80
100
120
0
0.5
1
1.5
2
2.5
3
IDAC Voltage (V)
3.5
4
4.5
5
Temperature (èC)
D033
D023
IDAC = 250 µA
图 46. IDAC Match Error vs IDAC Voltage
图 47. Oscillator Frequency Error vs Temperature
18
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ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
Typical Characteristics (接下页)
at TA = 25°C, HV_AVDD = 15 V, HV_AVSS = –15 V, AVDD = 5 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, data rate
= 20 SPS, and gain = 1 (unless otherwise noted)
300
200
100
0
110
105
100
95
Gain = 0.125, 20 SPS
Gain = 1, 20 SPS
Gain = 0.125, 1200 SPS
Gain = 1, 1200 SPS
90
85
-100
-200
-300
80
75
70
65
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
1
10
100
1000 10000
Frequency (Hz)
100000 1000000
D049
D031
HV_AVDD and HV_AVSS
32 units, normalized data
图 49. PSRR vs Frequency
图 48. Oscillator Frequency Long-Term Drift
150
140
130
120
110
100
90
5
4
3
2
1
0
AVDD, Gain = 0.125, 20 SPS
AVDD, Gain = 1, 20 SPS
AVDD, Gain = 0.125, 1200 SPS
AVDD, Gain = 1, 1200 SPS
DVDD, Gain = 1, 20 SPS
IAVDD (20 SPS)
IAVDD (40000 SPS)
IHV_AVDD
IHV_AVSS
IDVDD
80
70
1
10
100
1000 10000
Frequency (Hz)
100000 1000000
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D032
D008
AVDD and DVDD
图 50. PSRR vs Frequency
All gains
图 51. Operating Current vs Temperature
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8 Parameter Measurement Information
8.1 Noise Performance
Noise performance depends on the device configuration: data rate, input gain, digital filter mode, and auto-zero
mode. Two significant factors affecting noise performance are data rate and input gain. Decreasing the data rate
lowers the noise because the bandwidth is reduced over the fixed noise profile of the ADC. Increasing the gain
reduces noise (when noise is treated as an input-referred quantity) because the noise of the PGA is lower than
that of the ADC. Noise performance also depends on the digital filter and auto-zero mode. As the digital filter
order increases, the bandwidth decreases, which results in lower noise. As a result of two-point data averaging in
auto-zero mode, noise performance improves by √2 compared to the normal operating mode.
表 1 lists the noise data of gain equal to 0.125 to 2 (corresponding input ranges of ±20 V to ±1.25 V) as input-
referred values. 表 2 lists the noise data of gain equal to 4 to 128 (corresponding input ranges of ±625 mV to
±19.5 mV). The noise data are in units of µVRMS (RMS = root mean square) under the conditions listed. Values in
parenthesis are peak-to-peak (µVpp).
The noise data represent typical ADC performance at TA = 25°C, 2.5-V reference voltage, and auto-zero mode
disabled. The noise data are the standard deviation and peak-to-peak computations of the ADC data. The data
are acquired with inputs shorted, based on consecutive ADC readings for a period of ten seconds or 8192 data
points, whichever occurs first. Because of the statistical nature of noise, repeated measurements may yield
higher or lower noise results. Similarly, longer periods of data acquisition may result in higher peak-to-peak noise
results.
表 1. Typical Noise (en) in µVRMS and (µVPP), Gain = 0.125 to 2, VREF = 2.5 V
DATA
RATE
(SPS)
GAIN (Full-Scale Range)
FILTER MODE
0.125 (±20 V)
0.1875 (±13.3 V)
0.25 (±10 V)
0.5 (±5 V)
1 (±2.5 V)
2 (±1.25 V)
2.5
2.5
2.5
2.5
2.5
5
FIR
1.3 (4.8)
1.1 (4.2)
0.89 (3.6)
0.6 (2.4)
0.68 (2)
0.67 (2)
0.64 (2)
1.2 (4.8)
0.98 (3.6)
0.91 (4)
0.83 (3.2)
0.75 (3.2)
1.6 (7.9)
1.4 (6.8)
1.2 (5.6)
1.1 (5.2)
0.99 (4.4)
1.7 (8.7)
1.5 (7.5)
1.4 (7.2)
1.3 (6.4)
2.1 (11)
1.9 (9.5)
1.5 (7.2)
1.6 (8.3)
1.3 (6.8)
2.9 (17)
2.3 (12)
2.2 (13)
0.69 (2.1)
0.57 (2.4)
0.44 (1.8)
0.49 (1.5)
0.48 (1.2)
0.93 (4.2)
0.77 (3.6)
0.68 (2.4)
0.62 (2.4)
0.54 (2.1)
1.2 (5.7)
1.1 (5.4)
0.9 (4.5)
0.89 (4.2)
0.79 (3.6)
1.4 (6.6)
1.1 (5.7)
1.1 (5.1)
0.97 (4.8)
1.8 (8.6)
1.5 (7.5)
1.3 (6)
0.49 (1.9)
0.39 (1.5)
0.32 (1)
0.37 (1.5)
0.29 (1)
0.17 (0.67)
0.15 (0.63)
0.12 (0.52)
0.11 (0.41)
0.11 (0.41)
0.24 (1.2)
0.2 (0.93)
0.18 (0.82)
0.16 (0.75)
0.14 (0.56)
0.34 (1.7)
0.3 (1.5)
Sinc1
Sinc2
Sinc3
Sinc4
FIR
1
(3.6)
0.26 (0.97)
0.24 (0.89)
0.26 (0.97)
0.45 (2)
1.1 (3)
0.98 (3.6)
1.7 (6.6)
1.5 (6.6)
1.3 (4.8)
1.2 (4.8)
1.2 (3.6)
2.4 (11)
1.9 (9.5)
1.7 (8.9)
1.5 (6.6)
1.5 (6.6)
2.6 (11)
2.1 (10)
1.9 (9.5)
1.8 (7.7)
0.32 (1)
0.3 (1)
0.57 (2.5)
0.53 (2.2)
0.44 (1.8)
0.39 (1.6)
0.38 (1.5)
0.82 (4.3)
0.7 (3.4)
0.56 (2.7)
0.54 (2.7)
0.49 (2.4)
0.87 (4.5)
0.78 (3.7)
0.72 (3.6)
0.65 (3.1)
1.1 (5.2)
0.97 (5.5)
0.83 (4.2)
0.77 (4)
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
0.4 (1.9)
5
0.35 (1.6)
0.3 (1.3)
5
5
0.27 (1.2)
0.69 (3.3)
0.55 (2.7)
0.47 (2.3)
0.46 (2.5)
0.39 (1.9)
0.72 (3.5)
0.62 (3.2)
0.54 (2.5)
0.48 (2.5)
0.89 (4.8)
0.76 (4.2)
0.69 (3.7)
0.64 (3.1)
0.56 (2.7)
1.2 (7.5)
10
10
10
10
10
16.6
16.6
16.6
16.6
20
20
20
20
20
50
50
50
50
60
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
0.24 (1.2)
0.24 (1.1)
0.2 (1)
0.37 (2)
0.32 (1.6)
0.27 (1.3)
0.24 (1.2)
0.46 (2.6)
0.43 (2.3)
0.35 (1.8)
0.31 (1.6)
0.28 (1.4)
0.64 (3.7)
0.54 (3.1)
0.49 (3)
3
(15)
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
2.7 (13)
2.2 (11)
2.1 (10)
1.2 (5.4)
1.1 (4.8)
2.3 (14)
2
(9.5)
0.65 (3.1)
1.5 (7.7)
1.3 (7)
4.1 (24)
3.2 (18)
3.3 (18)
3.1 (17)
4.5 (27)
1.9 (11)
1.1 (5.8)
1.8 (9.2)
1.6 (8.3)
2.4 (13)
1.2 (6.7)
0.93 (5.3)
0.87 (4.7)
1.4 (8.3)
2
(11)
1
(5.8)
0.43 (2.4)
0.69 (3.8)
3.1 (17)
1.6 (9.2)
20
版权 © 2018–2019, Texas Instruments Incorporated
ADS125H02
www.ti.com.cn
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
Noise Performance (接下页)
表 1. Typical Noise (en) in µVRMS and (µVPP), Gain = 0.125 to 2, VREF = 2.5 V (接下页)
DATA
RATE
(SPS)
GAIN (Full-Scale Range)
FILTER MODE
0.125 (±20 V)
0.1875 (±13.3 V)
0.25 (±10 V)
0.5 (±5 V)
1 (±2.5 V)
2 (±1.25 V)
60
60
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
Sinc5
Sinc5
Sinc5
3.8 (23)
3.4 (19)
3.3 (18)
5.6 (34)
4.9 (30)
4.4 (26)
4.1 (24)
12 (74)
9.3 (60)
8.6 (54)
2.6 (14)
2.3 (13)
2.1 (12)
4.1 (23)
3.4 (21)
3.1 (18)
2.9 (17)
8.1 (55)
6.7 (44)
6.2 (39)
5.6 (37)
14 (98)
2.1 (11)
1.8 (9.2)
1.9 (9.8)
3.3 (20)
2.7 (16)
2.5 (14)
2.3 (14)
6.4 (43)
5.3 (32)
4.9 (32)
4.5 (30)
11 (75)
1.4 (7.3)
1.3 (6.9)
1.2 (6.6)
2.1 (12)
1.8 (11)
1.7 (10)
1.5 (8.5)
4.3 (27)
3.5 (23)
3.2 (20)
1.2 (5.9)
0.57 (3.1)
0.54 (3.1)
0.52 (2.8)
0.91 (5.7)
0.75 (4.4)
0.69 (4.2)
0.63 (4)
1.8 (11)
1.5 (10)
1.4 (9.1)
1.3 (8.3)
3.1 (20)
2.6 (18)
2.4 (16)
2.2 (15)
4.2 (30)
3.6 (26)
3.3 (23)
3.1 (22)
5.6 (42)
1
(5.4)
60
0.95 (5.2)
1.8 (9.7)
1.5 (8.7)
1.3 (8.2)
1.3 (7.7)
3.6 (25)
2.9 (19)
2.7 (17)
2.5 (16)
100
100
100
100
400
400
400
400
8
(52)
3 (20)
1200
1200
1200
1200
2400
2400
2400
2400
4800
4800
4800
4800
7200
7200
7200
7200
14400
19200
25600
40000
20 (140)
17 (110)
15 (100)
14 (95)
7.3 (48)
6.1 (41)
5.6 (37)
5.2 (37)
10 (72)
8.7 (62)
7.9 (59)
7.3 (53)
14 (110)
12 (88)
11 (83)
11 (81)
16 (120)
14 (100)
13 (100)
13 (95)
18 (140)
23 (180)
42 (350)
65 (530)
6
5
(40)
(33)
12 (78)
9.2 (62)
8.4 (56)
7.8 (51)
15 (110)
13 (97)
11 (72)
4.6 (31)
4.3 (29)
8.3 (60)
9.9 (68)
19 (140)
16 (120)
15 (110)
14 (100)
26 (200)
23 (170)
21 (150)
20 (150)
31 (230)
28 (210)
26 (200)
25 (180)
36 (290)
50 (390)
100 (870)
160 (1300)
27 (200)
23 (180)
21 (160)
20 (140)
37 (270)
33 (250)
31 (230)
29 (220)
44 (330)
39 (300)
37 (280)
35 (260)
53 (430)
72 (560)
150 (1300)
250 (2000)
7
(53)
6.5 (50)
(43)
12 (94)
11 (78)
6
21 (160)
18 (140)
17 (130)
16 (120)
24 (180)
22 (170)
21 (160)
20 (150)
29 (220)
39 (320)
79 (640)
120 (1000)
11 (83)
9.8 (73)
5
(40)
9
(65)
4.7 (36)
4.4 (33)
6.5 (48)
5.9 (46)
5.5 (41)
5.3 (41)
7.4 (58)
8.8 (71)
13 (110)
19 (150)
8.5 (63)
13 (98)
12 (90)
11 (82)
10 (81)
14 (120)
17 (130)
26 (220)
37 (310)
表 2. Typical Noise (en) in µVRMS and (µVPP), Gain = 4 to 128, VREF = 2.5 V
DATA
RATE
(SPS)
GAIN (Full-Scale Range)
FILTER MODE
4 (±625 mV)
8 (±312 mV)
16 (±156 mV)
32 (±78.1 mV)
64 (±39.1 mV)
128 (±19.5 mV)
2.5
2.5
2.5
2.5
2.5
5
FIR
0.082 (0.35)
0.088 (0.35)
0.059 (0.24)
0.06 (0.24)
0.054 (0.19)
0.12 (0.52)
0.11 (0.48)
0.093 (0.43)
0.081 (0.41)
0.066 (0.3)
0.19 (1)
0.051 (0.2)
0.05 (0.19)
0.037 (0.14)
0.034 (0.13)
0.034 (0.13)
0.071 (0.33)
0.061 (0.28)
0.048 (0.21)
0.044 (0.2)
0.043 (0.2)
0.099 (0.51)
0.086 (0.46)
0.068 (0.36)
0.032 (0.14)
0.024 (0.089)
0.021 (0.084)
0.019 (0.075)
0.019 (0.075)
0.046 (0.21)
0.038 (0.18)
0.029 (0.14)
0.03 (0.13)
0.027 (0.11)
0.024 (0.089)
0.018 (0.072)
0.017 (0.07)
0.016 (0.065)
0.038 (0.19)
0.029 (0.14)
0.024 (0.11)
0.023 (0.1)
0.027 (0.1)
0.029 (0.12)
0.024 (0.1)
Sinc1
Sinc2
Sinc3
Sinc4
FIR
0.023 (0.098)
0.017 (0.076)
0.016 (0.073)
0.015 (0.062)
0.039 (0.17)
0.029 (0.15)
0.026 (0.12)
0.022 (0.1)
0.019 (0.076)
0.018 (0.075)
0.016 (0.069)
0.037 (0.18)
0.029 (0.13)
0.023 (0.1)
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
5
5
0.022 (0.11)
0.021 (0.096)
0.054 (0.3)
5
0.027 (0.13)
0.064 (0.36)
0.054 (0.3)
0.022 (0.093)
0.053 (0.29)
0.045 (0.22)
0.037 (0.2)
0.022 (0.11)
0.051 (0.3)
10
10
10
Sinc1
Sinc2
0.16 (0.82)
0.12 (0.56)
0.043 (0.21)
0.034 (0.18)
0.044 (0.23)
0.033 (0.18)
0.044 (0.23)
版权 © 2018–2019, Texas Instruments Incorporated
21
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
128 (±19.5 mV)
表 2. Typical Noise (en) in µVRMS and (µVPP), Gain = 4 to 128, VREF = 2.5 V (接下页)
DATA
RATE
(SPS)
GAIN (Full-Scale Range)
FILTER MODE
4 (±625 mV)
8 (±312 mV)
16 (±156 mV)
32 (±78.1 mV)
64 (±39.1 mV)
10
10
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
0.11 (0.52)
0.096 (0.45)
0.19 (1)
0.066 (0.31)
0.059 (0.31)
0.11 (0.56)
0.086 (0.4)
0.084 (0.41)
0.076 (0.39)
0.14 (0.72)
0.12 (0.58)
0.1 (0.57)
0.089 (0.48)
0.083 (0.41)
0.19 (1.1)
0.15 (0.84)
0.14 (0.75)
0.13 (0.76)
0.21 (1.2)
0.17 (0.93)
0.15 (0.79)
0.14 (0.89)
0.27 (1.5)
0.22 (1.4)
0.2 (1.2)
0.042 (0.21)
0.039 (0.2)
0.075 (0.38)
0.054 (0.27)
0.053 (0.27)
0.053 (0.29)
0.088 (0.45)
0.079 (0.41)
0.062 (0.34)
0.063 (0.32)
0.056 (0.29)
0.12 (0.69)
0.099 (0.56)
0.093 (0.51)
0.087 (0.47)
0.14 (0.79)
0.11 (0.66)
0.097 (0.53)
0.092 (0.5)
0.17 (1)
0.032 (0.17)
0.032 (0.17)
0.054 (0.3)
0.044 (0.22)
0.041 (0.22)
0.042 (0.24)
0.072 (0.38)
0.064 (0.32)
0.049 (0.25)
0.046 (0.22)
0.045 (0.23)
0.097 (0.52)
0.075 (0.43)
0.074 (0.41)
0.066 (0.37)
0.11 (0.57)
0.085 (0.47)
0.078 (0.43)
0.075 (0.46)
0.14 (0.81)
0.11 (0.63)
0.1 (0.63)
0.094 (0.57)
0.27 (1.8)
0.22 (1.4)
0.2 (1.3)
0.032 (0.16)
0.031 (0.16)
0.055 (0.29)
0.049 (0.24)
0.04 (0.22)
0.04 (0.21)
0.071 (0.37)
0.061 (0.32)
0.049 (0.26)
0.045 (0.21)
0.042 (0.22)
0.096 (0.57)
0.077 (0.43)
0.07 (0.38)
0.065 (0.35)
0.1 (0.59)
0.084 (0.49)
0.078 (0.43)
0.076 (0.4)
0.14 (0.88)
0.11 (0.69)
0.1 (0.61)
0.092 (0.56)
0.27 (1.7)
0.22 (1.4)
0.2 (1.3)
0.032 (0.16)
0.03 (0.15)
0.056 (0.31)
0.046 (0.24)
0.041 (0.2)
0.036 (0.17)
0.074 (0.37)
0.06 (0.34)
0.047 (0.29)
0.045 (0.23)
0.046 (0.24)
0.098 (0.58)
0.076 (0.46)
0.071 (0.37)
0.065 (0.37)
0.1 (0.6)
16.6
16.6
16.6
16.6
20
0.16 (0.89)
0.15 (0.73)
0.13 (0.67)
0.24 (1.2)
0.22 (1.1)
0.18 (1)
20
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
Sinc5
Sinc5
Sinc5
20
20
0.16 (0.89)
0.15 (0.82)
0.35 (2.1)
0.28 (1.6)
0.25 (1.5)
0.23 (1.4)
0.38 (2.2)
0.3 (1.7)
0.27 (1.6)
0.27 (1.6)
0.49 (2.8)
0.39 (2.3)
0.35 (2.1)
0.32 (2)
20
50
50
50
50
60
60
0.083 (0.49)
0.076 (0.42)
0.073 (0.4)
0.13 (0.81)
0.11 (0.66)
0.1 (0.69)
0.093 (0.57)
0.27 (1.8)
0.22 (1.4)
0.2 (1.3)
60
60
100
100
100
100
400
400
400
400
1200
1200
1200
1200
2400
2400
2400
2400
4800
4800
4800
4800
7200
7200
7200
7200
14400
19200
25600
40000
0.14 (0.87)
0.13 (0.75)
0.13 (0.73)
0.34 (2.1)
0.29 (1.8)
0.26 (1.6)
0.24 (1.6)
0.59 (4.1)
0.49 (3.2)
0.45 (3.1)
0.41 (2.7)
0.81 (5.8)
0.68 (5)
0.18 (1.2)
0.53 (3.5)
0.44 (3.1)
0.4 (2.6)
0.94 (6)
0.78 (5.2)
0.72 (4.6)
0.67 (4.2)
1.6 (12)
0.37 (2.4)
0.91 (6.3)
0.76 (5.2)
0.69 (4.7)
0.64 (4.3)
1.2 (8.9)
0.19 (1.2)
0.46 (3.1)
0.39 (2.6)
0.35 (2.4)
0.33 (2.3)
0.64 (4.5)
0.54 (3.9)
0.49 (3.5)
0.46 (3.5)
0.83 (6.2)
0.75 (5.6)
0.69 (5)
0.19 (1.2)
0.45 (3.1)
0.38 (2.6)
0.35 (2.4)
0.32 (2.2)
0.62 (4.5)
0.54 (3.9)
0.48 (3.4)
0.46 (3.4)
0.83 (6.2)
0.74 (5.4)
0.68 (5.2)
0.65 (4.9)
0.94 (6.9)
0.86 (6.5)
0.82 (6.2)
0.78 (6)
0.19 (1.1)
0.45 (3.1)
0.38 (2.6)
0.35 (2.2)
0.32 (2.3)
0.62 (4.6)
0.54 (4)
1.3 (9.3)
1.2 (8.2)
1.2 (7.6)
2.2 (17)
1.9 (14)
1.1 (7.7)
1.7 (14)
0.97 (7.1)
0.91 (6.7)
1.6 (13)
0.62 (4.4)
0.59 (4.1)
1.1 (7.8)
0.49 (3.5)
0.46 (3.4)
0.82 (6.1)
0.73 (5.5)
0.69 (5.5)
0.64 (4.9)
0.94 (7.1)
0.86 (6.4)
0.82 (6.4)
0.78 (5.8)
1.6 (12)
3
(23)
2.6 (20)
2.4 (19)
2.3 (17)
3.3 (25)
3.1 (24)
2.9 (22)
2.8 (21)
3.8 (29)
4.6 (36)
6.7 (56)
9.6 (80)
1.5 (12)
0.95 (7.2)
0.89 (6.4)
0.82 (6.2)
1.2 (9)
1.4 (10)
1.3 (9.8)
0.64 (5)
1.9 (15)
0.95 (7)
1.7 (13)
1.1 (8.7)
0.87 (6.6)
0.83 (6.1)
0.79 (5.8)
1.1 (8.4)
1.6 (12)
1.1 (7.9)
1.6 (12)
1 (7.7)
2.1 (17)
1.4 (11)
1.6 (13)
2.1 (17)
2.9 (23)
1.1 (8.1)
1 (8.4)
2.5 (20)
1.2 (9.6)
1.2 (9.3)
1.2 (9.5)
1.4 (12)
1.8 (15)
3.6 (29)
1.5 (13)
1.4 (12)
5
(43)
2
(16)
1.8 (15)
22
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ADC noise performance can also be expressed as effective resolution and noise-free resolution (bits). The
resolution in bits are computed from the measured noise data. Effective resolution is computed from the RMS
value of the measured noise data. Noise-free resolution is computed from the peak-to-peak value of the
measured noise data, and is therefore the resolution with no code flicker. 公式 1 is used to compute effective
resolution (bits) and noise-free resolution (bits) based on the noise values listed in 表 1 and 表 2.
Effective Resolution or Noise-Free Resolution (Bits) = 3.32 log (FSR / en)
where:
•
•
FSR = Full-scale range = 2 VREF / Gain
en = Input-referred noise (RMS value for effective resolution, peak-to-peak value for noise-free resolution) (1)
For example, with a full-scale range = ±13.3 V, data rate = 20 SPS, and filter mode = FIR, the RMS noise value
(from 表 1) is 2.1 µV. The effective resolution is: 3.32 log (26.6 V / 2.1 µV) = 23.6 bits.
图 52 and 图 53 show effective resolution (bits) using 公式 1. 图 54 and 图 55 show the noise-free resolution
(bits) using 公式 1. The data are based on 2.5-V reference operation and the sinc3 filter mode. Effective
resolution and noise-free resolution (bits) are improved by increasing the reference voltage (up to 5 V).
24
23
22
21
20
19
18
17
16
24
22
20
18
16
14
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 2
1
10
100 1000
Data Rate (SPS)
10000 50000
1
10
100 1000
Data Rate (SPS)
10000 50000
D044
D045
VREF = 2.5 V, sinc3 filter mode
VREF = 2.5 V, sinc3 filter mode
图 52. Effective Resolution, Gain = 0.125 to 2
图 53. Effective Resolution, Gain = 4 to 128
24
22
20
18
16
14
12
24
22
20
18
16
14
12
10
Gain = 0.125
Gain = 0.1875
Gain = 0.25
Gain = 0.5
Gain = 1
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 2
1
10
100 1000
Data Rate (SPS)
10000 50000
1
10
100 1000
Data Rate (SPS)
10000 50000
D046
D047
VREF = 2.5 V, sinc3 filter mode
图 54. Noise-Free Resolution, Gain = 0.125 to 2
VREF = 2.5 V, sinc3 filter mode
图 55. Noise-Free Resolution, Gain = 4 to 128
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9 Detailed Description
9.1 Overview
The ADS125H02 is a ±20-V signal input, 24-bit, 40-kSPS, delta-sigma (ΔΣ) analog-to-digital converter. The
device features gain from 0.125 to 128 that program the input voltage range from ±20 V to ±20 mV (VREF
=
2.5 V). The inputs are configurable as one differential input or two single-ended inputs. The device includes a
low-noise, low-drift PGA with high input impedance, signal monitors to detect overload conditions, and a voltage
reference. A temperature sensor is provided to monitor the surrounding temperature.
The ADC provides a compact one-chip measurement solution for a wide range of input voltages, including typical
current and voltage inputs to industrial programmable logic controllers (PLCs), such as ±10-V and 4-mA to 20-
mA transmitters (using an external shunt resistor). The ADC provides the resolution necessary to interface
directly to low-level sensors such as strain-gauge sensors, thermocouples, and resistance temperature detectors
(RTDs). Four general-purpose, input/output (GPIO) pins expand the number of measurement channels with the
use of an external multiplexer. Two current sources (IDAC1 and IDAC2) are provided for RTD biasing.
In summary, the ADC features:
•
•
•
•
•
•
•
•
•
•
12 selectable gains for input ranges from ±20 mV to ±20 V (differential)
1-GΩ input impedance PGA
2.5-V voltage reference
Internal or external reference operation
Internal or external clock operation
PGA, voltage reference, and power-supply monitors
Temperature sensor
SPI-compatible serial interface with CRC error check
Two IDACs
Four GPIOs
Analog inputs (AIN0, AIN1, AINCOM) connect to the input multiplexer (MUX) to select the ADC input channel.
The ADC supports one differential or two single-ended input measurement configurations.
The programmable gain amplifier (PGA) follows the input multiplexer. The PGA is a high input impedance,
complementary metal oxide semiconductor (CMOS), differential-input and differential-output amplifier. The PGA
has gain and attenuation modes to match the signal amplitude requirements. In attenuation mode, the PGA
reduces the input voltage to the range of the ADC. In gain mode, the input voltage is amplified to the range of the
ADC. The PGA output connects to the CAPP and CAPN pins. The ADC antialias filter is provided by the
combination of the internal PGA output resistors and the external capacitor connected to these pins.
The input channel multiplexer and the PGA are powered by the high-voltage power-supply pins (HV_AVDD and
HV_AVSS).
The operating state of the PGA are monitored for signal out-of-range conditions. Status bits in the status register
indicate the possible PGA out-of-range conditions.
The ΔΣ modulator measures the input voltage relative to the reference voltage to produce a 24-bit conversion
result. The input range of the ADC is ±VREF / Gain, where gain is programable in binary steps from 0.125 to 128.
The ADC reference voltage is either internal (2.5 V) or external. The REFOUT pin is the internal reference
voltage output (with respect to the AGND pin). The reference is monitored for out-of-range conditions and the
status is reflected in the conversion data STATUS byte. The device provides two pairs of voltage reference input
pins (REFP0, REFN0 and REFP1, REFN1).
The digital filter both averages and reduces the data rate of the modulator output to provide the output
conversion result. The sinc filter mode of the digital filter provides programmable orders (sinc1 through sinc5)
that allow optimization of conversion latency, conversion noise, and line-cycle rejection. The finite impulse
response (FIR) filter mode provides no-latency conversion data with simultaneous rejection of 50-Hz and 60-Hz
interference for data rates of 20 SPS or less.
User-programmable offset and gain calibration registers correct the conversion data to provide the final
conversion result.
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Overview (接下页)
The SPI-compatible serial interface is used to read the conversion data and for ADC configuration and control.
Integrity of SPI I/O communication is validated by CRC error checking. The serial interface consists of the
following signals: CS1, CS2, SCLK, DIN, and DOUT/DRDY (see the Chip-Select Pins (CS1 and CS2) section for
details). The dual-function DOUT/DRDY pin combines the functions of the serial data output and data-ready
indication into one pin. DRDY is the data-ready output signal.
The device includes two current sources (IDAC1, IDAC2). The IDACs are powered by the 5-V AVDD power
supply. The IDACs provide excitation current to RTDs or other sensors that require constant-current excitation.
The device provides four GPIO pins to control an external signal multiplexer and for general-purpose I/O of 0-V
to 5-V logic signals.
The ADC has an internal temperature sensor to monitor the surrounding temperature. The high-voltage power
supply is available for readback by the ADC for user diagnostics.
Clock operation is either controlled by the internal oscillator or by an external clock source. The external clock is
automatically detected by the ADC. The nominal clock frequency is 7.3728 MHz (10.24 MHz for data rates equal
to 40 kSPS).
ADC conversions are controlled by the START pin or by the START command. Conversions are programmable
for either continuous mode (gated by START) or one-shot (pulse) conversions.
The ADC auto-resets at power-on, or is manually reset by the RESET input or by the RESET command.
The HV_AVDD and HV_AVSS power supplies allow either bipolar or unipolar configuration (bipolar: ±5 V to
±18 V, unipolar: 10 V to 36 V). The digital I/Os are powered by DVDD (3-V to 5-V range). An internal 2-V
subregulator powers the ADC digital core for the DVDD supply. An external bypass capacitor is required at the
subregulator output (BYPASS pin).
9.2 Functional Block Diagram
HV_AVDD
REFP0/N0
REFOUT
AVDD
BYPASS
2.5-V
Ref
2-V
Digital Core
DVDD
LDO
REFP1/GPIO0
REFN1/GPIO1
GPIO2
GPIO
Ref
MUX
START
GPIO3
Control
RESET
DRDY
IDAC1
IDAC2
AVDD
Ref
Monitor
BUF
AIN0
AIN1
CS1
Serial
CS2
Interface
and
CRC
Input
MUX
AINCOM
24-Bit
ûꢀ ADC
Digital
Filter
DIN
PGA
Calibration
Supply
Monitor
DOUT/DRDY
Verification
SCLK
Signal
Monitors
PGA
Nodes
Temp
Sensor
Internal
Oscillator
Clock
Mux
CLKIN
DGND
CAPP/N
HV_AVSS
AGND
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9.3 Feature Description
9.3.1 Input Range
The input range of the ADC (as defined by 公式 2) is determined by the reference voltage and by the PGA gain.
表 3 lists the input range verses gain when operating with a 2.5-V reference voltage. The input range scales with
the reference voltage. The maximum input differential signal that can be applied is restricted under certain
conditions because of the operating voltage headroom required by the PGA. See the PGA Operating Range
section for details.
Input Range = ± VREF / Gain
(2)
表 3. ADC Input Range(1)
INPUT RANGE
DIFFERENTIAL SINGLE-ENDED
±20 V
GAIN[2:0] BITS
GAIN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
0.125
0.1875
0.25
0.5
1
0 V to ±15.5 V
0 V to ±13.3 V
0 V to ±10 V
±13.3 V
±10 V
±5 V
0 V to ±5 V
±2.5 V
0 V to ±2.5 V
2
±1.25 V
±0.625 V
±0.312 V
±0.156 V
±0.0781 V
±0.0391 V
±0.0195 V
0 V to ±1.25 V
0 V to ±0.625 V
0 V to ±0.312 V
0 V to ±0.156 V
0 V to ±0.0781 V
0 V to ±0.0391 V
0 V to ±0.0195 V
4
8
16
32
64
128
(1) Reference voltage = 2.5 V and HV power supply = ±18 V.
9.3.2 Analog Inputs
As shown in 图 56, the analog inputs of the ADC consist of electrostatic discharge (ESD) protection diodes and
an input multiplexer.
Positive Multiplexer
AIN0
AIN1
ESD Diodes
AINCOM
HV_AVDD
HV_AVDD
VCOM
AINP
Temp Sensor P
AIN0
AIN1
AINCOM
PGA
Negative Multiplexer
ADC
AIN0
AIN1
HV_AVSS
AINCOM
AINN
HV_AVSS
VCOM
Temp Sensor N
图 56. Analog Input Diagram
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9.3.2.1 ESD Diodes
ESD diodes are incorporated to protect the ADC inputs from possible ESD events occurring during the
manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-
controlled environment. For system-level ESD protection, consider the use of external ESD protection devices for
pins that are exposed to possible ESD, including the analog inputs.
If an analog input is driven below HV_AVSS – 0.3 V, or above HV_AVDD + 0.3 V, the internal ESD protection
diodes can conduct. If this condition is possible, current can flow through the inputs and flow out from the
HV_AVDD or HV_AVSS pins. Use external clamp diodes, series resistors, or both to limit the input current to the
specified value (see the PGA Operating Range section for details).
9.3.2.2 Input Multiplexer
The input multiplexer selects the signal for measurement. The multiplexer is programmed by the MUX[2:0] bits of
the MODE4 register (address = 10h). 表 4 lists the input multiplexer settings used to select the signal for
measurement.
表 4. Input Multiplexer Settings
MUX[2:0] BITS OF REGISTER MODE4 (10h)
MEASUREMENT (P to N)
AIN1 to AIN0
000
001
010
011
100
101
110
111
AIN0 to AIN1
AIN1 to AINCOM
AIN0 to AINCOM
HV supply: (HV_AVDD – HV_AVSS) / 36
VCOM voltage: (HV_AVDD + HV_AVSS) / 2 (default)
Temperature sensor
Reserved
9.3.2.2.1 Analog Inputs (AIN0, AIN1, AINCOM)
The ADC allows one differential input (AIN0 to AIN1, and a reverse polarity connection from AIN1 to AIN0) and
two single-ended inputs (AIN0 to AINCOM and AIN1 to AINCOM).
9.3.2.2.2 High-Voltage Power Supply Readback
Read the high-voltage power supply by selecting the voltage with the input multiplexer. The supply voltage is
divided by 36 for measurement in order to reduce the voltage to within the PGA input range. 公式 3 shows the
supply voltage scaling.
High-Voltage Power Supply (V) = (HV_AVDD – HV_AVSS) / 36
(3)
Measure the high-voltage power supply using the internal or external reference. To measure, set the PGA gain to
1 and disable the auto-zero mode. Write 100b to the MUX[2:0] control bits and then start a new conversion.
9.3.2.2.3 Internal VCOM Connection (Default)
In this multiplexer configuration, the external inputs are disconnected and the PGA inputs are shorted to an
internal voltage given by: VCOM = (HV_AVDD + HV_AVSS) / 2. Use this mode to measure the ADC noise
performance and offset voltage, or to short the inputs to perform offset calibration. Be aware that shorting the
external inputs during calibration yields the best results. Write 101b to the MUX[2:0] control register and start a
new conversion to obtain the internal shorted-input reading.
9.3.2.2.4 Temperature Sensor
The ADC has a temperature sensor comprised of two internal diodes with one diode having 80 times the current
density of the other. The difference in current density of the diodes yields a differential output voltage that is
proportional to absolute temperature. To measure the temperature sensor, write 110b to the MUX[2:0] control
bits to select the multiplexer for the temperature sensor and then start a new ADC conversion. 公式 4 shows how
to convert the temperature sensor reading to degrees Celsius (°C):
Temperature (°C) = [(Temperature Reading (µV) – 120,000) / 390 µV/°C] + 25°C
(4)
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When measuring the temperature sensor, set the gain to 1 and disable auto-zero mode. As a result of the low
package-to-PCB thermal resistance, the internal temperature closely tracks the PCB temperature. Be aware that
device self-heating increases the internal temperature relative to the surrounding PCB.
9.3.3 Programmable Gain Amplifier (PGA)
The PGA is a low-noise, programmable gain and attenuation, CMOS differential-input, differential-output
amplifier. The PGA operates in gain or attenuation mode depending on the gain selected. Typically, the PGA is
programmed to provide gain when the expected range of the input signal is less than the reference voltage and
is programmed to provide attenuation when the expected range of the input signal is greater than the reference
voltage.
图 57 shows the block diagram of the PGA.
HV_AVDD
AVDD
PGA Monitor
PGA Monitor
AINP
+
375 ꢀ
œ
A3
A1
œ
CAPP
+
GAIN[3:0] bits 3:0 of MODE4
(register address = 10h)
1 nF
C0G
ADC
AVDD / 2
0110: 4
0111: 8
1000: 16
1001: 32
1010: 64
1011: 128
0000: 0.125
0001: 0.1875
0010: 0.25
0011: 0.5
0100: 1
375 ꢀ
+
0101: 2
œ
A2
A4
œ
CAPN
AINN
+
PGA Monitor
PGA Monitor
AGND
HV_AVSS
图 57. PGA Block Diagram
The PGA inputs are filtered by an RC network to decrease sensitivity to radio frequency interference (RFI) and
electromagnetic interference (EMI) interference. The PGA is comprised of two stages: a gain stage followed by
an attenuation stage. The first stage is a high input impedance, noninverting differential amplifier (amplifiers A1
and A2) and provides the PGA gain.
The second stage is an inverting, differential amplifier (amplifiers A3 and A4) and provides the attenuation stage.
The second stage provides the PGA attenuation for high-amplitude signals. The common-mode voltage of the
differential signal is shifted to AVDD / 2. The second stage drives the modulator input of the ADC and is also
connected to the CAPP and CAPN pins. An external 1-nF capacitor filters the modulator input sampling pulses
and also provides the antialias filter. Place the capacitor close to the pins using short, direct traces. Avoid
running clock traces or other digital traces underneath or in the vicinity of these pins.
Amplifiers A1 and A2 have inverse-parallel-connected protection diodes across the amplifiers inputs to clamp the
voltage under signal overrange conditions. When the input is overranged, the diodes may conduct resulting in
current flow through the diodes, and subsequently, through the analog input pins. Conditions of high dV/dt input
signals, such as those generated by the switching of a signal multiplexer, can lead to transient turn-on of the
clamp diodes. Use an RC filter at the PGA inputs to limit the dV/dt of the signal to reduce turn-on of the clamp
diodes.
The PGA is monitored for high and low operating voltage headroom at four signal points. The output of the eight
total monitor outputs are ORed together into a single error bit contained in the conversion data status byte and
the STATUS0 register.
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9.3.3.1 PGA Operating Range
As with many amplifiers, the PGA limits the absolute input voltage that must not be exceeded in the linear
operating range. The absolute voltage is the combined differential and common-mode voltages. The maximum
allowable absolute voltage is determined by the PGA gain, the maximum differential input voltage (VIN), and the
minimum value of the high-voltage power supply. Maintain the absolute input voltage (VAINX) within the range as
shown in 公式 5, otherwise incorrect conversion data can result:
HV_AVSS + 2.5 + VIN × (Gain – 1) / 2 < V(AINx) < HV_AVDD – 2.5 – VIN × (Gain – 1) / 2
where:
•
•
•
For gain < 1, use value = 1 for gain
V(AINx) = Absolute input voltage
VIN = VAINP – VAINN = Maximum expected differential input voltage
(5)
The differential input signal can also be limited by two other conditions. The first limiting condition is when the
reference voltage exceeds AVDD – 1 V (nominally VREF > 4 V). In this case, the differential input signal is limited
to: VIN = ±(AVDD – 1 V) / Gain, instead of the ideal VIN = ±VREF / Gain. The second limiting condition applies to
gains of 0.125 and 0.1875. In this case, the differential input signal is limited to: VIN = ±20 V, regardless of the
reference voltage.
图 58 and 图 59 show the relationship between the PGA input voltage to the PGA output voltage. In attenuation
mode, the first PGA stage is configured as a unity-gain follower. The second PGA stage attenuates the
differential input and shifts the signal common-mode voltage to AVDD / 2 to drive the ADC input.
In gain mode, the first PGA stage amplifies the differential signal. The second PGA stage is configured as a
unity-gain follower with level-shift. 图 58 and 图 59 show the corresponding output voltage of the PGA stages that
must have operating voltage headroom.
PGA Input
PGA First Stage Output
PGA Second Stage Output
HV_AVDD
HV_AVDD œ 2.5 V
VINP
AVDD
AVDD œ 0.5 V
VINP
AVDD/2 + VIN ‡ Gain / 2
AVDD/2
AVDD/2 - VIN ‡ Gain / 2
VIN = VINP - VINN
VINN
AGND + 0.5 V
AGND
VINN
HV_AVSS + 2.5 V
HV_AVSS
图 58. PGA Attenuation Mode
PGA Input
PGA First Stage Output
PGA Second Stage Output
HV_AVDD
HV_AVDD œ 2.5 V
AVDD
AVDD œ 0.5 V
VIN = VINP - VINN
VINP
VINP + VIN ‡ (Gain œ 1) / 2
AVDD/2 + VIN ‡ Gain / 2
AVDD/2
VINN
AVDD/2 - VIN ‡ Gain / 2
VINN - VIN ‡ (Gain œ 1) / 2
AGND + 0.5 V
AGND
HV_AVSS + 2.5 V
HV_AVSS
图 59. PGA Gain Mode
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9.3.3.2 PGA Monitor
The PGA requires operating voltage headroom at the input and output nodes. The PGA must be within the linear
operating range, otherwise the conversion data are not valid. Use the internal PGA monitors to assist in the
detection of PGA overload. The PGA has four monitors (two monitors for the input and two monitors for the
output) with high and low thresholds for each, for a total of eight possible alarms. The status of each PGA
monitor is read in the STATUS1 register. The PGA monitoring points are illustrated in 图 57. 图 60 shows the
operation of the low-overload threshold and the high-overload threshold of each PGA monitor point.
Respective High Alarm
HV_AVDD
HV_AVDD œ 2 V
PGA Input or Output Voltage
HV_AVSS + 2 V
HV_AVSS
Respective Low Alarm
图 60. PGA Monitor Thresholds
Check for PGA overload by polling the STAT12 bit (bit 4 of the STATUS conversion byte or STATUS0 register).
The STAT12 bit is the logical OR of all PGA error flags with the CRC-2 error flag. After the STAT12 bit asserts,
poll the STATUS1 and STATUS2 registers (address 11h and 12h) to determine the source of the error. The
status of the PGA overload is latched in the STATUS1 register and remains latched after the overload condition
is removed. Reading the STATUS1 register clears the PGA overload bits (clear-on-read operation). The PGA
overload flags and the CRC2 flag must be reset in order to clear the STAT12 bit. See the STATUS1 register for a
description of the PGA overload bits.
The PGA monitors are analog comparators that can respond to transient overload conditions. Transient
conditions can occur, for example, when multiplexing the inputs or when the gain is too high for the voltage of the
next channel.
9.3.4 Reference Voltage
The options for the ADC reference voltage are the internal 2.5-V reference, two external reference sources, or
the AVDD power supply. The reference voltage is differential and is defined by: VREF = (VREFP – VREFN), where
VREFP and VREFN are the positive and negative reference voltages. The polarity of VREF must always be positive.
图 61 illustrates the block diagram of the reference input multiplexer used to select the reference.
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REFENB bit 4 of REF
(register address = 06h)
0: Internal Ref off (default)
1: Internal Ref on
2.5-V
Internal
AVDD
RMUXP[1:0] bits 3:2 of REF
(register address = 06h)
REFOUT
00
01
10
11
VREFP
REFP0
10 µF
+
REFP1/GPIO0
(1)
REF
Monitor
BUF
00
01
10
11
AGND
ADC
REFN0
VREFN
REFN1/GPIO1
RMUXN[1:0] bits 1:0 of REF
(register address = 06h)
(1) The internal reference requires an external 10-µF capacitor connected from REFOUT to AGND.
图 61. Reference Multiplexer Diagram
Program the RMUXP[1:0] and RMUXN[1:0] bits of the REF register to select the positive and negative reference
voltages, respectively. The positive reference options are internal 2.5-V positive, external REFP0, external
REFP1, or AVDD. The negative selections are internal 2.5-V negative, external REFN0, external REFN1, or
AGND.
The reference voltage is internally monitored for a low-voltage condition; see the Reference Monitor section.
9.3.4.1 Internal Reference
The ADC includes a precision 2.5-V reference. The REFENB bit of the REF register enables the reference
(default = off). Program the reference multiplexer bits RMUXP[1:0] and RMUXN[1:0] to 00b to select the internal
reference. A 10-µF capacitor is required between the REFOUT and AGND pins to filter the reference noise. The
capacitor is not required if the internal reference is not used. Always enable the internal reference if using the
current sources.
REFOUT is the buffered reference output and AGND is the reference return. For good voltage regulation and to
minimize ground noise, use a star-layout connection for the reference return and make the return connection
close to the AGND pin.
Be aware of AVDD inrush current when the reference is enabled. The inrush current is a result of charging the
10-µF REFOUT capacitor. Also, be aware of the reference voltage stabilization time when starting a conversion
or when calibrating the ADC.
9.3.4.2 External Reference
Use an external reference by applying the reference voltage to the reference input pins and then program the
reference multiplexer bits RMUXP[1:0] and RMUXN[1:0]. Values of 10b select the REFP0 and REFN0 reference
input pins and values of 11b select the REFP1 and REFN1 reference input pins. The reference inputs are
differential with positive and negative inputs. Follow the specified absolute and differential reference voltage
operating conditions; see the Recommended Operating Conditions table. Use a 10-nF or larger bypass capacitor
across the reference input pins to filter noise. The reference input current can lead to a voltage error if large
reference impedances are present. When a reference impedance is present, consider the impact of the reference
voltage error to the overall measurement accuracy.
9.3.4.3 AVDD Power-Supply Reference
Use the AVDD power supply as a reference by setting the reference multiplexer bits RMUXP[1:0] and
RMUXN[1:0] to 01 (default mode of operation). For a 6-wire load cell application, connect the excitation sense
voltage to the reference inputs to improve measurement accuracy.
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9.3.4.4 Reference Monitor
The ADC incorporates a reference monitor to help detect a low or missing reference voltage. As shown in 图 62,
when the reference input voltage (VREF = VREFP – VREFN) falls below 0.4 V, the REFALM bit is set in the
STATUS0 register. The alarm is read-only and resets at the next conversion after the fault condition is cleared.
To implement detection of a missing reference voltage, use a 100-kΩ resistor across the reference inputs. If
either positive or negative reference inputs become disconnected, the reference inputs are biased to 0 V
differential, thereby triggering the low reference alarm. Poll bit 3 (REFALM) of the STATUS0 register to
determine if the reference alarm has triggered.
Reference Voltage
(VREF
)
0.4 V
REFALM
(Bit 3 of register STATUS0)
图 62. Reference Monitor Threshold
9.3.5 Current Sources (IDAC1 and IDAC2)
The ADC incorporates current sources designed to provide excitation current to the RTD, thermistor, diode, and
other sensor types that require constant-current biasing. The current sources are on the IDAC1 and IDAC2 pins.
The current sources are supplied by AVDD; therefore, the operating range is 5 V to AGND. Do not expose the
current source to voltages outside of this range. The full-accuracy voltage compliance range is specified in the
Electrical Characteristics table. The current sources are independently programmable over the 50-µA to 3000-µA
range. 图 63 shows the associated registers to configure the current sources (see 表 39). Enable the internal
reference to operate the current sources.
1000: Current source 1 connected to IDAC1 pin
I_MUX1[3:0] bits 3:0 of I_MUX
1001: Current source 1 connected to IDAC2 pin
1111: Open
(register address = 0Dh)
AVDD
I_MAG1[3:0] bits 3:0 of I_MAG
(register address = 0Eh)
0000: off
0001: 50 µA
IDAC1
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
AVDD
I_MAG2[3:0] bits 7:4 of I_MAG
(register address = 0Eh)
IDAC2
1000: Current source 2 connected to IDAC1 pin
1001: Current source 2 connected to IDAC2 pin
1111: Open
I_MUX2[3:0] bits 7:4 of I_MUX
(register address = 0Dh)
图 63. Current Source Diagram
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9.3.6 General-Purpose Inputs and Outputs (GPIOs)
The ADC provides four GPIO pins (GPIO0 through GPIO4). The GPIO are digital inputs and outputs with logic
values that are read and written by the GPIO_DAT bits of the MODE3 register. Two GPIOs are available on
dedicated pins and two GPIOs are multiplexed functions with an external reference (REFP1 and REFN1). The
GPIO input and output levels are referred to AVDD and AGND. As 图 64 shows, the input threshold value is
AVDD / 2 (typical). The GPIO_CON[3:0] bits set the GPIO connection to the designated pin (1 = connected). The
GPIO_DIR bits program the direction of the GPIO as an input (1) or output (0). The GPIO_DAT[3:0] bits are the
data values for the GPIO. If a GPIO pin is programmed as an output, the value read is the register data
previously written.
AVDD
Write Data
GPIO_CON[3:0] bits 7:4 of MODE2
GPIO_DAT[3:0] bits 3:0 of MODE3
(register address = 04h)
(register address = 05h)
0: VGPIOX is low (default)
1: VGPIOX is high
0: no connect (default)
1: connect
0
1
Read Data
GPIO[0]
GPIO[1]
GPIO[2]
REFP1/GPIO0
REFN1/GPIO1
GPIO2
GPIO_DIR[3:0] bits 3:0 of MODE2
(register address = 04h)
+
MUX
Read Select
GPIO[3]
œ
0: Output (default)
1: Input
GPIO3
GPIO
1 of 4
AVDD/2
AGND
图 64. GPIO Block Diagram
9.3.7 ADC Modulator
The modulator is an inherently stable, fourth-order, 2 + 2 pipelined ΔΣ modulator. The modulator samples the
analog input voltage at a high sample rate (fMOD = fCLK / 8) and converts the analog input to a ones density bit
stream for processing by the digital filter.
9.3.8 Digital Filter
The digital filter processes the modulator output data to produce the high-resolution conversion result. The digital
filter low-pass filters and decimates the data (data rate reduction), yielding the final data output. By adjusting the
type of filtering, tradeoffs are made between resolution, data rate, and line cycle rejection.
The digital filter has two operating modes, as shown in 图 65: sin(x) / x (sinc) mode and finite impulse response
(FIR) mode. The sinc mode provides data rates of 2.5 SPS through 40 kSPS with a selectable filter order of
sinc1 through sinc5. The FIR filter provides single-cycle settled conversions and simultaneous rejection of 50-Hz
and 60-Hz signal interference frequencies with data rates of 2.5 SPS through 20 SPS.
Sinc Filter Section
40000 SPS to 14400 SPS
fCLK / 8
7200 SPS to 2.5 SPS
Modulator
Sinc5 Filter
SincN Filter
To Offset/Gain
Calibration
Filter
Mux
FIR Filter Section
20 SPS
(
= Data rate reduction)
FIR
Averager
Data Rate
Filter Mode
10 SPS
5 SPS
2.5 SPS
DR[4:0] bits 7:3 of MODE0
(register address = 02h)
FILTER[2:0] bits 2:0 of MODE0
(register address = 02h)
图 65. Digital Filter Block Diagram
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9.3.8.1 Sinc Filter Mode
The sinc filter consists of two stages: a variable-decimation sinc5 filter followed by a variable-decimation,
variable-order sinc filter. The first stage sinc5 filter averages and down-samples the modulator data (fCLK / 8) to
produce 40000 SPS, 25600 SPS, 19200 SPS, and 14400 SPS by using decimation ratios of 32, 36, 48, and 64,
respectively. These data outputs bypass the second filter stage and as a result have response characteristics of
the first-stage sinc5 filter. The second stage receives the first stage output data at 14400 SPS, and performs
additional filtering and decimation to yield data rates of 7200 SPS to 2.5 SPS. The second stage is a
programmable order sinc filter.
The data rate is programmed by the DR[4:0] bits of the register MODE0. The filter mode is programmed by the
FILTER[2:0] bits of the MODE0 register.
9.3.8.1.1 Sinc Filter Frequency Response
As shown in 图 66 and 图 67, the first-stage sinc5 filter has frequency response nulls occurring at N × fDATA
(where N = 1, 2, 3, and so on). At the null frequencies, the filter has zero gain.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
D002
D201
图 67. Sinc Frequency Response (14400 SPS)
图 66. Sinc Frequency Response (40000 SPS)
The second stage superimposes additional nulls to the nulls produced by the first stage. The first of the
superimposed nulls occurs at the output data rate with additional nulls at multiples of the output data rate.
图 68 shows the frequency response of the combined filter stages at 2400 SPS. This data rate has five equally-
spaced nulls residing between the larger nulls at 14400-Hz multiples that are produced by the first stage. This
frequency response is similar to that of data rates 2.5 SPS to 7200 SPS. 图 69 shows the frequency response
nulls at 10 SPS.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
20 25
Frequency (kHz)
30
35
40
45
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (Hz)
D003
D004
图 68. Sinc Frequency Response (2400 SPS)
图 69. Sinc Frequency Response (10 SPS)
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图 70 and 图 71 show the frequency response of data rates 50 SPS and 60 SPS, respectively. The frequency
response is plotted to the 50-Hz 12th harmonic (10th harmonic for 60 Hz). The 50-Hz or 60-Hz fundamental and
harmonic noise of the signal are reduced by increasing the filter order of the second stage.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (Hz)
0
60 120 180 240 300 360 420 480 540 600
Frequency (Hz)
D005
D006
图 70. Sinc Frequency Response (50 SPS)
图 71. Sinc Frequency Response (60 SPS)
图 72 and 图 73 plot the detailed frequency response of the 50-SPS and 60-SPS data rates and show various
orders of the sinc filter. The high-order sinc filter increases the frequency width of the null, which improves line
cycle rejection. Improved 50-Hz or 60-Hz rejection occurs using the sinc3 or sinc4 order filter.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
45
46
47
48
49
Frequency (Hz)
50
51
52
53
54
55
55
56
57
58
59
Frequency (Hz)
60
61
62
63
64
65
D009
D010
图 72. Sinc Frequency Response, Detailed (50 SPS)
图 73. Sinc Frequency Response, Detailed (60 SPS)
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The sinc filter has an overall low-pass response that rolls off high-frequency components of the signal. The filter
bandwidth depends on the output data rate and the order of the output data rate. The overall system bandwidth
is the combined responses of the digital filter, the PGA antialias filter, and external signal filters. 表 5 lists the –3-
dB bandwidth of the sinc filter.
表 5. Sinc Filter Bandwidth
-3-dB BANDWIDTH (Hz)
DATA RATE
SINC1
SINC2
SINC3
SINC4
SINC5
(SPS)
2.5
1.10
2.23
4.43
7.38
8.85
22.1
26.6
44.3
177
525
1015
1798
2310
—
0.80
1.60
3.20
5.33
6.38
16.0
19.1
31.9
128
381
751
1421
1972
—
0.65
1.33
2.62
4.37
5.25
13.1
15.7
26.2
105
314
623
1214
1750
—
0.58
1.15
2.28
3.80
4.63
11.4
13.7
22.8
91.0
273
544
1077
1590
—
—
—
5
10
—
16.6
20
—
—
50
—
60
—
100
—
400
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
2940
3920
5227
8167
—
—
—
—
—
—
—
—
—
—
—
—
9.3.8.2 FIR Filter
The finite impulse response (FIR) filter is a coefficient-based filter that provides an overall low-pass filter
response. The filter provides simultaneous rejection of 50-Hz and 60-Hz line cycle frequencies and related
harmonics at data rates of 2.5 SPS, 5 SPS, 10 SPS, and 20 SPS. The conversion latency of the FIR filter is a
single cycle. (See 表 8 for latency of all filter settings). As illustrated in 图 65, the FIR filter section receives data
from the second-stage sinc filter. The FIR filter section decimates the data to yield the output data rate of 20
SPS. A first-order variable-decimation averaging filter (sinc1) yields 10 SPS, 5 SPS, and 2.5 SPS.
As shown in 图 74 and 图 75, the FIR filter frequency response has a series of response nulls that are positioned
close to 50 Hz and 60 Hz. The response nulls repeat near the harmonics of 50 Hz and 60 Hz.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
40
45
50
55
Frequency (Hz)
60
65
70
D011
D012
图 74. FIR Frequency Response (20 SPS)
图 75. FIR Frequency Response Detail (20 SPS)
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图 76 shows the FIR filter response at 10 SPS. New frequency nulls are superimposed to the nulls in 图 74 as a
result of the variable averager. The first of the combined response nulls occurs at 10 Hz. Additional nulls occur at
folded frequencies around multiples of 20 Hz. The first of the 10 SPS folded null frequencies is shown in 图 76 at
10 Hz, 30 Hz, 70 Hz, 90 Hz, and so on.
0
-20
-40
-60
-80
-100
-120
-140
-160
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
D013
图 76. FIR Frequency Response (10 SPS)
Similar to the response of the sinc filter, the overall FIR filter frequency has a low-pass response that rolls off
high frequencies. The response is such that the FIR filter limits the bandwidth of the input signal. The signal
bandwidth depends on the output data rate. 表 6 lists the –3-dB filter bandwidth of the FIR filter. The total system
bandwidth is the combined response of the digital filter, the PGA antialias filter, and external filters.
表 6. FIR Filter Bandwidth
DATA RATE (SPS)
–3-dB BANDWIDTH (Hz)
2.5
5
1.2
2.4
4.7
13
10
20
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9.3.8.3 50-Hz and 60-Hz Normal Mode Rejection
To reduce the effects of 50-Hz and 60-Hz noise interference, configure the data rate to reject noise occurring at
50 Hz and 60 Hz. 50-Hz and 60-Hz noise rejection depends on the filter type and order of the filter. 表 7
summarizes the 50-Hz and 60-Hz noise rejection versus data rate, filter type, and filter order. The table values
are based on 2% and 6% tolerance of noise frequency to ADC clock frequency. For the sinc filter mode, 50-Hz
and 60-Hz noise rejection is improved by increasing the filter order. Common-mode noise is also rejected at
50 Hz and 60 Hz.
表 7. 50-Hz and 60-Hz Normal Mode Rejection
DIGITAL FILTER AMPLITUDE (dB)
DATA RATE (SPS)
FILTER TYPE
FIR
50 Hz (±2%)
–113
–36
60 Hz (±2%)
–99
50 Hz (±6%)
–88
60 Hz (±6%)
–80
2.5
2.5
2.5
2.5
2.5
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–37
–40
–37
–72
–74
–80
–74
–108
–144
–111
–34
–111
–148
–95
–120
–160
–77
–111
–148
–76
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
–30
–30
5
–68
–68
–60
–60
5
–102
–136
–111
–34
–102
–136
–94
–90
–90
5
–120
–73
–120
–68
10
10
10
10
10
16.6
16.6
16.6
16.6
20
20
20
20
20
50
50
50
50
60
60
60
60
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
–25
–25
–68
–68
–50
–50
–102
–136
–34
–102
–136
–21
–75
–75
–100
–24
–100
–21
–68
–42
–48
–42
–102
–136
–95
–63
–72
–63
–84
–96
–84
–94
–66
–66
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
–18
–34
–18
–24
–36
–68
–36
–48
–54
–102
–136
–15
–54
–72
–72
–72
–96
–34
–24
–15
–68
–30
–48
–30
–102
–136
–13
–45
–72
–45
–60
–96
–60
–34
–12
–24
–27
–68
–24
–48
–40
–102
–136
–36
–72
–53
–48
–96
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9.4 Device Functional Modes
9.4.1 Conversion Control
The START pin or the START command controls the conversions. If using commands to control conversions,
keep the START pin low to avoid contention between the pin and commands. Commands take affect on the
32nd falling SCLK edge. See the Switching Characteristics table for details on conversion control timing.
The ADC has two conversion control operating modes: continuous-conversion mode and pulse-conversion mode.
The continuous-conversion mode performs conversions indefinitely until the user stops the conversions. Pulse-
conversion mode performs one conversion and then stops. The CONVRT (bit 4 of the MODE1 register)
programs the mode.
9.4.1.1 Continuous-Conversion Mode
This conversion mode performs continuous conversions until the user stops conversions. To start conversions,
take the START pin high or send the START command. DRDY is driven high when the conversion is started.
DRDY is driven low when the conversion data are ready. Conversion data are available to read at that time. Take
the START pin low or send a STOP command to stop conversions. When conversions are stopped, the
conversion in progress runs to completion. To restart a conversion that is in progress, toggle the START pin low-
then-high or send a new START command.
9.4.1.2 Pulse-Conversion Mode
In pulse-conversion mode, the ADC performs one conversion when START is taken high or when the START
command is sent. When the conversion completes, further conversions stop. The DRDY output is driven high to
indicate the conversion is in progress and is driven low when the conversion data are ready. Conversion data are
read at that time. To restart a conversion in progress, toggle the START pin low-then-high or send a new START
command. Driving START low or sending the stop command does not interrupt the current conversion.
9.4.1.3 Conversion Latency
The digital filter averages data from the modulator to produce the conversion result. The discrete stages of the
digital filter must have settled data to provide fully settled output data. The order and the decimation ratio of the
digital filter determine the amount of data averaged that affects the latency of the conversion data. The FIR and
sinc1 filter modes are zero latency because the ADC provides the conversion result in one conversion cycle.
Latency time is an important consideration for data throughput in multiplexed applications.
表 8 lists the conversion latency values of the ADC. Conversion latency is defined as the time from the start of
the first conversion by taking the START pin high or sending the start command to when the conversion data are
ready. The ADC is designed to provide fully settled data under this condition. The conversion latency values
listed in 表 8 include the programmable start-conversion delay equal to 50 µs before the digital filter starts, which
also includes overhead time for final data processing. After the first conversion completes in continuous
conversion mode, the period of the next conversions are equal to 1 / fDATA. The first conversion latency time in
auto-zero mode has twice the values listed in 表 8. The values listed in 表 8 are equal to the period of the next
conversions.
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Device Functional Modes (接下页)
表 8. Conversion Latency Time
CONVERSION LATENCY TIME (t(STDR)(1), ms)
DATA RATE
(SPS)
SINC1
400.4
200.4
100.4
60.43
50.43
20.43
17.09
10.43
2.925
1.258
0.841
0.633
0.564
—
SINC2
800.4
400.4
200.4
120.4
100.4
40.42
33.76
20.42
5.424
2.091
1.258
0.841
0.702
—
SINC3
1,200
600.4
300.4
180.4
150.4
60.43
50.43
30.43
7.925
2.925
1.675
1.050
0.841
—
SINC4
1,600
800.4
400.4
240.4
200.4
80.43
67.09
40.43
10.43
3.758
2.091
1.258
0.980
—
SINC5
—
FIR
402.2
202.2
102.2
—
2.5
5
—
10
—
16.6
20
—
—
52.22
—
50
—
60
—
—
100
—
—
400
—
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
—
—
—
—
0.423
0.336
0.271
0.179
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1) Auto-zero mode off, conversion-start time delay = 50 µs (DELAY[3:0] = 0001). Actual conversion latency time can vary depending on the
accuracy of fCLK
.
As shown in 图 77, if the input signal changes during the conversion phase, the conversion data are a mix of old
and new data. After an unsynchronized input change, the number of conversion periods required to provide fully
settled output data are calculated by dividing the conversion latency by the nominal period and then adding one
additional conversion. In auto-zero mode, use twice the latency values plus one additional conversion.
Old VIN
New VIN
VIN = VAINP - VAINN
Fully settled
new data
Mix of old data
and new data
Old data
DRDY pin
图 77. Input Change During Conversions
9.4.1.4 Start-Conversion Delay
At the start of a conversion, the ADC provides a programmable delay to allow for PGA settling time and to
provide a delay for any external component settling effects. The default value is 50 µs and provides the settling
time for the PGA antialiasing filter. Use additional delay time as needed to provide settling time for the effects of
external components. The latency values listed in 表 8 are with a start-conversion delay value = 50 µs. As an
alternative to this parameter, delay the start of conversion after the input and configuration changes.
9.4.2 Auto-Zero Mode
Auto-zero mode is a continuous calibration technique that provides low offset voltage and near-zero drift over
time and temperature. Auto-zero mode is a form of chopping that covers the internal ADC signal chain. The ADC
alternates the polarity of consecutive conversions by internally reversing the input signal. The digital filter
subtracts the results of two reverse-polarity conversions to yield the final conversion data. The subtraction result
removes the offset error. Auto-zero mode is available only for use with the AIN0 and AIN1 inputs. See the
MODE1 register for details on how to program auto-zero mode.
40
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Auto-zero mode changes the data rate and the conversion latency time corresponding to the first conversion.
The new data rate is equal to 1 divided by the latency values listed in 表 8. For example, when the ADC is
programmed to 20 SPS and FIR mode, the new data rate is = 1 / 52.22 ms = 19.15 SPS. Regardless of the new
data rate, the location of the digital filter frequency notches are unaltered. The latency time corresponding to the
first conversion is equal to 2 × the latency time values listed in 表 8. Auto-zero mode reduces conversion noise
by √2 because auto-zero mode effectively averages the data from two conversions.
9.4.3 Clock Mode
Operate the ADC with an external clock or with the internal oscillator. For external clock operation, apply the
clock signal to CLKIN. The ADC detects the presence of the external clock and selects the clock automatically.
As described in 表 9, the clock frequency depends on the data rate used. Be sure the external clock is free of
overshoot and glitches. A source-termination resistor placed at the clock buffer often helps reduce overshoot. For
internal clock operation, connect CLKIN to DGND. Be aware of the accuracy of the internal oscillator as
described in the Electrical Characteristics table. The internal oscillator begins operating immediately at device
power-on. Read the CLOCK bit in the STATUS0 register to verify the clock mode.
表 9. External Clock vs Data Rate
DATA RATE
2.5 SPS to 25600 SPS
40000 SPS
CLOCK FREQUENCY
7.3728 MHz
10.24 MHz
9.4.4 Reset
The ADC is reset in three ways: automatic by power-on-reset, manually via the RESET pin, or by the RESET
command.
When reset, the serial interface, conversion-control logic, digital filter, and register map values are reset. The
RESET bit of the STATUS0 register is set after a reset occurs. Clear the bit to detect the next device reset. If the
START pin is high after reset, the ADC immediately begins conversions.
9.4.4.1 Power-On Reset
After supply voltages cross the respective reset voltage thresholds at power-up, the ADC is reset and after 216
fCLK cycles the ADC is ready for communication. Until this time, DRDY is held low. DRDY is then driven high to
indicate when ADC communication can begin. The conversion cycle starts 512 / fCLK cycle after DRDY asserts
high. 图 4 illustrates the power-on reset behavior.
9.4.4.2 Reset by Pin
Reset the ADC by taking the RESET pin low for a minimum of four fCLK cycles, and then return the pin high. After
reset, the conversion starts 512 / fCLK cycles later. See 图 5 for RESET pin timing.
9.4.4.3 Reset by Command
Reset the ADC through the serial interface by the RESET command. Bring CS1 high first to reset the serial
interface to ensure the ADC is ready for the command. After reset, the conversion starts 512 / fCLK cycles later.
See 图 5 for the reset command timing.
9.4.5 Calibration
The ADC incorporates calibration registers and associated commands to calibrate offset and full-scale errors.
Calibrate the ADC by using calibration commands, or calibrate by writing to the calibration registers directly (user
calibration). To calibrate by command, send the offset or full-scale calibration commands. To user calibrate, write
to the calibration registers with values based on the acquired conversion data. Perform the offset calibration
operation before the full-scale calibration operation.
9.4.5.1 Offset and Full-Scale Calibration
Use the offset and full-scale (gain) registers to correct offset or full-scale errors, respectively. As illustrated in 图
78, the offset calibration register is subtracted from the output data before multiplication by the full-scale register,
which is divided by 400000h. After the calibration operation, the final value of the output data is clipped to 24
bits.
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VAINP
C A D
ADC
+
Output Data
Clipped to 24 bits
Digital
Filter
Final
Output
ꢀ
VAINN
-
1/400000h
OFCAL[2:0] registers
(register addresses = 07h, 08h, 09h)
FSCAL[2:0] registers
(register addresses = 0Ah, 0Bh, 0Ch)
图 78. Calibration Block Diagram
公式 6 shows the internal calibration.
Final Output Data = (Pre Data – OFCAL[2:0]) × FSCAL[2:0] / 400000h
(6)
9.4.5.1.1 Offset Calibration Registers
The offset calibration word, as listed in 表 10, is 24 bits consisting of three 8-bit registers. The offset value is
subtracted from the conversion result. The offset value is in two's-complement format with a maximum positive
value equal to 7FFFFFh and a maximum negative value equal to 800000h. A register value equal to 000000h
has no offset correction. Although the calibration registers provide a wide range of offset values, the input signal
cannot exceed ±106% of the precalibrated range; otherwise the ADC is overranged. 表 11 lists example values
of the offset register.
表 10. Offset Calibration Registers
BYTE
ORDER
REGISTER
ADDRESS
BIT ORDER
OFCAL0
OFCAL1
OFCAL2
LSB
07h
08h
09h
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
B23 (MSB)
B17
B16
表 11. Offset Calibration Register Values
OFCAL[2:0] REGISTER VALUE
OFFSET CALIBRATED OUTPUT VALUE
000001h
000000h
FFFFFFh
FFFFFFh
000000h
000001h
9.4.5.1.2 Full-Scale Calibration Registers
The full-scale calibration word, as listed in 表 12, is 24 bits consisting of three 8-bit registers. The full-scale
calibration value is straight binary and normalized to a unity-gain at a value of 400000h. 表 13 lists register
values for selected gain factors. Gain errors greater than unity are corrected by full-scale values less than
400000h. Although the calibration registers provide a wide range of possible values, the input signal must not
exceed ±106% of the precalibrated input range; otherwise the ADC is overranged.
表 12. Full-Scale Calibration Registers
BYTE
ORDER
REGISTER
ADDRESS
BIT ORDER
FSCAL0
FSCAL1
FSCAL2
LSB
0Ah
0Bh
0Ch
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
B23 (MSB)
B17
B16
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表 13. Full-Scale Calibration Register Values
FSCAL[2:0] REGISTER VALUE
GAIN FACTOR
433333h
400000h
1.05
1
3CCCCCh
0.95
9.4.5.2 Offset Calibration (OFSCAL)
The offset calibration command corrects offset errors. To calibrate offset errors, short the inputs to the ADC or to
calibrate the system, short the signal inputs to the system. When the command is sent, the ADC averages 16
conversion results to reduce conversion noise for improved calibration accuracy. When calibration is complete,
the ADC performs one conversion using the new calibration value. The new calibration value is written to the
offset calibration register.
9.4.5.3 Full-Scale Calibration (GANCAL)
The full-scale calibration command corrects gain errors. To calibrate, apply a positive calibration voltage to the
ADC, or apply the voltage to the signal inputs of the system, wait for the signal to settle, and then send the
command. The ADC averages 16 conversion results to reduce conversion noise to improve calibration accuracy.
The ADC computes the full-scale calibration value so that the applied calibration voltage is scaled to an equal
positive full-scale output code. The computed result is written to the calibration register. The ADC then performs
one new conversion using the new calibration value.
9.4.5.4 Calibration Command Procedure
Use the following calibration procedure using the calibration commands. The register lock mode must be in the
UNLOCK state prior to using the calibration commands. When calibrating at power-on, make sure the reference
voltage has stabilized. Perform an offset calibration operation prior to full-scale calibration.
1. Select the desired input channel, gain, reference mode, and related ADC configurations as required.
2. Apply the appropriate calibration signal (zero or full-scale) to the ADC or system inputs.
3. Take the START pin high or send the START command to start conversions. DRDY is driven high.
4. Before the first conversion completes, send the appropriate calibration command. Keep CS1 low; otherwise
the command is cancelled. Do not send other commands during the calibration period.
5. The calibration time, as described in 表 14, depends on the data rate and digital filter mode. DRDY is driven
low when calibration is complete. As a result, offset or full-scale calibration registers are updated with new
values. New conversion data are available immediately using the new calibration value.
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表 14. Calibration Time (ms)
FILTER MODE(1)
DATA RATE
(SPS)
SINC1
6801
3401
1701
1021
850.9
340.9
284.2
170.9
43.36
15.02
7.938
4.397
3.216
—
SINC2
SINC3
8401
4201
2101
1261
1051
421
SINC4
SINC5
—
FIR
6805
3405
1705
—
2.5
5
7601
3801
1901
1141
951
9201
4601
2300
1381
1151
460.9
384.2
230.9
58.36
20.02
10.44
5.647
4.050
—
—
10
—
16.6
20
—
—
854.5
—
50
380.9
317.5
190.9
48.36
16.69
8.772
4.813
3.494
—
—
60
350.9
210.9
53.36
18.36
9.605
5.230
3.772
—
—
—
100
—
—
400
—
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
—
—
—
—
1.892
1.458
1.133
0.738
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1) Nominal clock frequency. Auto-zero mode disabled.
9.4.5.5 User Calibration Procedure
To user calibrate, apply the calibration voltage, acquire conversion data, and compute the calibration value. Write
the computed value to the corresponding calibration registers. Before starting calibration, preset the offset and
full-scale registers to 000000h and 400000h, respectively.
To offset calibrate, short the inputs to the system and average n number of the conversion data. Averaging
conversion data reduces noise to increase calibration accuracy. Write the average value of the conversion data
to the offset registers.
To gain calibrate using a full-scale calibration signal, temporarily reduce the full-scale register by 95% to avoid
any output clipped codes (set FSCAL[2:0] to 3CCCCCh). Acquire n number of conversions and average the
conversions to increase calibration accuracy. Compute the full-scale calibration value as shown in 公式 7:
Full-Scale Calibration Value = (Expected Code / Actual Code) × 400000h
where:
•
Expected code = 799998h using full-scale calibration signal and 95% precalibration scale factor
(7)
44
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9.5 Programming
9.5.1 Serial Interface
The SPI-compatible serial interface is used to read conversion data, configure the device registers, and control
ADC operation. The CRC is used to validate error-free transmission of the input and output data flow. The serial
interface consists of the following control signals: CS1, CS2, SCLK, DIN, and DOUT/DRDY. Most microcontroller
SPI peripherals can operate with the ADC. The interface operates in SPI mode 1, where CPOL = 0 and CPHA =
1. In SPI mode 1, SCLK idles low and data are updated or changed on the SCLK rising edges; data are latched
or read on the SCLK falling edges. Timing details of the SPI protocol are provided in 图 1 and 图 2.
9.5.1.1 Chip-Select Pins (CS1 and CS2)
The ADC consists of discrete PGA and ADC sections with each section selected for communication by separate
chip-select inputs (CS1 and CS2). Most commands require the use of CS1 to control the ADC section. However,
for control of the PGA section, use CS2 for register access commands at address 10h and above. Communicate
to the device by taking either CS1 or CS2 low corresponding to the type of command and whether addressing
the ADC or PGA registers.
CS1 and CS2 are active low inputs. In normal operation, take one chip-select input low at a time and keep that
input low for the duration the command operation. Take the chip-select input high after the command operation
completes. When the chip-select input is taken high, the serial interface resets and SCLK activity is ignored (thus
blocking commands). When both chip-select inputs are high, DOUT/DRDY enters the high-impedance state. CS1
must be low in order to poll the data-ready function provided by DOUT/DRDY. DRDY remains active regardless
of the state of the chip-select inputs.
9.5.1.2 Serial Clock (SCLK)
SCLK is the serial interface shift clock input that clocks data into and out of the device. Output data are updated
on the rising edge of SCLK and input data are latched on the falling edge of SCLK. Return SCLK low after the
data operation completes. SCLK is a Schmidt-triggered input designed to provide noise immunity. Even though
SCLK is noise resistant, keep SCLK noise-free as possible to avoid unintentional SCLK transitions. Avoid ringing
and overshoot on the SCLK input. Use a series termination resistor at the SCLK drive pin to reduce ringing.
9.5.1.3 Data Input (DIN)
DIN is the serial interface data input. DIN inputs commands and register data to the device. Input data are
latched on the falling edge of SCLK.
9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
The DOUT/DRDY pin is the serial interface data output. This pin also provides the conversion-data ready output.
The function of the pin changes whether a read data (or read register) operation is in progress. With CS1 low
and when not reading register or conversion data, the pin indicates when data are ready by asserting low. For
conversion data and register read operations, the function changes to data output. When the read operation is
completed, the function changes to conversion-data ready. As DOUT, the data are updated on the SCLK rising
edge and the data must therefore be latched on the SCLK falling edge. CS1 must be low for DOUT/DRDY to
provide the data-ready function. When both chip-select pins are high, DOUT/DRDY is in high-impedance mode
(tri-state).
9.5.2 Data Ready (DRDY)
DRDY asserts low to indicate that new conversion data are ready for readback. The operation of DRDY depends
on the mode (continuous or pulse) and whether or not the conversion data are retrieved.
9.5.2.1 DRDY in Continuous-Conversion Mode
In continuous-conversion mode, DRDY is driven high when conversions are started and is driven low when
conversion data are ready. During data readback, DRDY is driven high, which indicates completion of the read
operation. If the conversion data are not read, DRDY remains low and pulses high 16 fCLK cycles prior to the next
falling edge.
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To read back the current conversion data before the next conversion completes, send the read data command at
least 16 fCLK cycles prior to the DRDY falling edge. If the readback command is sent less than 16 fCLK cycles
prior to the DRDY falling edge, either the previous or new conversion data are provided. The timing of the
command determines whether previous or new data are provided. In the event that previous data are provided,
DRDY transitioning to low is suspended until after the read data operation completes. In this case, the DRDY bit
of the STATUS0 byte is low to indicate that the previous data have already been read. In the event that new
conversion data are provided, DRDY transitions low as normal. The DRDY bit of the STATUS0 byte is high to
indicate new data are read. To ensure readback of new conversion data, wait until DRDY asserts low before
starting the data read operation.
9.5.2.2 DRDY in Pulse-Conversion Mode
DRDY is driven high at conversion start and is driven low when the conversion data are ready. DRDY remains
low until a new conversion is started.
图 79 shows DRDY operation with and without data retrieval in two conversion modes.
DRDY - with data retrieval
(Continuous-conversion mode)
DRDY œ w/o data retrieval
(Continuous-conversion mode)
DRDY œ w or w/o data retreival
(Pulse-conversion mode)
START
Command
START
STOP
START
STOP
图 79. DRDY Operation
9.5.2.3 Data Ready by Software Polling
If desired, poll the DRDY bit in the STATUS word instead of polling the DRDY pin. In software poll mode, read
the STATUS0 byte and poll the DRDY bit. If the bit is high, then conversion data are new from the last data read
operation. If the bit is low, conversion data are not new from the last data read operation. In this case, the
previous conversion data are returned. In order to avoid missing conversion data in continuos conversion mode,
poll the bit at least as often as the period of the data rate.
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9.5.3 Conversion Data
Conversion data are read by the RDATA command. To read conversion data, take CS1 low and issue the read
data command. The conversion data field consists of an optional STATUS0 byte, three data bytes, and the CRC
byte. The CRC byte is computed over the combined STATUS0 byte and three conversion data bytes. See the
RDATA Command section for details on reading conversion data.
9.5.3.1 Status Byte (STATUS0)
The status byte contains information on the operating status of the ADC. The contents of the STATUS0 register
byte is included with the conversion data by setting the STATENB bit of the MODE3 register. Alternatively, read
the STATUS0 register directly by the register read command without having to read conversion data.
9.5.3.2 Conversion Data Format
The conversion data are 24 bits, in two's-complement format to represent positive and negative values. The data
begins with the most significant bit (sign bit) first. The data are scaled so that VIN = 0 V results in an ideal code
value of 000000h, the positive full-scale input is equal to an ideal value of 7FFFFFh and the negative full-scale
input is equal to an ideal code value of 800000h. 表 15 shows the code values. The data are clipped to 7FFFFFh
and 800000h during positive and negative signal overdrive, respectively.
表 15. ADC Conversion Data Codes
DESCRIPTION
Positive full scale
1 LSB
INPUT SIGNAL (V)
≥ VREF / Gain × (223 – 1) / 223
24-BIT CONVERSION DATA(1)
7FFFFFh
000001h
000000h
FFFFFFh
800000h
VREF / (Gain × 223
)
Zero scale
0
–1 LSB
–VREF / (Gain × 223
≤ –VREF / Gain
)
Negative full scale
(1) Ideal output code excluding noise, offset, gain, and linearity errors.
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9.5.4 Cyclic Redundancy Check (CRC)
Cyclic redundancy check (CRC) is an error detection byte that detects communication errors to and from the host
and ADC. CRC is the division remainder of the payload data by the prescribed CRC polynomial. The payload
data are 1, 2, 3, or 4 bytes depending on the data transfer operation.
The host computes the CRC over the two command bytes and appends the CRC to the command string (third
byte). A fourth, zero-value byte completes the command field to the ADC. The ADC performs the CRC
calculation and compares the result to the CRC transmitted by the host. If the host and ADC CRC values match,
the command executes and the ADC responds by transmitting the valid CRC during the fourth byte of the
command. If the CRC is error free and the operation is a data read, the ADC responds with a second CRC that is
computed for the requested data byte payload. The response data payload is 1, 3, or 4 bytes depending on the
type of operation.
If the host and ADC CRC values do not match, the command does not execute and the ADC responds with an
inverted CRC value, calculated over the received command bytes. The inverted CRC is intended to signal the
host of the failed operation. The host terminates transmission of further bytes to stop the command operation.
The CRC1 bit is set in the STATUS0 register when a error pertaining to ADC registers occur. The STAT12 and
CRC2 flags are set when an error pertaining to PGA registers occur.
The ADC is ready to accept the next command after all required bytes are transmitted when no CRC error
occurs, or after a CRC error occurs when terminated at the end of the fourth command byte.
The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) of the argument by a CRC
polynomial. The CRC polynomial is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X + 1. The nine
binary polynomial coefficients are: 100000111b.
The following is a general procedure to compute the CRC value:
1. Left shift the concatenated 1-, 2-, 3-, or 4-byte argument (if required) to create a new 40-bit data value
(the starting data value). The shifted data are padded with ones to the right of the argument.
2. Align the MSB of the CRC polynomial (100000111) to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation
creates a new, shorter length value. The bits of the data values that are not in alignment with the CRC
polynomial drop down and append to the right of the new XOR result.
4. When the XOR result is less than 100000000b, the procedure ends, yielding the 8-bit CRC value.
Otherwise, continue with the XOR operation shown in step 2 using the current data value. The number of
loop iterations depends on the value of the initial data.
The following sections detail the input and output data of each command. In the descriptions that follow, these
CRC mnemonics apply:
•
CRC-2: Input the CRC of command bytes 1 and 2. Except for the WREG command, the byte 2 value is
arbitrary.
•
•
•
•
•
•
Out CRC-1: Output the CRC of one register data byte.
Out CRC-2: Output the CRC of two command bytes, inverted value if an input CRC error is detected.
Out CRC-3: Output the CRC of three conversion data bytes.
Out CRC-4: Output the CRC of three conversion data bytes plus the STATUS0 byte.
Echo Byte 1: Echo of received input byte 1.
Echo Byte 2: Echo of received input byte 2.
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9.5.5 Commands
Commands are used to read conversion data, control the device, and read and write register data. 表 16
provides a list of commands and the corresponding command byte sequence. Only send the commands that are
listed in 表 16.
The column labeled CSx shows the use of CS1 or CS2 for the particular command type. Most commands use
CS1. Only activate CS2 to access register data at address 10h and above and to lock register data at address
10h and above. See the Chip-Select Pins (CS1 and CS2) section for details of chip-select operation.
表 16. Command Byte Summary
MNEMONIC
CSx
DESCRIPTION
BYTE 1
BYTE 2(1)
BYTE 3
BYTE 4
CONTROL COMMANDS
NOP
CS1 or CS2
No operation
00h
06h
08h
0Ah
Arbitrary
Arbitrary
Arbitrary
Arbitrary
CRC-2
CRC-2
CRC-2
CRC-2
00h
00h
00h
00h
RESET
START
STOP
CS1
CS1
CS1
Reset
Start conversion
Stop conversion
READ DATA COMMAND
RDATA CS1
CALIBRATION COMMANDS
Read conversion data
12h
Arbitrary
CRC-2
00h
OFSCAL
GANCAL
CS1
CS1
Offset calibration
Gain calibration
16h
17h
Arbitrary
Arbitrary
CRC-2
CRC-2
00h
00h
REGISTER COMMANDS
RREG
WREG
CS1 or CS2
CS1 or CS2
Read register data
Write register data
20h + rrh(2)
40h + rrh(2)
Arbitrary
CRC-2
CRC-2
00h
00h
Register data
PROTECTION COMMANDS
LOCK
CS1 or CS2
CS1 or CS2
Register data lock
F2h
F5h
Arbitrary
Arbitrary
CRC-2
CRC-2
00h
00h
UNLOCK
Register data unlock
(1) Excluding the write-register command, the value of the second byte is arbitrary (any value) but is included in the CRC calculation.
(2) rrh = 5-bit register address.
9.5.5.1 General Command Format
图 80 shows an example register write operation to register address 02h (command opcode 42h). For this
register address (02h), take CS1 low. The first byte output from the ADC is always 0FFh. The host calculates the
CRC of the two input command bytes. The Out CRC-2 byte is the ADC-calculated, output CRC based on the
received command bytes. If the CRC values match, the command is executed beginning at the last SCLK of the
fourth byte in the sequence. Forcing chip select high before the command completes results in command
termination. Toggle chip select low-to-high between command operations.
CS1 or CS2
1
9
17
25
SCLK
DIN
42h
FFh
Reg Data
CRC-2
00h
DOUT/DRDY
Echo Byte 1
Echo Byte 2
Out CRC-2
图 80. Register Write Command Sequence (Address = 02h)
The following sections detail the input and output byte sequence corresponding to each command. See the
Cyclic Redundancy Check (CRC) section for the notation used for the CRC.
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9.5.5.2 NOP Command
This command has no operation. Use the NOP command to validate the CRC response byte and error detection
without affecting normal operation. 表 17 shows the NOP command byte sequence.
表 17. NOP Command
DIRECTION
DIN
BYTE 1
00h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.3 RESET Command
The RESET command resets the ADC operation and resets all registers to default. See the Reset by Command
section for details. 表 18 lists the RESET command byte sequence.
表 18. RESET Command
DIRECTION
DIN
BYTE 1
06h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.4 START Command
This command starts a conversions. See the Conversion Control section for details. 表 19 lists the START
command byte sequence.
表 19. START Command
DIRECTION
DIN
BYTE 1
08h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.5 STOP Command
This command is used to stop conversions. See the Conversion Control section for details. 表 20 lists the STOP
command byte sequence.
表 20. STOP Command
DIRECTION
DIN
BYTE 1
0Ah
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.6 RDATA Command
This command reads conversion data. Because the data are buffered, the data can be read at any time during
the conversion sequence. If data are read near the completion of the conversion phase, old or new conversion
data are returned. See the Data Ready (DRDY) section for details.
The response data of the ADC varies in length depending on inclusion of the optional STATUS0 byte. See the
Conversion Data Format section for details of the format of the conversion data. 表 21 and 图 81 describe the
RDATA command byte sequence that includes the STATUS0 byte.
50
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表 21. RDATA Command
DIRECTION
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
BYTE 9
DIN
12h
Arbitrary
CRC-2
00h
00h
00h
00h
00h
00h
Out CRC-3 or
Out CRC-4(2)
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
STATUS0(1)
MSB data
MID data
LSB data
(1) Optional STATUS0 byte shown.
(2) Out CRC-4 (4-byte CRC = STATUS0 + data) if the STATUS0 byte is included in the data packet.
CS1
41
49
57
65
1
9
17
25
33
SCLK
DIN
12h
FFh
Arbitrary
00h
00h
CRC-2
00h
00h
00h
00h
MSB data
MID data
LSB DATA
Out CRC-4
Echo Byte 1
Echo Byte 2
Out CRC-2
STATUS0
DOUT/DRDY
图 81. Conversion Data Read Operation
9.5.5.7 OFSCAL Command
This command is used for offset calibration. See the Calibration section for details. 表 22 lists the OFSCAL
command byte sequence.
表 22. OFSCAL Command
DIRECTION
DIN
BYTE 1
16h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.8 GANCAL Command
This command is used for gain calibration. See the Calibration section for details. 表 23 lists the GANCAL
command byte sequence.
表 23. GANCAL Command
DIRECTION
DIN
BYTE 1
17h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.9 RREG Command
Use the RREG command to read register data. Take CS1 low to access registers within the ADC register block.
Take CS2 low to access registers within the PGA register block (see the Register Map section for the register
block map). Register data are read one byte at a time using the RREG command for each operation. Add the
register address (rrh) to the base opcode (20h) to complete the command byte (20h + rrh). 表 24 lists the RREG
command byte sequence. The ADC responds with the register data byte, most significant bit first. Data for
registers addressed outside the range is 00h. Out CRC-2 is the output CRC corresponding to the received
command bytes. Out CRC-1 is the output CRC corresponding to the single register data byte.
表 24. RREG Command
DIRECTION
DIN
BYTE 1
20h + rrh
FFh
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
BYTE 5
00h
BYTE 6
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
Register data
Out CRC-1
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9.5.5.10 WREG Command
Use the WREG command to write register data. Take CS1 low to access registers within the ADC register block.
Take CS2 low to access registers within the PGA register block (see the Register Map section for the register
block map). The WREG command writes the register data one byte at a time using the WREG command for
each operation. Add the register address (rrh) to the base opcode (40h) to complete the command byte (40h +
rrh). 表 25 lists the WREG command byte sequence. Writing to certain registers results in conversion restart. 表
28 lists the affected registers. Do not write to registers outside the address range.
Register-write access is enabled and disabled by the UNLOCK and LOCK commands, respectively. The default
mode is register UNLOCK. See the LOCK Command section.
表 25. WREG Command
DIRECTION
DIN
BYTE 1
40h + rrh
FFh
BYTE 2
BYTE 3
CRC-2
BYTE 4
00h
Register data
Echo byte 1
DOUT/DRDY
Echo byte 2
Out CRC-2
9.5.5.11 LOCK Command
Use the LOCK command to lock unintended write operations to the registers. Send the LOCK command using
CS1 to lock registers 00h to 0fh. Use CS2 to lock registers 10h to 12h. Locking the registers disables register
write access including the calibration registers. The default mode is unlocked. Register reads are allowed in
LOCK mode. 表 26 lists the LOCK command byte sequence.
表 26. LOCK Command
DIRECTION
DIN
BYTE 1
F2h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.12 UNLOCK Command
Use the UNLOCK command to allow writing register data. Send the UNLOCK command using CS1 to unlock
registers 00h to 0fh. Use CS2 to unlock registers 10h to 12h. Register unlock allows register write access
including calibration registers. 表 27 lists the UNLOCK command byte sequence.
表 27. UNLOCK Command
DIRECTION
DIN
BYTE 1
F5h
BYTE 2
Arbitrary
BYTE 3
CRC-2
BYTE 4
00h
DOUT/DRDY
FFh
Echo byte 1
Echo byte 2
Out CRC-2
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9.6 Register Map
表 28 shows the device register map consisting of 19 one-byte registers. Collectively, the registers are used to
configure the device to the desired operating mode. Access the registers by using the RREG and WREG
commands (register-read and register-write, respectively). Data are accessed one register byte at a time for each
command operation. The address of the register corresponds to using either CS1 or CS2 for the register
command operation. The CSx column shows the correlation of CS1 or CS2 to the register address. Changing the
data of certain registers results in a restart of conversions already in progress. The Restart column lists these
registers.
表 28. Register Map Summary
ADDRESS
00h
REGISTER
ID
DEFAULT
6xh
RESTART
CSx
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS2
CS2
CS2
BIT 7
LOCK1
0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DEV_ID[3:0]
REV_ID1[3:0]
01h
STATUS0
MODE0
MODE1
MODE2
MODE3
REF
01h
24h
01h
00h
00h
05h
00h
00h
00h
00h
00h
40h
FFh
00h
00h
50h
xxh
CRC1
0
STAT12
CONVRT
REFALM
DRDY
CLOCK
RESET
02h
Yes
Yes
DR[4:0]
FILTER[2:0]
03h
0
AUTOZERO
DELAY[3:0]
04h
GPIO_CON[3:0]
GPIO_DIR[3:0]
GPIO_DAT[3:0]
05h
0
0
STATENB
0
0
0
0
06h
Yes
REFENB
RMUXP[1:0]
RMUXN[1:0]
07h
OFCAL0
OFCAL1
OFCAL2
FSCAL0
FSCAL1
FSCAL2
I_MUX
OFC[7:0]
08h
OFC[15:8]
OFC[23:16]
FSC[7:0]
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
FSC[15:8]
FSC[23:16]
I_MUX2[3:0]
I_MAG2[3:0]
I_MUX1[3:0]
I_MAG1[3:0]
I_MAG
RESERVED
MODE4
STATUS1
STATUS2
00h
0
PGA_ONL
0
MUX[2:0]
PGA_OPL
LOCK2
GAIN[3:0]
11h
PGA_ONH
0
PGA_OPH
CRC2
PGA_INL
PGA_INH
PGA_IPL
PGA_IPH
12h
0xh
REV_ID2[3:0]
表 29 lists the access codes for the ADS125H02 registers.
表 29. ADS125H02 Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
R/W
R-W
Read or write
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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9.6.1 Device Identification (ID) Register (address = 00h) [reset = 6xh]
ID is shown in 图 82 and described in 表 30.
Return to Register Map Summary.
图 82. ID Register(1)
7
6
5
4
3
2
1
0
DEV_ID[3:0]
R-6h
REV_ID1[3:0]
R-xh
(1) Reset values are device dependent.
表 30. ID Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID
7:4
DEV_ID[3:0]
R
6h
0110 = ADS125H02
Revision ID1
3:0
REV_ID1[3:0]
R
xh
There are two revision ID fields: REV_ID1 and REV_ID2. The
revision IDs can change without notification.
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9.6.2 Main Status (STATUS0) Register (address = 01h) [reset = 01h]
STATUS0 is shown in 图 83 and described in 表 31.
Return to Register Map Summary.
图 83. STATUS0 Register
7
6
5
0
4
3
2
1
0
LOCK1
R-0h
CRC1
R/W-0h
STAT12
R-0h
REFALM
R-0h
DRDY
R-0h
CLOCK
R-xh
RESET
R/W-1h
R-0h
表 31. STATUS0 Register Field Descriptions
Bit
Field
Type
Reset
Description
Register Write Lock1 Status
Indicates the register write lock status of register addresses 00h
to 0Fh. See the LOCK Command section for details.
7
LOCK1
R
0h
0: Registers 00h to 0Fh are not locked (default)
1: Registers 00h to 0Fh are locked
See the STATUS2 register for the register lock status of register
addresses 10h to 12h.
CRC1 Error
Indicates if a CRC error occurred during commands when CS1
is active. Write 0 to clear the CRC error.
6
CRC1
R/W
0h
0: No CRC error during commands using CS1
1: CRC error occurred during commands using CS1
See the STATUS2 register for the CRC error status for
commands using CS2.
Reserved
5
4
0
R
R
0h
0h
Always write 0.
STAT12 Error Flag
Indicates one or more error events have been logged in the
STATUS1 or STATUS2 registers. Read the STATUS1 and
STATUS2 registers to determine the error. This bit clears after
all errors are cleared.
STAT12
0: No error
1: Error logged to the STATUS1 or STATUS2 registers
Reference Voltage Alarm
This bit sets when the reference voltage falls below < 0.4 V
(typical). The alarm updates at each new conversion cycle (auto-
reset).
3
REFALM
R
0h
0: No reference low alarm
1: Reference low alarm
Data Ready
Indicates new conversion data.
2
1
DRDY
R
R
0h
xh
0: Conversion data are not new since the last data read
1: Conversion data are new since the last data read
Clock
Indicates internal or external clock mode. The ADC automatically
selects the clock mode.
CLOCK
0: ADC clock is internal
1: ADC clock is external
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表 31. STATUS0 Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
Reset
Indicates an ADC reset has occurred. Clear the bit to detect the
next device reset.
0
RESET
R/W
1h
0: No reset
1: Reset (default)
9.6.3 Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
MODE0 is shown in 图 84 and described in 表 32.
Return to Register Map Summary.
图 84. MODE0 Register
7
6
5
4
3
2
1
0
DR[4:0]
R/W-4h
FILTER[2:0]
R/W-4h
表 32. MODE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
Data Rate
These bits select the data rate.
00000: 2.5 SPS
00001: 5 SPS
00010: 10 SPS
00011: 16.6 SPS
00100: 20 SPS (default)
00101: 50 SPS
00110: 60 SPS
7:3
DR[4:0]
R/W
4h
00111: 100 SPS
01000: 400 SPS
01001: 1200 SPS
01010: 2400 SPS
01011: 4800 SPS
01100: 7200 SPS
01101: 14400 SPS
01110: 19200 SPS
01111: 25600 SPS
10000 - 11111: 40 kSPS (fCLK = 10.24 MHz)
Digital Filter (see the Digital Filter section)
These bits select the digital filter mode.
000: Sinc1
001: Sinc2
2:0
FILTER[2:0]
R/W
4h
010: Sinc3
011: Sinc4
100: FIR (default)
101-111: Reserved
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9.6.4 Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
MODE1 is shown in 图 85 and described in 表 33.
Return to Register Map Summary.
图 85. MODE1 Register
7
0
6
0
5
4
3
2
1
0
AUTOZERO
R/W-0h
CONVRT
R/W-0h
DELAY[3:0]
R/W-1h
R/W-0h
R/W-0h
表 33. MODE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7:6
0
R/W
0h
Always write 0
Auto-Zero Mode
Select normal or auto-zero operating mods. See the Auto-Zero
Mode section.
5
4
AUTOZERO
CONVRT
R/W
R/W
0h
0h
0: Normal mode (default)
1: Auto-zero mode
Conversion Mode
Select the ADC conversion mode. See the Conversion Control
section.
0: Continuous conversion mode (default)
1: Pulse (one shot) conversion mode
Conversion Start Delay
Program the time delay at the start of conversion. See the Start-
Conversion Delay section.
0000: 0 µs (not for 25600-SPS or 40000-SPS operation)
0001: 50 µs (default)
0010: 59 µs
0011: 67 µs
0100: 85 µs
0101: 119 µs
3:0
DELAY[3:0]
R/W
1h
0110: 189 µs
0111: 328 µs
1000: 605 µs
1001: 1.16 ms
1010: 2.27 ms
1011: 4.49 ms
1100: 8.93 ms
1101: 17.8 ms
1110-1111: Reserved
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9.6.5 Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
MODE2 is shown in 图 86 and described in 表 34.
Return to Register Map Summary.
图 86. MODE2 Register
7
6
5
4
3
2
1
0
GPIO_CON[3:0]
R/W-0h
GPIO_DIR[3:0]
R/W-0h
表 34. MODE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
GPIO[3] Pin Connection
Connect GPIO[3] to the GPIO3 pin.
7
GPIO_CON[3]
GPIO_CON[2]
GPIO_CON[1]
GPIO_CON[0]
GPIO_DIR[3]
GPIO_DIR[2]
R/W
0h
0: GPIO[3] not connected to GPIO3 (default)
1: GPIO[3] connected to GPIO3
GPIO[2] Pin Connection
Connect GPIO[2] to the GPIO2 pin.
0: GPIO[2] not connected to GPIO2 (default)
1: GPIO[2] connected to GPIO2
6
5
4
3
2
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
GPIO[1] Pin Connection
Connect GPIO[1] to the REFN1/GPIO1 pin.
0: GPIO[1] not connected to REFN1/GPIO1 (default)
1: GPIO[1] connected to REFN1/GPIO1
GPIO[0] Pin Connection
Connect GPIO[0] to the REFP1/GPIO0 pin.
0: GPIO[0] not connected to REFP1/GPIO0 (default)
1: GPIO[0] connected to REFP1/GPIO0
GPIO[3] Pin Direction
Configure GPIO[3] as a GPIO input or output to the GPIO3 pin.
0: GPIO[3] is an output (default)
1: GPIO[3] is an input
GPIO[2] Pin Direction
Configure GPIO[2] as a GPIO input or output to the GPIO2 pin.
0: GPIO[2] is an output (default)
1: GPIO[2] is an input
GPIO[1] Pin Direction
Configure GPIO[1] as a GPIO input or output to the REFN1/
GPIO1 pin.
1
0
GPIO_DIR[1]
GPIO_DIR[0]
R/W
R/W
0h
0h
0: GPIO[1] is an output (default)
1: GPIO[1] is an input
GPIO[0] Pin Direction
Configure GPIO[0] as
REFP1/GPIO0 pin.
a GPIO input or output to the
0: GPIO[0] is an output (default)
1: GPIO[0] is an input
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9.6.6 Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
MODE3 is shown in 图 87 and described in 表 35.
Return to Register Map Summary.
图 87. MODE3 Register
7
0
6
5
0
4
0
3
2
1
0
STATENB
R/W-0h
GPIO_DAT[3:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表 35. MODE3 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7
0
R/W
0h
Always write 0h.
STATUS0 Byte Enable
Enable the STATUS0 byte contents for inclusion during
conversion data read operation.
6
STATENB
R/W
0h
0: Exclude STATUS0 byte during conversion data read (default)
1: Include STATUS0 byte during conversion data read
Reserved
5:4
3
0
R/W
R/W
0h
0h
Always write 0h.
GPIO[3] Data
Read or write the GPIO data on the GPIO3 pin.
0: GPIO[3] is low (default)
1: GPIO[3] is high
GPIO_DAT[3]
GPIO[2] Data
Read or write the GPIO data on the GPIO2 pin.
0: GPIO[2] is low (default)
1: GPIO[2] is high
2
1
0
GPIO_DAT[2]
GPIO_DAT[1]
GPIO_DAT[0]
R/W
R/W
R/W
0h
0h
0h
GPIO[1] Data
Read or write the GPIO data on the REFN1/GPIO1 pin.
0: GPIO[1] is low (default)
1: GPIO[1] is high
GPIO[0] Data
Read or write the GPIO data on the REFP1/GPIO0 pin.
0: GPIO[0] is low (default)
1: GPIO[0] is high
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9.6.7 Reference Configuration (REF) Register (address = 06h) [reset = 05h]
REF is shown in 图 88 and described in 表 36.
Return to Register Map Summary.
图 88. REF Register
7
0
6
0
5
0
4
3
2
1
0
REFENB
R/W-0h
RMUXP[1:0]
R/W-1h
RMUXN[1:0]
R/W-1h
R/W-0h
R/W-0h
R/W-0h
表 36. REF Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7:5
0
R/W
0h
Always write 0h.
Internal Reference Enable
Enable the internal reference.
0: Internal reference disabled (default)
1: Internal reference enabled
4
REFENB
R/W
R/W
0h
1h
Reference Positive Input (see the Reference Voltage section)
Select the positive reference input.
00: Internal reference positive
01: AVDD (default)
3:2
RMUXP[1:0]
RMUXN[1:0]
10: REFP0 external
11: REFP1/GPIO0 external
Reference Negative Input (see the Reference Voltage section)
Select the negative reference input.
00: Internal reference negative
01: AGND (default)
1:0
R/W
1h
10: REFN0 external
11: REFN1/GPIO1 external
60
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9.6.8 Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
OFCALx is shown in 图 89 and described in 表 37.
Return to Register Map Summary.
图 89. OFCAL0, OFCAL1, OFCAL2 Registers
7
6
5
4
3
2
1
9
0
8
OFC[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
OFC[15:8]
R/W-00h
17
16
OFC[23:16]
R/W-00h
表 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
Bit
Field
Type
Reset
Description
Offset Calibration
These three registers are the 24-bit offset calibration word. The
offset calibration is in two's-complement data format. The offset
value is subtracted from the conversion result before the full-
scale operation.
23:0
OFC[23:0]
R/W
000000h
9.6.9 Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
FSCALx is shown in 图 90 and described in 表 38.
Return to Register Map Summary.
图 90. FSCAL0, FSCAL1, FSCAL2 Registers
7
6
5
4
3
2
1
9
0
8
FSCAL[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
FSCAL[15:8]
R/W-00h
17
16
FSCAL[23:16]
R/W-40h
表 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
Bit
Field
Type
Reset
Description
Full-Scale Calibration
These three registers are the 24-bit full-scale calibration word.
The full-scale calibration is in straight binary data format. The
full-scale value is divided by 400000h and multiplied with the
conversion data. The scaling operation occurs after the offset
operation.
23:0
FSCAL[23:0]
R/W
400000h
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9.6.10 Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
I_MUX is shown in 图 91 and described in 表 39.
Return to Register Map Summary.
图 91. I_MUX Register
7
6
5
4
3
2
1
0
I_MUX2[3:0]
R/W-Fh
I_MUX1[3:0]
R/W-Fh
表 39. I_MUX Register Field Descriptions
Bit
Field
Type
Reset
Description
Current Source 2 Output Multiplexer
These bits select the IDAC2 pin connection.
0000-0111: No connection
7:4
I_MUX2[3:0]
I_MUX1[3:0]
R/W
Fh
1000: Connect current source 2 to pin IDAC1
1001: Connect current source 2 to pin IDAC2
1010-1111: No connection (default = 1111)
Current Source 1 Output Multiplexer
These bits select the IDAC1 pin connection.
0000-0111: No connection
3:0
R/W
Fh
1000: Connect current 1 to pin IDAC1
1001: Connect current 1 to pin IDAC2
1010-1111: No connection (default = 1111)
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9.6.11 Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
I_MAG is shown in 图 92 and described in 表 40.
Return to Register Map Summary.
图 92. I_MAG Register
7
6
5
4
3
2
1
0
I_MAG2[3:0]
R/W-0h
I_MAG1[3:0]
R/W-0h
表 40. I_MAG Register Field Descriptions
Bit
Field
Type
Reset
Description
Current Source 2 Magnitude
These bits select current source 2 magnitude.
0000: Off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
7:4
I_MAG2[3:0]
R/W
0h
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011-1111: Off
Current Source 1 Magnitude
These bits select current source 1 magnitude.
0000: Off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
3:0
I_MAG1[3:0]
R/W
0h
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011-1111: Off
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9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
RESERVED is shown in 图 93 and described in 表 41.
Return to Register Map Summary.
图 93. RESERVED Register
7
6
5
4
3
2
1
0
00h
R/W-00h
表 41. RESERVED Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved bits
7:0
0
R
0h
Always write 00h.
9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
MODE4 is shown in 图 94 and described in 表 42.
Return to Register Map Summary.
图 94. MODE4 Register
7
0
6
5
4
3
2
1
0
MUX[2:0]
R/W-5h
GAIN[3:0]
R/W-0h
R/W-0h
表 42. MODE4 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7
0
R
0h
Always write 0h.
Input Multiplexer
These bits set the input multiplexer control.
000: AIN1 – AIN0
001: AIN0 – AIN1
010: AIN1 – AINCOM
6:4
MUX[2:0]
R/W
5h
011: AIN0 – AINCOM
100: HV supply readback (HV_AVDD – HV_AVSS) / 36
101: Internal short to VCOM (HV_AVDD + HV_AVSS) / 2 (default)
110: Temperature sensor reading
111: Reserved (do not use)
64
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表 42. MODE4 Register Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
PGA Gain
These bits set the PGA gain setting.
0000: 0.125 (default)
0001: 0.1875
0010: 0.25
0011: 0.5
0100: 1
3:0
GAIN[3:0]
R/W
0h
0101: 2
0110: 4
0111: 8
1000: 16
1001: 32
1010: 64
1011: 128
1100-1111: reserved
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9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
STATUS1 is shown in 图 95 and described in 表 43.
Return to Register Map Summary.
图 95. STATUS1 Register
7
6
5
4
3
2
1
0
PGA_ONL
PGA_ONH
PGA_OPL
PGA_OPH
PGA_INL
PGA_INH
PGA_IPL
PGA_IPH
R-xxh
表 43. STATUS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
PGA Output Negative Low Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
7
PGA_ONL
R
xh
1: Alarm active
PGA Output Negative High Alarm
This bit is cleared on register read (clear-on-read).
6
5
4
3
2
1
0
PGA_ONH
PGA_OPL
PGA_OPH
PGA_INL
PGA_INH
PGA_IPL
PGA_IPH
R
R
R
R
R
R
R
xh
xh
xh
xh
xh
xh
xh
0: No alarm
1: Alarm active
PGA Output Positive Low Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
PGA Output Positive High Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
PGA Input Negative Low Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
PGA Input Negative High Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
PGA Input Positive Low Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
PGA Input Positive High Alarm
This bit is cleared on register read (clear-on-read).
0: No alarm
1: Alarm active
66
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9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
STATUS2 is shown in 图 96 and described in 表 44.
Return to Register Map Summary.
图 96. STATUS2 Register
7
0
6
0
5
4
3
2
1
0
LOCK2
R-0h
CRC2
R/W-0h
REV_ID2[3:0]
R/W-xh
R/W-0h
R/W-0h
表 44. STATUS2 Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
7:6
0
R/W
0h
Always write 0.
Register Write Lock2 Status
Indicates the register write lock status of registers 10h to 12h.
See the LOCK Command section for details.
5
LOCK2
R
0h
0: Registers 10h to 12h are not locked (default)
1: Registers 10h to 12h are locked
See the STATUS2 register for the register write lock status of
registers 00h to 0fh.
CRC2 Error
Indicates if a CRC error occurred during commands with CS2.
The CRC error is latched until cleared by the user. Write 0 to
clear the error.
4
CRC2
R/W
0h
x
0: No CRC error during commands with CS2
1: CRC error occurred during commands with CS2
Revision ID2
3:0
REV_ID2[3:0]
R
Revision ID 2 field. The revision ID1 and ID2 can change without
notification.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Input Range
Linear operation of the PGA requires that the absolute input voltage does not exceed the specified range. The
following example shows how to verify the absolute input voltage is within the valid range. In this example, the
input signal is ±10 V with an arbitrary 15% overrange capability. The negative input lead of the sensor is
connected to AGND. The ADC gain is 0.1875 using a 2.5-V reference voltage and ±15-V power supplies with 5%
voltage tolerance. The summary of conditions to verify the ADC range are:
•
•
•
•
•
•
•
V(AINx_MAX) = 11.5 V
V(AINx_MIN) = –11.5 V
V(AINCOM) = AGND
HV_AVDD = 14.25 V
HV_AVSS = –14.25 V
Gain = 0.1875
VREF = 2.5 V
The evaluation of 公式 5 (for gain < 1) results in:
–11.75 V < –11.5 V and 11.5 V < 11.75 V
The inequality is satisfied, and as a result, the absolute input voltage is within the ADC input range requirement.
10.1.2 Input Overload
The input overvoltage precautions as described in the ESD Diodes section. If an overvoltage condition occurs on
an unused channel, the overvoltage channel may crosstalk to the measurement channel. One solution, as shown
in 图 97, is to externally clamp the inputs with low-forward voltage diodes. The external diodes shunt the
overvoltage current flow around the ADC inputs. Be aware of the reverse leakage current that can cause
measurement errors.
+15 V
IFAULT
Schottky
Diode
HV_AVDD
Zener
Diode
RLIM
AINx
ADS125H02
40 V
Schottky
Diode
HV_AVSS œ 0.3 V > VCLAMP > HV_AVDD + 0.3 V
HV_AVSS
IFAULT
-15 V
图 97. Optional Diode Clamps
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Application Information (接下页)
10.1.2.1 Input Signal Rate of Change (dV/dt)
A high dV/dt signal at the ADC input can lead to transient turn-on of the PGA inverse-parallel protection diodes
(see 图 57 for details). Turn-on of the PGA diodes can result in current flow in the analog inputs that can cause a
disturbance in the measurement channel. For example, a high dV/dt voltage can be generated at the output of a
signal multiplexer after a channel selection, leading to a possible flow of transient currents through the ADC
inputs. Filter the ADC input voltage to limit the rate of voltage change (dV/dt).
10.1.3 Unused Inputs and Outputs
•
•
•
Analog Inputs
To minimize input current leakage, connect unused analog inputs to AGND when operating the device with
bipolar supplies, or connect unused inputs to AVDD when operating the device with a unipolar supply.
Analog Outputs
A capacitor is not required for REFOUT if the internal reference or the IDAC current sources are not used.
Otherwise, connect a 10-µF capacitor between REFOUT and AGND.
Digital I/O
ADC operation is possible using only a subset of the digital I/O. Tie any unused digital inputs high or low
(DVDD or DGND, as appropriate). Do not float (tri-state) the digital inputs or unpredictable operation can
result. The following is a summary of digital I/O with optional connections:
•
•
•
•
CLKIN: Tie CLKIN to DGND to operate the ADC using the internal oscillator. The internal oscillator stops
operation if CLKIN is connected to DVDD, resulting in loss of ADC functionality. Connect CLKIN to an
external clock source to operate with an external clock.
START: Tie START low in order to control conversions entirely by command. Tie START high to free-run
conversions when programmed to the continuous-conversion mode. Connect START to the host controller
to control conversions directly by the pin.
RESET: Tie RESET high if desired. An external RC reset on the RESET input pin is not necessary
because the ADC resets at power on. The ADC can also be reset by the RESET command. Connect the
RESET pin to the host controller to reset the ADC by hardware.
DRDY: Indication of data ready is also provided by the DOUT/DRDY pin. CS1 must be low to use
DOUT/DRDY in the data-ready function. The indication of data ready is also achieved by polling the
DRDY bit of the STATUS0 byte. For these methods, the connection of DRDY to the host controller is not
necessary and the pin can be unconnected.
•
GPIO
Program unused GPIOs as outputs (default setting). If any GPIOs are programmed as inputs, the GPIO must
not be allowed to float (unconnected), otherwise AVDD power-supply leakage current may result.
10.2 Typical Applications
10.2.1 ±10-V Analog Input Module
图 98 illustrates an example of the ADS125H02 used in a ±10-V analog input programmable logic controller
(PLC) module. The inputs of the ADC are protected by external ESD diodes to provide system-level protection. A
100-MΩ resistor is used to pull the positive analog input to 15 V if the field-wiring connection is open or the
transmitter has failed in open-circuit mode.
The signal from the transmitter is filtered to remove EMI and RFI interference when operated in noisy
environments. The resistor also acts to limit the input current in the event of an input overvoltage, including if the
module loses power with the signal present. The negative input signal is connected to AIN0, which is also
connected to AGND. Connection to AGND is necessary if the sensor power supply is not referenced to the ADC
ground.
The ADC measures the differential voltage between inputs AIN1 and AIN0. The input configuration is single-
ended with the input voltage driven ±10 V relative to AIN0 (AGND).
Operation by internal reference requires a 10-µF capacitor connected to the REFOUT pin. Otherwise, apply the
external reference voltage to REFP0 and REFN0. A 100-kΩ resistor biases the differential reference voltage to
0 V. The resistor provides the bias to allow the reference monitor to detect a failed or missing reference voltage
that otherwise may be unnoticed.
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Typical Applications (接下页)
Because the excitation current sources and GPIOs are not used they are left unconnected.
The internal oscillator is selected by connecting the CLKIN input pin to ground. The serial interface and digital
control lines of the ADC are connected to the host.
The zener diode clamps the high-voltage supply (HV_AVDD – HV_AVSS) to 40 V to provide overvoltage
protection if an input signal is present with module power off.
15 V
-15 V
40 V
0.1 mF
0.1 mF
1 mF
19
20
15 V
HV_AVDD
HV_AVSS
5 V
ADS125H02
100 Mꢀ
5 kꢀ
4
2
27
26
AVDD
AIN1
AIN0
10 mF
0.1 mF
10 V
Input
10 nF
ESD
Protection
CAPP
25
1
AINCOM
1 nF
C0G
3
6
CAPN
2.5 V
Reference
5 V
REFP0
REFN0
10 nF
100 kΩ
REFOUT
10 mF
32
Optional
7
RESET
START
CS2
24
23
31
30
29
8
9
IDAC1
IDAC2
10
11
CS1
To Host control
REFP1/GPIO0
REFN1/GPIO1
GPIO2
47 ꢀ
SCLK
47 ꢀ
47 ꢀ
47 ꢀ
12
13
DIN
DRDY
28
22
GPIO3
NC
14
18
DOUT/DRDY
CLKIN
21
15
NC
5 V
17
BYPASS
DVDD
DGND
1 mF
1 mF
AGND
5
16
图 98. ±10-V Analog Input PLC Module
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Typical Applications (接下页)
10.2.1.1 Design Requirements
表 45 shows the design goals of the analog input PLC module. The ADC programmability allows various
tradeoffs of sample rate, conversion noise, and conversion latency. 表 46 shows the design parameters of the
analog input PLC module.
表 45. Design Goals
DESIGN GOAL
Accuracy
VALUE
±0.1%
Temperature range (internal module)
Acquisition period
0°C to +105°C
50 µs
Effective resolution
18 bits
表 46. Design Parameters
DESIGN PARAMETER
Nominal signal range
Extended range
VALUE
±10 V
±12 V
Input impedance
100 MΩ
±35 V
Overvoltage rating
10.2.1.2 Detailed Design Procedure
A key consideration in the design of an analog input module is the error over the ambient temperature range
resulting from the drift of gain, offset, reference voltage, and linearity error. This example assumes the initial
offset and gain (including reference voltage error) are user calibrated at TA = 25°C. 表 47 shows the maximum
drift error of the ADC over the 0°C to +105°C temperature range.
表 47. ADC Drift Error
PARAMETER
ERROR (0°C TO +105°C)
0.00125%
0.032%
Offset drift error
Gain drift error
Linearity error (over temperature)
0.001%
ADS125H02 internal reference
0.16%
Reference drift error
Total drift error
REF5025IDGK external reference
ADS125H02 internal reference
REF5025IDGK external reference
0.024%
0.19425%
0.05825%
As shown in 表 47, the largest error is from the internal voltage reference. The reference drift error is improved
by using the REF5025IDGK external reference. Using the external reference, the total drift error is 0.05825%,
which satisfies the 0.1% total error design goal.
The ADC gain is programmed to 0.1875. With a 2.5-V reference voltage, the ADC input range is ±2.5 V / 0.1875
= ±13.3 V. However, using ±15-V power supplies, the required headroom of the PGA limits the range to ±12.5 V
(which excludes the tolerance of the ±15-V power supplies). The input range satisfies the extended range design
target of ±12 V.
The 1-GΩ minimum input impedance of the ADC and the 100-MΩ external pullup resistor meets the input
impedance goal of 100 MΩ. The input fault overvoltage requirement (35 V) is met by limiting the ADC input
current to 10 mA. The external 5-kΩ input resistor limits the input current to 7 mA.
The data rate that meets the continuos conversion, 50-µs acquisition period is 25600 SPS (39 µs actual). If a
precise 50-µs conversion period is desired, reduce the clock frequency to the ADC with an external clock source.
The clock frequency that yields a 50-µs conversion period is 5.76 MHz.
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表 1 lists noise performance data under all combinations of gain, sample rate, and digital filter order. The
specified conversion noise for the ADC configuration in this example is 100 µVRMS. The effective resolution is
derived by 公式 1, and calculates to: 3.32 log (26.6 V / 100 µV) = 18 bits.
10.2.1.3 Application Curves
图 99 shows 100,000 consecutive conversions over a four-second interval with the ADC inputs shorted using the
ADC configuration given in this example. 100,000 conversions demonstrate the consistency of the ADC
conversion results over time. The conversion noise in this example is 107 µVRMS. The effective resolution
calculates to 18 bits, which meets the design requirement.
800
en = 107 mV RMS
en = 865 mV PP
600
400
200
0
-200
-400
-600
-800
0
1
2
Time (s)
3
4
D007
图 99. Conversion Noise
10.2.2 Thermocouple Input With High Common-Mode Voltage
The low noise and low drift performance, 50-Hz and 60-Hz noise rejection, and high common-mode voltage
range of the ADS125H02 make the device suitable for multiple thermocouple inputs that have varying levels of
common-mode voltage. The common-mode voltage can be AC (50-Hz or 60-Hz noise pickup) or DC caused by
varying ground potentials encountered in industrial machinery. 图 100 shows a simplified application of an 8-
input, isolated ground, thermocouple module using an external 8:1 differential input multiplexer. The GPIO of the
ADS125H02 drives the mux select pins.
18 V
18 V
R1
18 V
R3
R4
R5
R6
C1
AIN0
AIN1
ADS125H02
C2
ESD
Protection
R2
8:1
Differential
Mux
GPIO[3:0]
-18 V
-18 V
CJC
Temp Sensor
EN
A0
A1
A2
CH 2
R7
CH 8
GND
-18 V
图 100. Thermocouple Input
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10.3 Initialization Setup
图 101 shows a general configuration and measurement procedure.
Power On
/* RESET must be high for operation
Set RESET high
Y
External clock?
N
Apply clock to CLKIN
/* ADC automatically detects external clock
N
/* DRDY is held low at power-on until ready for communication
DRDY pin high?
Y
Y
START high?
/* If START pin is low, conversions are stopped
DRDY pulses at 20 Hz
N
Set START pin low /
Send STOP command
/* For simplicity, stop conversions before register configuration
DRDY not pulsing
/* Write register data with CRC validation byte attached
/* (Use CS1 for register addresses ≤ 0Eh)
/* (Use CS2 for register addresses ≥ 10h)
Write register data
Read register data
/* Optional readback validation of register data
Wait for reference
voltage to settle
/* The internal reference requires time to settle after power-on
Set START pin high /
Send START command
/* Start or restart new ADC conversion
N
/* Read data at a rate faster than
the data rate to avoid missed data
Hardware DRDY?
Y
Read STATUS0 register
N
/* New data when DRDY bit =1
DRDY bit asserted ?
N
DRDY pin low ?
Y
Y
Read Data
N
Change ADC
settings ?
Y
图 101. ADC Configuration and Measurement Procedure
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11 Power Supply Recommendations
The ADC requires three analog power supplies (high-voltage supplies HV_AVDD and HV_AVSS, and low-
voltage AVDD) and a digital power supply (DVDD). The high-voltage analog power-supply configuration is either
bipolar (±5 V to ±18 V) or unipolar (10 V to 36 V). The AVDD power supply is 5 V. The digital supply range is
2.7 V to 5.25 V. AVDD and DVDD can be tied together as long as the 5-V power supply is free from noise and
glitches that can affect conversion results. An internal low-dropout regulator (LDO) powers the digital core from
the DVDD power supply. DVDD is the digital I/O voltage. Keep in mind that the GPIOs are referenced to AVDD
and AGND voltage potentials.
Voltage ripple produced by switch-mode power supplies can interfere with the ADC conversion accuracy. Use
LDOs at the switching regulator output to reduce power-supply ripple.
Inrush current is drawn from AVDD when the internal reference is enabled as a result of charging the 10-µF
REFOUT capacitor. Observe the AVDD voltage under this condition and verify the supply does not drop below
4.5 V.
11.1 Power-Supply Decoupling
Good power-supply decoupling is important in order to achieve optimum performance. Power supplies must be
decoupled close to the device supply pins. For the high voltage analog supply (HV_AVDD and HV_AVSS), place
a 1-µF capacitor between the pins and place 0.1-µF capacitors from each supply to the ground plane. Connect
0.1-µF and 10-µF capacitors in parallel at AVDD to the ground plane. Connect a 1-µF capacitor from DVDD to
the ground plane. Connect a 1-µF capacitor from BYPASS to the ground plane. Use multilayer ceramic chip
capacitors (MLCCs) that offer low equivalent series resistance (ESR) and equivalent series inductance (ESL)
characteristics for power-supply decoupling purposes.
11.2 Analog Power-Supply Clamp
Circumstances must be evaluated when an input signal is present when the ADC is unpowered. When the input
signal exceeds the forward voltage of the ESD diodes, the diodes conduct resulting in backdrive of the analog
power-supply voltage through the internal ESD diodes. Backdriving the ADC power supply can also occur when
the power-supply is on. The backdrive fault-current path is illustrated in 图 97. Depending on the power supply
response during a backdrive condition, the ADC supply voltage rating may be exceeded. The ADC maximum-
rated supply voltage must not be exceeded under any condition. One solution is to clamp the analog supply
using a Zener diode placed across HV_AVSS and HV_AVDD.
11.3 Power-Supply Sequencing
The power supplies can be sequenced in any order, but do not allow analog or digital voltage inputs to exceed
the respective analog or digital power supplies without limiting the input current.
11.4 5-V to ±15-V DC-DC Converter
图 102 illustrates a 5-V to ±15-V DC/DC converter for use with the device. The DC/DC converter generates ±15-
V supply voltages from 5-V power. The SN6505B is a push-pull driver that drives the transformer primary from 5-
V power. The typical switching frequency of the driver is 424 kHz, and when combined with the driver spread-
spectrum clocking operation, reduces interference to the ADC as well as system-level EMI emissions. The
secondary voltage of the 2:1 step-up transformer is half-wave rectified in a configuration that quadruples the 5-V
primary voltage to generate output voltages of 20 V and –20 V. The rectified voltages are regulated by the
TPS7A39 high-PSRR, dual positive and negative regulator to provide the ±15-V supply voltages.
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5-V to ±15-V DC-DC Converter (接下页)
15 V
-15 V
40 V
0.1 mF
0.1 mF
5 V
Wurth Electronik
50 V
1 µF
#760390015
19
20
3
1
2
5
4
5
6
MBR0580
D1
VCC
HV_AVDD
HV_AVSS
TPS7A3901
10
1
2
5 V
INP
EN
2
1
SN6505B
ADS125H02
OUTP
50 V
10 mF
4
118 kꢀ
3
4
50 V
10 mF
AVDD
10 mF
EN
D2
10 kꢀ
0.1 mF
9
FBP
10 mF
5
3
INN
15
6
BYPASS
OUTN
6
GND
CLK
1 mF
50 V
10 mF
50 V
10 mF
127 kꢀ
5 V
7
17
FBN
BUF
DVDD
NR/NS
10 kꢀ
1 mF
8
0.01 mF
GND PAD
DGND
16
AGND
5
4
11
图 102. 5-V to ±15-V DC/DC Converter
12 Layout
12.1 Layout Guidelines
Good layout practices are crucial to realize the full performance of the ADC. Poor grounding can quickly degrade
the noise performance. This section discusses layout recommendations that help provide the best results.
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on layout restrictions, a dedicated ground plane may not be practical. If
ground plane separation is necessary, make a single, direct connection to the planes at the ADC. Do not connect
individual ground planes at multiple locations because this configuration creates ground loops.
Route digital traces away from the CAPP and CAPN pins, away from the REFOUT pin, and away from all analog
inputs and associated components in order to minimize interference.
Because large capacitance on DOUT/DRDY can lead to increased ADC noise levels, minimize the length of the
PCB trace. Use a series resistor or a buffer if long traces are used.
The internal reference output return is the AGND pin. To minimize coupling between the power supply and
reference-return trace, route the traces separately; ideally, as a star connection to the AGND pin.
Use C0G capacitors on the analog inputs and for the CAPP to CAPN capacitor. Use ceramic capacitors (for
example, X7R grade) for the power-supply decoupling capacitors. High-K capacitors (Y5V) are not
recommended. The REFOUT pin requires a 10-µF capacitor and can be either ceramic or tantalum type. Place
the required capacitors as close as possible to the device pins using short, direct traces. For optimum
performance, use low-impedance connections with multiple vias on the ground-side connections of the bypass
capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination
resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to
noisy conversion data.
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12.2 Layout Example
图 103 shows an example layout of the ADS125H02, requiring a minimum of three PCB layers. The example
circuit is shown with bipolar supply operation (such as ±15 V) and using the internal reference. In this example,
the inner layer is dedicated to the ground plane and the outer layers are used for signal and power traces. If a
four-layer PCB is used, dedicate an additional inner layer for the power planes. In this example, the ADC is
oriented in such a way to minimize crossover of the analog and digital signal traces.
ADC Clock Options:
Option 1: To enable INTERNAL
oscillator, tie CLKIN to
GND
HV_AVSS
Supply
Option 2: Connect EXTERNAL
clock source to CLKIN
47 ꢀ
0.1 µF
0.1 µF
DVDD
Supply
1 µF
1 µF
HV_AVDD
Supply
(9-mil traces shown)
Current
Source
1 µF
Input
Signal
10 nF
16
15
AINCOM 25
DGND
AIN0 26
(Diff. - Input Pair)
BYPASS
14 DOUT/DRDY
AIN1 27
GPIO3 28
GPIO2 29
ADS125H02
DRDY
DIN
13
12
11
10
9
47 ꢀ
47 ꢀ
47 ꢀ
47 ꢀ
Connect thermal pad to
AGND
30
SCLK
CS1
REFN1/GPIO1
REFP1/GPIO0 31
REFN0 32
GPIO
CS2
To
MCU
C0G
External
Reference
0.1 µF
10 nF
1 nF
10 µF
(0805 shown)
10 µF
(0805 shown)
AVDD Supply
图 103. PCB Layout Example
76
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《REF50xx 低噪声、极低漂移、精密电压基准》数据表
德州仪器 (TI)，《用于隔离电源的 SN6505x 低噪声 1A 变压器驱动器》数据表
德州仪器 (TI)，《TPS7A39 双路、150mA、宽输入电压正负 LDO 稳压器》数据表
13.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2018–2019, Texas Instruments Incorporated
77
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
78
版权 © 2018–2019, Texas Instruments Incorporated
ADS125H02
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ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
SYMM
33
3.5
0.3
32X
0.2
24
0.1
C A B
1
0.05
C
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
版权 © 2018–2019, Texas Instruments Incorporated
79
ADS125H02
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
www.ti.com.cn
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
80
版权 © 2018–2019, Texas Instruments Incorporated
ADS125H02
www.ti.com.cn
ZHCSIZ6C –OCTOBER 2018–REVISED JUNE 2019
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
版权 © 2018–2019, Texas Instruments Incorporated
81
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS125H02IRHBR
ADS125H02IRHBT
ACTIVE
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
ADS
125H02
ACTIVE
RHB
NIPDAU
ADS
125H02
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS125H02IRHBR
ADS125H02IRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS125H02IRHBR
ADS125H02IRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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本、损失和债务，TI 对此概不负责。
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
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