ADS1261BIRHBR [TI]
适用于工厂自动化且具有 PGA、VREF、IDAC 和交流激励的 24 位 40kSPS 10 通道 Δ-Σ ADC | RHB | 32 | -40 to 125;
| 型号： | ADS1261BIRHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于工厂自动化且具有 PGA、VREF、IDAC 和交流激励的 24 位 40kSPS 10 通道 Δ-Σ ADC | RHB | 32 | -40 to 125 转换器 |
| 文件： | 总92页 (文件大小：2030K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
ADS126x精密 5 通道和 10 通道 40kSPS 24 位
Δ-Σ ADC
1 特性
3 说明
1
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24 位高精度 ADC
ADS1260 和 ADS1261(ADS126x) 均为包含可编程增
益放大器 (PGA) 的精密 40kSPS ΔΣ 模数转换器
(ADC)。这些器件还包含精密的电压基准和内部故障监
控器。这些支持传感器的 ADC 可以为要求最严苛的测
量（包括称重秤和电阻式温度检测器 (RTD)）提供高
精度单芯片解决方案。
–
–
–
–
温漂：1nV/°C
增益漂移：0.5ppm/°C
噪声：30nVRMS（20SPS，增益 = 128）
线性度：2ppm
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CMOS PGA 增益：1 至 128
宽输入电压范围：±7mV 至 ±5V
数据速率：2.5SPS 至 40kSPS
2.5V 基准：2ppm/°C
这些 ADC 包含输入信号多路复用器、低噪声 PGA
（提供 1 至 128 的增益）、4 位 ΔΣ 调制器、精密电
压基准和可编程数字滤波器。
同步 50Hz 和 60Hz 抑制模式
单周期稳定模式
高阻抗 PGA 输入 (1GΩ) 可减小由传感器负载导致的
测量误差。ADS1260 支持三路差分输入或五路单端输
入。ADS1261 支持五路差分输入或十路单端输入。集
成式电流源可简化 RTD 测量。
信号和基准监控器
5V 或 ±2.5V 电源
内部温度传感器
循环冗余校验 (CRC)
灵活的数字滤波器可针对单周期稳定转换进行编程，同
时能够提供同步 50Hz 和 60Hz 线路周期抑制。信号和
基准监控器、温度传感器和 CRC 数据验证可增强数据
可靠性。
激励电流源
传感器烧毁电流源
四路通用输入/输出 (ADS1261)
用于桥式传感器的交流激励 (ADS1261)
5mm × 5mm VQFN 封装
ADS126x 是引脚兼容的器件，采用 5mm × 5mm
VQFN 封装，额定工作温度范围为 –40°C 至 +125°
C。
2 应用
器件信息(1)
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PLC 模拟输入模块
器件型号
ADS126x
封装
VQFN (32)
封装尺寸（标称值）
称重秤和应变仪数字转换器
温度、压力测量
实验室仪表
5.0mm × 5.0mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附
录。
过程分析
框图
REFOUT
5 V (A)
2.5-V
Ref
ADS1260
ADS1261
3 V œ 5 V (D)
Ref
Mux
START
RESET
PWDN
DRDY
AIN0
AIN1
Control
Sensor
Excitation
Ref
Monitor
AIN2
Buf
Sensor
Test
AIN3
AIN4
AINCOM
CS
24-Bit
ûꢀ ADC
Digital
Filter
Input
Mux
Serial
Interface
and
PGA
Level Shift
DIN
DOUT/DRDY
SCLK
CRC
Verification
AIN5
AIN6
AIN7
AIN8
AIN9
Signal
Monitor
Temp
Sensor
Internal
Clock
Mux
CLKIN
Oscillator
Supply
Monitor
GPIO
AC-Exc
ADS1261
(A)
(D)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS760
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
目录
9.5 Programming........................................................... 50
9.6 Register Map........................................................... 59
10 Application and Implementation........................ 72
10.1 Application Information.......................................... 72
10.2 Typical Application ................................................ 76
10.3 Initialization Setup................................................. 79
11 Power Supply Recommendations ..................... 80
11.1 Power-Supply Decoupling..................................... 80
11.2 Analog Power-Supply Clamp ................................ 80
11.3 Power-Supply Sequencing.................................... 80
12 Layout................................................................... 81
12.1 Layout Guidelines ................................................. 81
12.2 Layout Example .................................................... 81
13 器件和文档支持 ..................................................... 83
13.1 文档支持................................................................ 83
13.2 相关链接................................................................ 83
13.3 接收文档更新通知 ................................................. 83
13.4 社区资源................................................................ 83
13.5 商标....................................................................... 83
13.6 静电放电警告......................................................... 83
13.7 术语表 ................................................................... 83
14 机械、封装和可订购信息....................................... 84
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information.................................................. 7
7.5 Electrical Characteristics........................................... 8
7.6 Timing Requirements.............................................. 11
7.7 Switching Characteristics........................................ 12
7.8 Typical Characteristics............................................ 15
Parameter Measurement Information ................ 22
8.1 Noise Performance ................................................. 22
Detailed Description ............................................ 26
9.1 Overview ................................................................. 26
9.2 Functional Block Diagram ....................................... 27
9.3 Feature Description................................................. 28
9.4 Device Functional Modes........................................ 43
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4 修订历史记录
Changes from Revision B (October 2018) to Revision C
Page
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已更改 Figure 14, Offset Voltage Long-Term Drift to include 2000-hour data .................................................................... 15
已更改 Figure 31, Voltage Reference Long-Term Drift to include 2000-hour data ............................................................. 17
已更改 CRC polynomial to correct listing error: changed CRC-8-ATM (HEC): X8 + X2 + X0 + 1 to CRC-8-ATM (HEC):
X8 + X2 + X1 + 1.................................................................................................................................................................... 52
Changes from Revision A (May 2018) to Revision B
Page
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已添加 在产品说明书中添加了 ADS1261 器件 ....................................................................................................................... 1
已更改 将 ADS1260 器件从预览更改成了生产数据（有效）.................................................................................................. 1
Added connection options to NC pins .................................................................................................................................... 5
Added differential input current specification for gain = 128 in Electrical Characteristics ..................................................... 8
Added no missing codes specification in Electrical Characteristics ...................................................................................... 8
Changed integral nonlinearity specification for gain 64 and 128 in Electrical Characteristics ............................................... 8
Changed integral nonlinearity specification for 40 kSPS mode in Electrical Characteristics ................................................ 8
Added offset voltage long-term drift in Electrical Characteristics .......................................................................................... 8
Added note for PSRR calculation in Electrical Characteristics ............................................................................................. 8
Changed voltage reference inputs specification in Electrical Characteristics based on updated characteristics .................. 9
Added voltage reference initial error specification for ADS1260B and ADS1261B in Electrical Characteristics .................. 9
Added voltage reference temperature drift specification for ADS1260B and ADS1261B in Electrical Characteristics ........ 9
Added voltage reference long-term drift in Electrical Characteristics .................................................................................... 9
Added voltage reference thermal hysteresis in Electrical Characteristics ............................................................................. 9
Changed th(SCDO2) specification in Switching Characteristics ............................................................................................... 12
Changed tp(SCDO2) specification in Switching Characteristics................................................................................................ 12
2
版权 © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
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已添加 Figure 14, Offset Voltage Long-Term Drift ............................................................................................................... 15
已更改 Figure 24, Conversion Data Histogram (gain = 4) to 8192 data points.................................................................... 16
已更改 Figure 25, Conversion Data Histogram (gain = 128) to 8192 data points ............................................................... 16
已更改 Figure 27, Integral Nonlinearity vs Temperature based on updated characteristics ............................................... 17
已更改 Figure 28, Integral Nonlinearity Distribution to add gain = 128 ............................................................................... 17
已更改 Figure 29, Integral Nonlinearity vs Reference Voltage to add gain = 64 and 128 .................................................. 17
已添加 Figure 30, Voltage Reference vs Temperature for ADS1260B, ADS1261B ........................................................... 17
已添加 Figure 31, Voltage Reference Long-Term Drift ........................................................................................................ 17
已更改 Figure 32, Reference Input Current vs Reference Voltage based on updated characteristics ................................ 17
已添加 Figure 39, CMRR vs Frequency .............................................................................................................................. 19
已添加 Figure 40, PSRR vs Frequency ............................................................................................................................... 19
已添加 text for Table 2, Effective Resolution (Noise-Free Resolution) ................................................................................ 22
已更改 Table 2, Effective Resolution (Noise-Free Resolution) based on updated characteristics ...................................... 24
Changes from Original (March 2018) to Revision A
Page
•
已更改 将 ADS1261 器件从预告信息更改成了生产数据（有效） .......................................................................................... 1
Copyright © 2018–2019, Texas Instruments Incorporated
3
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
5 Device Comparison Table
CHANNELS(1)
PART
GPIO
AC EXCITATION
VOLTAGE REFERENCE GRADE
REFERENCE INPUTS
NUMBER
SINGLE-ENDED
DIFFERENTIAL
ADS1260B(2)
ADS1261B
ADS1261
5
3
5
5
12 ppm/°C max
12 ppm/°C max
40 ppm/°C max
1
2
2
—
4
10
10
4
(1) Reference inputs, GPIOs, and AC-excitation outputs are multiplexed with the analog input channels.
(2) The ADS1260 is available in B grade only.
6 Pin Configuration and Functions
RHB Package: ADS1260
VQFN-32
RHB Package: ADS1261
VQFN-32
Top View
Top View
AINCOM
CAPP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
AINCOM
CAPP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
AIN8
AIN9
NC
NC
CAPN
NC
CAPN
AVDD
NC
AVDD
NC
Thermal Pad
Thermal Pad
AVSS
NC
AVSS
NC
REFOUT
PWDN
RESET
NC
REFOUT
PWDN
RESET
NC
CLKIN
DVDD
CLKIN
DVDD
Not to scale
Not to scale
4
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
ADS1260
ADS1261
Analog
input/output
1
AINCOM
CAPP
AINCOM
Analog input common, IDAC1, IDAC2, VBIAS
Analog
output
PGA output P; connect a 4.7-nF C0G dielectric capacitor across CAPP and
CAPN
2
3
CAPP
CAPN
Analog
output
PGA output N; connect a 4.7-nF C0G dielectric capacitor across CAPP and
CAPN
CAPN
4
5
AVDD
AVSS
AVDD
AVSS
Analog
Analog
Positive analog power supply
Negative analog power supply
Analog
output
6
REFOUT
REFOUT
Internal 2.5-V reference output; connect a 10-µF capacitor to AVSS
7
PWDN
RESET
START
CS
PWDN
RESET
START
CS
Digital input Power down, active low
8
Digital input Reset, active low
9
Digital input Start conversion control, active high
Digital input Serial interface chip select, active low
Digital Input Serial interface shift clock
Digital Input Serial interface data input
Digital output Data ready indicator, active low
10
11
12
13
14
SCLK
DIN
SCLK
DIN
DRDY
DRDY
DOUT/DRDY DOUT/DRDY Digital output Dual function serial interface data output and active-low data ready indicator
Analog
15
BYPASS
BYPASS
Internal subregulator bypass; connect a 1-µF capacitor to DGND
output
Digital
Digital
16
17
DGND
DVDD
DGND
DVDD
Digital ground
Digital power supply
1) Internal oscillator: connect to DGND
2) External clock: connect clock input
18
CLKIN
NC
CLKIN
NC
Digital input
19-22
23
—
No connection. Electrically float or connect to DGND
Analog
ADS1260: No connection. Electrically float or connect to DGND
input/output ADS1261: Analog input 9, IDAC1, IDAC2
NC
AIN9
Analog
ADS1260: No connection. Electrically float or connect to DGND
24
NC
NC
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AIN0
Pad
input/output ADS1261: Analog input 8, IDAC1, IDAC2
Analog
ADS1260: No connection. Electrically float or connect to DGND
25
input/output ADS1261: Analog input 7, IDAC1, IDAC2
Analog
ADS1260: No connection. Electrically float or connect to DGND
26
NC
input/output ADS1261: Analog input 6, IDAC1, IDAC2
Analog
ADS1260: No connection. Electrically float or connect to DGND
27
NC
input/output ADS1261: Analog input 5, IDAC1, IDAC2, GPIO3, ACX2
Analog
ADS1260: Analog input 4, IDAC1, IDAC2
28
AIN4
AIN3
AIN2
AIN1
AIN0
Pad
input/output ADS1261: Analog input 4, IDAC1, IDAC2, GPIO2, ACX1
Analog ADS1260: Analog input 3, IDAC1, IDAC2
input/output ADS1261: Analog input 3, IDAC1, IDAC2, REFN1, GPIO1, ACX2
Analog ADS1260: Analog input 2, IDAC1, IDAC2
29
30
input/output ADS1261: Analog input 2, IDAC1, IDAC2, REFP1, GPIO0, ACX1
Analog
31
Analog input 1, IDAC1, IDAC2, REFN0
input/output
Analog
32
Analog input 0, IDAC1, IDAC2, REFP0
input/output
Exposed thermal pad; Connect to AVSS. Pad must be soldered for
mechanical integrity.
Thermal Pad
—
Copyright © 2018–2019, Texas Instruments Incorporated
5
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
(1)
see
MIN
–0.3
–3
MAX UNIT
AVDD to AVSS
7
Power-supply voltage
AVSS to DGND
0.3
7
V
DVDD to DGND
–0.3
Analog input voltage
Digital input voltage
Input current
AINx
AVSS – 0.3 AVDD + 0.3
DGND – 0.3 DVDD + 0.3
V
V
CS, SCLK, DIN, DOUT/DRDY, DRDY, START, RESET, PWDN, CLKIN
Continuous, all pins except power-supply pins(2)
–10
10
150
150
mA
°C
°C
Junction, TJ
Storage, Tstg
Temperature
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input and output pins are diode-clamped to the internal power supplies. Limit the input current to 10 mA in the event the analog input
voltage exceeds AVDD + 0.3 V or AVSS – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or DGND – 0.3 V.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
7.3 Recommended Operating Conditions
MIN
NOM
MAX UNIT
POWER SUPPLY
AVDD to AVSS
4.75
–2.6
2.7
5
5.25
V
Analog power supply
AVSS to DGND
DVDD to DGND
0
Digital power supply
5.25
V
ANALOG INPUTS
PGA mode
See 公式 5
V(AINx)
VIN
Absolute input voltage
Differential input voltage
V
V
PGA bypassed
VIN = VAINp – VAINn
AVSS – 0.1
AVDD + 0.1
(1)
±VREF / Gain
See
VOLTAGE REFERENCE INPUTS
VREF
Differential reference voltage
Negative reference voltage
Positive reference voltage
VREF = V(REFPx) – V(REFNx)
0.9
AVSS – 0.05
V(REFNx) + 0.9
AVDD – AVSS
V(REFPx) – 0.9
AVDD + 0.05
V
V
V
V(REFNx)
V(REFPx)
EXTERNAL CLOCK
2.5 SPS to 25.6 kSPS
40 kSPS
1
1
7.3728
10.24
8
10.75
60%
fCLK
Frequency
Duty cycle
MHz
40%
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)
Input voltage
AVSS
DGND
–45
AVDD
DVDD
125
V
V
DIGITAL INPUTS (Other Than GPIOs)
Input voltage
TEMPERATURE
TA
Operating ambient temperature
°C
(1) In PGA mode, the maximum differential input voltage is ±(AVDD – AVSS – 0.6 V) / Gain, when operating with
VREF ≥ AVDD – AVSS – 0.6 V.
7.4 Thermal Information
ADS126x
RHB (VQFN)
THERMAL METRIC(1)
UNIT
32 PINS
28.6
17.0
9.7
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
9.7
RθJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2018–2019, Texas Instruments Incorporated
7
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, PGA mode, gain = 1, and
data rate = 20 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
PGA mode, V(AINx) = 2.5 V
PGA bypass
4
200
0.01
±0.1
±1
6
Absolute input current
nA
Absolute input current drift
nA/°C
PGA mode, VIN = 19 mV
PGA mode, VIN = 2.5 V
PGA mode, chop mode(1)
PGA bypass, VIN = 2.5 V
–3
3
Differential input current
nA
±5
±40
0.05
1
Differential input current drift
Differential input impedance
Crosstalk
nA/°C
GΩ
PGA mode
PGA bypass
50
MΩ
0.1
µV/V
PGA
Gain settings
1, 2, 4, 8, 16, 32, 64, 128
60
V/V
kHz
Antialias filter frequency
CCAPP, CAPN = 4.7 nF
No missing codes
PERFORMANCE
Resolution
24
Bits
DR
Data rate
2.5
40000
SPS
Noise performance
See 表 1
Gain = 1 to 16
–10
–12
±2
±3
10
INL
Integral nonlinearity
Offset voltage
Gain = 32 to 128
Gain = 1 to 32 (40 kSPS)
TA = 25°C
12
15
ppmFSR
–15
±5
–175 / gain – 5
±50 / gain
175 / gain + 5
µV
–0.5 / gain –
0.05
0.5 / gain +
0.05
VOS
TA = 25°C, chop mode
±0.2 / gain
After calibration
On the level of noise
Gain = 1 to 8
100 / gain
350 / gain
Offset voltage drift
Gain = 16 to 128
10
50
5
nV/°C
µV
Chop mode, gain = 1 to 128
Gain = 1, 1000 hr
TA = 25°C, gain = 1 to 128
After calibration
1
Offset voltage long-term drift
Gain error
±0.1
–0.5%
±0.05%
0.5%
4
GE
On the level of noise
Gain drift
Normal-mode rejection ratio(2)
Gain = 1 to 128
0.5
See 表 7
130
ppm/°C
NMRR
CMRR
Data rate = 20 SPS
Data rate = 400 SPS
AVDD and AVSS
DVDD
Common-mode rejection ratio(3)
Power-supply rejection ratio(4)
dB
dB
105
85
115
100
PSRR
100
120
INTERNAL OSCILLATOR
2.5 SPS to 25.6 kSPS
40 kSPS
7.3728
10.24
fCLK
Frequency
Accuracy
MHz
–2%
±0.5%
2%
(1) Chop-mode input current scales with data rate.
(2) Normal-mode rejection ratio performance depends on the digital filter configuration.
(3) Common-mode rejection ratio is specified at 60 Hz.
(4) Power-supply rejection ratio specified at dc. PSRR (dB) = 20 Log (Δ power supply voltage / Δ offset voltage).
8
Copyright © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, PGA mode, gain = 1, and
data rate = 20 SPS (unless otherwise noted)
PARAMETER
VOLTAGE REFERENCE INPUTS
Absolute input current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±250
15
nA
nA/V
nA/°C
MΩ
Input current vs voltage
Input current drift
0.2
30
Input impedance
Differential
INTERNAL VOLTAGE REFERENCE(5)
Voltage
2.5
±0.1%
±0.2%
V
TA = 25°C, ADS1260B, ADS1261B
TA = 25°C, ADS1261
±0.2%
9
Initial error
TA = 0°C to +85°C, ADS1260B,
ADS1261B
2
4
Temperature drift
TA = –40°C to +125°C, ADS1260B,
ADS1261B
ppm/°C
12
40
TA = –40°C to +125°C, ADS1261
1000 hr
10
±25
±70
±20
Long-term drift
ppm
ppm
First temperature cycle
Second temperature cycle
Thermal hysteresis(6)
Output current
Load regulation
–10
10
mA
µV/mA
ms
50
Start-up time
Settling time to ±0.001% of final value
100
EXCITATION CURRENT SOURCES (IDACS)
50, 100, 250, 500, 750,
1000, 1500, 2000, 2500, 3000
Current settings
µA
V
Compliance range
Accuracy
AVSS
–4%
AVDD – 1.1
±0.7%
±0.1%
±1%
50
4%
1%
Same current magnitudes
Different current magnitudes
Absolute
–1%
Match error
Temperature drift
ppm/°C
Match drift, IIDAC1 = IIDAC2
5
25
LEVEL-SHIFT VOLTAGE (VBIAS)
Voltage
(AVDD + AVSS) / 2
100
V
Output impedance
BURN-OUT CURRENT SOURCES
Current settings
Ω
Sink and source
0.05-µA range
0.05, 0.2, 1, 10
µA
µA
Accuracy
0.025
0.05
0.075
TEMPERATURE SENSOR
Sensor voltage
TA = 25°C
122.4
420
mV
Temperature coefficient
MONITORS
µV/°C
Low
High
Low
AVSS + 0.2
AVDD – 0.2
0.4
PGA output
V
V
Reference voltage
0.6
(5) Soldered to PCB using recommended PCB layout pattern and using reflow profile per JEDEC standard J-STD-020D.1
(6) Voltage reference hysteresis measured by operating the device at 25°C cycling the device to 0°C and 105°C and returning the device to
25°C.
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, PGA mode, gain = 1, and
data rate = 20 SPS (unless otherwise noted)
PARAMETER
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)(7)
TEST CONDITIONS
MIN
TYP
MAX
0.2 · AVDD
0.3 · AVDD
UNIT
VOL
VOH
VIL
Low-level output voltage
High-level output voltage
Low-level input voltage
High-level input voltage
Input hysteresis
IOL = –1 mA
V
V
V
V
V
IOH = 1 mA
0.8 · AVDD
0.7 · AVDD
VIH
0.5
DIGITAL INPUTS/OUTPUTS (Other Than GPIOs)
IOL = –1 mA
IOL = –8 mA
IOH = 1 mA
IOH = 8 mA
0.2 · DVDD
VOL
Low-level output voltage
High-level output voltage
V
V
0.2 · DVDD
0.8 · DVDD
VOH
0.75 · DVDD
VIL
VIH
Low-level input voltage
High-level input voltage
Input hysteresis
0.3 · DVDD
V
V
0.7 · DVDD
–10
0.1
V
Input leakage
VIH or VIL
10
µA
POWER SUPPLY
PGA bypass
2.7
4.5
6
PGA mode, gain = 1 to 32
PGA mode, gain = 64 or 128
Power-down mode
Voltage reference
40-kSPS mode
3.8
mA
IAVDD
IAVSS
,
,
Analog supply current
4.3
6.5
8
2
µA
0.2
mA
IAVDD
IAVSS
Analog supply current (by function)
0.5
Current sources
20 SPS
As programmed
0.4
0.6
30
0.65
0.85
50
mA
µA
IDVDD
Digital supply current
Power dissipation
40 kSPS
Power-down mode(8)
PGA mode
20
32
PD
mW
Power-down mode
0.1
0.2
(7) GPIO voltage with respect to AVSS.
(8) CLKIN input stopped.
10
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ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
7.6 Timing Requirements
over operating ambient temperature range, DVDD = 2.7 V to 5.25 V, and DOUT/DRDY load: 20 pF || 100 kΩ to DGND
(unless otherwise noted); see 图 8
MIN
MAX
UNIT
SERIAL INTERFACE
td(CSSC)
tsu(DI)
th(DI)
Delay time, first SCLK rising edge after CS falling edge(1)
50
25
25
97
ns
ns
ns
ns
Setup time, DIN valid before SCLK falling edge
Hold time, DIN valid after SCLK falling edge
SCLK period(2)
tc(SC)
106
tw(SCH),
tw(SCL)
Pulse duration, SCLK high or low
40
ns
td(SCCS)
tw(CSH)
td(SCIR)
RESET
tw(RSTL)
Delay time, last SCLK falling edge before CS rising edge
Pulse duration, CS high to reset interface
50
25
ns
ns
Delay time, SCLK high or low to force interface auto-reset
65540
1/fCLK
Pulse duration, RESET low
4
1/fCLK
CONVERSION CONTROL
tw(STH) Pulse duration, START high
tw(STL)
4
4
1/fCLK
1/fCLK
Pulse duration, START low
Setup time, START low or STOP command after DRDY low to stop next
conversion (continuous mode)
tsu(DRST)
th(DRSP)
100
1/fCLK
1/fCLK
Hold time, START low or STOP command after DRDY low to continue next
conversion (continuous mode)
150
(1) CS can be tied low.
(2) Serial interface time-out mode: minimum SCLK frequency = 1 kHz. Otherwise, no minimum SCLK frequency.
.
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7.7 Switching Characteristics
over operating ambient temperature range, DVDD = 2.7 V to 5.25 V, and DOUT/DRDY load: 20 pF || 100 kΩ to DGND
(unless otherwise noted); see 图 8
PARAMETER
MIN
TYP
MAX
UNIT
SERIAL INTERFACE
tw(DRH)
Pulse duration, DRDY high
16
0
1/fCLK
ns
Propagation delay time, CS falling edge to DOUT/DRDY
driven
tp(CSDO)
50
40
Propagation delay time, SCLK rising edge to valid
DOUT/DRDY
tp(SCDO1)
th(SCDO1)
th(SCDO2)
tp(SCDO2)
ns
ns
ns
ns
ns
Hold time, SCLK rising edge to invalid data on
DOUT/DRDY
0
Hold time, last SCLK falling edge of operation to invalid
data on DOUT/DRDY
15
Propagation delay time, last SCLK falling edge to valid
data ready function on DOUT/DRDY
110
50
Propagation delay time, CS rising edge to DOUT/DRDY
high impedance
tp(CSDOZ)
RESET
tp(RSCN)
Propagation delay time, RESET rising edge or RESET
command to start of conversion
512
512
2
1/fCLK
1/fCLK
1/fCLK
Propagation delay time, power-on threshold voltage to
ADC communication
tp(PRCM)
tp(CMCN)
216
Propagation delay time, ADC communication to
conversion start
AC EXCITATION
td(ACX)
Delay time, phase-to-phase blanking period
ACX period
8
1/fCLK
tSTDR
tc(ACX)
CONVERSION CONTROL
Propagation delay time, START high or START command
tp(STDR)
2
1/fCLK
to DRDY high
tw(CSH)
CS
td(CSSC)
tc(SC)
td(SCCS)
tw(SCH)
SCLK
tw(SCL)
th(DI)
tsu(DI)
DIN
图 1. Serial Interface Timing Requirements
12
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ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
tw(DRH)
DRDY
CS
SCLK
tp(SCDO2)
tp(CSDO)
tp(SCDO1)
DATA
th(SCDO1)
tp(CSDOZ)
(1)
(1)
DRDY
DRDY
DOUT/DRDY
th(SCDO2)
(1) Before the first SCLK rising edge and after the last SCLK falling edge of a command, the function of DOUT/DRDY is data ready.
图 2. Serial Interface Switching Characteristics
Serial Interface
Auto-Reset
td(SCIR)
Next byte transaction
b7
b6
b5
b4
b3
b2
b1
b0
SCLK
图 3. Serial Interface Auto-Reset Characteristics
tw(STH)
START
tw(STL)
Serial
Command
START
STOP
tsu(DRST)
STOP
tp(STDR)
DRDY
th(DRSP)
图 4. Conversion Control Timing Requirements
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DVDD
1 V (typ)
1 V (typ)
VBYPASS
AVDD - AVSS
3.5 V (typ)
All supplies reach thresholds
DRDY
Begin ADC Communication
DOUT/DRDY
tp(PRCM)
tp(CMCN)
Conversion
Status
Start of 1st Conversion
图 5. Power-Up Characteristics
tw(RSTL)
RESET
Reset
Command
tp(RSCN)
Conversion
Status
Reset
Start
图 6. RESET pin and RESET Command Timing Requirements
tc(ACX)
td(ACX)
td(ACX)
ACX1
ACX1
ACX2
ACX2
图 7. AC-Excitation Timing Characteristics
DVDD
½ DVDD
DGND
50%
td, th, tp, tw,tc
图 8. Timing Voltage-Level Reference
14
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7.8 Typical Characteristics
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
10
8
0.5
0.4
0.3
0.2
0.1
0
PGA Bypass
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
PGA Bypass
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
6
4
2
0
-2
-4
-6
-8
-10
-0.1
-0.2
-0.3
-0.4
-0.5
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D009
D010
After calibration, shorted input
图 9. Offset Voltage vs Temperature
Chop mode, after calibration, shorted input
图 10. Offset Voltage vs Temperature
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
Gain = 1
Gain = 16
Gain = 128
Gain = 1
Gain = 16
Gain = 128
Input-Referred Offset Drift (nV/èC)
Input-Referred Offset Drift (nV/èC)
D012
D011
Shorted input, 30 units
Chop mode, shorted input, 30 units
图 11. Offset Voltage Drift Distribution
图 12. Offset Voltage Drift Distribution
2
1.5
1
40
35
30
25
20
15
10
5
Gain = 1, 400 SPS
Gain = 1, 40000 SPS
Gain = 16, 400 SPS
Gain = 16, 40000 SPS
Gain = 128, 400 SPS
Gain = 128, 40000
0.5
0
-0.5
-1
0
-1.5
-2
-5
-10
0
250
500
750
1000 1250 1500 1750 2000
0.5
1
1.5
2
2.5
VREF(V)
3
3.5
4
4.5
5
Time (hr)
D205
D001
After calibration
图 13. Offset Voltage vs Reference Voltage
After calibration, gain = 1
图 14. Offset Voltage Long-Term Drift
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
200
150
100
50
50
40
30
20
10
0
PGA Bypass
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 1
Gain = 8
Gain = 128
0
-50
-100
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Gain Drift (ppm/èC)
D014
D013
After calibration
30 units
图 15. Gain Error vs Temperature
图 16. Gain Error Drift Distributions
60
50
40
30
20
10
0
0.5
0.45
0.4
Gain = 1, 400 SPS
Gain = 1, 40000 SPS
Gain = 128, 400 SPS
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 128, 40000 SPS
0.35
0.3
0.25
0.2
-10
-20
-30
-40
0.15
0.1
0.05
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-40
-20
0
20
40
60
80
100
120
VREF (V)
Temperature (èC)
D002
DE0x0c3e
After calibration
图 17. Gain Error vs Reference Voltage
20 SPS, Sinc4
图 18. Noise vs Temperature
10
9
8
7
6
5
4
3
2
1
0
50
45
40
35
30
25
20
15
10
5
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 1
Gain = 16
Gain = 32
Gain = 64
Gain = 128
Gain = 2
Gain = 4
Gain = 8
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D004
D005
7200 SPS, Sinc1
40000 SPS, Sinc5
图 19. Noise vs Temperature
图 20. Noise vs Temperature
16
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
800
140
120
100
80
Gain = 1, 400 SPS
Gain = 128, 400 SPS
Gain = 1, 7200 SPS
Gain = 128, 7200 SPS
Gain = 1, 40000 SPS
Gain = 128, 40000 SPS
100
10
1
60
40
20
0.07
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VREF(V)
D006
D028
Conversion Data (mV)
20 SPS, gain = 4, 256 data points
图 21. Noise vs Reference Voltage
图 22. Conversion Data Histogram
3500
3000
2500
2000
1500
1000
500
160
140
120
100
80
60
40
20
0
0
Conversion Data (mV)
D030
D029
Conversion Data (mV)
7200 SPS, gain = 4, 8192 data points
20 SPS, gain = 128, 256 data points
图 23. Conversion Data Histogram
图 24. Conversion Data Histogram
4000
3500
3000
2500
2000
1500
1000
500
10
8
Gain = 1
Gain = 4
Gain = 16
Gain = 32
Gain = 64
6
4
2
0
-2
-4
-6
-8
-10
0
-100 -80 -60 -40 -20
0
20
40
60
80 100
Full Scale Range (%VIN
)
Conversion Data (mV)
D031
D033
7200 SPS, gain = 128, 8192 data points
图 25. Conversion Data Histogram
图 26. Integral Nonlinearity vs VIN
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
50
45
40
35
30
25
20
15
10
5
10
9
8
7
6
5
4
3
2
1
0
Gain = 1
Gain = 4
Gain = 32
Gain = 128
Gain = 1
Gain = 4
Gain = 16
Gain = 64
Gain = 128
0
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Integral Non-Linearity (ppmFSR
)
D007
D015
30 Units
图 27. Integral Nonlinearity vs Temperature
图 28. Integral Nonlinearity Distribution
20
16
12
8
2.4985
2.498
Gain = 1, 20 SPS
Gain = 4, 20 SPS
Gain = 32, 20 SPS
Gain = 64, 20 SPS
Gain = 128, 20 SPS
Gain = 1, 40000 SPS
Gain = 4, 40000 SPS
Gain = 32, 40000 SPS
2.4975
2.497
Data for gains 64, 128 limited
by instrument noise for VREF < 2 V
2.4965
2.496
2.4955
2.495
4
2.4945
0
-40
-20
0
20
40
60
80
100
120
0.5
1
1.5
2
2.5
VREF (V)
3
3.5
4
4.5
5
Temperature (èC]
D102
D008
ADS1260B, ADS1261B - 30 units
图 30. Voltage Reference vs Temperature
图 29. Integral Nonlinearity vs Reference Voltage
75
50
350
300
250
200
150
100
50
IREFN, TA = -40èC
IREFN, TA = 25èC
IREFN, TA = 85èC
IREFN, TA = 125èC
IREFP, TA = -40èC
IREFP, TA = 25èC
IREFP, TA = 85èC
IREFP, TA = 125èC
REFP
25
0
-25
-50
-75
0
REFN
-50
0
250
500
750
1000 1250 1500 1750 2000
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Time (hr)
Differential Reference Voltage (V)
D204
D024
IREFP measured with VREFN = AVSS
IREFN measured with VREFP = AVDD
After calibration, 30 units
图 32. Reference Input Current vs Reference Voltage
图 31. Voltage Reference Long-Term Drift
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
40
30
20
10
0
1
0.5
0
-0.5
-1
-1.5
-40
-20
0
20
40
60
80
100
120
D017
Temperature (èC)
Temperature Sensor Voltage (mV)
D016
30 units
30 units
图 34. Internal Oscillator vs Temperature
图 33. Temperature Sensor Voltage Histogram
6
5
4.95
4.9
IAVDD, IAVSS (Gain Ç 32)
IAVDD, IAVSS (Gain í 64)
IDVDD (20 SPS)
IDVDD (40000 SPS)
5
4
3
2
1
0
4.85
4.8
4.75
4.7
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D018
D025
图 35. Operating Current vs Temperature
图 36. PGA High Monitor Threshold
0.3
0.25
0.2
1
0.8
0.6
0.4
0.2
0
0.15
0.1
0.05
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
Temperature (èC)
D026
D027
图 37. PGA Low Monitor Threshold
图 38. Reference Voltage Low Alarm Threshold
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
135
120
105
90
125
120
115
110
105
100
95
90
75
AVDD
DVDD
85
60
80
1
10
100
1000
10000
100000 1000000
1
10
100
1000
10000
100000 1000000
Frequency (Hz)
Frequency (Hz)
D150
D151
Data rate = 1200 SPS
图 39. CMRR vs Frequency
Data rate = 1200 SPS
图 40. PSRR vs Frequency
130
125
120
115
110
105
100
95
55
52.5
50
47.5
45
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
90
CMRR
PSRR AVDD, AVSS
PSRR DVDD
42.5
40
85
80
-40
-20
0
20
40
60
80
100
120
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (èC)
IDAC Voltage (V)
D034
D022
IIDAC = 50 µA
图 41. CMRR and PSRR vs Temperature
图 42. IDAC Current vs IDAC Voltage
260
1050
1000
950
250
240
230
220
210
200
900
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
850
800
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IDAC Voltage (V)
IDAC Voltage (V)
D019
D020
IIDAC = 250 µA
图 43. IDAC Current vs IDAC Voltage
IIDAC = 1000 µA
图 44. IDAC Current vs IDAC Voltage
20
版权 © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, VREF = 2.5 V, data rate = 20 SPS, fCLK = 7.3728 MHz (fCLK
10.24 MHz for data rate = 40 kSPS), and gain = 1 (unless otherwise noted)
=
3050
3000
2950
2900
2850
2800
0.2
0.15
0.1
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0.05
0
-0.05
-0.1
-0.15
-0.2
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IDAC Voltage (V)
IDAC Voltage (V)
D021
D023
IIDAC = 3000 µA
IIDAC1 = IIDAC2 = 250 µA
图 46. IDAC Current Match vs IDAC Voltage
图 45. IDAC Current vs IDAC Voltage
0.2
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IDAC Voltage (V)
D035
IIDAC1 = IIDAC2 = 1000 µA
图 47. IDAC Current Match vs IDAC Voltage
版权 © 2018–2019, Texas Instruments Incorporated
21
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
8 Parameter Measurement Information
8.1 Noise Performance
The ADS126x noise performance depends on the ADC configuration: data rate, PGA gain, digital filter
configuration, and chop mode. The combination of the parameters affect noise performance. Two significant
factors affecting noise performance are data rate and PGA gain. Since the profile of noise is predominantly white
(flat vs frequency), decreasing the data rate proportionally decreases bandwidth and therefore, total noise. Since
the noise of the PGA is lower than that of the modulator of the ADC, increasing the gain reduces noise when
treated as an input-referred quantity. Noise performance also depends on the digital filter and chop mode. As the
order of the digital filter increases, the noise bandwidth correspondingly decreases resulting in lower noise.
Further, as a result of two-point data averaging in chop mode, noise performance improves by √2 compared to
normal operation.
表 1 shows noise performance in units of μVRMS (RMS = root mean square) under the conditions listed. The
values in parenthesis are peak-to-peak values. 表 2 shows the noise performance in effective resolution (bits)
under the specified conditions. The values shown in parenthesis are the noise-free resolution. Noise-free
resolution is the resolution of the ADC with no code flicker. The noise-free resolution data are calculated based
on the peak-to-peak noise measurements.
The effective resolution data listed in the tables are calculated using 公式 1:
Effective Resolution or Noise-Free Resolution = ln (FSR / en) / ln (2)
where
•
•
FSR = full scale range = 2 · VREF / Gain (See Recommended Operating Conditions for FSR)
en = Input referred voltage noise (RMS value to calculate effective resolution, p-p value to calculate noise-free
resolution)
(1)
The data shown in the noise performance table represent typical ADC performance at TA = 25°C. The noise-
performance data are the standard deviation and peak-to-peak computations of the ADC data. The noise data
are acquired with inputs shorted, based on consecutive ADC readings for a period of ten seconds or 8192 data
points, whichever occurs first. Because of the statistical nature of noise, repeated noise measurements may yield
higher or lower noise performance results.
As a result of the increased full-scale input range provided by 5-V reference operation, effective resolution and
noise-free resolution performance are typically optimized using a 5-V reference. The effective resolution and
noise-free resolution performance data shown in 表 2 are with external 5-V reference operation.
表 1. Noise in µVRMS (µVPP) at TA = 25°C and Internal 2.5-V Reference
DATA
GAIN
RATE FILTER
(SPS)
1
2
4
8
16
32
64
128
2.5
2.5
2.5
2.5
2.5
5
FIR
0.18 (0.6) 0.078 (0.28)
0.046 (0.16) 0.025 (0.096) 0.014 (0.053) 0.012 (0.045) 0.01 (0.042)
0.01 (0.04)
Sinc1 0.15 (0.47) 0.071 (0.28)
0.038 (0.14) 0.019 (0.075) 0.012 (0.051) 0.01 (0.039) 0.009 (0.037) 0.009 (0.037)
Sinc2 0.14 (0.38) 0.065 (0.23) 0.032 (0.096) 0.018 (0.059) 0.011 (0.037) 0.007 (0.028) 0.007 (0.028) 0.008 (0.033)
Sinc3 0.12 (0.38) 0.062 (0.17) 0.028 (0.064) 0.016 (0.053) 0.01 (0.035) 0.008 (0.027) 0.007 (0.026) 0.006 (0.023)
Sinc4
FIR
0.1 (0.26)
0.059 (0.17) 0.032 (0.085) 0.016 (0.059) 0.010 (0.035) 0.008 (0.027) 0.006 (0.025) 0.006 (0.024)
0.22 (0.89)
0.11 (0.4)
0.058 (0.24)
0.047 (0.17)
0.032 (0.13) 0.021 (0.085) 0.016 (0.065) 0.014 (0.061) 0.015 (0.066)
0.025 (0.11) 0.017 (0.069) 0.014 (0.061) 0.012 (0.054) 0.014 (0.063)
5
Sinc1
0.18 (0.6) 0.093 (0.36)
5
Sinc2 0.16 (0.64) 0.084 (0.32)
Sinc3 0.13 (0.51) 0.088 (0.32)
Sinc4 0.13 (0.51) 0.077 (0.28)
0.043 (0.16) 0.023 (0.085) 0.015 (0.064) 0.011 (0.047) 0.010(0.046) 0.011 (0.049)
0.036 (0.15) 0.024 (0.091) 0.014 (0.053) 0.01 (0.043) 0.009 (0.045) 0.009 (0.042)
0.034 (0.12) 0.021 (0.075) 0.013 (0.053) 0.010 (0.044) 0.008 (0.038) 0.009 (0.038)
5
5
10
10
10
10
10
16.6
FIR
0.27 (1.4)
0.23 (1.1)
0.2 (0.89)
0.14 (0.72)
0.13 (0.57)
0.11 (0.51)
0.076 (0.4)
0.064 (0.3)
0.054 (0.24)
0.05 (0.22)
0.049 (0.24)
0.082 (0.43)
0.042 (0.21)
0.036 (0.19)
0.03 (0.14)
0.029 (0.15)
0.024 (0.13)
0.023 (0.12)
0.02 (0.1)
0.023 (0.11)
0.022 (0.11)
Sinc1
Sinc2
0.018 (0.083) 0.018 (0.089)
0.019 (0.093) 0.015 (0.075) 0.015 (0.079) 0.016 (0.077)
Sinc3 0.18 (0.81) 0.097 (0.38)
Sinc4 0.17 (0.68) 0.099 (0.45)
0.028 (0.14) 0.019 (0.088) 0.015 (0.063) 0.013 (0.067) 0.013 (0.065)
0.024 (0.12) 0.018 (0.085) 0.013 (0.063) 0.012 (0.061) 0.012 (0.062)
Sinc1
0.3 (1.4)
0.16 (0.81)
0.048 (0.25)
0.031 (0.17)
0.025 (0.15)
0.024 (0.12)
0.024 (0.14)
22
版权 © 2018–2019, Texas Instruments Incorporated
ADS1260, ADS1261
www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
Noise Performance (接下页)
表 1. Noise in µVRMS (µVPP) at TA = 25°C and Internal 2.5-V Reference (接下页)
DATA
GAIN
RATE FILTER
(SPS)
1
2
4
8
16
0.026 (0.14)
32
64
128
16.6
16.6
16.6
20
Sinc2
0.24 (1.2)
0.13 (0.64)
0.12 (0.64)
0.12 (0.53)
0.2 (1.1)
0.18 (0.92)
0.15 (0.77)
0.13 (0.64)
0.13 (0.66)
0.27 (1.6)
0.22 (1.3)
0.2 (1.2)
0.19 (1.1)
0.28 (1.9)
0.24 (1.4)
0.21 (1.3)
0.2 (1.1)
0.37 (2.4)
0.3 (1.9)
0.27 (1.8)
0.26 (1.6)
0.72 (5.4)
0.58 (4.2)
0.53 (3.7)
0.51 (3.6)
1.2 (9.2)
1 (7.6)
0.067 (0.34)
0.065 (0.3)
0.06 (0.29)
0.1 (0.56)
0.091 (0.48)
0.073 (0.35)
0.069 (0.35)
0.066 (0.33)
0.14 (0.83)
0.11 (0.69)
0.11 (0.64)
0.098 (0.61)
0.15 (0.88)
0.12 (0.71)
0.11 (0.68)
0.11 (0.6)
0.19 (1.3)
0.16 (0.97)
0.14 (0.9)
0.14 (0.87)
0.38 (2.7)
0.31 (2.3)
0.28 (2)
0.038 (0.2)
0.036 (0.18)
0.035 (0.18)
0.059 (0.34)
0.051 (0.26)
0.042 (0.22)
0.039 (0.21)
0.037 (0.19)
0.08 (0.5)
0.064 (0.38)
0.058 (0.35)
0.056 (0.32)
0.087 (0.53)
0.07 (0.45)
0.065 (0.4)
0.059 (0.36)
0.11 (0.73)
0.09 (0.55)
0.083 (0.51)
0.078 (0.48)
0.22 (1.6)
0.18 (1.3)
0.17 (1.2)
0.15 (1.2)
0.37 (2.9)
0.31 (2.4)
0.29 (2.2)
0.27 (2)
0.021 (0.11) 0.019 (0.099) 0.019 (0.098)
Sinc3 0.22 (0.98)
0.024 (0.12) 0.019 (0.095) 0.017 (0.092) 0.018 (0.093)
0.022 (0.11) 0.017 (0.084) 0.016 (0.085) 0.016 (0.086)
Sinc4
FIR
0.21 (1.1)
0.37 (2)
0.32 (1.8)
0.27 (1.4)
0.24 (1.2)
0.23 (1.1)
0.49 (2.9)
0.4 (2.3)
0.37 (2.2)
0.34 (2)
0.55 (3.3)
0.45 (2.7)
0.41 (2.7)
0.37 (2)
0.69 (4.5)
0.56 (3.5)
0.51 (3.4)
0.48 (3.3)
1.4 (9.6)
1.1 (8.2)
1 (7.4)
0.041 (0.22)
0.034 (0.2)
0.027 (0.14)
0.026 (0.14)
0.034 (0.18)
0.028 (0.15)
0.022 (0.13)
0.02 (0.11)
0.029 (0.17)
0.025 (0.14)
0.021 (0.11)
0.018 (0.099)
0.03 (0.15)
0.025 (0.14)
0.02 (0.11)
0.018 (0.1)
20
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
20
20
20
0.024 (0.12) 0.018 (0.095) 0.017 (0.095) 0.017 (0.099)
50
0.053 (0.31)
0.043 (0.27)
0.04 (0.25)
0.036 (0.23)
0.058 (0.34)
0.048 (0.32)
0.044 (0.25)
0.041 (0.25)
0.075 (0.5)
0.062 (0.39)
0.056 (0.36)
0.053 (0.34)
0.15 (1.1)
0.12 (0.9)
0.11 (0.8)
0.1 (0.7)
0.043 (0.25)
0.035 (0.22)
0.033 (0.19)
0.03 (0.17)
0.047 (0.28)
0.039 (0.25)
0.036 (0.23)
0.033 (0.21)
0.06 (0.39)
0.051 (0.32)
0.045 (0.3)
0.043 (0.27)
0.12 (0.85)
0.099 (0.74)
0.09 (0.66)
0.084 (0.58)
0.2 (1.6)
0.039 (0.23)
0.033 (0.2)
0.029 (0.18)
0.028 (0.17)
0.044 (0.29)
0.036 (0.21)
0.032 (0.19)
0.03 (0.18)
0.056 (0.37)
0.046 (0.31)
0.041 (0.27)
0.039 (0.24)
0.11 (0.85)
0.091 (0.65)
0.083 (0.61)
0.077 (0.55)
0.19 (1.4)
0.16 (1.2)
0.14 (1.1)
0.13 (1)
0.038 (0.23)
0.032 (0.2)
0.03 (0.18)
0.028 (0.17)
0.042 (0.26)
0.035 (0.21)
0.031 (0.19)
0.03 (0.17)
0.056 (0.38)
0.045 (0.29)
0.041 (0.25)
0.039 (0.26)
0.11 (0.79)
0.091 (0.69)
0.083 (0.59)
0.077 (0.57)
0.19 (1.5)
0.16 (1.2)
0.14 (1.1)
0.13 (1)
50
50
50
60
60
60
60
100
100
100
100
400
400
400
400
1200
1200
1200
1200
2400
2400
2400
2400
4800
4800
4800
4800
7200
7200
7200
7200
0.95 (6.9)
2.3 (17)
1.9 (14)
1.8 (13)
1.6 (12)
3.2 (25)
2.7 (21)
2.5 (19)
2.3 (17)
4.3 (33)
3.8 (29)
3.5 (27)
3.3 (25)
5 (38)
0.27 (1.9)
0.64 (5)
0.25 (1.9)
0.21 (1.6)
0.19 (1.4)
0.18 (1.4)
0.35 (2.7)
0.3 (2.2)
0.54 (3.9)
0.49 (3.7)
0.46 (3.6)
0.88 (6.7)
0.76 (5.8)
0.69 (5.2)
0.65 (4.9)
1.2 (9.4)
0.17 (1.3)
0.16 (1.2)
0.15 (1.1)
0.28 (2.2)
0.24 (1.9)
0.22 (1.7)
0.21 (1.5)
0.37 (2.9)
0.33 (2.6)
0.31 (2.4)
0.29 (2.2)
0.43 (3.2)
0.39 (2.9)
0.37 (2.8)
0.35 (2.6)
0.49 (3.8)
0.57 (4.3)
0.83 (6.3)
1.2 (9.4)
0.92 (7)
0.86 (6.4)
1.7 (13)
0.51 (3.9)
0.44 (3.3)
0.4 (3)
0.26 (2)
0.26 (2)
1.4 (10)
0.22 (1.6)
0.2 (1.6)
0.22 (1.6)
0.2 (1.5)
1.3 (9.8)
1.2 (9.4)
2.3 (17)
0.27 (2.1)
0.25 (2)
0.37 (2.8)
0.69 (5.2)
0.61 (4.7)
0.56 (4.1)
0.53 (4.1)
0.8 (6)
0.19 (1.5)
0.34 (2.6)
0.31 (2.3)
0.28 (2.1)
0.27 (2.1)
0.39 (2.9)
0.36 (2.8)
0.34 (2.5)
0.33 (2.5)
0.45 (3.5)
0.54 (4)
0.19 (1.4)
0.34 (2.6)
0.3 (2.3)
0.46 (3.5)
0.41 (3.1)
0.38 (3)
2 (15)
1.1 (8.5)
1.8 (14)
0.97 (7.2)
0.92 (7.1)
1.4 (10)
0.28 (2.2)
0.27 (1.9)
0.39 (2.9)
0.36 (2.7)
0.34 (2.6)
0.32 (2.5)
0.45 (3.4)
0.53 (4.1)
0.81 (6)
1.7 (13)
0.36 (2.7)
0.53 (4)
2.6 (20)
4.6 (35)
4.3 (33)
4.1 (31)
6 (47)
2.4 (19)
1.3 (9.9)
0.73 (5.4)
0.68 (5)
0.49 (3.8)
0.46 (3.6)
0.44 (3.3)
0.61 (4.9)
0.77 (6)
2.2 (17)
1.2 (9.3)
2.1 (15)
1.1 (8.8)
0.65 (5)
14400 Sinc5
19200 Sinc5
25600 Sinc5
40000 Sinc5
3.1 (24)
1.7 (13)
0.93 (7.1)
1.2 (9.6)
8.5 (67)
19 (140)
30 (220)
4.3 (34)
2.3 (17)
9.5 (73)
4.8 (37)
2.5 (18)
1.3 (10)
0.8 (6)
15 (110)
7.7 (56)
3.9 (29)
2 (15)
1.2 (8.9)
1.2 (9)
版权 © 2018–2019, Texas Instruments Incorporated
23
ADS1260, ADS1261
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
www.ti.com.cn
表 2. Effective Resolution (Noise-Free Resolution) at TA = 25°C and External 5-V Reference
DATA
RATE
(SPS)
GAIN
FILTER
1
2
4
8
16
32
64
128
2.5
2.5
2.5
2.5
2.5
5
FIR
24 (24)
24 (24)
24 (22.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (21.8)
24 (22.8)
24 (22.8)
24 (22.8)
23.8 (21.5)
24 (22.2)
24 (22.2)
24 (22.8)
24 (22.8)
23.7 (21.5)
23.9 (21.5)
23.9 (21.5)
24 (21.8)
23.6 (21)
23.8 (21.5)
23.9 (21.5)
24 (21.8)
23.4 (20.6)
23.6 (21)
23.6 (21.2)
23.7 (21.2)
22.5 (19.7)
22.8 (20.1)
22.9 (20)
23 (20.2)
21.8 (19.1)
22.1 (19.3)
22.2 (19.2)
22.3 (19.6)
21.4 (18.3)
21.6 (18.6)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (23.8)
24 (22.8)
24 (22.8)
24 (22.8)
24 (23.8)
24 (23.8)
24 (22.2)
24 (22.2)
24 (22.2)
24 (22.8)
23.9 (21.8)
24 (21.8)
24 (22.2)
24 (22.2)
24 (22.8)
23.7 (21.2)
23.8 (21.2)
23.9 (21.5)
24 (21.8)
23.6 (21.2)
23.7 (21.2)
23.9 (21.5)
23.9 (21.5)
23.3 (20.5)
23.6 (21)
23.6 (21)
23.7 (21.2)
22.5 (19.6)
22.8 (20)
22.8 (19.9)
22.9 (20.1)
21.7 (18.9)
22 (19.1)
22.1 (19.2)
22.2 (19.2)
21.3 (18.4)
21.5 (18.6)
24 (23.8)
24 (23.8)
22.8 (23.8)
22.8 (23.8)
22.8 (23.8)
24 (22.8)
24 (22.8)
24 (23.8)
24 (23.8)
22.8 (23.8)
24 (22.2)
24 (22.8)
24 (22.8)
24 (23.8)
24 (22.8)
24 (21.8)
24 (22.2)
24 (22.8)
24 (22.8)
23.9 (21.5)
23.9 (21.8)
24 (21.8)
24 (22.8)
24 (22.2)
23.5 (20.8)
23.7 (21.5)
23.8 (21)
23.9 (21.5)
23.4 (20.8)
23.6 (21.2)
23.7 (21.2)
23.7 (21.2)
23.1 (20.4)
23.4 (21)
23.5 (21)
23.6 (21)
22.3 (19.6)
22.6 (19.6)
22.7 (20)
22.7 (20.1)
21.6 (18.7)
21.8 (18.9)
21.9 (19)
22 (19.1)
21.1 (18.1)
21.3 (18.5)
24 (23.8)
24 (22.8)
21.8 (22.8)
24 (23.8)
24 (23.8)
24 (22.2)
24 (22.2)
24 (23.8)
24 (23.8)
24 (23.8)
24 (21.8)
24 (22.2)
24 (22.2)
24 (22.8)
24 (22.8)
23.7 (21.2)
24 (21.8)
24 (22.8)
24 (22.2)
23.5 (21)
23.7 (21.5)
24 (21.8)
24 (21.8)
24 (22.2)
23.3 (20.6)
23.5 (20.8)
23.6 (21.2)
23.7 (21.2)
23.1 (20.5)
23.4 (20.8)
23.5 (20.8)
23.4 (20.6)
22.8 (20)
23 (20.2)
23.2 (20.5)
23.3 (20.6)
21.9 (19)
22.1 (19.2)
22.3 (19.4)
22.3 (19.5)
21.1 (18.3)
21.4 (18.4)
21.5 (18.5)
21.6 (18.7)
20.7 (17.7)
20.9 (18)
24 (22.8)
24 (22.8)
24 (22)
23 (20.8)
23.2 (21.2)
23.9 (22)
Sinc1
Sinc2
Sinc3
Sinc4
FIR
24 (22.4)
24 (24)
24 (23.8)
24 (22.4)
24 (24)
24 (23.8)
24 (22.4)
23.8 (22)
24 (24)
24 (23.8)
24 (23)
23.5 (22)
24 (23)
24 (21.8)
23.6 (21.7)
23.3 (21.4)
23.7 (21.7)
23.5 (21.4)
24 (22)
22.5 (20.7)
22.8 (20.7)
22.8 (21)
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
24 (23.7)
24 (24)
24 (22.8)
5
24 (22.8)
5
24 (24)
24 (22.8)
23.5 (21.7)
23.3 (21.2)
22.1 (19.9)
22.3 (19.8)
22.3 (20.2)
22.7 (20.7)
22.9 (20.8)
21.8 (19.6)
22 (19.5)
5
24 (24)
24 (23.8)
10
24 (22.4)
24 (23)
23.5 (21.2)
23.6 (21.2)
24 (22.2)
22.8 (20.5)
23.4 (21.2)
23.2 (21.4)
23.3 (21.2)
23.7 (21.4)
22.5 (20.3)
23 (20.7)
10
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
10
24 (23)
10
24 (24)
24 (22.2)
10
24 (24)
24 (22.2)
16.6
16.6
16.6
16.6
20
24 (22)
23.4 (21)
24 (22.4)
24 (23)
23.7 (21.2)
23.9 (21.5)
24 (21.5)
23.1 (21)
22 (19.8)
24 (23)
23.4 (20.7)
22.2 (19.8)
22.6 (20.3)
22.8 (20.3)
23 (20.7)
22.5 (20.1)
21.3 (18.7)
21.5 (19.2)
21.9 (19.6)
21.9 (19.4)
22 (19.4)
24 (22)
22.9 (20.5)
23.3 (21)
20
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
24 (22)
20
24 (23)
23.6 (21.2)
23.7 (21.5)
23.8 (21.2)
22.6 (20)
20
24 (22.4)
24 (23)
20
23.1 (20.7)
21.9 (19.3)
22.1 (19.3)
22.3 (19.8)
22.4 (20)
50
23.9 (21.4)
24 (21.7)
24 (22)
21 (18.6)
50
22.9 (20.2)
23 (20.5)
21.2 (18.8)
21.3 (18.6)
21.5 (18.9)
20.8 (18.2)
21.2 (18.5)
21.2 (18.8)
21.2 (18.7)
20.5 (17.7)
20.8 (18)
50
50
24 (22)
23.2 (20.8)
22.5 (19.9)
22.7 (20.2)
22.9 (20.5)
23 (20.2)
60
23.7 (21.4)
24 (21.4)
24 (21.7)
24 (22)
21.8 (19.1)
22.1 (19.3)
22.2 (19.5)
22.2 (19.5)
21.4 (18.8)
21.7 (19.1)
21.8 (19)
60
60
60
100
100
100
100
400
400
400
400
1200
1200
1200
1200
2400
2400
23.6 (21)
23.8 (21)
23.8 (21.2)
23.9 (21.4)
22.8 (19.8)
23.1 (20.3)
23.1 (20.4)
23.2 (20.3)
22.1 (19.2)
22.3 (19.5)
22.4 (19.6)
22.5 (19.6)
21.6 (18.7)
21.8 (18.8)
22.1 (19.4)
22.4 (19.7)
22.5 (19.9)
22.6 (19.7)
21.2 (18.2)
21.4 (18.6)
21.5 (18.7)
21.7 (18.9)
20.4 (17.5)
20.6 (17.7)
20.8 (18)
20.8 (17.9)
21 (18.1)
21.9 (19.4)
20.4 (17.6)
20.7 (17.9)
20.8 (17.8)
21 (18)
19.5 (16.6)
19.8 (17.1)
19.9 (17)
20 (17.2)
19.7 (16.8)
20 (17.1)
18.8 (15.7)
19 (16)
20.1 (17.2)
20.2 (17.3)
19.2 (16.2)
19.5 (16.6)
19.2 (16.2)
19.2 (16.4)
18.3 (15.4)
18.5 (15.6)
20.9 (18)
19.9 (17.1)
20.2 (17.3)
24
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www.ti.com.cn
ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
表 2. Effective Resolution (Noise-Free Resolution) at TA = 25°C and External 5-V Reference (接下页)
DATA
RATE
(SPS)
GAIN
FILTER
1
2
4
8
16
32
64
128
2400
2400
4800
4800
4800
4800
7200
7200
7200
7200
14400
19200
25600
40000
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
Sinc5
Sinc5
Sinc5
21.9 (19.1)
22 (19.1)
21.7 (18.8)
21.8 (19)
21.6 (18.6)
21.8 (19)
21.4 (18.6)
21.6 (18.6)
20.6 (17.7)
20.8 (17.9)
21 (18)
21 (18.1)
21.1 (18)
20.3 (17.5)
20.4 (17.5)
19.5 (16.6)
19.7 (16.6)
19.8 (16.8)
19.9 (17)
19.6 (16.7)
19.7 (16.7)
18.8 (15.8)
19 (16.1)
18.7 (15.7)
18.8 (15.9)
17.9 (14.9)
18 (14.9)
21.1 (18.1)
21.3 (18.4)
21.4 (18.4)
21.5 (18.6)
20.9 (17.8)
21 (18.1)
20.9 (17.9)
21.1 (18.1)
21.2 (18.3)
21.3 (18.4)
20.7 (17.7)
20.8 (17.9)
20.9 (18.1)
21 (18)
20.9 (17.9)
21 (18.1)
20.2 (17.2)
20.4 (17.4)
20.5 (17.6)
20.6 (17.7)
20 (17)
21.1 (18.3)
21.2 (18.2)
20.6 (17.4)
20.7 (17.9)
20.8 (17.9)
20.9 (18.1)
20.2 (17.3)
19.4 (16.5)
18 (15.2)
19.1 (16.3)
19.2 (16.3)
18.6 (15.7)
18.7 (15.9)
18.8 (15.9)
18.9 (15.9)
18.4 (15.4)
18 (15.1)
18.2 (15.1)
18.2 (15.3)
17.7 (14.7)
17.8 (14.9)
17.9 (14.9)
18 (15)
21.1 (18.1)
20.4 (17.5)
20.6 (17.6)
20.6 (17.8)
20.7 (18)
19.3 (16.4)
19.4 (16.4)
19.5 (16.5)
19.6 (16.7)
19.1 (16.1)
18.8 (15.9)
17.8 (14.8)
17.1 (14.3)
20.2 (17.2)
20.2 (17.2)
20.3 (17.2)
19.8 (16.9)
19.2 (16.2)
17.9 (15.1)
17.2 (14.2)
21.1 (18.1)
21.2 (18.1)
20.5 (17.7)
19.7 (16.8)
18.2 (15.2)
17.4 (14.6)
20.3 (17.5)
19.5 (16.5)
18 (14.9)
20.1 (17.1)
19.4 (16.3)
17.9 (14.7)
17.2 (14.3)
17.5 (14.5)
17 (14.2)
17 (14.2)
16 (13.2)
17.2 (14.2)
17.2 (14.2)
16.3 (13.4)
15.3 (12.5)
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9 Detailed Description
9.1 Overview
The ADS1260 and ADS1261 are 5-channel and 10-channel, precision 24-bit, delta-sigma (ΔΣ) ADCs with an
integrated analog front end (AFE) and voltage reference. The low-noise and low-drift architecture make the
ADCs suitable for precision measurement of low signal level sensors, such as strain-gauge bridges, pressure
transducers and temperature sensors.
Key features of the ADC are:
•
•
•
•
•
•
•
•
•
•
•
•
Very low noise, 1-GΩ input impedance PGA
High-precision, 24-bit ΔΣ ADC
Internal oscillator
2.5-V voltage reference
Signal and voltage reference monitors
Excitation current sources
Input level-shift voltage
Sensor burn-out current sources
Temperature sensor
Cyclic redundancy check (CRC) communication error detection
Two voltage reference inputs ( ADS1261)
Four GPIO with AC-excitation ( ADS1261)
The analog inputs (AINx) connect to the input multiplexer (MUX). The ADC supports three (five) differential or
five (ten) single-ended input configurations for the ADS1260 and ADS1261, respectively.
The programmable gain amplifier (PGA) follows the input multiplexer. The PGA is suitable for direct connection
to low-level sensors. The gain is programmable from 1 to 128. The PGA bypass option connects the analog
inputs directly to the precharge buffered modulator, extending the input voltage range to the power supplies. The
PGA output connects to pins CAPP and CAPN. The ADC antialias filter is provided at the PGA output with an
external capacitor.
The PGA is monitored to verify linear operation. Alarm bits in the status register set if the linear range of the PGA
is exceeded.
A delta-sigma modulator measures the input voltage relative to the reference voltage to produce the 24-bit
conversion result. The differential input range of the ADC is ±VREF / Gain.
The digital filter averages and decimates the modulator output data to yield the final, down-sampled conversion
result. The sinc filter is programmable (sinc1 through sinc5) allowing optimization of conversion time, conversion
noise and line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data
with simultaneous rejection of 50-Hz and 60-Hz at data rates of 20 SPS or less.
The ADC reference is either 2.5-V internal, external or the 5-V analog power supply. The REFOUT pin provides
the buffered reference voltage output. The external reference is monitored for low or missing voltage. The
ADS1261 provides two voltage reference inputs, multiplexed with the analog inputs.
The ADC includes two current sources that provide excitation to resistive sensors (RTD). Additionally, the
ADS1261 provides four GPIO control lines. The GPIOs are used for input and output of general-purpose logic
signals, as well as providing drive signals for AC-excited bridges. The GPIOs are multiplexed to the analog
inputs.
The temperature sensor and the power supply voltages are read through the multiplexer. The programmable
burn-out test currents connect to the multiplexer output. The currents detect failed sensors or faults in the sensor
connection. The level-shift voltage on AINCOM provides the bias for floating sensors.
The SPI-compatible serial interface is used to read the conversion data and also to configure and control the
ADC. Data communication errors are detected by CRC. The serial interface consists of four signals: CS, SCLK,
DIN and DOUT/DRDY. The dual function DOUT/DRDY provides data output and also the data ready signal. The
ADC serial interface can be implemented with as little as three pins by tying CS low.
26
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www.ti.com.cn
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Overview (接下页)
The ADC clock is either internal or external. The ADC detects the external clock automatically. The nominal clock
frequency is 7.3728 MHz (10.24 MHz for 40-kSPS operation).
ADC conversions are controlled by the START pin or by the START command. The ADC is programmable for
continuous or one-shot conversions. The DRDY or DOUT/DRDY pin provides the conversion data ready signal.
When taken low, the RESET pin resets the ADC. The ADC is powered down by the PWDN pin or is powered
down in software mode.
The ADC operates in either bipolar analog supply configuration (±2.5 V), or in a single 5-V supply configuration.
The digital power supply range is 2.7 V to 5 V. The BYPASS pin is the internal subregulator output used for the
ADC digital core.
9.2 Functional Block Diagram
AVDD AVSS
DVDD
CAPP CAPN
BYPASS
2.5-V Ref
2-V Digital Core
LDO
I/O Voltage
REFOUT
Ref
Mux
Level
Shift
AVDD
START
RESET
PWDN
Ref
Monitor
Excitation
Current
Sources
Control
AIN0
AIN1
AIN2
AIN3
Buf
DRDY
Sensor
Burn-Out
Currents
24-Bit
ûꢀ ADC
Digital
Filter
CS
Serial
Interface
+
PGA
AIN4
SCLK
AINCOM
DOUT/DRDY
DIN
CRC
Verification
Input
Mux
PGA
Monitor
AC
Exc
ADS1261
GPIO
Mux
Temp
Sensor
AIN5
AIN6
AIN7
AIN8
AIN9
Power
Supply
Clock
Mux
Internal
Oscillator
CLKIN
DGND
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9.3 Feature Description
The following sections describe the functional blocks of the ADC.
9.3.1 Analog Inputs
图 48 shows the analog input circuit consist of ESD-protection diodes, the input multiplexer and sensor burn-out
current sources. The ADS1260 has six analog inputs to support five single-ended measurement channels. The
ADS1261 has 11 analog inputs to support 10 single-ended measurement channels. Both devices have four
internal (system) measurements, and an option where no inputs are connected.
ESD Diodes
Positive Input Multiplexer
MUXP[3:0] bits 7:4 of INPMUX
(register address = 11h)
AVDD
Negative Input Multiplexer
0000
AINCOM
MUXN[3:0] bits 3:0 of INPMUX
0001
(register address = 11h)
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
0010
0011
0100
0101
0110
0111
1000
MUXP-OUT
MUXN-OUT
+
-
Sensor
Burn-Out
Currents
PGA
AIN6
AIN7
ADS1261
1001
1010
AIN8
AIN9
1011
1100
1101
1110
1111
Temperature Sensor
(AVDD œ AVSS) / 4
DVDD / 4
All Open
AVSS
VCOM: (AVDD + AVSS) / 2
ESD Diodes
图 48. Analog Input Block Diagram
9.3.1.1 ESD Diodes
ESD diodes are incorporated to protect the ADC inputs from possible ESD events occurring during the
manufacturing process and during PCB assembly when manufactured in an ESD-controlled environment. For
system-level ESD protection, consider the use of external ESD protection devices for pins that are exposed to
ESD, including the analog inputs.
If either input is driven below AVSS – 0.3 V, or above AVDD + 0.3 V, the internal protection diodes may conduct.
If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to
the specified maximum value.
9.3.1.2 Input Multiplexer
The input multiplexer selects the signal for measurement. The multiplexer consists of independent positive and
negative sections. See 图 48 for multiplexer register settings. The multiplexers select any input as positive and
any input as negative for the PGA. Because the level-shift voltage connects to AINCOM (only), AINCOM is
suitable as the common input for single-ended signals that require a level-shift voltage.
The switching sequence of the multiplexer is break-before-make in order to reduce charge injection into the next
measurement channel. Be aware that over-driving unused channels beyond the power supplies can effect
conversions taking place on active channels. See the Input Overload section for more information.
28
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ZHCSHW1C –MARCH 2018–REVISED JANUARY 2019
Feature Description (接下页)
9.3.1.3 Temperature Sensor
The ADC has an internal temperature sensor. The temperature sensor is comprised of two internal diodes with
one diode having 80 times the current density of the other. The difference in current density of the diodes yields
a differential output voltage that is proportional to absolute temperature. The temperature sensor reading is
converted by the ADC. See 图 48 for register settings to select the temperature sensor for measurement.
公式 2 shows how to convert the temperature sensor reading to degrees Celsius (˚C):
Temperature (°C) = [(Temperature Reading (µV) – 122,400) / 420 µV/°C] + 25°C
(2)
Measure the temperature sensor with PGA on, gain = 1, burn-out current sources disabled and AC-excitation
mode disabled. As a result of the low package-to-PCB thermal resistance, the internal temperature closely tracks
the PCB temperature. Be aware that device self-heating increases the internal temperature relative to the
surrounding PCB.
9.3.1.4 Power-Supply Readback
Read the power-supply voltage by the appropriate input multiplexer selection. The supply voltages are divided to
reduce the voltage levels to within the ADC input range. The analog and digital supply readback levels are
scaled by 公式 3 and 公式 4, respectively:
Analog supply (V) = (AVDD - AVSS) / 4
Digital supply (V) = DVDD / 4
(3)
(4)
Measure the power supply voltages with either the internal or an external reference. If using an external
reference, the minimum reference voltage is 1.5 V. Perform the measurement with PGA enabled, gain = 1, burn-
out current sources disabled and AC-excitation mode disabled. See 图 48 for register settings to measure the
supply voltages.
9.3.1.5 Inputs Open
This configuration opens all inputs. Use this configuration to test the functionality of the sensor burn-out current
sources, and the PGA output monitors. When the inputs are open, the current sources drive the PGA inputs to
full scale, resulting in an PGA monitor alarm and clipped conversion data. See 图 48 for register settings to open
all inputs.
9.3.1.6 Internal VCOM Connection
For this multiplexer configuration, all inputs are open and the PGA inputs are connected to an internal VCOM
voltage as defined: (AVDD + AVSS) / 2. Use this mode to measure the ADC noise performance and offset
voltage, or to short the inputs for offset calibration. See 图 48 for register settings of the internal VCOM
connection.
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Feature Description (接下页)
9.3.1.7 Alternate Functions
The ADC has several alternate functions that are multiplexed with the analog inputs. The alternate functions are
reference input, current source output, GPIO, AC-excitation and level-shift voltage output. The functions are
enabled by programming of the associated registers. The analog inputs retain measurement ability if the
alternate functions are programmed. 表 3 summarizes the alternate functions.
表 3. Analog Input Alternate Functions
ANALOG INPUTS
LEVEL-SHIFT
VOLTAGE
REFERENCE INPUTS
CURRENT SOURCES
GPIO/AC-EXCITATION(1)
ADS1260
AINCOM
AIN0
AIN1
AIN2
AIN3
AIN4
—
ADS1261
AINCOM
AIN0
—
REFP0
REFN0
REFP1(1)
REFN1(1)
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
—
—
—
—
—
—
—
—
—
—
—
AIN1
—
AIN2
GPIO0/ACX1
AIN3
GPIO1/ACX2
AIN4
GPIO2/ACX1
AIN5
—
GPIO3/ACX2
—
AIN6
—
—
—
—
—
—
AIN7
—
—
AIN8
—
—
AIN9
—
(1) ADS1261 and ADS1261B only.
9.3.2 PGA
The PGA is a low-noise, CMOS differential-input, differential-output amplifier. The PGA extends the dynamic
range of the ADC, important when used with low level sensors. The PGA provides gains of 1 through 32 and the
ADC provides additional gains of 2 and 4. The combined gains are 1 through 128. Gain is controlled by the
GAIN[2:0] register bits as shown in 图 49. In PGA bypass mode, the input voltage range extends to the analog
supplies. The PGA is powered down in bypass mode.
BYPASS bit 7 of PGA
(register address = 10h)
0: PGA active (shown)
1: PGA bypass
280 Ω
350 Ω
VAINP
+
A1
œ
8 pF
CAPP
GAIN[2:0] bits 2:0 of PGA
12 pF
(register address = 10h)
000: 1
001: 2
010: 4
011: 8
PGA
Output
Monitors
4.7 nF
C0G
ADC
12 pF
100: 16
101: 32
110: 64
111:128
12 pF
œ
A2
+
CAPN
350 Ω
280 Ω
VAINN
8 pF
图 49. PGA Block Diagram
30
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The PGA consists of two chopper-stabilized amplifiers (A1 and A2), and a resistor network that determines the
PGA gain. The resistor network is precision matched, providing low drift performance. The PGA integrates noise
filters to reduce sensitivity to electromagnetic-interference (EMI). The PGA output is monitored to indicate when
the operating headroom is exceeded.
Pins CAPP and CAPN are the PGA positive and negative outputs, respectively. Connect an external 4.7-nF
capacitor (type C0G) as shown in 图 49. The capacitor filters the modulator sample pulses and with the internal
resistors, forms the antialias filter. Place the capacitor as close as possible to the pins using short traces. Avoid
running clock traces or other digital traces close to these pins.
The full-scale differential input voltage range of the ADC is determined by the reference voltage and gain. 表 4
shows the differential input voltage range verses gain for VREF = 2.5 V.
表 4. Full-Scale Voltage Range
GAIN[2:0] BITS
GAIN
1
FULL-SCALE DIFFERENTIAL INPUT RANGE(1)
000
001
010
011
100
101
110
111
±2.500 V
±1.250 V
±0.625 V
±0.312 V
±0.156 V
±0.078 V
±0.039 V
±0.0195 V
2
4
8
16
32
64
128
(1) VREF = 2.5 V. Full scale differential input voltage range is proportional to VREF
.
As with many amplifiers, the PGA has an input voltage range limitation that must not be exceeded in order to
maintain linear operation. The specified input voltage range is expressed as the absolute voltage at the positive
and negative inputs. As specified in 公式 5, the specified absolute input voltage depends on gain, the expected
maximum differential voltage, and the minimum analog power-supply voltage.
AVSS + 0.3 V + VIN · (Gain – 1) / 2 · < VAINP and VAINN < AVDD – 0.3 V – VIN · (Gain – 1) / 2
where
•
•
•
•
•
VAINP, VAINN = absolute input voltage
VIN = maximum differential input voltage = VAINP - VAINN
Gain (for gains = 64 and 128, use gain = 32 in the calculation)
AVDD = minimum AVDD voltage
AVSS = maximum AVSS voltage
(5)
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The relationship of the PGA input to the PGA output is shown graphically in 图 50. The PGA output voltages
(VOUTP, VOUTN) depend on the respective absolute input voltage, the differential input voltage, and the PGA gain.
To maintain the PGA within the linear operating range, the PGA output voltages must not exceed either AVDD –
0.3 V or AVSS + 0.3 V. The diagram depicts a positive differential input voltage that results in a positive
differential output voltage.
PGA Input
PGA Output
AVDD
AVDD œ 0.3 V
VOUTP = VAINP + VIN ‡ (Gain œ 1) / 2
VAINP
VIN = VAINP ‡ VAINN
VAINN
VOUTN = VAINN œ VIN ‡ (Gain œ 1) / 2
AVSS + 0.3 V
AVSS
图 50. PGA Input/Output Range
9.3.2.1 PGA Bypass Mode
Bypass the PGA to extend the input voltage range up to the analog power supply voltages. In bypass mode, the
PGA is bypassed and the analog inputs are connected directly to the precharge buffers of the modulator, thereby
extending the input voltage range. Be aware of the increased analog input current in bypass mode. See the
Recommended Operating Conditions for the bypass-mode input voltage range specification, and see the
Electrical Characteristics for the input current specification.
9.3.2.2 PGA Voltage Monitor
The PGA has voltage monitors to provide indication when the PGA is overloaded. In overload condition, the
conversion data are no longer valid. If either the PGA positive or negative output exceeds AVDD – 0.2 V, the
high alarm bit is set (PGAH_ALM). Similarly, if either PGA positive or negative output is less than AVSS + 0.2 V,
the low alarm bit is set (PGAL_ALM). The monitor alarm state is read in the STATUS byte. The monitor alarm is
read-only and automatically resets at the start of the next conversion cycle after the overload condition is cleared.
The monitor diagram and threshold values are shown in 图 51 and 图 52.
PGAH_ALM Condition
AVDD œ 0.2 V
œ
+
PGAH_ALM
AVDD
AVDD t 0.2 V
œ
PGA Output
P or N
STATUS Byte
P
N
+
PGA
6
5
3
7
4
2
1
0
P or N
œ
+
AVSS + 0.2 V
AVSS
PGAL_ALM
œ
+
AVSS + 0.2 V
PGAL_ALM Condition
图 51. PGA Monitor Diagram
图 52. PGA Monitor Thresholds
The PGA monitors consist of fast-responding voltage comparators. Comparator operation is disabled during
multiplexer changes to minimize the false triggering during these input switching events. However, it is possible
the monitors can detect other transient overload conditions that may occur after gain changes, sensor connection
changes, and so on.
32
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9.3.3 Reference Voltage
The ADC requires a reference voltage for operation. The reference voltage options are 2.5-V internal, one or two
external inputs (ADS1260 or ADS1261, respectively) or the 5-V analog power supply. The reference voltage is
selected by independent positive and negative reference multiplexers for the reference positive and reference
negative voltages, respectively. The default reference is the 5-V analog power supply (AVDD – AVSS). 图 53
shows the block diagram of the reference multiplexer.
REFENB bit 4 of REF
(register address = 06h)
2.5 V
Internal
Ref
AVDD
0: Internal Ref off
1: Internal Ref on (default)
RMUXP[1:0] bits 3:2 of REF
(register address = 06h)
REFOUT
00
01
VREFP
10
(2)11
AIN0
AIN2
(1)
10 mF
BUF
00
01
AVSS
ADC
10
(2) 11
VREFN
AIN1
AIN3
RMUXN[1:0] bits 1:0 of REF
(register address = 06h)
(1) The internal reference requires a 10-µF capacitor connected to pins REFOUT and AVSS.
(2) ADS1261 only.
图 53. Reference Input Diagram
Program the RMUXP[1:0] and RMUXN[1:0] bits of the REF register to select the positive and negative reference
voltages, respectively. The positive reference selections are internal positive, AIN0, AIN2, or AVDD. The negative
reference input selections are internal negative, AIN1, AIN3, or AVSS. The reference low-voltage monitor is
located after the reference multiplexer. See the Reference Monitor section for more information.
9.3.3.1 Internal Reference
The ADC incorporates a 2.5-V reference that is enabled by the REFENB bit of the REF register (default = off).
Program the reference multiplexer bits RMUXP[1:0] and RMUXN[1:0] to 00b to select the internal reference. A
10-μF capacitor is required between pins REFOUT and AVSS to filter reference noise. REFOUT is the reference
output and AVSS is the reference return. Use a star-layout connection or plane connection for the reference
return, connecting close to the AVSS pin. When the reference is enabled, be aware of the settling time before
beginning conversions. Also be aware of the reference inrush current that may result in a transient droop of the
AVDD voltage. Enable the internal reference for sensor excitation current source operation.
9.3.3.2 External Reference
Use an external reference by applying the reference voltage to the designated analog inputs. The reference
inputs are differential with positive and negative inputs. Program the reference multiplexer bits RMUXP[1:0] and
RMUXN[1:0] to 10b or 11b to select inputs AIN0/AIN1 or AIN2/AIN3, respectively (AIN2/AIN3 is available only for
the ADS1261). For application that use multiple references, it is possible to connect the reference grounds
together and use a single input pin for ground. Follow the specified absolute and differential reference voltage
operating conditions, as specified in the Recommended Operating Conditions. Connect a 100-nF capacitor
across the reference input pins to filter noise. Be aware of the reference input current if reference impedances
are present. Consider the error to the overall system accuracy.
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9.3.3.3 AVDD - AVSS Reference (Default)
A third reference option is the 5-V analog power supply (AVDD - AVSS). Select this reference option by setting
the reference multiplexer bits RMUXP[1:0] and RMUXN[1:0] to 01b. For a 6-wire load cell application that uses
excitation sense lines, or for AC-excitation operation, connect the excitation sense lines to the analog input
reference inputs and program the ADC for external reference operation.
9.3.3.4 Reference Monitor
The ADC incorporates a reference monitor that detects an invalid reference voltage. As shown in 图 54 and 图
55, if the reference voltage (VREF = VREFP – VREFN) is below 0.4 V, the REFL_ALM bit is set in the STATUS byte.
The alarm is read-only and resets at the next conversion after the low reference condition is cleared.
Use the reference monitor to detect a missing or failed reference voltage. To implement detection of a missing
reference, use a 100-kΩ resistor across the reference inputs. If either input is unconnected, the resistor biases
the differential reference input towards 0 V so that the missing reference can be detected.
STATUS Byte
Differential
Reference Voltage
6
5
3
7
4
2
1
0
AIN0
100 kꢀ
AIN1
+
0.4 V, Typical
REFL_ALM
Ref
MUX
+
_
External
_
+
Reference
_
0.4 V
Reference Low Condition
图 54. Reference Monitor
9.3.4 Level-Shift Voltage (VBIAS)
图 55. Reference Monitor Threshold
The ADC integrates a level-shift voltage that can be connected to the AINCOM pin by an internal switch. As
shown in 图 56, the level-shift voltage is the mid-voltage between AVDD and AVSS. The purpose of the voltage
is to shift the signal level of floating sensors to within the input range of the ADC. Isolated thermocouples and
piezoelectric sensors are examples of sensors that are suitable for connection to the level-shift voltage. For these
sensors, connect the negative lead to the AINCOM pin and enable the level-shift voltage.
AINCOM
100 Ω
V = (AVDD + AVSS) / 2
VBIAS bit 4 of INPBIAS
(register address = 12h)
0: off (default)
1: on
图 56. Level-Shift Voltage Diagram
The turn-on time of the level-shift voltage depends on the total external capacitance connected from the AINCOM
pin to ground or AVSS. 表 5 lists the level-shift voltage settling times for various load capacitance. Be certain the
level-shift voltage is fully settled before starting a conversion.
表 5. Level-Shift Enable Time
LOAD CAPACITANCE
LEVEL-SHIFT VOLTAGE SETTLING TIME
0.1 µF
1 µF
0.22 ms
2.2 ms
22 ms
10 µF
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9.3.5 Burn-Out Current Sources
The burn-out current sources are used to detect the occurrence of sensor burn-out or break. If the sensor or
sensor connection is open, the currents drive either or both positive and negative PGA inputs to opposite supply
voltages where the occurrence of an open sensor is detected by the PGA monitors or detected by the host for
out-of-range (or clipped) conversion data.
图 57 shows the burn-out currents connect at the output of the analog input multiplexer. The currents sink and
source, and are configurable in pullup or pulldown mode. In pullup mode, the sourcing current connects to the
positive input channel and the sinking current connects to the negative input channel. In this configuration, an
open circuit pulls the inputs to positive full scale. The currents are Off, 0.050 µA, 0.2 µA, 1 µA, and 10 µA. See
the Burn-Out Current Source section for application information.
AVDD
BOCS[2:0] bits 2:0 of INPBIAS
(register address = 12h)
000: off
001: 0.05 uA
010: 0.2 uA
MUXP
011: 1 uA
100: 10 uA
AIN0
AINP
AINN
PGA
AINCOM
BOCSP bit 3 of INPBIAS
(register address = 12h)
MUXN
0 = Pull-up mode (shown)
1 = Pull-down Mode
AVSS
图 57. Burn-Out Current Sources
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9.3.6 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
The ADC incorporates two current sources that are used to provide excitation current to a resistive temperature
device (RTD), thermistor, diode and other sensor type that require constant current biasing. The currents are
programmable over the 50 μA to 3000 μA range and are internally multiplexed to all analog input pins. The
current source multiplexer is shown in 图 58. The IMUX1 and IMUX2 register bits connect the corresponding
current source to the analog inputs. The IMAG1 and IMAG2 register bits program the corresponding current
magnitude.
Enable the internal reference for current source operation. The current source value can be doubled or an
intermediate value produced by connecting the current sources to the same analog input. Take care not to
exceed the current source compliance voltage range. That is, when the current source is loaded by resistance,
the voltage at the pin increases and must not exceed specification; otherwise the specified current source
accuracy is not met.
IDAC1
IMUX1[3:0] bits 3:0 of IMUX
(register address = 0Dh)
IDAC2
IMUX2[3:0] bits 7:4 of IMUX
(register address = 0Dh)
AVDD
0000
0001
0010
0011
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
IDAC1
IMAG1[3:0] bits 3:0 of IMAG
(register address = 0Eh)
0000: Off
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
0100
0101
AVDD
0110
0111
1000
IDAC2
ADS1261
IMAG2[3:0] bits 7:4 of IMAG
(register address = 0Eh)
1001
1010
1111
AINCOM
Open
图 58. Current Source Connection
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9.3.7 General-Purpose Input/Outputs (GPIOs)
The ADS1261 and ADS1261B devices provide four GPIO pins, GPIO0 through GPIO3. The GPIOs are digital
inputs/outputs that are referenced to analog AVDD and AVSS. The GPIOs are read and written by the
GPIO_DAT bits of register MODE3. The GPIOs are multiplexed with analog inputs AIN2 to AIN5. As shown in 图
59, the GPIOs have a series of programming registers. Bits GPIO_CON[3:0] connect the GPIOs to the
associated pin (1 = connect). Bits GPIO_DIR program the direction of the GPIOs; (0 = output, 1 = input). The
input voltage threshold is the voltage value between AVDD and AVSS. Bits GPIO_DAT[3:0] are the data values
for the GPIOs. Observe that if a GPIO pin is programmed as an output, the value read is the value previously
written to the register data, not the actual state of the pin.
The GPIOs also provide the AC-excitation drive signals. AC-excitation mode override the GPIO register data
values. See the AC-Excitation Mode section for details.
AVDD
Write
AC-Excitation Mode
CHOP[1:0] bits 6:5 of MODE1
(register address = 03h)
GPIO_CON[3:0] bits 7:4 of MODE2
(register address = 04h)
GPIO_DAT[3:0] bits 3:0 of MODE3
(register address = 05h)
00: Normal mode (default)
01: Chop mode
10: 2-wire AC-excitation mode
11: 4-wire AC-excitation mode
Write
0: GPIO not connected (default)
1: GPIO connected
0: VGPIO low (default)
1: VGPIO high
0
Read
GPIO0
AIN2
AIN3
AIN4
1
GPIO1
GPIO2
GPIO_DIR[3:0] bits 3:0 of MODE2
+
MUX
Read Select
(register address = 04h)
GPIO3
œ
AIN5
0: GPIO is output (default)
1: GPIO is input
AVDD + AVSS
2
AVSS
图 59. GPIO Block Diagram
9.3.8 Oversampling
The ADC operates on the principle of oversampling, defined as the ratio of the sample rate of the modulator to
that of the ADC output data rate. Oversampling improves ADC noise by digital bandwidth limiting (low-pass
filtering) of the data. The digital filter also performs data rate reduction (decimation) in order to reduce the data
rate proportional with the amount of data filtering.
9.3.9 Modulator
The modulator is an inherently stable, fourth-order, 2 + 2 pipelined ΔΣ modulator. The modulator samples the
analog input voltage at a high sample rate (fMOD = fCLK / 8) and converts the analog input to a ones-density bit-
stream given by the ratio of the input signal to the reference voltage. The modulator shapes the noise of the
converter to high frequency, where the noise is removed by the digital filter.
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9.3.10 Digital Filter
The digital filter receives the modulator output data and produces a high-resolution conversion result. The digital
filter low-pass filters and decimates the modulator data (data rate reduction), yielding the final data output. By
adjusting the type of filtering, tradeoffs are made between resolution, data throughput and line cycle rejection.
The digital filter has two selectable modes: sin (x) / x (sinc) mode and finite impulse response (FIR) mode (see
图 60). The sinc mode provides data rates of 2.5 SPS through 40000 SPS with variable sinc orders of 1 through
5. The FIR filter provides simultaneous rejection of 50-Hz and 60-Hz frequencies with data rates 2.5 SPS through
20 SPS while providing single-cycle settled conversions.
Sinc Filter Section
40000 SPS to 14400 SPS
fCLK / 8
7200 SPS to 2.5 SPS
Modulator
Sinc5 Filter
SincN Filter
To Offset/Gain
Calibration
Filter
Mux
FIR Filter Section
20 SPS
(
= Data rate reduction)
FIR
Averager
10 SPS
5 SPS
2.5 SPS
图 60. Digital Filter Block Diagram
9.3.10.1 Sinc Filter
The sinc filter is composed of two stages: a variable-decimation sinc5 filter, followed by a variable-decimation,
variable-order sinc filter. The first stage filters and down-samples the modulator data to yield data rates of
40000 SPS, 25600 SPS, 19200 SPS, and 14400 SPS. These data rates bypass the second stage and as a
result have a sinc5 characteristic filter response. The second stage receives data from the first stage at a fixed
rate of 14400 SPS. The data rate is reduced to the range 7200 SPS to 2.5 SPS, with programmable orders of
sinc.
The data rate is programmed by the DR[4:0] bits of register MODE0. The filter mode is programmed by the
FILTER[2:0] bits of register MODE0 (see 表 32).
9.3.10.1.1 Sinc Filter Frequency Response
The characteristic of the sinc filter is low pass. The filter reduces noise present in the signal and noise present
within the ADC. Changing the data rate and filter order changes the filter bandwidth.
As shown in 图 61 and 图 62, the first-stage sinc5 filter has frequency response nulls occurring at N · fDATA
,
where N = 1, 2, 3 and so on. At the null frequencies, the filter has zero gain. Data rates of 25600 SPS and 19200
SPS have similar frequency response.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
D201
D002
图 62. Frequency Response (14400 SPS)
图 61. Frequency Response (40000 SPS)
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The second stage superimposes frequency response nulls to the nulls of the first stage 14400 SPS output. The
first of the superimposed response nulls occurs at the data rate, followed by nulls occurring at multiples of the
data rate. 图 63 illustrates the frequency response for various orders of sinc at data rate of 2400 SPS. This data
rate has five nulls between the larger nulls at multiples of 14400 Hz. This frequency response is similar to that of
data rates 2.5 SPS to 7200 SPS. 图 64 shows the frequency response nulls for 10 SPS.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
20
25
30
35
40
45
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (Hz)
Frequency (kHz)
D003
D004
图 63. Sinc Frequency Response (2400 SPS)
图 64. Sinc Frequency Response (10 SPS)
图 65 and 图 66 show the frequency response of data rates 50 SPS and 60 SPS, respectively. Increase the
attenuation at 50 Hz or 60 Hz and harmonics by increasing the order of the sinc filter, as shown in the figures.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (Hz)
0
60 120 180 240 300 360 420 480 540 600
Frequency (Hz)
D005
D006
图 65. Sinc Frequency Response (50 SPS)
图 66. Sinc Frequency Response (60 SPS)
图 67 and 图 68 show the detailed frequency response at 50 SPS and 60 SPS, respectively.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
45
46
47
48
49
50
51
52
53
54
55
55
56
57
58
59
60
61
62
63
64
65
Frequency (Hz)
Frequency (Hz)
D009
D010
图 67. Detail Sinc Frequency Response (50 SPS)
图 68. Detail Sinc Frequency Response (60 SPS)
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9.3.10.2 FIR Filter
The finite impulse response (FIR) filter is a coefficient based filter architecture that provides an overall low-pass
filter response. The filter provides simultaneous attenuation of 50 Hz and 60 Hz and harmonics at data rates of
20 SPS to 2.5 SPS. The conversion latency time of the FIR filter data rates are single-cycle. As shown in 图 60,
the FIR filter receives pre-filtered data from the sinc filter. The FIR filter decimates the data to yield the output
data rates of 20 SPS. A variable averager (sinc1) provides data rates of 10 SPS, 5 SPS, and 2.5 SPS. 表 6 lists
the bandwidth of the data rates in FIR filter mode.
9.3.10.2.1 FIR Filter Frequency Response
图 69 and 图 70 show the FIR filter frequency attenuates 50 Hz and 60 Hz by a series of response nulls placed
close to these frequencies. The response nulls are repeated at harmonics of 50 Hz and 60 Hz.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
40
45
50
55
60
65
70
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
Frequency (Hz)
D012
D011
图 70. FIR Frequency Response Detail (20 SPS)
图 69. FIR Frequency Response (20 SPS)
图 71 is the FIR filter response at 10 SPS. As a result of the variable averager, new frequency nulls are
superimposed. The first null appears at the date rate. Additional nulls occur at frequencies folded around
multiples of 20 Hz.
0
-20
-40
-60
-80
-100
-120
-140
-160
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
D013
图 71. FIR Frequency Response (10 SPS)
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9.3.10.3 Filter Bandwidth
The bandwidth of the filter depends on the data rate and the filter mode. Be aware that the bandwidth of the
entire system is the combined response of the filter, the antialias filter and external filters. 表 6 lists the bandwidth
versus data rate and filter mode. 表 6 also lists the filter modes available for each data rate.
表 6. Filter Bandwidth
-3-dB BANDWIDTH (Hz)
DATA RATE
(SPS)
2.5
FIR
1.2
2.4
4.7
—
SINC1
1.10
2.23
4.43
7.38
8.85
22.1
26.6
44.3
177
525
1015
1798
2310
—
SINC2
0.80
1.60
3.20
5.33
6.38
16.0
19.1
31.9
128
381
751
1421
1972
—
SINC3
0.65
1.33
2.62
4.37
5.25
13.1
15.7
26.2
105
314
623
1214
1750
—
SINC4
0.58
1.15
2.28
3.80
4.63
11.4
13.7
22.8
91.0
273
544
1077
1590
—
SINC5
—
5
—
10
—
16.6
20
—
13
—
—
50
—
60
—
—
100
—
—
400
—
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
—
—
—
—
—
2940
3920
5227
8167
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
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9.3.10.4 50-Hz and 60-Hz Normal Mode Rejection
To reduce 50-Hz and 60-Hz noise interference, configure the conversion period to reject the noise at 50 Hz and
60 Hz. 50-Hz and 60-Hz noise rejection depends on the filter type. 表 7 summarizes the 50-Hz and 60-Hz noise
rejection versus data rate and filter type. The table values are based on 2% and 6% tolerance of noise frequency
to ADC clock frequency. For the sinc filter mode, noise rejection is increased by increasing the order of the filter.
Common mode noise is also rejected at these frequencies.
表 7. 50-Hz and 60-Hz Normal Mode Rejection
DIGITAL FILTER RESPONSE (dB)
DATA RATE (SPS)
FILTER TYPE
FIR
50 Hz ±2%
–113
–36
60 Hz ±2%
–99
50 Hz ±6%
–88
–40
–80
–120
–160
–77
–30
–60
–90
–120
–73
–25
–50
–75
–100
–24
–48
–72
–96
–66
–18
–36
–54
–72
–24
–48
–72
–96
–12
–24
–36
–48
60 Hz ±6%
–80
–37
–74
–111
–148
–76
–30
–60
–90
–120
–68
–25
–50
–75
–100
–21
–42
–63
–84
–66
–24
–48
–72
–96
–15
–30
–45
–60
–24
–48
–72
–96
2.5
2.5
2.5
2.5
2.5
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–37
–72
–74
–108
–144
–111
–34
–111
–148
–95
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
5
–68
–68
5
–102
–136
–111
–34
–102
–136
–94
5
10
10
10
10
10
16.6
16.6
16.6
16.6
20
20
20
20
20
50
50
50
50
60
60
60
60
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
–68
–68
–102
–136
–34
–102
–136
–21
–68
–42
–102
–136
–95
–63
–84
–94
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
–18
–34
–36
–68
–54
–102
–136
–15
–72
–34
–68
–30
–102
–136
–13
–45
–60
–34
–27
–68
–40
–102
–136
–53
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9.4 Device Functional Modes
9.4.1 Conversion Control
Conversions are controlled by either the START pin or by the START command. If using commands to control
conversions, keep the START pin low to avoid contentions between pin and commands. Commands take affect
on the 16th falling SCLK edge (CRC mode disabled) or on the 32nd falling SCLK edge (CRC mode enabled).
See 图 4 for conversion-control timing details.
The ADC provides two conversion modes: continuous and pulse. The continuous-conversion mode performs
conversions indefinitely until stopped by the user. Pulse-conversion mode performs one conversion and then
stops. The conversion mode is programmed by the CONVRT bit (bit 4 of register MODE0).
9.4.1.1 Continuous-Conversion Mode
This conversion mode performs continuous conversions until stopped by the user. To start conversions, take the
START pin high or send the START command. DRDY is driven high at the time the conversion is initiated. DRDY
is driven low when the conversion data are ready. Conversion data are available to read at that time.
Conversions are stopped by taking the START pin low or by sending the STOP command. When conversions
are stopped, the conversion in progress runs to completion. To restart a conversion that is in progress, toggle the
START pin low-then-high or send a new START command.
9.4.1.2 Pulse-Conversion Mode
In pulse-conversion mode, the ADC performs one conversion when START is taken high or when the START
command is sent. When the conversion completes, further conversions stop. The DRDY output is driven high to
indicate the conversion is in progress, and is driven low when the conversion data are ready. Conversion data
are available to read at that time. To restart a conversion in progress, toggle the START pin low-then-high or
send a new START command. Driving START low or sending the STOP command does not interrupt the current
conversion.
9.4.1.3 Conversion Latency
The digital filter averages data from the modulator in order to produce the conversion result. The stages of the
digital filter must have settled data in order to provide fully-settled output data. The order and the decimation ratio
of the digital filter determine the amount of data averaged, and in turn, affect the latency of the conversion data.
The FIR and sinc1 filter modes are zero latency because the ADC provides the conversion result in one
conversion cycle. Latency time is an important consideration for the data throughput rate in multiplexed
applications.
表 8 lists the conversion latency values of the ADC. Conversion latency is defined as the time from the start of
the first conversion, by taking the START pin high or sending the START command, to the time when the
conversion data are ready. If the input signal is settled, then the ADC provides fully settled data under this
condition. The conversion latency values listed in the table are with the start-conversion delay parameter = 50 µs,
and include the overhead time needed to process the data. After the first conversion completes (in continuous
conversion mode), the period of the following conversions are equal to 1/fDATA. The first conversion latency in
chop and AC-excitation modes are twice the values listed in the table. Also when operating in these modes, the
period of the following conversions are equal to the values listed in the table.
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Device Functional Modes (接下页)
表 8. Conversion Latency
CONVERSION LATENCY - t(STDR)(1) (ms)
DATA RATE
(SPS)
FIR
402.2
202.2
102.2
—
SINC1
400.4
200.4
100.4
60.43
50.43
20.43
17.09
10.43
2.925
1.258
0.841
0.633
0.564
—
SINC2
800.4
400.4
200.4
120.4
100.4
40.43
33.76
20.43
5.425
2.091
1.258
0.841
0.702
—
SINC3
1,200
600.4
300.4
180.4
150.4
60.43
50.43
30.43
7.925
2.925
1.675
1.050
0.841
—
SINC4
1,600
800.4
400.4
240.4
200.4
80.43
67.09
40.43
10.43
3.758
2.091
1.258
0.980
—
SINC5
—
2.5
5
—
10
—
16.6
20
—
52.23
—
—
50
—
60
—
—
100
—
—
400
—
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
—
—
—
—
—
0.423
0.336
0.271
0.179
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1) Chop mode off, conversion-start delay = 50 µs (DELAY[3:0] = 0001)
If the input signal changes while free-running conversions, the conversion data are a mix of old and new data, as
shown in 图 72. After an input change, the number of conversion periods required for fully settled data are
determined by dividing the conversion latency by the period of the data rate, plus add one conversion period to
the result. In chop mode and AC-excitation mode, use twice the latency values listed in the table.
Old VIN
New VIN
VIN = VAINP - VAINN
Fully settled
new data
Mix of old data
and new data
Old data
DRDY pin
图 72. Input Change During Conversions
9.4.1.4 Start-Conversion Delay
Some applications may require a delay at the start of a conversion in order to allow settling time for the PGA
output antialias filter or to allow time after input and configuration changes. The ADC provides a user
programmable delay time that delays the start of a new conversion. The default value is 50 μs. This allows for
settling of the antialiasing filter. Use additional delay time as needed to provide settling time for external
components. The delay time increases the conversion latency values listed in 表 8. As an alternative to the
programmable start-conversion delay, manually delay the start of conversion after input and configuration
changes.
Start-conversion delay is an important consideration for operation in AC-excitation mode. In this mode, the
reference inputs to the bridge, and therefore, the bridge output signals are reversed for each conversion As a
result, time delay is required to allow for settling of external filter components after reversal. As a general
guideline, set the start-conversion delay parameter to a minimum of 15 times the R-C time constant of the signal
input and reference input filters.
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9.4.2 Chop Mode
The PGA and modulator are chopper-stabilized at high frequency in order to reduce offset voltage, offset voltage
drift and 1/f noise. The offset and noise artifacts are modulated to high frequency and are removed by the digital
filter. Although chopper stabilization is designed to remove all offset, a small offset voltage may remain. The
optional global chop mode removes the remaining offset errors, providing exceptional offset voltage drift
performance.
Chop mode alternates the signal polarity of consecutive conversions. The ADC subtracts consecutive, alternate-
phase conversions to yield the final conversion data. The result of subtraction removes the offset.
CHOP[1:0] bits 6:5 of MODE1
(register address = 03h)
00: Normal mode
01: Chop mode
10: 2-wire AC excitation mode
11: 4-wire AC excitation mode
Chop Switch
VOFS
AIN0
VAINP
-
+
Digital
Filter
Full-Scale
Cal
Input
MUX
Chop
Control
C
A D
Offset
Cal
Conversion
Output
ADC
PGA
VAINN
AINCOM
图 73. ADC Chop Mode
As shown in 图 73, the internal chop switch reverses the signal after the input multiplexer. VOFS models the
internal offset voltage. The operational sequence of chop mode is as follows:
Conversion C1: VAINP – VAINN – VOFS → First conversion withheld after start
Conversion C2: VAINN – VAINP – VOFS → Output 1 = (C1 – C2) / 2 = VAINP – VAINN
Conversion C3: VAINP – VAINN – VOFS → Output 2 = (C3 – C2) / 2 = VAINP – VAINN
The sequence repeats for all conversions. Because of the internal mathematical operations, the chop mode data
rate is reduced. The chop mode data rate is proportional to the order of the sinc filter. Referring to 表 8, the new
data rate is equal to 1 / latency values and the first conversion latency is 2 × latency values. Because of the two-
point data averaging arising from the mathematical operations, noise is reduced by √2. For chop mode, divide
the noise data values shown in 表 1 by √2 to derive the new noise performance data. The null frequencies of the
digital filter are not changed in chop-mode operation. However, new null frequencies appear at multiples of fDATA
/ 2.
9.4.3 AC-Excitation Mode
Resistive bridge sensors are excited by DC or AC voltages; for DC or AC currents. DC voltage excitation is the
most common type of excitation. AC excitation reverses the polarity of the voltage by the use of external
switching components. Similar in concept to chop mode, the result of the voltage reversal removes offset voltage
in the connections leading from the bridge to the ADC inputs. This removal includes the offset voltage of the ADC
itself. The ADS1261 and ADS1261B devices provide the signals necessary to drive the external switching
components in order to reverse the bridge voltage.
The timing of the drive signals is synchronized to the ADC conversion phase. During one conversion phase, the
voltage polarity is normal. For the alternate conversion phase, the voltage polarity is reversed. The ADC
compensates the reversed polarity conversion by internal reversal of the reference voltage. The ADC subtracts
the data corresponding to the normal and reverse phases in order to remove offset voltage from the input.
The ADC output drive signals do not overlap in order to avoid bridge cross-conduction that can otherwise occur
during excitation voltage reversal. The switch rate of the AC-excitation drive signals are at the data rate to avoid
unnecessary fast switching. See 图 7 for output drive timing.
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表 9 shows the AC-excitation drive signals and the associated GPIO pins. Program the AC-excitation mode using
the CHOP[1:0] bits in register MODE1. AC excitation can be programmed for two-wire or four-wire drive mode.
For two-wire operation, two drive signals are provided on the GPIOs. If needed, use two external inverters to
derive four signals to drive discrete transistors. The GPIO drive levels are referred to the 5-V analog supply. Be
aware that the AC-excitation mode changes the nominal data rate, depending on the order of the sinc filter. See
the Chop Mode section for details of the effective data rate.
表 9. AC-Excitation Drive Pins
DEVICE PIN
AIN2
GPIO
GPIO0
GPIO1
GPIO2
GPIO3
2-WIRE MODE (CHOP[1:0] = 10)
4-WIRE MODE (CHOP[1:0] = 11)
ACX1
ACX2
—
ACX1
ACX2
ACX1
ACX2
AIN3
AIN4
AIN5
—
9.4.4 ADC Clock Mode
Operate the ADC with an external clock or with the internal oscillator. The clock frequency is 7.3728 MHz, except
for fDATA = 40000 SPS then fCLK = 10.24 MHz (internal or external). For external clock operation, apply the clock
signal to CLKIN. For internal-clock operation, connect CLKIN to DGND. The internal oscillator begins operation
immediately at power-up. The ADC automatically selects the clock mode of operation. Read the clock mode bit in
the STATUS register to determine the clock mode.
9.4.5 Power-Down Mode
The ADC has two power-down modes: hardware and software. In both power-down modes, the digital outputs
remain driven. The digital inputs must be maintained at VIH or VIL levels (do not float the digital inputs). The
internal low-dropout regulator remains on, drawing 25 µA (typical) from DVDD.
9.4.5.1 Hardware Power-Down
Take the PWDN pin low to engage hardware power-down mode. Except for the internal LDO, all ADC functions
are disabled. To exit hardware power-down mode (wake-up) take the PWDN pin high. The register values are
not reset at wake-up. The internal reference is shut down in this mode; therefore, be sure to accommodate the
start-up time of the internal reference before starting conversions.
9.4.5.2 Software Power-Down
Set the PWDN bit (bit 7 of register MODE3) to engage software power-down mode. Similar to the operation of
hardware power-down mode, software mode powers down the internal functions except the serial interface
remains powered, and the internal reference bias is unchanged (On or Off). Exit the software power-down mode
by clearing the PWDN bit. The register values are not reset.
9.4.6 Reset
The ADC is reset in three ways: at power-on, by the RESET pin, and by the RESET command. When reset, the
serial interface, conversion-control logic, digital filter, and register values are reset. The RESET bit of the
STATUS byte is set to indicate a device reset has occurred by any of the three reset methods. Clear the bit to
detect the next device reset. If the START pin is high after reset, the ADC begins conversions.
9.4.6.1 Power-on Reset
At power-on, after the supply voltages cross the reset-voltage thresholds, the ADC is reset and 216 fCLK cycles
later the ADC is ready for communication. Until this time, DRDY is held low. DRDY is driven high to indicate
when the ADC is ready for communication. If the START pin is high, the conversion cycle starts 512 / fCLK cycle
after DRDY asserts high. 图 5 shows the power-on reset behavior.
9.4.6.2 Reset by Pin
Reset the ADC by taking the RESET pin low and then returning the pin high. After reset, the conversion starts
512 / fCLK cycles later. See 图 6 for RESET timing.
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9.4.6.3 Reset by Command
Reset the ADC by the RESET command. Toggle CS high to make sure the serial interface resets before sending
the command. For applications that tie CS low, see the Serial Interface Auto-Reset section for information on
how to reset the serial interface. After reset, the conversion starts 512 / fCLK cycles later. See 图 6 for timing
details.
9.4.7 Calibration
The ADC incorporates calibration registers and associated commands to calibrate offset and full-scale errors.
Calibrate by using calibration commands, or calibrate by writing to the calibration registers directly (user
calibration). To calibrate by command, send the offset or full-scale calibration commands. To user calibrate, write
values to the calibration registers based on calculations of the conversion data. Perform offset calibration before
full-scale calibration.
9.4.7.1 Offset and Full-Scale Calibration
Use the offset and full-scale (gain) registers to correct offset or full-scale errors, respectively. As shown in 图 74,
the offset calibration register is subtracted from the output data before multiplication by the full-scale register,
which is divided by 400000h. After the calibration operation, the final output data are clipped to 24 bits.
VAINP
C A D
+
Output Data
Clipped to 24 bits
Digital
Filter
Final
Output
ADC
ꢀ
VAINN
-
1/400000h
OFCAL[2:0] registers
(register addresses = 07h, 08h, 09h)
FSCAL[2:0] registers
(register addresses = 0Ah, 0Bh, 0Ch)
图 74. Calibration Block Diagram
公式 6 shows the internal calibration.
Final Output Data = (Filter Output - OFCAL[2:0]) · FSCAL[2:0] / 400000h
(6)
9.4.7.1.1 Offset Calibration Registers
The offset calibration word is 24 bits, consisting of three 8-bit registers, as listed in 表 10. The offset value is
subtracted from the conversion result. The offset value is in two's complement format with a maximum positive
value equal to 7FFFFFh, and a maximum negative value equal to 800000h. A register value equal to 000000h
has no offset correction. Although the offset calibration register provides a wide range of possible offset values,
the input signal after calibration cannot exceed ±106% of the pre-calibrated range; otherwise, the ADC is
overranged. 表 11 lists example values of the offset register.
表 10. Offset Calibration Registers
BYTE
REGISTER
OFCAL0
OFCAL1
OFCAL2
ORDER
ADDRESS
07h
BIT ORDER
LSB
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
08h
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
09h
B23 (MSB)
B17
B16
表 11. Offset Calibration Register Values
OFCAL[2:0] REGISTER VALUE
IDEAL OUTPUT VALUE(1)
000001h
000000h
FFFFFFh
FFFFFFh
000000h
000001h
(1) Output value with no offset error
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9.4.7.1.2 Full-Scale Calibration Registers
The full-scale calibration word is 24 bits consisting of three 8-bit registers, as listed in 表 12. The full-scale
calibration value is in straight-binary format, normalized to a unity-gain factor at a value of 400000h. 表 13 lists
register values for selected gain factors. Gain errors greater than unity are corrected by using full-scale values
less than 400000h. Although the full-scale register provides a wide range of possible values, the input signal after
calibration must not exceed ±106% of the precalibrated input range; otherwise, the ADC is overranged.
表 12. Full-Scale Calibration Registers
BYTE
ORDER
REGISTER
ADDRESS
BIT ORDER
FSCAL0
FSCAL1
FSCAL2
LSB
0Ah
0Bh
0Ch
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
B23 (MSB)
B17
B16
表 13. Full-Scale Calibration Register Values
FSCAL[2:0] REGISTER VALUE
GAIN FACTOR
433333h
400000h
1.05
1.00
0.95
3CCCCCh
9.4.7.2 Offset Self-Calibration (SFOCAL)
The offset self-calibration command corrects offset errors internal to the ADC. When the offset self-calibration
command is sent, the ADC disconnects the external inputs, shorts the inputs to the PGA, and then averages 16
conversion results to compute the calibration value. Averaging the data reduces conversion noise to improve
calibration accuracy. When calibration is complete, the ADC restores the user input and performs one conversion
using the new calibration value.
9.4.7.3 Offset System-Calibration (SYOCAL)
The offset system-calibration command corrects system offset errors. For this type of calibration, the user shorts
the inputs to either the ADC or to the system. When the command is sent, the ADC averages 16 conversion
results to compute the calibration value. Averaging the data reduces conversion noise to improve calibration
accuracy. When calibration is complete, the ADC performs one conversion using the new calibration value.
9.4.7.4 Full-Scale Calibration (GANCAL)
The full-scale calibration command corrects gain error. To calibrate, apply a positive full-scale calibration voltage
to the ADC, wait for the signal to settle, and then send the calibration command. The ADC averages 16
conversion results to compute the calibration value. Averaging the data reduces conversion noise to improve
calibration accuracy. The ADC computes the full-scale calibration value so that the calibration voltage is scaled
to positive full scale output code. When calibration is complete, the ADC performs one new conversion using the
new calibration value.
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9.4.7.5 Calibration Command Procedure
Use the following procedure to calibrate using commands. The register-lock mode must be UNLOCK for all
calibration commands. After power-on, make sure the reference voltage has stabilized before calibrating.
Perform offset calibration before full-scale calibration.
1. Configure the ADC as required.
2. Apply the appropriate calibration signal (zero or full-scale)
3. Take the START pin high or send the START command to start conversions. DRDY is driven high.
4. Before the conversion cycle completes, send the calibration command. Keep CS low otherwise the command
is cancelled. Send no other commands during the calibration period.
5. Calibration time depends on the data rate and digital filter mode. See 表 14. DRDY asserts low when
calibration is complete. The offset or full-scale calibration registers are updated with new values. At
calibration completion, new conversion data are ready using the new calibration value.
表 14. Calibration Time (ms)
(1)
FILTER MODE
DATA RATE
(SPS)
2.5
FIR
6805
3405
1705
—
SINC1
6801
3401
1701
1021
850.9
340.9
284.2
170.9
43.36
15.02
7.938
4.397
3.216
—
SINC2
7601
3801
1901
1141
951.0
380.9
317.5
190.9
48.36
16.69
8.772
4.813
3.494
—
SINC3
8401
4201
2101
1261
1051
420.9
350.9
210.9
53.36
18.36
9.605
5.230
3.772
—
SINC4
9201
4601
2301
1381
1151
460.9
384.2
230.9
58.36
20.02
10.44
5.647
4.050
—
SINC5
—
5
—
10
—
16.6
20
—
854.5
—
—
50
—
60
—
—
100
—
—
400
—
—
1200
2400
4800
7200
14400
19200
25600
40000
—
—
—
—
—
—
—
—
—
1.892
1.458
1.133
0.738
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1) Nominal clock frequency. Chop and AC-excitation modes disabled.
9.4.7.6 User Calibration Procedure
To user calibrate, apply the calibration voltage, acquire conversion data, and compute the calibration value. The
computed value is written to the corresponding calibration registers. Before starting calibration, preset the offset
and full-scale registers to 000000h and 400000h, respectively.
To offset calibrate, short the ADC inputs (or inputs to the system) and average n number of the conversion
results. Averaging conversion data reduces noise to improve calibration accuracy. Write the averaged value of
the conversion data to the offset registers.
To gain calibrate using a full scale calibration voltage, temporarily reduce the full scale register 95% to avoid
output clipped codes (set FSCAL[2:0] to 3CCCCCh). Acquire n number of conversions and average the
conversions to reduce noise to improve calibration accuracy. Compute the full-scale calibration value as shown
in 公式 7:
Full-Scale Calibration Value = Expected Code / Actual Code · 400000h
where
•
Expected code = 799998h using full scale calibration signal and 95% scale factor
(7)
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9.5 Programming
9.5.1 Serial Interface
The serial interface is SPI-compatible and is used to read conversion data, configure registers, and control the
ADC. The serial interface consists of four control lines: CS, SCLK, DIN, and DOUT/DRDY. Most microcontroller
SPI peripherals can operate with the ADC. The interface operates in SPI mode 1, where CPOL = 0 and CPHA =
1. In SPI mode 1, SCLK idles low and data are updated or changed on SCLK rising edges; data are latched or
read on SCLK falling edges. Timing details of the SPI protocol are found in 图 1 and 图 2.
9.5.1.1 Chip Select (CS)
CS is an active-low input that selects the serial interface for communication. CS must be low during the entire
data transaction. When CS is taken high, the serial interface resets, SCLK input activity is ignored (blocking
commands), and DOUT/DRDY enters the high-impedance state. The operation of DRDY is not effected by CS. If
the ADC is a single device connected to the serial bus, CS can be tied low in order to reduce the serial interface
to three lines.
9.5.1.2 Serial Clock (SCLK)
SCLK is the serial clock input that shifts data into and out of the ADC. Output data are updated on the rising
edge of SCLK and input data are latched on the falling edge of SCLK. Return SCLK low after the data operation
is completed. SCLK is a Schmidt-triggered input designed to improve noise immunity. Even though SCLK is
noise resistant, keep SCLK as noise-free as possible to avoid unintentional SCLK transitions. Avoid ringing and
overshoot on the SCLK input. Place a series termination resistor close to the SCLK drive pin to reduce ringing.
9.5.1.3 Data Input (DIN)
DIN is the serial data input to the ADC. DIN is used to input commands and register data to the ADC. Data are
latched on the falling edge of SCLK.
9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
The DOUT/DRDY pin is a dual-function output. The functions of this pin are data output and data ready. The
functionality changes automatically based on whether a read data operation is in progress. During a read data
operation, the functionality is data output. After the read operation is complete, the functionality changes to data
ready.
In data output mode, data are updated on the SCLK rising edge, therefore the host latches the data on the falling
edge of SCLK. In data-ready mode, the pin functions the same as DRDY (if CS is low) by asserting low when
data are ready. Therefore, monitor either DOUT/DRDY or DRDY to determine when data are ready. When CS is
high, the DOUT/DRDY pin is in the high-impedance mode (tri-state).
9.5.1.5 Serial Interface Auto-Reset
The serial interface is reset by taking CS high. Applications that tie CS low do not have the ability to reset the
serial interface by CS. If a false SCLK occurs (for example, caused by a noise pulse or clocking glitch), the serial
interface may inadvertently advance one or more bit positions, resulting in loss of synchronization to the host. If
loss of synchronization occurs, the ADC interface does not respond correctly until the interface is reset.
For applications that tie CS low, the serial interface auto-reset feature recovers the interface in the event that an
unintentional SCLK glitch occurs. When the first SCLK low-to-high transition occurs (either caused by a glitch or
by normal SCLK activity), seven SCLK transitions must occur within 65536 fCLK cycles (8.9 ms) to complete the
byte transaction, otherwise the serial interface resets. After reset, the interface is ready to begin the next byte
transaction. If the byte transaction is completed within the 65536 fCLK cycles, the serial interface does not reset.
The cycle of SCLK detection re-starts at the next rising edge of SCLK. The serial interface is reset by holding
SCLK low for a minimum 65536 fCLK cycles.
The auto-reset function is enabled by the SPITIM bit (default is off). See 图 3 for timing details.
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Programming (接下页)
9.5.2 Data Ready (DRDY)
DRDY is an output that asserts low when conversion data are ready. After power-up, DRDY also indicates when
the ADC is ready for communication. The operation of DRDY depends on the conversion mode (continuous or
pulse) and whether the conversion data are retrieved or not. 图 75 shows DRDY operation with and without data
retrieval in the two modes of conversion.
DRDY - with data retrieval
(Continuous-conversion mode)
DRDY œ w/o data retrieval
(Continuous-conversion mode)
DRDY œ w or w/o data retreival
(Pulse-conversion mode)
START
Command
START
STOP
START
STOP
图 75. DRDY Operation
9.5.2.1 DRDY in Continuous-Conversion Mode
In continuous-conversion mode, DRDY is driven high when conversions are started and is driven low when
conversion data are ready. During data readback, DRDY returns high at the end of the read operation. If the
conversion data are not read, DRDY pulses high 16 fCLK cycles prior to the next falling edge.
To read conversion data before the next conversion is ready, send the complete read-data command 16 fCLK
cycles before the next DRDY falling edge. If the readback command is sent less than 16 fCLK cycles before the
DRDY falling edge, either old or new conversion data are provided, depending on the timing of when the
command is sent. In the case that old conversion data are provided, DRDY driven low is delayed until after the
read data operation is completed. In this case, the DRDY bit of the STATUS byte is cleared to indicate the same
data have been read. If new conversion data are provided, DRDY transitions low at the normal period of the data
rate. In this case, the DRDY bit of the STATUS byte is set to indicate that new data have been read. To make
sure new data are read back, wait until DRDY asserts low before starting the data read operation.
9.5.2.2 DRDY in Pulse-Conversion Mode
DRDY is driven high at conversion start and is driven low when the conversion data are ready. During the data
read operation DRDY remains low until a new conversion is started.
9.5.2.3 Data Ready by Software Polling
Use software polling of data ready in lieu of hardware polling of DRDY or DOUT/DRDY. To software poll, read
the STATUS register and poll the DRDY bit. In order to not skip conversion data in continuous conversion mode,
poll the bit at least as often as the period of the data rate. If the DRDY bit is set, then conversion data are new
since the previous data read operation. If the bit is cleared, conversion data are not new since the previous data
read operation. In this case, the previous conversion data are returned.
9.5.3 Conversion Data
Conversion data are read by the RDATA command. To read data, take CS low and issue the read data
command. The data field response consists of the optional STATUS byte, three data bytes, and the optional
CRC byte. The CRC is computed over the combination of status byte and conversion data bytes. See the
RDATA Command section for details to read conversion data.
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Programming (接下页)
9.5.3.1 Status byte (STATUS)
The status byte contains information on the operating state of the ADC. The STATUS byte is included with the
conversion data by enabling bit STATENB of register MODE3. Optionally, read the STATUS register directly to
read status information without the need to read conversion data. See 图 81 for details.
9.5.3.2 Conversion Data Format
The conversion data are 24 bits, in two's-complement format to represent positive and negative values. The data
output begins with the most significant bit (sign bit) first. The data are scaled so that VIN = 0 V results in an
uncalibrated code value of 000000h; positive full scale equals 7FFFFFh and negative full scale equals 800000h;
see 表 15 for the uncalibrated code values. The data are clipped to 7FFFFFh (positive full scale) and 800000h
(negative full scale) during positive and negative signal overdrive, respectively.
表 15. ADC Conversion Data Codes
(1)
DESCRIPTION
Positive full scale
1 LSB
INPUT SIGNAL (V)
≥ VREF / Gain · (223 - 1) / 223
24-BIT CONVERSION DATA
7FFFFFh
VREF / (Gain · 223
)
000001h
Zero scale
0
000000h
-1 LSB
–VREF / (Gain · 223
≤ –VREF / Gain
)
FFFFFFh
Negative full scale
800000h
(1) Ideal (calibrated) conversion data.
9.5.4 CRC
Cyclic redundancy check (CRC) is an error checking code that detects communication errors to and from the
host. CRC is the division remainder of the data payload bytes by a fixed polynomial. The data payload is 1, 2, 3
or 4 bytes depending on the data operation. The CRC mode is optional and is enabled by the CRCENB bit. See
表 35 to program the CRC mode.
The user computes the CRC corresponding to the two command bytes and appends the CRC to the command
string (3rd byte). A 4th, zero-value byte completes the command field. The ADC repeats the CRC calculation and
compares the calculation to the received CRC. If the user and repeated CRC values match, the command
executes and the ADC responds by transmitting the repeated CRC during the 4th byte of the command. If the
operation is conversion data or register data read, the ADC responds with a 2nd CRC that is computed over the
requested data payload bytes. The response data payload is 1, 3, or 4 bytes depending on the data operation.
If the user and repeated CRC values do not match, the command does not execute and the ADC responds with
an inverted CRC for the actual received command bytes. The inverted CRC is intended to signal the host of the
failed operation. The user terminates transmission of the command bytes to match the action of ADC termination.
The CRCERR bit is set in the STATUS register when a CRC error is detected. The ADC is ready to accept the
next command after a CRC error occurs at the end of the 4th byte.
The CRC data byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the argument by a
CRC polynomial. The CRC polynomial is based on the CRC-8-ATM (HEC): X8 + X2 + X1 + 1. The nine binary
polynomial coefficients are: 100000111. The CRC calculation is preset with "1" data values.
The CRC mnemonics apply to the following command sections.
• CRC-2: Input CRC of command bytes 1 and 2. Except for WREG command, the value of byte 2 is arbitrary
• Out CRC-1: Output CRC of one register data byte
• Out CRC-2: Output CRC of two command bytes, inverted value if input CRC error detected
• Out CRC-3: Output CRC of three conversion data bytes
• Out CRC-4: Output CRC of three conversion data bytes plus STATUS byte
• Echo Byte 1: Echo of received input byte 1
• Echo Byte 2: Echo of received input byte 2
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9.5.5 Commands
Commands read conversion data, control the ADC, and read and write register data. See 表 16 for the list of
commands. Send only the commands that are listed in 表 16. The ADC executes commands at completion of the
2nd byte (no CRC verification) or at completion of the 4th byte (with CRC verification). Follow the two byte or four
byte format according to the CRC mode. Except for register write commands, the value of the second command
byte is arbitrary but the value is included in the CRC calculation (total of two-byte CRC). If a CRC error is
detected, the ADC does not execute the command. Taking CS high before the command is completed results in
termination of the command. When CS is taken low, the communication frame is reset to start a new command.
表 16. Command Byte Summary
BYTE 3
(CRC Mode Only)
BYTE 4
(CRC Mode only)
MNEMONIC
DESCRIPTION
BYTE 1
BYTE 2
Control Commands
NOP
No operation
Reset
00h
06h
08h
0Ah
Arbitrary
Arbitrary
Arbitrary
Arbitrary
CRC-2
CRC-2
CRC-2
CRC-2
00h
00h
00h
00h
RESET
START
STOP
Start conversion
Stop conversion
Read Data Command
RDATA
Read conversion data
12h
Arbitrary
CRC-2
00h
Calibration Commands
SYOCAL
GANCAL
SFOCAL
System offset calibration
16h
17h
19h
Arbitrary
Arbitrary
Arbitrary
CRC-2
CRC-2
CRC-2
00h
00h
00h
Gain calibration
Self offset calibration
Register Commands
RREG
WREG
Read register data
Write register data
20h + rrh(1)
40h + rrh(1)
Arbitrary
CRC-2
CRC-2
00h
00h
Register data
Protection Commands
LOCK
Register lock
Register unlock
F2h
F5h
Arbitrary
Arbitrary
CRC-2
CRC-2
00h
00h
UNLOCK
(1) rrh = 5-bit register address.
9.5.5.1 NOP Command
This command is no operation. Use the NOP command to validate the CRC response byte and error detection
without affecting normal operation. 表 17 shows the NOP command byte sequence.
表 17. NOP Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
00h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
00h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.2 RESET Command
The RESET command resets ADC operation and resets the registers to default values. See the Reset by
Command section for details. 表 18 shows the RESET command byte sequence.
表 18. RESET Command
DIRECTION
BYTE 1
BYTE 2
BYTE 3
BYTE 4
No CRC mode
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表 18. RESET Command (接下页)
DIRECTION
DIN
BYTE 1
06h
BYTE 2
Arbitrary
BYTE 3
BYTE 4
DOUT/DRDY
FFh
Echo byte 1
CRC mode
DIN
06h
FFh
Arbitrary
CRC-2
00H
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.3 START Command
This command starts conversions. See the Conversion Control section for details. 表 19 shows the START
command byte sequence.
表 19. START Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
08h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
08h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.4 STOP Command
This command stops conversions. See the Conversion Control section for details. 表 20 shows the STOP
command byte sequence.
表 20. STOP Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
0Ah
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
0Ah
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
9.5.5.5 RDATA Command
This command reads conversion data. Because the data are buffered, the data can be read at any time during
the conversion phase. If data are read near the completion of the next conversion, old or new conversion data
are returned. See the Data Ready (DRDY) section for details.
The response of conversion data varies in length from 3 to 5 bytes depending if the STATUS byte and CRC
bytes are included. See the Conversion Data Format section for the numeric data format. See 表 21, 图 76
(minimum configuration) and 图 77 (maximum configuration) for operation of the RDATA command.
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表 21. RDATA Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
BYTE 8
BYTE 9
12h
FFh
Arbitrary
00h
00h
00h
00h
DOUT/DRDY
CRC mode
DIN
Echo byte 1
STATUS(1)
MSB data
MID data
LSB data
12h
FFh
Arbitrary
CRC-2
00h
00h
00h
00h
00h
00h
Out CRC-3 or
Out CRC-4
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
STATUS(1)
MSB data
MID data
LSB data
(1) Optional STATUS byte.
(1)
CS
1
9
17
25
33
SCLK
DIN
12h
Arbitrary
00h
00h
00h
DOUT/DRDY
FFh
Echo byte 1
MSB data
MID data
LSB data
NOTE: CS can be tied low.
图 76. Conversion Data Read Operation (STATUS Byte and CRC Mode Disabled)
(1)
CS
41
49
57
65
1
9
17
25
33
SCLK
DIN
12h
FFh
Arbitrary
00h
00h
CRC-2
00h
00h
00h
00h
MSB data
MID data
LSB DATA
Out CRC-4
Echo byte 1
Echo byte 2
Out CRC-2
STATUS
DOUT/DRDY
NOTE: CS can be tied low.
图 77. Conversion Data Read Operation (STATUS Byte and CRC Mode Enabled)
9.5.5.6 SYOCAL Command
This command is used for system offset calibration. See the Offset System-Calibration (SYOCAL) section for
details. 表 22 shows the SYOCAL command byte sequence.
表 22. SYOCAL Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
16h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
16h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo Byte 2
Out CRC-2
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9.5.5.7 GANCAL Command
This command is for gain calibration. See the Full-Scale Calibration (GANCAL) section for details. 表 23 shows
the GANCAL command byte sequence.
表 23. GANCAL Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
17h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
17h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo Byte 2
Out CRC-2
9.5.5.8 SFOCAL Command
This command is used for self offset calibration. See the Offset Self-Calibration (SFOCAL) section for details. 表
24 shows the SFOCAL command byte sequence.
表 24. SFOCAL Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
19h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
19h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo Byte 2
Out CRC-2
9.5.5.9 RREG Command
Use the RREG command to read register data. The register data are read one byte at a time by issuing the
RREG command for each operation. Add the register address (rrh) to the base opcode (20h) to construct the
command byte (20h + rrh). 表 25 illustrates the command byte sequence. The ADC responds with the register
data byte, most significant bit first. The response to registers outside the valid address range is 00h. 图 78
depicts an example of the register read operation. The Out CRC-1 byte is the CRC calculated for the register
data byte.
表 25. RREG Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
20h + rrh(1)
FFh
Arbitrary
00h
DOUT/DRDY
CRC mode
DIN
Echo byte 1
Register data
20h + rrh
FFh
Arbitrary
CRC-2
00h
00h
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
Register data
Out CRC-1
(1) rrh = 5-bit register address.
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(1)
CS
1
9
17
25
33
41
SCLK
DIN
22h
FFh
Arbitrary
CRC-2
00h
00h
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
Reg data
Out CRC-1
NOTE: CS can be tied low.
图 78. Register Read Operation (address = 02h, CRC Mode Enabled)
9.5.5.10 WREG Command
Use the WREG command to write register data. The register data are written one byte at a time by issuing the
WREG command for each operation. Add the register address (rrh) to the base opcode (40h) to construct the
command byte (40h + rrh). 表 26 shows the command byte sequence. 图 79 shows an example of the WREG
operation. Be aware that writing to certain registers results in conversion restart. 表 29 lists the registers that
restart an ongoing conversion when written to. Do not write to registers outside the address range.
表 26. WREG Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
40h + rrh(1)
FFh
Register data
Echo byte 1
DOUT/DRDY
CRC mode
DIN
40h + rrh
FFh
Register data
Echo byte 1
CRC-2
00h
DOUT/DRDY
Echo byte 2
Out CRC-2
(1) rrh = 5-bit register address.
(1)
CS
1
9
17
25
SCLK
DIN
42h
FFh
Reg Data
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo byte 2
Out CRC-2
NOTE: CS can be tied low.
图 79. Register Write Operation (address = 02h, CRC Mode Enabled)
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9.5.5.11 LOCK Command
The LOCK command locks-out write access to the registers including the calibration registers that are changed
by calibration commands. The default mode is UNLOCK. Read access is allowed in LOCK mode. 表 27 shows
the LOCK command byte sequence.
表 27. LOCK Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
F2h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
F2h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo Byte2
out CRC-2
9.5.5.12 UNLOCK Command
The UNLOCK command allows register write access, including access to the contents of the calibration registers
that can be changed by the calibration commands. 表 28 shows the UNLOCK command byte sequence.
表 28. UNLOCK Command
DIRECTION
No CRC mode
DIN
BYTE 1
BYTE 2
BYTE 3
BYTE 4
F5h
FFh
Arbitrary
DOUT/DRDY
CRC mode
DIN
Echo byte 1
F5h
FFh
Arbitrary
CRC-2
00h
DOUT/DRDY
Echo byte 1
Echo Byte2
Out CRC-2
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9.6 Register Map
The register map consists of 19, one-byte registers. Collectively, the registers are used to configure the ADC to
the desired operating mode. Access the registers by using the RREG and WREG (read-register and write-
register) commands. Register data are accessed one register byte at a time for each command operation. At
power-on or device reset, the registers are reset to the default values, as shown in the Default column of 表 29.
Writing new data to certain registers causes the ADC conversion in progress to restart. These registers are listed
in the Restart column in 表 29.
Register-write access is enabled or disabled by the UNLOCK and LOCK commands, respectively. The default
mode is register UNLOCK. See the LOCK Command section for more details.
表 29. Register Map Summary
(rrh)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
REGISTER
ID
DEFAULT
xxh
RESTART
BIT 7
LOCK
0
BIT 6
DEV_ID[3:0]
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REV_ID[3:0]
STATUS
MODE0
MODE1
MODE2
MODE3
REF
01h
24h
01h
00h
00h
05h
00h
00h
00h
00h
00h
40h
FFh
00h
00h
00h
FFh
00h
CRCERR
PGAL_ALM
DR[4:0]
PGAH_ALM REFL_ALM
CONVRT
DRDY
CLOCK
RESET
Yes
Yes
FILTER[2:0]
CHOP[1:0]
GPIO_CON[3:0]
STATENB CRCENB
DELAY[3:0]
GPIO_DIR[3:0]
GPIO_DAT[3:0]
PWDN
0
SPITIM
Yes
0
0
REFENB
OFC[7:0]
RMUXP[1:0]
RMUXN[1:0]
OFCAL0
OFCAL1
OFCAL2
FSCAL0
FSCAL1
FSCAL2
IMUX
OFC[15:8]
OFC[23:16]
FSC[7:0]
FSC[15:8]
FSC[23:16]
IMUX2[3:0]
IMAG2[3:0]
IMUX1[3:0]
IMAG1[3:0]
IMAG
RESERVED
PGA
00h
0
Yes
Yes
Yes
BYPASS
0
0
0
0
0
0
GAIN[2:0]
MUXN[3:0]
BOCS[2:0]
INPMUX
INPBIAS
MUXP[3:0]
VBIAS
BOCSP
9.6.1 Device Identification (ID) Register (address = 00h) [reset = xxh]
图 80. ID Register
7
6
5
4
3
2
1
0
DEV_ID[3:0]
REV_ID[3:0]
NOTE: Reset values are device dependent
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 30. ID Register Field Descriptions
Bit
Field
Type
Reset
Description
Device ID
7:4
DEV_ID[3:0]
R
xh
1000: ADS1261, ADS1261B
1010: ADS1260B
3:0
REV_ID[3:0]
R
xh
Revision ID
Note: Revision ID can change without notification
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9.6.2 Device Status (STATUS) Register (address = 01h) [reset = 01h]
图 81. STATUS Register
7
6
5
4
3
2
1
0
LOCK
R-0h
CRCERR
R/W-0h
PGAL_ALM
R-0h
PGAH_ALM
R-0h
REFL_ALM
R-0h
DRDY
R-0h
CLOCK
R-xh
RESET
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 31. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LOCK
R
0h
Register Lock Status
Indicates register lock status. Register writes are locked by the
LOCK command and unlocked by the UNLOCK command.
0: Register write not locked (default)
1: Register write locked
CRC Error
6
5
CRCERR
R/W
0h
0h
Indicates that a CRC error is detected by the ADC. The CRC
error bit remains set until cleared by the user.
0: No CRC error
1: CRC error
PGAL_ALM
R
PGA Low Alarm
Indicates PGA output voltage is below the low limit. The alarm
resets at the start of conversion cycles.
0: No Alarm
1: Alarm
4
3
PGAH_ALM
REFL_ALM
R
R
0h
0h
PGA High Alarm
Indicates PGA output voltage is above the high limit. The alarm
resets at the start of conversion cycles.
0: No Alarm
1: Alarm
Reference Low Alarm
Indicates reference voltage is below the low limit. The alarm
resets at the start of conversion cycles.
0: No Alarm
1: Alarm
2
1
DRDY
R
R
0h
xh
Data Ready
Indicates conversion data ready.
0: Conversion data not new since the previous read operation
1: Conversion data new since the previous read operation
Clock
CLOCK
Indicates internal or external clock mode. The ADC automatically
selects the clock source.
0: ADC clock is internal
1: ADC clock is external
0
RESET
R/W
1h
Reset
Indicates ADC reset. Clear the bit to detect next device reset.
0: No reset
1: Reset (default)
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9.6.3 Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
图 82. MODE0 Register
7
6
5
4
3
2
1
0
DR[4:0]
R/W-4h
FILTER[2:0]
R/W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 32. MODE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:3
DR[4:0]
R/W
4h
Data Rate
Select the ADC data rate.
00000: 2.5 SPS
00001: 5 SPS
00010: 10 SPS
00011: 16.6 SPS
00100: 20 SPS (default)
00101: 50 SPS
00110: 60 SPS
00111: 100 SPS
01000: 400 SPS
01001: 1200 SPS
01010: 2400 SPS
01011: 4800 SPS
01100: 7200 SPS
01101: 14400 SPS
01110: 19200 SPS
01111: 25600 SPS
10000 - 11111: 40000 SPS (fCLK = 10.24 MHz)
2:0
FILTER[2:0]
R/W
4h
Digital Filter
Select the digital filter mode.
000: sinc1
001: sinc2
010: sinc3
011: sinc4
100: FIR (default)
101: Reserved
110: Reserved
111: Reserved
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9.6.4 Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
图 83. MODE1 Register
7
0
6
5
4
3
2
1
0
CHOP[1:0]
R/W-0h
CONVRT
R/W-0h
DELAY[3:0]
R/W-1h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 33. MODE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
0
R/W
0h
Reserved
Always write 0
6:5
CHOP[1:0]
R/W
0h
Chop and AC-Excitation Modes
Select the Chop and AC-excitation modes.
00: Normal mode (default)
01: Chop mode
10: 2-wire AC-excitation mode ( ADS1261 only)
11: 4-wire AC-excitation mode ( ADS1261 only)
ADC Conversion Mode
4
CONVRT
R/W
R/W
0h
1h
Select the ADC conversion mode.
0: Continuous conversions (default)
1: Pulse (one shot) conversion
3:0
DELAY[3:0]
Conversion Start Delay
Program the time delay at conversion start. Delay values are
with fCLK = 7.3728 MHz.
0000: 0 µs (not for 25600 SPS or 40000 SPS operation)
0001: 50 µs (default)
0010: 59 µs
0011: 67 µs
0100: 85 µs
0101: 119 µs
0110: 189 µs
0111: 328 µs
1000: 605 µs
1001: 1.16 ms
1010: 2.27 ms
1011: 4.49 ms
1100: 8.93 ms
1101: 17.8 ms
1110: Reserved
1111: Reserved
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9.6.5 Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
图 84. MODE2 Register
7
6
5
4
3
2
1
0
GPIO_CON[3:0]
R/W-0h
GPIO_DIR[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 34. MODE2 Register Field Descriptions(1)
Bit
Field
Type
Reset
Description
7
GPIO_CON[3]
R/W
0h
GPIO3 Pin Connection
Connect GPIO3 to analog input AIN5.
0: GPIO3 not connected to AIN5 (default)
1: GPIO3 connected to AIN5
6
5
4
3
2
1
0
GPIO_CON[2]
GPIO_CON[1]
GPIO_CON[0]
GPIO_DIR[3]
GPIO_DIR[2]
GPIO_DIR[1]
GPIO_DIR[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
GPIO2 Pin Connection
Connect GPIO2 to analog input AIN4.
0: GPIO2 not connected to AIN4 (default)
1: GPIO2 connected to AIN4
GPIO1 Pin Connection
Connect GPIO1 to analog input AIN3.
0: GPIO1 not connected to AIN3 (default)
1: GPIO1 connected to AIN3
GPIO0 Pin Connection
Connect GPIO0 to analog input AIN2
0: GPIO0 not connected to AIN2 (default)
1: GPIO0 connected to AIN2
GPIO3 Pin Direction
Configure GPIO3 as a GPIO input or GPIO output on AIN5.
0: GPIO3 is an output (default)
1: GPIO3 is an input
GPIO2 Pin Direction
Configure GPIO2 as a GPIO input or GPIO output on AIN4.
0: GPIO2 is an output (default)
1: GPIO2 is an input
GPIO1 Pin Direction
Configure GPIO1 as a GPIO input or GPIO output on AIN3.
0: GPIO1 is an output (default)
1: GPIO1 is an input
GPIO0 Pin Direction
Configure GPIO0 as a GPIO input or GPIO output on AIN2.
0: GPIO0 is an output (default)
1: GPIO0 is an input
(1) ADS1261 and ADS1261B only.
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9.6.6 Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
图 85. MODE3 Register
7
6
5
4
3
2
1
0
PWDN
R/W-0h
STATENB
R/W-0h
CRCENB
R/W-0h
SPITIM
R/W-0h
GPIO_DAT[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 35. MODE3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PWDN
R/W
0h
Software Power-down Mode
Select the software power-down mode.
0: Normal mode (default)
1: Software power-down mode
STATUS Byte
6
5
STATENB
CRCENB
R/W
R/W
0h
0h
Enable the Status byte for the conversion data read operation.
0: No Status byte (default)
1: Status byte enabled
CRC Data Verification
Enable CRC data verification.
0: No CRC (default)
1: CRC enabled
4
3
2
1
0
SPITIM
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
SPI Auto-Reset Function
Enable the SPI auto-reset function.
0: SPI auto-reset disabled (default)
1: SPI auto-reset enabled
GPIO_DAT[3](1)
GPIO_DAT[2](1)
GPIO_DAT[1](1)
GPIO_DAT[0](1)
GPIO3 Data
Read or write the GPIO3 data on AIN5.
0: GPIO3 is low (default)
1: GPIO3 is high
GPIO2 Data
Read or write the GPIO2 data on AIN4.
0: GPIO2 is low (default)
1: GPIO2 is high
GPIO1 Data
Read or write the GPIO1 data on AIN3.
0: GPIO1 is low (default)
1: GPIO1 is high
GPIO0 Data
Read or write the GPIO1 data on AIN3.
0: GPIO0 is low (default)
1: GPIO0 is high
(1) ADS1261 and ADS1261B only.
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9.6.7 Reference Configuration (REF) Register (address = 06h) [reset = 05h]
图 86. REF Register
7
0
6
0
5
0
4
3
2
1
0
REFENB
R/W-0h
RMUXP[1:0]
R/W-1h
RMUXN[1:0]
R/W-1h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 36. REF Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
0
R/W
0h
Reserved
Always write 0h
4
REFENB
R/W
R/W
0h
1h
Internal Reference Enable
Enable the internal reference.
0: Internal reference disabled (default)
1: Internal reference enabled
3:2
RMUXP[1:0]
Reference Positive Input
Select the positive reference input.
00: Internal reference positive
01: AVDD internal (default)
10: AIN0 external
11: AIN2 external ( ADS1261 only)
1:0
RMUXN[1:0]
R/W
1h
Reference Negative Input
Select the negative reference input.
00: Internal reference negative
01: AVSS internal (default)
10: AIN1 external
11: AIN3 external ( ADS1261 only)
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9.6.8 Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
图 87. OFCAL0, OFCAL1, OFCAL2 Registers
7
6
5
4
3
2
1
9
0
8
OFC[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
OFC[15:8]
R/W-00h
17
16
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
Bit
Field
Type
Reset
Description
23:0
OFC[23:0]
R/W
000000h
Offset Calibration
These three registers are the 24-bit offset calibration word. The
offset calibration is two's complement format. The ADC subtracts
the offset value from the conversion result before the full-scale
operation.
9.6.9 Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
图 88. FSCAL0, FSCAL1, FSCAL2 Registers
7
6
5
4
3
2
1
9
0
8
FSC[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
FSC[15:8]
R/W-00h
17
16
FSC[23:16]
R/W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
Bit
Field
Type
Reset
Description
23:0
FSC[23:0]
R/W
400000h
Full-Scale Calibration
These three registers are the 24-bit full scale calibration word.
The full-scale calibration is straight binary format. The ADC
divides the register value by 400000h then multiplies the result
with the conversion data. The scaling operation occurs after the
offset operation.
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9.6.10 IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
图 89. IMUX Register
7
6
5
4
3
2
1
0
IMUX2[3:0]
R/W-Fh
IMUX1[3:0]
R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 39. IMUX Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
IMUX2[3:0]
R/W
Fh
IDAC2 Output Multiplexer
Select the IDAC2 analog input pin connection.
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5 ( ADS1261 only)
0110: AIN6 ( ADS1261 only)
0111: AIN7 ( ADS1261 only)
1000: AIN8 ( ADS1261 only)
1001: AIN9 ( ADS1261 only)
1010: AINCOM
1011: No connection
1100: No connection
1101: No connection
1110: No connection
1111: No connection (default)
3:0
IMUX1[3:0]
R/W
Fh
IDAC1 Output Multiplexer
Select the IDAC1 analog input pin connection.
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5 ( ADS1261 only)
0110: AIN6 ( ADS1261 only)
0111: AIN7 ( ADS1261 only)
1000: AIN8 ( ADS1261 only)
1001: AIN9 ( ADS1261 only)
1010: AINCOM
1011: No connection
1100: No connection
1101: No connection
1110: No connection
1111: No connection (default)
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9.6.11 IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
图 90. IMAG Register
7
6
5
4
3
2
1
0
IMAG2[3:0]
R/W-0h
IMAG1[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 40. IMAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
IMAG2[3:0]
R/W
0h
IDAC2 Current Magnitude
Select the magnitude of current source IDAC2.
0000: Off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011: Off
1100: Off
1101: Off
1110: Off
1111: Off
3:0
IMAG1[3:0]
R/W
0h
IDAC1 Current Magnitude
Select the magnitude of current source IDAC1.
0000: Off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011: Off
1100: Off
1101: Off
1110: Off
1111: Off
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9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
图 91. RESERVED Register
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 41. RESERVED Register Field Descriptions
Bit
Field
Type
Reset
Description
7:0
0
R
0h
Reserved
These bits are read only and always return 0
9.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
图 92. PGA Register
7
6
0
5
0
4
0
3
0
2
1
0
BYPASS
R/W-0h
GAIN[2:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 42. PGA Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BYPASS
R/W
0h
PGA Bypass Mode
Select the PGA mode.
0: PGA mode (default)
1: PGA bypass
Reserved
6:3
2:0
0
R/W
R/W
0h
0h
Always write 0
Gain
GAIN[2:0]
Select the gain.
000: 1 (default)
001: 2
010: 4
011: 8
100: 16
101: 32
110: 64
111: 128
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9.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
图 93. INPMUX Register
7
6
5
4
3
2
1
0
MUXP[3:0]
R/W-Fh
MUXN[3:0]
R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 43. INPMUX Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUXP[3:0]
R/W
Fh
Positive Input Multiplexer
Select the positive multiplexer input.
0000: AINCOM
0001: AIN0
0010: AIN1
0011: AIN2
0100: AIN3
0101: AIN4
0110: AIN5 ( ADS1261 only)
0111: AIN6 ( ADS1261 only)
1000: AIN7 ( ADS1261 only)
1001: AIN8 ( ADS1261 only)
1010: AIN9 ( ADS1261 only)
1011: Internal temperature sensor positive
1100: Internal (AVDD - AVSS) / 4 positive
1101: Internal (DVDD / 4) positive
1110: Inputs open
1111: Internal connection to VCOM (default)
3:0
MUXN[3:0]
R/W
Fh
Negative Input Multiplexer
Select the negative multiplexer input.
0000: AINCOM
0001: AIN0
0010: AIN1
0011: AIN2
0100: AIN3
0101: AIN4
0110: AIN5 ( ADS1261 only)
0111: AIN6 ( ADS1261 only)
1000: AIN7 ( ADS1261 only)
1001: AIN8 ( ADS1261 only)
1010: AIN9 ( ADS1261 only)
1011: Internal temperature sensor negative
1100: Internal (AVDD - AVSS) / 4 negative
1101: Internal (DVDD / 4) negative
1110: All inputs open
1111: Internal connection to VCOM (default)
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9.6.15 Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
图 94. INPBIAS Register
7
0
6
0
5
0
4
3
2
1
0
VBIAS
R/W-0h
BOCSP
R/W-0h
BOCS[2:0]
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 44. INPBIAS Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
0
R/W
0h
Reserved
Always write 0
4
3
VBIAS
R/W
R/W
R/W
0h
0h
0h
VBIAS
Select the VBIAS connection to the AINCOM pin.
0: VBIAS disabled (default)
1: VBIAS enabled
BOCSP
BOCS[2:0]
Burn-Out Current Source Polarity
Select the burn-out current source polarity.
0: Pull-up mode (default)
1: Pull-down mode
2:0
Burn-Out Current Source Magnitude
Select the burn-out current source magnitude.
000: Off (default)
001: 50 nA
010: 200 nA
011: 1 µA
100: 10 µA
101: Reserved
110: Reserved
111: Reserved
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Input Range
In PGA mode, the input voltage must be within the specified input range for linear operation. The following
exercise shows how to use 公式 5 to verify the input voltage is within specification. The exercise is a
thermocouple with the negative lead connected to AINCOM and the level-shift voltage enabled (2.5 V). The gain
factor = 32 and the ADC is powered by a single 5-V power supply. The summary of conditions are:
•
•
•
•
•
•
VAINN = Negative absolute input voltage = 2.5 V
VAINP = Positive absolute input voltage = 2.56 V
VIN = Differential input voltage = 60 mV
AVDD = 4.75 V (worst-case minimum)
AVSS = 0 V
Gain = 32
Evaluation of the equation results in:
1.23 V < 2.5 V and 2.56 V < 3.52 V
The inequality is satisfied, therefore the absolute input voltages are within the specified PGA input range. The
input requirement can also be verified by measuring the PGA output voltages (pins CAPP and CAPN) with a
voltmeter. Check that both outputs are within the range: AVSS + 0.3 V < V(CAPP) and V(CAPN) < AVDD – 0.3 V,
under the worst-case input and power-supply conditions.
10.1.2 Input Overload
Observe the input overvoltage precautions as outlined in the ESD Diodes section. If an overvoltage condition
occurs on an unused channel, the overvoltage channel may crosstalk to the measurement channel. One solution
is to externally clamp the inputs with low-forward voltage diodes as shown in 图 95. The external diodes divert
the overvoltage current around the ADC inputs to the power supply and ground. Be aware of the reverse leakage
current of the Schottky diodes that may lead to measurement errors.
IFAULT
5 V
Schottky
Diode
AVDD
RLIM
AINx
ADC
AVSS œ 0.3 V > VCLAMP > AVDD + 0.3 V
Schottky
Diode
AVSS
IFAULT
图 95. External Diode Clamps
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Application Information (接下页)
10.1.3 Burn-Out Current Source
When using the burn-out current sources, be aware of the offset error caused by the currents flowing through
impedances in the input path, including the multiplexer resistance RMUX), external filter resistors and the internal
impedance of the sensor REXT), as shown in 图 96. In many cases, the offset error can be calibrated. Be aware
that the combination of chop mode and high data rates increases the input current to the PGA. The increased
input current can affect the accuracy of the burn-out current sources.
AVDD
IBOCS
REXT
RMUX
AINx
+
VSENSOR
VIN = VSENSOR + VOFFSET
PGA
œ
REXT
RMUX
AINx
IBOCS
AVSS
图 96. Burn-Out Current Source Offset Voltage Error
10.1.4 Unused Inputs and Outputs
•
•
Analog inputs:
To minimize input leakage of the measurement channel, tie unused inputs to mid-supply voltage (AVDD +
AVSS) / 2 or to AVDD.
Digital I/O:
Not all the digital I/Os may be needed to operate the ADC. Be sure not to float both used and unused digital
inputs, including during power-down mode. The following is a summary of the optional digital I/Os connection:
•
•
•
CS: Tie CS low to permanently enable the serial interface.
CLKIN: Tie CLKIN to DGND to permanently operate the ADC with the internal oscillator.
START: Tie START to DGND to control conversions by command. Tie START to DVDD to permanently
free-run conversions (Continuous-conversion mode only)
•
•
•
RESET: Tie RESET to DVDD if not using hardware reset. The ADC is reset at power-on. The ADC is also
reset by the RESET command.
PWDN: Tie PWDN to DVDD if not using the hardware power-down mode. The ADC can be powered down
by software.
DRDY: The functionality of the DRDY output is also provided by the dual-mode DOUT/DRDY pin. The
DOUT/DRDY output is active when CS is low. Data ready is also determined by software polling. Because
the conversion data are buffered, data can be read at any time without the need to synchronize to data
ready.
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Application Information (接下页)
10.1.5 AC-Excitation
图 97 shows a example of an AC-excited bridge measurement system. The example shown omits optional filter
components for clarity. The transistors switch the bridge excitation voltage by drive signals provided by the GPIO
drivers through the analog input pins. The timing of the drive signals are synchronized to the ADC conversions.
The drive signals do not overlap in order to avoid bridge commutation during the switching phase of the drive
signal. The transistors gate resistors bias the transistors off at power-on. At host start-up, the host configures the
ADC to the AC-excitation mode. See 图 7 for timing of the drive signals.
5 V
AVDD
5 V
ADS1261
100 kΩ
AIN2
(ACX1)
AIN5
(ACX2)
100 kΩ
AIN0
SEN +
(REFP0)
AIN6
AIN7
SIG +
SIG -
(AINP)
(AINN)
SEN -
AIN1
(REFN0)
5 V
100 kΩ
AIN3
AIN4
(ACX2)
(ACX1)
100 kΩ
AVSS
图 97. 4-Wire Drive, AC-Excitation Example
The recommended sequence AC-excitation configuration is as follows:
1. Stop conversions by taking the START pin low, or by control of conversions in software mode; send the
STOP command
2. Program the input and reference MUX, gain, data rata, filter mode and other configurations as needed
3. Program the 2-wire or 4-wire AC-excitation mode
4. Program the 2 GPIOs or 4 GPIOs internal connection to the analog input pins
5. Program the 2 GPIOs or 4 GPIOs as outputs to enable drive signals at the analog input pins.
Start the conversions. Adjust the time delay parameter as necessary based on the time constant of the input and
reference filters.
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Application Information (接下页)
10.1.6 Serial Interface and Digital Connections
图 98 shows an example of the digital connections from a host µC to the ADC. Not all I/O connections are
necessary for basic ADC operation; see the Unused Inputs and Outputs section. Impedance-matching resistors
in series with the I/O PCB traces help reduce overshoot and ringing, and is particularly helpful over long trace
runs.
ADC
Optional
Clock
47 ꢀ
CLKIN
Source
Host µC
47 ꢀ
47 ꢀ
PWDN
RESET
Port Pin
Port Pin
Port Pin
47 ꢀ
47 ꢀ
47 ꢀ
47 ꢀ
START
CS
Port Pin
(CS)
SCLK
DIN
SCLK
MOSI
MISO
IRQ;
DOUT
/DRDY
47 ꢀ
47 ꢀ
DRDY
图 98. Serial Interface and Digital I/O Connections
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10.2 Typical Application
图 99 shows a fault-protected, 3-wire RTD application with hardware-based, lead-wire compensation. Two
current sources are used together to compensate the RTD lead wire resistance. One current source (IDAC1)
provides excitation to the RTD element through RLEAD1. The reference voltage of the ADC is derived directly from
this current by resistor RREF. The second current source cancels lead-wire resistance by generating a voltage
drop on lead-wire resistance RLEAD2 equal to the voltage drop of RLEAD1. Because the RRTD signal voltage is
measured differentially via inputs AIN2 and AIN3, the voltages across the lead wire resistance cancel. Resistor
RBIAS level-shifts the RTD signal voltage to within the ADC input range. The current sources route to the RTD
element through low VF diodes to provide input fault protection.
5 V
3.3 V
1 µF
10 mF
0.1 mF
1 µF
DVDD
AVDD
BYPASS
IDAC1
AVDD
CAPP
CAPN
IIDAC1
AINCOM
(IDAC1)
ADS1260
ADS1261
4.7 nF
C0G
500 ꢀA
CCM4
RF4
(REFP0)
(REFN0)
AIN0
AIN1
REFOUT
Internal
Reference
RREF
Reference Mux
CDIF2
RF3
10 mF
CCM3
Ref
Mon
Buf
3-Wire RTD
RLEAD1
START
RESET
PWDN
CCM2
RF2
AIN2
AIN3
CS
Input
Mux
Serial
Interface
and
Digital
Filter
CDIF1
PGA
RRTD
ADC
DIN
RLEAD2
RF1
DOUT/DRDY
SCLK
Control
CCM1
DRDY
Signal
Mon
IDAC2
AVDD
IIDAC2
(IDAC2)
AIN4
Clock
Mux
Internal
Oscillator
CLKIN
500 ꢀA
AVSS
DGND
RLEAD3
IIDAC1 + IIDAC2
RBIAS
图 99. RTD Element With 3-Wire Lead Resistance Compensation
10.2.1 Design Requirements
The key considerations in the design of a 3-wire RTD circuit are the accuracy, stability and noise of the
measurement, accuracy of the lead-wire compensation and self-heating of the sensor. Stability of the
measurement is determined by the offset and gain drift of the ADC and by the drift of the external reference
resistor. Measurement noise is determined by the ADC sample rate and by the digital filter settings. These
parameters are not summarized here. 表 45 summarizes the basic design goals for a 3-wire Pt100 RTD.
表 45. Design Goals
DESIGN PARAMETER
RTD sensor type
VALUE
3-wire Pt100
20 Ω to 400 Ω
0 Ω to 10 Ω
< 1 mW
RTD resistance range
RTD lead resistance range
RTD self heating
76
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表 46 summarize the parameters of the detailed design procedure that follows.
表 46. Design Parameters
DESIGN PARAMETER
DESIGN VALUE
500 µA
0.1 mW
0.20 V
IIDAC
IDAC current
PRTD
VRTD
Gain
RTD power dissipation
RTD input voltage
ADC gain
8
VREF
RREF
RBIAS
VRTDN
VRTDP
VIDAC1
Reference voltage (design target allows for 10% overrange)
Reference resistor (senses the IDAC current to generate VREF
Bias resistor (provides the RTD level-shift voltage)
RTD negative input voltage
1.76 V
)
3.52 kΩ
1.10 kΩ
1.1 V
RTD positive input voltage
1.31 V
IDAC1 loop voltage
3.37 V
10.2.2 Detailed Design Procedure
IDAC1 current flows through reference resistor, RREF, which generates the ADC reference voltage, VREF = IIDAC1
·
RREF. IDAC1 current also flows through the RTD element. Since the same current flows through RREF and the
RTD element, the RTD measurement is ratiometric, which means the drift and error of the current source are
cancelled. Therefore, the measurement accuracy is solely dependent on the tolerance of RREF and on ADC gain
and offset errors. The errors are calibrated by host software control using shorted-input calibration and using a
400 Ω precision resistor for full-scale calibration.
The current of IDAC2 is programmed to the same value as IDAC1 and is connected to RLEAD2. IDAC2 generates
an equal voltage drop across RLEAD1 and IDAC1. The accuracy of lead-wire compensation depends on the
matching error between IDAC1 to IDAC2.
Using RRTD = 400 Ω, IDAC current = 500 µA, and gain = 8, the minimum ADC reference voltage requirement
calculates to 1.6 V. To provide 10% design margin, RREF calculates to 3.52 kΩ (1.76 V / 500 µA). 500 µA is
selected to minimize heating of the sensor.
Resistor RBIAS level-shifts the RTD voltage to meet the input range requirement of the ADC. This voltage is VRTDN
and the low limit is calculated by 公式 8. The VRTDN low limit is 1 V.
AVSS + 0.3 V + VRTD · (Gain – 1) / 2 ≤ VRTDN
(8)
Using 10% design margin, RBIAS calculates to 1.1 kΩ = 1.1 V / (2 · 500 µA). The next step is to verify the positive
RTD voltage (VRTDP) does not exceed the maximum input range, as shown in 公式 9:
Maximum VRTDP ≤ AVDD – 0.3 V – VRTD · (Gain – 1) / 2
(9)
Evaluation of the equation results in the VRTDP high limit = 3.75 V. Calculate the actual VRTDP input voltage by 公
式 10:
Actual VRTDP = VRTDN + IIDAC1 · ( RRTD + 2 · RLEAD) = 1.1 V + 500 µA · (400 Ω + 20 Ω) = 1.31 V
(10)
VRTDN = 1.1 V and VRTDP = 1.31 V satisfy the negative and positive input voltage requirements of the ADC,
respectively.
Verify the burden voltage of current source IDAC1 is below the specified compliance range. The burden voltage
is the sum of voltages in the IDAC1 loop as calculated by VRTDP+ (IDAC1 · RREF) + VD ( VD= external diode
voltage). The result is 3.37 V, which meets the specified compliance voltage of the current source.
External filter components RF1, RF2, CDIF1, CCM1, CCM2) and RF3, RF4, CDIF2, CCM3, and CCM4) filter the signal and
reference inputs of the ADC. The filters remove both differential and common-mode noise. The input signal
differential filter cutoff frequency as calculated by 公式 11:
fDIF = 1 / [2π · RF1 + RF2) · RDIF1 + CM1|| CM2)]
(11)
The Input signal common-mode filter is calculated by 公式 12:
fCM = 1 / (2π · RF1 · CM1) = 1 / (2π · RF2 · CM2
)
(12)
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Component mismatch in the common-mode filter converts common-mode noise into differential noise. Use a
differential capacitor CDIF1 10× higher value than the common-mode capacitors, CCM1 and CCM2 to minimize the
effects of mismatch. The recommended range of input resistors is 1 kΩ to 10 kΩ; increasing the resistance
beyond 10 kΩ beyond can compromise noise and drift performance of the ADC. Use high-quality C0G ceramics
or film-type capacitors. For consistent noise performance across the full RTD temperature range, match the
corner frequencies of the input and reference filters. Detailed information is found in the RTD Ratiometric
Measurements and Filtering Using the ADS1148 and ADS1248 Family of Devices application report.
10.2.3 Application Curves
图 100 shows the resistance measurement results. The measurements are taken at TA = 25°C. The data are
taken using a precision resistor simulator with a 3-wire connection in place of the RTD. A system offset
calibration is performed using shorted inputs. A system gain calibration is performed using a 390-Ω precision
resistor. The measurement data are in ohms and do not include the error of the RTD sensor. The measured
resistance error is < ±0.02 Ω over the 20-Ω to 400-Ω range.
0.1
0.05
0
-0.05
-0.1
0
50
100
150
200
250
300
350
400
RTD Value (W)
图 100. 3-Wire RTD Example Measurement Results
78
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10.3 Initialization Setup
图 101 shows a general configuration and measurement procedure.
Power On
/* These pins must be high for operation
Set RESET and PWDN high
Y
External clock?
N
Apply clock to CLKIN
/* ADC automatically detects external clock
N
/* DRDY is held low at power-on until ready for communication
/* If START pin is low, conversions are stopped
DRDY pin high?
Y
Y
START high?
DRDY pulses at 20 Hz
N
Set START low or
STOP command
/* For simplicity, stop conversions before register configuration
/* Write register data, CRC verfication is optional
/* Readback register data for verification
DRDY not pulsing
Configure the ADC
Verify registers
Wait for reference
voltage to settle
/* The internal reference requires time to settle after power-on
/* Start or restart new ADC conversion
Set START pin high
or START command
N
/* Read data at a rate faster than
the data rate to avoid missed data
Hardware DRDY?
Y
Read STATUS register
N
/* New data when DRDY bit =1
DRDY bit asserted ?
N
DRDY pin low ?
Y
Y
Read Data
N
Change ADC
settings ?
Y
图 101. ADC Configuration and Measurement Procedure
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11 Power Supply Recommendations
The ADC requires an analog power supply (AVDD, AVSS) and digital power supply (DVDD). The analog power
supply can be bipolar (AVDD = +2.5 V and AVSS = –2.5 V) or unipolar (AVDD = 5 V and AVSS = DGND). The
digital supply range is 2.7 V to 5.25 V. DVDD powers the ADC core by use of an internal regulator. DVDD also
sets the digital I/O voltage. Keep in mind that the GPIO I/O voltages are AVDD and AVSS. Voltage ripple
produced by switch-mode power supplies may interfere with the ADC conversions. Use low-dropout regulators
(LDOs) to reduce switch-mode power supply ripple.
11.1 Power-Supply Decoupling
Good power-supply decoupling is important in order to achieve optimum performance. Power supplies must be
decoupled close to the power supply pins using short, direct connections to ground. For the analog supply, place
0.1-µF and 10-µF capacitors between AVDD and AVSS and 0.1-µF capacitors from each supply to ground.
Connect a 1-µF capacitor from DVDD to the ground plane. Connect a 1-µF capacitor from BYPASS to the
ground plane.
11.2 Analog Power-Supply Clamp
It is important to evaluate circumstances when an input signal is present with the ADC, both powered and
unpowered. When the input signal exceeds the power-supply voltage, it is possible to backdrive the analog
power-supply voltage with the input signal through a conduction path of the internal ESD diodes. Backdriving the
ADC power supply can also occur when the power-supply is on. The backdriven current path is illustrated in 图
102. Depending on how the power supply responds during a backdriven condition, it is possible to exceed the
maximum rated ADC supply voltage. The ADC voltage must not be exceeded at all times. One solution is to
clamp the analog supply to safe voltage using an external zener diode.
ADC supply On or Off
IFAULT
+V
+5 V Reg
AVDD
RLIMIT
ESD Diode
AINx
Optional
+
6-V Zener Diode
ADC
Input Voltage
œ
AINx
IFAULT
ESD Diode
IFAULT
AVSS
图 102. Analog Power-Supply Clamp
11.3 Power-Supply Sequencing
The power supplies can be sequenced in any order, but do not allow the analog or digital inputs to exceed the
respective analog or digital power-supplies without external limits of the possible input fault currents.
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12 Layout
Good layout practices are crucial to realize the full-performance of the ADC. Poor grounding can quickly degrade
the noise performance. The following layout guidelines help provide the best results.
12.1 Layout Guidelines
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane
may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the
ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground
loops.
Route digital traces away from the CAPP and CAPN pins, away from the REFOUT pin, and away from all analog
inputs and associated components in order to minimize interference.
Avoid long traces on DOUT/DRDY, because high capacitance on this pin can lead to increase of ADC noise
levels. Use a series resistor or a buffer if long traces are used.
The internal reference output return shares the same pin as the AVSS power supply. To minimize coupling
between the power supply and reference-return trace, route the traces separately; ideally, as a star connection to
the AVSS pin.
Use C0G capacitors on the analog inputs and for the CAPP to CAPN capacitor. Use ceramic capacitors (for
example, X7R grade) for the power supply decoupling capacitors. High-K capacitors (Y5V) are not
recommended. The REFOUT pin requires a 10-µF capacitor and can be either ceramic or tantalum type. Place
the required capacitors as close as possible to the device pins using short, direct traces. For optimum
performance, use low-impedance connections on the ground-side connections of the bypass capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination
resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to
noise within the conversion data.
12.2 Layout Example
图 103 is an example layout of the ADS1261, requiring a minimum of three PCB layers. The example circuit is
shown with single supply operation (AVSS = DGND). In this example, the inner layer is dedicated to the ground
plane and the outer layers are used for signal and power traces. If a four-layer PCB is used, dedicate the
additional inner layer as the power plane. In this example, the ADC is oriented in such a way to minimize
crossover of the analog and digital signal traces.
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Layout Example (接下页)
ADC Clock Options:
Option 1: To enable INTERNAL
oscillator, tie CLKIN to
GND
C0G
DVDD
Supply
(Differential Input Pair)
Option 2: Connect EXTERNAL
clock source to CLKIN
1 µF
C0G
1 µF
(Leave NC pins floating)
16
15
AIN7 25
(Differential Input Pair)
AIN6 26
DGND
BYPASS
14 DOUT/DRDY
DRDY
AIN5 27
(Differential Input Pair)
ADS1261
13
AIN4 28
C0G
C0G
C0G
12 DIN
AIN3 29
(Differential Input Pair)
To
Analog
Circuitry
Connect thermal pad to
AVSS
11 SCLK
AIN2 30
CS
10
9
AIN1 31
(Differential Input Pair)
AIN0 32
START
To
MCU
4.7 nF
C0G
(0805 shown)
(0805 shown)
10 µF
10 µF
1 µF
AVDD
Supply
(0603 shown)
(9-mil traces shown)
Reference
Output
For Unipolar Supply,
AVSS = GND
图 103. ADS1261 Layout Example
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13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档：
德州仪器 (TI)，ADS1261 和 ADS1235 评估模块用户指南
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 47. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
ADS1260
ADS1261
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
2X
SYMM
33
3.5
0.3
32X
0.2
24
0.1
C A B
1
0.05
C
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223442/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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87
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1260BIRHBR
ADS1260BIRHBT
ADS1261BIRHBR
ADS1261BIRHBT
ADS1261IRHBR
ADS1261IRHBT
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
32
32
32
32
32
32
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
ADS
1260B
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RHB
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
ADS
1260B
RHB
ADS
1261B
RHB
ADS
1261B
RHB
ADS
1261
RHB
ADS
1261
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1260BIRHBR
ADS1260BIRHBT
ADS1261BIRHBR
ADS1261BIRHBT
ADS1261IRHBR
ADS1261IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
3000
250
330.0
180.0
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
1.1
1.1
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1260BIRHBR
ADS1260BIRHBT
ADS1261BIRHBR
ADS1261BIRHBT
ADS1261IRHBR
ADS1261IRHBT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RHB
RHB
RHB
RHB
RHB
RHB
32
32
32
32
32
32
3000
250
346.0
210.0
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
33.0
35.0
3000
250
3000
250
Pack Materials-Page 2
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