ADS1262IPWR [TI]
适用于工厂自动化且具有 PGA 和电压基准的 32 位 38kSPS 10 通道 Δ-Σ ADC | PW | 28 | -40 to 125;
| 型号： | ADS1262IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于工厂自动化且具有 PGA 和电压基准的 32 位 38kSPS 10 通道 Δ-Σ ADC | PW | 28 | -40 to 125 |
| 文件： | 总136页 (文件大小：4201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1262, ADS1263
ZHCSDN4C –FEBRUARY 2015 –REVISED MAY 2021
具有可编程增益放大器(PGA) 和电压基准的ADS126x 32 位、38kSPS、精密模
数转换器(ADC)
1 特性
3 说明
• 32 位精密Δ-ΣADC
• 24 位辅助Δ-ΣADC (ADS1263)
• 数据速率：2.5SPS 至38400SPS
• 差分输入，CMOS PGA
• 11 个多功能模拟输入
• 高精度架构：
ADS1262 和ADS1263 (ADS126x) 是具有集成 PGA、
电压基准和内部故障监视器的低噪声、低漂移、
38.4kSPS、Δ-Σ ADC。ADS1263 集成了一个 24 位
辅助Δ-ΣADC，适用于后台测量。这种支持传感器的
ADC 提供了一套完备的高精度、单芯片测量解决方
案，可满足要求极为严苛的传感器应用需求，其中包括
称重秤、应变计传感器、热电偶和电阻式温度器件
(RTD)。
– 温漂：1nV/°C
– 增益漂移：0.5ppm/°C
– 噪声：7nVRMS（2.5SPS，增益= 32）
– 线性度：3ppm
ADC 由低噪声 CMOS PGA（增益范围为 1 至 32）、
Δ-Σ 调制器以及可编程数字滤波器组成。模拟前端
(AFE) 非常灵活，其包含两个传感器激励电流源，非常
适合直接进行RTD 测量。
• 2.5V 内部电压基准：
– 温漂：2ppm/°C
• 50Hz 和60Hz 抑制
• 单周期稳定转换
• 双传感器激励电流源
• 内部故障监测器
单周期稳定数字滤波器可更大限度提高多输入转换吞吐
量，同时能够为 50Hz 和 60Hz 线路周期干扰提供
130dB 抑制。
• 内部ADC 测试信号
• 8 个通用输入/输出
ADS1262 与 ADS1263 的引脚和功能彼此兼容。这两
款器件均采用28 引脚TSSOP 封装，
并且额定工作温度范围均为-40°C 至+125°C。
2 应用
器件信息(1)
• 工厂自动化和控制：
封装尺寸（标称值）
器件型号
ADS126x
封装
– 模拟输入模块
– 温度控制器
– 称重模块
TSSOP (28)
9.70mm x 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 仪表：
– 过程分析
– 实验室和现场仪表
– 称重秤
+5 V
0.25
+3.3 V
Input Range = ê78 mV
Data Rate = 20 SPS
Noise = 0.16 mVP-P
REFOUT
AVDD
DVDD
0.2
2.5-V Ref
ADS1262
ADS1263
Ref
Mux
0.15
+Exc
+Sen
+Sig
AIN0
AIN1
AIN2
AIN3
AIN4
Dual Sensor
Excitation
Ref
Alarm
0.1
0.05
0
œSig
Buf
START
RESET/PWDN
CS
œSen
Sensor Test
Bridge
AIN5
Serial
Interface
and
32-Bit
ûꢀ ADC
Digital
Filter
AIN6
AIN7
AIN8
DIN
PGA
œExc
DOUT/DRDY
Control
Input
Mux
SCLK
DRDY
-0.05
-0.1
-0.15
-0.2
-0.25
Signal
Alarm
AIN9
Pt 100
AINCOM
GPIO
Internal
Oscillator
24-Bit
ûꢀ ADC
Digital
Filter
PGA
Level Shift
Temp Sensor
Test V
XTAL2
ADS1263 Only
Clock
Mux
XTAL1/CLKIN
DGND
AVSS
0
1
2
3
4
5
Time (s)
6
7
8
9
10
温度补偿电桥测量
D017
ADC 转换噪声
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS661
ADS1262, ADS1263
ZHCSDN4C –FEBRUARY 2015 –REVISED MAY 2021
www.ti.com.cn
Table of Contents
8.8 Noise Performance................................................... 25
9 Detailed Description......................................................30
9.1 Overview...................................................................30
9.2 Functional Block Diagram.........................................31
9.3 Feature Description...................................................32
9.4 Device Functional Modes..........................................62
9.5 Programming............................................................ 86
9.6 Register Maps...........................................................89
10 Application and Implementation..............................107
10.1 Application Information......................................... 108
10.2 Typical Application................................................ 115
10.3 What To Do and What Not To Do..........................120
10.4 Initialization Setup.................................................121
11 Power Supply Recommendations............................123
11.1 Power-Supply Decoupling.....................................123
11.2 Analog Power-Supply Clamp................................ 124
11.3 Power-Supply Sequencing....................................124
12 Layout.........................................................................124
12.1 Layout Guidelines................................................. 124
12.2 Layout Example.................................................... 126
13 Device and Documentation Support........................127
13.1 接收文档更新通知................................................. 127
13.2 支持资源................................................................127
13.3 Trademarks...........................................................127
13.4 Electrostatic Discharge Caution............................127
13.5 Glossary................................................................127
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................4
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements: Serial Interface......................10
7.7 Switching Characteristics: Serial Interface................10
7.8 Timing Diagrams.......................................................10
7.9 Typical Characteristics..............................................12
8 Parameter Measurement Information..........................23
8.1 Offset Temperature Drift Measurement.....................23
8.2 Gain Temperature Drift Measurement.......................23
8.3 Common-Mode Rejection Ratio Measurement.........23
8.4 Power-Supply Rejection Ratio Measurement........... 24
8.5 Crosstalk Measurement (ADS1263)......................... 24
8.6 Reference-Voltage Temperature-Drift
Measurement.............................................................. 24
8.7 Reference-Voltage Thermal-Hysteresis
Measurement.............................................................. 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (July 2015) to Revision C (May 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式........................................................................................1
• 添加了指向应用部分的链接................................................................................................................................1
• Changed Functional Block Diagram to correct XTAL1/CLKIN pin name.......................................................... 31
• Added discussion to Internal Reference section regarding 10 μF (max) REFOUT capacitor ability to
decrease reference noise................................................................................................................................. 42
• Changed IDAC Block Diagram and text to include 2500 μA setting............................................................... 50
• Added last paragraph to Pulse Conversion Mode section to explain operation in chop mode.........................63
• Changed EBh to AFh in the example checksum computation in the Checksum Mode section....................... 73
• Changed text in GPIO Data Register section regarding GPIO data read when programmed as an output...104
• Changed calculation of VREFMIN to use gain = 8 in Detailed Design Procedure application section...............116
• Changed title of What To Do and What Not To Do from Do's and Don'ts ......................................................120
Changes from Revision A (May 2015) to Revision B (July 2015)
Page
• 将ADS1263 从产品预发布更改为量产数据，并在整个数据表中添加了ADS1263 和ADC2 的文本和规格.......1
• 更改了整个数据表中的文本，使之更加清晰....................................................................................................... 1
• Added condition line to Absolute Maximum Ratings table..................................................................................5
• Added Crosstalk section to Electrical Characteristics table................................................................................7
• Added 图7-32 ..................................................................................................................................................12
• Added 图7-36 ..................................................................................................................................................12
• Changed legend in 图7-45 ..............................................................................................................................12
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• Added missing gain term in FSR definition of 方程式8 ...................................................................................25
• Changed text in fourth paragraph of Noise Performance section to clarify conditions to achieve maximum
ENOB................................................................................................................................................................25
• Changed bit names from PGAH and PGAL to PGAH_ALM and PGAL_ALM, respectively, in PGA Absolute
Output-Voltage Monitor section........................................................................................................................ 40
• Changed 图9-12 to show correct name of bit 4............................................................................................... 41
• Changed RMUX to RMUXP in second paragraph of ADC Reference Voltage section.................................... 41
• Changed text in last paragraph of ADC Reference Voltage section to show correct name of bit 4..................41
• Changed text in External Reference section to clarify external reference inputs, polarity reversal switch,
reference input current, and external reference buffer..................................................................................... 42
• Changed text in Power-Supply Reference section to clarify use of power-supply reference in critical
applications.......................................................................................................................................................42
• Added ADC1 Modulator section....................................................................................................................... 42
• Changed text in last paragraph of Sensor-Excitation Current Sources (IDAC1 and IDAC2) section to clarify
settling time in IDAC rotation mode.................................................................................................................. 50
• Changed text in General-Purpose Input/Output (GPIO) section regarding GPIO data readback when
programmed as an output.................................................................................................................................53
• Changed 图9-27 ............................................................................................................................................. 53
• Changed TSIGP and TSIGN to TDACP and TDACN, respectively, in the last paragraph of the Test DAC
(TDAC) section................................................................................................................................................. 54
• Changed text in Test DAC (TDAC) section allowing for any common-mode value instead of 0 V................... 54
• Added note (1) to 图9-30 ................................................................................................................................ 58
• Changed th(DRSP) value of 16 from max to min.................................................................................................62
• Added stop-start sequence text to restart conversions in Continuous Conversion Mode section....................62
• Deleted software polling text from Data Ready ( DRDY) section..................................................................... 68
• Added Conversion Data Software Polling section............................................................................................ 68
• Added text to clarify data reset at conversion restart........................................................................................69
• Added text to Read Data Direct (ADC1) section to clarify conversion restart...................................................69
• Changed 图9-43 to show complete list of CRC bit settings.............................................................................69
• Changed text in Read Data by Command section to clarify software polling................................................... 70
• Changed 图9-44 to show complete list of CRC bit settings.............................................................................70
• Added text to Offset Calibration Registers section regarding offset calibration disabled in chop mode...........77
• Added new step 1 to Calibration Command Procedure section....................................................................... 80
• Added text to WREG Command section regarding conversion restart.............................................................88
• Changed text in 2nd paragraph of Register Map section................................................................................. 89
• Changed Group Update column of 表9-34 ..................................................................................................... 89
• Added software polling to 图10-16 ................................................................................................................121
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5 Device Comparison
PRODUCT
INPUTS
11
AUXILIARY 24-BIT ADC
ADS1262
No
ADS1263
11
Yes
6 Pin Configuration and Functions
AIN8
AIN9
1
2
3
4
5
28
27
26
25
24
23
22
21
20
AIN7
AIN6
AIN5
AIN4
AIN3
AIN2
AIN1
AINCOM
CAPP
CAPN
AVDD
AVSS
6
7
8
9
REFOUT
START
AIN0
RESET/PWDN
DVDD
CS
SCLK
19
18
17
16
15
10
11
12
DGND
BYPASS
XTAL2
DIN
DOUT/DRDY
DRDY
13
14
XTAL1/CLKIN
图6-1. PW Package, 28-Pin TSSOP, Top View (Not To Scale)
表6-1. Pin Functions
PIN
NAME
I/O
DESCRIPTION
NO.
1
AIN8
AIN9
Analog input/output Analog input 8, IDAC1, IDAC2, GPIO5
Analog input/output Analog input 9, IDAC1, IDAC2, GPIO6
Analog input/output Analog input common, IDAC1, IDAC2, GPIO7, VBIAS
2
3
AINCOM
CAPP
4
Analog output
Analog output
Analog
PGA output P: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN
PGA output N: connect a 4.7-nF C0G dielectric capacitor from CAPP to CAPN
Positive analog power supply
5
CAPN
6
AVDD
7
AVSS
Analog
Negative analog power supply
8
REFOUT
START
CS
Analog Output
Digital Input
Digital Input
Digital Input
Digital Input
Digital output
Digital output
Internal reference voltage output, connect 1-µF capacitor to AVSS
Start conversion control
9
10
11
12
13
14
Serial interface chip select (active low)
SCLK
Serial interface shift clock
DIN
Serial interface data input
DOUT/DRDY
DRDY
Serial interface data output and data ready indicator (active low)
Data ready indicator (active low)
1) Internal oscillator: Connect to DGND
15
16
XTAL1/CLKIN
XTAL2
Digital Input
Digital Input
2) External clock: Connect clock input
3) Crystal oscillator: Connect to crystal and crystal load capacitor
1) Internal oscillator: No connection (float)
2) External clock: No connection (float)
3) Crystal oscillator: Connect to crystal and crystal load capacitor
17
18
BYPASS
DGND
Analog Output
Digital
2-V sub-regulator external bypass; connect 1-µF capacitor to DGND
Digital ground
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表6-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NO.
19
20
21
22
23
24
25
26
27
28
NAME
DVDD
RESET/PWDN
AIN0
Digital
Digital power supply
Reset (active low); hold low to power down the ADC
Digital input
Analog input/output Analog input 0, REFP1, IDAC1, IDAC2
Analog input/output Analog input 1, REFN1, IDAC1, IDAC2
Analog input/output Analog input 2 ,REFP2, IDAC1, IDAC2
Analog input/output Analog input 3, REFN2, IDAC1, IDAC2, GPIO0
Analog input/output Analog input 4, REFP3, IDAC1, IDAC2, GPIO1
Analog input/output Analog input 5, REFN3, IDAC1, IDAC2, GPIO2
Analog input/output Analog input 6, IDAC1, IDAC2, GPIO3, TDACP
Analog input/output Analog input 7, IDAC1, IDAC2, GPIO4, TDACN
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
AVDD to AVSS
AVSS to DGND
7
V
V
V
V
0.3
7
–3
DVDD to DGND
Voltage
–0.3
Analog input
VAVDD + 0.3
V
AVSS –0.3
VDGND
0.3
–
Digital input
VDVDD + 0.3
V
Current
Input(2)
10
mA
°C
–10
–50
-60
Junction, TJ
Storage, Tstg
150
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds
VAVDD + 0.3 V or is below VAVSS –0.3 V, or if the digital input voltage exceeds VDVDD + 0.3 V or is below VDGND –0.3 V.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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MAX UNIT
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
POWER SUPPLY
VAVDD to VAVSS
Analog power supply
4.75
–2.6
2.7
5
5.25
V
VAVSS to VDGND
0
Digital power supply
ADC1 ANALOG INPUTS
FSR
Full-scale differential input voltage range(1)
VDVDD to VDGND
5.25
V
VREF / Gain
V
V
–VREF / Gain
PGA enabled
See 方程式12
VINP,VINN Absolute input voltage(2)
PGA bypassed
VAVDD + 0.1
V
AVSS –0.1
ADC2 ANALOG INPUTS (ADS1263)
Full-scale differential input voltage range
VREF / Gain
VAVDD + 0.1
V
V
–VREF / Gain
Gain = 1, 2 and 4
Gain = 8 to 128
V
AVSS –0.1
Absolute input voltage
See 方程式15
VOLTAGE REFERENCE INPUTS
V
AVDD –VAVSS
VREF
Differential reference voltage
0.9
V
VREF = VREFP –VREFN
+ 0.2
VREFN
VREFP
Negative reference voltage
Positive reference voltage
V
V
V
AVSS –0.1
VREFP –0.9
VREFN + 0.9
VAVDD + 0.1
CLOCK INPUT
External clock frequency
1
30%
1
7.3728
7.3728
8
70%
8
MHz
MHz
V
fCLK
External clock duty cycle
External crystal frequency
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Input voltage
VAVSS
VDGND
–40
VAVDD
VDVDD
125
DIGITAL INPUTS (other than GPIO)
Input voltage
V
TEMPERATURE
TA
Operating ambient temperature
°C
(1) FSR is the ideal full-scale differential input voltage range, excluding noise, offset and gain errors. For ADC1, the maximum FSR is
achieved with VREF = 5 V and the PGA bypassed. If the PGA is enabled and VREF = 5 V, the FSR is limited by the PGA input range.
For ADC2, if VREF = 5 V and gains = 8 to 128 then FSR is limited by the PGA input range.
(2) VINP, VINN = Absolute Input Voltage. VIN = Differential Input Voltage = VINP –VINN
.
7.4 Thermal Information
ADS126x
PW (TSSOP)
28 PINS
65.2
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
13.6
23.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
23.1
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS
with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC1 ANALOG INPUTS
Gain = 32
2
150
0.1
150
1
Absolute input current
Differential input current
nA
nA
PGA bypassed
Gain = 32
PGA bypassed, VIN = 5 V
PGA enabled
GΩ
MΩ
Differential input impedance
Channel-to-channel crosstalk
PGA bypassed
40
0.5
DC, VAVSS ≤VINX ≤VAVDD
μV/V
ADC1 PERFORMANCE
PGA gain
1, 2, 4, 8, 16, 32
V/V
Bits
SPS
Resolution
32
DR
INL
VOS
Data rate
2.5
38400
Noise performance
Integral nonlinearity
See 表8-1
3
Gain = 1 to 32, PGA bypassed
12
800 / Gain
±0.5 / Gain
ppm
Chop mode off
Chop mode on
350 / Gain
±0.1 / Gain
Noise / 4
TA = 25°C
μV
Offset voltage
After calibration(1)
Chop mode off
Chop mode on
30 / Gain + 10 100 / Gain + 50
Offset voltage drift
Gain error
nV/°C
ppm
1
±50
5
TA = 25°C, gain = 1 to 32
After calibration(1)
±300
GE
Noise / 4
0.5
Gain drift
Gain = 1 to 32, and PGA bypassed
4
ppm/°C
NMRR
CMRR
Normal-mode rejection ratio(2)
See 表9-6
fIN = 60 Hz, data rate = 20 SPS
fIN = 60 Hz, data rate = 400 SPS
AVDD and AVSS
130
120
90
Common-mode rejection ratio(3)
Power-supply rejection ratio(4)
dB
dB
100
80
PSRR
DVDD
80
120
ADC2 ANALOG INPUTS (ADS1263)
Absolute input current
Differential input current
ADC2 PERFORMANCE (ADS1263)
Gain
Gain = 16
Gain = 16
2
nA
nA
0.5
1, 2, 4, 8, 16, 32, 64, 128
V/V
Bits
SPS
Resolution
24
DR
Data rate
10, 100, 400, 800
Noise performance
See 表8-3
Gain = 1 to 64
4
20
30
INL
Integral nonlinearity
ppm
Gain = 128
7
VOS
Offset voltage
TA = 25°C, gain = 1 to 128
Gain = 1 to 128
±150
±500
200
μV
nV/°C
ppm
Offset voltage drift
Gain error
30
GE
TA = 25°C, gain = 1 to 128
Gain = 1 to 128
±500
±3000
5
Gain drift
1
See 表9-11
110
ppm/°C
NMRR
CMRR
PSRR
Normal-mode rejection ratio
fIN = 60 Hz, DR = 10 SPS
fIN = 60 Hz, DR = 400 SPS, gain = 8
AVDD and AVSS
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
75
75
90
90
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7.5 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS
with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CROSSTALK
ADC1 to ADC2
20
1
Crosstalk
μV/V
ADC2 to ADC1
EXTERNAL VOLTAGE REFERENCE INPUTS
ADC1
150
1
Reference input current(5)
nA
ADC2
Input current vs voltage
Input current drift
VREF = 2 V to 4.8 V, ADC1
ADC1
10
0.1
50
0.4
nA/V
nA/°C
MΩ
V
Input impedance
Differential, ADC1
Threshold, ADC1
Low reference monitor
INTERNAL VOLTAGE REFERENCE
Reference voltage
0.6
2.5
±0.1%
2
V
Initial accuracy
TA = 25°C
±0.2%
6
TA = 0°C to +85°C
TA = –40°C to +105°C
TA = 85°C, 1st 1000 hr
First 0°C to 85°C cycle
Reference voltage temperature drift
ppm/°C
4
12
Reference voltage long term drift
Thermal hysteresis
50
ppm
ppm
50
Output current
-10
10
mA
Load regulation
40
50
μV/mA
ms
Start-up time
Settling time to ±0.001% final value
TA = 25°C
TEMPERATURE SENSOR
Voltage
122.4
420
mV
Temperature coefficient
CURRENT SOURCES (IDAC1, IDAC2)
μV/°C
50, 100, 250, 500, 750,
1000, 1500, 2000, 2500, 3000
Currents
μA
Compliance range
Absolute error
All currents
VAVSS
V
V
AVDD –1.1
±4%
All currents
±0.7%
±0.1%
±1%
50
IDAC1 current = IDAC2 current
IDAC1 current ≠IDAC2 current
Absolute
±1%
Match error
Temperature drift
ppm/°C
Match
5
20
LEVEL-SHIFT VOLTAGE
Voltage
(VAVDD + VAVSS) / 2
100
V
Output impedance
SENSOR BIAS
Ω
Currents
±0.5, ±2, ±10, ±50, ±200
10
μA
MΩ
Pull-up/pull-down resistor
TEST DAC (TDAC)
DAC reference voltage
Differential output voltage
Absolute output voltage
Accuracy
V
V
V
V
AVDD –VAVSS
18 binary weighted settings
To VAVSS
4
4.5
–4
0.5
±0.1%
±1.5%
Output impedance
See 表9-8
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7.5 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, fCLK = 7.3728 MHz, ADC1 data rate = 20 SPS
with PGA enabled and gain = 1, and ADC2 data rate = 10 SPS with gain = 1 (unless otherwise noted)
PARAMETER
PGA OVER-RANGE MONITOR
Differential alarm
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Threshold
±105%
±1%
FSR
Differential alarm accuracy
±3%
Low threshold
High threshold
VAVSS + 0.2
V
V
Absolute alarm thresholds
V
AVDD –0.2
ADC CLOCK
fCLK
Internal oscillator frequency
Internal oscillator accuracy
External crystal start-up time
7.3728
±0.5%
20
MHz
ms
±2%
See 表9-21 for recommended crystals
GENERAL-PURPOSE INPUT/OUTPUTS (GPIO)(6)
VOH
VOL
VIH
VIL
High-level output voltage
Low-level output voltage
High-level input voltage
Low-level input voltage
Input hysteresis
IOH = 1 mA
0.8 · VAVDD
V
V
V
V
V
0.2 · VAVDD
VAVDD
IOL = –1 mA
0.7 · VAVDD
VAVSS
0.3 · VAVDD
0.5
DIGITAL INPUT/OUTPUT (Other Than GPIO)
IOH = 1 mA
IOH = 8 mA
IOL = –1 mA
IOL = –8 mA
0.8 · VDVDD
VOH
High-level output voltage
Low-level output voltage
V
V
0.75 · VDVDD
0.2 · VDVDD
0.2 · VDVDD
VOL
VIH
VIL
High-level input voltage
Low-level input voltage
Input hysteresis
0.7 · VDVDD
VDGND
VDVDD
V
V
0.3 · VDVDD
0.1
V
Input leakage
±10
μA
POWER SUPPLY
Active mode,
voltage reference off
ADS1262
4
Active mode,
voltage reference on
ADS1262
4.2
6.5
mA
IAVDD
IAVSS
Analog supply current
Active mode,
voltage reference on
ADS1263
4.3
2
6.5
15
Power-down mode
μA
mA
μA
ADS1262
Active mode
1
1.25
50
ADS1263
IDVDD
Digital supply current
Power dissipation
Power-down mode(7)
25
24
Active mode,
voltage reference on
ADS1262
37
mW
Active mode,
voltage reference on
PD
ADS1263
25
90
37
Power-down mode
240
μW
(1) Offset and gain calibration accuracy on the order of ADC conversion noise / 4. Conversion noise depends on data rate and PGA gain.
(2) Normal-mode rejection ratio depends on the digital filter setting.
(3) Common-mode rejection ratio is specified at date rate 20 SPS and 400 SPS.
(4) Power-supply rejection ratio is specified at dc.
(5) Specified with VAVSS ≤VREFN and VREFP ≤VAVDD. For reference input voltage exceeding VAVDD or VAVSS, the ADC1 reference input
current = 10 nA/ mV.
(6) GPIO input and output voltages are referenced to VAVSS
.
(7) External CLK input stopped. All other digital inputs maintained at VDVDD or VDGND
.
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7.6 Timing Requirements: Serial Interface
MIN
50
0
MAX
UNIT
ns
CS↓before first SCLK↑: delay time(1)
DRDY↓or DOUT/DRDY↓before first SCLK↑: delay time
Valid DIN to SCLK↓: setup time
td(CSSC)
td(DRSC)
tsu(DI)
ns
35
25
125
40
40
30
ns
th(DI)
ns
SCLK↓to valid DIN: hold time
tc(SC)
SCLK period(2)
106
ns
tw(SCH), w(SCL)
td(SCCS)
tw(CSH)
t
SCLK high pulse duration or SCLK low pulse duration
Last SCLK↓to CS↑: delay time
CS high pulse duration
ns
ns
ns
(1) CS can be tied low.
(2) If serial interface time-out mode enabled, minimum SCLK frequency = 1 kHz. If serial interface time-out mode disabled (default), there
is no minimum SCLK frequency.
7.7 Switching Characteristics: Serial Interface
over operating the ambient temperature range and DVDD = 2.7 V to 5.25 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tw(DRH)
DRDY high pulse duration
16
1/fCLK
CS↓to DOUT/DRDY driven:
propagation delay time
DOUT/DRDY load: 20 pF || 100 kΩto
DGND
tp(CSDO)
0
40
60
ns
ns
ns
ns
SCLK↑to valid DOUT/DRDY:
propagation delay time
DOUT/DRDY load: 20 pF || 100 kΩto
DGND
tp(SCDO)
th(SCDO)
tp(CSDOZ)
SCLK↑to invalid DOUT/DRDY:
hold time
DOUT/DRDY load: 20 pF || 100 kΩto
DGND
0
CS↑to DOUT/DRDY high impedance: DOUT/DRDY load: 20 pF || 100 kΩto
propagation delay time DGND
40
7.8 Timing Diagrams
DRDY
td(DRSC)
tw(CSH)
CS
td(CSSC)
td(SCCS)
tc(SC)
tw(SCH)
SCLK
DIN
tw(SCL)
tsu(DI)
th(DI)
图7-1. Serial Interface Timing Requirements
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tw(DRH)
DRDY
CS
SCLK
tp(CSDOZ)
tp(SCDO)
(A)
MSB
DOUT/DRDY
tp(CSDO)
th(SCDO)
图7-2. Serial Interface Switching Characteristics
VDVDD
½ VDVDD
VDGND
50%
td, th, tp, tw,tc
图7-3. Timing Reference
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7.9 Typical Characteristics
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
4
3
0.5
0.4
0.3
0.2
0.1
0
2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-1
-2
-3
-4
PGA Bypass
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Gain = 32
PGA Bypass
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Gain = 32
Gain = 4
Gain = 4
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D028
D029
After offset calibration, shorted inputs
Chop mode on, after offset calibration, shorted inputs
图7-4. ADC1 Offset Voltage vs Temperature
图7-5. ADC1 Offset Voltage vs Temperature
80
70
60
50
40
30
20
10
0
100
Gain = 1
Gain = 32
Gain = 1
Gain = 32
90
80
70
60
50
40
30
20
10
0
Input Referred Offset Voltage Drift (nV/èC)
Input Referred Offset Voltage Drift (nV/èC)
D064
D072
Shorted inputs, 30 units
Chop mode on, shorted inputs, 30 units
图7-6. ADC1 Offset Voltage vs Temperature Distribution
图7-7. ADC1 Offset Voltage vs Temperature Distribution
400
50
20 SPS, Gain = 1
20 SPS, Gain = 32
400 SPS, Gain = 1
7200 SPS, Gain = 1
38400 SPS, Gain = 1
300
25
0
200
100
0
-100
-200
-300
-25
PGA Bypass
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Gain = 32
Gain = 4
-50
-50
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
-25
0
25
50
75
100
125
Temperature (èC)
D054
D030
Shorted inputs
After gain calibration
图7-8. ADC1 Offset Voltage vs Reference Voltage
图7-9. ADC1 Gain Error vs Temperature
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
100
80
60
40
20
0
60
40
20
0
Gain = 1
Gain = 32
20 SPS, Gain = 1
20 SPS, Gain = 32
400 SPS, Gain = 1
7200 SPS, Gain = 1
38400 SPS, Gain = 1
-20
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
Gain Drift (ppm/èC)
D037
D053
30 units
图7-10. ADC1 Gain vs Temperature Distribution
图7-11. ADC1 Gain Error vs Reference Voltage
0.5
8
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
7
6
5
4
3
2
1
0
0.4
0.3
0.2
0.1
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D026
D027
20 SPS, sinc4
7200 SPS, sinc4
图7-12. ADC1 Noise vs Temperature
图7-13. ADC1 Noise vs Temperature
80
70
60
50
40
30
20
10
0
500
200
100
50
20 SPS, Gain = 1
20 SPS, Gain = 32
400 SPS, Gain = 1
7200 SPS, Gain = 1
38400 SPS, Gain = 1
20
10
5
2
1
0.5
0.2
0.1
0.05
0.02
0.01
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
D055
Output Voltage (mV)
D070
20 SPS, FIR filter, gain = 1, after offset calibration,
256 samples
20 SPS, 400 SPS, 7200 SPS = sinc4, 38400 SPS = sinc5
图7-15. ADC1 Output Reading Distribution
图7-14. ADC1 Noise vs Reference Voltage
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
120
100
80
60
40
20
0
3000
2700
2400
2100
1800
1500
1200
900
600
300
0
D056
Input Referred Voltage (mV)
Input Referred Voltage (mV)
D057
20 SPS, FIR filter, gain = 32, after offset calibration,
256 samples
7200 SPS, sinc4 filter, gain = 1, after offset calibration,
8192 samples
图7-16. ADC1 Output Reading Distribution
图7-17. ADC1 Output Reading Distribution
2100
0
-20
-40
-60
-80
1800
1500
1200
900
600
300
0
-100
-120
-140
-160
-180
0
1
2
3
4
5
6
Frequency (Hz)
7
8
9
10
D058
D059
Input Referred Voltage (mV)
20 SPS, gain = 1, 256 points
7200 SPS, sinc4 filter, gain = 32, after offset calibration,
8192 samples
图7-19. ADC1 Output Spectrum
图7-18. ADC1 Output Reading Distribution
0
8
6
Gain = 1
Gain = 32
-20
-40
4
-60
2
-80
0
-100
-120
-140
-160
-180
-2
-4
-6
-8
Gain = 1
Gain = 4
Gain = 16
Gain = 32
-100 -80 -60 -40 -20
0
VIN (% of FSR)
20
40
60
80 100
0
2
4
6
8
10
12
Frequency (kHz)
14
16
18
20
D024
D060
38400 SPS, 8192 points
图7-20. ADC1 Output Spectrum
图7-21. ADC1 INL vs VIN
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
6
5
4
3
2
1
0
60
50
40
30
20
10
0
Gain = 1
Gain = 4
Gain = 16
Gain = 32
-50
-25
0
25
50
75
100
125
0
1
2
3
4
5
INL (ppm)
6
7
8
9
10
Temperature (èC)
D033
D03041
Gain = 32, 30 units
图7-23. ADC1 INL Distribution
图7-22. ADC1 INL vs Temperature
10
8
180
150
120
90
20 SPS, Gain = 1
20 SPS, Gain = 32
20 SPS, Gain = 1
7200 SPS, Gain = 1
38400 SPS, Gain = 1
60
6
30
0
-30
-60
-90
-120
-150
-180
4
T = -40èC
T = 25èC
T = 85èC
T = 125èC
2
0
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
-5
-4
-3
-2
-1
0
1
2
Differential Input Voltage (V)
3
4
5
D052
D040
PGA bypassed
图7-24. ADC1 INL vs Reference Voltage
图7-25. ADC1 Differential Input Current
250
200
150
100
50
8
7
6
5
4
3
2
1
0
Gain = 1, T = -40èC
Gain = 1, T = 25èC
Gain = 1, T = 85èC
Gain = 1, T = 125èC
Gain = 4, T = -40èC
Gain = 4, T = 25èC
Gain = 4, T = 85èC
Gain = 4, T = 125èC
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0
0
0.5
1
1.5
2
2.5
3
3.5
Absolute Input Voltage (V)
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
Absolute Input Voltage (V)
4
4.5
5
D041
D042
PGA bypassed
Gain = 1, 4
图7-26. ADC1 Absolute Input Current
图7-27. ADC1 Absolute Input Current
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
8
7
6
5
4
3
2
1
0
3
Gain = 16, T = -40èC
Gain = 16, T = 25èC
Gain = 16, T = 85èC
Gain = 16, T = 125èC
Gain = 32, T = -40èC
Gain = 32, T = 25èC
Gain = 32, T = 85èC
Gain = 32, T = 125èC
PGA = 1, T = -40èC
PGA = 1, T = 25èC
PGA = 1, T = 85èC
PGA = 1, T = 125èC
PGA = 4, T = -40èC
PGA = 4, T = 25èC
PGA = 4, T = 85èC
PGA = 4, T = 125èC
2
1
0
-1
-2
-3
0
0.5
1
1.5
Absolute Input Voltage (V)
2
2.5
3
3.5
4
4.5
5
-100 -80 -60 -40 -20
0
Differential Input Voltage (% FSR)
20
40
60
80 100
D043
D044
Gain = 16, 32
Gain = 1, 4
图7-28. ADC1 Absolute Input Current
图7-29. ADC1 Differential Input Current
3
2
2.502
2.501
2.5
PGA = 16, T = -40èC
PGA = 16, T = 25èC
PGA = 16, T = 85èC
PGA = 16, T = 125èC
PGA = 32, T = -40èC
PGA = 32, T = 25èC
PGA = 32, T = 85èC
PGA = 32, T = 125èC
1
0
2.499
2.498
2.497
-1
-2
-3
-100 -80 -60 -40 -20
0
20
40
Differential Input Voltage (% FSR)
60
80 100
-50
-25
0
25
50
75
100
125
Temperature (èC)
D045
D0350
Gain = 16, 32
30 units
图7-30. ADC1 Differential Input Current
图7-31. Voltage Reference vs Temperature
80
60
40
20
0
0.01
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
-0.008
-0.01
-20
-40
-60
0
100 200 300 400 500 600 700 800 900 1000
Time (hr)
0
0.5
1
1.5
2
2.5
Time (s)
3
3.5
4
4.5
5
D086
D025
TA = 85°C, 30 units
图7-32. Voltage Reference Long-Term Drift
图7-33. Voltage Reference Start-Up Time
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
200
175
150
125
100
75
140
120
100
80
60
50
25
40
IREFP, T = -40èC
IREFP, T = 25èC
IREFP, T = 85èC
IREFP, T = 125èC
IREFN, T = -40èC
IREFN, T = 25èC
IREFN, T = 85èC
IREFN, T = 125èC
0
20
-25
-50
0
0.001
0.5
1
1.5
2
Reference Voltage (V)
2.5
3
3.5
4
4.5
5
0.01
0.1
1
Frequency (kHz)
10
100
1000
D031
D065
IREFP measured with VREFN = VAVSS, IREFN measured with
VREFP = VAVDD
图7-34. ADC1 Reference Input Current
图7-35. ADC1 CMRR vs Frequency
140
140
120
100
80
60
40
20
0
120
100
80
60
40
20
0
CMRR
PSRR (Analog)
PSRR (Digital)
Analog Supply
Digital Supply
0.001
0.01
0.1
1
Frequency (kHz)
10
100
1000
-50
-25
0
25
50
75
100
125
Temperature (èC)
D075
D069
图7-36. ADC1 PSRR vs Frequency
图7-37. ADC1 CMRR, PSRR vs Temperature
0.25
0
0.25
0
T = -40èC
T = 25èC
T = 85èC
T = 125èC
-0.25
-0.5
-0.75
-1
-0.25
-0.5
-0.75
-1
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0
0.5
1
1.5
IDAC Compliance Voltage (VAVDD - VAINX
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
IDAC Compliance Voltage (VAVDD - VAINx)
2
2.5
3
3.5
4
4.5
5
)
D046
D047
IIDAC = 250 μA
IIDAC = 1000 μA
图7-38. IDAC Error vs Compliance Voltage
图7-39. IDAC Error vs Compliance Voltage
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
0.25
0.1
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0
0
-0.25
-0.5
-0.75
-1
-0.1
-0.2
-0.3
T = -40èC
T = 25èC
T = 85èC
T = 125èC
0
0.5
1
1.5
2
2.5
3
3.5
IDAC Compliance Voltage (VAVDD - VAINX
4
4.5
5
0
0.5
1
1.5
2
2.5
3
3.5
IDAC Compliance Voltage (VAVDD - VAINX
4
4.5
5
)
)
D048
D049
IIDAC = 3000 μA
IIDAC1= IIDAC2 = 250 μA
图7-40. IDAC Error vs Compliance Voltage
图7-41. IDAC Current Error vs Compliance Voltage
50
170
160
150
140
130
120
110
100
90
40
30
20
10
0
-50
-25
0
25
50
75
100
125
D039
Temperature (èC)
Temperature Sensor Voltage (mV)
D038
TA = 25°C, 30 units
30 units
图7-43. Temperature Sensor Voltage Distribution
图7-42. Temperature Sensor Voltage vs Temperature
2
1.5
1
6
IAVDD,IAVSS
IDVDD, 20 SPS
IDVDD, 38400 SPS
5
4
3
2
1
0
0.5
0
-0.5
-1
-1.5
-2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D036
D032
30 units
图7-44. Internal Oscillator Frequency vs Temperature
图7-45. ADS1262 Active Current vs Temperature
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
110
108
106
104
102
100
0.25
0.24
0.23
0.22
0.21
0.2
0.19
0.18
0.17
0.16
0.15
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D001
D061
30 units
30 units
图7-46. ADC1 Differential Over-range Alarm Threshold vs
图7-47. ADC1 Absolute Low Alarm Threshold vs Temperature
Temperature
4.85
4.84
4.83
4.82
4.81
4.8
0.14
0.5 V
2.25 V
2.484375 V
2.5 V
2.515625 V
2.75 V
4.5 V
0.12
0.1
0.08
0.06
0.04
0.02
0
4.79
4.78
4.77
4.76
4.75
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D062
D067
30 units
图7-48. ADC1 Absolute High Alarm Threshold vs Temperature
图7-49. TDAC Error vs Temperature
10
8
60
55
50
45
40
35
30
25
20
15
10
5
Gain = 1
Gain = 64
6
4
2
0
-2
-4
Gain = 1
Gain = 4
Gain = 16
-6
-8
Gain = 64
-10
0
-50
-25
0
25
50
75
100
125
Temperature (èC)
Input Referred Offset Voltage Drift (nV/°C)
D080
D081
After offset calibration, shorted input
图7-50. ADC2 Offset Voltage vs Temperature
Inputs shorted, 30 units
图7-51. ADC2 Offset Voltage vs Temperature Distribution
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
100
75
100
80
60
40
20
0
Gain = 1
Gain = 4
Gain = 16
Gain = 64
Gain = 1
Gain = 64
50
25
0
-25
-50
-75
-100
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Temperature (èC)
Gain drift (ppm/èC)
D078
D079
After gain calibration
30 units
图7-52. ADC2 Gain vs Temperature
图7-53. ADC2 Gain vs Temperature Distribution
35
30
25
20
15
10
5
50
40
30
20
10
0
0
Input Referred Voltage (mV)
D091
D05962
Input Referred Voltage (mV)
Gain = 1, 10 SPS, after offset calibration, 128 samples
Gain = 128, 10 SPS, after offset calibration, 128 samples
图7-54. ADC2 Output Reading Distribution
图7-55. ADC2 Output Reading Distribution
6
10
Gain = 1
Gain = 4
Gain = 16
Gain = 64
Gain = 1
Gain = 4
Gain = 16
Gain = 64
4
2
8
6
0
4
2
0
-2
-4
-6
-100 -80 -60 -40 -20
0
20
VIN (% of FSR)
40
60
80 100
-50
-25
0
25
50
75
100
125
Temperature (èC)
D076
D077
图7-56. ADC2 INL vs VIN
图7-57. ADC2 INL vs Temperature
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
100
50
1000
500
Gain = 1
Gain = 4
Gain = 16
Gain = 64
10 SPS, Gain = 1
10 SPS, Gain = 4
10 SPS, Gain = 8
10 SPS, Gain = 16
800 SPS, Gain = 8
30
20
200
100
50
10
5
20
10
5
3
2
1
2
1
0.5
0.5
0.3
0.2
0.2
0.1
0.1
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
-50
-25
0
25
50
75
100
125
Temperature (èC)
D074
D090
10 SPS
图7-59. ADC2 Noise vs Reference Voltage
图7-58. ADC2 Noise vs Temperature
20
16
12
8
8
7
6
5
4
3
2
1
Gain = 1, T = -40èC
Gain = 1, T = 25èC
Gain = 1, T = 85èC
Gain = 1, T = 125èC
Gain = 4, T = -40èC
Gain = 4, T = 25èC
Gain = 4, T = 85èC
Gain = 4, T = 125èC
Gain = 16, T = -40èC
Gain = 16, T = 25èC
Gain = 16, T = 85èC
Gain = 16, T = 125èC
Gain = 64, T = -40èC
Gain = 64, T = 25èC
Gain = 64, T = 85èC
Gain = 64, T = 125èC
4
0
0
0
0
0.5
1
1.5
Absolute Input Voltage (V)
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
Absolute Input Voltage (V)
2.5
3
3.5
4
4.5
5
D082
D043
Gain = 1, 4
Gain = 16, 64
图7-60. ADC2 Absolute Input Current
图7-61. ADC2 Absolute Input Current
25
20
15
10
5
5
4
3
2
1
0
0
-5
-1
-2
-3
-4
-5
-10
-15
-20
-25
PGA = 1, T = -40èC
PGA = 1, T = 25èC
PGA = 1, T = 85èC
PGA = 1, T = 125èC
PGA = 4, T = -40èC
PGA = 4, T = 25èC
PGA = 4, T = 85èC
PGA = 4, T = 125èC
PGA = 16, T = -40èC
PGA = 16, T = 25èC
PGA = 16, T = 85èC
PGA = 16, T = 125èC
PGA = 64, T = -40èC
PGA = 64, T = 25èC
PGA = 64, T = 85èC
PGA = 64, T = 125èC
-100 -80 -60 -40 -20
0
20
40
Differential Input Voltage (% FSR)
60
80 100
-100 -80 -60 -40 -20
0
20
40
Differential Input Voltage (% FSR)
60
80 100
D084
D085
Gain = 1, 4
Gain = 16, 64
图7-62. ADC2 Differential Input Current
图7-63. ADC2 Differential Input Current
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7.9 Typical Characteristics (continued)
at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VDVDD = 3.3 V, VREF = 2.5 V, and fCLK = 7.3728 MHz (unless otherwise noted); typical
ADC1 characteristics at data rate = 20 SPS and gain = 1; typical ADC2 characteristics at data rate = 10 SPS and gain = 1
120
100
80
60
40
20
0
16
14
12
10
8
IREFP, T = -40èC
IREFP, T = 25èC
IREFP, T = 85èC
IREFP, T = 125èC
IREFN, T = -40èC
IREFN, T = 25èC
IREFN, T = 85èC
IREFN, T = 125èC
6
4
2
0
-2
-4
-6
0.001
0.01
0.1
1
Frequency (kHz)
10
100
1000
0.5
1
1.5
2
2.5
3
3.5
Reference Voltage (V)
4
4.5
5
D073
D031
IREFP measured with VREFN = VAVSS, IREFN measured with
VREFP = VAVDD
图7-64. ADC2 CMRR vs Frequency
图7-65. ADC2 Reference Input Current
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8 Parameter Measurement Information
8.1 Offset Temperature Drift Measurement
Offset temperature drift is defined as the maximum change of offset voltage measured over the specified
temperature range. The offset voltage drift is input referred and is calculated using the box method, as described
by 方程式1:
Offset Voltage Drift = (VOSMAX –VOSMIN) / (TMAX –TMIN
)
(1)
where
• VOSMAX and VOSMIN are the maximum and minimum offset voltages, respectively
• TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature
range
8.2 Gain Temperature Drift Measurement
Gain temperature drift is defined as the maximum change of gain error measured over the specified temperature
range. The gain error drift is calculated using the box method, as described by 方程式2:
Gain Error Drift = (GEMAX –GEMIN) / (TMAX –TMIN
)
(2)
where
• GEMAX and GEMIN are the maximum and minimum gain errors, respectively
• TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature
range
8.3 Common-Mode Rejection Ratio Measurement
Common-mode rejection ratio (CMRR) is defined as the rejection of the ADC output to an applied common-
mode input voltage. The common-mode input is 60 Hz with a peak-to-peak amplitude equal to the specified
absolute input voltage range. The standard deviation (RMS) value of the ADC output is calculated and scaled to
volts. In order to measure CMRR, record two ADC readings. The first reading (VA) is with no common-mode
input signal. The first reading represents the baseline ADC noise. The second reading (VB) is with the common-
mode input applied. The second reading represents the combination of the ADC baseline noise plus the
increased RMS noise caused by the common-mode input. The ADC baseline noise is extracted from the
combined noise to yield the noise induced by the common-mode input voltage. The CMRR measurement is
described by 方程式3:
CMRR = 20 · Log (VIC / VOC
)
(3)
where
• VIC = RMS value of the input common-mode voltage = 1.56 VRMS
2
2 0.5
• VOC = Calculated RMS value of output voltage = (VB –VA
)
• VA = RMS output voltage with no common-mode input
• VB = RMS output voltage with common-mode input
For gains > 1, add 6 dB of compensation value for each binary increase of gain.
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8.4 Power-Supply Rejection Ratio Measurement
Power-supply rejection ratio (PSRR) is defined as the rejection of the ADC output to the DC change of the power
supply voltage referred to the input range. PSRR is calculated using two ADC mean-value readings with inputs
shorted, scaled to volts. The first ADC reading (VOA) is acquired at one power-supply voltage, and the second
ADC reading (VOB) is acquired after changing the power-supply voltage by 0.5 V. The PSRR calculation is
described by 方程式4:
PSRR = 20 · Log |(VPSA–VPSB )/ (VOA –VOB)| –20 dB
(4)
where
• VPSA–VPSB = power-supply DC voltage change = 0.5 V
• VOA –VOB = ADC DC output voltage change (V)
• Range compensation factor = 20 · log (0.5 V / 5 V) = –20 dB for gain = 1
For gains > 1, add an additional 6 dB of compensation value for each binary increase of gain.
8.5 Crosstalk Measurement (ADS1263)
Crosstalk is defined as the unintended coupling of signals between ADC1 and ADC2. Measure crosstalk by
changing the dc input voltage of one ADC and measuring the rejection of the other ADC. The dc input voltage
change is 0.3 V, and the gain of the affected ADC is 16. Acquire two mean-value readings of the affected ADC
with inputs shorted. Take the first ADC reading (VOA) with VIN = 0 V, and take the second ADC reading (VOB
)
after changing the input voltage by 0.3 V. The crosstalk calculation is described by 方程式5:
Crosstalk = |(VOA –VOB) / (VINA –VINB)| · 106 (µV/V)
(5)
where
• VOA –VOB = DC output voltage change of the affected ADC
• VINA –VINB = DC input voltage change of the driven ADC = 0.3 V
8.6 Reference-Voltage Temperature-Drift Measurement
Internal reference-voltage temperature drift is defined as the maximum change in reference voltage measured
over the specified temperature range. The reference voltage drift is calculated using the box method, as
described by 方程式6:
Reference Drift = (VREFMAX –VREFMIN) / (VREFNOM · (TMAX –TMIN) ) · 106 (ppm)
(6)
where
• VREFMAX, VREFMIN and VREFNOM are the maximum, minimum and nominal (TA = 25°C) reference voltages,
respectively
• TMAX and TMIN are the maximum and minimum temperatures, respectively, over the specified temperature
range
8.7 Reference-Voltage Thermal-Hysteresis Measurement
Internal reference-voltage thermal hysteresis is defined as the change in reference voltage after operating the
device at TA = 25°C, cycling the device through the TA = 0°C to 85°C temperature range for ten minutes at each
temperature and returning to TA = 25°C. The internal reference thermal hysteresis is defined in 方程式7:
Reference Thermal Hysteresis = |VREFPRE –VREFPOST| / VREFPRE · 106 (ppm)
(7)
where
• VREFPRE and VREFPOST are the reference voltages before and after the temperature cycle, respectively
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8.8 Noise Performance
The ADC noise performance depends on the following ADC settings: PGA gain, data rate, digital filter mode, and
chop mode. Generally, the lowest input-referred noise is achieved using the highest gain possible, consistent
with the input signal range. Do not set the gain too high or the result is ADC overrange. Noise also depends on
the output data rate and mode of the digital filter. As the data rate reduces, the ADC bandwidth correspondingly
reduces. As the order of the digital filter mode increases, the ADC bandwidth also reduces. This reduction in
total bandwidth results in lower overall noise. The ADC noise is reduced by a factor of 1.4 with chop mode
enabled.
表 8-1 lists ADC1 noise performance in units of μVRMS (RMS = root mean square) under the conditions shown.
The values in parenthesis are peak-to-peak values. 表 8-2 lists the noise performance in effective number of bits
(ENOB) with an external 5-V reference voltage. The values shown in parenthesis are noise-free bits. The
definition of noise-free bits is the resolution of the ADC with no code flicker. The noise-free bits data are based
on the µVPP values. Note that for data rate = 38400 SPS, noise scales with increased reference voltage. For all
other data rates, noise does not scale with reference voltage.
表 8-3 lists the noise performance of ADC2 (ADS1263) in units of μVRMS and (µVP–P). The values in
parenthesis are peak-to-peak values. 表8-4 lists the ENOB and noise-free bits of ADC2.
The ENOB and noise-free bits shown in the tables are calculated using 方程式8:
ENOB = ln (FSR / VNRMS) / ln (2)
(8)
where
• FSR = full scale range = 2 · VREF/Gain
• VNRMS = Input referred noise voltage
Achieve maximum ENOB with maximum FSR. For ADC1, achieve maximum FSR with VREF = 5 V and the PGA
bypassed. If the PGA is enabled, the FSR is limited by the PGA input range (see the Electrical Characteristics
table.) For ADC2, achieve maximum FSR with VREF = 5 V and gains = 1, 2, or 4. If gain = 8 to 128, then FSR is
limited by the PGA input range (see the Electrical Characteristics table).
For ADC1 operation, if the reference voltage is equal to 5 V and the PGA is enabled, the available FSR is
restricted because of the limited PGA range specification. For ADC2 operation, if the reference voltage is equal
to 5 V, The FSR is reduced for ADC2 gains equal to or greater than eight because of the limited PGA range.
The data shown in the noise performance tables represent typical ADC performance at TA = 25°C. The noise-
performance data are the standard deviation and peak-to-peak computations of the ADC data. Because of the
statistical nature of noise, repeated noise measurements may yield higher or lower noise results. The noise data
are acquired with inputs shorted, from consecutive ADC readings for a period of ten seconds or 8192 data
points, whichever occurs first.
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表8-1. ADC1 Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V
GAIN
DATA RATE
FILTER MODE
1
2
4
8
16
32
2.5 SPS
2.5 SPS
2.5 SPS
2.5 SPS
2.5 SPS
5 SPS
FIR
0.145 (0.637)
0.121 (0.510)
0.101 (0.437)
0.080 (0.307)
0.080 (0.308)
0.206 (1.007)
0.161 (0.726)
0.146 (0.661)
0.128 (0.611)
0.122 (0.587)
0.284 (1.418)
0.229 (1.220)
0.193 (1.019)
0.176 (0.896)
0.164 (0.788)
0.306 (1.708)
0.248 (1.401)
0.216 (1.221)
0.214 (1.169)
0.393 (2.467)
0.336 (1.861)
0.270 (1.560)
0.237 (1.415)
0.229 (1.285)
0.514 (2.925)
0.426 (2.400)
0.389 (2.324)
0.358 (2.319)
0.558 (3.574)
0.465 (2.753)
0.414 (2.704)
0.383 (2.288)
0.734 (4.715)
0.604 (3.662)
0.531 (3.431)
0.511 (3.340)
0.071 (0.279)
0.058 (0.249)
0.055 (0.225)
0.046 (0.195)
0.043 (0.180)
0.098 (0.448)
0.090 (0.432)
0.069 (0.308)
0.067 (0.325)
0.063 (0.269)
0.142 (0.753)
0.123 (0.662)
0.093 (0.488)
0.088 (0.452)
0.076 (0.389)
0.147 (0.810)
0.122 (0.729)
0.120 (0.667)
0.101 (0.544)
0.191 (1.102)
0.167 (0.964)
0.136 (0.745)
0.124 (0.701)
0.113 (0.612)
0.255 (1.584)
0.209 (1.217)
0.196 (1.185)
0.175 (1.023)
0.285 (1.703)
0.235 (1.424)
0.208 (1.187)
0.195 (1.174)
0.361 (2.276)
0.305 (1.934)
0.277 (1.780)
0.255 (1.632)
0.038 (0.149)
0.033 (0.143)
0.025 (0.104)
0.026 (0.116)
0.020 (0.078)
0.054 (0.252)
0.047 (0.246)
0.038 (0.195)
0.033 (0.153)
0.030 (0.144)
0.077 (0.379)
0.060 (0.322)
0.048 (0.254)
0.043 (0.217)
0.040 (0.200)
0.077 (0.436)
0.068 (0.403)
0.060 (0.332)
0.054 (0.302)
0.104 (0.603)
0.085 (0.486)
0.070 (0.376)
0.067 (0.399)
0.060 (0.325)
0.140 (0.940)
0.108 (0.666)
0.104 (0.624)
0.096 (0.597)
0.151 (0.913)
0.121 (0.760)
0.112 (0.655)
0.105 (0.623)
0.192 (1.209)
0.156 (1.072)
0.143 (0.935)
0.134 (0.861)
0.380 (2.657)
0.313 (2.280)
0.285 (1.991)
0.266 (1.947)
0.651 (5.044)
0.545 (4.107)
0.494 (3.833)
0.459 (3.405)
0.023 (0.089)
0.018 (0.073)
0.015 (0.064)
0.013 (0.052)
0.013 (0.049)
0.028 (0.123)
0.026 (0.120)
0.021 (0.100)
0.019 (0.095)
0.017 (0.076)
0.041 (0.197)
0.035 (0.177)
0.028 (0.149)
0.028 (0.137)
0.024 (0.119)
0.044 (0.250)
0.037 (0.213)
0.033 (0.197)
0.031 (0.175)
0.057 (0.353)
0.049 (0.266)
0.039 (0.231)
0.035 (0.192)
0.034 (0.193)
0.077 (0.457)
0.064 (0.381)
0.057 (0.367)
0.055 (0.319)
0.085 (0.515)
0.068 (0.417)
0.064 (0.396)
0.059 (0.347)
0.108 (0.679)
0.088 (0.579)
0.081 (0.545)
0.076 (0.479)
0.215 (1.469)
0.178 (1.313)
0.161 (1.132)
0.151 (1.061)
0.368 (2.807)
0.309 (2.315)
0.281 (2.145)
0.261 (2.018)
0.014 (0.064)
0.012 (0.054)
0.010 (0.043)
0.008 (0.034)
0.008 (0.031)
0.020 (0.098)
0.017 (0.083)
0.013 (0.061)
0.012 (0.054)
0.011 (0.048)
0.027 (0.156)
0.023 (0.118)
0.019 (0.099)
0.018 (0.091)
0.016 (0.081)
0.030 (0.176)
0.024 (0.136)
0.022 (0.130)
0.022 (0.129)
0.039 (0.222)
0.033 (0.191)
0.028 (0.149)
0.024 (0.130)
0.022 (0.123)
0.051 (0.315)
0.042 (0.265)
0.038 (0.228)
0.036 (0.217)
0.055 (0.335)
0.046 (0.276)
0.042 (0.276)
0.040 (0.242)
0.071 (0.473)
0.059 (0.371)
0.054 (0.343)
0.050 (0.322)
0.143 (1.066)
0.119 (0.884)
0.107 (0.781)
0.101 (0.708)
0.244 (1.846)
0.205 (1.586)
0.186 (1.374)
0.174 (1.337)
0.011 (0.051)
0.008 (0.037)
0.007 (0.031)
0.006 (0.023)
0.007 (0.027)
0.015 (0.073)
0.012 (0.057)
0.011 (0.050)
0.010 (0.046)
0.008 (0.039)
0.023 (0.118)
0.018 (0.103)
0.016 (0.079)
0.014 (0.067)
0.013 (0.065)
0.024 (0.138)
0.020 (0.111)
0.017 (0.095)
0.016 (0.092)
0.030 (0.167)
0.026 (0.138)
0.021 (0.111)
0.020 (0.109)
0.017 (0.098)
0.042 (0.264)
0.033 (0.200)
0.030 (0.179)
0.028 (0.176)
0.045 (0.271)
0.036 (0.208)
0.034 (0.197)
0.031 (0.188)
0.058 (0.362)
0.048 (0.321)
0.043 (0.288)
0.041 (0.271)
0.116 (0.843)
0.095 (0.676)
0.087 (0.630)
0.081 (0.583)
0.197 (1.519)
0.165 (1.283)
0.148 (1.094)
0.139 (1.032)
Sinc1
Sinc2
Sinc3
Sinc4
FIR
5 SPS
Sinc1
Sinc2
Sinc3
Sinc4
FIR
5 SPS
5 SPS
5 SPS
10 SPS
10 SPS
10 SPS
10 SPS
10 SPS
16.6 SPS
16.6 SPS
16.6 SPS
16.6 SPS
20 SPS
20 SPS
20 SPS
20 SPS
20 SPS
50 SPS
50 SPS
50 SPS
50 SPS
60 SPS
60 SPS
60 SPS
60 SPS
100 SPS
100 SPS
100 SPS
100 SPS
400 SPS
400 SPS
400 SPS
400 SPS
1200 SPS
1200 SPS
1200 SPS
1200 SPS
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
1.438 (10.374) 0.734 (5.410)
1.186 (8.523)
1.072 (7.923)
0.995 (7.107)
0.607 (4.333)
0.550 (3.999)
0.508 (3.664)
2.451 (17.755) 1.254 (9.305)
2.038 (15.480) 1.037 (8.128)
1.858 (14.005) 0.960 (7.223)
1.743 (13.428) 0.890 (6.585)
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表8-1. ADC1 Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V (continued)
GAIN
DATA RATE
FILTER MODE
1
2
4
8
16
32
2400 SPS
2400 SPS
2400 SPS
2400 SPS
4800 SPS
4800 SPS
4800 SPS
4800 SPS
7200 SPS
7200 SPS
7200 SPS
7200 SPS
14400 SPS
19200 SPS
38400 SPS
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
Sinc5
Sinc5
3.411 (26.095) 1.724 (13.528) 0.903 (6.609)
2.870 (21.677) 1.468 (11.032) 0.770 (5.932)
0.510 (3.920)
0.435 (3.379)
0.395 (3.035)
0.371 (2.869)
0.682 (5.252)
0.606 (4.777)
0.560 (4.176)
0.527 (4.004)
0.335 (2.626)
0.286 (2.123)
0.262 (1.951)
0.245 (1.885)
0.446 (3.239)
0.398 (2.986)
0.367 (2.890)
0.349 (2.626)
0.516 (3.881)
0.472 (3.531)
0.445 (3.590)
0.426 (3.261)
0.596 (4.430)
0.747 (5.725)
0.270 (2.107)
0.230 (1.758)
0.211 (1.533)
0.198 (1.576)
0.361 (2.957)
0.321 (2.397)
0.297 (2.211)
0.277 (2.184)
0.409 (3.189)
0.379 (2.792)
0.359 (2.666)
0.341 (2.467)
0.466 (3.524)
0.555 (4.058)
2.656 (20.100) 1.337 (9.936)
2.475 (19.447) 1.262 (9.452)
0.705 (5.355)
0.657 (4.966)
4.590 (34.155) 2.329 (17.298) 1.221 (8.943)
4.091 (30.903) 2.070 (15.168) 1.077 (8.141)
3.720 (28.423) 1.894 (14.842) 0.998 (7.626)
3.535 (27.437) 1.784 (13.760) 0.926 (7.273)
5.326 (42.076) 2.709 (19.749) 1.407 (11.126) 0.792 (5.784)
4.867 (36.820) 2.467 (18.627) 1.280 (9.874)
4.567 (35.194) 2.310 (17.516) 1.209 (9.036)
4.365 (34.008) 2.211 (17.432) 1.143 (8.804)
0.726 (5.612)
0.682 (5.181)
0.642 (5.075)
6.377 (48.242) 3.235 (25.178) 1.675 (12.508) 0.929 (7.280)
8.720 (65.389) 4.432 (32.931) 2.285 (17.055) 1.227 (9.870)
103.55 (759.91) 51.76 (371.46) 25.95 (192.20) 13.02 (99.09)
6.493 (46.060) 3.276 (24.435)
Copyright © 2021 Texas Instruments Incorporated
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表8-2. ADC1 ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V
GAIN
DATA RATE
FILTER MODE
1 (BYPASS)
26.0 (23.9)
26.3 (24.2)
26.6 (24.4)
26.9 (25.0)
26.9 (25.0)
25.5 (23.2)
25.9 (23.7)
26.0 (23.9)
26.2 (24.0)
26.3 (24.0)
25.1 (22.7)
25.4 (23.0)
25.6 (23.2)
25.8 (23.4)
25.9 (23.6)
25.0 (22.5)
25.3 (22.8)
25.5 (23.0)
25.5 (23.0)
24.6 (22.0)
24.8 (22.4)
25.1 (22.6)
25.3 (22.8)
25.4 (22.9)
24.2 (21.7)
24.5 (22.0)
24.6 (22.0)
24.7 (22.0)
24.1 (21.4)
24.4 (21.8)
24.5 (21.8)
24.6 (22.1)
23.7 (21.0)
24.0 (21.4)
24.2 (21.5)
24.2 (21.5)
22.7 (19.9)
23.0 (20.2)
23.2 (20.3)
23.3 (20.4)
22.0 (19.1)
22.2 (19.3)
22.4 (19.4)
22.5 (19.5)
2
4
8
16
32
2.5 SPS
2.5 SPS
2.5 SPS
2.5 SPS
2.5 SPS
5 SPS
FIR
25.9 (23.9)
26.2 (24.1)
26.3 (24.2)
26.5 (24.4)
26.6 (24.5)
25.4 (23.2)
25.5 (23.3)
25.9 (23.8)
26.0 (23.7)
26.1 (24.0)
24.9 (22.5)
25.1 (22.7)
25.5 (23.1)
25.6 (23.2)
25.8 (23.4)
24.8 (22.4)
25.1 (22.5)
25.1 (22.7)
25.4 (22.9)
24.5 (21.9)
24.7 (22.1)
24.9 (22.5)
25.1 (22.6)
25.2 (22.8)
24.0 (21.4)
24.3 (21.8)
24.4 (21.8)
24.6 (22.0)
23.9 (21.3)
24.2 (21.6)
24.3 (21.8)
24.4 (21.8)
23.5 (20.9)
23.8 (21.1)
23.9 (21.2)
24.0 (21.4)
22.5 (19.6)
22.8 (20.0)
22.9 (20.1)
23.0 (20.2)
21.7 (18.9)
22.0 (19.0)
22.1 (19.2)
22.2 (19.3)
25.8 (23.8)
26.0 (23.9)
26.4 (24.3)
26.3 (24.2)
26.7 (24.7)
25.3 (23.1)
25.5 (23.1)
25.8 (23.4)
26.0 (23.8)
26.1 (23.9)
24.8 (22.5)
25.1 (22.7)
25.4 (23.0)
25.6 (23.3)
25.7 (23.4)
24.8 (22.3)
24.9 (22.4)
25.1 (22.7)
25.3 (22.8)
24.3 (21.8)
24.6 (22.1)
24.9 (22.5)
25.0 (22.4)
25.1 (22.7)
23.9 (21.2)
24.3 (21.7)
24.3 (21.8)
24.4 (21.8)
23.8 (21.2)
24.1 (21.5)
24.2 (21.7)
24.3 (21.8)
23.5 (20.8)
23.8 (21.0)
23.9 (21.2)
24.0 (21.3)
22.5 (19.7)
22.7 (19.9)
22.9 (20.1)
23.0 (20.1)
21.7 (18.7)
21.9 (19.0)
22.1 (19.1)
22.2 (19.3)
25.5 (23.6)
25.9 (23.8)
26.1 (24.0)
26.3 (24.3)
26.3 (24.4)
25.2 (23.1)
25.4 (23.1)
25.7 (23.4)
25.8 (23.5)
25.9 (23.8)
24.7 (22.4)
24.9 (22.6)
25.2 (22.8)
25.2 (22.9)
25.5 (23.1)
24.6 (22.1)
24.8 (22.3)
25.0 (22.4)
25.1 (22.6)
24.2 (21.6)
24.4 (22.0)
24.7 (22.2)
24.9 (22.4)
25.0 (22.4)
23.8 (21.2)
24.0 (21.5)
24.2 (21.5)
24.3 (21.7)
23.6 (21.0)
24.0 (21.3)
24.0 (21.4)
24.1 (21.6)
23.3 (20.6)
23.6 (20.9)
23.7 (20.9)
23.8 (21.1)
22.3 (19.5)
22.6 (19.7)
22.7 (19.9)
22.8 (20.0)
21.5 (18.6)
21.8 (18.9)
21.9 (19.0)
22.0 (19.1)
25.4 (23.0)
25.6 (23.3)
25.8 (23.6)
26.1 (23.9)
26.2 (24.1)
24.8 (22.4)
25.0 (22.7)
25.4 (23.1)
25.6 (23.3)
25.7 (23.5)
24.4 (21.8)
24.6 (22.2)
24.9 (22.4)
25.0 (22.5)
25.1 (22.7)
24.2 (21.6)
24.6 (21.9)
24.6 (22.0)
24.7 (22.0)
23.9 (21.2)
24.1 (21.5)
24.3 (21.8)
24.5 (22.0)
24.6 (22.1)
23.5 (20.7)
23.7 (21.0)
23.9 (21.2)
24.0 (21.3)
23.4 (20.6)
23.6 (20.9)
23.7 (20.9)
23.8 (21.1)
23.0 (20.1)
23.2 (20.5)
23.4 (20.6)
23.5 (20.7)
22.0 (19.0)
22.2 (19.2)
22.4 (19.4)
22.5 (19.6)
21.2 (18.2)
21.5 (18.4)
21.6 (18.6)
21.7 (18.6)
24.6 (22.4)
25.0 (22.8)
25.2 (23.1)
25.6 (23.5)
25.2 (23.3)
24.1 (21.9)
24.4 (22.2)
24.6 (22.4)
24.7 (22.5)
25.0 (22.8)
23.5 (21.2)
23.8 (21.4)
24.1 (21.7)
24.2 (22.0)
24.4 (22.0)
23.5 (20.9)
23.7 (21.2)
23.9 (21.5)
24.0 (21.5)
23.1 (20.7)
23.3 (20.9)
23.6 (21.2)
23.7 (21.3)
23.9 (21.4)
22.6 (20.0)
23.0 (20.4)
23.1 (20.6)
23.2 (20.6)
22.5 (20.0)
22.9 (20.3)
23.0 (20.4)
23.1 (20.5)
22.2 (19.5)
22.4 (19.7)
22.6 (19.9)
22.7 (20.0)
21.2 (18.3)
21.5 (18.6)
21.6 (18.7)
21.7 (18.8)
20.4 (17.5)
20.7 (17.7)
20.8 (17.9)
20.9 (18.0)
Sinc1
Sinc2
Sinc3
Sinc4
FIR
5 SPS
Sinc1
Sinc2
Sinc3
Sinc4
FIR
5 SPS
5 SPS
5 SPS
10 SPS
10 SPS
10 SPS
10 SPS
10 SPS
16.6 SPS
16.6 SPS
16.6 SPS
16.6 SPS
20 SPS
20 SPS
20 SPS
20 SPS
20 SPS
50 SPS
50 SPS
50 SPS
50 SPS
60 SPS
60 SPS
60 SPS
60 SPS
100 SPS
100 SPS
100 SPS
100 SPS
400 SPS
400 SPS
400 SPS
400 SPS
1200 SPS
1200 SPS
1200 SPS
1200 SPS
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: ADS1262 ADS1263
ADS1262, ADS1263
ZHCSDN4C –FEBRUARY 2015 –REVISED MAY 2021
www.ti.com.cn
表8-2. ADC1 ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V (continued)
GAIN
DATA RATE
FILTER MODE
1 (BYPASS)
21.5 (18.5)
21.7 (18.8)
21.8 (18.9)
21.9 (19.0)
21.1 (18.2)
21.2 (18.3)
21.4 (18.4)
21.4 (18.5)
20.8 (17.9)
21.0 (18.1)
21.1 (18.1)
21.1 (18.2)
20.6 (17.7)
20.1 (17.2)
15.6 (12.6)
2
4
8
16
32
2400 SPS
2400 SPS
2400 SPS
2400 SPS
4800 SPS
4800 SPS
4800 SPS
4800 SPS
7200 SPS
7200 SPS
7200 SPS
7200 SPS
14400 SPS
19200 SPS
38400 SPS
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
Sinc5
Sinc5
21.3 (18.3)
21.5 (18.6)
21.7 (18.8)
21.7 (18.8)
20.8 (18.0)
21.0 (18.1)
21.1 (18.2)
21.2 (18.3)
20.6 (17.8)
20.8 (17.8)
20.9 (17.9)
20.9 (17.9)
20.4 (17.4)
19.9 (17.0)
15.4 (12.6)
21.2 (18.3)
21.4 (18.5)
21.6 (18.6)
21.7 (18.8)
20.8 (17.9)
21.0 (18.0)
21.1 (18.1)
21.2 (18.2)
20.6 (17.6)
20.7 (17.8)
20.8 (17.9)
20.9 (17.9)
20.3 (17.4)
19.9 (17.0)
15.4 (12.5)
21.0 (18.1)
21.3 (18.3)
21.4 (18.5)
21.5 (18.5)
20.6 (17.7)
20.8 (17.8)
20.9 (18.0)
21.0 (18.1)
20.4 (17.5)
20.5 (17.6)
20.6 (17.7)
20.7 (17.7)
20.2 (17.2)
19.8 (16.8)
15.3 (12.5)
20.7 (17.7)
21.0 (18.0)
21.1 (18.1)
21.2 (18.2)
20.3 (17.4)
20.5 (17.5)
20.6 (17.5)
20.7 (17.7)
20.1 (17.1)
20.2 (17.2)
20.3 (17.2)
20.4 (17.4)
19.9 (16.9)
19.6 (16.6)
15.5 (12.6)
20.0 (17.0)
20.2 (17.3)
20.3 (17.5)
20.4 (17.4)
19.5 (16.5)
19.7 (16.8)
19.8 (16.9)
19.9 (16.9)
19.4 (16.4)
19.5 (16.6)
19.5 (16.7)
19.6 (16.8)
19.2 (16.3)
18.9 (16.0)
15.4 (12.5)
表8-3. ADC2 (ADS1263) Noise in µVRMS (µVPP) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 2.5 V
GAIN
DATA RATE FILTER
1
2
4
8
16
32
64
128
10 SPS
Sinc1
Sinc3
Sinc3
Sinc3
7.34 (32.6) 3.54 (16.5) 1.52 (7.57) 0.87 (4.22) 0.47 (2.42) 0.28 (1.43) 0.20 (1.08) 0.14 (0.70)
10.3 (65.2) 5.58 (36.0) 3.13 (20.4) 1.80 (11.5) 0.96 (6.30) 0.62 (4.03) 0.48 (3.08) 0.32 (2.04)
100 SPS
400 SPS
800 SPS
56.8 (827)
29.2 (345)
15.3 (158)
7.88 (76.9) 4.02 (36.2) 2.18 (17.9) 1.32 (9.94) 0.80 (5.56)
38.9 (417) 19.8 (199) 10.0 (90.0) 5.21 (43.6) 2.71 (21.9)
299 (3195) 151 (1756) 76.8 (875)
表8-4. ADC2 (ADS1263) ENOB (Noise Free Bits) at TA = 25°C, VAVDD = 5 V, VAVSS = 0 V, VREF = 5 V
GAIN
DATA RATE FILTER
1
2
4
8
16
32
64
128
10 SPS
Sinc1
Sinc3
Sinc3
Sinc3
21.4 (18.8) 21.3 (18.8) 21.1 (18.6) 20.6 (18.2) 20.6 (18.1) 20.2 (17.8) 19.4 (17.0) 19.1 (16.7)
20.3 (17.5) 20.1 (17.3) 19.8 (17.2) 19.4 (16.7) 19.3 (16.5) 18.9 (16.2) 18.2 (15.6) 17.8 (15.0)
16.5 (12.5) 16.5 (12.5) 16.4 (12.7) 16.2 (12.8) 16.2 (12.6) 16.2 (13.0) 16.1 (13.0) 15.9 (13.0)
14.0 (10.7) 14.0 (10.7) 14.0 (10.4) 13.8 (10.4) 13.8 (10.4) 13.8 (10.4) 13.7 (10.6) 13.7 (10.7)
100 SPS
400 SPS
800 SPS
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9 Detailed Description
9.1 Overview
The ADS1262 and ADS1263 are precision 32-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front end
(AFE) to simplify connection to sensors. A 32-bit ADC (ADC1) provides output data rates from 2.5 SPS to 38400
SPS for flexibility in resolution and data rates over a wide range of applications. The ADC low noise and low drift
architecture make these devices suitable for precise digitization of low-level transducers, such as load cell
bridges and temperature sensors. The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2).
The ADS1262 and the ADS1263 incorporate several functions that provide increased utility. The key integrated
functions include:
• Low-drift voltage reference
• Dual, matched, sensor-excitation current sources (IDAC)
• Input-level-shift voltage
• Eight GPIOs
• Dual-sensor, bias current sources
• Low-noise, CMOS PGA with integrated signal fault detection
• Internal test signal source (TDAC)
• Temperature sensor
• Internal oscillator
• Three sets of buffered external reference inputs with low reference voltage alarm
As shown in the Functional Block Diagram, these devices feature 11 analog inputs that are configurable as either
ten single-ended inputs, five differential inputs, or any combination, to either ADC1 or ADC2. Many of the analog
inputs are multifunction as programmed by the user. The analog inputs can be programmed to the following
extended functions:
• Three external reference inputs: pins AIN0, AIN1, AIN2, AIN3, AIN4 and AIN5
• Two sensor excitation current source: all analog input pins
• Level shift (VBIAS): AINCOM pin
• Eight GPIO: pins AIN3, AIN4, AIN5, AIN6, AIN7, AIN8, AIN9, AINCOM
• Sensor break current source: all analog input pins
• Two test signal output: pins AIN6, AIN7
Following the input multiplexer (mux), ADC1 features a high-impedance, CMOS, programmable gain amplifier
(PGA). The PGA provides very low voltage and current noise, enabling direct connection to low-level
transducers, and in many cases, eliminating the need for an external amplifier. The PGA gain is programmable
from 1 V/V to 32 V/V in binary steps. The PGA can be bypassed to allow the input range to extend below
ground. The PGA has voltage overrange monitors to improve the integrity of the conversion result. The PGA
overrange alarm is latched during the conversion phase and appended to the conversion data. The
programmable sensor bias uses a test current to help detect a failed sensor or sensor connection.
An inherently stable delta-sigma modulator measures the ratio of the input voltage to the reference voltage to
provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to three external
reference inputs. The external reference inputs are continuously monitored for low (or missing) voltage. The
reference alarm status is latched during the conversion phase and appended to the conversion data. The
REFOUT pin is the buffered 2.5-V internal voltage reference output.
Dual excitation current sources (IDAC) provide bias to resistance sensors (such as 3-wire RTD). The ADC
integrates several system monitors for readback, such as temperature sensor and supply monitor. The ADC
features an internal test signal voltage (TDAC) that is used to verify the ADC operation across all gains. The
TDAC has two outputs to provide test voltages for single-ended and differential input configurations. Eight GPIO
ports are available on the analog input pins.
The digital filter provides two functional modes, sinc and FIR, allowing optimization of settling time and line-cycle
rejection. The sinx/x (sinc) filter is programmable to sinc orders one through four to tradeoff filter settling time
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and 50-Hz and 60-Hz line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle
settled data with 50-Hz and 60-Hz line cycle rejection at data rates up to 20 SPS.
The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2) featuring buffered PGA inputs, gains from 1
V/V to 128 V/V, and data rates up to 800 SPS. All analog inputs and reference inputs are available to ADC2.
ADC2 can be used to provide redundant measurements or system measurements such as sensor temperature
compensation and thermocouple cold junction compensation (CJC). The ADS1263 is pin and functionally
compatible to the ADS1262.
The SPI™-compatible serial interface is used to read the conversion data and also to configure and control the
ADC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The conversion data are
provided with a CRC code for improved data integrity. The dual function DOUT/DRDY output indicates when
conversion data are ready and also provides the data output. The serial interface can be implemented with as
little as three connections by tying CS low.
The ADC has three clock options: internal oscillator, external crystal, and external clock. The ADC detects the
clock mode automatically. The nominal clock frequency is 7.3728 MHz.
ADC conversions are started by a control pin or by commands. The ADC can be programmed to free-run mode
or perform one-shot conversions. The DRDY and DOUT/DRDY pins are driven low when the conversion data
are ready. The RESET/PWDN digital input resets the ADC when momentarily pulsed low, and when held low,
enables the ADC power-down mode.
The ADC operates with bipolar (± 2.5 V) supplies, or with a single 5-V supply. For single-supply operation, use
the internal level-shift voltage to level-shift isolated (floating) sensors. The digital power-supply range is 2.7 V to
5.25 V. The BYPASS pin is the subregulator output (2 V) that is used for internal digital supply.
9.2 Functional Block Diagram
AVSS
AVDD
CAPP
CAPN
BYPASS
DVDD
Ref
Mux
2V Digital
Supply
2.5 V Ref
LDO
ADC1
REFOUT
START
RESET/PWDN
DRDY
Ref
Mux
ADC2
Control
Low Ref
Alarm
Dual
Sensor
Excitation
AIN0
AIN1
Buf
Input
Mux
AIN2
ADC1
AIN3
32-bit
ADC1
Sensor
Bias
Digital
Filter
CS
AIN4
PGA
Serial
Interface
AIN5
SCLK
AIN6
DOUT/DRDY
Signal
Level
Alarm
AIN7
GPIO
DIN
AIN8
8
AIN9
Input
Mux
AINCOM
ADC2
Power Supplies
ADS1263 only
Buf
Internal
Oscillator
Level Shift
24-bit
ADC2
Digital
Filter
Sensor
Bias
PGA
XTAL2
Temp Sensor
Clock
Mux
XTAL1/CLKIN
Test DAC
DGND
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9.3 Feature Description
9.3.1 Multifunction Analog Inputs
The ADS1262 and ADS1263 have 11 multifunction analog inputs configurable in a variety of extended functions.
图 9-1 shows the internal analog signal routing to the circuit blocks. 表 9-1 summarizes the input pin functions.
The devices have two cross-point multiplexers; one multiplexer for ADC1, and one multiplexer for ADC2. The
multiplexers select any analog input for the positive PGA input and any input for the negative PGA input. The
ADCs are also configurable for a number of internal monitor functions. The internal monitors are temperature
sensor, TDAC test voltage, analog power-supply voltage, and digital power-supply voltage. The dual excitation-
current sources (IDAC1 and IDAC2) are independently connected to any analog input pin. Eight analog inputs
are configurable as GPIO. The GPIOs are programmable as inputs or outputs, and are referenced to the analog
power-supply voltages (VAVDD and VAVSS). The level-shift function (VBIAS) is available on AINCOM and is used
to provide an input level-shift voltage for isolated sensors. The internal TDAC test voltage is available on output
pins AIN6 and AIN7. The ADC has two voltage-reference multiplexers; one reference multiplexer for ADC1, and
one reference multiplexer for ADC2. Through the reference multiplexers, select the internal reference, three
external reference sources, or the analog power-supply voltage (VAVDD –VAVSS).
6
AIN0-AIN5
VREFP
ADC1
INT REF
Reference
Mux
VREFN
Sensor
Excitation
Analog Supply
11
AIN0 - AINCOM
ADC1
Input
Mux
GPIO[7:0]
Test DAC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
VAINP
VAINN
TEMP Sensor
8
Analog Supply
Monitor
Digital Supply
Monitor
ADS1263 Only
AIN7
AIN8
AIN0 - AIN5
INT REF
VREFP_2
VREFN_2
ADC2
Reference
Mux
2.5 V Reference
AIN9
Analog Supply
AINCOM
VBIAS
Temperature
Sensor
AIN0 - AINCOM
Test DAC
2
ADC2
Input
Mux
VAINP_2
VAINN_2
TEMP Sensor
Test DAC
Analog Supply
Monitor
Digital Supply
Monitor
图9-1. Analog Input Routing Overview
表9-1. Analog Input Pin Functions
LEVEL
SHIFT
ADC1
INPUT
ADC2
PIN
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AINCOM
INPUT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ADC1 REF INPUT(1)
ADC2 REF INPUT
IDAC1 OUTPUT IDAC2 OUTPUT
GPIO
TDAC OUTPUT
OUTPUT
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
REFP1, REFN1
REFP1
REFN1
REFP2
REFN2
REFP3
REFN3
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
—
—
—
—
—
—
—
—
—
—
—
—
Yes
REFP1, REFN1
—
REFP2, REFN2
—
—
REFP2, REFN2
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
—
REFP3, REFN3
—
REFP3, REFN3
—
TDACP
TDACN
—
—
—
—
—
—
—
—
—
—
—
—
(1) The reference voltage of ADC1 can be either polarity and reversed by programming.
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9.3.2 Analog Input Description
As shown in 图9-2, the analog inputs of the device consist of ESD protection diodes, an ADC1 and ADC2 cross-
point input multiplexer, the sensor bias circuit, and individual PGAs for each ADC. The ADC has 11 external
inputs, four internal monitor signals, and one no-connection (float). Note that in figures throughout this
document, italic text shows the associated register and register settings.
AVDD
AIN0
AIN1
0000
0001
0010
0011
AIN2
AIN3
AIN4
AIN5
ADC1 Positive Multiplexer
MUXP[3:0] bits 7:4 of INPMUX
(register address = 06h)
0100
0101
0110
0111
1000
1001
1010
AIN6
AIN7
ADC2 Positive Multiplexer
MUXP2[3:0] bits 7:4 ADC2MUX
(register address = 16h)
AIN8
ESD Diodes
AIN9
AINCOM
1011
1100
1101
TEMP Sensor P
Analog Supply Mon P
Digital Supply Mon P
TDAC P
AIN0
AIN1
1110
1111
VAINP1
AIN2
Float
Sensor
PGA1
Bias
VAINN1
AIN3
AIN4
AIN5
AIN6
VAINP2
AIN7
Sensor
PGA2
Bias
AIN8
0000
0001
0010
0011
AIN0
AIN1
VAINN2
AIN9
AINCOM
AIN2
AIN3
AIN4
AIN5
(ADS1263)
0100
0101
0110
ADC1 Negative Multiplexer
AIN6
AIN7
MUXN[3:0] bits 3:0 of INPMUX
(register address = 06h)
ESD Diodes
0111
1000
1001
1010
1011
1100
AIN8
AIN9
ADC2 Negative Multiplexer
AINCOM
MUXN2[3:0] bits 3:0 of ADC2MUX
(register address = 16h)
TEMP Sensor N
Analog Supply Mon N
Digital Supply Mon N
TDAC N
1101
1110
1111
Float
AVSS
图9-2. ADC1 and ADC2 Input Block Diagram
9.3.2.1 ESD Diode
The analog inputs have internal ESD diodes that are connected to the analog supplies (AVDD and AVSS). The
function of the diodes is to protect the ADC inputs from ESD events. If the input signal exceeds VAVDD by more
than 0.3 V or goes below VAVSS by more than –0.3 V, the diodes may conduct. When the diodes conduct, input
current flows into the analog inputs through the AVDD or AVSS pins. If an input overvoltage is possible, limit the
input current to less than |±10 mA|. In many applications, a resistor in series with the input is sufficient to limit the
current. Depending on the application requirements, be aware of the thermal noise of the current limit resistor.
9.3.2.2 Input Multiplexer
Use the dual, cross-point input multiplexers to select from one of the 11 external inputs, one of the four internal
monitors, and a floating connection, in any combination, to either ADC. One input is selected by the positive
multiplexer, and one input is selected by the negative multiplexer. The ADC1 positive and negative multiplexers
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are programmed by bits MUXP[3:0] and bits MUXN[3:0] in the INPMUX register (address = 06h). The ADC2
positive and negative multiplexers have identical functionality and are programmed by bits MUXP2[3:0] bits and
bits MUXN2[3:0] in the ADC2MUX register (address = 16h).
9.3.3 Sensor Bias
The ADC incorporates a sensor bias current source that can be used to apply a small test current to diagnose
broken sensor leads or problems existing in the sensor. 图9-3 shows the sensor bias block diagram. The sensor
bias circuit consists of programmable current sources and bias resistors. The sensor bias circuit connects to the
outputs of either the ADC1 or ADC2 multiplexers. Program the sensor bias to either pull-up or pull-down mode.
In pull-up mode, the current flows into the positive input and flows out of the negative input. In pull-down mode,
the polarities are reversed. Configure the sensor bias either to a 10-MΩ bias resistor, or to current with
magnitudes of ±0.5, ±2, ±10, ±50, or ±200 µA.
AVDD
AVSS
SBMAG[2:0] bits 2:0 of MODE1
(register address = 04h)
10 MΩ
10 MΩ
000 = off
001 = 0.5 uA
010 = 2 uA
011 = 10 uA
100 = 50 uA
101 = 200 uA
110 = 10 MΩ (shown)
SBPOL bit 3 of MODE1
(register address = 04h)
0 = Pull-up mode (shown)
1 = Pull-down Mode
0 = ADC1 Connection (shown)
1 = ADC2 Connection
SBADC bit 4 MODE1
(register address = 04h)
VAINP1
ADC1
PGA1
INPUT
MUX
VAINN1
VAINP2
ADC2
INPUT
MUX
PGA2
VAINN2
图9-3. Sensor Bias Block Diagram
In pull-up mode, an open sensor results in the positive input pulled to VAVDD, and the negative input pulled to
VAVSS. An open sensor in pull-up mode results in a positive full-scale reading. A full-scale reading can also be an
indication of sensor overload or that the reference voltage is lower than expected. The sensor bias can remain
on while actively converting, or pulsed on periodically to test the sensor. When pulsed on, allow time for settling
because external capacitance loads the sensor bias when first enabled. Be aware of offset error as a result of
sensor bias current flowing through the multiplexer switch resistance.
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9.3.4 Temperature Sensor
The ADC incorporates an integrated temperature sensor. The temperature sensor is comprised of two internal
diodes with one diode having 16 times the current density of the other, as shown in 图 9-4. The difference in
current density of the diodes yields a differential output voltage that is proportional to absolute temperature.
Measure the temperature sensor voltage with either ADC1 or ADC2. For ADC1 measurement, set the INPMUX
register (address 06h) to BBh. For ADC2 measurement, set the ADC2MUX register (address 16h) to BBh. 方程
式9 shows how to convert the temperature sensor reading to degrees Celcius (°C):
Temperature (°C) = [(Temperature Reading (µV) –122,400) / 420 µV/°C] + 25°C
(9)
where
• Temperature reading units are in µV
Before temperature sensor measurement, enable the PGA, set gain = 1, disable chop mode, and make sure the
internal voltage reference is powered on. As a result of the low package-to-PCB thermal resistance, the internal
device temperature closely tracks the PCB temperature. Note that ADC self-heating results in an increase of
0.7°C relative to the temperature of the surrounding PCB.
AVDD
ADC1 MUX P
1x
2x
TEMP Sensor P
TEMP Sensor N
ADC1 MUX N
ADC2 MUX P
ADC2 MUX N
1x
8x
AVSS
图9-4. Temperature Sensor
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9.3.5 Power-Supply Monitor
To internally monitor the ADC power supplies, use either ADC1 or ADC2. As shown in 图 9-5, the power supply
voltages are divided by a resistor network to reduce the voltages within the ADC input range. The reduced
power-supply voltage is routed to the ADC input multiplexers. The analog (VANLMON) and digital (VDIGMON) power
supply readings are scaled by 方程式10 and 方程式11, respectively:
VANLMON = (VAVDD –VAVSS) / 4
VDIGMON = (VDVDD –VDGND) / 4
(10)
(11)
Measure the supply monitor readings using either the internal or an external reference. For an external
reference, the minimum reference voltage is 1.5 V.
Before measurement, enable the PGA, set gain = 1, and disable chop mode.
For analog supply monitor ADC1 measurement, set the INPMUX register (address 06h) to CCh.
For digital supply monitor ADC1 measurement, set the INPMUX register to DDh.
For analog supply monitor ADC2 measurement, set the ADC2MUX register (address 16h) to CCh.
For digital supply monitor ADC2 measurement, set the ADC2MUX register to DDh.
Analog Supply Monitor
Digital Supply Monitor
AVDD
DVDD
ADC1 MUX P
ADC1 MUX N
ADC1 MUX P
ADC1 MUX N
1.5 R
2.5 R
VANLMON_ P
VDIGMON_ P
R
R
VANLMON_ N
VDIGMON_ N
ADC2 MUX P
ADC2 MUX N
ADC2 MUX P
ADC2 MUX N
0.5 R
1.5 R
AVSS
DGND
图9-5. Power-Supply Monitors
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9.3.6 PGA
The ADC1 PGA is a low-noise, programmable gain, CMOS differential-input, differential-output amplifier. The
PGA extends the ADC dynamic range of sensors with low input-signal levels. The PGA provides gains of 1, 2, 4,
8 ,16, and 32. Bypass the PGA to extend the analog input range to below ground (if the AVSS pin is grounded).
图 9-6 shows the PGA block diagram. The PGA consists of two chopper-stabilized amplifiers (A1 and A2), and a
resistor network that is programmed to set the PGA gain. The PGA input is equipped with a high-frequency,
electromagnetic-interference (EMI) input filter consisting of two 350-Ω input resistors, and several filter
capacitors, as shown in the figure. Bypass the PGA to directly connect the inputs to the ADC. The PGA output is
monitored by an overrange voltage monitor. The voltage monitor triggers an alarm when the absolute or
differential PGA output voltage exceeds the linear range of operation. Pins CAPP and CAPN are the PGA
positive and negative outputs, respectively. Connect a 4.7-nF (C0G) capacitor as shown in the figure. The
capacitor provides an analog antialias filter, as well as the deglitch filter for the modulator sample pulses. Place
the capacitor close to the pins using short, direct traces. Avoid running clock traces or other digital traces close
to the pins.
0 = PGA active (shown)
1 = PGA bypass
BYPASS bit 7 of MODE2
(register address = 05h)
280 Ω
350 Ω
VAINP
CAPP
+
A1
œ
8 pF
12 pF
GAIN[2:0] bits 6:4 of MODE2
(register address = 05h)
PGA1
Over-range
Detection
000: 1
001: 2
010: 4
011: 8
100: 16
101: 32
4.7 nF
C0G
ADC1
12 pF
12 pF
œ
A2
350 Ω
280 Ω
VAINN
+
CAPN
8 pF
图9-6. ADC1 PGA Block Diagram
The ADC1 full-scale voltage range is determined by the reference voltage and the PGA gain. 表 9-2 shows the
full-scale voltage range verses gain for reference voltage = 2.5 V. The full-scale voltage range scales with the
reference voltage and is increased or decreased by changing the reference voltage.
表9-2. ADC1 Full-Scale Voltage Range
GAIN[2:0] BITS OF REGISTER
MODE2
GAIN (V/V)
FULL SCALE RANGE (V)(1)
±2.500 V
000
1
2
001
±1.250 V
010
4
±0.625 V
011
8
±0.312 V
100
16
32
±0.156 V
101
±0.078 V
(1) VREF = 2.5 V. The full-scale input range is proportional to VREF
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As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded.
The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA
output. The specified minimum and maximum absolute input voltages (VINP and VINN) depend on the PGA gain,
the input differential voltage (VIN), and the tolerance of the analog power-supply voltages (VAVDD and VAVSS).
The absolute positive and negative input voltages must be within the specified range, as shown in 方程式12:
VAVSS + 0.3 + |VIN| · (Gain –1) / 2 · < VINP and VINN < VAVDD –0.3 –|VIN| · (Gain –1) / 2
(12)
where
• VINP, VINN = absolute input voltage
• VIN = differential input voltage = VINP - VINN
The relationship between the PGA input to the PGA output is shown graphically in 图 9-7. The PGA output
voltages (VOUTP, VOUTN) depend on the PGA gain and the input voltage magnitudes. For linear operation, the
PGA output voltages must not exceed VAVDD – 0.3 or VAVSS + 0.3. Note the diagram depicts a positive
differential input voltage that results in a positive differential output voltage.
PGA Input
PGA Output
VAVDD
VAVDD œ 0.3 V
VOUTP = VINP + VIN ‡ (Gain œ 1) / 2
VINP
VIN = VINP ‡ VINN
VINN
VOUTN = VINN œ VIN ‡ (Gain œ 1) / 2
VAVSS + 0.3 V
VAVSS
图9-7. PGA Input/Output Range
If the PGA is bypassed, the ADC absolute input voltage range extends beyond the VAVDD and VAVSS power
supplies allowing input voltages at or below ground. The absolute input voltage range when the PGA is
bypassed is shown in 方程式13:
V
AVSS –0.1 < VINP and VINN < VAVDD + 0.1
(13)
9.3.7 PGA Voltage Overrange Monitors
ADC1 incorporates two PGA output-voltage monitors. The monitors trigger an alarm if the PGA output is driven
into overrange. The corresponding bits are set (= 1) in the data output status byte when an alarm is triggered.
The PGA output voltage is monitored in two ways:
1) Differential: If the PGA differential output voltage exceeds either +105% or –105% FSR.
2) Absolute: If either PGA absolute output voltage is higher than VAVDD –0.2 V or lower than VAVSS + 0.2 V.
The alarms automatically reset when the PGA is no longer in voltage overload. The monitors are fast-
responding, analog, voltage-level comparators. Therefore, these monitors detect short-duration voltage
overrange events that are not necessarily evident in the output as clipped codes because of averaging of the
digital filter that may span one or more conversion cycles. Use the monitor function to detect certain type of
faults (such as signal overranges, incorrect gain settings, sensor faults, input miswiring, and so on) without the
need to change input configuration or interrupt readings.
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9.3.7.1 PGA Differential Output Monitor
ADC1 incorporates a differential PGA output voltage monitor. This voltage monitor triggers an alarm when the
magnitude of the differential PGA output voltage is more positive than +105% or more negative than –105% of
full scale, but only during a conversion cycle. The alarm event, corresponding to the conversion cycle when the
alarm occurred, is set in the status byte (PGAD_ALM). For the next conversion, the alarm resets. If the
magnitude of differential output voltage is within the range of ±105% of full-scale range, the alarm remains reset.
The PGA differential monitor block diagram is shown in 图9-8.
Data Bytes
VOUTP
C
A D
Digital
Filter
ADC
DATA 3
DATA 4
STATUS
DATA 2
CRC/CHK
DATA 1
PGA
VOUTN
VREF Comparators
PGAD_ALM
Bit 1 of STATUS byte
+105% VREF
œ
+
Latch
+
S
Q
Q
œ
œ
R
PGA Output
difference amplifier
-105% VREF
Conversion
Start Reset
+
图9-8. PGA Differential Overload Monitor
图9-9 shows an example of the differential overrange monitor event.
+ 105%
- 105%
Alarms latched during
conversion cycle
Conversions (DRDY)
PGAD_ALM bit
图9-9. PGA Differential Alarm
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9.3.7.2 PGA Absolute Output-Voltage Monitor
ADC1 contains an integrated a PGA absolute output-voltage monitor. If the absolute level of the PGA positive or
negative output exceeds VAVDD – 0.2 V, the PGA high alarm triggers (PGAH_ALM). If the absolute level of the
PGA positive or negative output voltage is less than VAVSS + 0.2 V, the PGA low alarm triggers (PGAL_ALM).
The alarms are set in the status byte corresponding to the conversion cycle when the alarms occurred. For the
next conversion cycle, the alarms reset. If the magnitude of PGA output voltages remains within the range
(VAVDD – 0.2 V and VAVSS + 0.2 V), the alarms remain reset. The PGA absolute output-voltage monitor block
diagram is shown in 图9-10.
Data Bytes
VOUTP
VOUTN
C
A D
Digital
Filter
ADC
DATA 3
DATA 4
STATUS
DATA 2
CRC/CHK
DATA 1
PGA
VAVDD œ 0.2 V
œ
PGAH_ALM
Bit 2 of STATUS byte
+
S
R
Q
Q
Latch
œ
+
Supply Rail
Comparators
œ
PGAL_ALM
Bit 3 of STATUS byte
+
S
R
Q
Q
Latch
œ
+
VAVSS + 0.2 V
Conversion
Start Reset
图9-10. PGA Absolute Output-Voltage Monitor
图9-11 shows an example of the PGA absolute output-voltage monitor overrange event.
VAVDD - 0.2
VAVSS + 0.2
Alarms latched during
conversion cycle
Conversions (DRDY)
PGAH_ALM bit
PGAL_ALM bit
图9-11. PGA Absolute Alarm
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9.3.8 ADC Reference Voltage
These devices require a reference voltage for operation. Both ADCs default to the same internal reference,
however, the reference voltage of ADC1 is independent of the ADC2 reference voltage. The reference voltage is
provided internally by the internal 2.5-V reference, or externally, by one of the three external reference inputs.
The specified external reference voltage range is 0.9 V to 5 V. The reference voltage is defined as VREF = VREFP
– VREFN, where VREFP and VREFN are the absolute positive and absolute negative reference voltages,
respectively. The polarity of the reference voltage internal to the ADC must be always positive. The magnitude of
the reference voltage together with the PGA gain establishes the ADC full-scale differential input range as
defined by VIN = ±VREF / gain. 图 9-12 shows the block diagram of the ADC1 reference multiplexer. Use the
reference multiplexer to select the internal reference, one of three external reference inputs, or the analog power
supply.
INTREF bit 0 of POWER 0 = reference off
(register address = 01h) 1 = reference on
RMUXP[2:0] bits 5:3 of REFMUX
(register address = 0Fh)
+2.5 V
Reference
AVDD
REFREV bit 7 of MODE0
(register address = 03h)
REFOUT
000
001
010
AIN0
AIN2
AIN4
REF_ALM bit of status byte
(bit 4)
0 = normal
1 = reverse
Low Reference
Monitor
REF_MUXP
(A)
1 mF
011
100
0 = no alarm
1 = alarm
+0.4 V
VVREFP
+
+
S Q
œ
VVREFN
œ
Q
R
000
001
010
011
AIN1
AIN3
Start Conversion Reset
REF_MUXN
AIN5
100
ADC1
AVSS
RMUXN[2:0] bits 2:0 of REFMUX
(register address = 0Fh)
A. The internal reference requires a 1-µF capacitor connected to pins REFOUT and AVSS.
图9-12. ADC1 Reference Multiplexer Block Diagram
The ADC1 reference multiplexer consists of a positive multiplexer and a negative multiplexer. The positive and
negative multiplexers are programmed by the RMUXP[2:0] and RMUXN[2:0] bits, respectively, of the REFMUX
register. The positive reference input is either internal (2.5 V), external (pins AIN0, AIN2, AIN4), or the analog
power-supply voltage (VAVDD). The negative reference input is either internal (2.5 V), external (pins AIN1, AIN3,
AIN5), or the analog power-supply voltage (VAVSS). A reference polarity-reversal switch changes the reference
polarity from negative to positive. The polarity switch allows either positive or negative external reference
polarity. Set the reversal switch to the normal position (REFREV = 0) when using the internal reference or analog
power supplies.
The ADC also contains and integrated low-reference voltage monitor. This monitor provides continuous detection
of a low or missing reference during the conversion cycle. The low reference alarm is appended to the data
output status byte (REF_ALM, bit 4 of the status byte).
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9.3.8.1 Internal Reference
The ADC incorporates an integrated, precision, 2.5-V reference featuring very low drift. The internal reference is
enabled by setting INTREF equal to 1 (default is on). To select the internal reference for use with ADC1, set the
RMUXP and RMUXN bits of register REFMUX to 0h. The REFOUT pin provides a buffered reference output
voltage. The negative reference (return) is the AVSS pin, as shown in 图 9-12. Be careful when laying out the
REFOUT return to the AVSS pin. Connect a 1-uF capacitor from the REFOUT pin to the AVSS pin. The
capacitor can be increased up to 10 μF (maximum) to decrease the reference noise, but results in increased
reference start-up time. The capacitor is not required if the internal reference is not used. The internal reference
must be powered if using the IDACs or the internal temperature sensor. After internal reference start-up, the
reference requires start-up time before beginning the first conversion; see 图7-33.
9.3.8.2 External Reference
The ADC provides three external reference inputs. The reference inputs are differential with independent positive
and negative inputs. The reference inputs are the analog pins, AIN0 to AIN5. Typically, the positive reference is
applied to pin AIN0, AIN2, or AIN4, and the negative reference is applied to pin AIN1, AIN2, or AIN3. The
reference polarity can be negative, but the ADC requires a positive voltage reference. In this case, reverse the
polarity using the internal polarity-reversal switch (ADC1 reference only). The reference polarity-reversal switch
changes the reference polarity from negative to positive, and is controlled by REFREV (bit 7 of MODE0).
The reference inputs are high impedance. A reference input current flowing through a reference-voltage source
impedance leads to possible loading errors (see 图 7-34). To reduce the input current, use an external reference
buffer; however, in most applications, an external reference buffer is not necessary.
Connect a 100-nF bypass capacitor across the external reference input pins. Follow the specified absolute and
differential reference voltage requirements.
9.3.8.3 Power-Supply Reference
A third option for ADC reference is the internal analog power supply. However, an increase of linearity error
results with this connection, and therefore, use this option only for less-critical applications, such as ADC self-
diagnostics.
For critical applications, do not use the power-supply reference option. For applications that use the power-
supply voltage as the reference voltage, connect the power-supply voltage to the external reference inputs, and
select the appropriate external reference bits in the REFMUX register. For example, to measure a 6-wire load-
cell, connect the bridge excitation voltages to the external reference inputs, and select the appropriate REFMUX
bits.
9.3.8.4 Low-Reference Monitor
ADC1 incorporates a low-reference monitor to detect a low or missing reference. If the differential reference
voltage (VREF = VREFP – VREFN) falls below 0.4 V (typical), the low reference alarm triggers (REF_ALM). The
low-reference monitor sets the corresponding alarm bit in the conversion data status byte. The alarm resets at
the start of each new conversion. Use the low-reference monitor to detect a missing or failed reference voltage
connection. Connect a 100-kΩ resistor across the reference inputs to provide the necessary bias. If either
reference input is missing or unconnected, this external resistor biases the reference inputs to each other. The
low-reference monitor is a fast-responding analog comparator; therefore, transients in the reference voltage may
trigger the alarm.
9.3.9 ADC1 Modulator
The ADC1 modulator is an inherently stable, fourth-order, 2 + 2 pipelined ΔΣ modulator. The modulator
samples the analog input voltage at a high sample rate (fMOD = fCLK / 8 = 921.6 kHz) and converts the analog
input to a ones density bit stream. The digital filter receives the ones density bit stream output, and then filters
and decimates the data to yield the final conversion result.
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9.3.10 Digital Filter
The digital filter of ADC1 receives the modulator output data and produces a high-resolution conversion result.
The digital filter low-pass filters and decimates the modulator data (rate reduction), yielding the final data output.
By adjusting the type of filtering, tradeoffs are made between resolution, data rate, line cycle rejection, and
conversion latency.
The digital filter has two selectable modes: sin (x) / x (sinc) mode and finite impulse response (FIR) mode (see
图 9-13). The sinc mode provides data rates of 2.5 SPS though 38400 SPS with selectable sinc orders of 1
through 5. The FIR filter provides simultaneous rejection of 50-Hz and 60-Hz power-line frequencies with data
rates 2.5 SPS through 20 SPS with single-cycle settled conversions.
fCLK: 7.3728 MHz
38400 SPS
19200 SPS
14400 SPS
fCLK/8
fMOD: 921.6 kHz
14400 SPS
921.6 kHz
2.5 SPS...7200 SPS
FIR Filter Section
1st Stage
Sinc5 Filter
2nd Stage
SincN Filter
Modulator
Filter Output
Decimation A
(24, 48, 64)
Decimation B
(2...5760)
20 SPS
600 SPS
FIR
Averager
10 SPS
5 SPS
2.5 SPS
Decimation
(30)
Average
(2,4,8)
DR[3:0] bits 3:0 of MODE2
(register address = 05h)
FILTER[2:0] bits 7:5 of MODE1
(register address = 04h)
000 = sinc1
001 = sinc2
010 = sinc3
011 = sinc4
100 = FIR
0000 = 2.5 SPS
0001 = 5 SPS
1000 = 400 SPS
1001 = 1200 SPS
1010 = 2400 SPS
1011 = 4800 SPS
1100 = 7200 SPS
1101 = 14400 SPS
1110 = 19200 SPS
1111 = 38400 SPS
0010 = 10 SPS
0011 = 16.6 SPS
0100 = 20 SPS
0101 = 50 SPS
0110 = 60 SPS
0111 = 100 SPS
图9-13. Digital Filter Block Diagram
9.3.10.1 Sinc Filter Mode
The sinc filter consists of two stages: a variable-decimation, fixed-order sinc5 filter, followed by a variable-
decimation, variable-order sinc filter. The first-stage filter is sinc5. The sinc5 stage filters and down-samples the
modulator data (fCLK / 8 = 921.6 kHz) to 38400 SPS, 19200 SPS, and 14400 SPS by decimating to 24, 48, and
64, respectively. These data rates bypass the second filter stage and as a result have a sinc5 frequency
response profile. The second filter stage receives the data from the first stage at 14400 SPS. The second stage
reduces the data rate to produce output data of 7200 SPS to 2.5 SPS. The second stage is a variable-order sinc
filter that is programmable.
The combined decimation ratio of the first and second stages determine the output data rate as follows: data
rate = 921.6 kHz / (A · B). The filter order of the second stage affects the 50-Hz and 60-Hz rejection together
with conversion latency. The high-order sinc filter yields the widest 50-Hz and 60-Hz response null widths, but
correspondingly increases the conversion latency. The sinc order is programmed by the FILTER[2:0] bits of
register MODE1. 表 9-3 lists the decimation ratio corresponding to the first and second filter stages (A and B,
respectively) for each data rate. The data rate is programmed by the DR[3:0] bits of register MODE2.
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表9-3. Sinc Filter Mode Data Rates and Decimation Ratio
DATA RATE
(SPS)(1)
DR[3:0] BITS OF
REGISTER MODE2
FIRST-STAGE
DECIMATION RATIO A
SECOND-STAGE
DECIMATION RATIO B
2.5
5
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
64
64
64
64
64
64
64
64
64
64
64
64
64
64
48
24
5760
2880
1440
864
720
288
240
144
36
10
16.6
20
50
60
100
400
1200
2400
4800
7200
14400
19200
38400
12
6
3
2
1
1
1
(1) fCLK = 7.3728 MHz. Data rate scales with fCLK
9.3.10.1.1 Sinc Filter Frequency Response
The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC. The frequency
response of data rates 14400 SPS, 19200 SPS and 38400 SPS is that of the first filter stage. The frequency
response of data rates 2.5 SPS ranging to 7200 SPS is the product of the first and second stage individual
frequency responses. The overall filter response is given in 方程式14:
5
N
»
…
ÿ
»
…
ÿ
8ŒfA
fCLK
512Œf B
fCLK
sin
sin
Ÿ
Ÿ
⁄
8Œf
fCLK
⁄
H( = Hsinc
5
(
f
)
ì HsincN
(
f
)
=
ì
f
)
»
…
ÿ
»
…
ÿ
512Œf
fCLK
Aìsin
Bìsin
Ÿ
⁄
Ÿ
⁄
(14)
where
• f = signal frequency
• fCLK = ADC clock frequency
• A = First-stage decimation ratio (see 表9-3)
• B = Second-stage decimation ratio (see 表9-3)
• N = Second-stage filter order where N = 1 (sinc1), 2 (sinc2), 3 (sinc3), or 4 (sinc4)
The digital filter attenuates out-of-band noise that is present in the signal, and noise within the PGA and ADC
modulator. Adjusting the filter by changing the decimation ratio and sinc order changes the filter bandwidth.
Tradeoffs are made between signal bandwidth, noise, and filter latency.
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As shown in 图 9-14 and 图 9-15, the first-stage sinc5 filter has frequency response nulls occurring at the data
rate (fMOD / A) and at data rate multiples. At the null frequencies, the filter has zero gain.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (kHz)
D002
D001
图9-15. Sinc Frequency Response
图9-14. Sinc Frequency Response
(14400 SPS)
(38400 SPS)
The second stage superimposes new nulls in the frequency response over the nulls produced by the first stage.
The first of the superimposed frequency response nulls occur at the output data rate, followed by nulls occurring
at data rate multiples.
图 9-16 illustrates the frequency response of data rate 2400 SPS produced by the combined filter stages. This
data rate has five equally-spaced nulls between the larger nulls produced by the first stage. The frequency
response is also characteristic of data rates 2.5 SPS to 7200 SPS that are also produced by the second-stage
filter. 图9-17 shows the frequency response nulls for 10 SPS.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
20 25
Frequency (kHz)
30
35
40
45
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (Hz)
D003
D004
图9-16. Sinc Frequency Response (2400 SPS)
图9-17. Sinc Frequency Response (10 SPS)
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图 9-18 and 图 9-19 illustrate the frequency response of data rates 50 SPS and 60 SPS. The frequency
response is plotted out to the 50-Hz 12th harmonic (10th harmonic for 60 Hz). The 50-Hz or 60-Hz fundamental
frequency and harmonics are suppressed by increasing the second-stage filter order, as shown in the figures.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (Hz)
0
60 120 180 240 300 360 420 480 540 600
Frequency (Hz)
D005
D006
图9-18. Sinc Frequency Response (50 SPS)
图9-19. Sinc Frequency Response (60 SPS)
图9-20 and 图9-21 plot the detailed frequency response of 50-SPS and 60-SPS data rates of different sinc-filter
orders. Note that the high-order sinc filter increases the width of the null and improves line cycle rejection. The
high-order filter decreases the sensitivity of the ratio tolerance between the ADC clock frequency and the line
frequency that can otherwise degrade line cycle rejection. As shown in the plots, the best 50-Hz or 60-Hz
rejection is provided by the sinc4 order, but has longer filter latency compared to the sinc1 order.
0
-20
0
-20
sinc1
sinc2
sinc3
sinc4
sinc1
sinc2
sinc3
sinc4
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
45
46
47
48
49
Frequency (Hz)
50
51
52
53
54
55
55
56
57
58
59
Frequency (Hz)
60
61
62
63
64
65
D009
D010
图9-20. Sinc Frequency Response Zoom
图9-21. Sinc Frequency Response Zoom
(50 SPS)
(60 SPS)
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The overall sinc filter frequency has a low-pass response that rolls off high-frequency components in the signal.
The signal bandwidth depends on the output data rate and the order of the sinc filter. Note the overall system
bandwidth is the combination of the digital filter, the antialias filter, and external filter components. 表9-4 lists the
–3-dB filter bandwidth of the sinc filter. Note the bandwidth reduction of the higher-order sinc filters.
表9-4. Sinc Filter Bandwidth
-3-dB BANDWIDTH (Hz)
DATA RATE (SPS)
SINC1
1.10
2.23
4.43
7.38
8.85
22.1
26.6
44.3
177
SINC2
0.80
1.60
3.20
5.33
6.38
16.0
19.1
31.9
128
381
751
1421
1972
—
SINC3
0.65
1.33
2.62
4.37
5.25
13.1
15.7
26.2
105
314
623
1214
1750
—
SINC4
0.58
1.15
2.28
3.80
4.63
11.4
13.7
22.8
91.0
273
544
1077
1590
—
SINC5
2.5
5
—
—
10
—
16.6
20
—
—
50
—
60
—
100
—
400
—
1200
2400
4800
7200
14400
19200
38400
525
—
1015
1798
2310
—
—
—
—
2940
3920
7740
—
—
—
—
—
—
—
—
9.3.10.2 FIR Filter
The finite impulse response (FIR) filter of ADC1 is a coefficient-based filter that provides simultaneous rejection
of 50-Hz and 60-Hz line cycle frequencies and harmonics. The FIR filter data rates are 2.5, 5, 10 and 20 SPS. All
of the FIR data rates settle within a single conversion cycle. As shown in 图 9-13, the FIR filter section receives
data from the second-stage sinc filter at 600 Hz. The FIR filter section decimates by 30 to yield the output data
rate of 20 SPS. A first-order averager (sinc1) with variable decimation provides the data rates of 10 SPS, 5 SPS,
and 2.5 SPS.
As shown in 图9-22 and 图9-23, the FIR filter frequency response has a series of response nulls close to 50 Hz
and 60 Hz. The response nulls repeat close to the 50-Hz and 60-Hz harmonics. The FIR frequency response
superimposes with the response of the 600-SPS pre-stage filter.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
40
45
50
55
Frequency (Hz)
60
65
70
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
D012
D011
图9-23. FIR Frequency Response Detail
图9-22. FIR Frequency Response (20 SPS)
(20 SPS)
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图 9-24 is the FIR filter response at 10 SPS. As a result of the sinc1 averager in the FIR filter block, new
frequency-response nulls are superimposed to the response in 图 9-22. The first of the added response nulls
occur at 10 Hz. Additional nulls occur at folded frequencies around 20-Hz multiples. These additional nulls are
seen at 10 Hz and 30 Hz.
0
-20
-40
-60
-80
-100
-120
-140
-160
0
30
60
90 120 150 180 210 240 270 300
Frequency (Hz)
D013
图9-24. FIR Frequency Response (10 SPS)
Similar to the response of the sinc filter, the overall FIR filter frequency has a low-pass response that rolls off
high frequencies of the signal. The response is such that the FIR filter limits the bandwidth of the input signal.
The FIR filter signal bandwidth depends on the output data rate. 表 9-5 lists the –3-dB filter bandwidth of the
FIR filter. The total system bandwidth is the combined individual responses of the digital filter, the ADC antialias
filter, and external filter components.
表9-5. FIR Filter Bandwidth
DATA RATE (SPS)
–3-dB BANDWIDTH (Hz)
2.5
5
1.2
2.4
4.7
13
10
20
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9.3.10.3 50-Hz and 60-Hz Line Cycle Rejection
If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50-Hz and
60-Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and may lead to
inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line coupled noise for
data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired
level of line cycle rejection. 表9-6 summarizes the ADC1 50-Hz and 60-Hz line-cycle rejection based on 2% and
6% ratio tolerance of power-line to ADC clock frequency. Best possible power line rejection is provided by the
high-order sinc filter and by using an accurate ADC clock.
表9-6. 50-Hz and 60-Hz Line Cycle Rejection
DIGITAL FILTER Response (dB)
DATA RATE (SPS)
FILTER TYPE
FIR
50 Hz ±2%
–113
–36
60 Hz ±2%
–99
50 Hz ±6%
–88
–40
–80
–120
–160
–77
–30
–60
–90
–120
–73
–25
–50
–75
–100
–24
–48
–72
–96
–66
–18
–36
–54
–72
–24
–48
–72
–96
–12
–24
–36
–48
60 Hz ±6%
–80
–37
–74
–111
–148
–76
–30
–60
–90
–120
–68
–25
–50
–75
–100
–21
–42
–63
–84
–66
–24
–48
–72
–96
–15
–30
–45
–60
–24
–48
–72
–96
2.5
2.5
2.5
2.5
2.5
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–37
–72
–74
–108
–144
–111
–34
–111
–148
–95
5
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
5
–68
–68
5
–102
–136
–111
–34
–102
–136
–94
5
10
10
10
10
10
16.6
16.6
16.6
16.6
20
20
20
20
20
50
50
50
50
60
60
60
60
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
FIR
–34
–68
–68
–102
–136
–34
–102
–136
–21
–68
–42
–102
–136
–95
–63
–84
–94
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
Sinc1
Sinc2
Sinc3
Sinc4
–18
–34
–36
–68
–54
–102
–136
–15
–72
–34
–68
–30
–102
–136
–13
–45
–60
–34
–27
–68
–40
–102
–136
–53
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9.3.11 Sensor-Excitation Current Sources (IDAC1 and IDAC2)
The ADS1262 and ADS1263 incorporate two, integrated, matched current sources (IDAC1, IDAC2). The current
sources provide excitation current to resistive temperature devices (RTDs), thermistors, diodes, and other
sensors that require constant current biasing. These devices also contain an internal IDAC multiplexer that
provides connection of IDAC1 or IDAC2 to one of the 11 analog pins (AIN0 to AINCOM). The IDACs can be
programmed over these current ranges: 50 μA, 100 μA, 250 μA, 500 μA, 750 μA, 1000 μA, 1500 μA, 2000
μA, 2500 μA, and 3000 μA. 图 9-25 details the IDAC connection. The IDAC switches shown in the diagram
are used in the IDAC rotation mode.
MUX1[3:0] bits 3:0 of IDACMUX
(register address = 0Dh)
IDAC Modes
CHOP[1:0] bits 5:4 of register MODE0
00: Normal (shown)
(register address = 03h)
01: Chop on (see Chop section)
10: IDAC rotation (automated)
11: Chop on and IDAC rotation
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0000
0001
0010
0011
VAVDD
IDAC1
MUX
MAG1[3:0] bits 3:0 of IDACMAG
(register address = 0Eh)
0100
0101
0110
0000: off
0001: 50 µA
IDAC1
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
0111
1000
1001
1010
AINCOM
1011
No Connection
AIN0
AIN1
AIN2
AIN3
0000
0001
0010
0011
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN4
VAVDD
IDAC2
MUX
AIN5
MAG2[3:0] bits 7:4 of IDACMAG
(register address = 0Eh)
AIN6
AIN7
0100
0101
0110
0111
1000
1001
1010
1011
0000: off
0001: 50 µA
AIN8
IDAC2
AIN9
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
AINCOM
AINCOM
No Connection
MUX2[3:0] bits 7:4 of IDACMUX
(register address = 0Dh)
图9-25. IDAC Block Diagram
The internal reference must be enabled for IDAC operation. Take care not to exceed the compliance voltage of
the IDACs. In other words, the voltage on the input pin must not exceed VAVDD – 1.1 V; otherwise, the specified
accuracy of the IDAC current is not met.
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The IDAC currents track the internal reference voltage. As a result of using the same reference voltage for
IDAC1 and IDAC2, the current sources are matched. Matched performance is important for applications such as
hardware compensated, 3-wire RTDs. IDAC to IDAC mismatch can be improved further by use of the IDAC
rotation mode. The rotation mode automatically swaps the IDAC1 and IDAC2 connections of alternate
conversions. The ADC averages the alternate conversions to eliminate IDAC mismatch. IDAC rotation can be
performed manually by the user (by alternating the IDAC pin connections) or by the IDAC automatic rotation
mode. The IDAC rotation sequence is shown as follows:
• Conversion 1: IDAC1, IDAC2 normal →first output result withheld
• Conversion 2: IDAC1, IDAC2 rotated positions →Output result 1 = (Conversion 1 + Conversion 2) / 2
• Conversion 3: IDAC1, IDAC2 normal →Output result 2 = (Conversion 3 + Conversion 2) / 2
• Conversion 4: IDAC1, IDAC2 rotated positions →Output result 3 = (Conversion 4 + Conversion 3) / 2
The sequence repeats for all succeeding conversions.
In rotation mode, the ADC provides a time delay to allow for settling after the IDAC pin connections are
alternated. Note IDAC switching transients may interact with external components that may require additional
time to settle. Additional settling time are provided by bits DELAY[3:0] in the MODE0 register. The total delay
time results in a reduction of the nominal data rate (see the Conversion Latency section). Nevertheless, the
existing frequency response nulls provided by the digital filter remain unchanged.
9.3.12 Level-Shift Voltage
The ADC integrates an optional level-shift voltage on the AINCOM pin. As shown in 图 9-26, the level-shift
voltage is the mid-voltage of the analog power supply. The level-shift voltage shifts floating sensors (that is,
sensors isolated from the ADC ground) to within the ADC specified input range. Thermocouple and 4-mA to 20-
mA transmitters (isolated supply) are examples of floating signals.
AVDD
INPUT
MUX
AINCOM
R
100 Ω
VBIAS = (VAVDD + VAVSS) /2
R
0 = off
1 = on
VBIAS bit 1 of POWER
(register address = 01h)
AVSS
图9-26. Level-Shift Voltage Diagram
When operating the ADC with ±2.5-V analog supplies, either ground the AINCOM pin or use the level-shift
voltage. Level shift other inputs by connecting the input pins to the REFOUT pin (2.5 V). The turn-on time of the
level-shift voltage depends on the pin load capacitance. The total capacitance includes those connected to
AVDD, AVSS and ground. 表9-7 lists the level-shift voltage settling times for various external load capacitances.
Be certain the level-shift voltage is fully settled before starting a conversion.
表9-7. Level-Shift Enable Time
LOAD CAPACITANCE
LEVEL-SHIFT VOLTAGE SETTLING TIME
0.1 µF
1 µF
0.22 ms
2.2 ms
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表9-7. Level-Shift Enable Time (continued)
LOAD CAPACITANCE
LEVEL-SHIFT VOLTAGE SETTLING TIME
10 µF
22 ms
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9.3.13 General-Purpose Input/Output (GPIO)
Eight analog inputs can be programmed as GPIO functions (GPIO[0] through GPIO[7]). The GPIO function is a
digital input/output with a logic value that is read and written by the GPIODAT data register. The GPIO voltage
levels are referenced to the ADC analog power supply voltages, VAVDD and VAVSS. The GPIO input voltage
threshold for logic 1 is (VAVDD + VAVSS) / 2. As shown in 图 9-27, analog inputs, AIN3 through AINCOM, can be
programmed for GPIO function. Register GPIOCON programs the GPIO connection for each pin (1 = connect).
Register GPIODIR programs the direction of each pin, either as input or output (0 = output). Register GPIODAT
is the GPIO data value register. Note if a GPIO pin is programmed as an output, the readback data value of the
corresponding GPIODAT register bit is zero.
AVDD
CON[7:0] bits 7:0 of GPIOCON 0 = no connect
1 = connect
(register address = 12h)
DAT[7:0] bits 7:0 of GPIODAT
(register address = 14h)
0 = VGPIO < (VAVDD+ VAVSS) /2
1 = VGPIO > (VAVDD+ VAVSS) /2
GPIO[0]
GPIO[1]
GPIO[2]
AIN3
AIN4
GPIO
1 of 8
Write
0
Read
AIN5
0
1
GPIO[3]
GPIO[4]
AIN6
AIN7
+
GPIO[5]
GPIO[6]
GPIO[7]
GPIO Read Select
AIN8
œ
AIN9
VAVDD + VAVSS
2
DIR[7:0] bits 7:0 of GPIODIR
(register address = 13h)
AINCOM
0 = Output
1 = Input
AVSS
图9-27. GPIO Block Diagram
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9.3.14 Test DAC (TDAC)
The ADC includes a test voltage digital-to-analog converter (TDAC) intended for ADC self-testing and
verification. The TDAC is capable of providing single-ended, differential and common mode test voltages. The
voltages are suitable to test the ADCs under all gains and input configurations.
As shown in 图 9-28, the TDAC consists of two independent DACs, TDACP, and TDACN. The DACs have
independent control registers to program the output voltage. TDACP is programmed by register TDACP and
TDACN is programmed by register TDACN. The TDACP output connects to the ADC1 and ADC2 positive input
multiplexer input and TDACN connects to the ADC1 and ADC2 negative input multiplexer. The OUT1 and OUT2
bits can be programmed to connect the TDAC outputs to pins AIN6 and AIN7. The TDAC outputs are unbuffered
and should not be loaded. The TDAC reference voltage is the analog supply (VAVDD – VAVSS); therefore, the
output levels refer to, and scale with, the analog power supply. Note that chop mode must be disabled to test the
ADC with the TDAC.
AVDD
AVSS
VTDACP
MAGP[4:0] bits 4:0 of TDACP
(register address = 10h)
TDACP
ADC1 Input
MUX
VTDACN
MAGN[4:0] bits 4:0 of TDACN
(register address = 11h)
TDACN
>0000h: > Mid-supply
00000: = Mid-supply
<0000h: < Mid-supply
ADC2 Input
MUX
AIN6
0: No connect
1: Connect
OUTP bit 7 of TDACP
(register address = 10h)
AIN7
0: No connect
1: Connect
OUTN bit 7 of TDACN
(register address = 11h)
图9-28. Test DAC Block Diagram
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表 9-8 shows the TDAC output voltages and the corresponding output impedance. The TDAC settings are
binary-weighted and correspond to the binary-weighted ADC gains. To generate a single ended test voltage, set
TDACN = 00h. This value sets the TDACN voltage to mid-supply. Set TDACP above or below the TDACN
voltage to generate positive or negative test voltages, respectively. Differential test voltages are generated by
setting TDACP and TDACN to symmetric values centered around a common-code value (typical common value
= 00h). For example, use code values equal to 01h and 11h, 02h and 12h, and so forth, to generate a differential
voltage. To generate common-mode test voltages, set the TDACs to equal values.
表9-8. TDAC Output Voltage
OUTPUT
IMPEDANCE
TDACP, TDACN
REGISTER VALUES
DIVIDER RATIO
(V/V)
OUTPUT VOLTAGE (V),
5-V SUPPLY(1)
OUTPUT VOLTAGE (V),
±2.5-V SUPPLY(1)
(kΩ)
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
11h
12h
13h
14h
15h
16h
17h
18h
19h
0.9
0.7
4.5
3.5
2
1
2.9
6.4
8.7
10
0.6
3
0.5
0.55
2.75
0.25
0.525
0.5125
0.50625
0.503125
0.5015625
0.5
2.625
2.5625
2.53125
2.515625
2.5078125
2.5
0.125
10.7
9.6
8.7
8.1
7.8
7.5
7.8
8.1
8.7
9.6
10.7
10
0.0625
0.03125
0.015625
0.0078125
0
0.4984375
0.496875
0.49375
0.4875
0.475
0.45
2.4921875
2.484375
2.46875
2.4375
2.375
2.25
–0.0078125
–0.015625
–0.03125
–0.0625
–0.125
–0.25
–0.5
0.4
2
8.7
6.4
2.9
0.3
1.5
–1
0.1
0.5
–2
(1) Output voltages relative to VDGND
.
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9.3.15 ADC2 (ADS1263)
The ADS1263 includes an auxiliary, 24-bit, delta-sigma ADC (ADC2). ADC2 operation is independent of ADC1,
with independent selections of input channel, reference voltage, sample rate, and channel gain. All input
configurations (channel select, IDAC, level shift, sensor bias) are available to ADC2. Use ADC2 to perform main
channel (ADC1) cross-checking measurements (for example, diagnostics purposes and redundant channel
measurements), system background measurements, or temperature compensation of the primary sensor (such
as thermocouple cold junction compensation). Using data rates of 10, 100, and 400 SPS for both ADCs, ADC2
performs virtual parallel conversions with ADC1 on the same input channel.
As shown in 图 9-29, the ADC2 consists of an input signal multiplexer followed by a high-impedance PGA. The
input multiplexer has the same functionality as the ADC1 input multiplexer. The sensor bias current source or a
10-MΩ bias resistor can be connected to the multiplexer output. Connect the sensor bias to either of the ADCs.
ADC2 provides gains of 1, 2, 4 ,8, 16, 32, 64, and 128. Depending on the gain settings, ADC2 gains are either
implemented in the PGA or in the modulator. For gains of 1, 2, and 4, the PGA is bypassed and the gain is
performed in the modulator. For gains of 8, 16, 32, 64, and 128, the modulator gain is fixed at gain = 4, and the
additional gains are performed in the PGA.
The PGA drives an inherently-stable, second-order, delta-sigma modulator. The modulator output data are
filtered and down-sampled by a programmable decimation digital filter. The digital filter provides data rates of 10,
100, 400, or 800 SPS with 24-bit resolution. A calibration block follows the digital filter. The calibration block
consists of 16-bit offset correction and 16-bit, full-scale correction registers. The ADC2 reference multiplexer
selects from one of three external reference input pairs, the analog power supply, or the internal reference. The
reference input is buffered to minimize errors caused by external circuit loading.
AVDD
ADC2
Ref
Mux
AVSS
Internal REF P
VREFP2
VREF2N
Internal REF N
AIN0
AIN1
AIN2
AIN3
VAVDD
Sensor Bias
0.5 µA
AIN4
AIN5
ADC2 Ref
Buffer
2 µA
10 µA
50 µA
200 µA
10 MΩ
AIN0
AIN1
ADC2
Input
Mux
VAINP2
24-bit
Output Data
ADC2
2nd order
ûꢀ Modulator
ADC2
Digital Filter
(sinc3/sinc1)
ADC2
PGA
ADC2
Calibration
AIN2
VAINN2
AIN3
AIN4
AIN5
PGA bypassed for
gains = 1, 2 and 4
AIN6
0.5 µA
2 µA
AIN7
AIN8
10 µA
50 µA
200 µA
10 MΩ
AIN9
AINCOM
VAVSS
TEMP Sensor P
TEMP Sensor N
VAVDD
Dual Sensor
Excitation
Analog Supply Mon P
Analog Supply Mon N
50 µA
100 µA
250 µA
500 µA
750 µA
1000 µA
1500 µA
2000 µA
2500 µA
3000 µA
Digital Supply Mon P
Digital Supply Mon N
TDAC P
TDAC N
图9-29. ADC2 Block Diagram
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9.3.15.1 ADC2 Inputs
ADC2 features an independent input multiplexer with identical channel selections of ADC1. As shown in 图 9-2,
all the external and internal inputs are available to ADC2. The ADC2 positive input is programmed by the value
of MUXP2[3:0] bits (register ADC2MUX) and the negative input is programmed by the value of the MUXN2[3:0]
bits of same ADC2MUX register. The ADC2MUX register address is 16h.
9.3.15.2 ADC2 PGA
ADC2 features a low-drift, low-noise CMOS PGA. The ADC2 PGA is bypassed for gains = 1, 2 and 4. Therefore,
for these gains the input signal is connected directly to the buffered modulator input.
The full-scale voltage range of ADC2 is determined by the reference voltage and gain. 表 9-9 shows the ADC2
full-scale voltage range versus gain using reference voltage = 2.5 V. The full-scale voltage range scales with the
reference voltage and is increased or decreased by changing the reference voltage.
表9-9. ADC2 Full-Scale Voltage Range
GAIN2[2:0] BITS
OF ADC2CFG REGISTER
FULL-SCALE INPUT RANGE
(V)(1)
GAIN (V/V)
000
001
010
011
100
101
110
111
1
2
±2.500 V
±1.250 V
±0.625 V
±0.312 V
±0.156 V
±0.078 V
±0.039 V
±0.0195 V
4
8
16
32
64
128
(1) VREF = 2.5 V. The full-scale voltage range is proportional to VREF
.
As with many amplifiers, do not exceed the PGA absolute input voltage requirement. For gains ≥ 8 (PGA
active), the absolute input voltage is limited by the PGA output voltage swing range. The specified minimum and
maximum absolute input voltages (VINP2 and VINN2) depend on the PGA gain, the input differential voltage (VIN2),
and the tolerance of the analog power supply voltages (VAVDD, VAVSS). If using ADC2 in an overall gain ≥ 8, the
absolute positive and negative input voltage must be within the specified range, as shown in 方程式15:
VAVSS + 0.3 + |VIN2| · (Gain –1) / 2 · < VINP2 and VINN2 < VAVDD –0.3 –|VIN2| · (Gain –1) / 2
(15)
where
• VINP2, VINN2 = ADC2 absolute input voltage
• VIN2 = ADC2 differential input voltage = VINP2 - VINN2
• Gain = 8, 16, 32, 64 or 128
For gains 1, 2, or 4, the ADC2 absolute input voltage range extends beyond the VAVDD and VAVSS supply
voltages, allowing voltage inputs at or below ground. The absolute input voltage range corresponding to gains 1,
2 and 4 is shown in 方程式16:
V
AVSS –0.1 < VINP2 and VINN2 < VAVDD + 0.1
(16)
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9.3.15.3 ADC2 Reference
ADC2 requires a reference voltage for operation. Use the ADC2 reference multiplexer to select from one of the
external reference sources on pins AIN0 to AIN5, the internal 2.5-V internal reference, or the analog power
supply, as shown in 图 9-30. The external reference uses positive and negative pairs for the positive and
negative references, respectively. The external reference input pairs are pins AIN0-AIN1, AIN2-AIN3, and AIN4-
AIN5, for the positive and negative references, respectively.
0 = Internal reference off
1 = Internal reference on
INTREF bit 0 of POWER
(register address = 01h)
REF[2:0] bits 5:4 of ADC2CFG
(register address = 15h)
+2.5 V
Reference
AVDD
REFOUT
000h
001h
010h
011h
AIN0
AIN2
AIN4
ADC2 REFMUX P
(A)
1 mF
100h
VREFP2
VREFN2
000h
001h
010h
011h
AIN1
AIN3
BUF
AIN5
ADC2 REFMUX N
100h
ADC2
AVSS
A. The internal reference requires a 1-μF capacitor connected to pins REFOUT and AVSS.
图9-30. ADC2 Reference Multiplexer
9.3.15.4 ADC2 Modulator
ADC2 is an inherently stable, second-order, ΔΣ modulator. The modulator samples the analog input voltage at
fMOD2 = fCLK / 144 = 51.2 kHz and converts the analog input to a ones density bit-stream output. The digital filter
receives the ones density bit stream output, and then filters and decimates the data to yield the final conversion
result.
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9.3.15.5 ADC2 Digital Filter
The ADC2 digital filter receives the modulator output and produces a 24-bit digital output. The digital filter low-
pass filters and down-samples the modulator data to yield the final data rate. The ADC2 digital filter is a cascade
of two stages. The first stage is a sinc3 filter that decimates by 64, 128, or 512, to derive data rates of 800 SPS,
400 SPS, or 100 SPS, respectively. The second stage receives the output of the first stage at 100 SPS. The
second stage is a sinc1 filter with decimation equal to ten that derives the data rate of 10 SPS, as illustrated in 图
9-31. The ADC bypasses the second stage for data rates of 800 SPS, 400 SPS, and 100 SPS. 表 9-10 shows
the sinc filter data rates and decimation ratios (A and B) that correspond to each filter stage. The overall filter
decimation ratio is the product of A and B decimation ratios. The data rate is programmed by the DR2[1:0] bits of
register ADC2CFG.
fCLK: 7.3728 MHz
800 SPS
400 SPS
100 SPS
fCLK / 144
fMOD2: 51.2 kHz
51.2 kHz
ADC2
Calibration
ADC2
Final data output
Clip to 24 Bits
100 SPS
10 SPS
ADC2
Sinc1 Filter
Sinc3 Filter
Decimation A
(64,128, 512)
Decimation B
(10)
DR2[1:0] bits 7:6 of ADC2CFG
(register address = 15h)
00 = 10 SPS
01 = 100 SPS
10 = 400 SPS
11 = 800 SPS
图9-31. ADC2 Digital Filter Block Diagram
表9-10. ADC2 Data Rates and Filter Decimation Ratios
DR2[1:0] BITS OF
1st STAGE
2nd STAGE DECIMATION
RATIO B
DATA RATE (SPS)(1) REGISTER ADC2CFG DECIMATION RATIO A
10 ( default)
100
00
01
10
11
512
512
128
64
10
-
400
-
800
-
(1) fCLK = 7.3728 MHz. The data rate scales with fCLK
.
The low pass nature of the ADC2 sinc filter establishes the overall frequency response. The frequency response
is given by 方程式17:
3
»
…
ÿ
»
…
ÿ
144 ŒfA
fCLK
73728 Œf B
fCLK
sin
sin
Ÿ
Ÿ
⁄
⁄
H( = Hsinc 3
(
f
)
ì Hsinc
(
f
)
=
ì
f
)
»
…
ÿ
»
…
ÿ
144 Œf
fCLK
73728 Œf
fCLK
A ì sin
B ì sin
Ÿ
⁄
Ÿ
⁄
(17)
where
• f = Input frequency
• fCLK = ADC clock (7.3728 MHz)
• A = First stage decimation ratio
• B = Second stage decimation ratio
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Figures 图 9-32 through 图 9-36 show the frequency response of different ADC2 data rates. Nulls are located in
the frequency response at the data rate and at data rate multiples. 图 9-32 (data rate = 10 SPS) has frequency
response nulls at 50 Hz and 60 Hz and their multiples. Therefore, the rate of 10 SPS provides rejection of power
line cycle frequencies. 图9-33 shows filter response detail of frequencies centered around 50 Hz and 60 Hz.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
10 20 30 40 50 60 70 80 90 100 110 120
Frequency (Hz)
46
48
50
52
54 56
Frequency (Hz)
58
60
62
64
D018
D019
图9-32. ADC2 10 SPS Frequency Response
图9-33. ADC2 10 SPS Frequency Response 50-Hz
and 60-Hz Detail
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
0
0.4 0.8 1.2 1.6
2
Frequency (kHz)
2.4 2.8 3.2 3.6
4
D020
D021
图9-34. ADC2 100 SPS Frequency Response
图9-35. ADC2 400 SPS Frequency Response
0
-20
-40
-60
-80
-100
-120
-140
0
0.8 1.6 2.4 3.2
4
Frequency (kHz)
4.8 5.6 6.4 7.2
8
D022
图9-36. ADC2 800 SPS Frequency Response
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表 9-11 summarizes the ADC2 digital filter –3-dB bandwidth and 50-Hz and 60-Hz line-cycle rejection based on
2% and 6% ratio tolerance of power-line frequency to ADC clock frequency. The sample rate of 10 SPS has
frequency response nulls at 50 Hz and 60 Hz; therefore, this data rate provides the best possible rejection of
power-line interference.
表9-11. ADC2 –3-dB Bandwidth, 50-Hz and 60-Hz Line Cycle Rejection
DIGITAL FILTER RESPONSE (dB)
-3-dB BANDWIDTH
(Hz)
50-Hz REJECTION
±2%
60-Hz REJECTION
±2%
50-Hz REJECTION
±6%
60-Hz REJECTION
±6%
DATA RATE (SPS)
10
4.4
26
–41
–12
–0.5
–0.2
–47
–17
–0.9
–0.2
–32
–10
–0.5
–0.1
–36
–16
–0.9
–0.2
100
400
800
104
208
The ADC digital filter provides attenuation of frequencies greater than ½ of the data rate (Nyquist frequency) to
minimize out-of-band frequencies folding back to the bandwidth of interest. As with all digital filters, response
images appear at frequency multiples of the filter input frequency (fMOD2 = fCLK / 144 = 51.2 kHz). 图 9-37 shows
the frequency response to 175 kHz for DR = 800 SPS. The response near dc is the desired signal bandwidth.
Note how the filter response repeats at multiplies of 51.2 kHz. The filter response repeats at frequencies shown
in 方程式18:
Aliased frequency bands = N · fMOD2 ± fDR2
(18)
where
• N = 1, 2, 3...
• fDR2 = ADC2 data-rate frequency
The digital filter attenuates signal or noise up to the frequency where the response repeats. However, any signal
or noise present within the frequency bands where the response repeats aliases into the passband, unless
attenuated by an analog filter. Often, using a simple RC analog filter is sufficient to reject these frequencies.
0
-20
-40
-60
-80
-100
-120
-140
0
25
50
75 100
Frequency (kHz)
125
150
175
D023
图9-37. ADC2 Frequency Response to 175 kHz
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9.4 Device Functional Modes
9.4.1 Conversion Control
ADC1 conversions are controlled by the START pin or by serial commands. If using commands to control ADC1
conversions, keep the START pin low to avoid possible contentions between the START pin and commands.
ADC1 has two conversion modes: continuous or pulse. Continuous-conversion mode converts indefinitely until
stopped by the user. Pulse-conversion mode performs one conversion after the START pin is taken high or after
the start command is sent. Use RUNMODE (bit 6, MODE0) to program the conversion mode. 图 9-38 shows the
start and stop timing to control ADC conversions.
tw(STH)
(A)
START pin
tw(STL)
or
Serial (B)
Command
STOP
START
tsu(STDR)
td(STDR)
DRDY pin
th(DRSP)
A. START and DRDY pins apply only to ADC1 operation.
B. Start and stop opcodes take effect on the 7th SCLK falling edge.
C. Start and stop opcodes:
•
•
•
•
START1 for ADC1: 08h or 09h
START2 for ADC2: 0Ch or 0Dh
STOP1 for ADC1: 0Ah or 0Bh
STOP2 for ADC2: 0Eh or 0Fh
图9-38. ADC1 Start and Stop Conversion Timing
表9-12. ADC1 START and STOP Conversion Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
(1)
tw(STH)
tw(STL)
td(STDR)
START pin high: pulse duration
4
tCLK
tCLK
tCLK
START pin low to re-start conversion: pulse duration
Start condition to DRDY high: delay time
4
Pulse conversion mode
2
Continuous conversion
mode
Stop condition to DRDY↓stopping additional
conversions: set-up time
tsu(STDR)
th(DRSP)
16
16
tCLK
Continuous conversion
mode
DRDY↓to stop condition to continue current
conversion: hold time
tCLK
(1) tCLK = 1 / fCLK
9.4.1.1 Continuous Conversion Mode
To start ADC1 conversions, take the START pin high or send the START1 command. In this mode, ADC1
continuously converts until stopped by taking the START pin low or by sending the STOP1 command. To restart
a conversion in progress, toggle the START pin or send a STOP1 and START1 command sequence. DRDY is
driven high if conversions are restarted. DRDY is driven low when the conversion data are ready. See 图 9-38
and 表9-12 for stop-to-DRDY timing requirements in order to stop further conversions.
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9.4.1.2 Pulse Conversion Mode
In pulse conversion mode, ADC1 performs one conversion each time the START pin is taken high or the
START1 command is sent. After the first conversion completes, further conversions are automatically stopped.
To restart a conversion in progress, toggle the START pin or send a STOP1 and START1 command sequence.
The DRDY output is driven high to indicate conversion start, and is driven low when the conversion data are
ready. If a stop command is sent during an ongoing conversion, the command has no effect because the ADC
completes the conversion.
The pulse conversion mode cannot be used in conjunction with chop mode. Instead, use the continuous-
conversion mode when chop is enabled by briefly pulsing the START pin (or sequentially send the START1 and
STOP1 commands) to achieve the same single-conversion result provided by the pulse conversion mode.
9.4.1.3 ADC2 Conversion Control (ADS1263)
ADC2 conversions are independent of ADC1 conversions, and are controlled by commands only. The ADC2
conversion mode is similar to the ADC1 continuous conversion mode. To start an ADC2 conversion, send the
START2 command. Conversions continue until the STOP2 command is sent. To restart a conversion in
progress, send a STOP2 and START2 command sequence.
9.4.2 Conversion Latency
The digital filter averages and down-samples data from the modulator to provide the final data rate (rate
reduction). The order of the digital filter affects the amount of data averaging and in turn, the time delay of the
conversion (or filter latency). The FIR and sinc1 filter modes are zero latency providing the conversion result in
single cycle. The higher order sinc filters (sinc2, 3, 4, 5) have more than one conversion latency and therefore
require more conversion cycles to provide fully settled data. Tradeoffs can be made between 50-Hz and 60-Hz
line cycle rejection verses conversion latency by selection of the sinc filter order. A higher order sinc filter
increases the rejection of the 50-Hz and 60-Hz line cycles, but also increases the filter latency. Filter latency is
an important consideration when multiplexing (scanning) through input channels. To make sure that conversions
are settled after changing channels, start a new conversion for each channel using the START pin or start
command. Note if the multiplexer is changed during ongoing conversions, the conversion is stopped and
restarted at the time multiplexer register is changed.
表 9-13 lists the filter latency after starting the first conversion. Note the conversion latency depends on the filter
setting. The conversion latency is illustrated in 图 9-39. Parameter td(STDR) shows the latency from start to
conversion data ready (DRDY low). Note that settled data are provided, assuming the analog input is settled
before the start condition. After the first conversion is completed (in continuous conversion mode), subsequent
conversions occur at the nominal data rate. The latency values are for the programmable time-delay parameter
set to off (DELAY[3:0] = 000).
Settled VIN
VIN = VAINP - VAINN
START pin
or
Serial Command
START1
td(STDR)
DRDY pin
图9-39. Conversion Latency After Start Condition
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表9-13. ADC1 Conversion Latency, td (STDR)
CONVERSION LATENCY(1) (ms)
DATA RATE
(SPS)
SINC1
400.4
200.4
100.4
60.35
50.35
20.35
17.02
10.35
2.855
1.188
0.771
0.563
0.494
—
SINC2
800.4
400.4
200.4
120.4
100.4
40.42
33.76
20.42
5.424
2.091
1.258
0.8409
0.702
—
SINC3
1,200
600.4
300.4
180.4
150.4
60.42
50.42
30.42
7.924
2.924
1.674
1.049
0.841
—
SINC4
1,600
800.4
400.4
240.4
200.4
80.42
67.09
40.42
10.42
3.758
2.091
1.258
0.980
—
SINC5
FIR
2.5
5
402.2
202.2
102.2
—
—
10
—
16.6
20
—
—
52.22
—
50
—
—
—
—
—
—
—
—
—
—
—
—
60
—
100
—
400
—
1200
2400
4800
7200
14400
19200
38400
—
—
—
—
0.424
0.337
0.207
—
—
—
—
—
—
—
—
(1) Chop and IDAC rotation off, DELAY[3:0] = 0000.
If using chop or IDAC rotation modes, the latency of the first conversion increases. The latency of chop and
IDAC rotation modes is shown in 方程式19 and 方程式20.
Chop or IDAC rotation mode: latency = 2 · (td(STDR) + DELAY[3:0] value)
Chop and IDAC rotation modes: latency = 4 · (td(STDR) + DELAY[3:0] value)
(19)
(20)
In addition, chop or IDAC rotation mode can reduce the conversion data rate depending on the time-delay
parameter. The 50-Hz and 60-Hz filter response nulls are not altered by chop or IDAC rotation modes. 方程式21
shows the effective data rate with the DELAY parameter.
Chop or IDAC rotation mode data rate = 1 / (td(STDR) + DELAY[3:0] value)
(21)
表 9-14 shows the first conversion latency of ADC2. The filter latency is the elapsed time after sending the
START2 command before the first conversion is ready.
表9-14. ADC2 Conversion Latency, td (STDR)
DATA RATE (SPS)
CONVERSION LATENCY (ms)
10
121
31.2
8.71
4.97
100
400
800
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If the input signal changes while the ADC is continuously converting, the output data are a mix of old and new
data, as shown in 图 9-40. The filter latency values for settled data (td(STDR)) with an input step change while
continuously converting is shown in 表 9-15. The filter latency values listed in the table (td(STDR)) assume the
analog input is settled before the start of the first whole conversion period.
New VIN
Old VIN
VIN = VAINP - VAINN
Fully settled
new data
Mix of old data
and new data
Old data
DRDY pin
td(DRDR)
图9-40. ADC1 Latency Timing While Continuously Converting
表9-15. Fully-Settled Conversion Values for 图9-40
FULLY SETTLED CONVERSION
td(DRDR)
DIGITAL FILTER
FIR
(1 / DR)(1)
1
1
2
3
4
5
Sinc1
Sinc2
Sinc3
Sinc4
Sinc5
(1) Chop and IDAC rotation modes off.
9.4.3 Programmable Time Delay
When a new conversion is started, the ADC provides an internal delay of 52 µs before the actual start of the
conversion. This timed delay is provided to allow for the integrated, analog, antialias filter to settle. In some
cases, more delay is required to allow for external settling effects. Program additional time by using bits
DELAY[3:0] of the MODE register. The programable range is 8.7 µs to 8.8 ms in binary steps. As an alternative
to using the programmable time delay, the initiation of the start condition can also be delayed as needed after an
ADC configuration change. For CHOP or IDAC rotation modes, additional time delay may be necessary to allow
for external settling effects, and can only be provided by the DELAY bits; see 表9-38 for the delay settings.
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9.4.4 Serial Interface
The ADC has an SPI-compatible, bidirectional serial interface that is used to read the conversion data as well as
configure and control the ADC. The serial interface consists of four control lines: CS, SCLK, DIN, and DOUT/
DRDY. If the ADS1262 or ADS1263 is the only device connected to the SPI bus, the CS input can be tied low,
resulting in a minimum of three control signals for communications: SCLK, DIN, and DOUT/DRDY. The ADC has
a data ready output signal (DRDY) that asserts regardless of interface selection. The DRDY functionality is also
integrated with the DOUT/DRDY pin.
9.4.4.1 Chip Select (CS)
The CS pin is an active low input that enables the ADC serial interface for communication. CS must be low
during the entire data transaction. When CS is high, the serial interface is reset, SCLK input activity is ignored
(blocking input commands), and the DOUT/DRDY output pin enters a high-impedance state. ADC conversions
are not affected by the state of CS. If the serial bus is dedicated to the ADC, the CS pin can be optionally tied
low to reduce the serial interface from four I/Os to three I/Os. Tying the CS pin low permanently enables the ADC
serial interface. The DRDY output asserts low when conversion data are ready and is not affected by CS.
9.4.4.2 Serial Clock (SCLK)
The serial interface clock is a noise-filtered, Schmidt-triggered input used to clock data into and out of the ADC.
Input data to the ADC is latched on the falling SCLK edge and data output from the ADC is updated on the rising
SCLK edge. Return SCLK low after the data sequence is complete. Even though the SCLK is a noise-immune,
keep SCLK as clean as possible to prevent unintentional SCLK transitions. Avoid ringing and voltage overshoot
on the SCLK input. Place a series termination resistor at the SCLK drive pin to help reduce ringing.
9.4.4.3 Data Input (DIN)
The DIN pin is the serial data input to the ADC. DIN is used to input commands and register data to the ADC.
The ADC latches input data on the falling edge of SCLK. During direct-mode data readback, when no command
is intended, keep DIN low.
9.4.4.4 Data Output/Data Ready (DOUT/DRDY)
The DOUT/DRDY pin is a dual-function output. The pin functions as the digital data output and the ADC1 data-
ready indication. When CS is high, the DOUT/DRDY pin is in high-impedance mode (tri-state). Output data are
updated on the rising edge of SCLK. As a data-ready indicator, the DOUT/DRDY pin transitions low at the same
time as the DRDY pin. Therefore, monitor either the DOUT/DRDY pin or the DRDY pin to determine when ADC1
data are ready. CS must be low to monitor DOUT/DRDY as a data-ready indicator.
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9.4.4.5 Serial Interface Autoreset
The CS input resets the serial interface when taken high. However, applications that tie the CS pin low do not
have the ability to reset the serial interface by using this pin. If a false SCLK occurs (for example, caused by a
noise pulse or clocking glitch), the serial interface may inadvertently advance one or more bit positions, resulting
in loss of synchronization to the external microcontroller. If loss of synchronization occurs, the interface does not
respond correctly until the interface is reset.
For applications that tie CS low, the ADC provides a feature that automatically resets the serial interface in the
event of a glitch. As shown in 图 9-41, after the first SCLK low-to-high transition is detected by the ADC (either
caused by a glitch or a normal SCLK input), if the ADC does not detect seven additional SCLK transitions within
65536 fCLK cycles (approximately 8.9 ms), the serial interface resets. After reset, the interface is ready for the
next transaction four fCLK cycles later.
If the seven SCLK transitions are detected within the 65536 fCLK cycles, the serial interface is not reset, and the
SCLK detection cycle restarts at the next SCLK transition.
If the serial interface loses synchronization to an external controller, reset the serial interface by holding SCLK
low for 65536 fCLK cycles.
The serial interface autoreset function is enabled by the setting TIMEOUT = 1 (bit 3 of the INTERFACE register).
The default mode is off.
TIMEOUT bit 3 of INTERFACE
(register address = 02h)
0 = Disabled
1 = Enabled
Serial Interface
Auto-reset
td(SCRS)
td(RSSC)
b7
b6
b5
b4
b3
b2
b1
b0
SCLK pin
图9-41. Serial Interface Autoreset
表9-16. Autoreset Timing Requirement
PARAMETER
TEST CONDITIONS
MIN
UNIT
(1)
td(SCRS)
td(RSSC)
TIMEOUT bit =1
TIMEOUT bit =1
65536
4
tCLK
tCLK
SCLK↑transition to interface reset : delay time
Serial interface reset to first SCLK↑: delay time
(1) tCLK = 1 / fCLK
.
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9.4.5 Data Ready Pin (DRDY)
The DRDY pin is an output that transitions low to indicate when ADC1 conversion data are ready for retrieval. 图
9-42 depicts the DRDY operation. Initially, DRDY is high at power-on. When converting, the state of DRDY
depends on the conversion mode (continuous or pulse) and whether the conversion data are retrieved or not. In
Continuous conversion mode, after DRDY goes low, DRDY is driven high on the first SCLK falling edge. If data
are not read, DRDY remains low and then pulses high 16 fCLK cycles before the next DRDY falling edge. The
data must be retrieved before the next DRDY falling edge otherwise the data are overwritten by new data and
previous data are lost. In Pulse mode, DRDY is driven high when a conversion is started and goes low when the
conversion data are ready. DRDY remains low until the next conversion is started.
The DOUT/DRDY output operates similarly to DRDY. DOUT/DRDY transitions low when ADC1 conversion data
are ready. If data are not retrieved, the DOUT/DRDY pin stays low and is pulsed high for 16 fCLK cycles at the
next data ready. Note that CS must be low to enable the DOUT/DRDY pin.
tc(DR)
tw(DRL)
DRDY
With data retrieval
(Continuous conversion Mode)
DRDY
No data retrieval
(Continuous conversion Mode)
tw(DRH)
DRDY
(Pulse conversion Mode)
START Pin
or
Command
START1
STOP1
START1
STOP1
图9-42. DRDY Operation
表9-17. DRDY Timing Characteristics
PARAMETER
TEST CONDITIONS
TYP
UNIT
DRDY↓to DRDY↓conversion time: DRDY
period
tc(DR)
After first conversion
1
1/data rate
DRDY drives high
on first falling
SCLK edge
With data retrieval, Continuous
conversion mode
t w(DRL)
DRDY↓to DRDY↑: delay time
No data retrieval, Continuous
conversion mode,
(1)
t w(DRH)
DRDY pulse high: pulse duration
16
tCLK
(1) tCLK = 1 / fCLK
.
9.4.6 Conversion Data Software Polling
In addition to hardware polling using DRDY, new conversion data are also detected by software polling. In
software polling, read either ADC1 or ADC2 conversion data and poll the STATUS byte ADC1 or ADC2 data-
ready bits. The data ready bits are set if the corresponding ADC1 or ADC2 conversion data are new since the
last ADC1 or ADC2 data read; otherwise, the bits are cleared. If the bits are cleared, the corresponding
conversion data are the previous data. To avoid missing data when using software polling, poll the status bits at
a rate faster than the corresponding ADC1 or ADC2 conversion rate. The ADC2 status bit is valid only when the
data are read by command (RDATA1 or RDATA2).
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9.4.7 Read Conversion Data
ADC1 data are read by two methods: read data direct or read data by command. ADC1 writes new conversion
data to the output shift register and the internal data-holding register. Two registers hold the conversion data;
therefore, data are read either from the output shift register (in direct mode) or read from the data-holding
register (in command mode). Reading data from the data-holding register (command mode) does not require
synchronizing the start of data readback to DRDY. ADC2 data are read only from the ADC2 data-holding register
(command mode).
9.4.7.1 Read Data Direct (ADC1 Only)
In this method of data retrieval, ADC1 conversion data are shifted out directly from the output shift register. No
opcode is necessary. Read data direct requires that no serial activity occur from the time of DRDY low to the
readback, or the data are invalid. The serial interface is full duplex; therefore, commands are decoded during the
data readback. If no command is intended, keep the DIN pin low during readback. If an input command is sent
during readback, the ADC executes the command, and data interruption may result. The data readback
operation must be completed 16 fCLK cycles before the next DRDY, or the old data are overwritten with new
data. Synchronize the data readback to DRDY or to DOUT/DRDY to make sure the data are read before the
next DRDY falling edge.
If new ADC1 conversion data are ready during an ongoing data or register read or write operation, data are not
loaded to the output register but are written only to the data holding register. Retrieve the conversion data later
from the holding register by sending a read command. However, writing new data to certain registers results in a
conversion-cycle restart. Conversion restart clears the contents of the conversion data-holding register;
therefore, the previous conversion data are not available. Read the conversion data before the register write
operation.
As shown in 图 9-43, the ADC1 data field is 4, 5, or 6 bytes long, depending on programming. The data field
consists of an optional status byte, four bytes of conversion data, and an optional checksum byte. After all the
bytes are read, the data-byte sequence is repeated by continuing SCLK. The byte sequence repeats starting
with the first byte. In order to help verify error-free communication, read the same data multiple times in each
conversion interval and compare.
(A)
DRDY
CS (B)
48
9
25
40
1
17
33
SCLK
DIN
HI-Z
DOUT/DRDY
Status
Data 1
Data 2
Data 3
Data 4
CRC/CHK
Optional (D)
Repeat
(C)
Optional (D)
Repeated Data (E)
00 = Off
ADC1 Data Bytes
0 = Off
1 = On
01 = Checksum
10 = CRC
STATUS bit 2 of INTERFACE
(register address = 02h)
CRC[1:0] bits 1:0 of INTERFACE
(register address = 02h)
A. In Continuous conversion mode, DRDY returns high on the first SCLK falling edge. In Pulse Conversion mode, DRDY stays low until the
next conversion is started.
B. CS can be tied low. If CS is low, DOUT/DRDY asserts low at the same time as DRDY.
C. Data read must be completed before DOUT/DRDY and DRDY goes high (16 tCLK before new data ready).
D. The STATUS and CRC/CHK bytes are optional.
E. The byte sequence repeats by continuing SCLK.
图9-43. Data Read Direct
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9.4.7.2 Read Data by Command
In this method of data retrieval, a command is used to read ADC1 or ADC2 data. When the command is sent,
the data are retrieved from the respective ADC data-holding register. Read the data at any time because the
command method does not require synchronizing to DRDY. In addition to hardware polling of DRDY or DOUT/
DRDY to determine when ADC1 data are ready, the ADC can be software polled by reading bits ADC1 and
ADC2 of the status byte. If the ADC1 or ADC2 status bit is 1, the ADC1 or ADC2 data are new since the last
ADC1 or ADC2 read operation. If data are read again before the new data are ready, the status bit is 0 and the
previous data are returned. ADC2 data can only be read by the command method.
图 9-44 shows the read data by command sequence. The output data MSB begins on the first rising edge of
SCLK after the command. The output data field can be 4, 5, or 6 bytes long, depending on programming. The
data field consists of an optional status byte, four bytes of conversion data, and an optional checksum byte. The
ADC2 data block consists of the optional status byte, 3 bytes of data, a fixed-value byte equal to 00h (zero pad
byte), and the optional checksum byte. A read data command must be sent for each read operation. The ADC
does not respond to commands until the read operation is complete, or terminated by taking CS high.
(A)
CS
49
9
25
41
1
17
33
(B)
SCLK
DIN
OPCODE (C)
HI-Z
DOUT/DRDY
(D)
Data 4
CRC/CHK
Don‘t Care
STATUS
Data 1
Data 2
Data 3
ADC2 (00h)
ADC2 Data Bytes
ADC1 Data Bytes
Optional (E)
Optional (E)
00 = Off
01 = Checksum
10 = CRC
0 = Off
1 = On
CRC[1:0] bits 1:0 of INTERFACE
(register address = 02h)
STATUS bit 2 of INTERFACE
(register address = 02h)
A. CS can be tied low. If CS is low, DOUT/DRDY asserts low with DRDY.
B. In continuous conversion mode, DRDY returns high on the first SCLK falling edge of sending the opcode. For pulse conversion mode,
DRDY stays low until the next conversion is started.
C. Read ADC1 command byte = 12h or 13h, Read ADC2 command byte = 14h or 15h
D. DOUT/DRDY is driven low with DRDY. If a read operation occurs after DRDY falling edge, then DOUT can be high or low.
E. The STATUS and CRC/CHK bytes are optional.
图9-44. Read Data by Command
9.4.7.3 Data-Byte Sequence
The ADC1 data sequence can be 4, 5, or 6 bytes long, depending on whether the optional status and checksum
bytes are enabled. The entire data sequence consists of the status byte, four bytes of the 32-bit conversion
word, and the checksum byte. The ADC2 data sequence is the same, except the conversion data are three
bytes long (24-bit word), followed by a zero-value pad byte. If the status byte is not enabled, the remaining bytes
are left shifted.
9.4.7.3.1 Status Byte
The status byte is the first byte in the sequence. The status byte indicates new ADC1 and ADC2 data, the state
of the ADC1 PGA alarms, the low-reference alarm state, the clock mode, and the reset state. The status byte is
enabled by the STATUS bit of the INTERFACE register (bit 2 of register 02h). 图 9-45 and 表 9-18 shows the
status-byte field description.
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图9-45. Status Byte
7
6
5
4
3
2
1
0
ADC2
ADC1
EXTCLK
REF_ALM
PGAL_ALM
PGAH_ALM
PGAD_ALM
RESET
表9-18. Status Byte Field Descriptions
Bit
Field
Type
Description
ADC2 Data(1)
7
ADC2
Read Only
This bit indicates the status of ADC2 conversion data
0: ADC2 data not new since the last ADC2 read operation
1: ADC2 data new since the last ADC2 read operation
6
5
4
ADC1
Read Only
Read Only
Read Only
ADC1 Data
This bit indicates the status of ADC1 conversion data
0: ADC1 data not new since the last ADC1 read operation
1: ADC1 data new since the last ADC1 read option
EXTCLK
ADC Clock
This bit indicates the ADC clock source
0: ADC clock is internal
1: ADC clock is external
ADC1 Low Reference Alarm(2)
REF_ALM
This bit is the low reference voltage alarm of ADC1. The alarm bit is set if
REF ≤0.4 V, typical.
V
0: No alarm
1: Low reference alarm
3
2
1
0
PGAL_ALM
PGAH_ALM
PGAD_ALM
RESET
Read Only ADC1 PGA Output Low Alarm (2)
This bit is the ADC1 PGA absolute low voltage alarm. The bit is set if the
absolute voltage of either PGA output is less than VAVSS + 0.2 V. See the
PGA Absolute Output-Voltage Monitor section.
0: No alarm
1: PGA low voltage alarm
Read Only ADC1 PGA Output High Alarm (2)
This bit is the ADC1 PGA absolute high voltage alarm. The bit is set if the
absolute voltage of either PGA output is greater than VAVDD –0.2 V. See
the PGA Absolute Output-Voltage Monitor section.
0: No alarm
1: PGA high voltage alarm
Read Only ADC1 PGA Differential Output Alarm (2)
This bit is the ADC1 PGA differential output range alarm. The bit is set if
the PGA differential output voltage exceeds +105% FS or –105% FS.
See the PGA Differential Output Monitor section.
0: No alarm
1: PGA differential range alarm
Read Only RESET
Indicates device reset. Device reset occurs at power-on, by the RESET/
PWDN pin or by the reset command. This bit is the same as the RESET
bit of the POWER register (see 表9-36).
0: No reset occurred since the RESET bit in power register last cleared by
the user
1: Device reset occurred
(1) The ADC2 status bit is valid only with use of RDATA1 or RDATA2 read data commands.
(2) These bits are valid during the readback of ADC1 data only. All other bits are valid during the readback of either ADC1 or ADC2.
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9.4.7.3.2 Data Byte Format
ADC1 data are 32 bits in a twos complement format that represents positive and negative values, and are output
starting with the most significant bit first (ADC1[31]). The data are scaled so that VIN = 0 V results in ideal code
value of 00000000h; see 表 9-19 for other ideal code values. Some applications require reduction of the 32-bit
data to 24-bit data in order to provide compatibility to 24-bit systems. This reduction is done by simple truncation
(or rounding) of the 32-bit data to 24 bits. See 图9-46 for the ADC1 data byte field.
表9-19. ADC1 and ADC2 Output Codes
INPUT SIGNAL (V)(1)
ADC1 OUTPUT CODE (32 Bits) (2)
ADC2 OUTPUT CODE (24 Bits) (2)
≥VREF / Gain · (2N–1 - 1) / 2N–1
7FFFFFFFh
7FFFFFh
000001h
000000h
FFFFFFh
800000h
VREF / (Gain · 2N–1
)
00000001h
0
00000000h
–VREF / (Gain · 2N–1
≤–VREF / Gain
)
FFFFFFFFh
80000000h
(1) N = 32 (ADC1), N = 24 (ADC2)
(2) Ideal output code, excluding effects of ADC noise, offset, gain and linearity errors.
图9-46. ADC1 Data Field, Four Bytes - 32 Bits
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
ADC1[31:24]
R-0
ADC1[23:16]
R-0
ADC1[15:8]
R-0
1
0
ADC1[7:0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
ADC2 data are 24 bits in a twos complement data format that represents positive and negative code values, and
are output starting with the most significant bit first (ADC2[23]). The data are scaled so that a zero-voltage input
results in an ideal code value of 000000h; see 表 9-19 for other ideal code values. See 图 9-47 for the ADC2
data-byte field.
图9-47. ADC2 Data Field, Three Bytes - 24 Bits
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
2
17
9
16
8
ADC2[23:16]
R-0
ADC2[15:8]
R-0
1
0
ADC2[7:0]
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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9.4.7.3.3 Checksum Byte (CRC/CHK)
The checksum byte is the last byte in the data-byte sequence. The checksum byte can be programmed to
checksum mode or to cyclic redundancy check (CRC) mode. The checksum byte is optional and is enabled by
the CRC[1:0] bits of the INTERFACE register. Use the checksum byte to detect transmission errors during data
read-back. 图 9-48 and 表 9-20 shows the checksum byte description. The checksum byte is not provided when
register data are read.
图9-48. Checksum Byte (CRC/CHK)
7
6
5
4
3
2
1
0
SUM[7:0]
表9-20. Checksum Byte (CRC/CHK) Field Descriptions
Bit
7:0
Field
Type
Description
SUM[7:0]
R
CRC or Checksum value
This byte is the CRC or checksum of four ADC1 data bytes, or three
ADC2 data bytes.
9.4.7.3.3.1 Checksum Mode (CRC[1:0] = 01h)
In checksum mode, the checksum byte is the lower 8-bit sum of the data conversion bytes plus an offset value
9Bh. The offset value is added to help detect whether the DOUT/DRDY has failed and is in a permanent low
state. ADC1 sums four data bytes. and ADC2 sums three data bytes. To verify the correct checksum, sum the
data bytes plus 9Bh and compare the value read from the ADC. If the checksum values do not match, a data
transmission error occurred. In the event of a data transmission error, read the data again for verification. The
checksum provides basic levels of error detection caused by single-bit errors, and limited combinations of
multiple-bit errors.
Example computation of ADC1 four-data-byte checksum calculation:
• Data byte 1: 12h
• Data byte 2: 34h
• Data byte 3: 56h
• Data byte 4: 78h
• Constant: 9Bh
• Checksum value = AFh
9.4.7.3.4 CRC Mode (CRC[1:0] = 10h)
In CRC mode, the checksum byte is the 8-bit remainder of the bitwise exclusive-OR (XOR) of the data bytes by
a CRC polynomial. For ADC1, use four conversion data bytes in the calculation; for ADC2, use three conversion
data bytes. The CRC is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X + 1.
The nine binary coefficients of the polynomial are: 100000111. Calculate the CRC by dividing (XOR operation)
the data bytes (excluding the CRC) with the polynomial and compare the calculated CRC values to the ADC
CRC value. If the values do not match, a data transmission error has occurred. In the event of a data
transmission error, read the data again. The CRC provides a higher level of detection of multiple-bit errors.
The following list shows a general procedure to compute the CRC value:
1. Left shift the initial ADC1 32-bit data value by 8 bits, with zeros padded to the right, creating a new 40-bit
data value (the starting data value). For ADC2, left shift the 24-bit value to create a new 32-bit starting data
value.
2. Align the MSB of the CRC polynomial (100000111) to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation creates a
new, shorter-length value. The bits of the data values that are not in alignment with the CRC polynomial drop
down and append to the right of the new XOR result.
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4. When the XOR result is less than 100h, the procedure ends, yielding the 8-bit CRC value. Otherwise,
continue with the XOR operation shown in step 2, using the current data value. The number of loop iterations
depends on the value of the initial data.
9.4.8 ADC Clock Modes
The ADC conversion process requires a clock for operation. These devices have three clock operating modes:
1. Internal oscillator
2. External clock
3. External crystal
The nominal clock frequency is 7.3728 MHz. The output data rate and the corresponding 50-Hz and 60-Hz filter
response nulls scale with clock frequency. Good line-cycle rejection requires an accurate clock frequency that is
best provided by a crystal oscillator.
As depicted in 图 9-49, the ADC contains an integrated clock generator and automatic detection circuit. If no
external clock is detected, the ADC automatically selects the internal oscillator. If an external clock is detected,
the ADC automatically selects the external clock. The clock mode can be verified by reading the EXTCLK bit, bit
5 of the status byte (0 = internal clock).
Clock Mux
Internal Oscillator
(7.3728 MHz)
System
Clock
Clock Detect
Logic
EXTCLK bit of status byte
(bit 5)
XTAL1/
XTAL2
CLKIN
图9-49. ADC Clock Block Diagram
图9-50 illustrates the configuration for the three clock modes.
External Clock Mode
Crystal Oscillator Mode
Internal Oscillator Mode
XTAL1/
CLKIN
XTAL1/
CLKIN
XTAL1/
CLKIN
XTAL2
XTAL2
C2
XTAL2
7.3728 MHz
Clock
C1
50 Ω
C1, C2: 5 pf to 20 pF
see text
图9-50. Clock Mode Configurations
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9.4.8.1 Internal Oscillator
The ADC contains an integrated 7.3728-MHz internal oscillator. After ADC power-on, the internal oscillator
immediately starts. To select the internal oscillator, ground the XTAL1/CLKIN pin and float the XTAL2 pin; see 图
9-50 (internal oscillator mode).
9.4.8.2 External Clock
Drive the ADC with an external clock by applying the clock input to the XTAL1/CLKIN pin and floating the XTAL2
pin; see 图 9-50 (external clock mode). The ADC automatically detects the external clock. Be sure the external
clock is free of overshoot and glitches. A source-terminating resistor placed at the external clock buffer often
helps to reduce overshoot.
9.4.8.3 Crystal Oscillator
The ADC contains an integrated oscillator circuit for use with an external crystal. Connect the crystal and load
capacitors to the XTAL1/CLKIN and XTAL2 pins; see 图 9-50 (crystal oscillator mode). Place the crystal and
crystal load capacitors close to the ADC pins using short direct traces. Connect the load capacitors to digital
ground. Do not connect any other external circuit to the crystal oscillator. 表 9-21 shows approved crystals for
use with the ADS1262 and ADS1263. The crystal oscillator start-up time is characterized at 10 ms (typical), and
can be longer depending on the crystal characteristics.
表9-21. Recommended Crystals
OPERATING TEMPERATURE
MANUFACTURER
Citizen
FREQUENCY
7.3728 MHz
7.3728 MHz
7.3728 MHz
LOAD CAPACITORS
RANGE
PART NUMBER
HCM497372800ABJT
ATS073BSM-1E
18 pF
18 pF
18 pF
-40°C to +85°C
-40°C to +85°C
-40°C to +125°C
CTS
Abracon
ABLS-7.3728MHZ-K4T
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9.4.9 Calibration
The ADC incorporates offset and gain calibration commands, as well as user-offset and full-scale calibration
registers to calibrate the ADC. The ADC1 calibration registers are 24-bits wide and the ADC2 calibration
registers are 16-bits wide. Use calibration to correct internal ADC errors or overall system errors. Calibrate by
sending calibration commands to the ADC, or by direct user calibration. In user calibration, the user calculates
and writes the correction values to the calibration registers. The ADC performs self or system-offset calibration,
or for full-scale calibration, system calibration. Perform offset calibration before full-scale calibration. After power-
on, but before calibrating, wait for the power supplies and reference voltage to fully settle.
9.4.9.1 Offset and Full-Scale Calibration
Use the offset and full-scale (gain) registers to correct ADC error. As shown in 图 9-51, the value of the offset
calibration register is subtracted from the filter output and then multiplied by the full-scale register value divided
by 400000h. The data are then clipped to a 32-bit value to provide the final output.
VAINP
C A D
+
Output Data
Clipped to 32 bits
Digital
Filter
Final
Output
ADC
VAINN
-
1/400000h
OFCAL[2:0] registers
(register addresses = 07h, 08h, 09h)
>000000h: negative offset
000000h: no offset
<000000h: positive offset
FSCAL[2:0] registers
(register addresses = 0Ah, 0Bh, 0Ch)
<400000h: gain >1
400000h: gain =1
>400000h: gain <1
图9-51. ADC1 Calibration Block Diagram
方程式 22 shows the internal calibration. ADC2 calibration registers are 16 bit. For ADC2, the ADC2FSC[1:0}
registers are for full-scale calibration and the ADC2OFC[1:0] registers are for offset calibration.
ADC1 Final Output Data = (Filter Output - OFCAL[2:0]) · FSCAL[2:0]/400000h
(22)
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9.4.9.1.1 Offset Calibration Registers
The ADC1 offset calibration word is 24 bits, consisting of three 8-bit registers, as shown in 表 9-22. The offset
value is twos complement format with a maximum positive value equal to 7FFFFFh (for negative offset), and a
maximum negative value equal to 800000h (for positive offset). The 24-bit register is internally left-shifted to
align with the 32-bit data before subtraction occurs. A register value equal to 000000h has no offset correction.
Although the offset calibration register allows a wide range of offset values, the input signal cannot exceed
±106% of the precalibrated range in order to prevent ADC overrange. If chop mode is enabled, the offset
calibration register is disabled. 表9-23 shows example settings of the offset register.
表9-22. ADC1 Offset Calibration Registers
BYTE
REGISTER
OFCAL0
OFCAL1
OFCAL2
ORDER
ADDRESS
07h
BIT ORDER
LSB
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
08h
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
09h
B23 (MSB)
B17
B16
表9-23. ADC1 Offset Calibration Register Values
OFCAL[2:0] REGISTER VALUE
OFFSET CALIBRATED 32-BIT OUTPUT CODE(1)
000001h
000000h
FFFFFFh
FFFFFF00h
00000000h
00000100h
(1) Ideal output code with shorted input, excluding ADC noise and offset voltage error.
The ADC2 offset calibration word is 16 bits, consisting of two 8-bit registers, as shown in 表 9-24. The 16-bit
calibration value is internally aligned with the 24-bit ADC2 conversion result. The offset calibration value is
subtracted from the conversion data.
表9-24. ADC2 Offset Calibration Registers
BYTE
REGISTER
ADC2OFC0
ADC2OFC1
ORDER
ADDRESS
17h
BIT ORDER
LSB
B7
B6
B5
B4
B12
B3
B2
B1
B9
B0 (LSB)
B8
MSB
18h
B15
B14
B13
B11
B10
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9.4.9.1.2 Full-Scale Calibration Registers
The ADC1 full-scale calibration word is 24 bits consisting of three 8-bit registers, as shown in 表 9-25. The full-
scale calibration value is straight binary, normalized to a unity-gain correction factor at a register value equal to
400000h. 表 9-26 shows register values for selected gain factors. Correct ADC gain for gain errors greater than
one (resulting in full-scale register values less than 400000h, or less than 4000h for ADC2). However, to prevent
ADC overrange, the input signal must not exceed ±106% of the precalibrated input range. Do not exceed the
PGA input range limits during full-scale calibration.
表9-25. ADC1 Full-Scale Calibration Registers
BYTE
ORDER
REGISTER
ADDRESS
BIT ORDER
FSCAL0
FSCAL1
FSCAL2
LSB
0Ah
0Bh
0Ch
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
MSB
B23 (MSB)
B17
B16
表9-26. ADC1 Full-Scale Calibration Register Values
FSCAL[2:0] REGISTER VALUE
GAIN FACTOR
433333h
400000h
1.05
1.00
0.95
3CCCCCh
The ADC2 full-scale calibration word is 16 bits consisting of two 8-bit registers, as shown in 表 9-27. The full-
scale calibration value is straight binary, normalized to a unity correction factor at a register value equal to
4000h. A full-scale register value greater than 4000h increases the ADC2 gain factor.
表9-27. ADC2 Full-Scale Calibration Registers
BYTE
ORDER
REGISTER
ADDRESS
BIT ORDER
ADC2FSC0
ADC2FSC1
LSB
19h
1Ah
B7
B6
B5
B4
B12
B3
B2
B1
B9
B0 (LSB)
B8
MSB
B15
B14
B13
B11
B10
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9.4.9.2 ADC1 Offset Self-Calibration (SFOCAL1)
The offset self-calibration command corrects internal ADC1 offset error. Program the ADC1 input multiplexer
register (INPMUX) to FFh to force open all input connections before sending the command. When the SFOCAL1
self-calibration command is sent, the ADC shorts together the internal PGA inputs, then averages 16 readings to
reduce the conversion noise for an accurate calibration. When calibration is complete, the calibration result is
written to the 24-bit offset calibration register (OFCAL[2:0]). After calibration, set the input multiplexer to the
desired measurement channel. The offset calibration register is disabled in chop mode.
9.4.9.3 ADC1 Offset System Calibration (SYOCAL1)
The offset system-calibration command corrects ADC1 system offset error. For this type of calibration, externally
short the system inputs before the command. When the SYSOCAL1 command is sent, the ADC averages 16
readings to reduce conversion noise for an accurate calibration. When calibration is complete, the offset
calibration result is written to the 24-bit offset calibration register (OFCAL[2:0]). The offset calibration register is
disabled in chop mode.
9.4.9.4 ADC2 Offset Self-Calibration ADC2 (SFOCAL2)
The offset self-calibration command corrects internal ADC2 offset error. Program the ADC2 input multiplexer
register (ADC2MUX) to FFh to force open all input connections before sending the command. When the
SFOCAL2 self-calibration command is sent, the ADC shorts together the internal PGA inputs of ADC2, then
averages 16 readings to reduce conversion noise for an accurate calibration. When calibration is complete, the
offset calibration result is written to the 16-bit ADC2 offset calibration register ADC2OFC[1:0]. After calibration,
set the input multiplexer to the desired channel.
9.4.9.5 ADC2 Offset System Calibration ADC2 (SYOCAL2)
The offset system-calibration command corrects ADC2 system offset error. For this offset calibration, externally
short the ADC2 inputs before sending the command. When the SYOCAL2 command is sent, the ADC averages
16 readings to reduce conversion noise for an accurate calibration. When calibration is complete, the calibration
result is written to the 16-bit ADC2 offset calibration register (ADC2OFC[1:0)].
9.4.9.6 ADC1 Full-Scale System Calibration (SYGCAL1)
The full-scale calibration command corrects ADC1 system gain error. To calibrate, apply a positive full-scale dc
signal to the ADC, wait until the signal is fully settled, and then send the command. When the SYGCAL1
command is sent, the ADC averages 16 readings to reduce conversion noise for an accurate calibration. When
calibration completes, the ADC computes a full-scale calibration where the applied voltage calibrates to a
positive full-scale code value. The computed result is written to the 24-bit offset calibration register (FSCAL[2:0]).
The precalibrated ADC overrange limitation is 106% FSR.
9.4.9.7 ADC2 Full-Scale System Calibration ADC2 (SYGCAL2)
The full-scale system calibration command corrects ADC2 system gain error. To calibrate, apply a positive full-
scale dc signal to ADC2, wait until the signal is fully settled, and then send the command. When the SYGCAL2
command is sent, the ADC averages 16 readings to reduce conversion noise for an accurate calibration. When
calibration is complete, the full-scale calibration is computed so that applied voltage calibrates to positive full
scale. The computed result is written to the ADC2 16-bit, full-scale calibration register (ADC2FSC[1:0]). The
precalibrated ADC overrange limitation is 106% FSR.
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9.4.9.8 Calibration Command Procedure
The following steps show the ADC calibration procedure using commands. Make sure that the reference voltage
is stable before calibrating the ADC. Perform offset calibration before full-scale calibration.
1. Enable continuous-conversion mode (ADC1 only).
2. Select the desired gain and reference voltage of the ADC.
3. Choose calibration type:
a. For offset self-calibration, program the ADC1 or ADC2 input multiplexer register to FFh to open all inputs
before sending the calibration command.
b. For system calibration, select the input channel and short the external inputs (offset calibration); or apply
positive full-scale input (full-scale calibration). If performing full-scale calibration, the analog inputs
cannot exceed 106% FSR. Do not exceed the specified absolute or differential PGA input range when
calibrating.
4. Start conversions:
a. If calibrating ADC1, take the START pin high (or send the ADC1 start command).
b. If calibrating ADC2, send the ADC2 start command.
5. Send the desired calibration command. When the calibration command is received, calibration is started,
and for ADC1, DRDY is driven high. Keep CS and SCLK low during the calibration time. The calibration time
depends on the data rate and digital filter mode, as shown in 表9-28 for ADC1 and 表9-29 for ADC2.
For ADC1, DRDY is driven low when calibration is complete. The new offset or full-scale calibration values are
written to the calibration registers. New conversion data are now ready using the new calibration coefficients.
For ADC2, the end of calibration is not indicated by DRDY. Instead, wait for the time shown in 表 9-29 before
reading ADC2 data.
表9-28. ADC1 Calibration Time (ms)
FILTER MODE (1)
DATA RATE
(SPS)
SINC1
6801
3401
1701
1021
850.7
340.9
284.1
170.8
43.27
14.93
7.845
4.302
3.123
—
SINC2
7601
3801
1901
1141
951.0
380.9
317.7
190.9
48.43
16.72
8.816
4.858
3.534
—
SINC3
8401
4201
2101
1261
1051
421.0
350.9
210.9
53.42
18.40
9.643
5.276
3.815
—
SINC4
9201
4601
2300
1381
1151
460.9
384.4
230.8
58.41
20.07
10.48
5.692
4.095
—
SINC5
FIR
2.5
6805
3405
1705
—
—
5
10
—
16.6
20
—
—
854.5
—
50
—
—
—
—
—
—
—
—
—
—
—
—
60
—
100
—
400
—
1200
2400
4800
7200
14400
19200
38400
—
—
—
—
1.941
1.490
0.812
—
—
—
—
—
—
—
—
(1) fCLK = 7.3728 MHz. CHOP disabled.
表9-29. ADC2 Calibration Time
DATA RATE (SPS)
ADC2 CALIBRATION TIME (ms)(1)
10
1742
212
100
400
800
54.6
28.3
(1) fCLK = 7.3728 MHz.
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9.4.9.9 User Calibration Procedure
The user calibration procedure is similar to the calibration command procedure, except the user computes the
calibration coefficients and writes the corresponding values to the calibration registers. Before starting user
calibration, preset the ADC1 offset and full-scale registers to 000000h and 400000h, respectively.
For ADC2, preset the offset and full-scale registers to 0000h and 4000h, respectively.
For offset calibration, short the ADC inputs or system inputs and average the conversions (averaging reduces
noise for a more accurate calibration). Write the average value to the offset calibration registers. The ADC
subtracts the value from the conversion result.
For full-scale calibration, apply a dc calibration voltage that is less than positive full scale to avoid clipped codes
(VIN < +FSR), and average the conversions to reduce noise for a more accurate calibration. Full-scale calibration
is computed as shown in 方程式23:
Full-Scale Calibration = (Expected Code Value / Actual Code Value) × NF
(23)
where
• NF = Normalization Factor = 400000h for ADC1, or 4000h for ADC2
If the actual code is higher than the expected value, the calculated calibration value is less than 400000h
(4000h) and the ADC gain is subsequently reduced. Write the calibration value to the full-scale register.
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9.4.10 Reset
The ADC is reset in one of three ways:
1) Power-on reset
2) RESET/PWDN pin
3) RESET command
When the ADC is reset, the device registers reset to default values and the analog-to-digital conversion cycles
restart. After reset, the RESET bit of the status byte (bit 0) and of the power register (bit 4) are set to 1 to
indicate reset has occurred. Set the RESET register bit to 0 to clear the reset flag. If the RESET bit is then set
after clearing the bit, a new reset has occurred.
9.4.10.1 Power-On Reset (POR)
After the power supplies are turned on, the ADC remains in reset until VDVDD, the internal LDO output (BYPASS
pin voltage), and the combined (VAVDD – VAVSS) power supply voltage have exceeded their respective POR
voltage thresholds. 图 9-52 shows the POR sequence. When the power supplies have crossed the voltage
thresholds, the ADC is operational 65536 fCLK cycles later (9 ms, typical). Note the 1-µF capacitor connected to
the BYPASS pin requires charging at power-on, and as a result, can delay when the ADC is operational. Wait at
least 9 ms after the power supplies have fully stabilized before beginning ADC communication.
VDVDD
VDIGITAL_POR
VAVDD - VAVSS
VANALOG_POR
fCLK
Internal Reset
ADC Reset
ADC Operational
td(POROP)
Set RESET bit of status byte
(bit 0 of data byte 1)
Set RESET, bit4 of POWER
(register address 01h )
图9-52. Power-On Reset
表9-30. POR Characteristics
PARAMETER
TEST CONDITIONS
VDVDD and VBYPASS
AVDD –VAVSS
TYP
1
UNIT
V
VDIGITAL_POR
VANALOG_POR
Digital power supply POR threshold
Analog power supply POR threshold
3.5
V
V
Propagation delay from last POR supply threshold
to ADC operational
(1)
td(POROP)
65536
tCLK
(1) tCLK = 1 / fCLK
.
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9.4.10.2 RESET/PWDN Pin
Reset the ADC by taking the RESET/PWDN pin low for a minimum four fCLK cycles, and then returning the pin
high, as shown in 图 9-53. Holding the RESET/PWDN pin low for longer than 65536 fCLK cycles (9 ms) engages
power-down mode. As depicted in the diagram, after the RESET/PWDN pin is taken high, the delay time shown
in 表9-31 is required before sending the first serial interface command.
Set RESET bit of status byte
(bit 0)
Set RESET bit 4 of POWER
(register address 01h )
th(RSTL)
RESET/PWDN
Serial
Command
Serial Interface
th(RSTCM)
图9-53. RESET/PWDN Pin Timing
表9-31. RESET/PWDN Pin Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
4
UNIT
RESET/PWDN low for reset: hold time
RESET/PWDN low for power down: hold time
(1)
th(RSTL)
tCLK
65536
8
RESET/PWDN high to serial command: hold time After reset
th(RSTCM)
tCLK
RESET/PWDN high to serial command: hold time After exiting power down
65536
(1) tCLK = 1 / fCLK
.
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9.4.10.3 Reset by Command
Reset the ADC by using the reset command (opcode = 06h or 07h). Toggle CS high first to make sure the serial
interface resets before sending the command. For applications that tie CS low, see the Serial Interface Autoreset
section for information on how to reset the serial interface. After sending the reset command, provide an 8-fCLK
-
cycle delay before sending the next command, as shown in 图9-54 and 表9-32.
Set RESET bit of status byte
(bit 0)
Set RESET bit 4 of POWER
(register address 01h )
Serial
Command
RESET
Command
Next
Command
th(CMCM)
图9-54. RESET Command Timing
表9-32. RESET Command Timing Requirements
PARAMETER
MIN
UNIT(1)
th(CMCM)
RESET command to next command: hold time
8
tCLK
(1) tCLK = 1 / fCLK
.
9.4.11 Power-Down Mode
Power down the ADC by holding the RESET/PWDN pin low. To reset the ADC without engaging power-down
mode, pulse the pin low for less than 65536 clock cycles. In power-down mode, the ADC (including the internal
reference) is shutdown. The internal low-dropout regulator (LDO) output to the BYPASS pin remains on, typically
drawing 25-µA idle current from the DVDD power supply. To exit power-down mode, take the RESET/PWDN pin
high.
While in power-down mode, the ADC digital outputs remain driven and the analog inputs and reference inputs
are high impedance. Maintain the digital inputs at VIH or VIL levels (do not float the digital inputs). When power-
down mode is exited, the ADC resets, resulting in the registers resetting to default values. Wait the required
65536 fCLK cycles (9 ms) before first communication to the ADC. Make sure to allow time for the internal
reference to settle before starting the first conversion.
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9.4.12 Chop Mode
The device uses a chopper-stabilized PGA and modulator in order to provide very low input voltage offset drift
(VOS/dT). However, because of nonidealities arising from chopper stabilization, a small amount of offset voltage
drift sometimes remains. ADC1 incorporates a global chop option to reduce the offset voltage and offset voltage
drift to very low levels. When Chop is enabled, the ADC performs two internal conversions to cancel the input
offset voltage. The first conversion is taken with normal input polarity. The ADC reverses the internal input
polarity for the second conversion. The difference of the two conversions is computed to yield the final corrected
result with the offset voltage removed. See 图9-55. The ADC internal offset voltage is modeled as VOFS
.
CHOP[1:0] bits 5:4 of MODE0
(register address = 03h)
00: Chop off
01: Chop on
10: IDAC rotation
Chop Switch
11: Chop on and IDAC rotation
VOFS
AIN0
VINP
-
+
Digital
Filter
Input
MUX
Chop
Control
C
A D
Conversion Output
ADC
PGA
VINN
AINCOM
图9-55. ADC1 Chop Block Diagram
The following is the internal Chop mode sequence.
Internal Conversion 1: VAINP - VAINN - VOFS => First conversion withheld
Internal Conversion 2: VAINN - VAINP - VOFS => Output result 1 = (Conversion 1 - Conversion 2) /2 = VAINP - VAINN
Internal Conversion 3: VAINP - VAINN - VOFS => Output result 2 = (Conversion 3 - Conversion 2) /2 = VAINP - VAINN
Internal Conversion 4: VAINN - VAINP - VOFS => Output result 3 = (Conversion 3 - Conversion 4) /2 = VAINP - VAINN
The internal chop sequence repeats for all successive conversions.
As a result of the delay required by the digital filter to settle after reversing the inputs, the chop-mode data rate is
less than the nominal data rate, depending on the digital filter order and programmed settling delay.
Nevertheless, if the data rate currently in use has 50-Hz and 60-Hz frequency response nulls, the null
frequencies remain unchanged. Chop mode also reduces the ADC noise by a factor of 1.4 because of the
averaging of two conversions. In some cases, it is necessary to increase the time delay parameter, DELAY[3:0],
to allow for settling of external components.
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9.5 Programming
Commands are used to access the configuration and data registers and also to control the ADC. Many of the
ADC commands are stand-alone (that is, single-byte). The register write and register read commands, however,
are multibyte, consisting of two opcode bytes plus the register data byte or bytes. The commands are listed in 表
9-33.
Commands can be sent at any time, either during a conversion or while conversions are stopped. However, if
register read/write commands are in progress when conversion data are ready, the ADC blocks loading of
conversion data to the output shift register. The CS input pin can be taken high between commands; or held low
between consecutive commands. CS must stay low for the entirety of the command sequence. Complete the
command, or terminate before command completion by taking CS high. Only send the commands that are listed
in 表9-33.
表9-33. ADC Commands
COMMAND MNEMONIC
NOP
COMMAND TYPE
NOP
DESCRIPTION
OPCODE 1 BYTE
OPCODE 2 BYTE
No operation
0000 0000 (00h)
RESET
Reset the ADC
0000 011x (06h or 07h)(1)
0000 100x (08h or 09h)(1)
0000 101x (0Ah or 0Bh)(1)
0000 110x (0Ch or 0Dh)(1)
0000 111x (0Eh or 0Fh)(1)
0001 001x (12h or 13h)(1)
0001 010x (14h or 15h)(1)
START1
Start ADC1 conversions
Stop ADC1 conversions
Start ADC2 conversions
Stop ADC2 conversions
Read ADC1 data
STOP1
Control
START2
STOP2
RDATA1
Conversion data read
RDATA2
Read ADC2 data
ADC1 system offset
calibration
SYOCAL1
SYGCAL1
SFOCAL1
SYOCAL2
SYGCAL2
SFOCAL2
0001 0110 (16h)
0001 0111 (17h)
0001 1001 (19h)
0001 1011 (1Bh)
0001 1100 (1Ch)
0001 1110 (1Eh)
ADC1 system gain
calibration
ADC1 self offset
calibration
Calibration
ADC2 system offset
calibration
ADC2 system gain
calibration
ADC2 self offset
calibration
RREG
WREG
Read registers
Write registers
001r rrrr (20h+000r rrrr)(2) 000n nnnn(3)
010r rrrr (40h+000r rrrr)(2) 000n nnnn(3)
Register data read and
write
(1) x = don't care.
(2) r rrrr = register address.
(3) n nnnn = number of registers to read or write minus 1.
9.5.1 NOP Command
The NOP command sends a no operation command to the device. The NOP command opcode is 00h. Hold the
DIN pin low for the NOP command.
9.5.2 RESET Command
The RESET command resets the ADC operation and resets the device registers to default. See the Reset by
Command section.
9.5.3 START1, STOP1, START2, STOP2 Commands
These commands start and stop the conversions of ADC1 and ADC2. See the Conversion Control section.
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9.5.4 RDATA1, RDATA2 Commands
These commands are used to read ADC1 or ADC2 conversion data from the respective data holding buffers.
See the Read Conversion Data section for more details.
9.5.5 SYOCAL1, SYGCAL1, SFOCAL1, SYOCAL2, SYGCAL2, SFOCAL2 Commands
These commands are used to calibrate ADC1 or ADC2. See the Calibration section.
9.5.6 RREG Command
Use the RREG command to read the device register data. Read the register data one register at a time, or read
as a block of register data. The starting register address is any register in the map. The RREG opcode consists
of two bytes. The first byte specifies the starting register address: 001r rrrr: where r rrrr is the starting register
address. The second opcode byte is the number of registers to read (minus 1): 000n nnnn: where n nnnn is the
number of registers to read minus 1.
After the read command is sent, the ADC responds with one or more register data bytes, most significant bit first.
If the byte count exceeds the last register address, the ADC begins to output zero data (the address pointer
does not wrap). During the register read operation, if ADC1 data are ready, the conversion data are not loaded to
the output shift register to avoid data contention. However, the conversion data can be retrieved later by the
RDATA1 command. After the register read command has been started, further commands are disabled until one
of the following conditions:
1) The read operation is completed.
2) The read operation is terminated by taking CS high.
3) The read operation is terminated by a serial interface autoreset.
4) The ADC is reset by toggling the RESET/PWDN pin.
图 9-56 depicts a two-register read operation example. As shown, the opcodes required to read data from two
registers starting at register MODE2 (address = 05h) are: OPCODE 1 = 25h and OPCODE 2 = 01h. Keep the
DIN input low after the two opcode bytes are sent.
(Aa)
CS
1
9
17
25
SCLK
DOUT/DRDY
DON‘T CARE
DON‘T CARE
REG DATA 1
REG DATA 2
DIN
OPCODE 1
OPCODE 2
A. CS can be set high or kept low between commands. If kept low, the command must be completed.
图9-56. Read Register Sequence
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9.5.7 WREG Command
Use the WREG command to write the device register data. The register data are written one register at a time or
as a block of register data. The starting register address is any register in the map.
The WREG opcode consists of two bytes. The first byte specifies the starting register address: 010r rrrr, where r
rrrr is the starting register address The second opcode byte is the number of registers to write (minus one): 000n
nnnn, where n nnnn is the number of registers to write minus one. The following byte (or bytes) is the register
data, most significant bit first. If the byte count exceeds the last register address, the ADC ignores the data (the
address pointer does not wrap). Writing new data to certain registers results in a reset of ADC1 or ADC2
conversions, as specified in the ADC restart column in the Register Maps. The previous conversion data are
cleared at restart; therefore, read the data before the register write operation. After the register write command
has been started, further commands are disabled until one of these conditions occur:
1) The write operation is completed.
2) The write operation is terminated by taking CS high.
3) The write operation is terminated by a serial interface auto-reset
4) The ADC is reset by toggling the RESET/PWDN pin.
图 9-57 depicts a two-register write operation example. As shown, the required opcodes to write data to two
registers starting at register MODE2 (address = 05h) are: OPCODE 1 = 45h and OPCODE 2 = 01h.
(A)
CS
1
9
17
25
SCLK
DOUT/DRDY
DIN
DON‘T CARE
DON‘T CARE
DON‘T CARE
DON‘T CARE
OPCODE 1
OPCODE 2
REG DATA 1
REG DATA 2
A. Between commands, either set CS high or keep CS low. If CS is kept low, the command must be completed.
图9-57. Write Register Sequence
The MODE2 and INPMUX registers are modified. Typically, register changes take effect immediately after the
data are written. However, if the registers are part of a group, then the data are written only after all data for the
grouped registers in the write block have been sent. In this example, data for MODE2 and INPMUX are written
only after the data for INPMUX are sent. See the Register Maps section for those registers that are grouped
when writing register data.
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9.6 Register Maps
The ADS1262 register map consists of 21, 8-bit registers. The ADS1263 has six additional registers totaling 27
registers. Registers with addresses 15h through 1Ah apply exclusively to the ADC2. Collectively, these registers
are used to configure and control the ADC to the desired mode of operation. Access the registers through the
serial interface by using the RREG and WREG register-read and -write commands. At power-on or reset, the
registers default to their initial settings, as shown in the Default column of 表9-34.
Writing new data to certain registers results in restart of conversions that are in progress. The registers that
result in conversion restart (either ADC1 or ADC2) are shown in the ADC Restart column in 表 9-34. The device
drives the DRDY output high when ADC1 restarts. Additionally, data can be written as a block to multiple
registers using a single command. If data are written as a block, the data of certain registers take effect
immediately as the data are shifted in, while the data of other registers are buffered and take effect when the
command is fully completed. The registers that update as a group are identified in the Group Update column in
表 9-34. The group update registers that pertain to ADC1 operation are labeled Group1. The group update
registers that pertain to ADC2 operation are labeled Group2. Update registers as a group to minimize the ADC
recovery time after a configuration change. If the write command is terminated before completion, the data of
group registers are not saved.
表9-34. Register Map
ADC
GROUP
ADDR
00h
REGISTER
ID
DEFAULT RESTART UPDATE
BIT 7
BIT 6
DEV_ID[2:0]
0
BIT 5
BIT 4
BIT 3
BIT 2
REV_ID[4:0]
0
BIT 1
BIT 0
xxh
11h
01h
POWER
0
0
0
0
RESET
0
0
VBIAS
INTREF
TIME
OUT
02h
03h
INTERFACE
MODE0
05h
0
STATUS
CRC[1:0]
RUN
MODE
00h
ADC1
Group1
REFREV
BYPASS
CHOP[1:0]
DELAY[3:0]
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
MODE1
MODE2
80h
04h
01h
00h
00h
00h
00h
00h
40h
BBh
00h
00h
00h
00h
00h
00h
00h
00h
01h
00h
00h
00h
40h
ADC1
ADC1
ADC1
Group1
Group1
Group1
FILTER[2:0]
SBADC SBPOL
SBMAG[2:0]
DR[3:0]
GAIN[2:0]
INPMUX
MUXP[3:0]
MUXN[3:0]
OFCAL0
OFC[7:0]
OFC[15:8]
OFC[23:16]
FSC[7:0]
OFCAL1
OFCAL2
FSCAL0
FSCAL1
FSC[15:8]
FSC[23:16]
FSCAL2
IDACMUX
IDACMAG
REFMUX
TDACP
ADC1
ADC1
ADC1
Group1
Group1
Group1
MUX2[3:0]
MAG2[3:0]
MUX1[3:0]
MAG1[3:0]
0
0
RMUXP[2:0]
RMUXN[2:0]
MAGP[4:0]
MAGN[4:0]
OUTP
OUTN
0
0
0
0
TDACN
GPIOCON
GPIODIR
GPIODAT
ADC2CFG
ADC2MUX
ADC2OFC0
ADC2OFC1
ADC2FSC0
ADC2FSC1
CON[7:0]
DIR[7:0]
DAT[7:0]
ADC2
ADC2
Group2
Group2
DR2[1:0]
REF2[2:0]
GAIN2[2:0]
MUXN2[3:0]
MUXP2[3:0]
OFC2[7:0]
OFC2[15:8]
FSC2[7:0]
FSC2[15:8]
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9.6.1 Device Identification Register (address = 00h) [reset = x]
图9-58. Device Identification Register (ID)
7
6
5
4
3
2
1
0
DEV_ID[2:0]
REV_ID[4:0]
NOTE: Reset values are device dependent
表9-35. Device Identification Register (ID) Field Descriptions
Bit
Field
Type
Reset
Description
7:5
DEV_ID[2:0]
R
x
Device ID.
000: ADS1262
001: ADS1263
4:0
REV_ID[4:0]
R
x
Revision ID
Note: the chip revision ID can change without notification
9.6.2 Power Register (address = 01h) [reset = 11h]
图9-59. Power Register (POWER)
7
6
5
4
3
2
1
0
RESERVED
R-0h
RESET
R/W-1h
RESERVED
R-0h
VBIAS
R/W-0h
INTREF
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-36. Power Register (POWER) Field Descriptions
Bit
Field
Type
Reset
Description
7:5
RESERVED
R
0h
Reserved
Always write 000
4
RESET
R/W
1h
Reset Indicator
Indicates ADC reset has occurred. Clear this bit to detect the
next device reset.
0: No new reset occurred
1: New reset has occurred (default)
3:2
1
RESERVED
VBIAS
R
0h
0h
Reserved
Always write 00
R/W
Level Shift Voltage Enable
Enables the internal level shift voltage to the AINCOM pin.
VBIAS = (VAVDD + VAVSS)/2
0: Disabled (default)
1: VBIAS enabled
0
INTREF
R/W
1h
Internal Reference Enable
Enables the 2.5 V internal voltage reference. Note the IDAC and
temperature sensor require the internal voltage reference.
0: Disabled
1: Internal reference enabled (default)
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9.6.3 Interface Register (address = 02h) [reset = 05h]
图9-60. Interface Register (INTERFACE)
7
6
5
4
3
2
1
0
RESERVED
R-0h
TIMEOUT
R/W-0h
STATUS
R-1h
CRC[1:0]
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-37. Interface Register (INTERFACE) Field Descriptions
Bit
Field
Type
Reset
Description
7:4
RESERVED
R
0h
Reserved
Always write 00h
3
2
TIMEOUT
STATUS
R/W
R/W
0h
1h
Serial Interface Time-Out Enable
Enables the serial interface automatic time-out mode
0: Disabled (default)
1: Enable the interface automatic time-out
Status Byte Enable
Enables the inclusion of the status byte during conversion data
read-back
0: Disabled
1: Status byte included during conversion data read-back
(default)
1:0
CRC[1:0]
R/W
1h
Checksum Byte Enable
Enables the inclusion of the checksum byte during conversion
data read-back
00: Checksum byte disabled
01: Enable Checksum byte in Checksum mode during
conversion data read-back (default)
10: Enable Checksum byte in CRC mode during conversion
data read-back
11: Reserved
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9.6.4 Mode0 Register (address = 03h) [reset = 00h]
图9-61. Mode0 Register (MODE0)
7
6
5
4
3
2
1
0
REFREV
R/W-0h
RUNMODE
R/W-0h
CHOP[1:0]
R/W-0h
DELAY[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-38. Mode0 Register (MODE0) Field Descriptions
Bit
Field
Type
Reset
Description
7
REFREV
R/W
0h
Reference Mux Polarity Reversal
Reverses the ADC1 reference multiplexer output polarity
0: Normal polarity of reference multiplexer output (default)
1: Reverse polarity of reference multiplexer output
6
RUNMODE
CHOP[1:0]
R/W
R/W
0h
0h
ADC Conversion Run Mode
Selects the ADC conversion (run) mode
0: Continuous conversion (default)
1: Pulse conversion (one shot conversion)
5:4
Chop Mode Enable
Enables the ADC chop and IDAC rotation options
00: Input chop and IDAC rotation disabled (default)
01: Input chop enabled
10: IDAC rotation enabled
11: Input chop and IDAC rotation enabled
3:0
DELAY[3:0]
R/W
0h
Conversion Delay
Provides additional delay from conversion start to the beginning
of the actual conversion
0000: no delay (default)
0001: 8.7 µs
0010: 17 µs
0011: 35 µs
0100: 69 µs
0101: 139 µs
0110: 278 µs
0111: 555 µs
1000: 1.1 ms
1001: 2.2 ms
1010: 4.4 ms
1011: 8.8 ms
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
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9.6.5 Mode1 Register (address = 04h) [reset = 80h]
图9-62. Mode1 Register (MODE1)
7
6
5
4
3
2
1
0
FILTER[2:0]
R/W-4h
SBADC
R/W-0h
SBPOL
R/W-0h
SBMAG[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-39. Mode1 Register (MODE1) Field Descriptions
Bit
Field
Type
Reset
Description
7:5
FILTER[2:0]
R/W
4h
Digital Filter
Configures the ADC digital filter
000: Sinc1 mode
001: Sinc2 mode
010: Sinc3 mode
011: Sinc4 mode
100: FIR mode (default)
101: Reserved
110: Reserved
111: Reserved
4
3
SBADC
SBPOL
R/W
R/W
0h
0h
Sensor Bias ADC Connection
Selects the ADC to connect the sensor bias
0: Sensor bias connected to ADC1 mux out (default)
1: Sensor bias connected to ADC2 mux out
Sensor Bias Polarity
Selects the sensor bias for pull-up or pull-down
0: Sensor bias pull-up mode (AINP pulled high, AINN pulled low)
(default)
1: Sensor bias pull-down mode (AINP pulled low, AINN pulled
high)
2:0
SBMAG[2:0]
R/W
0h
Sensor Bias Magnitude
Selects the sensor bias current magnitude or the bias resistor
000: No sensor bias current or resistor (default)
001: 0.5-µA sensor bias current
010: 2-µA sensor bias current
011: 10-µA sensor bias current
100: 50-µA sensor bias current
101: 200-µA sensor bias current
110: 10-MΩresistor
111: Reserved
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9.6.6 Mode2 Register (address = 05h) [reset = 04h]
图9-63. Mode2 Register (MODE2)
7
6
5
4
3
2
1
0
BYPASS
R/W-0h
GAIN[2:0]
R/W-0h
DR[3:0]
R/W-4h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-40. Mode2 Register (MODE2) Field Descriptions
Bit
Field
Type
Reset
Description
7
BYPASS
R/W
0h
PGA Bypass Mode
Selects PGA bypass mode
0: PGA enabled (default)
1: PGA bypassed
6:4
GAIN[2:0]
R/W
0h
PGA Gain
Selects the PGA gain
000: 1 V/V (default)
001: 2 V/V
010: 4 V/V
011: 8 V/V
100: 16 V/V
101: 32 V/V
110: Reserved
111: Reserved
3:0
DR[3:0]
R/W
4h
Data Rate
Selects the ADC data rate. In FIR filter mode, the available data
rates are limited to 2.5, 5, 10 and 20 SPS.
0000: 2.5 SPS
0001: 5 SPS
0010: 10 SPS
0011: 16. 6SPS
0100: 20 SPS (default)
0101: 50 SPS
0110: 60 SPS
0111: 100 SPS
1000: 400 SPS
1001: 1200 SPS
1010: 2400 SPS
1011: 4800 SPS
1100: 7200 SPS
1101: 14400 SPS
1110: 19200 SPS
1111: 38400 SPS
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9.6.7 Input Multiplexer Register (address = 06h) [reset = 01h]
图9-64. Input Multiplexer Register (INPMUX)
7
6
5
4
3
2
1
0
MUXP[3:0]
R/W-0h
MUXN[3:0]
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-41. Input Multiplexer Register (INPMUX) Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUXP[3:0]
R/W
0h
Positive Input Multiplexer
Selects the positive input multiplexer.
0000: AIN0 (default)
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: Temperature sensor monitor positive
1100: Analog power supply monitor positive
1101: Digital power supply monitor positive
1110: TDAC test signal positive
1111: Float (open connection)
3:0
MUXN[3:0]
R/W
1h
Negative Input Multiplexer
Selects the negative input multiplexer.
0000: AIN0
0001: AIN1 (default)
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: Temperature sensor monitor negative
1100: Analog power supply monitor negative
1101: Digital power supply monitor negative
1110: TDAC test signal negative
1111: Float (open connection)
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9.6.8 Offset Calibration Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
图9-65. Offset Calibration Registers (OFCAL0, OFCAL1, OFCAL2) 24-bit, 3 Rows
7
6
5
4
3
2
1
0
8
OFC[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
9
OFC[15:8]
R/W-00h
17
16
OFC[23:16]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-42. Offset Calibration Registers (OFCAL0, OFCAL1, OFCAL2) Field Descriptions
Bit
Field
Type
Reset
Description
23:0
OFC[23:0]
R/W
000000h
Offset Calibration
Three registers compose the 24-bit offset calibration word. The
24-bit word is twos complement format, and is internally left-
shifted to align with the 32-bit conversion result. The ADC
subtracts the register value from the 32-bit conversion result
before the full-scale operation.
9.6.9 Full-Scale Calibration Registers (address = 0Ah, 0Bh, 0Ch) [reset = 40h, 00h, 00h]
图9-66. Full-Scale Calibration Registers (FSCAL0, FSCAL1, FSCAL2) 24-bit, 3 Rows
7
6
5
4
3
2
1
0
8
FSCAL[7:0]
R/W-00h
15
23
14
22
13
21
12
20
11
19
10
18
9
FSCAL[15:8]
R/W-00h
17
16
FSCAL[23:16]
R/W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-43. Full-Scale Calibration Registers (FSCAL0, FSCAL1, FSCAL2) Field Descriptions
Bit
Field
Type
Reset
Description
23:0
FSCAL[23:0]
R/W
400000h
Full-Scale Calibration
Three 8-bit registers compose the 24-bit full scale calibration
word. The 24-bit word format is straight binary. The ADC divides
the 24-bit value by 400000h to derive the gain coefficient. The
ADC multiplies the gain coefficient by the 32-bit conversion
result after the offset operation.
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9.6.10 IDACMUX Register (address = 0Dh) [reset = BBh]
图9-67. IDAC Multiplexer Register (IDACMUX)
7
6
5
4
3
2
1
0
MUX2[3:0]
R/W-Bh
MUX1[3:0]
R/W-Bh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-44. IDAC Multiplexer Register (IDACMUX) Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUX2[3:0]
R/W
Bh
IDAC2 Output Multiplexer
Selects the analog input pin to connect IDAC2
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: No Connection (default)
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
3:0
MUX1[3:0]
R/W
Bh
IDAC1 Output Multiplexer
Selects the analog input pin to connect IDAC1
0000: AIN0
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: No Connection (default)
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
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9.6.11 IDACMAG Register (address = 0Eh) [reset = 00h]
图9-68. IDAC Magnitude Register (IDACMAG)
7
6
5
4
3
2
1
0
MAG2[3:0]
R/W-0h
MAG1[3:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-45. IDAC Magnitude (IDACMAG) Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MAG2[3:0]
R/W
0h
IDAC2 Current Magnitude
Selects the current values of IDAC2
0000: off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
3:0
MAG1[3:0]
R/W
0h
IDAC1 Current Magnitude
Selects the current values of IDAC1
0000: off (default)
0001: 50 µA
0010: 100 µA
0011: 250 µA
0100: 500 µA
0101: 750 µA
0110: 1000 µA
0111: 1500 µA
1000: 2000 µA
1001: 2500 µA
1010: 3000 µA
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
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9.6.12 REFMUX Register (address = 0Fh) [reset = 00h]
图9-69. Reference Multiplexer Register (REFMUX)
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
RMUXP[2:0]
R/W-0h
RMUXN[2:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-46. Reference Multiplexer Register (REFMUX) Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Reserved
R
0h
Reserved
Always write 0h
5:3
RMUXP[2:0]
R/W
0h
Reference Positive Input
Selects the positive reference input
000: Internal 2.5 V reference - P (default)
001: External AIN0
010: External AIN2
011: External AIN4
100: Internal analog supply (VAVDD
101: Reserved
)
110: Reserved
111: Reserved
2:0
RMUXN[2:0]
R/W
0h
Reference Negative Input
Selects the negative reference input
000: Internal 2.5 V reference - N (default)
001: External AIN1
010: External AIN3
011: External AIN5
100: Internal analog supply (VAVSS
101: Reserved
)
110: Reserved
111: Reserved
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9.6.13 TDACP Control Register (address = 10h) [reset = 00h]
图9-70. TDACP Control Register (TDACP)
7
6
5
4
3
2
1
0
OUTP
R/W-0h
RESERVED
R-0h
MAGP[4:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-47. TDACP Output Register (TDACP) Field Descriptions
Bit
Field
Type
Reset
Description
7
OUTP
R/W
0h
TDACP Output Connection
Connects TDACP output to pin AIN6
0: No connection
1: TDACP output connected to pin AIN6
6:5
4:0
Reserved
R
0h
0h
Reserved
Always write 0
MAGP[4:0]
R/W
MAGP Output Magnitude
Select the TDACP output magnitude. The TDAC output voltages
are ideal and are with respect to VAVSS
01001: 4.5 V
01000: 3.5 V
00111: 3 V
00110: 2.75 V
00101: 2.625 V
00100: 2.5625 V
00011: 2.53125 V
00010: 2.515625 V
00001: 2.5078125 V
00000: 2.5 V
10001: 2.4921875 V
10010: 2.484375 V
10011: 2.46875 V
10100: 2.4375 V
10101: 2.375 V
10110: 2.25 V
10111: 2 V
11000: 1.5 V
11001: 0.5 V
Remaining codes are reserved
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9.6.14 TDACN Control Register (address = 11h) [reset = 00h]
图9-71. TDACN Control Register (TDACN)
7
6
5
4
3
2
1
0
OUTN
R/W-0h
RESERVED
R-0h
MAGN[4:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-48. TDAC Negative Output Register (TDACN) Field Descriptions
Bit
Field
Type
Reset
Description
7
OUTN
R/W
0h
TDACN Output Connection
Connects TDACN output to pin AIN7
0: No external connection
1: TDACN output connected to pin AIN7
6:5
4:0
Reserved
R
0h
0h
Reserved
Always write 0h
MAGN[4:0]
R/W
TDACN Output Magnitude
Select the TDACN output magnitude. The TDAC output voltages
are ideal and are with respect to VAVSS
01001: 4.5 V
01000: 3.5 V
00111: 3 V
00110: 2.75 V
00101: 2.625 V
00100: 2.5625 V
00011: 2.53125 V
00010: 2.515625 V
00001: 2.5078125 V
00000: 2.5 V
10001: 2.4921875 V
10010: 2.484375 V
10011: 2.46875 V
10100: 2.4375 V
10101: 2.375 V
10110: 2.25 V
10111: 2 V
11000: 1.5 V
11001: 0.5 V
Remaining codes are reserved
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9.6.15 GPIO Connection Register (address = 12h) [reset = 00h]
图9-72. GPIO Connection Register (GPIOCON)
7
6
5
4
3
2
1
0
CON[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-49. GPIO Connection Register (GPIOCON) Field Descriptions
Bit
Field
Type
Reset
Description
0
CON[0]
R/W
0h
GPIO[0] Pin Connection
Connects GPIO[0] to analog input pin AIN3
0: GPIO[0] not connected to AIN3 (default)
1: GPIO[0] connected to AIN3
1
2
3
4
5
6
7
CON[1]
CON[2]
CON[3]
CON[4]
CON[5]
CON[6]
CON[7]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
GPIO[1] Pin Connection
Connects GPIO[1] to analog input pin AIN4
0: GPIO[1] not connected to AIN4 (default)
1: GPIO[1] connected to AIN4
GPIO[2] Pin Connection
Connects GPIO[2] to analog input pin AIN5
0: GPIO[2] not connected to AIN5 (default)
1: GPIO[2] connected to AIN5
GPIO[3] Pin Connection
Connects GPIO[3] to analog input pin AIN6
0: GPIO[3] not connected to AIN6 (default)
1: GPIO[3] connected to AIN6
GPIO[4] Pin Connection
Connects GPIO[4] to analog input pin AIN7
0: GPIO[4] not connected to AIN7 (default)
1: GPIO[4] connected to AIN7
GPIO[5] Pin Connection
Connects GPIO[5] to analog input pin AIN8
0: GPIO[5] not connected to AIN8 (default)
1: GPIO[5] connected to AIN8
GPIO[6] Pin Connection
Connects GPIO[6] to analog input pin AIN9
0: GPIO[6] not connected to AIN9 (default)
1: GPIO[6] connected to AIN9
GPIO[7] Pin Connection
Connects GPIO[7] to analog input pin AINCOM
0: GPIO[7] not connected to AINCOM (default)
1: GPIO[7] connected to AINCOM
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9.6.16 GPIO Direction Register (address = 13h) [reset = 00h]
图9-73. GPIO Direction Register (GPIODIR)
7
6
5
4
3
2
1
0
DIR[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-50. GPIO Direction Register (GPIODIR) Field Descriptions
Bit
Field
Type
Reset
Description
0
DIR[0]
R/W
0h
GPIO[0] Pin Direction
Configures GPIO[0] as a GPIO input or GPIO output
0: GPIO[0] is an output (default)
1: GPIO[0] is an input
1
2
3
4
5
6
7
DIR[1]
DIR[2]
DIR[3]
DIR[4]
DIR[5]
DIR[6]
DIR[7]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
GPIO[1] Pin Direction
Configures GPIO[1] as a GPIO input or GPIO output
0: GPIO[1] is an output (default)
1: GPIO[1] is an input
GPIO[2] Pin Direction
Configures GPIO[2] as a GPIO input or GPIO output
0: GPIO[2] is an output (default)
1: GPIO[2] is an input
GPIO[3] Pin Direction
Configures GPIO[3] as a GPIO input or GPIO output
0: GPIO[3] is an output (default)
1: GPIO[3] is an input
GPIO[4] Pin Direction
Configures GPIO[4] as a GPIO input or GPIO output
0: GPIO[4] is an output (default)
1: GPIO[4] is an input
GPIO[5] Pin Direction
Configures GPIO[5] as a GPIO input or GPIO output
0: GPIO[5] is an output (default)
1: GPIO[5] is an input
GPIO[6] Pin Direction
Configures GPIO[6] as a GPIO input or GPIO output
0: GPIO[6] is an output (default)
1: GPIO[6] is an input
GPIO[7] Pin Direction
Configures GPIO[7] as a GPIO input or GPIO output
0: GPIO[7] is an output (default)
1: GPIO[7] is an input
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9.6.17 GPIO Data Register (address = 14h) [reset = 00h]
图9-74. GPIO Data Register (GPIODAT)
7
6
5
4
3
2
1
0
DAT[7:0]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-51. GPIO Data Register (GPIODAT) Field Descriptions
Bit
Field
Type
Reset
Description
0
DAT[0]
R/W
0h
GPIO[0] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[0] is low
1: GPIO[0] is high
1
2
3
4
5
6
7
DAT[1]
DAT[2]
DAT[3]
DAT[4]
DAT[5]
DAT[6]
DAT[7]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
GPIO[1] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[1] is low
1: GPIO[1] is high
GPIO[2] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[2] is low
1: GPIO[2] is high
GPIO[3] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[3] is low
1: GPIO[3] is high
GPIO[4] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[4] is low
1: GPIO[4] is high
GPIO[5] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[5] is low
1: GPIO[5] is high
GPIO[6] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[6] is low
1: GPIO[6] is high
GPIO[7] Pin Data
Configured as an output, read returns 0b
Configured as an input, write sets the register value only
0: GPIO[7] is low
1: GPIO[7] is high
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9.6.18 ADC2 Configuration Register (address = 15h) [reset = 00h]
图9-75. ADC2 Configuration Register (ADC2CFG)
7
6
5
4
3
2
1
0
DR2[1:0]
R/W-0h
REF2[2:0]
R/W-0h
GAIN2[2:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-52. ADC2 Configuration Register (ADC2CFG) Field Descriptions
Bit
Field
Type
Reset
Description
7:6
DR2[1:0]
R/W
0h
ADC2 Data Rate
These bits select the data rate of ADC2
00: 10 SPS (default)
01: 100 SPS
10: 400 SPS
11: 800 SPS
5:3
REF2[2:0]
R/W
0h
ADC2 Reference Input
Selects the reference inputs of ADC2 as positive and negative
pairs
000: Internal 2.5 V reference, positive and negative (default)
001: External AIN0 and AIN1 pin pairs as positive and negative
010: External AIN2 and AIN3 pin pairs as positive and negative
011: External AIN4 and AIN5 pin pairs as positive and negative
100: Internal VAVDD and VAVSS
101: Reserved
110: Reserved
111: Reserved
2:0
GAIN2[2:0]
R/W
0h
ADC2 Gain
These bits configure the gain of ADC2
000: 1 V/V (default)
001: 2 V/V
010: 4 V/V
011: 8 V/V
100: 16 V/V
101: 32 V/V
110: 64 V/V
111: 128 V/V
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9.6.19 ADC2 Input Multiplexer Register (address = 16h) [reset = 01h]
图9-76. ADC2 Input Multiplexer Register (ADC2MUX)
7
6
5
4
3
2
1
0
MUXP2[3:0]
R/W-0h
MUXN2[3:0]
R/W-1h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-53. ADC2 Input Multiplexer Register (ADC2MUX) Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUXP2[3:0]
R/W
0h
ADC2 Positive Input Multiplexer
Selects the ADC2 positive input
0000: AIN0 (default)
0001: AIN1
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: Temperature sensor monitor positive
1100: Analog power supply monitor positive
1101: Digital power supply monitor positive
1110: TDAC test signal positive
1111: Open connection
3:0
MUXN2[3:0]
R/W
1h
ADC2 Negative Input Multiplexer
Selects the ADC2 negative input
0000: AIN0
0001: AIN1 (default)
0010: AIN2
0011: AIN3
0100: AIN4
0101: AIN5
0110: AIN6
0111: AIN7
1000: AIN8
1001: AIN9
1010: AINCOM
1011: Temperature sensor monitor negative
1100: Analog power supply monitor negative
1101: Digital power supply monitor negative
1110: TDAC test signal negative
1111: Open Connection
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9.6.20 ADC2 Offset Calibration Registers (address = 17h, 18h) [reset = 00h, 00h]
图9-77. ADC2 Offset Calibration Registers (ADC2OFC0, ADC2OFC1) 16-bit, 2 Rows
7
6
5
4
3
2
1
0
8
OFC2[7:0]
R/W-00h
15
14
13
12
11
10
9
OFC2[15:8]
R/W-00h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-54. ADC2 Offset Calibration Registers (ADC2OFC0, ADC2OFC1) Field Descriptions
Bit
Field
Type
Reset
Description
15:0
OFC2[15:0]
R/W
0000h
ADC2 Offset Calibration
Two registers compose the ADC2 16-bit offset calibration word.
The 16-bit word is twos complement format and is internally left-
shifted to align with the ADC2 24-bit conversion result. The ADC
subtracts the register value from the conversion result before
full-scale operation.
9.6.21 ADC2 Full-Scale Calibration Registers (address = 19h, 1Ah) [reset = 00h, 40h]
图9-78. ADC2 Full-Scale Calibration Registers (ADC2FSC0, ADC2FSC1) 16-bit, 2 Rows
7
6
5
4
3
2
1
0
8
FSC2[7:0]
R/W-00h
15
14
13
12
11
10
9
FSC2[15:8]
R/W-40h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表9-55. ADC2 Full-Scale Calibration Registers (ADC2FSC0, ADC2FSC1) Field Descriptions
Bit
Field
Type
Reset
Description
15:0
FSC2[15:0]
R/W
4000h
ADC2 Full-Scale Calibration
Two registers compose the ADC2 16-bit full scale calibration
word. The 16-bit word format is straight binary. The ADC divides
the 16-bit value by 4000h to derive the scale factor for
calibration. After the offset operation, the ADC multiplies the
scale factor by the conversion result.
10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
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10.1 Application Information
10.1.1 Isolated (or Floated) Inputs
Isolated sensors (sensors that are not referenced to the ADC ground) must have a common-mode voltage
established within the specified ADC input range. Level shift the common-mode voltage by external resistor
biasing, by connecting the negative lead to ground (bipolar analog supply), or by connecting to a dc voltage
(unipolar analog supply). Use the level-shift voltage option on the AINCOM pin for this purpose. The 2.5-V
reference output voltage is also used to provide level shifting to other floating sensor inputs.
10.1.2 Single-Ended Measurements
Single-ended measurements typically have one input connected to a fixed potential (ground or dc voltage) and
the other input is the signal. Usually, the fixed connection is the negative input. The positive input is the signal
and is driven above and below the negative input, as depicted in 图 10-1. This is an example of a bipolar signal
because the positive input can swing above and below the negative input. Unipolar signals are those where the
positive signal is equal to or greater than the negative signal. The single-ended signal plus the level-shift voltage
must be within the ADC specified operating range. In single supply configurations (5 V), the level-shift voltage is
usually 2.5 V. This type of input configuration is shown in 图 10-2. For bipolar power supplies (±2.5 V), the
negative voltage can be grounded. This type of input is shown in 图10-3.
Voltage
+ Full Scale Input
VAINP
VAINN
Offset Voltage
Time
- Full Scale Input
图10-1. Single-Ended Input Voltage Diagram
+5 V
AVDD
+
œ
+/- Signal
ADC
AVSS
+
Level Shift Voltage= +2.5 V
图10-2. Single-Ended Input with Level-Shift Voltage
+2.5 V
AVDD
+
œ
+/- Signal
ADC
AVSS
-2.5 V
图10-3. Single-Ended Input with Ground
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10.1.3 Differential Measurements
A differential signal is one where both inputs are driven in symmetric and opposite polarities centered at a
common-mode voltage. Optimally, the common-mode voltage is the midpoint of the ADC input range. The
common-mode voltage plus the signal must always be within the ADC specified operating range to avoid signal
clipping. As shown in 图 10-4, the magnitude of each signal is maximum ½ of the ADC full-scale range. The
maximum differential signal (VAINP – VAINN) is equal to or less than the ADC FSR. For single 5-V operation, the
common-mode voltage is typically equal to mid-supply (2.5 V) in order to use the full ADC input range. This type
of input with single 5-V supply operation is shown in 图 10-5. For bipolar supplies (±2.5 V), the common-mode
voltage of VAINP and VAINN are typically equal to ground potential. This type of input of configuration is shown in
图 10-6. Certain types of differential signals, such as from a bridge circuits, are referenced to ADC ground;
therefore, the common-mode voltage is defined.
Voltage
VAINP
+ ½ Full Scale Input
Common Mode Voltage
Time
- ½ Full Scale Input
VAINN
图10-4. Differential Input Voltage Diagram
+5 V
+ ½ VDIFF
œ
AVDD
ADC
œ
AVSS
Common Mode Voltage = +2.5 V
- ½ VDIFF
图10-5. Differential Input With Common-Mode Level-Shift
+2.5 V
+ ½ VDIFF
œ
AVDD
ADC
œ
AVSS
- ½ VDIFF
-2.5 V
图10-6. Differential Input With Common-Mode Ground
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10.1.4 Input Range
For proper operation of ADC1, the PGA absolute input voltages, VINP and VINN, must always remain within the
valid PGA input range, as shown in 方程式12.
The following example uses 方程式 12 to determine the input-range requirement. For this example, use a
thermocouple (60 mV, maximum differential output) with the negative lead connected to the internal level-shift
voltage (2.5 V). Use a PGA gain of 32 and operate the ADC with a single 5-V power supply. To verify the PGA
input-range requirement, the conditions are:
• VINN = Negative absolute input voltage = 2.5 V
• VINP = Positive absolute input voltage = 2.56 V
• VIN = Differential input voltage = 0.06 V
• VAVDD = 4.75 V (worst-case minimum)
• VAVSS = 0 V
• Gain = 32
Filling in 方程式12 with the values shown gives:
VAVSS + 0.3 + |VIN| · (Gain –1) / 2 < VINP and VINN < VAVDD –0.3 –|VIN| · (Gain –1) / 2
= 0 + 0.3 + 0.06 · (32 –1) / 2 < 2.5 and 2.56 < 4.75 –0.3 –0.06 · (32 –1) / 2
= 1.23 V < 2.5 V and 2.56 V < 3.52 V
The inequality is satisfied, therefore the VINN and VINP absolute input voltages are within the required PGA input
range. Alternatively, measure the PGA output voltages (pins CAPP and CAPN) with a voltmeter to verify that
each PGA output voltage is < VAVDD – 0.3 V and > VAVSS – 0.3 V under the expected minimum and maximum
input conditions, respectively.
The input range requirement of ADC2 is verified in the same way as ADC1. See 方程式 15 for the ADC2 input
range requirements.
10.1.5 Input Filtering
Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process; and
second, to reduce external noise that affects the measurement.
10.1.5.1 Aliasing
As with all ADCs, out-of-band input signals can fold back or alias if not band-limited. Aliasing describes the effect
of input frequencies greater than ½ the sample rate folding back to the bandwidth of interest. An antialias filter
placed at the ADC inputs reduces the magnitude of the aliased frequencies. The ADS1262 and ADS1263
incorporate analog and digital antialiasing filters to attenuate the aliased frequencies. There are two ranges of
aliased frequencies: frequencies greater than ½ of the down-sampled output data rate (Nyquist frequency) and
frequencies occurring at multiples of the modulator sample rate.
Aliasing can occur at frequencies greater than ½ the ADC output data rate. For example, at data rate of 50 SPS,
aliasing occurs at frequencies greater than 25 Hz. The ADC digital filter rejects the aliased frequencies as input
frequency increases. The amount of aliased frequency rejection is given by the filter type and order. 图 10-7
illustrates the frequency response of the sinc filter. Note the sinc4 filter provides the best rejection of aliased
frequencies.
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0
-20
sinc1
sinc2
sinc3
sinc4
-40
-60
-80
-100
-120
-140
-160
0
50 100 150 200 250 300 350 400 450 500 550 600
Frequency (Hz)
D005
图10-7. Frequency Response (50 SPS)
The second band of aliased frequencies occur at the ADC modulator sample rate multiples (fMOD = fCLK / 8 =
921.6 kHz, multiples = 1843.2 kHz and so on). 图 10-8 shows the 38400 SPS frequency response plotted to 1.2
MHz. The response near dc is the signal bandwidth of interest. Observe how the digital filter response repeats
on the sides of the modulator sample rate (921.6 kHz). 图 10-9 shows the repeated response at the modulator
frequency multiples = N · fMOD ± fDR, where N = multiples of fMOD starting at 1, and fDR = data rate frequency.
The digital filter attenuates signal or noise up to where the response repeats. However, signal or noise occurring
at the modulator sample rate is not attenuated by the digital filter and therefore, is aliased to the passband.
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
200
400
600
Frequency (kHz)
800
1000
1200
D014
0
1
2
3
Frequency (MHz)
4
5
6
7
8
D015
图10-8. Frequency Response to 1.2 MHz (38400
图10-9. Frequency Response to 8 MHz
SPS)
(38400 SPS)
图 10-10 illustrates how the frequencies alias near the modulator sample rate frequency. The final figure shows
the aliased frequency rejection provided by an antialias filter. The ADC incorporates an analog antialias filter with
a cutoff frequency of 60 kHz that rejects the aliased frequencies.
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Magnitude
Sensor
Signal
Unwanted
Signals
Unwanted
Signals
Output
Data Rate
fMOD / 2
fMOD
Frequency
Frequency
Frequency
Magnitude
Digital Filter
Aliasing of Unwanted
Signals
Output
Data Rate
fMOD / 2
fMOD
Magnitude
External
Antialiasing Filter
Roll-Off
Output
Data Rate
fMOD / 2
fMOD
图10-10. Alias Effect
Many sensor signals are inherently band-limited; for example, the output of a thermocouple has a limited rate of
change. In this case, the sensor signal does not alias back into the pass band when using a ΔΣ ADC.
However, any noise picked up along the sensor wiring or the application circuitry can potentially alias into the
pass band. Power line-cycle frequency and harmonics are one common noise source. External noise is also
generated from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as
nearby motors and cellular phones. Another noise source exists on the printed circuit board (PCB) in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result. The ADC incorporates a low-pass, antialias filter with a corner frequency of 60 kHz to
reduce the aliased frequencies. The filter consists of the external 4.7-nF PGA output capacitor (CAPP and CAPN
pins) and internal 280-Ωresistors.
Use an input filter to provide increased rejection of aliased noise frequencies and further attenuate possible
strong high-frequency interference signals. For best performance, filter strong interference frequencies at the
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ADC inputs. Ideally, select a low-pass corner frequency that allows frequencies within the desired bandwidth and
attenuates those frequencies outside the desired bandwidth. As a result of the stable and linear dielectric
characteristics, use C0G-type MLCC capacitors in analog signal filters. In applications where high energy
transients can be generated, such as caused by inductive load switching, transient voltage suppressor (TVS)
diodes or external ESD diodes should be used to protect the ADC inputs.
10.1.6 Input Overload
Follow the input overvoltage precautions as outlined in the ESD Diode section. Despite external current limit
provided for the input pins, if an overvoltage condition occurs on an unused channel, the overvoltage channel
may crosstalk to the measurement channel. One solution is to externally clamp the inputs with low-forward
voltage diodes as shown in 图 10-11. The external diodes shunt the overvoltage fault current around the ADC
inputs. Be aware of the reverse leakage current in the external clamp diodes in the application.
IFAULT
+5 V
Schottky
Diode
AVDD
RI-LIM
AINx
ADC
VIN-FAULT > VAVDD + 0.3 V
VIN-FAULT < VAVSS + 0.3 V
Schottky
Diode
AVSS
IFAULT
图10-11. External Diode Voltage Clamp
10.1.7 Unused Inputs and Outputs
To minimize input leakage of the measurement channel, tie the unused input channels to mid-supply (VAVDD
+
VAVSS) / 2. Use the 2.5-V reference output voltage for this purpose if operating with single 5-V supply. Do not
float unused digital inputs. Tie all unused digital inputs to the appropriate levels, VDVDD or VDGND, including when
in power-down mode. Do not float (3-state) the digital inputs to the ADC or excessive power-supply leakage
current can result. If the DRDY output is unused, leave the pin unconnected or connect to an external circuit.
10.1.8 Voltage Reference
For nonratiometric (absolute) measurements where the input signal is not derived from the voltage reference,
either use the internal precision voltage reference, or use an external precision reference. Examples of these
types of measurements come from sensors such as thermocouples, 20-mA transmitters, and accelerometers.
For ratiometric measurements, where the input signal is derived from the voltage reference, reference noise and
drift are canceled by the same ratio of noise and drift within the signal. Ratiometric operation is common with
many types of bridge and RTD measurements. For best noise performance, match the reference filter and input
filter time constants (see the 3-Wire RTD Measurement with Lead-Wire Compensation section for more
information). In general, achieve the best ADC signal-to-noise ratio by using large amplitude signals, a large
reference voltage, and the highest gain setting possible.
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10.1.9 Serial Interface Connections
After power up, take the CS input high to reset the ADC serial interface. CS high resets the serial interface in the
event an unintentional SCLK glitch has occurred during power-on initialization. If CS is tied low, glitches at SCLK
power on can interrupt synchronization to the serial interface and must be avoided. In this case, reset the ADC
using the RESET/PWDN input. The SCLK input is edge sensitive, and therefore must be free of noise, glitches,
and overshoot. Use a terminating resistor located at the SCLK buffer to smooth the edges and reduce overshoot.
Most microcontroller SPI peripherals can operate with the ADC. The interface operates in SPI mode 1, where
CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are updated or changed on SCLK rising
edges; data are latched or read by the host and the ADC on SCLK falling edges. Details of the SPI
communication protocol employed by the device is found in the Timing Requirements: Serial Interface table.
Place a 47-Ω resistor in series with all digital input and output pins (CS, SCLK, DIN, DOUT/DRDY, and DRDY).
The resistors match the characteristic impedance of the PCB trace by source termination, helping reduce
overshoot and ringing.
1
2
3
4
5
6
7
8
9
AIN8
AIN7 28
AIN6 27
AIN9
AINCOM
CAPP
CAPN
AVDD
AVSS
AIN5 26
AIN4 25
4.7 nF
AIN3 24
5 V
AIN2 23
1 ꢀF
0.1 ꢀF
1 ꢀF
3.3 V
AIN1 22
Device
REFOUT
START
AIN0 21
10 kꢁ
47 ꢁ
47 ꢁ
47 ꢁ
47 ꢁ
GPIO
GPIO
RESET/PWDN 20
DVDD 19
GPIO
3.3 V
10 CS
0.1 ꢀF
1 ꢀF
SCLK
11 SCLK
12 DIN
DGND 18
BYPASS 17
XTAL2 16
XTAL1/CLKIN 15
MOSI
47 ꢁ
1 ꢀF
MISO
13 DOUT/DRDY
14 DRDY
47 ꢁ
GPIO/IRQ
DVDD
3.3 V
0.1 ꢀF
DGND
图10-12. Serial Interface Connections
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10.2 Typical Application
10.2.1 3-Wire RTD Measurement with Lead-Wire Compensation
图
10-13 is a fault-protected, filtered, 3-wire RTD application circuit with hardware-based, lead-wire
compensation. Two IDAC current sources provide the lead-wire compensation. One IDAC current source
(IDAC1) provides excitation to the RTD element. The ADC reference voltage input (pins AIN2 and AIN3) is
derived from the same current by resistor RREF, providing ratiometric cancellation of current-source drift. The
other current source (IDAC2) has the same current setting, providing cancellation of lead-wire resistance by
generating a voltage drop across lead-wire resistance RLEAD2 equal to the voltage drop of RLEAD1. Because the
RRTD voltage is measured differentially at ADC pins AIN4 and AIN5, the voltages across the lead wire resistance
cancel. Resister RBIAS level-shifts the RTD signal to within the ADC specified input range. The current sources
are provided by two additional pins (AIN1 and AIN6) that connect to the RTD through blocking diodes. The
additional pins are used to route the RTD excitation currents around the input resistors, avoiding the voltage
drop otherwise caused by the filter resistors RF1 and RF4. The diodes protect the ADC inputs in the event of a
miswired connection. The input filter resistors limit the input fault currents flowing into the ADC.
5 V
3.3 V
0.1 mF
0.1 mF
AVDD
DVDD
IDAC1
AVDD
IIDAC1
AIN1
(IDAC1)
500 ꢁA
Device
CCM4
RF4
AIN2
(REFP)
Reference
Mux
Internal
Reference
RREF
REFOUT
CDIF2
RF3
AIN3
(REFN)
CCM3
Ref
Alarm
Buf
3-Wire RTD
RLEAD1
CCM2
START
RESET/PWDN
CS
RF2
AIN4
(AINP)
Serial
Interface
and
Input
MUX
32-bit
ûꢀ ADC
Digital
Filter
CDIF1
PGA
RRTD
DIN
RLEAD2
RF1
AIN5
DOUT/DRDY
SCLK
Control
(AINN)
CCM1
DRDY
Signal
Alarm
IDAC2
AVDD
IIDAC2
AIN6
XTAL2
XTAL1
Clock
Mux
Internal
Oscillator
(IDAC2)
500 ꢁA
AVSS
DGND
RLEAD3
IIDAC1 + IIDAC2
RBIAS
图10-13. 3-Wire RTD Application
10.2.1.1 Design Requirements
表10-1 shows the design requirements of the 3-wire RTD application.
表10-1. Design Requirements
DESIGN PARAMETER
ADC supply voltage
RTD sensor type
VALUE
4.75 V (minimum)
3-wire Pt100
20 Ωto 400 Ω
0 Ωto 10 Ω
1 mW
RTD resistance range
RTD lead resistance range
RTD self heating
Accuracy (1)
±0.02 Ω
(1) TA = 25°C. After offset and full-scale calibration.
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10.2.1.2 Detailed Design Procedure
The key considerations In the design of a 3-wire RTD circuit are the accuracy, the lead wire compensation, and
the sensor self-heating. As the design values of 表 10-2 illustrate, several values of excitation currents are
available. The resolution is expressed in units of noise-free bits (NFR). Noise-free resolution is resolution with no
code flicker. The selection of excitation currents trades off resolution against sensor self-heating. In general,
measurement resolution improves with increasing excitation current. Increasing the excitation current beyond
1000 µA results in no further improvement in resolution. The design procedure is based on 500-µA excitation
current, because this level of current results in very low sensor self-heating (0.4 mW).
表10-2. RTD Circuit Design Parameters
(5)
(8)
(1)
(3)
(4)
(6)
(7)
(9)
(10)
(11)
RREF
(kΩ)
RBIAS
IIDAC
(µA)
NFR
(bits)
PRTD
(mW)
VRTD
(V)
Gain(2) VREFMIN
VREF
(V)
VINNLIM
(V)
VINPLIM
(V)
VRTDN
(V)
VRTDP
(V)
VIDAC1
(V)
(V/V)
32
32
16
8
(V)
(kΩ)
7.10
5.10
2.30
1.10
0.57
0.50
0.23
0.10
50
16.8
17.8
18.8
19.1
18.9
19.3
19.1
18.3
0.001
0.004
0.025
0.100
0.225
0.400
0.900
1.600
0.02
0.04
0.10
0.20
0.30
0.40
0.60
0.80
0.64
1.28
1.60
1.60
1.20
1.60
1.20
0.80
0.90
1.41
1.76
1.76
1.32
1.76
1.32
0..90
18
0.6
0.9
1.1
1.0
0.8
0.9
0.6
0.3
4.1
3.8
3.7
3.8
4.0
3.9
4.2
4.5
0.7
1.0
1.2
1.1
0.9
1.0
0.7
0.4
0.7
1.1
1.3
1.3
1.2
1.4
1.3
1.2
1.9
2.8
3.3
3.4
2.8
3.5
3.0
2.4
100
14.1
7.04
3.52
1.76
1.76
0.88
0.45
250
500
750
4
1000
1500
2000
4
2
1
(1) VRTD is the RTD input voltage.
(2) Gain is the ADC gain
(3) VREFMIN is the minimum reference voltage required by the design.
(4) VREF is the design target reference voltage allowing for 10 % over-range or the minimum 0.9 V reference voltage requirement.
(5) RREF is the resistor that senses the IDAC current to generate VREF
.
(6) VINNLIM is the absolute minimum input voltage required by the ADC.
(7) VINPLIM is the absolute maximum input voltage required by the ADC.
(8) RBIAS establishes the level-shift voltage.
(9) VRTDN is the design target negative input voltage.
(10) VRTDP is the design target positive input voltage.
(11) VIDAC1 is the design target IDAC1 loop voltage.
Initially, RLEAD1 and RLEAD2 are considered to be 0 Ω. Route the IDAC1 current through the external reference
resistor, RREF. IDAC1 generates the ADC reference voltage, VREF, across the reference resistor. This voltage is
defined by 方程式24:
VREF = IIDAC1 · RREF
(24)
Route the second current (IDAC2) to the second RTD lead.
Program both IDAC1 and IDAC2 to the same value by using the IDACMAG register; however, only the IDAC1
current flows through the reference resistor and RTD. The IDAC1 current excites the RTD to produce a voltage
proportional to the RTD resistance. The RTD voltage is defined by 方程式25:
VRTD = RRTD · IIDAC1
(25)
The ADC amplifies the RTD signal voltage (VRTD) and measures the resulting voltage against the reference
voltage to produce a proportional digital output code, as shown in 方程式26 through 方程式28.
Code ∝VRTD · Gain / VREF
(26)
(27)
(28)
Code ∝(RRTD · IIDAC1) · Gain / (IIDAC1 · RREF
Code ∝(RRTD · Gain) / RREF
)
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As shown in 方程式 28, the RTD measurement depends on the value of the RTD, the PGA gain, and the
reference resistor RREF, but not on the IDAC1 value. Therefore, the absolute accuracy and temperature drift of
the excitation current does not matter.
The second excitation current (IDAC2) provides a second voltage drop across the second RTD lead resistance,
RLEAD2. The second voltage drop compensates the voltage drop caused by IDAC1 and RLEAD1. The leads of a 3-
wire RTD typically have the same length; therefore, the lead resistance is typically identical. Taking the lead
resistance into account (RLEADx ≠0), the differential voltage (VIN) across ADC inputs AIN4 and AIN5 is shown in
方程式29:
VIN = IIDAC1 · (RRTD + RLEAD1) –IIDAC2 · RLEAD2
(29)
If RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2, the expression for VIN reduces to 方程式30:
VIN = IIDAC1 · RRTD
(30)
In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is
compensated, as long as the lead resistance values and the IDAC values are matched.
Using 方程式 25, the value of RTD resistance (400 Ω, maximum) and the excitation current (500 μA) yields an
RTD voltage of VRTD = 500 μA · 400 Ω = 0.2 V. Use the maximum gain of 8 V/V in order to limit the reference
voltage requirement as well as the corresponding loop voltage of IDAC1. The total loop voltage must not exceed
the maximum IDAC voltage compliance specification. Gain = 8 requires a minimum reference voltage VREFMIN
=
0.2 V · 8 = 1.6 V. To provide a margin for the ADC operating range, increase the target reference voltage by 10%
(VREF = 1.6 V · 1.1 = 1.76 V). Calculate the value of the reference resistor, as shown in 方程式31:
RREF = VREF / IIDAC1 = 1.76 V / 500 μA = 3.52 kΩ
(31)
For best results, use a precision reference resistor RREF with a low temperature drift (< 10 ppm/°C).
The next step in the design is determining the value of the RBIAS resistor, in order to level shift the RTD voltage
to meet the ADC absolute input-voltage specification. The required level-shift voltage is determined by
calculating the minimum absolute voltage (VINNLIM) as shown in 方程式32:
VAVSS + 0.3 + VRTD · (Gain –1) / 2 ≤VINNLIM
(32)
where
• VRTD = maximum differential RTD voltage = 0.2 V
• Gain = 8
• VAVSS = 0 V
The result of the equation requires a minimum absolute input voltage (VRTDN) > 1.0 V. Therefore, the RTD
voltage must be level shifted a minimum of 1.0 V. To meet this requirement, a target level-shift value of 1.1 V is
chosen to provide 0.1 V margin. Calculate the value of RBIAS as shown in 方程式33:
RBIAS= VINN / (IIDAC1+ IIDAC2) = 1.1 V / ( 2 · 500 μA) = 1.1 kΩ.
(33)
After the level-shift voltage is determined, verify that the positive RTD voltage (VRTDP) is less than the maximum
absolute input voltage (VINPLIM), as shown in 方程式34:
V
INPLIM ≤VAVDD –0.3 –VRTD · (Gain –1) / 2
(34)
where
• VRTD = maximum differential RTD voltage = 0.2 V
• Gain = 8
• VAVDD = 4.75 V (minimum)
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Solving 方程式34 results in a required VRTDP of less than 3.8 V. Calculate the VRTDP input voltage by 方程式35:
VINP = VRTDN + IIDAC1 · ( RRTD + RLEAD1) = 1.1 V + 500 μA · (400 Ω+ 10 Ω) = 1.3 V
(35)
Because 1.3 V is less than the 3.8-V maximum input voltage limit, the absolute positive and negative RTD
voltages are within the ADC specified input range.
The next step in the design is to verify that the loop voltage of the excitation current is less than the specified
IDAC compliance voltage. The IDAC compliance voltage is the maximum voltage drop developed across each
IDAC current path to AVSS. In this circuit, IDAC1 has the largest voltage drop developed across its current path.
The IDAC1 calculation is sufficient to satisfy IDAC2 because the IDAC2 voltage drop is always less than IDAC1
voltage drop. The sum of voltages in the IDAC1 loop is shown in 方程式36:
VIDAC1 = [(IIDAC1 + IIDAC2) · (RLEAD3 + RBIAS)] + [IIDAC1 · (RRTD + RLEAD1 + RREF)] + VD
(36)
where
• VD = external blocking diode voltage.
The equation results in a loop voltage of VIDAC1= 3.4 V. The worst-case current source compliance voltage is:
(VAVDD – 1.1 V) = (4.75 V – 1.1 V) = 3.64 V. The VIDAC1 loop voltage is less than the specified current source
compliance voltage (3.4 V < 3.64 V).
Many applications benefit from using an analog filter at the inputs to remove noise and interference from the
signal. Filter components are placed on the ADC inputs (RF1, RF2, CDIF1, CCM1, and CCM2), as well as on the
reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The filters remove both differential and common-mode
noise. The application shows a differential input noise filter formed by RF1, RF2 and CDIF, with additional
differential mode capacitance provided by the common-mode filter capacitors, CM1 and CM2. Calculate the
differential cutoff frequency as shown in 方程式37:
fDIF = 1 / [2π· (RF1 + RF2) · (CDIF1 + CM1|| CM2)]
(37)
The common-mode noise filter is formed by components RF1, RF2, CM1 and CM2. Calculate the common-mode
signal cutoff frequency as shown in 方程式38:
fCM = 1 / (2π· RF1 · CM1) = 1 / (2π· RF2 · CM2
)
(38)
Mismatches in the common-mode filter components convert common-mode noise into differential noise. To
reduce the effect of mismatch, use a differential mode filter with a corner frequency that is 10 times lower than
the common-mode filter corner frequency. The low-frequency differential filter removes the common-mode
converted noise. The filter resistors (RFx) also serve as current-limiting resistors. These resistors limit the current
into the analog inputs (AINx) of the device to safe levels when an overvoltage occurs on the inputs.
Filter resistors lead to an offset voltage error due to the dc input current leakage flowing into and out of the
device. Remove this voltage error by system offset calibration. Resistor values that are too large generate
excess thermal noise and degrade the overall noise performance. The recommended range of the filter resistor
values is 2 kΩto 10 kΩ. The properties of the capacitors are important because the capacitors are connected to
the signal; use high-quality C0G ceramics or film-type capacitors.
For consistent noise performance across the full range of RTD measurements, match the corner frequencies of
the input and reference filter. Detailed information on matching the input and reference filter is found in the RTD
Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 application report.
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10.2.1.3 Application Curve
图 10-14 shows the resistance measurement results. The measurements are taken at TA = 25°C. A system
offset calibration is performed using shorted inputs. A system gain calibration is performed using a 390-Ω
precision resistor. The data are taken using a precision resistor simulator with a 3-wire connection in place of a
3-wire RTD. Note that the measurement data are in ohms and do not include the error of the RTD sensor itself.
The measured resistance error is < ±0.02 Ωover the 20-Ωto 400-Ωrange.
0.1
0.05
0
-0.05
-0.1
0
50
100
150
200
250
300
350
400
RTD Value (W)
图10-14. Resistance Measurement Error
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10.3 What To Do and What Not To Do
• Do partition the analog, digital, and power supply circuitry into separate sections on the PCB.
• Do use a single ground plane for analog and digital grounds.
• Do place the analog components close to the ADC pins using short, direct connections.
• Do keep the SCLK pin free of glitches and noise.
• Do verify that the analog input voltages are within the specified PGA input voltage range under all input
conditions.
• Do tie unused analog input pins to midsupply to minimize input leakage current.
• Do provide current limiting to the analog inputs in case overvoltage faults occur.
• Do use an LDO regulator to reduce ripple voltage generated by switch-mode power supplies.
• Don't route digital clock traces in the vicinity of the CAPP and CAPN pins.
• Don't cross digital signals over analog signals.
• Don't allow the analog and digital power supply voltages to exceed 7 V under all conditions, including during
power-up and power-down.
图10-15 shows Do's and Don'ts of ADC circuit connections.
INCORRECT
CORRECT
5 V
5 V
AVDD
AVDD
Device
Device
AINP
AINN
AINP
AINN
32-bit
32-bit
PGA
PGA
ûꢀ ADC
ûꢀ ADC
AVSS
0 V
AVSS
0 V
0 V
0 V
Single-ended input, PGA enabled
Single-ended input, PGA bypassed
CORRECT
CORRECT
5 V
2.5 V
AVDD
AVDD
Device
Device
AINP
AINN
AINP
AINN
32-bit
32-bit
PGA
PGA
PGA enabled
2.5 V
ûꢀ ADC
ûꢀ ADC
AVSS
AVSS
0 V
-2.5 V
0 V
Single-ended input, PGA enabled
Single-ended input, PGA enabled
3.3 V
5 V
5 V
3.3 V
INCORRECT
INCORRECT
Device
AVDD
PGA
DVDD
AVDD
PGA
DVDD
Device
32-bit
32-bit
ûꢀ ADC
ûꢀ ADC
AVSS
DGND
AVSS
DGND
Inductive supply or ground connections
AGND/DGND isolation
CORRECT
3.3 V
3.3 V
5 V
2.5 V
CORRECT
AVDD
PGA
DVDD
32-bit
AVDD
DVDD
Device
Device
32-bit
PGA
ûꢀ ADC
ûꢀ ADC
AVSS
DGND
AVSS
-2.5 V
DGND
Low impedance AGND/DGND connection
Low impedance AGND/DGND connection
图10-15. Dos and Don'ts Circuit Connections
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10.4 Initialization Setup
图10-16 is a general procedure that shows a typical ADS1262 configuration and measurement sequence.
Apply Power
Set RESET/PWDN High
/* This pin must be high for operation
Y
/* ADC automatically detects external clock
(external clock can be applied at power-on)
External clock?
N
Apply clock to XTAL1
Wait 216 clock cycles
/* The ADC is internally held in reset for 216 clocks after power-on
Y
/* If START pin is high, conversions are free-running
If START pin is low, conversions are stopped
START High?
DRDY pulses at 20 Hz
N
Set START low or
STOP1 command
/* For simplicity, stop conversions before register configuration
DRDY not pulsing
Issue Write Register
command to configure the
ADC
/* Readings are suspended until Write Register command completes
(If conversions are active, changes to certain registers result in ADC restart)
Issue Read Register
command to verify registers
/* Readings are suspended until Read Register command completes
Wait for reference
voltage to settle
/* The internal reference require time to settle after power-on
/* Start or restart new ADC conversion
Set START pin high
or START1 command
N
/* Read data at a rate faster than
the data rate to avoid dropping data
Read Data using
RDATA1 command
Hardware DRDY?
Y
N
ADC1 Status bit = 1 ?
Y
N
DRDY low ?
Y
New ADC1 data
/* By Direct or
Command method
Read Data
N
Change ADC
Settings ?
Y
图10-16. ADS1262 Configuration and Measurement Procedure
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图 10-17 shows a general procedure to read concurrent ADC1 and ADC2 data of the ADS1263. The conversion
time of ADC1 can be faster or slower than ADC2. If the conversion time of ADC1 is less than or equal to that of
ADC2, and if the ADC2 status bit is equal to 1, then when ADC1 data are ready, ADC2 data are also ready. The
ADC2 data can then be read by the RDATA2 command. Similarly, if the conversion time of ADC2 is less than
that of ADC1, and if the ADC1 status bit is equal to 1, then when ADC2 data are ready. ADC1 data are also
ready, The ADC1 data can then be read by the RDATA1 command. It is important to note an exception to the
conversion time related to the data rate: the time of the first conversion is not always the same as (1 / data rate)
because of digital filter latency. Therefore, it is possible that although the data rate of ADC1 can be faster than
ADC2, the time required for the first conversion of ADC1 can be greater than ADC2 depending on the digital filter
setting and chop mode. When checking the ADC2 status by reading ADC1 data, use the RDATA1 command.
Begin
Stop Conversions
ADC1: START pin low; or
STOP1 command
ADC2: STOP2 command
/* For simplicity, stop conversions before ADC configuration
Configure ADC1
/* Configure the ADCs
Configure ADC2
Start Conversions
ADC1: START pin high; or
/* Start conversions
START1 command
ADC2: START2 command
/* Read data at a rate faster than
the data rate to avoid dropping data
N
Read ADC2 data
using RDATA2 command
ADC1 conversion
time ≤ ADC2 ?
Y
N
N
ADC2 Status bit = 1 ?
Read ADC1 data
using RDATA1 command
Hardware DRDY?
Y
Y
New ADC2 data
N
ADC1 Status bit = 1 ?
N
DRDY low ?
Y
N
Y
ADC1 Status bit =1 ?
New ADC1 data
Read ADC1 data
using RDATA1 command
Y
Read ADC1 data using
RDATA1 command
N
ADC2 Status bit =1 ?
Y
Read ADC2 data
using RDATA2 command
N
Change ADC
configuration ?
Y
图10-17. ADS1263 Concurrent Read of ADC1 and ADC2 Data
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11 Power Supply Recommendations
The ADS1262 and ADS1263 require an analog power supply (VAVDD, VAVSS) and digital power supply (VDVDD).
The analog power supply can be bipolar (for example, VAVDD = +2.5 V, VAVSS = –2.5 V) or unipolar (for
example, VAVDD = 5 V, VAVSS = 0 V). The digital supply (VDVDD) range is 2.7 V to 5.25 V. The digital supply
voltage determines the digital I/O logic levels. Keep in mind that the GPIO logic levels (AIN3-AINCOM) are
referenced to the analog supply voltage and may be different from the digital I/O logic level. The analog and
digital sections of the ADC are not internally isolated and the grounds for analog and digital must be connected
together. Output voltage ripple produced by switch-mode power supplies may interfere with the ADC resulting in
reduced performance. Use low-dropout regulators (LDOs) to reduce the power-supply ripple voltage produced
by switch-mode power supplies.
11.1 Power-Supply Decoupling
Good power-supply decoupling is important in order to achieve optimum performance. Power supplies VAVDD
,
VAVSS and VDVDD must be decoupled to a common ground potential. For proper power-supply decoupling, place
a 0.1-µF capacitor as close as possible to the supply with an additional 1-µF bulk capacitor placed nearby. 图
11-1 shows decoupling for bipolar-supply (left figure) and single-supply (right figure) operation. When using
bipolar supplies, bypass both AVDD and AVSS to ground separately, and include a bypass capacitor between
AVDD and AVSS. Use a multilayer ceramic chip capacitors (MLCCs) that offers low equivalent series resistance
(ESR) and equivalent series inductance (ESL) characteristics for power-supply decoupling purposes. The
BYPASS pin is the bypass output of an internal 2-V regulator. The 2-V regulator powers the digital circuitry.
Connect a ceramic or tantalum 1-µF capacitor from this pin to DGND. Do not load this voltage by external
circuits.
1
2
3
4
5
6
7
8
9
AIN8
AIN7 28
AIN6 27
1
2
3
4
5
6
7
8
9
AIN8
AIN7 28
AIN6 27
AIN9
AIN9
AINCOM
CAPP
CAPN
AVDD
AVSS
AIN5 26
AINCOM
CAPP
CAPN
AVDD
AVSS
AIN5 26
AIN4 25
AIN4 25
4.7 nF
4.7 nF
AIN3 24
AIN3 24
5 V
+2.5 V
AIN2 23
AIN2 23
1 mF
1 mF
0.1 mF
1 mF
1 mF
0.1 mF
1 mF
AIN1 22
AIN1 22
ADS1262
ADS1263
ADS1262
ADS1263
REFOUT
START
AIN0 21
REFOUT
START
AIN0 21
œ2.5 V
œ2.5 V
3.3 V
RESET/PWDN 20
DVDD 19
RESET/PWDN 20
DVDD 19
3.3 V
10 CS
10 CS
0.1 mF
0.1 mF
1 mF
1 mF
11 SCLK
12 DIN
DGND 18
BYPASS 17
XTAL2 16
XTAL1/CLKIN 15
11 SCLK
12 DIN
DGND 18
BYPASS 17
XTAL2 16
XTAL1/CLKIN 15
1 mF
1 mF
13 DOUT/DRDY
14 DRDY
13 DOUT/DRDY
14 DRDY
图11-1. Power-Supply Decoupling for Bipolar (left) and Single-Supply (right) Operation
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11.2 Analog Power-Supply Clamp
It is important to evaluate circumstances when an input signal is present while the ADC is powered and
unpowered. When the input signal exceeds the power-supply voltage, it is possible to back drive the analog
power-supply voltage with the input signal through a conduction path of the internal ESD diodes. Back driving
the ADC power supply can also occur when the power-supply voltage is on. The back-drive, fault-current path is
shown in 图11-2. Depending on the external power-supply components, it is possible that the maximum rating of
the ADC power-supply voltage can be exceeded if back-driven. ADC power supply overvoltage must be
prevented in all cases. One solution is to clamp the AVDD to AVSS voltage with an external 6-V Zener diode.
ADC supply On or Off
IFAULT
+V
+5 V Reg
AVDD
RLIMIT
ESD Diode
AINx
Optional
6-V Zener Diode
+
œ
ADC
Input Voltage
AINx
IFAULT
ESD Diode
IFAULT
AVSS
图11-2. Analog Power-Supply Clamp
11.3 Power-Supply Sequencing
Sequence the power supplies in any order, but never allow and analog or digital inputs to exceed the respective
analog or digital power-supplies without limiting the input fault current. The ADC remains in reset until both
analog and digital power supplies exceed the respective power-on reset (POR) thresholds. 图 9-52 shows the
power-on reset sequence. After the power supplies have crossed the reset levels (including the internal 2-V
LDO), the ADC resets (POR) and is ready for communication 65536 clock periods later (nominally 9 ms).
Delay communication for 50 ms after the power supplies have stabilized within the specified range to make sure
the ADC is operational. In addition to POR, make sure that the reference voltage has fully settled before starting
the conversions. When using a 1-µF reference capacitor allow a minimum of 50 ms for the internal reference to
settle. External references may require additional settling time.
12 Layout
Good layout practices are crucial to realize the full-performance of the ADS1262 and ADS1263. Poor grounding
can quickly degrade the noise performance of the main 32-bit ADC and auxiliary 24-bit ADC. The following
layout recommendations are given to help provide best results.
12.1 Layout Guidelines
Ground must be a low impedance connection for return currents to flow undisturbed back to their respective
sources. Keep connections to the ground plane as short and direct as possible. When using vias to connect to
the ground layer, use multiple vias in parallel to reduce impedance to ground.
A mixed-signal layout sometimes incorporates separate analog and digital ground planes that are tied together
at one location; however, separating the ground planes is not necessary when analog, digital, and power supply
components are properly placed. Proper placement of components partitions the analog, digital, and power
supply circuitry into different PCB regions to prevent digital return currents from coupling into sensitive analog
circuitry.
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For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on restrictions imposed by specific form factors, single ground planes may not
be possible. If ground plane separation is necessary, then make the connection at the ADC. Do not connect
individual ground planes at multiple locations because this configuration creates ground loops. A single plane for
analog and digital ground avoids ground loops.
If isolation is required in the application, isolate the digital signals between the ADC and controller, or provide the
isolation from the controller to the remaining system. if an external crystal is used to provide the ADC clock,
place the crystal and load capacitors directly to the ADC pins using short direct traces. See the Crystal Oscillator
section for more details.
Supply pins must be bypassed with a low-ESR ceramic capacitor. Place the bypass capacitors as close as
possible to the supply pins using short, direct traces. For optimum performance, use low-impedance connections
on the ground-side connections of the bypass capacitors. Flow the supply current through the bypass capacitor
pin first and then to the supply pin to make the bypassing most effective (also known as a Kelvin connection). If
multiple ADCs are on the same PCB, use wide power supply traces or dedicated power-supply planes to
minimize the potential of crosstalk between ADCs.
If external filtering is used for the analog inputs, use C0G-type ceramic capacitors when possible. C0G
capacitors have stable properties and low-noise characteristics. Ideally, route the differential signals as pairs in
order to minimize the loop area between the traces. For the ADC CAPP and CAPN pins, place the 4.7-nF C0G
capacitor close to the pins using short direct traces. Route digital circuit traces (such as clock signals) away from
all analog pins. Note the internal reference output return shares the same pin as the AVSS power supply. To
minimize coupling between the power-supply trace and reference-return trace, route the two traces separately;
ideally, as a star connection at the AVSS pin.
It is important the SCLK input of the serial interface is free from noise and glitches. Even with relatively slow
SCLK frequencies, short digital-signal rise and fall times may cause excessive ringing and noise. For best
performance, keep the digital signal traces short, use termination resistors as needed, and ensure all digital
signals are routed directly above the ground plane with minimal use of vias.
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Supply
Generation
Signal
Conditioning
(RC filters
and
Interface
Device
Microcontroller
Tranceiver
amplifiers)
Connector
or Antenna
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
图12-1. System Component Placement
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12.2 Layout Example
图 12-2 is an example layout of the ADS1262 and ADS1263, requiring a minimum of three PCB layers. The
example circuit is shown for a single analog supply (5 V) connection and an external crystal oscillator. In this
example, an inner layer is dedicated to the ground plane and the outer layers are used for signal and power
traces. If a four-layer PCB is used, dedicate the additional inner layers to route power traces. The ADC
orientation is shown left to right to minimize crossover of the analog and digital signal traces. The PCB is
partitioned with analog signals routed from the left, digital signals routed to the lower-right, and power routed
from the upper-right. Analog supply bypass capacitors are placed opposite to the ADC on the bottom layer to
allow the reference and PGA output capacitors to be placed closer to the ADC.
Internal plane connected to GND (DGND = AVSS)
IN1
RTD input
IN2
6V Zener Diode
(OPTIONAL)
AVDD
IN6
DVDD
Differential input
External Crystal
IN7
(OPTIONAL)
IN6
(TO XTAL1)
(TO XTAL2)
Differential input
IN7
/RESET/PWDN
START
/CS
COM
/DRDY
DOUT
DIN
Thermocouple/single-ended input
IN9
SCLK
Tie unused inputs to REFOUT
for lowest leakage current
图12-2. PCB Layout Example
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13 Device and Documentation Support
13.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.3 Trademarks
SPI™ is a trademark of Motorola Inc.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 127
Product Folder Links: ADS1262 ADS1263
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1262IPW
ADS1262IPWR
ADS1263IPW
ADS1263IPWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
28
28
28
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1262
1262
1263
1263
2000 RoHS & Green
50 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1262IPWR
ADS1263IPWR
TSSOP
TSSOP
PW
PW
28
28
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1262IPWR
ADS1263IPWR
TSSOP
TSSOP
PW
PW
28
28
2000
2000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ADS1262IPW
ADS1263IPW
PW
PW
TSSOP
TSSOP
28
28
50
50
530
530
10.2
10.2
3600
3600
3.5
3.5
Pack Materials-Page 3
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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