ADS1278-EP_技术文档

ADS1278-EP

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ZHCSAC0 –AUGUST 2012

八路同步采样 24 位模数转换器

查询样品: ADS1278-EP

1

特性

•

234

同时测量八个通道

应用范围

•

高达 128kSPS 数据速率

•

振动/模式分析

多通道数据采集

声学/动态应变仪

压力传感器

•

AC 性能：

62kHz 带宽

111dB 信噪比 (SNR)（高分辨率模式）

-108dB 总谐波失真 (THD)

xxxx

•

DC 精度：

0.8-μV/°C 偏移漂移

1.3-ppm/°C 增益漂移

说明

基于单通道ADS1271，ADS1278（八通道）是一款 24

位、三角积分 (ΔΣ) 模数转换器 (ADC)，其数据速率高

达每秒 128k 次采样 (SPS)，从而可实现八通道同时采

样。

可选运行模式：

高速：128kSPS，106dB SNR

高分辨率：52kSPS，111dB SNR

低功耗：52kSPS，31mW/ch

低速：10kSPS，7mW/ch

传统上来讲，提供良好漂移性能的工业用三角积分

ADC 使用带有较大通带衰减的数字滤波器。因此，它

们的信号带宽有限并且主要适合于 dc 测量。音频应用

中的高分辨 ADC 提供更大的可用带宽，但是与工业用

ADC 相比，它的偏移和漂移技术规格被大大削弱。

ADS1278 将三种类型的转换器组合在一起，从而实现

带有出色 dc 和 ac 技术规格的高精度工业测量。

•

线性相位数字滤波器

SPI™ 或者帧同步串行接口

低采样孔径错误

调制器输出选项（数字滤波器旁通）

模拟电源：5V

数字内核：1.8V

I/O 电源：1.8V 至 3.3V

高阶、斩波稳定调制器在低带内噪声情况下实现极低漂

移。板载抽取滤波器抑制调制器和信号带外噪声。这

些 ADC 在纹波小于 0.005dB 的情况下提供高达那奎

斯特速率 90% 的可用信号带宽。

当前提供散热增强薄型四方扁平封装 (HTQFP)-64

封装 PowerPAD™ 封装

支持国防、航空航天、和医疗应用

四个运行模式可实现速度、分辨率和功率的优化。所

有操作直接由引脚控制；无需寄存器编程。器件可在

军用温度范围（-55°C 至 125°C）内运行并且采用

HTQFP-64 PowerPAD 封装。

•

受控基线

一个组装/测试场所

一个制造场所

(1)

军用温度范围 (-55°C/125°C) 内可用

延长的产品生命周期

延长的产品变更通知

产品可追溯性

(1) 可提供额外温度范围-请与厂家联系

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

SPI is a trademark of Motorola, Inc.

All other trademarks are the property of their respective owners.

2

3

4

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SBAS579

ADS1278-EP

ZHCSAC0 –AUGUST 2012

www.ti.com.cn

VREFP VREFN AVDD

DVDD

IOVDD

DS

Input1

Input2

Input3

Input4

Input5

Input6

Input7

Input8

SPI

and

DRDY/FSYNC

SCLK

Frame-

Sync

DOUT[8:1]

DIN

Interface

Eight

Digital

Filters

DS

TEST[1:0]

FORMAT[2:0]

CLK

Control

Logic

SYNC

PWDN[8:1]

CLKDIV

MODE[1:0]

AGND

DGND

ADS1278

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE

TQFP - PAP Reel of 250

ORDERABLE PART NUMBER

TOP-SIDE MARKING

VID NUMBER

–55°C to 125°C

ADS1278MPAPTEP

ADS1278EP

V62/12611-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

2

ADS1278-EP

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ZHCSAC0 –AUGUST 2012

PIN ASSIGNMENTS

PAP PACKAGE

TQFP-64

(TOP VIEW)

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AINN7

AINP2

AINN2

AINP1

AINN1

AVDD

AINP7

3

AINN8

4

AINP8

5

AVDD

6

AGND

DGND

TEST0

TEST1

CLKDIV

SYNC

DIN

AGND

7

PWDN1

PWDN2

PWDN3

PWDN4

PWDN5

PWDN6

PWDN7

PWDN8

MODE0

MODE1

8

ADS1278

9

10

11

12

13

14

15

16

DOUT8

DOUT7

DOUT6

DOUT5

(PowerPAD Outline)

Table 1. PIN DESCRIPTIONS

NAME

NO.

FUNCTION

DESCRIPTION

6, 43, 54,

58, 59

AGND

Analog ground

Analog ground; connect to DGND using a single plane.

AINP1

AINP2

AINP3

AINP4

AINP5

AINP6

AINP7

AINP8

3

Analog input

1

63

61

51

49

47

45

AINP[8:1] Positive analog input, channels 8 through 1.

3

ADS1278-EP

ZHCSAC0 –AUGUST 2012

www.ti.com.cn

Table 1. PIN DESCRIPTIONS (continued)

NAME

AINN1

AINN2

AINN3

AINN4

AINN5

AINN6

AINN7

AINN8

AVDD

VCOM

VREFN

VREFP

CLK

NO.

FUNCTION

DESCRIPTION

4

Analog input

2

64

62

AINN[8:1] Negative analog input, channels 8 through 1.

52

50

48

46

5, 44, 53, 60

Analog power supply Analog power supply (4.75V to 5.25V).

55

57

56

27

Analog output

Analog input

Digital input

AVDD/2 Unbuffered voltage output.

Negative reference input.

Positive reference input.

Master clock input (f_CLK).

CLK input divider control:

1 = 37MHz (High-Speed mode)/otherwise 27MHz

0 = 13.5MHz (low-power)/5.4MHz (low-speed)

CLKDIV

10

Digital input

DGND

DIN

7, 21, 24, 25

Digital ground

Digital input

Digital ground power supply.

Daisy-chain data input.

12

20

19

18

17

16

15

14

13

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

Digital output

DOUT1 is TDM data output (TDM mode).

DOUT[8:1] Data output for channels 8 through 1.

DRDY/

FSYNC

29

Digital input/output

Frame-Sync protocol: frame clock input; SPI protocol: data ready output.

DVDD

FORMAT0

FORMAT1

FORMAT2

IOVDD

26

32

31

30

22, 23

34

33

42

41

40

39

38

37

36

35

28

11

8

Digital power supply Digital core power supply.

Digital input

FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,

fixed/dynamic position TDM data, and modulator mode/normal operating mode.

Digital input

Digital power supply I/O power supply (+1.65V to +3.6V).

MODE0

MODE1

PWDN1

PWDN2

PWDN3

PWDN4

PWDN5

PWDN6

PWDN7

PWDN8

SCLK

Digital input

Digital input/output

Digital input

MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed

mode operation.

PWDN[8:1] Power-down control for channels 8 through 1.

Serial clock input, Modulator clock output.

Synchronize input (all channels).

SYNC

TEST0

TEST[1:0] Test mode select:

01 = Do not use

10 = Do not use

00 = Normal operation

11 = Test mode

TEST1

9

4

ADS1278-EP

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ZHCSAC0 –AUGUST 2012

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range, unless otherwise noted⁽¹⁾

UNIT

V

AVDD to AGND

–0.3 to 6.0

–0.3 to 3.6

–0.3 to 0.3

100

DVDD, IOVDD to DGND

AGND to DGND

V

Momentary

mA

V

Input current

Continuous

10

Analog input to AGND

–0.3 to AVDD + 0.3

–0.3 to DVDD + 0.3

150

Digital input or output to DGND

Maximum junction temperature, T_J

Storage temperature range

V

°C

–60 to 150

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

THERMAL INFORMATION

ADS1278

THERMAL METRIC⁽¹⁾

PAP

64 PINS

33.1

6.2

UNITS

θ_JA

θ_JC

θ_JB

ψ_JT

ψ_JB

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case thermal resistance

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

7.9

°C/W

0.2

7.8

(1) 有关传统和新的热度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。

(2) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的指定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环

境热阻。

(3) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结板热阻。

(4) 结至顶部特征参数， ψ_JT，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该参

数以便获得 θ_JA

(5) 结至电路板特征参数， ψ_JB，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该

参数以便获得 θ_JA

。

5

ADS1278-EP

ZHCSAC0 –AUGUST 2012

www.ti.com.cn

ELECTRICAL CHARACTERISTICS

All specifications at T_A= –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V,

VREFN = 0 V, and all channels active, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating temperature range, T_A

-55

125

°C

Analog Inputs

Full-scale input voltage (FSR⁽¹⁾

)

V_IN= (AINP – AINN)

AINP or AINN to AGND

V_CM= (AINP + AINN)/2

±V_REF

V

AVDD +

0.1

Absolute input voltage

AGND – 0.1

Common-mode input voltage (V_CM

)

2.5

14

V

High-Speed mode

High-Resolution mode

Low-Power mode

Low-Speed mode

kΩ

14

Differential input

impedance

28

140

DC Performance

Resolution

No missing codes

f_CLK= 32.768MHz⁽²⁾

f_CLK= 27MHz

24

Bits

SPS

SPS⁽³⁾

128,000

105,469

52,734

10,547

±0.0003

0.25

High-Speed mode

Data rate (f_DATA

)

High-Resolution mode

Low-Power mode

Low-Speed mode

SPS

% FSR⁽¹⁾

Integral nonlinearity (INL)⁽⁴⁾

Differential input, V_CM= 2.5V

±0.0014

2

Offset error

mV

Offset drift

0.8

μV/°C

% FSR

ppm/°C

μV, rms

dB

Gain error

0.1

0.5

Gain drift

1.3

High-Speed mode

Shorted input

f_CM= 60Hz

8.5

68

13

21

High-Resolution mode

Low-Power mode

Low-Speed mode

5.5

Noise

8.5

8.0

Common-mode rejection

90

108

AVDD

80

dB

Power-supply rejection DVDD

IOVDD

f_PS= 60Hz

No load

85

dB

105

dB

V_COMoutput voltage

AC Performance

Crosstalk

AVDD/2

V

f = 1kHz, –0.5dBFS⁽⁵⁾

–107

106

dB

Hz

High-Speed mode

88.3

101

V_REF= 2.5V

V_REF= 3V

110

High-Resolution mode

Signal-to-noise ratio

111

(SNR)⁽⁶⁾(unweighted)

Low-Power mode

Low-Speed mode

Total harmonic distortion (THD)⁽⁷⁾

Spurious-free dynamic range

Passband ripple

98

106

107

V_IN= 1kHz, –0.5dBFS

–108

–96

109

±0.005

0.453 f_DATA

0.49 f_DATA

Passband

–3dB Bandwidth

(1) FSR = full-scale range = 2V_REF

.

(2) f_CLK= 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When f_CLK> 27MHz, operation is limited to Frame-

Sync mode and V_REF≤ 2.6V.

(3) SPS = samples per second.

(4) Best fit method.

(5) Worst-case channel crosstalk between one or more channels.

(6) Minimum SNR is ensured by the limit of the DC noise specification.

(7) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.

6

ADS1278-EP

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ZHCSAC0 –AUGUST 2012

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V,

VREFN = 0 V, and all channels active, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

High-Resolution mode

All other modes

95

dB

Stop band attenuation

Stop band

100

127.453

f_DATA

High-Resolution mode

All other modes

0.547 f_DATA

Hz

63.453

f_DATA

High-Resolution mode

All other modes

39/f_DATA

38/f_DATA

78/f_DATA

76/f_DATA

s

Group delay

High-Resolution mode

All other modes

Complete settling

Settling time (latency)

Voltage Reference Inputs

f_CLK= 27MHz

f_CLK= 32.768MHz⁽²⁾

0.5

2.5

3.1

2.6

V

Reference input voltage (V_REF

(V_REF= VREFP – VREFN)

)

AGND +

0.1

Negative reference input (VREFN)

Positive reference input (VREFP)

AGND – 0.1

VREFN + 0.5

V

AVDD +

0.1

High-Speed mode

0.65

1.3

kΩ

High-Resolution mode

Low-Power mode

Low-Speed mode

Reference Input

impedance

6.5

Digital Input/Output (IOVDD = 1.8V to 3.6V)

V_IH

0.7 IOVDD

DGND

IOVDD

V

0.3

IOVDD

V_IL

V_OH

I_OH= 4mA

I_OL= 4mA

0.8 IOVDD

DGND

IOVDD

0.2

IOVDD

V_OL

Input leakage

0 < V_{IN DIGITAL}< IOVDD

High-Speed mode⁽⁸⁾

Other modes

±10

32.768

27

μA

0.1

MHz

Master clock rate (f_CLK

)

Power Supply

AVDD

4.75

1.65

5

5.25

1.95

3.6

10

V

DVDD

1.8

V

IOVDD

V

AVDD

1

μA

mA

Power-down current

AVDD current

DVDD

50

IOVDD

1

11

High-Speed mode

High-Resolution mode

Low-Power mode

Low-Speed mode

High-Speed mode

High-Resolution mode

Low-Power mode

Low-Speed mode

High-Speed mode

High-Resolution mode

Low-Power mode

Low-Speed mode

97

145

64

97

44

9

14

23

30

16

20

DVDD current

IOVDD current

12

17

2.5

0.25

0.125

0.035

4.5

1

0.6

0.3

(8) f_CLK= 32.768MHz max for High-Speed mode, and 27MHz max for all other modes. When f_CLK> 27MHz, operation is limited to Frame-

Sync mode and V_REF≤ 2.6V.

7

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ZHCSAC0 –AUGUST 2012

www.ti.com.cn

ELECTRICAL CHARACTERISTICS (continued)

All specifications at T_A= –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V,

VREFN = 0 V, and all channels active, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

530

515

245

50

MAX

785

765

355

80

UNIT

mW

High-Speed mode

High-Resolution mode

Low-Power mode

Low-Speed mode

Power dissipation

TIMING CHARACTERISTICS: SPI FORMAT

t_CLK

t_CPW

CLK

· · ·

t_CPW

t_CD

t_CONV

DRDY

t_SD

t_DS

t_SCLK

t_SPW

SCLK

t_SPW

t_DOPD

t_MSBPD

t_DOHD

Bit 23 (MSB)

Bit 22

t_DIST

Bit 21

DOUT

DIN

t_DIHD

TIMING REQUIREMENTS: SPI FORMAT

For T_A= –40°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V.

SYMBOL

t_CLK

PARAMETER

MIN

37

TYP

MAX

UNIT

(1)

CLK period (1/f_CLK

)

10,000

ns

t_CPW

CLK positive or negative pulse width

15

(2)

t_CONV

Conversion period (1/f_DATA

)

256

2560

t_CLK

ns

(3)

t_CD

Falling edge of CLK to falling edge of DRDY

Falling edge of DRDY to rising edge of first SCLK to retrieve data

DRDY falling edge to DOUT MSB valid (propagation delay)

Falling edge of SCLK to rising edge of DRDY

SCLK period

22

18

(3)

t_DS

1

t_CLK

ns

t_MSBPD

16

32

(3)

t_SD

ns

(4)

t_SCLK

1

0.4

10

t_CLK

ns

t_SPW

SCLK positive or negative pulse width

(5)(3) (6)

t_DOHD

t_DOPD

t_DIST

SCLK falling edge to new DOUT invalid (hold time)

SCLK falling edge to new DOUT valid (propagation delay)

New DIN valid to falling edge of SCLK (setup time)

Old DIN valid to falling edge of SCLK (hold time)

(5)(3)

ns

6

ns

(6)

t_DIHD

ns

(1) f_CLK= 27MHz maximum.

(2) Depends on MODE[1:0] and CLKDIV selection. See Table 7 (f_CLK/f_DATA).

(3) Load on DRDY and DOUT = 20pF.

(4) For best performance, limit f_SCLK/f_CLKto ratios of 1, 1/2, 1/4, 1/8, etc.

(5) Timing parameters are characerized or guranteed by design for specified temperature but not production tested.

(6) t_DOHD(DOUT hold time) and t_DIHD(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.

8

ADS1278-EP

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ZHCSAC0 –AUGUST 2012

Figure 1. TIMING CHARACTERISTICS: FRAME-SYNC FORMAT

t_CPW

t_CLK

CLK

t_CPW

t_CS

t_FRAME

t_FPW

FSYNC

SCLK

DOUT

DIN

t_FS

t_SCLK

t_SPW

t_SF

t_SPW

t_MSBPD

Bit 23 (MSB)

t_DOPD

t_DOHD

Bit 21

Bit 22

t_DIST

t_DIHD

TIMING REQUIREMENTS: FRAME-SYNC FORMAT⁽¹⁾

For T_A= –40°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V.

SYMBOL

PARAMETER

MIN

37

TYP

MAX

UNIT

ns

All modes

10,000

t_CLK

CLK period (1/f_CLK)

High-Speed mode only

30.5

12

ns

t_CPW

t_CS

CLK positive or negative pulse width

ns

Falling edge of CLK to falling edge of SCLK

–0.25

256

1

0.25

t_CLK

t_SCLK

ns

(2)

t_FRAME

t_FPW

t_FS

Frame period (1/f_DATA

)

2560

FSYNC positive or negative pulse width

Rising edge of FSYNC to rising edge of SCLK

Rising edge of SCLK to rising edge of FSYNC

SCLK period⁽³⁾

5

t_SF

5

ns

t_SCLK

t_SPW

t_DOHD

1

t_CLK

ns

SCLK positive or negative pulse width

0.4

10

(4)(5) (6)

SCLK falling edge to old DOUT invalid (hold time)

SCLK falling edge to new DOUT valid (propagation delay)

FSYNC rising edge to DOUT MSB valid (propagation delay)

New DIN valid to falling edge of SCLK (setup time)

Old DIN valid to falling edge of SCLK (hold time)

(4)(6)

t_DOPD

31

ns

(4)

t_MSBPD

t_DIST

ns

6

ns

(5)

t_DIHD

ns

(1) Timing parameters are characerized or guranteed by design for specified temperature but not production tested.

(2) Depends on MODE[1:0] and CLKDIV selection. See Table 7 (f_CLK/f_DATA).

(3) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of f_CLK

.

(4) Timing parameters are characerized or guranteed by design for specified temperature but not production tested.

(5) t_DOHD(DOUT hold time) and t_DIHD(DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and

ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4 ns.

(6) Load on DOUT = 20 pF.

9

ADS1278-EP

ZHCSAC0 –AUGUST 2012

100000000.00

www.ti.com.cn

10000000.00

1000000.00

100000.00

10000.00

Wirebond Voiding Fail Mode

Electromigration Fail Mode

80

90

100

110

120

130

140

150

160

170

Continuous T (°C)

J

Figure 2. ADS1278 Operating Life Derating and Wirebond Voiding Fail Mode Chart

Notes:

1. See datasheet for absolute maximum and minimum recommended operating conditions.

2. Sillicon operating life design goal is 10 years at 110°C junction temperature.

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TYPICAL CHARACTERISTICS

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

OUTPUT SPECTRUM

0

-20

0

-20

High-Speed Mode

f_IN= 1kHz, -0.5dBFS

f_IN= 1kHz, -20dBFS

32,768 Points

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 3.

Figure 4.

OUTPUT SPECTRUM

NOISE HISTOGRAM

25k

20k

15k

10k

5k

0

High-Speed Mode

Shorted Input

-20 Shorted Input

262,144 Points

-40

-60

-80

-100

-120

-140

-160

-180

0

1

10

100

1k

10k

Frequency (Hz)

Output (mV)

Figure 5.

Figure 6.

OUTPUT SPECTRUM

0

-20

0

-20

High-Resolution Mode

f_IN= 1kHz, -0.5dBFS

32,768 Points

High-Resolution Mode

f_IN= 1kHz, -20dBFS

32,768 Points

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

10

100

1k

10k

10

100

1k

10k

100k

Frequency (Hz)

Figure 7.

Figure 8.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

OUTPUT SPECTRUM

NOISE HISTOGRAM

25k

20k

15k

10k

5k

0

High-Resolution Mode

-20 Shorted Input

Shorted Input

262,144 Points

-40

-60

-80

-100

-120

-140

-160

-180

0

1

10

100

1k

10k

100k

Frequency (Hz)

Output (mV)

Figure 9.

Figure 10.

OUTPUT SPECTRUM

0

-20

0

Low-Power Mode

f_IN= 1kHz, -0.5dBFS

32,768 Points

Low-Power Mode

f_IN= 1kHz, -20dBFS

32,768 Points

-20

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

10

100

1k

10k

100k

10

100

1k

10k

100k

Frequency (Hz)

Figure 11.

Figure 12.

OUTPUT SPECTRUM

NOISE HISTOGRAM

0

25k

Low-Power Mode

Shorted Input

-20 Shorted Input

262,144 Points

20k

15k

10k

5k

-40

-60

-80

-100

-120

-140

-160

-180

0

1

10

100

1k

10k

100k

Frequency (Hz)

Output (mV)

Figure 13.

Figure 14.

12

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

OUTPUT SPECTRUM

0

-20

0

-20

Low-Speed Mode

f_IN= 100Hz, -0.5dBFS

f_IN= 100Hz, -20dBFS

32,768 Points

-40

-60

-80

-100

-120

-140

-160

-100

-120

-140

-160

1

10

100

1k

10k

1

10

100

1k

10k

Frequency (Hz)

Figure 15.

Figure 16.

OUTPUT SPECTRUM

NOISE HISTOGRAM

25k

20k

15k

10k

5k

0

Low-Speed Mode

-20 Shorted Input

Shorted Input

262,144 Points

-40

-60

-80

-100

-120

-140

-160

-180

0

0.1

1

10

100

1k

10k

Frequency (Hz)

Output (mV)

Figure 17.

Figure 18.

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

INPUT AMPLITUDE

0

-20

0

-20

High-Speed Mode

V_IN= -0.5dBFS

High-Speed Mode

f_IN= 1kHz

-40

-60

-80

THD+N

THD

THD+N

THD

-100

-120

-140

-100

-120

-140

10

100

1k

10k

100k

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Input Amplitude (dBFS)

Figure 19.

Figure 20.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

INPUT AMPLITUDE

0

-20

0

-20

High-Resolution Mode

V_IN= -0.5dBFS

High-Resolution Mode

f_IN= 1kHz

-40

-60

-80

THD+N

THD

-100

-120

-140

-100

-120

-140

THD+N

THD

10

100

1k

10k

100k

10k

-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

Input Amplitude (dBFS)

Figure 21.

Figure 22.

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

INPUT AMPLITUDE

0

-20

0

-20

Low-Power Mode

V_IN= -0.5dBFS

Low-Power Mode

f_IN= 1kHz

-40

-60

-80

THD+N

THD

THD+N

THD

-100

-120

-140

-100

-120

-140

10

100

1k

10k

-120

-100

-80

-60

-40

-20

Frequency (Hz)

Input Amplitude (dBFS)

Figure 23.

Figure 24.

TOTAL HARMONIC DISTORTION

vs

FREQUENCY

INPUT AMPLITUDE

0

-20

Low-Speed Mode

V_IN= -0.5dBFS

Low-Speed Mode

-20

-40

-60

-80

THD+N

THD

THD+N

THD

-100

-120

-140

-100

-120

-140

10

100

1k

-120

-100

-80

-60

-40

-20

Frequency (Hz)

Input Amplitude (dBFS)

Figure 25.

Figure 26.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

OFFSET DRIFT HISTOGRAM

GAIN DRIFT HISTOGRAM

400

350

300

250

200

150

100

50

900

800

700

600

500

400

300

200

100

0

Multi-lot data based on

25 units based on

20°C intervals over the

range -40°C to +105°C.

20°C intervals over the

range -40°C to +105°C.

Outliers: T < -20°C

0

Offset Drift (mV/°C)

Gain Drift (ppm/°C)

Figure 27.

Figure 28.

OFFSET WARMUP DRIFT RESPONSE BAND

ADS1278 High-Speed and High-Resolution Modes

ADS1278 Low-Power Mode

GAIN WARMUP DRIFT RESPONSE BAND

ADS1274/78 High-Speed and High-Resolution Modes

ADS1278 Low-Power Mode

40

30

20

10

0

40

30

20

10

0

-10

-20

-30

-40

-20

-30

-40

ADS1278 Low-Speed Mode

ADS1274 High-Speed and High-Resolution Modes

0

50

100

150

200

250

300

350

400

0

50

100

150

200

250

300

350

400

Time (s)

Figure 29.

Figure 30.

OFFSET ERROR HISTOGRAM

GAIN ERROR HISTOGRAM

90

40

35

30

25

20

15

10

5

High-Speed Mode

25 Units

High-Speed Mode

25 Units

80

70

60

50

40

30

20

10

0

Offset (mV)

Gain Error (ppm)

Figure 31.

Figure 32.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

CHANNEL GAIN MATCH HISTOGRAM

CHANNEL OFFSET MATCH HISTOGRAM

100

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

High-Speed Mode

10 Units

High-Speed Mode

10 Units

Channel Gain Match (ppm)

Channel Offset Match (mV)

Figure 33.

Figure 34.

OFFSET AND GAIN

vs

TEMPERATURE

VCOM VOLTAGE OUTPUT HISTOGRAM

400

20

18

16

14

12

10

8

600

500

AVDD = 5V

25 Units, No Load

300

200

100

400

300

200

100

0

Offset

0

6

-100

4

-200

-300

Gain

-200

-300

2

0

-55

-35

-15

5

25

45

65

85

105

125

Temperature (°C)

VCOM Voltage Output (V)

Figure 35.

Figure 36.

REFERENCE INPUT DIFFERENTIAL

IMPEDANCE

vs

SAMPLING MATCH ERROR HISTOGRAM

TEMPERATURE

6.8

6.7

0.68

40

30 units over 3 production lots,

inter-channel combinations.

35

30

25

20

15

10

5

0.67

0.66

0.65

0.64

6.6

6.5

6.4

High Speed and

High Resolution

6.3

6.2

0.63

0.62

Low Speed Mode

0

-55

-40

-20

0

25

45

65

85

105

125

Temperature (°C)

Sampling Match Error (ps)

Figure 37.

Figure 38.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

ANALOG INPUT DIFFERENTIAL IMPEDANCE

vs

TEMPERATURE

14.3

14.2

14.1

170

160

150

140

28.6

28.4

28.2

Low-Speed Mode

14

28

13.9

13.8

13.7

13.6

13.5

27.8

27.6

27.4

27.2

27

High Speed and

High Resolution

130

13.4

13.3

26.8

26.6

120

110

Low Power Mode

13.2

13.1

26.4

26.2

-55

-35

-15

5

25

45

65

85

105

125

-55

-35

-15

5

25

45

65

85

105

125

Temperature (°C)

Figure 39.

Figure 40.

INTEGRAL NONLINEARITY

LINEARITY ERROR

vs

TEMPERATURE

INPUT LEVEL

10

8

6

8

T = +105°C

4

T = +25°C

6

4

2

0

-2

-4

-6

-8

-10

T = -40°C

T = +125°C

0

-55

-35

-15

5

25

45

65

85

105

125

-2.5 -2.0 -1.5 -1.0 -0.5

0

0.5 1.0 1.5 2.0 2.5

Temperature (°C)

V_IN(V)

Figure 41.

Figure 42.

LINEARITY AND TOTAL HARMONIC DISTORTION

vs

NOISE AND LINEARITY

vs

REFERENCE VOLTAGE

INPUT COMMON-MODE VOLTAGE

14

12

10

8

-100

14

12

10

8

14

12

10

8

THD: f_IN= 1kHz, V_IN= -0.5dBFS

-104

-108

-112

-116

-120

-124

-128

Noise

THD

6

Linearity

4

Linearity

2

See Electrical Characteristics for V_REFOperating Range.

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

-0.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Common-Mode Voltage (V)

V_REF(V)

Figure 43.

Figure 44.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

NOISE

vs

NOISE

vs

TEMPERATURE

REFERENCE VOLTAGE

12

10

12

10

8

High-Speed

Low Power Mode

Low-Power

High Speed Mode

8

Low Speed Mode

Low-Speed

6

4

2

6

4

High Resolution Mode

High-Resolution

2

0

See Electrical Characteristics for V_REFOperating Range.

0

-55

-35

-15

5

25

45

65

85

105

125

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Temperature (°C)

V_REF(V)

Figure 45.

Figure 46.

TOTAL HARMONIC DISTORTION AND NOISE

COMMON-MODE REJECTION

vs

CLK

INPUT FREQUENCY

0

-20

14

12

10

8

0

High-Speed Mode

f_CLK> 32.768MHz: V_REF= 2.048V, DVDD = 2.1V

-20

-40

THD: A_IN= f_CLK/5120, -0.5dBFS

Noise: Shorted Input

-40

-60

Noise

-80

6

THD

-80

-100

-120

-140

4

-100

-120

2

0

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

CLK (Hz)

Input Frequency (Hz)

Figure 47.

Figure 48.

POWER-SUPPLY REJECTION

vs

AVDD CURRENT

vs

POWER-SUPPLY FREQUENCY

TEMPERATURE

160

0

140

High Speed and High Resolution Modes

-20

-40

120

100

80

-60

Low Power Mode

AVDD

60

40

-80

Low Speed Mode

DVDD

-100

-120

20

IOVDD

0

-55

-35

-15

5

25

45

65

85

105

125

10

100

1k

10k

100k

1M

Temperature (°C)

Power-Supply Modulation Frequency (Hz)

Figure 49.

Figure 50.

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TYPICAL CHARACTERISTICS (continued)

At T_A= 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, f_CLK= 27 MHz, VREFP = 2.5 V, and

VREFN = 0 V, unless otherwise noted.

DVDD CURRENT

IOVDD CURRENT

vs

TEMPERATURE

0.5

0.4

30

25

20

15

10

High Speed Mode

High Resolution Mode

0.3

0.2

High Speed Mode

Low Power Mode

Low Speed Mode

High Resolution and Low Power Modes

Low Speed Mode

0.1

0

5

0

-55

-35

-15

5

25

45

65

85

105

125

-35

-15

5

25

45

65

85

105

125

Temperature (°C)

Figure 51.

Figure 52.

POWER DISSIPATION

vs

TEMPERATURE

800

700

600

500

High Speed Mode

400

300

High Resolution Mode

Low Power Mode

200

100

Low Speed Mode

0

-55

-35

-15

5

25

45

65

85

105

125

Temperature (°C)

Figure 53.

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OVERVIEW

High-Speed, High-Resolution, Low-Power, and Low-

Speed. Table 2 summarizes the performance of each

mode.

The ADS1278 is an octal 24-bit, delta-sigma ADC

based on the single-channel ADS1271. It offers the

combination of outstanding dc accuracy and superior

ac performance. Figure 54 shows the block diagram.

The converter is comprised of eight advanced, 6th-

order, chopper-stabilized, delta-sigma modulators

followed by low-ripple, linear phase FIR filters. The

In High-Speed mode, the maximum data rate is 128

kSPS (when operating at 128 kSPS, Frame-Sync

format must be used). In High-Resolution mode, the

SNR = 111dB (V_REF= 3.0 V); in Low-Power mode,

the power dissipation is 31 mW/channel; and in Low-

modulators measure the differential input signal, V_IN

=

(AINP – AINN), against the differential reference,

V_REF= (VREFP – VREFN). The digital filters receive

the modulator signal and provide a low-noise digital

output. To allow tradeoffs among speed, resolution,

and power, four operating modes are supported:

Speed mode, the power dissipation is only 7

mW/channel at 10.5 kSPS. The digital filters can be

bypassed, enabling direct access to the modulator

output.

The ADS1278 is configured by simply setting the

appropriate I/O pins—there are no registers to

program. Data are retrieved over a serial interface

that supports both SPI and Frame-Sync formats. The

ADS1278 has a daisy-chainable output and the ability

to synchronize externally, so it can be used

conveniently in systems requiring more than eight

channels.

VREFP

AVDD

VREFN

DVDD

IOVDD

Mod 1

Mod 2

R

S

Modulator

Output

VCOM

V_REF

R

Mod 8

V_IN1

DS

AINP1

AINN1

Digital

DRDY/FSYNC

SCLK

S

Modulator1

SPI

and

Frame-Sync

Interface

Filter1

[8:1]

DOUT

DIN

V_IN2

DS

AINP2

AINN2

Digital

Filter2

Modulator2

TEST[1:0]

FORMAT[2:0]

CLK

Control

Logic

SYNC

[8:1]

PWDN

V_IN4/8

DS

AINP8

AINN8

Digital

Filter8

CLKDIV

S

Modulator8

MODE[1:0]

AGND

DGND

Figure 54. Block Diagram

Table 2. Operating Mode Performance Summary

MODE

High-Speed

High-Resolution

Low-Power

Low-Speed

MAX DATA RATE (SPS)

PASSBAND (kHz)

57,984

SNR (dB)

106

NOISE (μV_RMS

)

POWER/CHANNEL (mW)

128,000

52,734

10,547

8.5

5.5

8.5

8.0

70

64

31

7

23,889

110

23,889

106

4,798

107

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FUNCTIONAL DESCRIPTION

SAMPLING APERTURE MATCHING

The ADS1278 is a delta-sigma ADC consisting of

eight independent converters that digitize eight input

signals in parallel.

The ADS1278 converter operates from the same CLK

input. The CLK input controls the timing of the

modulator sampling instant. The converter is

designed such that the sampling skew, or modulator

sampling aperture match between channels, is

controlled. Furthermore, the digital filters are

synchronized to start the convolution phase at the

same modulator clock cycle. This design results in

excellent phase match among the ADS1278

channels.

The converter is composed of two main functional

blocks to perform the ADC conversions: the

modulator and the digital filter. The modulator

samples the input signal together with sampling the

reference voltage to produce a 1s density output

stream. The density of the output stream is

proportional to the analog input level relative to the

reference voltage. The pulse stream is filtered by the

internal digital filter where the output conversion

result is produced.

Figure 37 shows the inter-device channel sample

matching for the ADS1278.

FREQUENCY RESPONSE

In operation, the input signal is sampled by the

modulator at a high rate (typically 64x higher than the

final output data rate). The quantization noise of the

modulator is moved to a higher frequency range

where the internal digital filter removes it.

Oversampling results in very low levels of noise

within the signal passband.

The digital filter sets the overall frequency response.

The filter uses a multi-stage FIR topology to provide

linear phase with minimal passband ripple and high

stop band attenuation. The filter coefficients are

identical to the coefficients used in the ADS1271. The

oversampling ratio of the digital filter (that is, the ratio

of the modulator sampling to the output data rate, or

f_MOD/f_DATA) is a function of the selected mode, as

shown in Table 3.

Since the input signal is sampled at a very high rate,

input signal aliasing does not occur until the input

signal frequency is at the modulator sampling rate.

This architecture greatly relaxes the requirement of

external antialiasing filters because of the high

modulator sampling rate.

Table 3. Oversampling Ratio versus Mode

MODE SELECTION

High-Speed

OVERSAMPLING RATIO (f_MOD/f_DATA)

64

128

64

High-Resolution

Low-Power

Low-Speed

64

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High-Speed, Low-Power, and Low-Speed Modes

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

The digital filter configuration is the same in High-

Speed, Low-Power, and Low-Speed modes with the

oversampling ratio set to 64. Figure 55 shows the

frequency response in High-Speed, Low-Power, and

Low-Speed modes normalized to f_DATA. Figure 56

shows the passband ripple. The transition from

passband to stop band is shown in Figure 57. The

overall frequency response repeats at 64x multiples

of the modulator frequency f_MOD, as shown in

Figure 58.

0

-20

0.45

0.47

0.49

0.51

0.53

0.55

Normalized Input Frequency (f_IN/f_DATA

)

-40

Figure 57. Transition Band Response for High-

Speed, Low-Power, and Low-Speed Modes

-60

-80

20

0

-100

-120

-140

-20

-40

-60

0

0.2

0.4

0.6

0.8

1.0

Normalized Input Frequency (f_IN/f_DATA

)

-80

-100

-120

-140

-160

Figure 55. Frequency Response for High-Speed,

Low-Power, and Low-Speed Modes

0.02

0

16

32

48

64

Input Frequency (f_IN/f_DATA

)

Figure 58. Frequency Response Out to f_MODfor

High-Speed, Low-Power, and Low-Speed Modes

-0.02

-0.04

-0.06

-0.08

-0.10

These image frequencies, if present in the signal and

not externally filtered, will fold back (or alias) into the

passband, causing errors. The stop band of the

ADS1278 provides 100 dB attenuation of frequencies

that begin just beyond the passband and continue out

to f_MOD. Placing an antialiasing, low-pass filter in front

of the ADS1278 inputs is recommended to limit

possible high-amplitude, out-of-band signals and

noise. Often, a simple RC filter is sufficient. Table 4

lists the image rejection versus external filter order.

0

0.1

0.2

0.3

0.4

0.5

0.6

Normalized Input Frequency (f_IN/f_DATA

)

Figure 56. Passband Response for High-Speed,

Low-Power, and Low-Speed Modes

Table 4. Antialiasing Filter Order Image Rejection

IMAGE REJECTION (dB)

(f_–3dBat f_DATA

)

ANTIALIASING

FILTER ORDER

HS, LP, LS

HR

45

1

2

3

39

75

87

111

129

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High-Resolution Mode

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-10

The oversampling ratio is 128 in High-Resolution

mode. Figure 59 shows the frequency response in

High-Resolution mode normalized to f_DATA. Figure 60

shows the passband ripple, and the transition from

passband to stop band is shown in Figure 61. The

overall frequency response repeats at multiples of the

modulator frequency f_MOD(128 × f_DATA), as shown in

Figure 62. The stop band of the ADS1278 provides

100 dB attenuation of frequencies that begin just

beyond the passband and continue out to f_MOD

.

Placing an antialiasing, low-pass filter in front of the

ADS1278 inputs is recommended to limit possible

high-amplitude out-of-band signals and noise. Often,

a simple RC filter is sufficient. Table 4 lists the image

rejection versus external filter order.

0.45

0.47

0.49

0.51

0.53

0.55

Normalized Input Frequency (f_IN/f_DATA

)

Figure 61. Transition Band Response for High-

Resolution mode

0

-20

20

0

-40

-20

-60

-40

-80

-60

-100

-120

-140

-80

-100

-120

-140

-160

0

0.25

0.50

0.75

1

Normalized Input Frequency (f_IN/f_DATA

)

0

32

64

96

128

Normalized Input Frequency (f_IN/f_DATA

)

Figure 59. Frequency Response for High-

Resolution Mode

Figure 62. Frequency Response Out to f_MODfor

High-Resolution Mode

0.02

0

-0.02

-0.04

-0.06

-0.08

-0.10

0

0.1

0.2

0.3

0.4

0.5

0.6

Normalized Input Frequency (f_IN/f_DATA

)

Figure 60. Passband Response for High-

Resolution Mode

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Table 5. Ideal Output Code versus Input Signal

PHASE RESPONSE

INPUT SIGNAL V_IN

(AINP – AINN)

The ADS1278 incorporates a multiple stage, linear

phase digital filter. Linear phase filters exhibit

constant delay time versus input frequency (constant

group delay). This characteristic means the time

delay from any instant of the input signal to the same

instant of the output data is constant and is

independent of input signal frequency. This behavior

results in essentially zero phase errors when

analyzing multi-tone signals.

IDEAL OUTPUT CODE⁽¹⁾

≥ +V_REF

7FFFFFh

) V_REF

2²³* 1

0

000001h

000000h

FFFFFFh

* V_REF

2²³* 1

2²³

ǒ

Ǔ

v −V_REF

800000h

SETTLING TIME

2²³* 1

As with frequency and phase response, the digital

filter also determines settling time. Figure 63 shows

the output settling behavior after a step change on

the analog inputs normalized to conversion periods.

The X-axis is given in units of conversion. Note that

after the step change on the input occurs, the output

data change very little prior to 30 conversion periods.

The output data are fully settled after 76 conversion

periods for High-Speed and Low-Power modes, and

78 conversion periods for High-Resolution mode.

(1) Excludes effects of noise, INL, offset, and gain errors.

ANALOG INPUTS (AINP, AINN)

The ADS1278 measures each differential input signal

V_IN= (AINP – AINN) against the common differential

reference V_REF= (VREFP – VREFN). The most

positive measurable differential input is +V_REF, which

produces the most positive digital output code of

7FFFFFh. Likewise, the most negative measurable

differential input is –V_REF, which produces the most

negative digital output code of 800000h.

Final Value

100

For optimum performance, the inputs of the ADS1278

are intended to be driven differentially. For single-

ended applications, one of the inputs (AINP or AINN)

can be driven while the other input is fixed (typically

to AGND or 2.5 V). Fixing the input to 2.5 V permits

bipolar operation, thereby allowing full use of the

entire converter range.

Fully Settled Data

at 76 Conversions

(78 Conversions for

High-Resolution mode)

Initial Value

0

While the ADS1278 measures the differential input

signal, the absolute input voltage is also important.

This value is the voltage on either input (AINP or

AINN) with respect to AGND. The range for this

voltage is:

0

10

20

30

40

50

60

70

80

Conversions (1/f_DATA

)

Figure 63. Step Response

–0.1 V < (AINN or AINP) < AVDD + 0.1 V

If either input is taken below –0.4 V or above

(AVDD + 0.4 V), ESD protection diodes on the inputs

may turn on. If these conditions are possible, external

Schottky clamp diodes or series resistors may be

required to limit the input current to safe values (see

the Absolute Maximum Ratings table).

DATA FORMAT

The ADS1278 outputs 24 bits of data in twos

complement format.

A positive full-scale input produces an ideal output

code of 7FFFFFh, and the negative full-scale input

produces an ideal output code of 800000h. The

output clips at these codes for signals exceeding full-

scale. Table 5 summarizes the ideal output codes for

different input signals.

The ADS1278 is a very high-performance ADC. For

optimum performance, it is critical that the appropriate

circuitry be used to drive the ADS1278 inputs. See

the Application Information section for several

recommended circuits.

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The ADS1278 uses switched-capacitor circuitry to

measure the input voltage. Internal capacitors are

charged by the inputs and then discharged. Figure 64

shows a conceptual diagram of these circuits. Switch

S₂represents the net effect of the modulator circuitry

in discharging the sampling capacitor; the actual

implementation is different. The timing for switches S₁

and S₂is shown in Figure 65. The sampling time

AINP

AINN

Z_eff= 14kW ´ (6.75MHz/f_MOD

)

(t_SAMPLE

) is the inverse of modulator sampling

frequency (f_MOD) and is a function of the mode, the

CLKDIV input, and CLK frequency, as shown in

Table 6.

Figure 66. Effective Input Impedances

VOLTAGE REFERENCE INPUTS

(VREFP, VREFN)

AVDD AGND

The voltage reference for the ADS1278 ADC is the

differential voltage between VREFP and VREFN:

V_REF= (VREFP – VREFN). The voltage reference is

common to all channels. The reference inputs use a

structure similar to that of the analog inputs with the

equivalent circuitry on the reference inputs shown in

Figure 67. As with the analog inputs, the load

presented by the switched capacitor can be modeled

with an effective impedance, as shown in Figure 68.

However, the reference input impedance depends on

the number of active (enabled) channels in addition to

f_MOD. As a result of the change of reference input

impedance caused by enabling and disabling

channels, the regulation and setting time of the

external reference should be noted, so as not to

affect the readings.

S₁

AINP

S₂

9pF

AINN

S₁

AGND AVDD

ESD Protection

Figure 64. Equivalent Analog Input Circuitry

t_SAMPLE= 1/f_MOD

VREFP

VREFN

ON

S₁

OFF

ON

S₂

AGND

AVDD

AGND

AVDD

OFF

Figure 65. S₁and S₂Switch Timing for Figure 64

ESD

Protection

Table 6. Modulator Frequency (f_MOD) Mode

Selection

MODE SELECTION

High-Speed

CLKDIV

f_MOD

f_CLK/4

f_CLK/8

f_CLK/4

f_CLK/40

f_CLK/8

1

0

1

0

High-Resolution

Figure 67. Equivalent Reference Input Circuitry

Low-Power

Low-Speed

VREFP

VREFN

The average load presented by the switched

capacitor input can be modeled with an effective

differential impedance, as shown in Figure 66. Note

5.2kW

Z_eff

=

´ (6.75MHz/f_MOD)

N

that the effective impedance is a function of f_MOD

.

N = number of active channels.

Figure 68. Effective Reference Impedance

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Table 7. Clock Input Options

ESD diodes protect the reference inputs. To keep

these diodes from turning on, make sure the voltages

on the reference pins do not go below AGND by

more than 0.4 V, and likewise do not exceed AVDD

by 0.4 V. If these conditions are possible, external

Schottky clamp diodes or series resistors may be

required to limit the input current to safe values (see

the Absolute Maximum Ratings table).

MODE

MAX f_CLK

DATA RATE

(SPS)

SELECTION

(MHz)

32.768

27

CLKDIV f_CLK/f_DATA

High-Speed

1

0

1

0

256

512

128,000

52,734

High-Resolution

27

512

Low-Power

Low-Speed

52,734

10,547

13.5

27

256

2,560

512

Note that the valid operating range of the reference

inputs is limited to the following parameters:

5.4

–0.1 V ≤ VREFN ≤ +0.1 V

MODE SELECTION (MODE)

VREFN + 0.5 V ≤ VREFP ≤ AVDD + 0.1 V

The ADS1278 supports four modes of operation:

High-Speed, High-Resolution, Low-Power, and Low-

Speed. The modes offer optimization of speed,

resolution, and power. Mode selection is determined

by the status of the digital input MODE[1:0] pins, as

shown in Table 8. The ADS1278 continually monitors

the status of the MODE pin during operation.

CLOCK INPUT (CLK)

The ADS1278 requires a clock input for operation.

The individual converters of the ADS1278 operate

from the same clock input. At the maximum data rate,

the clock input can be either 27 MHz or 13.5 MHz for

Low-Power mode, or 2 7MHz or 5.4 MHz for Low-

Speed mode, determined by the setting of the

CLKDIV input. For High-Speed mode, the maximum

CLK input frequency is 32.768 MHz. For High-

Resolution mode, the maximum CLK input frequency

is 27 MHz. The selection of the external clock

frequency (f_CLK) does not affect the resolution of the

ADS1278. Use of a slower f_CLKcan reduce the power

consumption of an external clock buffer. The output

data rate scales with clock frequency, down to a

minimum clock frequency of f_CLK= 100 kHz. Table 7

summarizes the ratio of the clock input frequency

(f_CLK) to data rate (f_DATA), maximum data rate and

corresponding maximum clock input for the four

operating modes.

Table 8. Mode Selection

(1)

MODE[1:0]

MODE SELECTION

High-Speed

MAX f_DATA

128,000

52,734

00

01

10

11

High-Resolution

Low-Power

52,734

Low-Speed

10,547

(1) f_CLK= 27 MHz max (32.768MHz max in High-Speed mode).

When using the SPI protocol, DRDY is held high after

a mode change occurs until settled (or valid) data are

ready; see Figure 69 and Table 9.

In Frame-Sync protocol, the DOUT pins are held low

after a mode change occurs until settled data are

ready; see Figure 69 and Table 9. Data can be read

from the device to detect when DOUT changes to

logic 1, indicating that the data are valid.

As with any high-speed data converter, a high-quality,

low-jitter clock is essential for optimum performance.

Crystal clock oscillators are the recommended clock

source. Make sure to avoid excess ringing on the

clock input; keeping the clock trace as short as

possible, and using a 50-Ω series resistor placed

close to the source end, often helps.

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MODE[1:0]

Pins

ADS1278

Mode

New Mode

t_NDR-SPI

SPI

DRDY

DOUT

Protocol

New Mode

Valid Data Ready

t_NDR-FS

Frame-Sync

Protocol

New Mode

Valid Data on DOUT

Figure 69. Mode Change Timing

Table 9. New Data After Mode Change

SYMBOL

t_NDR-SPI

t_NDR-FS

DESCRIPTION

MIN

TYP

MAX

129

UNITS

Time for new data to be ready (SPI)

Time for new data to be ready (Frame-Sync)

Conversions (1/f_DATA

)

127

128

Conversions (1/f_DATA

SYNCHRONIZATION (SYNC)

See Figure 71 for the Frame-Sync format timing

requirement.

The ADS1278 can be synchronized by pulsing the

SYNC pin low and then returning the pin high. When

the pin goes low, the conversion process stops, and

the internal counters used by the digital filter are

reset. When the SYNC pin returns high, the

conversion process restarts. Synchronization allows

the conversion to be aligned with an external event,

such as the changing of an external multiplexer on

the analog inputs, or by a reference timing pulse.

After synchronization, indication of valid data

depends on whether SPI or Frame-Sync format was

used.

In the SPI format, DRDY goes high as soon as SYNC

is taken low; see Figure 70. After SYNC is returned

high, DRDY stays high while the digital filter is

settling. Once valid data are ready for retrieval,

DRDY goes low.

Because the ADS1278 converters operate in parallel

from the same master clock and use the same SYNC

input control, they are always in synchronization with

each other. The aperture match among internal

channels is typically less than 500 ps. However, the

synchronization of multiple devices is somewhat

different. At device power-on, variations in internal

reset thresholds from device to device may result in

uncertainty in conversion timing.

In the Frame-Sync format, DOUT goes low as soon

as SYNC is taken low; see Figure 71. After SYNC is

returned high, DOUT stays low while the digital filter

is settling. Once valid data are ready for retrieval,

DOUT begins to output valid data. For proper

synchronization, FSYNC, SCLK, and CLK must be

established before taking SYNC high, and must then

remain running. If the clock inputs (CLK, FSYNC or

SCLK) are subsequently interrupted or reset, re-

assert the SYNC pin.

The SYNC pin can be used to synchronize multiple

devices to within the same CLK cycle. Figure 70

illustrates the timing requirement of SYNC and CLK

in SPI format.

For consistent performance, re-assert SYNC after

device power-on when data first appear.

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t_CSHD

CLK

t_SCSU

t_SYN

SYNC

DRDY

t_NDR

Figure 70. Synchronization Timing (SPI Protocol)

Table 10. SPI Protocol

SYMBOL

t_CSHD

t_SCSU

t_SYN

DESCRIPTION

MIN

10

5

TYP

MAX

UNITS

CLK to SYNC hold time

SYNC to CLK setup time

Synchronize pulse width

Time for new data to be ready

ns

1

CLK periods

t_NDR

129

Conversions (1/f_DATA)

t_CSHD

CLK

t_SCSU

t_SYN

SYNC

FSYNC

DOUT

t_NDR

Valid Data

Figure 71. Synchronization Timing (Frame-Sync Protocol)

Table 11. Frame-Sync Protocol

SYMBOL

t_CSHD

t_SCSU

t_SYN

DESCRIPTION

MIN

10

5

TYP

MAX

UNITS

CLK to SYNC hold time

SYNC to CLK setup time

Synchronize pulse width

Time for new data to be ready

ns

1

CLK periods

Conversions (1/f_DATA)

t_NDR

127

128

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POWER-DOWN (PWDN)

3. Detect for non-zero data in the powered-up

channel.

The channels of the ADS1278 can be independently

powered down by use of the PWDN inputs. To enter

the power-down mode, hold the respective PWDN pin

low for at least two CLK cycles. To exit power-down,

return the corresponding PWDN pin high. Note that

when all channels are powered down, the ADS1278

enters a microwatt (μW) power state where all

internal biasing is disabled. In this state, the

TEST[1:0] input pins must be driven; all other input

pins can float. The ADS1278 outputs remain driven.

After powering up one or more channels, the

channels are synchronized to each other. It is not

necessary to use the SYNC pin to synchronize them.

When a channel is powered down in TDM data

format, the data for that channel are either forced to

zero (fixed-position TDM data mode) or replaced by

shifting the data from the next channel into the

vacated data position (dynamic-position TDM data

mode).

As shown in Figure 72 and Table 12, a maximum of

130 conversion cycles must elapse for SPI interface,

and 129 conversion cycles must elapse for Frame-

Sync, before reading data after exiting power-down.

Data from channels already running are not affected.

The user software can perform the required delay

time in any of the following ways:

In Discrete data format, the data are always forced to

zero. When powering-up a channel in dynamic-

position TDM data format mode, the channel data

remain packed until the data are ready, at which time

the data frame is expanded to include the just-

powered channel data. See the Data Format section

for details.

1. Count the number of data conversions after

taking the PWDN pin high.

2. Delay 129/f_DATAor 130/f_DATAafter taking the

PWDN pins high, then read data.

· · ·

CLK

t_PWDN

t_NDR

PWDN

DRDY/FSYNC⁽¹⁾

DOUT

(Discrete Data Output Mode)

Post Power-Up Data

Normal Position

DOUT1

(TDM Mode, Dynamic Position)

Normal Position

Data Shifts Position

DOUT1

(TDM Mode, Fixed Position)

Normal Position

Data Remains in Position

Normal Position

Figure 72. Power-Down Timing

Table 12. Power-Down Timing

SYMBOL

t_PWDN

t_NDR

DESCRIPTION

MIN

TYP

MAX

UNITS

PWDN pulse width to enter Power-Down mode

Time for new data ready (SPI)

2

CLK periods

129

128

130

129

Conversions (1/f_DATA

)

t_NDR

Time for new data ready (Frame-Sync)

Conversions (1/f_DATA

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FORMAT[2:0]

Even though the SCLK input has hysteresis, it is

recommended to keep SCLK as clean as possible to

prevent glitches from accidentally shifting the data.

Data can be read from the ADS1278 with two

interface protocols (SPI or Frame-Sync) and several

options of data formats (TDM/Discrete and

Fixed/Dynamic data positions). The FORMAT[2:0]

inputs are used to select among the options. Table 13

lists the available options. See the DOUT Modes

section for details of the DOUT Mode and Data

Position.

SCLK may be run as fast as the CLK frequency.

SCLK may be either in free-running or stop-clock

operation between conversions. Note that one f_CLKis

required after the falling edge of DRDY until the first

rising edge of SCLK. For best performance, limit

f_SCLK/f_CLKto ratios of 1, 1/2, 1/4, 1/8, etc. When the

device is configured for modulator output, SCLK

becomes the modulator clock output (see the

Modulator Output section).

Table 13. Data Output Format

INTERFACE

PROTOCOL

DOUT

MODE

DATA

POSITION

FORMAT[2:0]

DRDY/FSYNC (SPI Format)

000

001

010

011

100

101

110

SPI

TDM

Dynamic

Fixed

—

In the SPI format, this pin functions as the DRDY

output. It goes low when data are ready for retrieval

and then returns high on the falling edge of the first

subsequent SCLK. If data are not retrieved (that is,

SCLK is held low), DRDY pulses high just before the

next conversion data are ready, as shown in

Figure 73. The new data are loaded within one CLK

cycle before DRDY goes low. All data must be shifted

out before this time to avoid being overwritten.

SPI

Discrete

TDM

Frame-Sync

Modulator Mode

Dynamic

Fixed

—

TDM

Discrete

—

SERIAL INTERFACE PROTOCOLS

Data are retrieved from the ADS1278 using the serial

interface. Two protocols are available: SPI and

Frame-Sync. The same pins are used for both

interfaces: SCLK, DRDY/FSYNC, DOUT[8:1], and

DIN. The FORMAT[2:0] pins select the desired

interface protocol.

1/f_CLK

1/f_DATA

DRDY

SCLK

Figure 73. DRDY Timing with No Readback

SPI SERIAL INTERFACE

DOUT

The SPI-compatible format is a read-only interface.

Data ready for retrieval are indicated by the falling

DRDY output and are shifted out on the falling edge

of SCLK, MSB first. The interface can be daisy-

chained using the DIN input when using multiple

devices. See the Daisy-Chaining section for more

information.

The conversion data are output on DOUT[8:1]. The

MSB data are valid on DOUT[8:1] after DRDY goes

low. Subsequent bits are shifted out with each falling

edge of SCLK. If daisy-chaining, the data shifted in

using DIN appear on DOUT after all channel data

have been shifted out. When the device is configured

for modulator output, DOUT[8:1] becomes the

modulator data output for each channel (see the

Modulator Output section).

NOTE: The SPI format is limited to a CLK input

frequency of 27 MHz, maximum. For CLK input

operation above 27 MHz (High-Speed mode only),

use Frame-Sync format.

DIN

SCLK

This input is used when multiple ADS1278s are to be

daisy-chained together. The DOUT1 pin of the first

device connects to the DIN pin of the next, etc. It can

be used with either the SPI or Frame-Sync formats.

Data are shifted in on the falling edge of SCLK. When

using only one ADS1278, tie DIN low. See the Daisy-

Chaining section for more information.

The serial clock (SCLK) features a Schmitt-triggered

input and shifts out data on DOUT on the falling

edge. It also shifts in data on the falling edge on DIN

when this pin is being used for daisy-chaining. The

device shifts data out on the falling edge and the user

normally shifts this data in on the rising edge.

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DOUT

FRAME-SYNC SERIAL INTERFACE

The conversion data are shifted out on DOUT[8:1].

The MSB data become valid on DOUT[8:1] after

FSYNC goes high. The subsequent bits are shifted

out with each falling edge of SCLK. If daisy-chaining,

the data shifted in using DIN appear on DOUT[8:1]

after all channel data have been shifted out. When

the device is configured for modulator output, DOUT

becomes the modulator data output (see the

Modulator Output section).

Frame-Sync format is similar to the interface often

used on audio ADCs. It operates in slave

fashion—the user must supply framing signal FSYNC

(similar to the left/right clock on stereo audio ADCs)

and the serial clock SCLK (similar to the bit clock on

audio ADCs). The data are output MSB first or left-

justified on the rising edge of FSYNC. When using

Frame-Sync format, the FSYNC and SCLK inputs

must be continuously running with the relationships

shown in the Frame-Sync Timing Requirements.

DIN

SCLK

This input is used when multiple ADS1278s are to be

daisy-chained together. It can be used with either SPI

or Frame-Sync formats. Data are shifted in on the

falling edge of SCLK. When using only one

ADS1278, tie DIN low. See the Daisy-Chaining

section for more information.

The serial clock (SCLK) features a Schmitt-triggered

input and shifts out data on DOUT on the falling

edge. It also shifts in data on the falling edge on DIN

when this pin is being used for daisy-chaining. Even

though SCLK has hysteresis, it is recommended to

keep SCLK as clean as possible to prevent glitches

from accidentally shifting the data. When using

Frame-Sync format, SCLK must run continuously. If it

is shut down, the data readback will be corrupted.

The number of SCLKs within a frame period (FSYNC

clock) can be any power-of-2 ratio of CLK cycles (1,

1/2, 1/4, etc), as long as the number of cycles is

sufficient to shift the data output from all channels

within one frame. When the device is configured for

modulator output, SCLK becomes the modulator

clock output (see the Modulator Output section).

DOUT MODES

For both SPI and Frame-Sync interface protocols, the

data are shifted out either through individual channel

DOUT pins, in a parallel data format (Discrete mode),

or the data for all channels are shifted out, in a serial

format, through a common pin, DOUT1 (TDM mode).

TDM Mode

In TDM (time-division multiplexed) data output mode,

the data for all channels are shifted out, in sequence,

on a single pin (DOUT1). As shown in Figure 74, the

data from channel 1 are shifted out first, followed by

channel 2 data, etc. After the data from the last

channel are shifted out, the data from the DIN input

follow. The DIN is used to daisy-chain the data output

from an additional ADS1278 or other compatible

device. Note that when all channels of the ADS1278

are disabled, the interface is disabled, rendering the

DIN input disabled as well. When one or more

channels of the device are powered down, the data

format of the TDM mode can be fixed or dynamic.

DRDY/FSYNC (Frame-Sync Format)

In Frame-Sync format, this pin is used as the FSYNC

input. The frame-sync input (FSYNC) sets the frame

period, which must be the same as the data rate. The

required number of f_CLKcycles to each FSYNC period

depends on the mode selection and the CLKDIV

input. Table 7 indicates the number of CLK cycles to

each frame (f_CLK/f_DATA). If the FSYNC period is not

the proper value, data readback will be corrupted.

SCLK

1

2

23

24

25

47

48

49

71

73

95

96

97

167

168

169

191

192

193

194

195

72

DOUT1

CH1

CH2

CH3

CH4

CH5

CH7

CH8

DIN

DRDY

(SPI)

FSYNC

(Frame-Sync)

Figure 74. TDM Mode (All Channels Enabled)

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TDM Mode, Fixed-Position Data

TDM Mode, Dynamic Position Data

In this TDM data output mode, the data position of

the channels remain fixed, regardless of whether the

channels are powered down. If a channel is powered

down, the data are forced to zero but occupy the

same position within the data stream. Figure 75

shows the data stream with channel 1 and channel 3

powered down.

In this TDM data output mode, when a channel is

powered down, the data from higher channels shift

one position in the data stream to fill the vacated data

slot. Figure 76 shows the data stream with channel 1

and channel 3 powered down.

Discrete Data Output Mode

In Discrete data output mode, the channel data are

shifted out in parallel using individual channel data

output pins DOUT[8:1]. After the 24th SCLK, the

channel data are forced to zero. The data are also

forced to zero for powered down channels. Figure 77

shows the discrete data output format.

SCLK

1

2

23

24

25

47

48

49

71

72

73

95

96

97

167

168

169

191

192

193

194

195

DOUT1

CH1

CH2

CH3

CH4

CH5

CH7

CH8

DIN

DRDY

(SPI)

FSYNC

(Frame-Sync)

Figure 75. TDM Mode, Fixed-Position Data (Channels 1 and 3 Shown Powered Down)

SCLK

1

2

23

24

25

47

48

49

50

119

120

121

143

144

145

146

CH2

CH4

CH5

CH7

CH8

DIN

DOUT1

DRDY

(SPI)

FSYNC

(Frame- Sync)

Figure 76. TDM Mode, Dynamic Position Data (Channels 1 and 3 Shown Powered Down)

32

ADS1278-EP

www.ti.com.cn

ZHCSAC0 –AUGUST 2012

SCLK

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

1

2

22

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

23

24

25

26

DRDY

(SPI)

FSYNC

(Frame-Sync)

Figure 77. Discrete Data Output Mode

Table 14. Maximum Channels in a Daisy-Chain

(f_SCLK= f_CLK) (continued)

DAISY-CHAINING

(f_SCLK= f_CLK

)

Multiple ADS1278s can be daisy-chained together to

output data on a single pin. The DOUT1 data output

pin of one device is connected to the DIN of the next

device. As shown in Figure 78, the DOUT1 pin of

device 1 provides the output data to a controller, and

the DIN of device 2 is grounded. Figure 79 shows the

data format when reading back data.

MAXIMUM NUMBER

OF CHANNELS

MODE SELECTION

High-Speed

CLKDIV

1

0

1

0

10

21

High-Resolution

21

Low-Power

Low-Speed

10

The maximum number of channels that may be

daisy-chained in this way is limited by the frequency

of f_SCLK, the mode selection, and the CLKDIV input.

The frequency of f_SCLKmust be high enough to

completely shift the data out from all channels within

one f_DATAperiod. Table 14 lists the maximum number

106

21

Whether the interface protocol is SPI or Frame-Sync,

it is recommended to synchronize all devices by tying

the SYNC inputs together. When synchronized in SPI

protocol, it is only necessary to monitor the DRDY

output of one ADS1278.

of daisy-chained channels when f_SCLK= f_CLK

.

To increase the number of data channels possible in

a chain, a segmented DOUT scheme may be used,

producing two data streams. Figure 80 illustrates four

ADS1278s, with pairs of ADS1278s daisy-chained

together. The channel data of each daisy-chained

pair are shifted out in parallel and received by the

processor through independent data channels.

In Frame-Sync interface protocol, the data from all

devices are ready after the rising edge of FSYNC.

Since DOUT1 and DIN are both shifted on the falling

edge of SCLK, the propagation delay on DOUT1

creates a setup time on DIN. Minimize the skew in

SCLK to avoid timing violations.

Table 14. Maximum Channels in a Daisy-Chain

33

ADS1278-EP

ZHCSAC0 –AUGUST 2012

www.ti.com.cn

U1

U2

SYNC

CLK

SYNC

DRDY

DRDY Output from Device 1

DOUT from Devices 1 and 2

CLK

DIN

CLK

DIN

DOUT1

SCLK

Note: The number of chained devices is limited by the SCLK rate and device mode.

Figure 78. Daisy-Chaining of Two Devices, SPI Protocol (FORMAT[2:0] = 000 or 001)

SCLK

1

2

25

26

49

50

73

74

97

98

193

194

217

218

385

386

DOUT1

CH1, U1

CH2, U1

CH3, U1

CH4, U1

CH5, U1

CH1, U2

CH2, U2

DIN2

DRDY

(SPI)

FSYNC

(Frame-Sync)

Figure 79. Daisy-Chain Data Format of Figure 78

SYNC

CLK

Serial Data

Devices 3 and 4

U1

U2

U3

U4

SYNC

CLK

SYNC

CLK

SYNC

CLK

SYNC

CLK

Serial Data

DOUT1

DIN

DOUT1

DIN

DOUT1

DIN

Devices 1 and 2

FSYNC

SCLK

FSYNC

SCLK

FSYNC

SCLK

FSYNC

SCLK

FSYNC

Note: The number of chained devices is limited by the SCLK rate and device mode.

Figure 80. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (FORMAT[2:0] = 011 or 100)

34

ADS1278-EP

www.ti.com.cn

ZHCSAC0 –AUGUST 2012

POWER SUPPLIES

space

The ADS1278 has three power supplies: AVDD,

DVDD, and IOVDD. AVDD is the analog supply that

powers the modulator, DVDD is the digital supply that

powers the digital core, and IOVDD is the digital I/O

power supply. The IOVDD and DVDD power supplies

can be tied together if desired (1.8 V). To achieve

rated performance, it is critical that the power

supplies are bypassed with 0.1-μF and 10-μF

capacitors placed as close as possible to the supply

pins. A single 10-μF ceramic capacitor may be

substituted in place of the two capacitors.

MODULATOR OUTPUT

The ADS1278 incorporates a 6th-order, single-bit,

chopper-stabilized modulator followed by a multi-

stage digital filter that yields the conversion results.

The data stream output of the modulator is available

directly, bypassing the internal digital filter. The digital

filter is disabled, reducing the DVDD current, as

shown in Table 15. In this mode, an external digital

filter implemented in an ASIC, FPGA, or similar

device is required. To invoke the modulator output, tie

FORMAT[2:0], as shown in Figure 82. DOUT[8:1]

then becomes the modulator data stream outputs for

each channel and SCLK becomes the modulator

clock output. The DRDY/FSYNC pin becomes an

unused output and can be ignored. The normal

operation of the Frame-Sync and SPI interfaces is

disabled, and the functionality of SCLK changes from

an input to an output, as shown in Figure 82.

Figure 81 shows the start-up sequence of the

ADS1278. At power-on, bring up the DVDD supply

first, followed by IOVDD and then AVDD. Check the

power-supply sequence for proper order, including

the ramp rate of each supply. DVDD and IOVDD may

be sequenced at the same time if the supplies are

tied together. Each supply has an internal reset circuit

whose outputs are summed together to generate a

global power-on reset. After the supplies have

exceeded the reset thresholds, 2¹⁸f_CLKcycles are

counted before the converter initiates the conversion

process. Following the CLK cycles, the data for 129

conversions are suppressed by the ADS1278 to allow

output of fully-settled data. In SPI protocol, DRDY is

held high during this interval. In frame-sync protocol,

DOUT is forced to zero. The power supplies should

be applied before any analog or digital pin is driven.

For consistent performance, assert SYNC after

device power-on when data first appear.

Table 15. Modulator Output Clock Frequencies

MODULATOR

CLOCK OUTPUT

(SCLK)

MODE

[1:0]

CLKDIV

DVDD (mA)

00

01

1

0

1

0

f_CLK/4

f_CLK/8

f_CLK/4

f_CLK/40

f_CLK/8

8

7

4

1

10

11

DVDD

IOVDD

AVDD

1V nom⁽¹⁾

Modulator Data Channel 1

DOUT1

DOUT2

3V nom⁽¹⁾

Modulator Data Channel 2

IOVDD

Internal Reset

CLK

DIN

2¹⁸

129 (max)

t_DATA

FORMAT0

FORMAT1

FORMAT2

f_CLK

DOUT8

SCLK

Modulator Data Channel 8

Modulator Clock Output

DRDY

(SPI Protocol)

DOUT

Figure 82. Modulator Output

(Frame-Sync Protocol)

Valid Data

Figure 81. Start-Up Sequence

35

ADS1278-EP

ZHCSAC0 –AUGUST 2012

www.ti.com.cn

Table 16. Test Mode Pin Map (TEST[1:0] = 11)

In modulator output mode, the frequency of the

modulator clock output (SCLK) depends on the mode

selection of the ADS1278. Table 15 lists the

modulator clock output frequency and DVDD current

versus device mode.

TEST MODE PIN MAP

INPUT PINS

PWDN1

OUTPUT PINS

DOUT1

DOUT2

DOUT3

DOUT4

DOUT5

DOUT6

DOUT7

DOUT8

DIN

PWDN2

Figure 83 shows the timing relationship of the

modulator clock and data outputs.

PWDN3

PWDN4

The data output is a modulated 1s density data

stream. When V_IN= +V_REF, the 1s density is

approximately 80% and when V_IN= –V_REF, the 1s

density is approximately 20%.

PWDN5

PWDN6

PWDN7

PWDN8

Modulator

MODE0

SCLK

Clock Output

MODE1

SYNC

FORMAT0

FORMAT1

FORMAT2

CLKDIV

FSYNC/DRDY

SCLK

Modulator

DOUT

Data Output

(13ns max)

Figure 83. Modulator Output Timing

VCOM OUTPUT

The VCOM pin provides a voltage output equal to

AVDD/2. The intended use of this output is to set the

output common-mode level of the analog input

drivers. The drive capability of the output is limited;

therefore, the output should only be used to drive

high-impedance nodes (> 1 MΩ). In some cases, an

external buffer may be necessary. A 0.1-μF bypass

capacitor is recommended to reduce noise pickup.

PIN TEST USING TEST[1:0] INPUTS

The test mode feature of the ADS1278 allows

continuity testing of the digital I/O pins. In this mode,

the normal functions of the digital pins are disabled

and routed to each other as pairs through internal

logic, as shown in Table 16. The pins in the left

column drive the output pins in the right column.

Note: some of the digital input pins become outputs;

these outputs must be accommodated in the design.

The analog input, power supply, and ground pins all

remain connected as normal. The test mode is

engaged by setting the pins TEST [1:0] = 11. For

normal converter operation, set TEST[1:0] = 00. Do

not use '01' or '10'.

OPA350

VCOM » (AVDD/2)

0.1mF

Figure 84. VCOM Output

36

ADS1278-EP

www.ti.com.cn

ZHCSAC0 –AUGUST 2012

APPLICATION INFORMATION

VREFP and VREFN. The reference input should

be driven by a low-impedance source. For best

performance, the reference should have less than

3 μV_RMSin-band noise. For references with noise

higher than this level, external reference filtering

may be necessary.

To obtain the specified performance from the

ADS1278, the following layout and component

guidelines should be considered.

1. Power Supplies: The device requires three

power supplies for operation: DVDD, IOVDD, and

AVDD. The allowed range for DVDD is 1.65 V to

1.95 V; the range of IOVDD is 1.65 V to 3.6 V;

AVDD is restricted to 4.75 V to 5.25 V. For all

supplies, use

a

10-μF tantalum capacitor,

bypassed with a 0.1-μF ceramic capacitor, placed

close to the device pins. Alternatively, a single

10-μF ceramic capacitor can be used. The

supplies should be relatively free of noise and

should not be shared with devices that produce

voltage spikes (such as relays, LED display

drivers, etc.). If a switching power-supply source

is used, the voltage ripple should be low (less

than 2 mV) and the switching frequency outside

the passband of the converter.

6. Analog Inputs: The analog input pins must be

driven differentially to achieve specified

performance.

A

true differential driver or

2. Ground Plane: A single ground plane connecting

both AGND and DGND pins can be used. If

separate digital and analog grounds are used,

connect the grounds together at the converter.

transformer (ac applications) can be used for this

purpose. Route the analog inputs tracks (AINP,

AINN) as a pair from the buffer to the converter

using short, direct tracks and away from digital

tracks. A 1-nF to 10-nF capacitor should be used

directly across the analog input pins, AINP and

AINN. A low-k dielectric (such as COG or film

type) should be used to maintain low THD.

Capacitors from each analog input to ground can

be used. They should be no larger than 1/10 the

size of the difference capacitor (typically 100 pF)

to preserve the ac common-mode performance.

3. Digital Inputs: It is recommended to source-

terminate the digital inputs to the device with 50-

Ω series resistors. The resistors should be placed

close to the driving end of digital source

(oscillator, logic gates, DSP, etc.) This placement

helps to reduce ringing on the digital lines (ringing

may lead to degraded ADC performance).

4. Analog/Digital Circuits: Place analog circuitry

(input buffer, reference) and associated tracks

together, keeping them away from digital circuitry

(DSP, microcontroller, logic). Avoid crossing

digital tracks across analog tracks to reduce

noise coupling and crosstalk.

7. Component Placement: Place the power supply,

analog input, and reference input bypass

capacitors as close as possible to the device

pins. This layout is particularly important for

small-value ceramic capacitors. Larger (bulk)

decoupling capacitors can be located farther from

the device than the smaller ceramic capacitors.

5. Reference Inputs: It is recommended to use a

minimum 10-μF tantalum with a 0.1-μF ceramic

capacitor directly across the reference inputs,

37

GENERIC PACKAGE VIEW

PAP 64

10 x 10, 0.5 mm pitch

HTQFP - 1.2 mm max height

QUAD FLATPACK

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4226442/A

www.ti.com

PACKAGE OUTLINE

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

SCALE 1.300

PLASTIC QUAD FLATPACK

10.2

9.8

B

NOTE 3

64

49

PIN 1 ID

1

48

10.2

9.8

12.2

TYP

11.8

NOTE 3

16

33

17

32

A

0.27

64X

60X 0.5

0.17

0.08

C A B

4X 7.5

C

SEATING PLANE

1.2 MAX

(0.127)

TYP

SEE DETAIL A

17

32

0.25

GAGE PLANE

(1)

33

16

0.15

0.05

0.08 C

0 -7

0.75

0.45

65

7.00

5.99

DETAIL A

A

17

TYPICAL

1

48

49

64

4218924/A 01/2022

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs.

4. Strap features may not be present.

5. Reference JEDEC registration MS-026.

www.ti.com

EXAMPLE BOARD LAYOUT

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

8)

NOTE 8

(

7)

SYMM

SOLDER MASK

49

64

DEFINED PAD

64X (1.5)

(R0.05)

TYP

1

48

64X (0.3)

65

(11.4)

SYMM

(1.3 TYP)

60X (0.5)

33

16

(

0.2) TYP

VIA

METAL COVERED

BY SOLDER MASK

17

32

SEE DETAILS

(1.3 TYP)

(11.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:6X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4218924/A 01/2022

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. This package is designed to be soldered to a thermal pad on the board. See technical brief, Powerpad thermally enhanced package,

Texas Instruments Literature No. SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).

9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled,

plugged or tented.

10. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

TM

PAP0064G

PowerPAD TQFP - 1.2 mm max height

PLASTIC QUAD FLATPACK

(

7)

BASED ON 0.125

THICK STENCIL

SYMM

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

64

49

64X (1.5)

1

48

64X (0.3)

(R0.05) TYP

SYMM

65

(11.4)

60X (0.5)

33

16

METAL COVERED

BY SOLDER MASK

17

32

(11.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD

100% PRINTED SOLDER COVERAGE BY AREA

SCALE:6X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

7.83 X 7.83

7.0 X 7.0 (SHOWN)

6.39 X 6.39

0.125

0.15

0.175

5.92 X 5.92

4218924/A 01/2022

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS1278-EP
厂家：	TEXAS INSTRUMENTS
描述：	增强型产品：八路、144kHz、24 位同步采样 Σ-Δ ADC
文件：	总44页 (文件大小：2059K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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