ADS1278MHFQ-MLS [TI]
抗辐射加固 24 位 8 通道同步采样 Δ-Σ ADC | HFQ | 84 | -55 to 125;
| 型号： | ADS1278MHFQ-MLS |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 抗辐射加固 24 位 8 通道同步采样 Δ-Σ ADC | HFQ | 84 | -55 to 125 |
| 文件： | 总57页 (文件大小：1770K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
ADS1278-SP 耐辐射 8 通道同步采样
24 位模数转换器
1 特性
3 说明
1
•
耐辐射
ADS1278-SP（八通道）是一款数据速率高达每秒
12.8 万个采样 (128kSPS) 的 24 位、Σ-Δ 模数转换器
(ADC)，可支持八通道同步采样。
–
–
–
TID 75krad (Si)
TID 辐射批次验收测试 (RLAT) 待定
在 125°C 的环境下，单粒子锁定 (SEL) 对于
LET 的抗扰度为 68MeV-cm2/mg
传统上来讲，提供良好漂移性能的工业用三角积分
ADC 使用带有较大通带衰减的数字滤波器。因此，它
们的信号带宽有限并且主要适合于 dc 测量。音频应用
中的 高分辨率 ADC 可提供更大的可用带宽，但其失
调电压和漂移规格均显著低于工业领域对应器件。
ADS1278-SP 对上述类型的转换器进行了整合，可支
持高精度工业测量，且具备出色的直流和交流规格。
•
•
•
八个同步采样通道
高达 128kSPS 的数据速率
交流性能：
–
–
–
63KHz 带宽
111dB SNR（高分辨率模式）
-108dB THD
高阶、斩波稳定调制器在低带内噪声情况下实现极低漂
移。板载抽取滤波器抑制调制器和信号带外噪声。这些
ADC 在纹波小于 0.005dB 的情况下提供高达那奎斯特
速率 90% 的可用信号带宽。
•
•
直流精度：
–
–
0.8μV/°C 的温漂
1.3ppm/°C 增益漂移
可选择工作模式:
器件信息(1)
–
–
–
–
高速：128kSPS、106dB SNR
高分辨率：52kSPS、111dB SNR
低功耗：52kSPS、31mW/ch
低速：10kSPS、7mW/ch
器件型号
等级
封装
耐辐射等级 75krad
(Si)；–55°C 至 125°C
ADS1278MHFQ-MLS
84 引脚 HFQ
重量：
耐辐射等级 75krad
(Si)；–55°C 至 115°C
工程样片(2)
ADS1278WHFQ-MLS
ADS1278HFQ/EM
•
•
•
•
•
•
•
线性相位数字滤波器
SPI™或者帧同步串行接口
低采样孔径错误
4.46g(3)
ADS1278EVM-CVAL 陶瓷评估板
EVM
调制器输出选项（数字滤波器旁路）
模拟电源：5V
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 这些部件仅适用于工程评估。部件按照不合规的流程进行加工
处理。这些部件不适用于质检、生产、辐射测试或飞行。这些
零部件无法在 –55°C 至 125°C 的完整 MIL 额定温度范围内或
运行寿命中保证其性能。
数字内核：1.8V
I/O 电源：1.8V 至 3.3V
(3) 重量误差在 ±10% 以内。
2 应用
•
空间系统（卫星、摆渡车、站点）
简化原理图
DVDD
VREFP VREFN AVDD
IOVDD
–
–
–
–
卫星温度和位置检测
轨道观测系统
Input1
Input2
Input3
Input4
Input5
Input6
Input7
Input8
DS
DS
DS
SPI
and
DRDY/FSYNC
SCLK
Frame-
Sync
精密且科学 应用
高精度仪器
DOUT[8:1]
DIN
Interface
DS
DS
DS
DS
DS
Eight
Digital
Filters
TEST[1:0]
FORMAT[2:0]
CLK
Control
Logic
SYNC
PWDN[8:1]
CLKDIV
MODE[1:0]
AGND
DGND
ADS1278-SP
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS937
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
目录
8.2 Functional Block Diagram ....................................... 23
8.3 Feature Description................................................. 23
8.4 Device Functional Modes........................................ 45
Application and Implementation ........................ 46
9.1 Application Information............................................ 46
9.2 Typical Application .................................................. 46
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements: SPI Format............................ 9
7.7 Timing Requirements: Frame-Sync Format............ 11
7.8 Quality Conformance Inspection............................. 11
7.9 Typical Characteristics............................................ 13
Detailed Description ............................................ 22
8.1 Overview ................................................................. 22
9
10 Power Supply Recommendations ..................... 49
11 Layout................................................................... 50
11.1 Layout Guidelines ................................................. 50
11.2 Layout Example .................................................... 51
12 器件和文档支持 ..................................................... 52
12.1 接收文档更新通知 ................................................. 52
12.2 社区资源................................................................ 52
12.3 商标....................................................................... 52
12.4 静电放电警告......................................................... 52
12.5 术语表 ................................................................... 52
13 机械、封装和可订购信息....................................... 53
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (December 2018) to Revision B
Page
•
已更改 将“预告信息”更改为“生产数据”。 ................................................................................................................................ 1
2
版权 © 2018, Texas Instruments Incorporated
ADS1278-SP
www.ti.com.cn
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
5 说明 （续）
四个运行模式可实现速度、分辨率和功率的优化。所有操作直接由引脚控制；无需寄存器编程。该器件具有 –55°C
至 +125°C 的扩展级温度范围，并且可提供 84 引脚 HFQ 封装。
6 Pin Configuration and Functions
HFQ Package
84-Pin CFP
Top View
AINP2
AINN2
AGND
AINP1
AINN1
AGND
AVDD
1
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
AGND
AINN7
AINP7
2
3
4
AGND
5
AINN8
AINP8
6
7
AGND
AVDD
8
AVDD
AGND
AGND
AGND
DGND
TEST0
TEST1
CLKDIV
SYNC
DIN
9
AVDD
10
11
12
13
14
15
16
17
18
19
20
21
AGND
AGND
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5
PWDN6
PWDN7
PWDN8
MODE0
MODE1
DOUT8
DOUT7
DOUT6
DOUT5
Not to scale
Copyright © 2018, Texas Instruments Incorporated
3
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
3, 6, 9, 10,
11, 53, 54,
57, 60, 63,
66, 69, 72,
76, 77, 82
AGND
Analog ground
Analog ground; connect to DGND using a single plane.
AINP1
AINP2
AINP3
AINP4
AINP5
AINP6
AINP7
AINP8
AINN1
AINN2
AINN3
AINN4
AINN5
AINN6
AINN7
AINN8
4
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
1
83
80
67
64
61
58
5
AINP[8:1] Positive analog input, channels 8 through 1.
2
84
81
68
65
62
59
AINN[8:1] Negative analog input, channels 8 through 1.
7, 8, 55, 56,
70, 71, 78,
79
AVDD
Analog power supply
Analog power supply (4.75 V to 5.25 V).
VCOM
VREFN
VREFP
CLK
73
75
74
37
Analog output
Analog input
Analog input
Digital input
AVDD / 2 Unbuffered voltage output.
Negative reference input.
Positive reference input.
Master clock input.
1 = 32.768 MHz (High-Speed mode only) / 27
MHz
0 = 13.5 MHz (low-power) / 5.4 MHz (low-speed)
CLK input divider
control:
CLKDIV
15
Digital input
12, 26, 31,
32, 33, 34
DGND
Digital ground
Digital ground power supply.
DIN
17
25
24
23
22
21
20
19
18
Digital input
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Daisy-chain data input.
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT1 is TDM data output (TDM mode).
DOUT[8:1] Data output for channels 8 through 1.
DRDY/
FSYNC
39
Digital input/output
Frame-Sync protocol: frame clock input; SPI protocol: data ready output.
Digital core power supply (+1.65 V to +1.95 V).
DVDD
35, 36
42
Digital power supply
Digital input
FORMAT0
FORMAT1
FORMAT2
FORMAT[2:0] Selects Frame-Sync/SPI protocol, TDM/discrete data outputs,
fixed/dynamic position TDM data, and modulator mode/normal operating
mode.
41
Digital input
40
Digital input
27, 28, 29,
30
IOVDD
Digital power supply
I/O power supply (+1.65 V to +3.6 V).
4
Copyright © 2018, Texas Instruments Incorporated
ADS1278-SP
www.ti.com.cn
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
44
43
52
51
50
49
48
47
46
45
38
16
13
14
MODE0
MODE1
PWDN1
PWDN2
PWDN3
PWDN4
PWDN5
PWDN6
PWDN7
PWDN8
SCLK
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input/output
Digital input
Digital input
Digital input
MODE[1:0] Selects High-Speed, High-Resolution, Low-Power, or Low-Speed
mode operation.
PWDN[8:1] Power-down control for channels 8 through 1.
Serial clock input, modulator clock output.
Synchronize input (all channels).
SYNC
TEST0
TEST1
TEST[1:0] Test mode
select:
00 = Normal operation
11 = Test mode
01 = Do not use
10 = Do not use
Copyright © 2018, Texas Instruments Incorporated
5
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
6
UNIT
AVDD to AGND
V
V
V
AGND to DGND
0.3
3.6
DVDD, IOVDD to DGND
Momentary
100
10
Input current
Continuous
mA
Analog input to AGND
–0.3
–0.3
–55
–55
–60
AVDD + 0.3
DVDD + 0.3
217
V
V
Digital input or output to DGND
HFQ and HKP Packages
Junction temperature
D Package
°C
°C
175
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
TBD
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
TBD
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
–55
–55
NOM
MAX
125
UNIT
ADS1278MHFQ-MLS
ADS1278WHFQ-MLS
TJ
Operating junction temperature
°C
115
7.4 Thermal Information
ADS1278-SP
HFQ (CFP)
84 PINS
23.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
9.6
11.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.0
ψJB
10.9
RθJC(bot)
7.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2018, Texas Instruments Incorporated
ADS1278-SP
www.ti.com.cn
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
7.5 Electrical Characteristics
All specifications at TA = –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
VREFN = 0 V, and all channels active, unless otherwise noted.
–55°C to +125°C
(ADS1278MHFQ-MLS)
–55°C to +115°C
(ADS1278WHFQ-MLS)
SUBGROUP
PARAMETER
TEST CONDITIONS
UNIT
(1)(2)
MIN
TYP
MAX
MIN
TYP
MAX
ANALOG INPUTS
Full-scale input voltage (FSR(3)
)
VIN = (AINP – AINN)
±VREF
±VREF
V
V
V
AGND –
0.1
AVDD AGND –
AVDD
+ 0.1
Absolute input voltage
AINP or AINN to AGND
VCM = (AINP + AINN) / 2
1, 2, 3
+ 0.1
0.1
Common-mode input voltage (VCM
)
2.5
14
2.5
14
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
Differential
input
impedance
14
14
kΩ
28
28
140
140
DC PERFORMANCE
Resolution
No missing codes
fCLK = 32.768 MHz(4)
fCLK = 27 MHz
1, 2, 3
24
24
Bits
128,000
105,469
52,734
52,734
10,547
128,000
105,469
52,734
52,734
10,547
High-Speed mode
Maximum data
rate (fDATA
High-Resolution mode
Low-Power mode
Low-Speed mode
SPS(5)
)
Differential input, VCM
2.5 V
=
±0.001
2
±0.001
2
Integral nonlinearity (INL)(6)
1, 2, 3
1, 2, 3
±0.0003
±0.0003
% FSR(3)
Offset error
Offset drift
Gain error
Gain drift
0.25
0.8
0.1
1.3
8.5
5.5
8.5
8.0
108
80
2
0.25
0.8
0.1
1.3
8.5
5.5
8.5
8.0
108
80
2
mV
μV/°C
1, 2, 3
0.5
0.5 % FSR
ppm/°C
21
High-Speed mode
Shorted input
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
23
14
23
23
High-Resolution mode Shorted input
13
Noise
μV, rms
21
Low-Power mode
Low-Speed mode
Shorted input
Shorted input
fCM = 60 Hz
21
Common-mode rejection
AVDD
90
90
dB
Power-supply
rejection
DVDD
fPS = 60 Hz
No load
85
85
dB
V
IOVDD
105
105
AVDD /
2
AVDD /
2
VCOM output voltage
AC PERFORMANCE
Crosstalk
f = 1 kHz, –0.5 dBFS(7)
–107
106
110
111
106
107
–108
109
–107
106
110
111
106
107
–108
109
dB
High-Speed mode
4, 5, 6
4, 5, 6
98
98
VREF = 2.5 V
VREF = 3 V
101
101
Signal-to-noise
ratio (SNR)(8)
(unweighted)
High-Resolution mode
dB
Low-Power mode
Low-Speed mode
4, 5, 6
4, 5, 6
4, 5, 6
98
98
98
98
Total harmonic distortion (THD)(9)
VIN = 1 kHz, –0.5 dBFS
–96
–96
dB
dB
Spurious-free dynamic range
(1) For subgroup definitions, please see Quality Conformance Inspection table.
(2) Subgroups apply to –55°C to +125°C column only.
(3) FSR = full-scale range = 2 VREF
.
(4) fCLK = 32.768-MHz max for High-Speed mode and 27-MHz max for all other modes. When fCLK > 27 MHz, operation is limited to Frame-
Sync mode and VREF ≤ 2.6 V.
(5) SPS = samples per second.
(6) Best fit method.
(7) Worst-case channel crosstalk between one or more channels.
(8) Minimum SNR is ensured by the limit of the DC noise specification.
(9) THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
Copyright © 2018, Texas Instruments Incorporated
7
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
All specifications at TA = –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
VREFN = 0 V, and all channels active, unless otherwise noted.
–55°C to +125°C
(ADS1278MHFQ-MLS)
–55°C to +115°C
(ADS1278WHFQ-MLS)
SUBGROUP
PARAMETER
TEST CONDITIONS
UNIT
(1)(2)
MIN
TYP
MAX
MIN
TYP
MAX
Passband ripple
±0.005
±0.005
dB
Hz
0.453
fDATA
0.453
fDATA
Passband
0.49
fDATA
0.49
fDATA
–3-dB bandwidth
Hz
High-Resolution mode
All other modes
4, 5, 6
4, 5, 6
95
95
dB
dB
Stop band
attenuation
100
100
0.547
fDATA
127.45
3 fDATA
0.547
fDATA
127.45
3 fDATA
High-Resolution mode
All other modes
4, 5, 6
4, 5, 6
Stop band
Hz
0.547
fDATA
63.453
fDATA
0.547
fDATA
63.453
fDATA
High-Resolution mode
All other modes
39/fDATA
38/fDATA
78/fDATA
76/fDATA
39/fDATA
38/fDATA
78/fDATA
76/fDATA
Group delay
s
s
High-Resolution mode Complete settling
Settling time
(latency)
All other modes
Complete settling
VOLTAGE REFERENCE INPUTS
fCLK = 27 MHz
fCLK = 32.768 MHz(4)
1, 2, 3
1, 2, 3
0.5
0.5
2.5
2.5
3.1
2.6
0.5
0.5
2.5
2.5
3.1
2.6
Reference input voltage (VREF
(VREF = VREFP – VREFN)
)
V
AGND –
0.1
AGND AGND –
AGND
+ 0.1
Negative reference input (VREFN)
1, 2, 3
1, 2, 3
V
V
+ 0.1
0.1
VREFN
+ 0.5
AVDD
+ 0.1
VREFN
+ 0.5
AVDD
+ 0.1
Positive reference input (VREFP)
High-Speed mode
0.65
0.65
1.3
0.65
0.65
1.3
Reference
Input
impedance
High-Resolution mode
Low-Power mode
Low-Speed mode
kΩ
6.5
6.5
DIGITAL INPUT/OUTPUT (IOVDD = 1.8 V to 3.6 V)
0.7
IOVDD
0.7
IOVDD
VIH
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
IOVDD
IOVDD
V
V
V
0.3
IOVDD
0.3
IOVDD
VIL
DGND
DGND
0.8
IOVDD
0.8
IOVDD
VOH
IOH = 4 mA
IOL = 4 mA
IOVDD
IOVDD
0.2
IOVDD
0.2
IOVDD
VOL
DGND
DGND
V
Input leakage
0 < VIN DIGITAL < IOVDD
High-Speed mode(4)
Other modes
4, 5, 6
4, 5, 6
1, 2, 3
±11
32.768
27
±10
32.768
27
μA
0.1
0.1
0.1
0.1
Master clock rate (fCLK
)
MHz
POWER SUPPLY
AVDD
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
4.75
1.65
1.65
5
5.25
1.95
3.6
11
4.75
1.65
1.65
5
5.25
1.95
3.6
10
V
V
V
DVDD
1.8
1.8
IOVDD
AVDD
1
1
1
1
Power-down
current
DVDD
52
50
μA
IOVDD
1
12
1
11
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
97
97
44
9
148
148
66
97
97
44
9
145
145
64
AVDD current
mA
15
14
8
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
Electrical Characteristics (continued)
All specifications at TA = –55°C to 125°C, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
VREFN = 0 V, and all channels active, unless otherwise noted.
–55°C to +125°C
(ADS1278MHFQ-MLS)
–55°C to +115°C
(ADS1278WHFQ-MLS)
SUBGROUP
PARAMETER
TEST CONDITIONS
UNIT
(1)(2)
MIN
TYP
23
MAX
31
MIN
TYP
23
MAX
30
High-Speed mode
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
High-Resolution mode
Low-Power mode
Low-Speed mode
16
21
16
20
DVDD current
IOVDD current
mA
12
18
12
17
2.5
5
2.5
4.5
1
0.25
0.125
0.125
0.035
530
515
245
50
1.5
0.8
0.8
0.5
805
785
370
85
0.25
0.125
0.125
0.035
530
515
245
50
0.6
0.6
0.3
785
765
355
80
mA
Power
dissipation
mW
7.6 Timing Requirements: SPI Format(1)
For TA = –55°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V.
SYMBOL
tCLK
PARAMETER
MIN
TYP
MAX
UNIT
(2)
CLK period (1 / fCLK
)
37
15
10,000
ns
ns
tCPW
CLK positive or negative pulse width
(3)
tCONV
Conversion period (1 / fDATA
)
256
2560
16
tCLK
ns
(4)
tCD
Falling edge of CLK to falling edge of DRDY
Falling edge of DRDY to rising edge of first SCLK to retrieve data
DRDY falling edge to DOUT MSB valid (propagation delay)
Falling edge of SCLK to rising edge of DRDY
SCLK period
22
18
(4)
tDS
1
tCLK
ns
tMSBPD
(4)
tSD
ns
(5)
tSCLK
tSPW
1
0.4
10
tCLK
tCLK
ns
SCLK positive or negative pulse width
(4) (6)
(4)
tDOHD
tDOPD
tDIST
SCLK falling edge to new DOUT invalid (hold time)
SCLK falling edge to new DOUT valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
32
ns
6
6
ns
(6)
tDIHD
ns
(1) Timing parameters are characterized or assured by design for specified temperature but not production tested.
(2) fCLK = 27-MHz maximum.
(3) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK / fDATA).
(4) Load on DRDY and DOUT = 20 pF.
(5) For best performance, limit fSCLK / fCLK to ratios of 1, 1/2, 1/4, 1/8, etc..
(6) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4 ns.
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tCLK
tCPW
CLK
· · ·
tCPW
tCD
tCONV
DRDY
tSD
tDS
tSCLK
tSPW
SCLK
tSPW
tDOPD
tMSBPD
Bit 23 (MSB)
tDOHD
Bit 22
tDIST
Bit 21
DOUT
DIN
tDIHD
Figure 1. SPI Format Timing Characteristics
10
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
7.7 Timing Requirements: Frame-Sync Format(1)
over operating free-air temperature range (unless otherwise noted)
SYMBOL
PARAMETER
MIN
37
TYP
MAX
UNIT
ns
All modes
10,000
tCLK
CLK period (1 / fCLK)
High-Speed mode only
30.5
12
ns
tCPW
tCS
CLK positive or negative pulse width
ns
Falling edge of CLK to falling edge of SCLK
–0.25
256
1
0.25
tCLK
tCLK
tSCLK
ns
(2)
tFRAME
tFPW
tFS
Frame period (1 / fDATA
)
2560
FSYNC positive or negative pulse width
Rising edge of FSYNC to rising edge of SCLK
Rising edge of SCLK to rising edge of FSYNC
SCLK period(3)
5
tSF
5
ns
tSCLK
tSPW
1
tCLK
tCLK
SCLK positive or negative pulse width
0.4
(4)
tDOHD
SCLK falling edge to old DOUT invalid (hold time)
10
ns
(5)
(5)
tDOPD
SCLK falling edge to new DOUT valid (propagation delay)
FSYNC rising edge to DOUT MSB valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
31
31
ns
ns
ns
ns
tMSBPD
tDIST
6
6
(4)
tDIHD
(1) Timing parameters are characterized or assured by design for specified temperature but not production tested.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK / fDATA).
(3) SCLK must be continuously running and limited to ratios of 1, 1/2, 1/4, and 1/8 of fCLK
.
(4) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4 ns.
(5) Load on DOUT = 20 pF.
tCPW
tCLK
CLK
tCPW
tCS
tFRAME
tFPW
tFPW
FSYNC
SCLK
DOUT
DIN
tFS
tSCLK
tSPW
tSF
tSPW
tMSBPD
Bit 23 (MSB)
tDOPD
tDOHD
Bit 21
Bit 22
tDIST
tDIHD
Figure 2. Frame-Sync Format Timing Characteristics
7.8 Quality Conformance Inspection
MIL-STD-883, Method 5005 - Group A
SUBGROUP
DESCRIPTION
Static tests at
TEMP (°C)
25
1
2
3
4
5
6
7
Static tests at
125
Static tests at
–55
Dynamic tests at
Dynamic tests at
Dynamic tests at
Functional tests at
25
125
–55
25
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Quality Conformance Inspection (continued)
SUBGROUP
DESCRIPTION
Functional tests at
Functional tests at
Switching tests at
Switching tests at
Switching tests at
Setting time at
TEMP (°C)
8A
8B
9
125
–55
25
10
11
12
13
14
125
–55
25
Setting time at
125
–55
Setting time at
12
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
7.9 Typical Characteristics
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
0
-20
0
-20
High-Speed Mode
fIN = 1kHz, -0.5dBFS
32,768 Points
High-Speed Mode
fIN = 1kHz, -20dBFS
32,768 Points
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
10
100
1k
10k
100k
100k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 3. Output Spectrum
Figure 4. Output Spectrum
25k
20k
15k
10k
5k
0
High-Speed Mode
High-Speed Mode
-20 Shorted Input
Shorted Input
262,144 Points
262,144 Points
-40
-60
-80
-100
-120
-140
-160
-180
0
1
10
100
1k
10k
Frequency (Hz)
Output (mV)
Figure 5. Output Spectrum
Figure 6. Noise Histogram
0
-20
0
-20
High-Resolution Mode
High-Resolution Mode
fIN = 1kHz, -0.5dBFS
fIN = 1kHz, -20dBFS
32,768 Points
32,768 Points
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
10
100
1k
10k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 7. Output Spectrum
Figure 8. Output Spectrum
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Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
25k
20k
15k
10k
5k
0
High-Resolution Mode
High-Resolution Mode
Shorted Input
-20 Shorted Input
262,144 Points
262,144 Points
-40
-60
-80
-100
-120
-140
-160
-180
0
1
10
100
1k
10k
100k
100k
100k
Output (mV)
Frequency (Hz)
Figure 10. Noise Histogram
Figure 9. Output Spectrum
0
0
Low-Power Mode
fIN = 1kHz, -0.5dBFS
32,768 Points
Low-Power Mode
fIN = 1kHz, -20dBFS
-20
-40
-20
32,768 Points
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
10
100
1k
10k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 11. Output Spectrum
Figure 12. Output Spectrum
0
25k
Low-Power Mode
Low-Power Mode
-20 Shorted Input
Shorted Input
262,144 Points
262,144 Points
20k
15k
10k
5k
-40
-60
-80
-100
-120
-140
-160
-180
0
1
10
100
1k
10k
Frequency (Hz)
Output (mV)
Figure 13. Output Spectrum
Figure 14. Noise Histogram
14
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
0
0
Low-Speed Mode
fIN = 100Hz, -0.5dBFS
32,768 Points
Low-Speed Mode
fIN = 100Hz, -20dBFS
32,768 Points
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
1
10
100
Frequency (Hz)
1k
10k
1
10
100
1k
10k
Frequency (Hz)
Figure 15. Output Spectrum
Figure 16. Output Spectrum
25k
20k
15k
10k
5k
0
Low-Speed Mode
Low-Speed Mode
-20 Shorted Input
Shorted Input
262,144 Points
262,144 Points
-40
-60
-80
-100
-120
-140
-160
-180
0
0.1
1
10
100
1k
10k
Frequency (Hz)
Output (mV)
Figure 17. Output Spectrum
Figure 18. Noise Histogram
0
-20
0
-20
High-Speed Mode
VIN = -0.5dBFS
High-Speed Mode
fIN = 1kHz
-40
-40
-60
-60
-80
-80
THD+N
THD
THD+N
THD
-100
-120
-140
-100
-120
-140
10
100
1k
Frequency (Hz)
10k
100k
-120
-100
-80
-60
-40
-20
0
Input Amplitude (dBFS)
Figure 19. Total Harmonic Distortion vs Frequency
Figure 20. Total Harmonic Distortion vs Input Amplitude
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Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
0
0
High-Resolution Mode
High-Resolution Mode
fIN = 1kHz
VIN = -0.5dBFS
-20
-20
-40
-40
-60
-60
-80
-80
THD+N
THD
-100
-120
-140
-100
-120
-140
THD+N
THD
10
100
1k
Frequency (Hz)
10k
100k
-120
-100
-80
-60
-40
-20
0
Input Amplitude (dBFS)
Figure 21. Total Harmonic Distortion vs Frequency
Figure 22. Total Harmonic Distortion vs Input Amplitude
0
0
Low-Power Mode
Low-Power Mode
VIN = -0.5dBFS
fIN = 1kHz
-20
-20
-40
-40
-60
-80
-60
-80
THD+N
THD
THD+N
THD
-100
-120
-140
-100
-120
-140
10
100
1k
10k
100k
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Input Amplitude (dBFS)
Figure 23. Total Harmonic Distortion vs Frequency
Figure 24. Total Harmonic Distortion vs Input Amplitude
0
0
Low-Speed Mode
Low-Speed Mode
VIN = -0.5dBFS
-20
-40
-20
-40
-60
-80
-60
-80
THD+N
THD
THD+N
THD
-100
-120
-140
-100
-120
-140
10
100
1k
10k
-120
-100
-80
-60
-40
-20
0
Frequency (Hz)
Input Amplitude (dBFS)
Figure 25. Total Harmonic Distortion vs Frequency
Figure 26. Total Harmonic Distortion vs Input Amplitude
16
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Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
400
350
300
250
200
150
100
50
900
800
700
600
500
400
300
200
100
0
Multi-lot data based on
20°C intervals over the
range -40°C to +105°C.
25 units based on
20°C intervals over the
range -40°C to +105°C.
Outliers: T < -20°C
0
Offset Drift (mV/°C)
Gain Drift (ppm/°C)
Figure 27. Offset Drift Histogram
Figure 28. Gain Drift Histogram
40
30
20
10
0
40
30
20
10
0
ADS1278 High-Speed and High-Resolution Modes
ADS1278 Low-Power Mode
ADS1274/78 High-Speed and High-Resolution Modes
ADS1278 Low-Power Mode
-10
-10
-20
-30
-40
-20
-30
-40
ADS1278 Low-Speed Mode
ADS1278 Low-Speed Mode
ADS1274 High-Speed and High-Resolution Modes
0
50
100
150
200
250
300
350
400
0
50
100
150
200
250
300
350
400
Time (s)
Time (s)
Figure 29. Offset Warmup Drift Response Band
Figure 30. Gain Warmup Drift Response Band
90
40
35
30
25
20
15
10
5
High-Speed Mode
25 Units
High-Speed Mode
25 Units
80
70
60
50
40
30
20
10
0
0
Gain Error (ppm)
Offset (mV)
Figure 32. Gain Error Histogram
Figure 31. Offset Error Histogram
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Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
High-Speed Mode
10 Units
High-Speed Mode
10 Units
Channel Gain Match (ppm)
Channel Offset Match (mV)
Figure 33. Channel Gain Match Histogram
Figure 34. Channel Offset Match Histogram
400
300
200
100
0
600
20
AVDD = 5V
18
16
14
12
10
8
500
400
25 Units, No Load
Offset
300
200
100
0
6
-100
-200
-300
4
-100
2
-200
Gain
0
-300
-55 -35 -15
5
25 45 65 85 105 125
VCOM Voltage Output (V)
Temperature (°C)
Figure 35. Offset and Gain vs Temperature
Figure 36. VCOM Voltage Output Histogram
6.8
0.68
40
35
30
25
20
15
10
5
30 units over 3 production lots,
inter-channel combinations.
6.7
6.6
6.5
0.67
0.66
0.65
0.64
6.4
High Speed and
High Resolution
6.3
0.63
0.62
Low Speed Mode
0
6.2
-55 -40 -20
0
25
Temperature (°C)
45 65 85 105 125
Sampling Match Error (ps)
Figure 37. Sampling Match Error Histogram
Figure 38. Reference Input Differential Impedance vs
Temperature
18
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
170
160
150
140
14.3
14.2
14.1
28.6
28.4
28.2
Low-Speed Mode
14
13.9
13.8
13.7
13.6
13.5
28
27.8
27.6
27.4
27.2
27
High Speed and
High Resolution
130
13.4
13.3
26.8
26.6
120
110
Low Power Mode
13.2
13.1
26.4
26.2
-55 -35 -15
5
25 45 65 85 105 125
-55 -35 -15
5
25 45 65 85 105 125
Temperature (°C)
Temperature (°C)
Figure 40. Analog Input Differential Impedance vs
Temperature
Figure 39. Analog Input Differential Impedance vs
Temperature
10
10
8
6
8
T = +105°C
4
T = +25°C
2
6
4
0
-2
-4
-6
-8
-10
T = -40°C
2
0
T = +125°C
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
-55 -35 -15
5
25 45 65 85 105 125
VIN (V)
Temperature (°C)
Figure 42. Linearity Error vs Input Level
Figure 41. Integral Nonlinearity vs Temperature
14
12
10
8
-100
14
12
10
8
14
12
10
8
THD: fIN = 1kHz, VIN = -0.5dBFS
-104
-108
-112
-116
-120
-124
-128
Noise
THD
6
6
6
Linearity
4
4
4
Linearity
2
2
2
See Electrical Characteristics for VREF Operating Range.
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Common-Mode Voltage (V)
VREF (V)
Figure 43. Linearity and Total Harmonic Distortion vs
Reference Voltage
Figure 44. Noise and Linearity vs Input Common-Mode
Voltage
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Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
12
12
10
8
High-Speed
Low Power Mode
High Speed Mode
Low-Power
10
8
6
Low Speed Mode
Low-Speed
6
4
4
High-Resolution
High Resolution Mode
2
0
2
0
See Electrical Characteristics for VREF Operating Range.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-55 -35 -15
5
25 45 65 85 105 125
VREF (V)
Temperature (°C)
Figure 46. Noise vs Reference Voltage
Figure 45. Noise vs Temperature
0
-20
14
12
10
8
0
High-Speed Mode
fCLK > 32.768MHz: VREF = 2.048V, DVDD = 2.1V
-20
-40
THD: AIN = fCLK/5120, -0.5dBFS
Noise: Shorted Input
-40
-60
-60
Noise
-80
6
THD
-80
-100
-120
-140
4
-100
-120
2
0
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
CLK (Hz)
Input Frequency (Hz)
Figure 47. Total Harmonic Distortion and Noise vs CLK
Figure 48. Common-Mode Rejection vs Input Frequency
160
0
140
-20
High Speed and High Resolution Modes
120
100
-40
-60
80
AVDD
Low Power Mode
60
-80
40
DVDD
-100
-120
Low Speed Mode
20
IOVDD
0
10
100
1k
10k
100k
1M
-55 -35 -15
5
25 45 65 85 105 125
Power-Supply Modulation Frequency (Hz)
Temperature (°C)
Figure 49. Power-Supply Rejection vs Power-Supply
Frequency
Figure 50. AVDD Current vs Temperature
20
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ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
Typical Characteristics (continued)
At TA = 25°C, High-Speed mode, AVDD = 5 V, DVDD = 1.8 V, IOVDD = 3.3 V, fCLK = 27 MHz, VREFP = 2.5 V,
and VREFN = 0 V, unless otherwise noted.
30
25
20
15
10
0.5
High Speed Mode
0.4
High Resolution Mode
0.3
0.2
High Speed Mode
Low Power Mode
Low Speed Mode
High Resolution and Low Power Modes
Low Speed Mode
0.1
0
5
0
-55 -35 -15
5
25 45 65 85 105 125
-55 -35 -15
5
25 45 65 85 105 125
Temperature (°C)
Temperature (°C)
Figure 51. DVDD Current vs Temperature
Figure 52. IOVDD Current vs Temperature
800
700
600
High Speed Mode
500
400
300
High Resolution Mode
Low Power Mode
200
100
0
Low Speed Mode
-55 -35 -15
5
25 45 65 85 105 125
Temperature (°C)
Figure 53. Power Dissipation vs Temperature
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8 Detailed Description
8.1 Overview
The ADS1278-SP is a delta-sigma ADC consisting of eight independent converters that digitize eight input
signals in parallel.
The converter is composed of two main functional blocks to perform the ADC conversions: the modulator and the
digital filter. The modulator samples the input signal together with sampling the reference voltage to produce a 1-
s density output stream. The density of the output stream is proportional to the analog input level relative to the
reference voltage. The pulse stream is filtered by the internal digital filter where the output conversion result is
produced.
In operation, the input signal is sampled by the modulator at a high rate (typically 64x higher than the final output
data rate). The quantization noise of the modulator is moved to a higher frequency range where the internal
digital filter removes it. Oversampling results in very low levels of noise within the signal passband.
Since the input signal is sampled at a very high rate, input signal aliasing does not occur until the input signal
frequency is at the modulator sampling rate. This architecture greatly relaxes the requirement of external
antialiasing filters because of the high modulator sampling rate.
The ADS1278-SP is an octal 24-bit, delta-sigma ADC. It offers the combination of outstanding dc accuracy and
superior ac performance. Functional Block Diagram section shows the block diagram. The converter is
comprised of eight advanced, 6th-order, chopper-stabilized, delta-sigma modulators followed by low-ripple, linear
phase FIR filters. The modulators measure the differential input signal, VIN = (AINP – AINN), against the
differential reference, VREF = (VREFP – VREFN). The digital filters receive the modulator signal and provide a
low-noise digital output. To allow tradeoffs among speed, resolution, and power, four operating modes are
supported:
High-Speed, High-Resolution, Low-Power, and Low-Speed. Table 15 summarizes the performance of each
mode.
In High-Speed mode, the maximum data rate is 128 kSPS (when operating at 128 kSPS, Frame-Sync format
must be used). In High-Resolution mode, the SNR = 111 dB (VREF = 3.0 V); in Low-Power mode, the power
dissipation is 31 mW/channel; and in Low-Speed mode, the power dissipation is only 7 mW/channel at 10.5
kSPS. The digital filters can be bypassed, enabling direct access to the modulator output.
The ADS1278-SP is configured by simply setting the appropriate I/O pins—there are no registers to program.
Data are retrieved over a serial interface that supports both SPI and Frame-Sync formats. The ADS1278-SP has
a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in systems
requiring more than eight channels.
22
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8.2 Functional Block Diagram
VREFP
AVDD
VREFN
DVDD
IOVDD
Mod 1
Mod 2
R
S
Modulator
Output
VCOM
VREF
R
Mod 8
VIN1
DS
AINP1
AINN1
Digital
DRDY/FSYNC
SPI
S
S
Modulator1
Filter1
SCLK
DOUT
DIN
and
Frame-Sync
Interface
[8:1]
VIN2
DS
AINP2
AINN2
Digital
Filter2
Modulator2
TEST[1:0]
FORMAT[2:0]
CLK
Control
Logic
SYNC
[8:1]
PWDN
VIN4/8
DS
AINP8
AINN8
Digital
Filter8
CLKDIV
S
Modulator8
MODE[1:0]
AGND
DGND
8.3 Feature Description
8.3.1 Sampling Aperture Matching
The ADS1278-SP converter operates from the same CLK input. The CLK input controls the timing of the
modulator sampling instant. The converter is designed such that the sampling skew, or modulator sampling
aperture match between channels, is controlled. Furthermore, the digital filters are synchronized to start the
convolution phase at the same modulator clock cycle. This design results in excellent phase match among the
ADS1278-SP channels.
Figure 37 shows the inter-device channel sample matching for the ADS1278-SP.
8.3.2 Frequency Response
The digital filter sets the overall frequency response. The filter uses a multi-stage FIR topology to provide linear
phase with minimal passband ripple and high stop band attenuation. The filter coefficients are identical to the
coefficients used in the ADS1271. The oversampling ratio of the digital filter (that is, the ratio of the modulator
sampling to the output data rate, or fMOD/fDATA) is a function of the selected mode, as shown in Table 1.
Table 1. Oversampling Ratio vs Mode
MODE SELECTION
High-Speed
OVERSAMPLING RATIO (fMOD/fDATA)
64
128
64
High-Resolution
Low-Power
Low-Speed
64
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8.3.2.1 High-Speed, Low-Power, And Low-Speed Modes
The digital filter configuration is the same in High-Speed, Low-Power, and Low-Speed modes with the
oversampling ratio set to 64. Figure 54 shows the frequency response in High-Speed, Low-Power, and Low-
Speed modes normalized to fDATA. Figure 55 shows the passband ripple. The transition from passband to stop
band is shown in Figure 56. The overall frequency response repeats at 64x multiples of the modulator frequency
fMOD, as shown in Figure 57.
0
-20
-40
-60
-80
-100
-120
-140
0
0.2
0.4
0.6
0.8
1.0
Normalized Input Frequency (fIN/fDATA
)
Figure 54. Frequency Response For High-Speed, Low-Power, And Low-Speed Modes
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
0
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Input Frequency (fIN/fDATA
)
Figure 55. Passband Response For High-Speed, Low-Power, And Low-Speed Modes
24
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0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Input Frequency (fIN/fDATA
)
Figure 56. Transition Band Response For High-Speed, Low-Power, and Low-Speed Modes
20
0
-20
-40
-60
-80
-100
-120
-140
-160
0
16
32
48
64
Input Frequency (fIN/fDATA
)
Figure 57. Frequency Response Out To FMOD For High-Speed, Low-Power, And Low-Speed Modes
These image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the
passband, causing errors. The stop band of the ADS1278-SP provides 100-dB attenuation of frequencies that
begin just beyond the passband and continue out to fMOD. Placing an anti-aliasing, low-pass filter in front of the
ADS1278-SP inputs is recommended to limit possible high-amplitude, out-of-band signals and noise. Often, a
simple RC filter is sufficient. Table 2 lists the image rejection versus external filter order.
Table 2. Antialiasing Filter Order Image Rejection
IMAGE REJECTION (dB)
(f–3dB at fDATA
)
ANTIALIASING FILTER ORDER
HS, LP, LS
HR
45
1
2
3
39
75
87
111
129
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8.3.2.2 High-Resolution Mode
The oversampling ratio is 128 in High-Resolution mode. Figure 58 shows the frequency response in High-
Resolution mode normalized to fDATA. Figure 59 shows the passband ripple, and the transition from passband to
stop band is shown in Figure 60. The overall frequency response repeats at multiples of the modulator frequency
fMOD (128 × fDATA), as shown in Figure 61. The stop band of the ADS1278-SP provides 100-dB attenuation of
frequencies that begin just beyond the passband and continue out to fMOD. Placing an antialiasing, low-pass filter
in front of the ADS1278-SP inputs is recommended to limit possible high-amplitude out-of-band signals and
noise. Often, a simple RC filter is sufficient. Table 2 lists the image rejection versus external filter order.
0
-20
-40
-60
-80
-100
-120
-140
0
0.25
0.50
0.75
1
Normalized Input Frequency (fIN/fDATA
)
Figure 58. Frequency Response For High-Resolution Mode
0.02
0
-0.02
-0.04
-0.06
-0.08
-0.10
0
0.1
0.2
0.3
0.4
0.5
0.6
Normalized Input Frequency (fIN/fDATA
)
Figure 59. Passband Response For High-Resolution Mode
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0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
0.45
0.47
0.49
0.51
0.53
0.55
Normalized Input Frequency (fIN/fDATA
)
Figure 60. Transition Band Response For High-Resolution Mode
20
0
-20
-40
-60
-80
-100
-120
-140
-160
0
32
64
96
128
Normalized Input Frequency (fIN/fDATA
)
Figure 61. Frequency Response Out To FMOD For High-Resolution Mode
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8.3.3 Phase Response
The ADS1278-SP incorporates a multiple stage, linear phase digital filter. Linear phase filters exhibit constant
delay time versus input frequency (constant group delay). This characteristic means the time delay from any
instant of the input signal to the same instant of the output data is constant and is independent of input signal
frequency. This behavior results in essentially zero phase errors when analyzing multi-tone signals.
8.3.4 Settling Time
As with frequency and phase response, the digital filter also determines settling time. Figure 62 shows the output
settling behavior after a step change on the analog inputs normalized to conversion periods. The X-axis is given
in units of conversion. Note that after the step change on the input occurs, the output data change very little prior
to 30 conversion periods. The output data are fully settled after 76 conversion periods for High-Speed and Low-
Power modes, and 78 conversion periods for High-Resolution mode.
Final Value
100
Fully Settled Data
at 76 Conversions
(78 Conversions for
High-Resolution mode)
Initial Value
0
0
10
20
30
40
50
60
70
80
Conversions (1/fDATA
)
Figure 62. Step Response
8.3.5 Data Format
The ADS1278-SP outputs 24 bits of data in twos complement format.
A positive full-scale input produces an ideal output code of 7FFFFFh, and the negative full-scale input produces
an ideal output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 3
summarizes the ideal output codes for different input signals.
Table 3. Ideal Output Code Versus Input Signal
INPUT SIGNAL VIN
IDEAL OUTPUT CODE(1)
(AINP – AINN)
≥ +VREF
7FFFFFh
000001h
000000h
FFFFFFh
) VREF
223 * 1
0
* VREF
223 * 1
223
ǒ
Ǔ
v −VREF
800000h
223 1
(1) Excludes effects of noise, INL, offset, and gain errors.
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8.3.6 Analog Inputs (AINP, AINN)
The ADS1278-SP measures each differential input signal VIN = (AINP – AINN) against the common differential
reference VREF = (VREFP – VREFN). The most positive measurable differential input is +VREF, which produces
the most positive digital output code of 7FFFFFh. Likewise, the most negative measurable differential input is
–VREF, which produces the most negative digital output code of 800000h.
For optimum performance, the inputs of the ADS1278-SP are intended to be driven differentially. For single-
ended applications, one of the inputs (AINP or AINN) can be driven while the other input is fixed (typically to
AGND or 2.5 V). Fixing the input to 2.5 V permits bipolar operation, thereby allowing full use of the entire
converter range.
While the ADS1278-SP measures the differential input signal, the absolute input voltage is also important. This
value is the voltage on either input (AINP or AINN) with respect to AGND. The range for this voltage is:
–0.1 V < (AINN or AINP) < AVDD + 0.1 V
If either input is taken below –0.4 V or above (AVDD + 0.4 V), ESD protection diodes on the inputs may turn on.
If these conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the
input current to safe values (see the Absolute Maximum Ratings table).
The ADS1278-SP is a very high-performance ADC. For optimum performance, it is critical that the appropriate
circuitry be used to drive the ADS1278-SP inputs. See the Application Information section for several
recommended circuits.
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The ADS1278-SP uses switched-capacitor circuitry to measure the input voltage. Internal capacitors are charged
by the inputs and then discharged. Figure 63 shows a conceptual diagram of these circuits. Switch S2 represents
the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is
different. The timing for switches S1 and S2 is shown in Figure 64. The sampling time (tSAMPLE) is the inverse of
modulator sampling frequency (fMOD) and is a function of the mode, the CLKDIV input, and CLK frequency, as
shown in Table 4.
AVDD AGND
S1
AINP
S2
9pF
AINN
S1
AGND AVDD
ESD Protection
Figure 63. Equivalent Analog Input Circuitry
tSAMPLE = 1/fMOD
ON
S1
OFF
ON
S2
OFF
Figure 64. S1 and S2 Switch Timing for Figure 63
Table 4. Modulator Frequency (FMOD) Mode Selection
MODE SELECTION
High-Speed
CLKDIV
fMOD
1
1
1
0
1
0
fCLK / 4
fCLK / 4
fCLK / 8
fCLK / 4
fCLK / 40
fCLK / 8
High-Resolution
Low-Power
Low-Speed
The average load presented by the switched capacitor input can be modeled with an effective differential
impedance, as shown in Figure 65. Note that the effective impedance is a function of fMOD
.
AINP
Zeff = 14kW ´ (6.75MHz/fMOD
)
AINN
Figure 65. Effective Input Impedances
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8.3.7 Voltage Reference Inputs
(VREFP, VREFN)
The voltage reference for the ADS1278-SP ADC is the differential voltage between VREFP and VREFN: VREF
=
(VREFP – VREFN). The voltage reference is common to all channels. The reference inputs use a structure
similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in Figure 66. As
with the analog inputs, the load presented by the switched capacitor can be modeled with an effective
impedance, as shown in Figure 67. However, the reference input impedance depends on the number of active
(enabled) channels in addition to fMOD. As a result of the change of reference input impedance caused by
enabling and disabling channels, the regulation and setting time of the external reference should be noted, so as
not to affect the readings.
VREFP
VREFN
AGND
AVDD
AGND
AVDD
ESD
Protection
Figure 66. Equivalent Reference Input Circuitry
VREFP
VREFN
5.2kW
Zeff
=
´ (6.75MHz/fMOD)
N
N = number of active channels.
Figure 67. Effective Reference Impedance
ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the
reference pins do not go below AGND by more than 0.4 V, and likewise do not exceed AVDD by 0.4 V. If these
conditions are possible, external Schottky clamp diodes or series resistors may be required to limit the input
current to safe values (see the Absolute Maximum Ratings table).
Note that the valid operating range of the reference inputs is limited to the following parameters:
–0.1 V ≤ VREFN ≤ +0.1 V
VREFN + 0.5 V ≤ VREFP ≤ AVDD + 0.1 V
8.3.8 Clock Input (CLK)
The ADS1278-SP requires a clock input for operation. The individual converters of the ADS1278-SP operate
from the same clock input. At the maximum data rate, the clock input can be either 27 MHz or 13.5 MHz for Low-
Power mode, or 27MHz or 5.4 MHz for Low-Speed mode, determined by the setting of the CLKDIV input. For
High-Speed mode, the maximum CLK input frequency is 32.768 MHz. For High-Resolution mode, the maximum
CLK input frequency is 27 MHz. The selection of the external clock frequency (fCLK) does not affect the resolution
of the ADS1278-SP. Use of a slower fCLK can reduce the power consumption of an external clock buffer. The
output data rate scales with clock frequency, down to a minimum clock frequency of fCLK = 100 kHz. Table 5
summarizes the ratio of the clock input frequency (fCLK) to data rate (fDATA), maximum data rate and
corresponding maximum clock input for the four operating modes.
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As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.
Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock
input; keeping the clock trace as short as possible, and using a 50-Ω series resistor placed close to the source
end, often helps.
Table 5. Clock Input Options
MODE SELECTION
High-Speed
MAX fCLK (MHz)
CLKDIV
fCLK/fDATA
256
DATA RATE (SPS)
128,000
32.768
27
1
1
1
0
1
0
High-Resolution
512
52,734
27
512
Low-Power
Low-Speed
52,734
10,547
13.5
27
256
2,560
512
5.4
8.3.9 Mode Selection (MODE)
The ADS1278-SP supports four modes of operation: High-Speed, High-Resolution, Low-Power, and Low-Speed.
The modes offer optimization of speed, resolution, and power. Mode selection is determined by the status of the
digital input MODE[1:0] pins, as shown in Table 6. The ADS1278-SP continually monitors the status of the
MODE pin during operation.
Table 6. Mode Selection
(1)
MODE[1:0]
MODE SELECTION
High-Speed
MAX fDATA
128,000
52,734
00
01
10
11
High-Resolution
Low-Power
52,734
Low-Speed
10,547
(1) fCLK = 27-MHz max (32.768-MHz max in High-Speed mode).
When using the SPI protocol, DRDY is held high after a mode change occurs until settled (or valid) data are
ready; see Figure 68 and Table 7.
In Frame-Sync protocol, the DOUT pins are held low after a mode change occurs until settled data are ready;
see Figure 68 and Table 7. Data can be read from the device to detect when DOUT changes to logic 1,
indicating that the data are valid.
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MODE[1:0]
Pins
ADS1278
Mode
Previous
Mode
New Mode
tNDR-SPI
SPI
DRDY
DOUT
Protocol
New Mode
Valid Data Ready
tNDR-FS
Frame-Sync
Protocol
New Mode
Valid Data on DOUT
Figure 68. Mode Change Timing
Table 7. New Data After Mode Change
SYMBOL
tNDR-SPI
tNDR-FS
DESCRIPTION
MIN
TYP
MAX
129
UNITS
Time for new data to be ready (SPI)
Time for new data to be ready (Frame-Sync)
Conversions (1/fDATA
)
)
127
128
Conversions (1/fDATA
8.3.10 Synchronization (SYNC)
The ADS1278-SP can be synchronized by pulsing the SYNC pin low and then returning the pin high. When the
pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. When
the SYNC pin returns high, the conversion process restarts. Synchronization allows the conversion to be aligned
with an external event, such as the changing of an external multiplexer on the analog inputs, or by a reference
timing pulse.
Because the ADS1278-SP converters operate in parallel from the same master clock and use the same SYNC
input control, they are always in synchronization with each other. The aperture match among internal channels is
typically less than 500 ps. However, the synchronization of multiple devices is somewhat different. At device
power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion
timing.
The SYNC pin can be used to synchronize multiple devices to within the same CLK cycle. Figure 69 illustrates
the timing requirement of SYNC and CLK in SPI format.
See Figure 70 for the Frame-Sync format timing requirement.
After synchronization, indication of valid data depends on whether SPI or Frame-Sync format was used.
In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 69. After SYNC is returned high,
DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low.
In the Frame-Sync format, DOUT goes low as soon as SYNC is taken low; see Figure 70. After SYNC is
returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, DOUT
begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before
taking SYNC high, and must then remain running. If the clock inputs (CLK, FSYNC or SCLK) are subsequently
interrupted or reset, re-assert the SYNC pin.
For consistent performance, re-assert SYNC after device power-on when data first appear.
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tCSHD
CLK
tSCSU
tSYN
SYNC
tNDR
DRDY
Figure 69. Synchronization Timing (SPI Protocol)
Table 8. SPI Protocol
SYMBOL
tCSHD
tSCSU
tSYN
DESCRIPTION
MIN
10
5
TYP
MAX
UNITS
CLK to SYNC hold time
SYNC to CLK setup time
Synchronize pulse width
Time for new data to be ready
ns
ns
1
CLK periods
tNDR
129
Conversions (1/fDATA)
tCSHD
CLK
tSCSU
tSYN
SYNC
FSYNC
DOUT
tNDR
Valid Data
Figure 70. Synchronization Timing (Frame-Sync Protocol)
Table 9. Frame-Sync Protocol
SYMBOL
tCSHD
tSCSU
tSYN
DESCRIPTION
MIN
10
5
TYP
MAX
UNITS
CLK to SYNC hold time
SYNC to CLK setup time
Synchronize pulse width
Time for new data to be ready
ns
ns
1
CLK periods
Conversions (1/fDATA)
tNDR
127
128
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8.3.11 Power-Down (PWDN)
The channels of the ADS1278-SP can be independently powered down by use of the PWDN inputs. To enter the
power-down mode, hold the respective PWDN pin low for at least two CLK cycles. To exit power-down, return
the corresponding PWDN pin high. Note that when all channels are powered down, the ADS1278-SP enters a
microwatt (μW) power state where all internal biasing is disabled. In this state, the TEST[1:0] input pins must be
driven; all other input pins can float. The ADS1278-SP outputs remain driven.
As shown in Figure 71 and Table 10, a maximum of 130 conversion cycles must elapse for SPI interface, and
129 conversion cycles must elapse for Frame-Sync, before reading data after exiting power-down. Data from
channels already running are not affected. The user software can perform the required delay time in any of the
following ways:
1. Count the number of data conversions after taking the PWDN pin high.
2. Delay 129/fDATA or 130/fDATA after taking the PWDN pins high, then read data.
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3. Detect for non-zero data in the powered-up channel.
After powering up one or more channels, the channels are synchronized to each other. It is not necessary to use
the SYNC pin to synchronize them.
When a channel is powered down in TDM data format, the data for that channel are either forced to zero (fixed-
position TDM data mode) or replaced by shifting the data from the next channel into the vacated data position
(dynamic-position TDM data mode).
In Discrete data format, the data are always forced to zero. When powering-up a channel in dynamic-position
TDM data format mode, the channel data remain packed until the data are ready, at which time the data frame is
expanded to include the just-powered channel data. See the Data Format section for details.
· · ·
· · ·
CLK
tPWDN
tNDR
PWDN
DRDY/FSYNC(1)
DOUT
(Discrete Data Output Mode)
Post Power-Up Data
Normal Position
DOUT1
(TDM Mode, Dynamic Position)
Normal Position
Normal Position
Data Shifts Position
DOUT1
(TDM Mode, Fixed Position)
Data Remains in Position
Normal Position
Figure 71. Power-Down Timing
Table 10. Power-Down Timing
SYMBOL
tPWDN
tNDR
DESCRIPTION
MIN
TYP
MAX
UNITS
PWDN pulse width to enter Power-Down mode
Time for new data ready (SPI)
2
CLK periods
129
128
130
129
Conversions (1/fDATA
)
)
tNDR
Time for new data ready (Frame-Sync)
Conversions (1/fDATA
36
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8.3.12 Format[2:0]
Data can be read from the ADS1278-SP with two interface protocols (SPI or Frame-Sync) and several options of
data formats (TDM/Discrete and Fixed/Dynamic data positions). The FORMAT[2:0] inputs are used to select
among the options. Table 11 lists the available options. See the DOUT Modes section for details of the DOUT
Mode and Data Position.
Table 11. Data Output Format
FORMAT[2:0]
INTERFACE PROTOCOL
SPI
DOUT MODE
TDM
DATA POSITION
000
001
010
011
100
101
110
Dynamic
Fixed
—
SPI
TDM
SPI
Discrete
TDM
Frame-Sync
Frame-Sync
Frame-Sync
Modulator Mode
Dynamic
Fixed
—
TDM
Discrete
—
—
8.3.13 Serial Interface Protocols
Data are retrieved from the ADS1278-SP using the serial interface. Two protocols are available: SPI and Frame-
Sync. The same pins are used for both interfaces: SCLK, DRDY/FSYNC, DOUT[8:1], and DIN. The
FORMAT[2:0] pins select the desired interface protocol.
8.3.14 SPI Serial Interface
The SPI-compatible format is a read-only interface. Data ready for retrieval are indicated by the falling DRDY
output and are shifted out on the falling edge of SCLK, MSB first. The interface can be daisy-chained using the
DIN input when using multiple devices. See the Daisy-Chaining section for more information.
NOTE: The SPI format is limited to a CLK input frequency of 27 MHz, maximum. For CLK input operation above
27 MHz (High-Speed mode only), use Frame-Sync format.
8.3.14.1 SCLK
The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It
also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. The device shifts
data out on the falling edge and the user normally shifts this data in on the rising edge.
Even though the SCLK input has hysteresis, it is recommended to keep SCLK as clean as possible to prevent
glitches from accidentally shifting the data.
SCLK may be run as fast as the CLK frequency. SCLK may be either in free-running or stop-clock operation
between conversions. Note that one fCLK is required after the falling edge of DRDY until the first rising edge of
SCLK. For best performance, limit fSCLK / fCLK to ratios of 1, 1/2, 1/4, 1/8, etc. When the device is configured for
modulator output, SCLK becomes the modulator clock output (see the Modulator Output section).
8.3.14.2 DRDY/FSYNC (SPI Format)
In the SPI format, this pin functions as the DRDY output. It goes low when data are ready for retrieval and then
returns high on the falling edge of the first subsequent SCLK. If data are not retrieved (that is, SCLK is held low),
DRDY pulses high just before the next conversion data are ready, as shown in Figure 72. The new data are
loaded within one CLK cycle before DRDY goes low. All data must be shifted out before this time to avoid being
overwritten.
1/fCLK
1/fDATA
DRDY
SCLK
Figure 72. DRDY Timing With No Readback
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8.3.14.3 DOUT
The conversion data are output on DOUT[8:1]. The MSB data are valid on DOUT[8:1] after DRDY goes low.
Subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted in using DIN
appear on DOUT after all channel data have been shifted out. When the device is configured for modulator
output, DOUT[8:1] becomes the modulator data output for each channel (see the Modulator Output section).
8.3.14.4 DIN
This input is used when multiple ADS1278-SPs are to be daisy-chained together. The DOUT1 pin of the first
device connects to the DIN pin of the next, etc. It can be used with either the SPI or Frame-Sync formats. Data
are shifted in on the falling edge of SCLK. When using only one ADS1278-SP, tie DIN low. See the Daisy-
Chaining section for more information.
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8.3.15 Frame-Sync Serial Interface
Frame-Sync format is similar to the interface often used on audio ADCs. It operates in slave fashion—the user
must supply framing signal FSYNC (similar to the left/right clock on stereo audio ADCs) and the serial clock
SCLK (similar to the bit clock on audio ADCs). The data are output MSB first or left-justified on the rising edge of
FSYNC. When using Frame-Sync format, the FSYNC and SCLK inputs must be continuously running with the
relationships shown in the Timing Requirements: Frame-Sync Format table.
8.3.15.1 SCLK
The serial clock (SCLK) features a Schmitt-triggered input and shifts out data on DOUT on the falling edge. It
also shifts in data on the falling edge on DIN when this pin is being used for daisy-chaining. Even though SCLK
has hysteresis, it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally
shifting the data. When using Frame-Sync format, SCLK must run continuously. If it is shut down, the data
readback will be corrupted. The number of SCLKs within a frame period (FSYNC clock) can be any power-of-2
ratio of CLK cycles (1, 1/2, 1/4, etc), as long as the number of cycles is sufficient to shift the data output from all
channels within one frame. When the device is configured for modulator output, SCLK becomes the modulator
clock output (see the Modulator Output section).
8.3.15.2 DRDY/FSYNC (Frame-Sync Format)
In Frame-Sync format, this pin is used as the FSYNC input. The frame-sync input (FSYNC) sets the frame
period, which must be the same as the data rate. The required number of fCLK cycles to each FSYNC period
depends on the mode selection and the CLKDIV input. Table 5 indicates the number of CLK cycles to each
frame (fCLK/fDATA). If the FSYNC period is not the proper value, data readback will be corrupted.
8.3.15.3 DOUT
The conversion data are shifted out on DOUT[8:1]. The MSB data become valid on DOUT[8:1] after FSYNC
goes high. The subsequent bits are shifted out with each falling edge of SCLK. If daisy-chaining, the data shifted
in using DIN appear on DOUT[8:1] after all channel data have been shifted out. When the device is configured
for modulator output, DOUT becomes the modulator data output (see the Modulator Output section).
8.3.15.4 DIN
This input is used when multiple ADS1278-SPs are to be daisy-chained together. It can be used with either SPI
or Frame-Sync formats. Data are shifted in on the falling edge of SCLK. When using only one ADS1278-SP, tie
DIN low. See the Daisy-Chaining section for more information.
8.3.16 DOUT Modes
For both SPI and Frame-Sync interface protocols, the data are shifted out either through individual channel
DOUT pins, in a parallel data format (Discrete mode), or the data for all channels are shifted out, in a serial
format, through a common pin, DOUT1 (TDM mode).
8.3.16.1 TDM Mode
In TDM (time-division multiplexed) data output mode, the data for all channels are shifted out, in sequence, on a
single pin (DOUT1). As shown in Figure 73, the data from channel 1 are shifted out first, followed by channel 2
data, etc. After the data from the last channel are shifted out, the data from the DIN input follow. The DIN is used
to daisy-chain the data output from an additional ADS1278-SP or other compatible device. Note that when all
channels of the ADS1278-SP are disabled, the interface is disabled, rendering the DIN input disabled as well.
When one or more channels of the device are powered down, the data format of the TDM mode can be fixed or
dynamic.
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SCLK
1
2
23
24
25
47
48
49
71
73
95
96
97
167
168
169
191
192
193
194
195
72
DOUT1
CH1
CH2
CH3
CH4
CH5
CH7
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 73. TDM Mode (All Channels Enabled)
8.3.16.2 TDM Mode, Fixed-Position Data
In this TDM data output mode, the data position of the channels remain fixed, regardless of whether the channels
are powered down. If a channel is powered down, the data are forced to zero but occupy the same position
within the data stream. Figure 74 shows the data stream with channel 1 and channel 3 powered down.
8.3.16.3 TDM Mode, Dynamic Position Data
In this TDM data output mode, when a channel is powered down, the data from higher channels shift one
position in the data stream to fill the vacated data slot. Figure 75 shows the data stream with channel 1 and
channel 3 powered down.
8.3.16.4 Discrete Data Output Mode
In Discrete data output mode, the channel data are shifted out in parallel using individual channel data output
pins DOUT[8:1]. After the 24th SCLK, the channel data are forced to zero. The data are also forced to zero for
powered down channels. Figure 76 shows the discrete data output format.
SCLK
1
2
23
24
25
47
48
49
71
72
73
95
96
97
167
168
169
191
192
193
194
195
DOUT1
CH1
CH2
CH3
CH4
CH5
CH7
CH8
DIN
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 74. TDM Mode, Fixed-Position Data (Channels 1 And 3 Shown Powered Down)
SCLK
1
2
23
24
25
47
48
49
50
119
120
121
143
144
145
145
146
CH2
CH4
CH5
CH7
CH8
DIN
DOUT1
DRDY
(SPI)
FSYNC
(Frame- Sync)
Figure 75. TDM Mode, Dynamic Position Data (Channels 1 And 3 Shown Powered Down)
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SCLK
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
1
2
22
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
23
24
25
26
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 76. Discrete Data Output Mode
8.3.17 Daisy-Chaining
Multiple ADS1278-SPs can be daisy-chained together to output data on a single pin. The DOUT1 data output pin
of one device is connected to the DIN of the next device. As shown in Figure 77, the DOUT1 pin of device 1
provides the output data to a controller, and the DIN of device 2 is grounded. Figure 78 shows the data format
when reading back data.
The maximum number of channels that may be daisy-chained in this way is limited by the frequency of fSCLK, the
mode selection, and the CLKDIV input. The frequency of fSCLK must be high enough to completely shift the data
out from all channels within one fDATA period. Table 12 lists the maximum number of daisy-chained channels
when fSCLK = fCLK
.
To increase the number of data channels possible in a chain, a segmented DOUT scheme may be used,
producing two data streams. Figure 79 illustrates four ADS1278-SPs, with pairs of ADS1278-SPs daisy-chained
together. The channel data of each daisy-chained pair are shifted out in parallel and received by the processor
through independent data channels.
Table 12. Maximum Channels In A Daisy-Chain (FSCLK = FCLK
)
MODE SELECTION
High-Speed
CLKDIV
MAXIMUM NUMBER OF CHANNELS
1
1
1
0
1
0
10
21
High-Resolution
21
Low-Power
Low-Speed
10
106
21
Whether the interface protocol is SPI or Frame-Sync, it is recommended to synchronize all devices by tying the
SYNC inputs together. When synchronized in SPI protocol, it is only necessary to monitor the DRDY output of
one ADS1278-SP.
In Frame-Sync interface protocol, the data from all devices are ready after the rising edge of FSYNC.
Since DOUT1 and DIN are both shifted on the falling edge of SCLK, the propagation delay on DOUT1 creates a
setup time on DIN. Minimize the skew in SCLK to avoid timing violations.
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U1
U2
SYNC
CLK
SYNC
SYNC
DRDY
DRDY Output from Device 1
DOUT from Devices 1 and 2
CLK
DIN
CLK
DIN
DOUT1
DOUT1
SCLK
SCLK
SCLK
Note: The number of chained devices is limited by the SCLK rate and device mode.
Figure 77. Daisy-Chaining of Two Devices, SPI Protocol (Format[2:0] = 000 or 001)
SCLK
1
2
25
26
49
50
73
74
97
98
193
194
217
218
385
386
DOUT1
CH1, U1
CH2, U1
CH3, U1
CH4, U1
CH5, U1
CH1, U2
CH2, U2
DIN2
DRDY
(SPI)
FSYNC
(Frame-Sync)
Figure 78. Daisy-Chain Data Format of Figure 77
SYNC
CLK
Serial Data
Devices 3 and 4
U1
U2
U3
U4
SYNC
CLK
SYNC
CLK
SYNC
CLK
SYNC
CLK
Serial Data
DOUT1
DOUT1
DIN
DOUT1
DIN
DIN
DOUT1
DIN
Devices 1 and 2
FSYNC
SCLK
FSYNC
SCLK
FSYNC
SCLK
FSYNC
SCLK
SCLK
FSYNC
Note: The number of chained devices is limited by the SCLK rate and device mode.
Figure 79. Segmented DOUT Daisy-Chain, Frame-Sync Protocol (Format[2:0] = 011 or 100)
8.3.18 Modulator Output
The ADS1278-SP incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage
digital filter that yields the conversion results. The data stream output of the modulator is available directly,
bypassing the internal digital filter. The digital filter is disabled, reducing the DVDD current, as shown in Table 13.
In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the
modulator output, tie FORMAT[2:0], as shown in Figure 80. DOUT[8:1] then becomes the modulator data stream
outputs for each channel and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an
unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and
the functionality of SCLK changes from an input to an output, as shown in Figure 80.
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Table 13. Modulator Output Clock Frequencies
MODE
[1:0]
CLKDIV
MODULATOR CLOCK OUTPUT (SCLK)
DVDD (mA)
00
1
1
1
0
1
0
fCLK / 4
fCLK / 4
fCLK / 8
fCLK / 4
fCLK / 40
fCLK / 8
8
7
4
4
1
1
01
10
11
Modulator Data Channel 1
Modulator Data Channel 2
DOUT1
DOUT2
IOVDD
DIN
FORMAT0
FORMAT1
FORMAT2
DOUT8
SCLK
Modulator Data Channel 8
Modulator Clock Output
Figure 80. Modulator Output
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In modulator output mode, the frequency of the modulator clock output (SCLK) depends on the mode selection of
the ADS1278-SP. Table 13 lists the modulator clock output frequency and DVDD current versus device mode.
Figure 81 shows the timing relationship of the modulator clock and data outputs.
The data output is a modulated 1s density data stream. When VIN = +VREF, the 1s density is approximately 80%
and when VIN = –VREF, the 1s density is approximately 20%.
Modulator
SCLK
Clock Output
Modulator
DOUT
Data Output
(13ns max)
Figure 81. Modulator Output Timing
8.3.19 Pin Test Using Test[1:0] Inputs
The test mode feature of the ADS1278-SP allows continuity testing of the digital I/O pins. In this mode, the
normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as
shown in Table 14. The pins in the left column drive the output pins in the right column. Note: some of the digital
input pins become outputs; these outputs must be accommodated in the design. The analog input, power supply,
and ground pins all remain connected as normal. The test mode is engaged by setting the pins TEST [1:0] = 11.
For normal converter operation, set TEST[1:0] = 00. Do not use '01' or '10'.
Table 14. Test Mode Pin Map (Test[1:0] = 11)
TEST MODE PIN MAP
INPUT PINS
PWDN1
OUTPUT PINS
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DIN
PWDN2
PWDN3
PWDN4
PWDN5
PWDN6
PWDN7
PWDN8
MODE0
MODE1
SYNC
FORMAT0
FORMAT1
FORMAT2
CLKDIV
FSYNC/DRDY
SCLK
8.3.20 VCOM Output
The VCOM pin provides a voltage output equal to AVDD / 2. The intended use of this output is to set the output
common-mode level of the analog input drivers. The drive capability of the output is limited; therefore, the output
should only be used to drive high-impedance nodes (> 1 MΩ). In some cases, an external buffer may be
necessary. A 0.1-μF bypass capacitor is recommended to reduce noise pickup.
LM124AQML-SP
VCOM » (AVDD/2)
µF
0.1
Figure 82. VCOM Output
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8.4 Device Functional Modes
Table 15. Operating Mode Performance Summary
MODE
High-Speed
High-Resolution
Low-Power
Low-Speed
MAX DATA RATE (SPS)
PASSBAND (kHz)
57,984
SNR (dB)
106
NOISE (μVRMS
)
POWER/CHANNEL (mW)
128,000
52,734
52,734
10,547
8.5
5.5
8.5
8.0
70
64
31
7
23,889
110
23,889
106
4,798
107
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1278-SP is a radiation-hardened high resolution delta-sigma ADC that is ideal for precision sensing and
high accuracy instrumentation applications. With eight simultaneous sampling 24-bit ADCs integrated, the device
reduces the board area needed to digitize eight analog signals.
9.2 Typical Application
(1)
THS4521
+3.3 V
ADS1278-SP
IN1(+)
IN1(-)
AINP1
AINN1
IOVDD
DVDD (I/O)
10 µF(2)
2.2 nF(3)
Microcontroller /
DSP
CLK
DRDY/FSYNC
DOUT1
50 Ω
FSR
DR
U2
0
>
Q
U1
CVDD
+1.6 V
SCLK
Q
(CORE)
50 Ω
DOUT2
CLKR
See
Note (5)
200 MHz
DOUT3
IN4/8(+)
IN4/8(-)
AINP4/8
AINN4/8
DOUT4
2.2 nF(3)
+5 V
SYNC
PWDN1
PWDN2
PWDN3
PWDN4
I/O
AVDD
DVDD
+
10 µF(2)
+1.8 V(6)
10 µF(2)
See
Note (6)
1 µF
LM4050QML-SP
VREFP
VREFN
+
10 µF
0.1 µF(2)
+3.3 V
CLKDIV
(High-Speed, Frame-Sync, TDM,
and Fixed-Position data selected.)
MODE0
MODE1
VCOM
+5 V
0.1 µF(2)
(4)
TEST0
TEST1
DIN
+3.3 V
FORMAT2
FORMAT1
100 Ω
Buffered
VCOM
Output
LM124AQML-SP
AGND
DGND
FORMAT0
Figure 83. Typical Application Schematic
9.2.1 Design Requirements
Depending on the accuracy and speed requirements of the sensing application to be digitized by the ADC1278-
SP, users must first determine the optimal device configuration. Table 16 shows the possible configurations for
device for the maximum fCLKIN for each configuration. The yellow highlighted columns indicate user defined
inputs (through I/O pins) to the device, while the italic row indicates the default configuration of the
ADS1278EVM-CVAL EVM that is available as a reference design. As shown, a maximum data rate of 52734
SPS is possible while using the High Resolution mode, which yields a typical SNR of 111 dB or an ENOB of 18
bits.
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Typical Application (continued)
Table 16. ADS1278-SP Configuration Modes
fCLKIN_max
(MHz)
Oversampling
(fMOD/fDATA)
fMOD
(MHz)
fDATA_max
(SPS)
Mode
CLKDIV
fCLK/fMOD
fCLKIN/fMOD
High-Speed
High-Speed
High-Speed
High Resolution
Low-Power
Low-Power
Low-Speed
Low-Speed
1
1
1
1
1
0
1
0
4
4
32.768
32.768
27
64
64
64
128
64
64
64
64
8.192
8.192
6.75
128000
128000
105469
52734
52734
52734
10547
10547
4
4
4
4
4
27
6.75
4
8
27
3.375
3.375
0.675
0.675
8
4
13.5
27
4
40
8
40
8
5.4
9.2.2 Detailed Design Procedure
To obtain the specified performance from the ADS1278-SP, the following layout and component guidelines
should be considered.
1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The
allowed range for DVDD is 1.65 V to 1.95 V; the range of IOVDD is 1.65 V to 3.6 V; AVDD is restricted to
4.75 V to 5.25 V. For all supplies, use a 10-μF tantalum capacitor, bypassed with a 0.1-μF ceramic capacitor,
placed close to the device pins. Alternatively, a single 10-μF ceramic capacitor can be used. The supplies
should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as
relays, LED display drivers, etc.). If a switching power-supply source is used, the voltage ripple should be low
(less than 2 mV) and the switching frequency outside the passband of the converter.
2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate
digital and analog grounds are used, connect the grounds together at the converter.
3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50-Ω series
resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates,
DSP, etc.) This placement helps to reduce ringing on the digital lines (ringing may lead to degraded ADC
performance).
4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together,
keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across
analog tracks to reduce noise coupling and crosstalk.
5. Reference Inputs: It is recommended to use a minimum 10-μF tantalum with a 0.1-μF ceramic capacitor
directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-
impedance source. For best performance, the reference should have less than 3-μVRMS in-band noise. For
references with noise higher than this level, external reference filtering may be necessary.
6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true
differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs
tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital
tracks. A 1-nF to 10-nF capacitor should be used directly across the analog input pins, AINP and AINN. A
low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each
analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor
(typically 100 pF) to preserve the ac common-mode performance.
7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as
close as possible to the device pins. This layout is particularly important for small-value ceramic capacitors.
Larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic
capacitors.
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9.2.3 Application Curve
Figure 84 illustrates how the noise of the device, and thus, the SNR, is determined by the mode that is utilized.
12
Low Power Mode
10
High Speed Mode
8
Low Speed Mode
6
4
High Resolution Mode
2
0
-55 -35 -15
5
25 45 65 85 105 125
Temperature (°C)
Figure 84. Noise vs Temperature
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10 Power Supply Recommendations
The ADS1278-SP has three power supplies: AVDD, DVDD, and IOVDD. AVDD is the analog supply that powers
the modulator, DVDD is the digital supply that powers the digital core, and IOVDD is the digital I/O power supply.
The IOVDD and DVDD power supplies can be tied together if desired (1.8 V). To achieve rated performance, it is
critical that the power supplies are bypassed with 0.1-μF and 10-μF capacitors placed as close as possible to the
supply pins. A single 10-μF ceramic capacitor may be substituted in place of the two capacitors.
Figure 85 shows the start-up sequence of the ADS1278-SP. At power-on, bring up the DVDD supply first,
followed by IOVDD and then AVDD. Check the power-supply sequence for proper order, including the ramp rate
of each supply. DVDD and IOVDD may be sequenced at the same time if the supplies are tied together. Each
supply has an internal reset circuit whose outputs are summed together to generate a global power-on reset.
After the supplies have exceeded the reset thresholds, 218 fCLK cycles are counted before the converter initiates
the conversion process. Following the CLK cycles, the data for 129 conversions are suppressed by the
ADS1278-SP to allow output of fully-settled data. In SPI protocol, DRDY is held high during this interval. In
frame-sync protocol, DOUT is forced to zero. The power supplies should be applied before any analog or digital
pin is driven. For consistent performance, assert SYNC after device power-on when data first appear.
DVDD
IOVDD
AVDD
1V nom(1)
1V nom(1)
3V nom(1)
Internal Reset
CLK
218
129 (max)
tDATA
fCLK
DRDY
(SPI Protocol)
DOUT
(Frame-Sync Protocol)
Valid Data
Figure 85. Start-Up Sequence
Copyright © 2018, Texas Instruments Incorporated
49
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
In any mixed-signal system design, the power-supply and grounding design plays a significant role. The device
distinguishes between two different grounds: AVSS (analog ground) and DGND (digital ground). In low frequency
applications such as temperature sensing with thermocouples, laying out the printed circuit board (PCB) to use a
single ground plane is adequate but care must be taken so that ground loops are avoided. Ground loops act as
loop antennas picking up interference currents which transform into voltage fluctuations. These fluctuations are
effectively noise which can degrade system performance in high resolution applications. When placing
components and routing over the ground plane, pay close attention to the path that ground currents will take.
Avoid having return currents for digital functions pass close to analog sensitive devices or traces.
Additionally, the proximity of digital devices to an analog signal chain has the potential to induce unwanted noise
into the system. One primary source of noise is the switching noise from any digital circuitry such as the data
output serializer or the microprocessor receiving the data. For the device, care must be taken to ensure that the
interaction between the analog and digital supplies within the device is kept to a minimal amount. The extent of
noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each
of the supply and ground connections. Smaller effective inductances of the supply and ground pins results in
better noise suppression. For this reason, multiple pins are used to connect to the digital ground. Low inductance
properties must be maintained throughout the design of the PCB layout by use of proper planes and layer
thickness.
To avoid noise coupling through supply pins, TI recommends to keep sensitive input pins away from the DVDD
and DGND planes. Do not route the traces or vias connected to these pins across these planes; that is, avoid the
digital power planes under the analog input pins. Care should be taken to minimize inductance and route digital
signals away from analog section.
The analog inputs represent the most sensitive node of the ADC as the total system accuracy depends on the
how well the integrity of this signal is maintained. The analog differential inputs to the ADC should be routed
tightly coupled and symmetrical for common mode rejection. These inputs should be as short in length as
possible to minimize exposure to potential sources of noise.
50
Copyright © 2018, Texas Instruments Incorporated
ADS1278-SP
www.ti.com.cn
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
11.2 Layout Example
Figure 86. ADS1278-SP Layout Example
版权 © 2018, Texas Instruments Incorporated
51
ADS1278-SP
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.3 商标
E2E is a trademark of Texas Instruments.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
52
版权 © 2018, Texas Instruments Incorporated
ADS1278-SP
www.ti.com.cn
ZHCSIS6B –SEPTEMBER 2018–REVISED DECEMBER 2018
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
53
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS1278HFQ/EM
ADS1278MHFQ-MLS
ADS1278WHFQ-MLS
ACTIVE
CFP
CFP
CFP
HFQ
84
84
84
1
RoHS-Exempt
& Green
Call TI
Call TI
Call TI
Call TI
25 to 25
-55 to 125
-55 to 115
ADS1278HFQ/EM
EVAL ONLY
Samples
Samples
Samples
ACTIVE
ACTIVE
HFQ
1
RoHS-Exempt
& Green
Call TI
Call TI
ADS1278MHFQ-MLS
HFQ
1
RoHS-Exempt
& Green
ADS1278
WHFQ-MLS
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS1278-SP :
Catalog : ADS1278
•
Enhanced Product : ADS1278-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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