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ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

ADS127L01 24 位高速、高带宽模数转换器

1 特性

3 说明

1

•

数据速率：高达 512kSPS

交流 + 直流性能：

ADS127L01 是一款 24 位 Δ-Σ 模数转换器 (ADC)，其

数据速率最高可达 512kSPS。该器件兼具出色直流精

度和卓越交流性能。高阶、斩波稳定调制器在低带内噪

声条件下实现极低漂移。集成抽取滤波器抑制调制器带

外噪声。除低延迟滤波器外，ADS127L01 还提供多个

纹波小于 ±0.00004dB 的宽带滤波器以及在奈奎斯特速

率下实现 –116dB 阻带衰减的选项。

–

通带：最高可达 230kHz

信噪比 (SNR)：最高可达 115.5dB

总谐波失真 (THD)：低至 -129dB

直流精度：

偏移漂移：1.5μV/°C

增益漂移：0.2ppm/°C

提供良好漂移性能的工业 Δ-Σ ADC 通常使用通带显著

衰减的数字滤波器。因此，工业 Δ-Σ ADC 的信号带宽

有限，主要用于直流测量。音频应用中的高分辨率

ADC 提供较大的可用带宽，但偏移和漂移规范明显弱

于同类工业产品。ADS127L01 将这些转换器相结合，

能够在 –40°C 到 +125°C 的工业温度范围内提供高精

度工业测量，实现出色的直流和交流规范。

•

运行模式：

–

高分辨率（26mW 时为 128kSPS）

低功耗（15mW 时为 128kSPS）

超低功耗：105dB SNR（9mW 时为

128kSPS）

数字滤波器选项：

–

低延迟滤波器：正弦频率响应

该器件的不同工作模式可优化速度、分辨率和功率。可

编程串行接口具备 SPI、帧同步从器件或帧同步主器件

这三个选项中的任意一个，可轻松跨越隔离栅与单片机

或数字信号处理器 (DSP) 相连。

宽带 1 滤波器：

(0.45 至 0.55) × f_DATA过渡带

–

宽带 2 滤波器：

(0.40 至 0.50) × f_DATA过渡带

•

SPI™或者帧同步串行接口

兼容菊花链

器件信息⁽¹⁾

–

器件型号

ADS127L01

封装

TQFP (32)

封装尺寸（标称值）

•

模拟电源：2.7V 到 3.6V

5.00mm x 5.00mm

数字电源：1.7V 到 3.6V

(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。

工作温度范围：-40°C 至 +125°C

2 应用

•

振动和模态分析

数据采集系统

声学和动态应力计

电能质量分析

ADS127L01 框图

ADC 频谱

REFP REFN LVDD AVDD

DVDD

0

256 kSPS Data Rate

65536 Data Points

-20

-40

LDO

INTLDO

SCLK

CS

SPI and

Frame-Sync

Interface

Low-Latency

Filter

DIN

AINP

AINN

DOUT

-60

ûꢀ ADC

Modulator

Wideband 1

Filter

DRDY/FSYNC

-80

DAISYIN

Wideband 2

Filter

FSMODE

FORMAT

-100

-120

-140

-160

-180

Control Logic

RESET/PWDN

OSR [1:0]

FILTER [1:0]

CLK

ADS127L01

DGND

AGND

0

20

40

60 80

Frequency (kHz)

100

120

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBAS607

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

8.2 Functional Block Diagram ....................................... 26

8.3 Feature Description................................................. 27

8.4 Device Functional Modes........................................ 38

8.5 Programming .......................................................... 46

8.6 Register Maps......................................................... 53

Application and Implementation ........................ 58

9.1 Application Information............................................ 58

9.2 Typical Application ................................................. 72

9.3 Do's and Don'ts ...................................................... 75

9.4 Initialization Setup .................................................. 77

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 8

6.6 Timing Requirements: Serial Interface.................... 11

6.7 Switching Characteristics: Serial Interface Mode.... 11

6.8 Timing Requirements: Frame-Sync Master Mode .. 13

9

10 Power Supply Recommendations ..................... 78

10.1 Power-Supply Sequencing.................................... 78

10.2 Power-Supply Decoupling .................................... 78

11 Layout................................................................... 79

11.1 Layout Guidelines ................................................. 79

11.2 Layout Example .................................................... 80

12 器件和文档支持 ..................................................... 82

12.1 文档支持 ............................................................... 82

12.2 接收文档更新通知 ................................................. 82

12.3 社区资源................................................................ 82

12.4 商标....................................................................... 82

12.5 静电放电警告......................................................... 82

12.6 Glossary................................................................ 82

13 机械、封装和可订购信息....................................... 82

6.9 Switching Characteristics: Frame-Sync Master

Mode ........................................................................ 13

6.10 Timing Requirements: Frame-Sync Slave Mode .. 14

6.11 Switching Characteristics: Frame-Sync Slave

Mode ........................................................................ 14

6.12 Typical Characteristics.......................................... 16

Parameter Measurement information ................ 24

7.1 Noise Performance ................................................. 24

Detailed Description ............................................ 26

8.1 Overview ................................................................. 26

7

8

4 修订历史记录

Changes from Revision A (May 2016) to Revision B

Page

•

特性，将交流性能更改为：交流 + 直流性能........................................................................................................................... 1

特性，将 SNR：最高可达 115.5dB（在 OSR 256 条件下）更改为：SNR：最高可达 115.5dB ........................................... 1

特性，将 THD：–126dB（低功耗 (LP) 和超低功耗 (VLP) 模式）更改为：THD：低至 -129dB ............................................ 1

特性，将直流精度更改为：积分非线性：1ppm ..................................................................................................................... 1

特性，将 HR：111dB SNR 更改为：高分辨率....................................................................................................................... 1

特性，将 LP：108dB SNR 更改为：低功耗........................................................................................................................... 1

特性，将 VLP：105dB SNR 更改为：超低功耗..................................................................................................................... 1

Pin Functions, Changed pin 14 description of 1: Master mode.............................................................................................. 5

Pin Functions, Changed pin 19 description "protocol" To: interface ...................................................................................... 5

Pin Functions, Changed pin 27 description "Decouple DVDD to DGND with a 1-μF capacitor" To: Connect a 1-μF

capacitor to DGND ................................................................................................................................................................. 5

•

Pin Functions, Changed pin 32 description "Decouple AVDD to AGND with a 1-μF capacitor" To: Connect a 1-μF

capacitor to AGND.................................................................................................................................................................. 5

•

Recommended Operating Conditions, Changed V_CMNOM value From: (AVDD + AGND) / 2 To: AVDD / 2 ...................... 7

Electrical Characteristics, Added test conditions to SNR: WB2, OSR 32/64/128, V_REF= 3 V ............................................... 9

Figure 2, Changed t_h(DO)To: t_v(DO)in order to match Switching Characteristics: Serial Interface Mode table...................... 12

Timing Requirements: Frame-Sync Slave Mode, Deleted text from conditions statement "and DVDD = 1.7 V to 3.6 V"... 14

Typical Characteristics, Changed conditions statement....................................................................................................... 16

Table 1, Changed the values in the ENOB column.............................................................................................................. 25

Table 2, Changed the values in the ENOB column.............................................................................................................. 25

Changed text frame-sync mode To: frame-sync interface mode throughout the document ................................................ 26

2

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

修订历史记录 (接下页)

•

Changed text frame-sync protocol. To: frame-sync interface mode throughout the document ........................................... 26

Changed section Mode Selection To: Operating Modes (HR, LP, VLP).............................................................................. 38

Changed section Filter Selection Pins (FILTER) To: Digital-Filter Path Selection Pins (FILTER[1:0])................................ 40

Figure 85, Changed t_w(STH)To: t_w(STL).................................................................................................................................... 41

Table 13, Changed t_w(STH)To: t_w(STL)..................................................................................................................................... 41

Start Pin (START), Deleted text "For consistent performance, reassert START after device power-on when data first

appear, or after any hardware MODE pin change." ............................................................................................................. 42

•

Figure 86, Changed t_w(STH)To: t_w(STL).................................................................................................................................... 42

Table 14, Changed t_w(STH)To: t_w(STL)..................................................................................................................................... 42

Data Ready (DRDY/FSYNC), Changed "...with the first SCLK rising edge." To: "...with the first SCLK falling edge, as

shown in Figure 91."............................................................................................................................................................. 47

•

Data Ready (DRDY/FSYNC), Added text "A new conversion result is..."............................................................................ 47

Data Ready (DRDY/FSYNC), Added Figure 91 ................................................................................................................... 47

START (0000 100x), Added sentence "The START command is decoded..." ................................................................... 48

STOP (0000 101x) , Added sentence "The START pin must be held low..."....................................................................... 48

RREG (0010 rrrr 0000 nnnn), Added Figure 92 ................................................................................................................... 49

WREG (0100 rrrr 0000 nnnn), Added Figure 93 .................................................................................................................. 49

Synchronizing Devices, Added text "When synchronizing multiple devices..." .................................................................... 63

Figure 112, Changed position of f_MODarrow......................................................................................................................... 64

Antialiasing Filter, Changed paragraph following Figure 112 .............................................................................................. 65

Table 30, Changed THS4551 Gain Bandwidth Product (MHz) From: 130 To: 135............................................................. 66

Modulator Saturation, Added new section............................................................................................................................ 68

Table 32, Changed values in the Noise column................................................................................................................... 70

Detailed Design Procedure, Changed "With a 130-MHz gain-bandwidth product" To: "With a 135-MHz gain-

bandwidth product" .............................................................................................................................................................. 72

•

Layout Guidelines, Changed section.................................................................................................................................... 79

Changes from Original (April 2016) to Revision A

Page

•

已从“产品预览”更改为“量产数据” ............................................................................................................................................ 1

3

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

5 Pin Configuration and Functions

PBS package

32-Pin TQFP

Top View

LVDD

CAP1

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

CLK

CS

AINN

SCLK

AINP

DIN

AGND

AVDD

REXT

INTLDO

DOUT

DRDY/FSYNC

DAISYIN

START

Not to scale

Pin Functions

NAME

I/O

DESCRIPTION⁽¹⁾

NO.

LVDD analog supply.

1

LVDD

Supply

INTLDO = 0: LVDD is an analog-supply output pin. Connect a 1-µF capacitor to AGND.

INTLDO = 1: LVDD is an analog-supply input pin. Connect to a 1.8-V supply.

Modulator common-mode voltage.

Connect a 1-µF capacitor to AGND

2

CAP1

Analog output

3

4

5

AINN

AINP

Analog input

Supply

Negative analog input.

Positive analog input.

Analog ground.

AGND

Analog supply.

Connect a 1-μF capacitor to AGND.

6

AVDD

REXT

Supply

Analog power-scaling bias resistor pin.

Recommended external resistor values:

R_EXT= 60.4 kΩ to AGND for high-resolution (HR) and low-power (LP) modes

R_EXT= 120 kΩ to AGND for very-low-power (VLP) mode

7

Analog input

LVDD voltage selection pin (pull high to AVDD or low to AGND through 10-kΩ resistor).

0: Internal analog low-dropout regulator (LDO) for LVDD voltage supply.

1: External LVDD voltage supply.

8

INTLDO

Digital input

Positive analog reference input.

Connect a minimum 10-μF capacitor to REFN

9

REFP

REFN

CAP2

Analog input

Analog output

10

11

Negative analog reference input.

Reference common-mode voltage.

Connect a 1-µF capacitor to AGND.

(1) See the Unused Inputs and Outputs section for unused pin connections.

4

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Pin Functions (continued)

I/O

DESCRIPTION⁽¹⁾

NO.

12

NAME

FILTER1

Digital input

Digital filter select pin⁽²⁾

.

00: Wideband 1 filter (WB1)

01: Wideband 2 filter (WB2)

10: Low-latency filter (LL)

11: Reserved

13

FILTER0

Digital input

Frame-sync mode pin⁽²⁾

0: Slave mode

1: Master mode. Applies to Frame-Sync interface mode only. No effect in SPI interface

mode.

.

14

15

FSMODE

OSR1

Digital input

Oversampling ratio (OSR) pin for the decimation filters⁽²⁾

.

Wideband filters, FILTER[1:0] = 00 or 01:

00: 32x oversampling (OSR 32)

01: 64x oversampling (OSR 64)

10: 128x oversampling (OSR 128)

11: 256x oversampling (OSR 256)

16

OSR0

Digital input

Low-latency filter, FILTER[1:0] = 10:

00: 32x oversampling (OSR 32)

01: 128x oversampling (OSR 128)

10: 512x oversampling (OSR 512)

11: 2048x oversampling (OSR 2048)

17

18

START

Digital input

Synchronization signal to start or restart a conversion.

Daisy-chain input.

DAISYIN

SPI interface: Data ready, active low⁽³⁾

.

19

20

21

22

23

24

25

26

27

28

DRDY/FSYNC

DOUT

Digital input/output

Digital output

Frame-sync interface: Frame-sync input signal⁽³⁾

Serial data output

Serial data input.

Tie directly to DGND when using the frame-sync interface.

Digital input/output Serial clock input⁽³⁾

.

DIN

Digital input

SCLK

Chip select.

Digital input

CS

Tie directly to DGND when using the frame-sync interface.

Master clock input.

CLK

Digital input

Analog output

Supply

Internally-generated digital operating voltage.

Connect a 1-µF capacitor to DGND.

CAP3

DGND

DVDD

Digital ground.

Digital supply.

Supply

Connect a 1-μF capacitor to DGND⁽³⁾

RESET/PWDN

Digital input

Reset or power-down pin, active low⁽³⁾

.

ADC operating mode⁽²⁾

1: High-resolution (HR)

.

29

30

HR

Digital input

0: Low-power (LP) or very-low-power (VLP)⁽⁴⁾

Interface select pin⁽²⁾

0: SPI

.

FORMAT

1: Frame-Sync

31

32

AGND

AVDD

Supply

Analog ground.

Analog supply.

Decouple AVDD to AGND with a 1-μF capacitor.

(2) Pull the hardware mode pins high to DVDD or low to DGND through 100-kΩ resistors.

(3) See the Reset and Power-Down Pin (RESET/PWDN) section for specific hardware design details if using power-down mode.

(4) Entering LP mode or VLP mode is set by R_EXTresistor value.

5

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

MIN

–0.3

MAX

4.0

UNIT

AVDD to AGND

DVDD to DGND

LVDD to AGND

–0.3

4.0

–0.3

2.0

AGND to DGND

–0.3

0.3

Voltage

V

REFP to AGND

–0.3

AVDD + 0.3

DVDD + 0.3

10

REFN to AGND

Analog input

Digital input

–0.3

AGND – 0.3

DGND – 0.3

–10

(2)

Current

Input, continuous, any pin except power supply pins

mA

°C

Operating ambient, T_A

Junction, T_J

–40

125

Temperature

150

Storage, T_stg

–60

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Input pins are diode-clamped to the power-supply rails. Limit the input current to 10 mA or less if the analog input voltage exceeds

AVDD + 0.3 V or is less than AGND – 0.3 V, or if the digital input voltage exceeds DVDD + 0.3 V or is less than DGND – 0.3 V.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVDD

LVDD

DVDD

Analog power supply

Low voltage analog supply

Digital supply

2.7

1.7

3.0

1.8

3.6

1.9

3.6

V

INTLDO = 1

ANALOG INPUTS

V_IN

Differential input voltage

V_IN= (V_AINP– V_AINN

)

–V_REF

AGND

V_REF

V

V_AINP

V_AINN

,

Absolute input voltage

AINP or AINN to AGND

V_CM= (V_AINP+ V_AINN) / 2

AVDD

V_CM

Common-mode input voltage

AVDD / 2

VOLTAGE REFERENCE INPUTS

V_REFN

V_REFP

V_REF

Negative reference input

Positive reference input

Reference input voltage

AGND – 0.1

V_REFN+ 0.5

0.5

AGND

2.5

AGND + 1.0

AVDD

V

V_REF= V_REFP– V_REFN

2.5

3.0

EXTERNAL CLOCK SOURCE

HR mode

LP mode

VLP mode

0.1

16.384

8.192

4.096

17.6

8.8

f_CLK

Master clock rate⁽¹⁾

MHz

4.4

DIGITAL INPUTS

Input voltage

TEMPERATURE RANGE

T_AOperating ambient temperature

DGND

DVDD

125

V

–40

°C

(1) To meet maximum speed conditions, f_CLKduty cycle must be 49% < duty cycle < 51%.

6.4 Thermal Information

ADS127L01

THERMAL METRIC⁽¹⁾

PBS (TQFP)

32 PINS

73.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

15.9

26.7

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

26.5

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

6.5 Electrical Characteristics

Minimum and maximum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, V_REF= 2.5 V, INTLDO = 1, FILTER[1:0] = 01

(WB2), and f_CLK= 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

HR mode, f_CLK= 16.384 MHz

5

11

23

Differential input

impedance

LP mode, f_CLK= 8.192 MHz

VLP mode, f_CLK= 4.096 MHz

kΩ

DC PERFORMANCE

Resolution

No missing codes

HR mode

24

Bits

Wideband filters

Low-latency filter

Wideband filters

Low-latency filter

Wideband filters

Low-latency filter

V_CM= AVDD / 2

512, 256, 128, 64

512, 128, 32, 8

256, 128, 64, 32

f_DATA

Data rate

LP mode

kSPS

256, 64, 16, 4

128, 64, 32, 16

VLP mode

128, 32, 8, 2

HR mode

LP mode

VLP mode

2.5

1

10

5

INL

Integral nonlinearity⁽¹⁾

ppm

1

5

Offset error

±0.1

1.5

mV

Offset drift

3.0

μV/°C

%FSR

Gain error

0.2

Gain calibration accuracy

0.003%

0.8

HR mode

LP mode

VLP mode

3

2.5

2

Gain drift

Noise⁽²⁾

0.4

ppm/°C

0.2

WB2, OSR 32

WB2, OSR 64

WB2, OSR 128

WB2, OSR 256

10.6

7.3

10.1

7.2

HR mode

μV_RMS

5.1

3.6

5.2

Common-mode rejection

ratio

CMRR

PSRR

f_CM= 60 Hz

f_PS= 60 Hz

95

dB

AVDD

DVDD

LVDD

90

85

80

Power-supply rejection

ratio

(1) Best fit method.

(2) For all Wideband filter configurations, see Table 1. For all Low-latency filter configurations, see Table 2.

8

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Electrical Characteristics (continued)

Minimum and maximum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, V_REF= 2.5 V, INTLDO = 1, FILTER[1:0] = 01

(WB2), and f_CLK= 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

AC PERFORMANCE

WB2, OSR 32

WB2, OSR 64

WB2, OSR 128

WB2, OSR 256

104.4

107.8

110.9

113.9

105.8

109.3

112

104.9

107.9

110.6

SNR

Signal-to-noise ratio⁽²⁾⁽³⁾

dB

WB2, OSR 32, V_REF= 3 V

WB2, OSR 64, V_REF= 3 V

WB2, OSR 128, V_REF= 3 V

WB2, OSR 256, V_REF= 3 V

HR mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

LP mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

VLP mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

HR mode

115.5

–113

–126

–129

–115

–130

Total harmonic

distortion⁽⁴⁾

THD

dB

Spurious-free dynamic

range

SFDR

LP mode

VLP mode

DIGITAL FILTER RESPONSE: WIDEBAND

Bandwidth

See Table 1

Pass-band ripple

±0.000032

dB

Hz

(0.45 to 0.55) ×

f_DATA

FILTER[1:0] = 00 (WB1)

Transition band

(0.40 to 0.50) ×

f_DATA

FILTER[1:0] = 01 (WB2)

Stop-band attenuation

Group delay

116

dB

s

42 / f_DATA

84 / f_DATA

Settling time

Complete settling

s

DIGITAL FILTER RESPONSE: LOW-LATENCY

Bandwidth

Group delay

See Table 2

See Low-Latency Filter section

Settling time

VOLTAGE REFERENCE INPUTS

HR mode

Reference input

LP mode

2.2

3.2

4

kΩ

impedance

VLP mode

SYSTEM MONITORS

Input over-range detect

accuracy

±100

mV

DIGITAL INPUT/OUTPUT (DVDD = 1.7 V to 3.6 V)

V_IH

V_IL

V_OH

V_OL

I_H

High-level input voltage

0.7 DVDD

DGND

DVDD

V

Low-level input voltage

0.3 DVDD

DVDD

0.2 DVDD

10

High-level output voltage I_OH= 2 mA

Low-level output voltage I_OL= 2 mA

0.8 DVDD

DGND

–10

V

Input leakage, high

Input leakage, low

I_H= 3.6 V

μA

I_L

I_L= DGND

–10

10

(3) Minimum SNR is ensured by the limit of the dc noise specification.

(4) THD includes the first nine harmonics of the input signal.

9

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Electrical Characteristics (continued)

Minimum and maximum specifications apply from T_A= –40°C to +125°C. Typical specifications are at T_A= 25°C.

All specifications are at AVDD = 3 V, LVDD = 1.8 V (external), DVDD = 1.8 V, V_REF= 2.5 V, INTLDO = 1, FILTER[1:0] = 01

(WB2), and f_CLK= 16.384 MHz for HR mode, 8.192 MHz for LP mode, or 4.096 MHz for VLP mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

INTLDO = 0

8

2

AVDD

INTLDO = 1

Power-down current

AVDD current

μA

DVDD

0.6

1.3

0.8

0.4

9.3

4.6

2.3

2.8

1.5

0.8

LVDD, INTLDO = 1

HR mode

LP mode

1.6

1.0

0.6

11

I_AVDD

I_LVDD

I_DVDD

mA

VLP mode

HR mode

LP mode

(6)

LVDD current⁽⁵⁾

5.5

2.8

3.4

1.8

1.1

VLP mode

HR mode

LP mode

OSR 128

DVDD current⁽²⁾

VLP mode

INTLDO = 1,

LVDD = 1.8 V,

HR mode, OSR 128,

AVDD = 3.0 V,

DVDD = 1.8 V

25.7

36.8

13.4

18.9

6.8

30.8

44.2

16.1

22.7

8.2

INTLDO = 0

INTLDO = 1,

LVDD = 1.8 V,

LP mode, OSR 128,

AVDD = 3.0 V,

DVDD = 1.8 V

P_D

Power dissipation

mW

INTLDO = 0

INTLDO = 1,

LVDD = 1.8 V,

VLP mode, OSR 128,

AVDD = 3.0 V,

DVDD = 1.8 V

INTLDO = 0

9.5

11.4

(5) LVDD current sourced from AVDD when the internal LDO is used (INTLDO = 0).

(6) LVDD current scales with f_CLK; see Figure 47.

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6.6 Timing Requirements: Serial Interface

over operating ambient temperature range (unless otherwise noted)

2.8 V < DVDD ≤ 3.6 V

1.7 V ≤ DVDD ≤ 2.8 V

MIN

57

TYP

MAX

10,000

5,000

MIN

57

TYP

MAX

10,000

5,000

UNIT

HR mode

LP mode

VLP mode

HR mode

LP mode

VLP mode

t_c(CLK)

Master clock period

114

227

28

114

227

28

ns

Pulse duration, Master clock

high or low

t_w(CP)

56

5,000

56

5,000

ns

112

5,000

112

5,000

Delay time, CS falling edge to first SCLK rising

edge⁽¹⁾

t_d(CSSC)

8

12

t_c(SC)

SCLK period

40

20

6

6250

50

25

9

6250

ns

t_w(SCHL)

t_su(DI)

t_h(DI)

Pulse duration, SCLK high or low

Setup time, DIN valid before SCLK falling edge

Hold time, DIN valid after SCLK falling edge

Pulse duration, CS high

ns

8

9

ns

t_w(CSH)

6

t_CLK

Delay time, final SCLK falling edge to CS rising

edge

t_d(SCCS)

2

4

2

4

t_CLK

t_d(DECODE)

Delay time, command decode time

t_CLK

TOUT_DEL = 0

SPI timeout⁽²⁾

2¹⁶

2¹⁴

2¹⁶

2¹⁴

TOUT_DEL = 1

Setup time, DAISYIN valid before SCLK falling

edge

t_su(DCI)

t_h(DCI)

5

8

ns

Hold time, DAISYIN valid after SCLK falling

edge

20

25

(1) CS can be tied low permanently in case the serial bus is not shared with any other device.

(2) See the SPI Timeout section for more information.

6.7 Switching Characteristics: Serial Interface Mode

over operating ambient temperature range (unless otherwise noted)

2.8 V < DVDD ≤ 3.6 V

1.7 V ≤ DVDD ≤ 2.8 V

MIN TYP

MIN

TYP

MAX

UNIT

Propagation delay time,

CS falling edge to DOUT driven

t_p(CSDO)

12

18

ns

Propagation delay time,

SCLK rising edge to valid new DOUT

t_p(SCDO)

t_v(DO)

15

20

21

20

ns

Valid time, SCLK falling edge to DOUT invalid

18 t_SCLK/ 2

20 t_SCLK/ 2

Propagation delay time,

CS rising edge to DOUT high impedance

t_p(CSDOZ)

11

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t_w(CP)

t_c(CLK)

CLK

CS

t_w(CSH)

t_d(DECODE)

t_d(CSSC)

t_w(SCHL)

t_d(SCCS)

t_c(SC)

SCLK

DIN

1

2

3

8

1

2

3

8

t_h(DI)

t_v(DO)

t_su(DI)

t_p(SCDO)

t_p(CSDOZ)

t_p(CSDO)

DOUT

NOTE: SPI settings are CPOL = 0 and CPHA = 1.

Figure 1. SPI Interface Timing

MSB_D1

LSB_D1

DAISYIN

t_su(DCI)

t_h(DCI)

SCLK

DOUT

t_v(DO)

MSB_D0

LSB_D0

MSB_D1

Figure 2. SPI Daisy-Chain Interface Timing

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6.8 Timing Requirements: Frame-Sync Master Mode

over operating ambient temperature range and DVDD = 1.7 V to 3.6 V (unless otherwise noted)

1.7 V ≤ DVDD ≤ 3.6 V

MIN

57

TYP

MAX

10,000

5,000

UNIT

HR mode

LP mode

VLP mode

HR mode

LP mode

VLP mode

t_c(CLK)

Master clock period

114

227

28

ns

t_w(CP)

Pulse duration, Master clock high or low

56

5,000

ns

112

5,000

6.9 Switching Characteristics: Frame-Sync Master Mode

over operating free-air temperature range (unless otherwise noted)

2.8 V < DVDD ≤ 3.6 V

MIN TYP

1.7 V ≤ DVDD ≤ 2.8 V

MAX

MIN

TYP

MAX

UNIT

Delay time, CLK rising edge to SCLK falling

edge

t_d(CSC)

15

ns

t_c(FRAME)

t_w(FP)

Frame period

1 / f_DATA

s

Pulse duration, FSYNC high or low

1 / (2f_DATA

)

1 / (2f_DATA

)

Delay time, FSYNC rising edge to SCLK falling

edge

t_d(FSSC)

6

8

ns

t_c(SC)

SCLK period

1 / (32f_DATA

)

1 / (32f_DATA

)

s

t_w(SCHL)

t_v(DO)

Pulse duration, SCLK high or low

Valid time, SCLK rising edge to DOUT invalid

1 / (64f_DATA

25

ns

Propagation delay time,

SCLK falling edge to DOUT driven

t_p(SCDO)

t_p(FSDO)

15

12

17

15

ns

Propagation delay time,

FSYNC rising edge to DOUT MSB valid

t_w(CP)

t_c(CLK)

CLK

t_c(FRAME)

t_d(CSC)

t_w(FP)

t_w(SCHL)

FSYNC

t_d(FSSC)

t_c(SC)

SCLK

t_p(FSDO)

t_v(DO)

t_p(SCDO)

Bit 31

Bit 30

Bit 15

Bit 14

Bit 0

DOUT

Figure 3. Frame-Sync Interface Timing Master Mode

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6.10 Timing Requirements: Frame-Sync Slave Mode

over operating ambient temperature range (unless otherwise noted)

2.8 V < DVDD ≤ 3.6 V

1.7 V ≤ DVDD ≤ 2.8 V

MIN

57

TYP

MAX

10,000

5,000

MIN

57

TYP

MAX

UNIT

HR mode

LP mode

VLP mode

HR mode

LP mode

VLP mode

10,000

5,000

t_c(CLK)

Master clock period

114

227

28

114

227

28

ns

Pulse duration, Master clock

high or low

t_w(CP)

56

5,000

56

5,000

ns

112

5,000

112

5,000

Delay time, CLK rising edge to SCLK falling

edge

t_d(CSC)

2

t_c(FRAME)

t_w(FP)

Frame period

1 / f_DATA

s

Pulse durration, FSYNC high or low

2

t_SCLK

Delay time, FSYNC rising edge to SCLK falling

edge

t_d(FSSC)

t_d(SCFS)

6

2

6

2

ns

Delay time, SCLK falling edge to FSYNC rising

edge

t_c(SC)

SCLK period

40

20

56

28

ns

t_w(SCHL)

Pulse duration, SCLK high or low

DAISY-CHAIN TIMING

Setup time, DAISYIN valid before SCLK rising

edge

t_su(DCI)

t_h(DCI)

8

ns

Hold time, DAISYIN valid after SCLK rising

edge

25

31

6.11 Switching Characteristics: Frame-Sync Slave Mode

over operating ambient temperature range (unless otherwise noted)

2.8 V < DVDD ≤ 3.6 V

1.7 V ≤ DVDD ≤ 2.8 V

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

t_v(DO)

Valid time, SCLK rising edge to DOUT invalid

17

25

ns

Propagation delay time,

SCLK falling edge to valid new DOUT

t_p(SCDO)

22

32

ns

Propagation delay time,

FSYNC rising edge to DOUT MSB valid

t_p(FSDO)

15

25

t_w(CP)

t_c(CLK)

CLK

t_d(CSC)

t_c(FRAME)

FSYNC

t_w(FP)

t_d(FSSC)

t_d(SCFS)

t_w(SCHL)

t_c(SC)

SCLK

t_p(FSDO)

t_v(DO)

t_p(SCDO)

Bit 31

Bit 30

Bit 15

Bit 14

Bit 0

DOUT

Figure 4. Frame-Sync Interface Timing Slave Mode

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MSB_D1

LSB_D1

DAISYIN

SCLK

t_su(DCI)

t_h(DCI)

MSB_D0

LSB_D0

MSB_D1

DOUT

Figure 5. Frame-Sync Interface Slave Daisy-Chain Timing

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6.12 Typical Characteristics

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

40

80

120

160

200

240

0

40

80

120

160

200

240

Frequency (kHz)

D026

D027

f_IN= 4 kHz, V_IN= –0.5 dBFS, HR mode, WB2, 512 kSPS,

32768 samples

f_IN= 4 kHz, V_IN= –20 dBFS, HR mode, WB2, 512 kSPS,

32768 samples

Figure 6. Output Spectrum

Figure 7. Output Spectrum

0

-20

-40

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

40

80

120

160

200

240

0

40

80

120

160

200

240

Frequency (kHz)

D028

D029

f_IN= 4 kHz, V_IN= –0.5 dBFS, HR mode, WB1, 512 kSPS,

32768 samples

f_IN= 4 kHz, V_IN= –20 dBFS, HR mode, WB1, 512 kSPS,

32768 samples

Figure 8. Output Spectrum

Figure 9. Output Spectrum

0

-20

-40

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

20

40

60

80

100

120 130

0

20

40

60

80

100

120 130

Frequency (kHz)

D030

D031

f_IN= 4 kHz, V_IN= –0.5 dBFS, LP mode, WB2, 256 kSPS,

32768 samples

f_IN= 4 kHz, V_IN= –20 dBFS, LP mode, WB2, 256 kSPS,

32768 samples

Figure 10. Output Spectrum

Figure 11. Output Spectrum

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ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

10

20

30

40

50

60 65

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Frequency (kHz)

D032

D033

f_IN= 4 kHz, V_IN= –0.5 dBFS, VLP mode, WB2, 128 kSPS,

32768 samples

f_IN= 4 kHz, V_IN= –20 dBFS, VLP mode, WB2, 128 kSPS,

32768 samples

Figure 12. Output Spectrum

Figure 13. Output Spectrum

0

-20

-40

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

30

60

90

120 150 180 210 240

0

20

40

60

80

100

120

Frequency (kHz)

D034

D035

Inputs shorted, HR mode, WB2, 512 kSPS,

32768 samples

Inputs shorted, LP mode, WB2, 256 kSPS,

32768 samples

Figure 14. Output Spectrum

Figure 15. Output Spectrum

0

-20

30

25

20

15

10

5

-40

-60

-80

0

-100

-120

-140

-160

-180

-5

-10

-15

-20

-25

-30

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Frequency (kHz)

0

12000

24000

36000

48000

60000

Time (ms)

D036

D039

Inputs shorted, VLP mode, WB2, 128 kSPS,

32768 samples

HR mode, 0.5 seconds data collection

space

Figure 16. Output Spectrum

Figure 17. ADC Conversion Noise

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

5.2

5.18

5.16

5.14

5.12

5.1

5.08

5.06

5.04

5.02

5

4.98

4.96

4.94

4.92

4.9

4200

3900

3600

3300

3000

2700

2400

2100

1800

1500

1200

900

600

300

0

0.5 0.75

1

1.25 1.5 1.75

V_REF(V)

2

2.25 2.5 2.75

3

Voltage (mV)

D053

D040

Inputs shorted, HR mode

Inputs shorted, HR mode, 65536 points

Figure 19. Noise vs V_REF

Figure 18. Noise Histogram

9

8

7

6

5

4

3

5.15

5.125

5.1

5.075

5.05

5.025

5

2

-40

-20

0

20

40

60

80

100

120

0

2

4

6

8

10

12

14

16

18

Temperature (èC)

f_CLK(MHz)

D048

D055

Inputs shorted

Inputs shorted, HR mode

Figure 20. Noise vs Temperature

Figure 21. Noise vs f_CLK

0

-15

0

-20

HR Mode

LP Mode

VLP Mode

HR Mode

LP Mode

VLP Mode

-30

-40

-45

-60

-80

-75

-100

-120

-140

-160

-90

-105

-120

-135

0.5 0.7

1

2

3

4 5 6 78 10

20 30 4050 70 100

-60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5

Input Amplitude (dBFS)

0

Input Frequency (kHz)

D037

D038

WB2, OSR 32

Figure 22. Total Harmonic Distortion vs f_IN

Figure 23. Total Harmonic Distortion vs V_IN

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

-100

-105

-110

-115

-120

-125

-130

-100

-105

-110

-115

-120

-125

-130

-135

-140

0.5

1

1.5

2

2.5

3

0

2

4

6

8

10

12

14

16

18

V_REF(V)

f_CLK(MHz)

D052

D054

HR mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

f_IN= 4 kHz, HR mode

Figure 25. Total Harmonic Distortion vs f_CLK

Figure 24. Total Harmonic Distortion vs V_REF

15

12.5

10

14

13

12

11

10

9

8

7.5

5

7

6

5

4

3

2.5

0

2

1

0

1

3

4

6

8

2

5

4

8

6.

2.

8.

4.

9.

8.

3.

1.

-12

-11

-10

-12

Total Harmonic Distortion (dB)

D074

D072

HR mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

Figure 26. Total Harmonic Distortion Histogram

LP mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

Figure 27. Total Harmonic Distortion Histogram

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

HR Mode

LP Mode

VLP Mode

-40

-20

0

20

40

60

80

100

120

4

5

6

7

9

6

1

3

5.

3.

1.

9.

7.

4.

2.

-12

Temperature (èC)

D050

-13

-12

Total Harmonic Distortion (dB)

D073

VLP mode, f_IN= 4 kHz, V_IN= –0.5 dBFS

Figure 28. Total Harmonic Distortion Histogram

Figure 29. INL vs Temperature

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

3

2.5

2

1400

1200

1000

800

600

400

200

0

25èC

-40èC

125èC

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

-3

-2.5 -2 -1.5 -1 -0.5

0

0.5

1

1.5

2

2.5

1

8

4

-79

-39

121

161

D042

-231 -199

-159

-119

V_IN(V)

D051

Offset Error (mV)

Inputs shorted

Figure 30. INL vs V_IN

Figure 31. Offset Error Histogram

200

150

100

50

1400

1200

1000

800

600

400

200

0

-50

-100

-150

-200

-250

-300

-40

-20

0

20

40

60

80

100

120

8

1

9

6

3

1

2

5

7

3

1.2

0.2

0.5

0.8

1.5

Temperature (èC)

-1.6 -1.4

-1.0

-0.7

-0.4

-0.1

D047

Gain Error (%FSR)

D041

Inputs shorted

Figure 33. Offset Error vs Temperature

Figure 32. Gain Error Histogram

-0.24

10

9

8

7

6

5

4

3

2

1

0

-0.21

-0.18

-0.15

-0.12

-0.09

-40

-20

0

20

40

60

80

100

120

1

2

3

4

6

7

8

9

0.6

1.9

0.7

0.8

0.9

1.1

1.3

1.5

1.6

1.7

¹O^.0ffset Drift (mV¹/è^.4C)

Temperature (èC)

D049

D043

Inputs shorted, 30 devices

Figure 34. Gain Error vs Temperature

Figure 35. Offset Drift Histogram

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Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

10

9

8

7

6

5

4

3

2

1

0

20

17.5

15

12.5

10

7.5

5

2.5

0

51

19

14

46

79

11

44

76

09

42

74

43

15

13

41

69

97

25

53

Gai⁰n^.Drift (ppm/èC)

0.

1.

2.

0.

1.

G⁰a^.in Drift (ppm/èC¹)^.

-0.

D044

D045

HR mode, 30 Devices

LP mode, 30 Devices

Figure 36. Gain Drift Histogram

Figure 37. Gain Drift Histogram

0.22

0.21

0.2

20

18

16

14

12

10

8

T_A= 25èC

T_A= -40èC

T_A= 125èC

0.19

0.18

0.17

0.16

0.15

0.14

0.13

0.12

0.11

0.1

6

4

2

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17

4

65

14

11

36

61

87

12

37

63

88

13

-0.

0.

1.

2.

Gain⁰E^.rror⁰(^.ppm/èC) ^1.

f_CLK(MHz)

-0.

D061

D046

HR mode

VLP mode, 30 Devices

Figure 39. Gain Error vs f_CLK

Figure 38. Gain Drift Histogram

250

200

150

100

50

5.29

5.27

5.25

5.23

5.21

5.19

5.17

5.15

5.13

5.11

5.09

T_A= 25èC

T_A= -40èC

T_A= 125èC

0

-50

-100

-150

-200

-250

-300

-40

-20

0

20

40

60

80

100 120 140

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Temperature (èC)

f_CLK(MHz)

D075

D062

HR mode, f_CLK= 16.384 MHz

Inputs shorted, HR mode

Figure 40. Offset Voltage vs f_CLK

Figure 41. Differential Input Impedance vs Temperature

21

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

180

170

160

150

140

130

120

110

100

90

180

170

160

150

140

130

120

110

100

90

AVDD

LVDD

DVDD

AVDD

DVDD

80

70

60

0

50 100 150 200 250 300 350 400 450 500

f_PS(kHz)

0

50 100 150 200 250 300 350 400 450 500

f_PS(kHz)

D076

D077

HR mode, INTLDO = 1

HR mode, INTLDO = 0

Figure 42. PSRR vs Power-Supply Frequency

Figure 43. PSRR vs Power-Supply Frequency

2

1.6

1.2

0.8

0.4

0

10

8

HR Mode

LP Mode

VLP Mode

HR Mode

LP Mode

VLP Mode

6

4

2

0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D056

D057

Figure 44. I_AVDDvs Temperature

Figure 45. I_LVDDvs Temperature

3

10

9

8

7

6

5

4

3

2

1

HR Mode

LP Mode

VLP Mode

2.4

1.8

1.2

0.6

0

HR Mode

LP Mode

VLP Mode

-40

-20

0

20

40

60

80

100

120

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Temperature (èC)

f_CLK(MHz)

D058

D063

Figure 46. I_DVDDvs Temperature

Figure 47. I_LVDDvs f_CLK

22

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

30

25

20

15

10

5

40

32

24

16

8

HR Mode

LP Mode

VLP Mode

HR Mode

LP Mode

VLP Mode

0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

Temperature (èC)

D059

D060

INTLDO = 1, LVDD = 1.8 V

Figure 48. Power Dissipation vs Temperature

INTLDO = 0

Figure 49. Power Dissipation vs Temperature

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

40

80

120

160

200

240

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Frequency (kHz)

D064

D065

Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples

Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples

Figure 50. Output Spectrum

Figure 51. Output Spectrum

0

-20

-40

-20

-40

-60

-80

-100

-120

-140

-160

-180

-100

-120

-140

-160

-180

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Frequency (kHz)

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

Frequency (kHz)

D065

D067

Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples

Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples

Figure 52. Output Spectrum

Figure 53. Output Spectrum

23

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

At T_A= 25°C, AVDD = 3.3 V, and external V_REF= 2.5 V (unless otherwise noted)

7000

6500

6000

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

0

5.4

2.1

4.2

6.4

8.5

Voltage (mV)

^-2.1Voltage (mV)

-5.4

-8.5

-6.4

-4.2

10.8

16.2

20.5

10.2

-20.5

-16.2

-10.8

-10.2

D068

D069

Inputs shorted, HR mode, LL, 512 kSPS, 32768 samples

Inputs shorted, HR mode, LL, 128 kSPS, 32768 samples

Figure 54. Noise Histogram

Figure 55. Noise Histogram

7000

6500

6000

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

6500

6000

5500

5000

4500

4000

3500

3000

2500

2000

1500

1000

500

0

6

4

2

0

2

4

6

2

1

-

0

1

2

-

7.6

3.1

4.1

D071

-7.6

-3.9

-3.1

Noise (mV)

Voltage (mV)

D070

Inputs shorted, HR mode, LL, 32 kSPS, 32768 samples

Inputs shorted, HR mode, LL, 8 kSPS, 32768 samples

Figure 56. Noise Histogram

Figure 57. Noise Histogram

7 Parameter Measurement information

7.1 Noise Performance

Adjust the oversampling ratio (OSR) to control the data rate and change the digital filter in order to optimize the

noise performance of the ADS127L01. Hardware control pins offer four oversampling options and three

selectable digital filter options to configure the ADC for a specific bandwidth of interest. When averaging is

increased by reducing the data rate (increasing the OSR), the in-band noise drops as more samples from the

modulator are averaged to yield one conversion result. Table 1 and Table 2 summarize the device noise

performance across the various oversampling and digital filter options. Wideband 1 filter has a filter transition

band of (0.45 to 0.55) f_DATA, and Wideband 2 filter has a filter transition band of (0.40 to 0.50) f_DATA. Data are

representative of typical noise performance at T_A= 25°C with an external 2.5-V reference. Data shown are the

result of one standard deviation of the readings with the inputs shorted together and biased to midsupply. A

minimum of 1,000 consecutive readings are used to calculate the V_{RMS_noise}voltage noise for each

measurement. Equation 1 is used to convert the noise in V_{RMS_noise}to SNR, and Equation 2 is used to convert

the noise in V_{RMS_noise}to ENOB. The peak-to-peak noise for the Low-latency filter is defined as V_{PP_noise}

.

SNR = 20 × log (V_REF× 0.7071 / V_{RMS_noise}

)

(1)

(2)

ENOB = In (2 x V_REF/ V_{RMS_noise}) / In (2)

24

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Noise Performance (continued)

Table 1. Wideband Filters Performance Summary

at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference

DATA RATE

(SPS)

PASS BAND

(kHz)

SNR

(dB)

V_{RMS_noise}

I_DVDD

(mA)

MODE

OSR

TRANSITION BAND

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

Wideband 1 filter

Wideband 2 filter

(μV_RMS

11.61

10.64

7.61

7.25

5.35

5.06

3.79

3.58

11.27

10.31

7.38

6.96

5.18

4.95

3.67

3.47

11.01

10.11

7.20

6.80

5.07

4.81

3.59

3.41

)

ENOB

18.72

18.84

19.33

19.40

19.83

19.91

20.33

20.41

18.76

18.89

19.37

19.45

19.88

19.95

20.38

20.46

18.79

18.92

19.41

19.49

19.91

19.99

20.41

20.48

230.4

204.8

115.2

102.4

57.6

51.2

28.8

25.6

115.2

102.4

57.6

51.2

28.8

25.6

14.4

12.8

57.6

51.2

28.8

25.6

14.4

12.8

7.2

103.7

104.1

107.3

107.7

110.4

110.9

113.4

113.9

103.9

104.7

107.6

108.1

110.7

111.1

113.7

114.1

104.1

104.9

107.8

108.3

110.9

111.3

113.9

114.3

512,000

256,000

128,000

64,000

256,000

128,000

64,000

32,000

128,000

64,000

32,000

16,000

32

7.50

4.35

2.80

2.00

3.80

2.25

1.50

1.10

1.95

1.20

0.80

0.60

64

128

256

32

High-resolution

(HR)

64

Low-power

(LP)

128

256

32

64

Very-low-power

(VLP)

128

256

6.9

Table 2. Low-Latency Filter Performance Summary

at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference

-3-dB

DATA RATE

(SPS)

BANDWIDTH

(kHz)

SNR

(dB)

V_{RMS_noise}

V_{PP_noise}

(μV_PP)

I_DVDD

(mA)

MODE

OSR

32

(μV_RMS

7.40

5.12

2.74

1.41

7.22

4.97

2.65

1.37

6.97

4.80

2.57

1.34

)

ENOB

19.37

19.90

20.80

21.76

19.40

19.94

20.85

21.80

19.45

19.99

20.89

21.83

512,000

128,000

32,000

8,000

101.8

50.6

13.7

3.5

107.6

110.8

116.2

122.0

107.8

111.0

116.5

122.2

108.1

111.3

116.7

122.4

64.67

44.11

24.14

11.32

61.99

46.79

22.05

10.73

65.57

39.64

20.27

10.73

1.60

1.39

1.33

1.32

0.85

0.75

0.73

0.72

0.50

0.44

0.41

0.40

128

512

2048

32

High-resolution

(HR)

256,000

64,000

16,000

4,000

50.9

25.3

6.9

128

512

2048

32

Low-power

(LP)

1.7

128,000

32,000

8,000

25.5

12.7

3.4

128

512

2048

Very-low-power

(VLP)

2,000

0.9

25

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

8 Detailed Description

8.1 Overview

The ADS127L01 is a 24-bit delta-sigma (ΔΣ) ADC that offers a combination of excellent dc accuracy and ac

performance. The flexible digital-filter options make it suitable for both dc and ac applications. The device is

hardware programmable, making it easy to configure for a variety of applications without the need to program

any registers.

The Functional Block Diagram shows the main internal features of the ADS127L01. The converter is comprised

of a third-order, chopper-stabilized, delta-sigma modulator, that measures the differential input signal, V_IN

=

(V_AINP– V_AINN), against the differential reference, V_REF= (V_REFP– V_REFN). The converter core consists of a

differential, switched-capacitor, delta-sigma modulator followed by a selectable digital filter. The digital-filter low-

latency path uses a cascaded combination of a fifth-order sinc and a first-order sinc filter, ideal for applications

requiring fast response time or systems using a multiplexed input. Two wide-bandwidth paths (Wideband 1 and

Wideband 2) are also available, providing outstanding frequency response with very low pass-band ripple, a

steep-transition band, and high stop-band attenuation. The ADS127L01 provides two selectable options for

transition-band frequency. The Wideband-filter paths are suited for applications that require high-resolution

measurements of high-frequency, ac-signal content. To allow tradeoffs among speed, resolution, and power,

three operating modes are supported: high-resolution (HR), low-power (LP), and very-low-power (VLP).

In HR mode, SNR = 104.4 dB (V_REF= 2.5 V) at a maximum data rate of 512 kSPS. At this data rate, the power

dissipation is only 35 mW, and scales with master clock frequency. In LP mode, the maximum data rate is 256

kSPS, while consuming only 19 mW of power. In VLP mode, the maximum data rate is 128 kSPS, while

consuming only 9 mW of power.

Configure the ADS127L01 by setting the appropriate hardware I/O pins. Registers are available for gain and

offset calibrations. Three interface communication modes are available, providing flexibility for convenient

interfacing to microcontrollers, DSPs, or FPGAs. SPI, frame-sync slave, or frame-sync master communication

modes are hardware selectable on the device. The ADS127L01 has a daisy-chain output available, and can

synchronize externally to another device or system using the START signal. The daisy-chain configuration allows

the device to be used conveniently in systems that require multiple channels.

8.2 Functional Block Diagram

REFP REFN LVDD AVDD

DVDD

LDO

INTLDO

SCLK

CS

SPI and

Frame-Sync

Interface

Low-Latency

Filter

DIN

AINP

AINN

DOUT

ûꢀ ADC

Modulator

Wideband 1

Filter

DRDY/FSYNC

DAISYIN

Wideband 2

Filter

FSMODE

FORMAT

Control Logic

RESET/PWDN

OSR [1:0]

FILTER [1:0]

CLK

ADS127L01

DGND

AGND

26

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

8.3 Feature Description

This section discusses the details of the ADS127L01 internal functional elements. Throughout this document,

f_CLKdenotes the frequency of the signal at the CLK pin, t_CLKdenotes the period of the signal at the CLK pin, f_DATA

denotes the output data rate, and t_DATAdenotes the time period of the output data.

8.3.1 Analog Inputs (AINP, AINN)

The ADS127L01 measures the differential input signal V_IN= (V_AINP– V_AINN) against the differential reference

V_REF= (V_REFP– V_REFN). The most positive measurable differential input is +V_REFand the most negative

measurable differential input is –V_REF

.

For optimum performance, drive the ADS127L01 inputs differentially, centered around a common-mode voltage

of AVDD / 2. Alternatively, if the signal is of pseudo-differential nature, the negative input can be held at a

constant voltage other than 0 V (typically AVDD / 2), and the voltage on the positive input can change. Figure 58

and Figure 59 show examples of both fully-differential and pseudo-differential signals, respectively.

AINP

V_CM

1.5 V

AINN

0 V

Figure 59. Pseudo-Differential Input Signal

Figure 58. Fully-Differential Input Signal

Electrostatic discharge (ESD) diodes to AVDD and AGND protect the inputs. To prevent the ESD diodes from

turning on, the absolute voltage on any input must stay within the range provided by Equation 3:

AGND – 0.3 V < V_AINx< AVDD + 0.3 V

(3)

The analog input pins, AINP and AINN, at the front end of the converter are connected directly to the switched-

capacitor sampling network to measure the input voltage. Figure 60 shows a conceptual diagram of the

modulator circuit charging and discharging the sampling capacitor through switches, although the actual

implementation is slightly different. The sampling time (t_CLK/ 2) is equivalent to half the master clock period, and

is the inverse of the modulator sampling frequency.

AVDD AGND

t_CLK= 1/f_CLK

AINP

S1

ON

S1

S2

OFF

S2

8 pF

ON

AINN

OFF

AVDD AGND

Figure 60. Equivalent Analog Input Circuitry

27

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Feature Description (continued)

The average load presented by the switched-capacitor input can be modeled with an effective differential

impedance, as shown in Figure 61. The effective impedance is a function of the modulator clock, and is equal to

the master clock, f_CLK. The ADS127L01 samples the input at very high speeds, and does not include an

integrated buffer; a suitable driver must be used. See the Application and Implementation section for

recommended driver circuit designs.

AINP

Z_eff= 5 kꢀ x (16.384 MHz/f_CLK

)

AINN

Figure 61. Effective Input Impedance

The ADC sampling network is connected to a delta-sigma modulator used to convert the analog input voltage

into a data bit stream. The modulator is third-order, with a multibit quantizer that runs at the modulator clock

frequency, f_MOD, equal to the master clock frequency, f_CLK

.

8.3.2 Digital Filter

The ADS127L01 offers three selectable digital filters to perform both filtering and decimation of the digital data

stream coming from the modulator. The oversampling ratio (OSR) and digital-filter selection sets the overall

frequency response for the data converter. The available filter options for the ADS127L01 are:

•

Low-latency sinc filter (LL)

Wideband finite impulse response (FIR) filter with a transition band of (0.45 to 0.55) × f_DATA(WB1)

Wideband finite impulse response (FIR) filter with a transition band of (0.40 to 0.50) × f_DATA(WB2)

Use the hardware FILTER[1:0] pins shown in Table 11. Each filter has four OSR options (the ratio of the

modulator sampling to the output data rate, or f_MOD/ f_DATA), shown in Table 12, that are selectable through

hardware OSR[1:0] pins. The low-latency sinc filter is a cascaded sinc5 and sinc1 filter, and provides OSR

options to achieve data rates ranging from 8 kSPS to 512 kSPS when operating from a 16.384-MHz master

clock. The two Wideband filters use a multistage FIR topology to provide linear phase response with very low

pass-band ripple and high stop-band attenuation. Wideband filters 1 and 2 provide four OSRs to achieve data

rates ranging from 64 kSPS to 512 kSPS when operating from a 16.384-MHz master clock.

Select the filter and data rate when START is low, or take the START or RESET/PWDN pin low and back high

after a filter-path or data-rate change. If software commands are used to control conversions, use the STOP and

START commands after a change to the filter path selection or the data rate. If a conversion is in process during

a filter-path or data-rate change, the output data are not valid and must be discarded.

8.3.2.1 Low-Latency Filter

The low-latency sinc filter consists of two stages: a fixed-decimation, sinc5 filter, followed by a variable-

decimation, sinc1 filter. The first-stage, sinc5 digital filter decimates by a fixed value of 32. When using OSR 32,

the first-stage digital filter bypasses the second filter stage, and has a sinc5 frequency response profile. The

second digital-filter stage provides an additional decimation of 4, 16, or 64 to create overall decimation options of

128, 512, and 2048. Together, the two stages create four selectable, Low-latency, filter data rates when operated

from a 16.384-MHz clock: 512 kSPS, 128 kSPS, 32 kSPS, and 4 kSPS.

8.3.2.1.1 Low-Latency Filter Frequency Response

The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC when in low-latency

filter mode. The frequency response of OSR 32 is from only the sinc5 filter stage. The frequency response of

OSR 128, 512, or 2048 is the product of the sinc5 first-stage and sinc1 second-stage frequency responses. The

overall filter response is given in Equation 4:

28

ADS127L01

www.ti.com.cn

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

Feature Description (continued)

5

»

…

ÿ

Ÿ

⁄

»

…

ÿ

Ÿ

⁄

32pf

f_CLK

32Npf

f_CLK

sin

H_(f)= H_sinc₅(f) ì H

(f) =

ì

sinc¹

»

…

ÿ

Ÿ

⁄

»

…

ÿ

Ÿ

⁄

pf

f_CLK

32pf

f_CLK

32ì sin

Nì sin

where

•

f = signal frequency

f_CLK= ADC master clock frequency = ADC modulator clock frequency

N = Second-stage oversampling = 1 (OSR 32), 4 (OSR 128), 16 (OSR 512), or 64 (OSR 2048)

(4)

The inherent nature of the sinc filter response begins to attenuate frequencies as the signal moves away from dc.

The pass band droop for inband ac signals makes the low-latency filter less ideal for ac signals.

As shown in Figure 62 and Figure 63, when OSR is set to 32, the digital filter frequency response follows a sinc5

transfer function with nulls occurring at f_DATAand at multiples thereof. At the null frequencies, the filter has zero

gain. Convert the x-axis from the data rate, f_DATA, to terms of the master clock, f_CLK, by using Equation 5:

f_DATA= f_CLK/ OSR

(5)

0

-20

0

-25

-40

-50

-60

-75

-80

-100

-125

-150

-175

-200

-225

-250

-100

-120

-140

-160

-180

-200

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Normalized Input Frequency (f_IN/f_DATA

)

Normalized Input Frequency (f_IN/f_DATA

)

D001

D002

Figure 62. Low-Latency Filter Frequency Response

(OSR 32)

Figure 63. Low-Latency Filter Frequency Response

(OSR 32) to f_CLK

Adjust the digital-filter response by changing the OSR or the master clock, f_CLK. Noise tradeoffs are made with

signal bandwidth and filter latency.

Selecting an OSR other than 32 superimposes new nulls from the second-stage sinc1 filter over the nulls

produced by the sinc5 stage. The end result is a combined frequency response from a sinc5 function at OSR 32

with nulls created from the sinc1 second stage at f_DATAand multiple thereof.

Figure 64 and Figure 65 illustrate the normalized frequency response of the Low-latency filter across all four

OSR settings. OSR 32 follows a sinc5 frequency response, as highlighted in Figure 62. OSR 128, OSR 512, and

OSR 2048 show a combined sinc5 and sinc1 response.

Figure 66, Figure 67, and Figure 68 illustrate the frequency response of OSR 128, OSR 512, and OSR 2048,

respectively.

The Low-latency filter uses a multiple-stage, linear-phase, digital filter. Linear-phase filters exhibit constant delay

time versus input frequency (also known as constant group delay). This feature of linear phase filters means that

the time delay from any instant of the input signal to the corresponding same instant of the output data is

constant and independent of the input-signal frequency. This behavior results in essentially zero phase error

when measuring multitone signals.

29

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Feature Description (continued)

0

-2

-20

-40

-4

-60

-6

-80

-8

-100

-120

-10

-12

-14

-16

-18

-20

-140

OSR 32

OSR 128

OSR 512

OSR 2048

OSR 128

OSR 512

OSR 2048

-160

-180

-200

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0

0.1

0.2

0.3

0.4

0.5

Normalized Input Frequency (f_IN/f_DATA

)

Normalized Input Frequency (f_IN/f_DATA)

D003

Figure 64. Low-Latency Filter Frequency Response

Figure 65. Low-Latency Filter Frequency Response

to 0.5 × f_IN/ f_DATA

0

-25

0

-25

-50

-75

-100

-125

-150

-175

-200

-225

-250

-100

-125

-150

-175

-200

-225

-250

0

20

40

60

80

100

120

0

80

160

240

320

400

480

Normalized Input Frequency (f_IN/f_DATA

)

Normalized Input Frequency (f_IN/f_DATA

)

D004

D005

Figure 66. Low-Latency Filter Frequency Response

(OSR 128) to f_CLK

Figure 67. Low-Latency Filter Frequency Response

(OSR 512) to f_CLK

0

-25

-50

-75

-100

-125

-150

-175

-200

-225

-250

0

300

600

900

1200

1500

1800

2100

Normalized Input Frequency (f_IN/f_DATA

)

D006

Figure 68. Low-Latency Filter Frequency Response

(OSR 2048) to f_CLK

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Feature Description (continued)

8.3.2.1.2 Low-Latency Filter Settling Time

The Low-latency filter takes several conversion cycles to provide fully-settled data following a START pin low-to-

high transition or a START command. The OSR setting determines the exact number of conversion cycles for

first new available data, as shown in Table 3. In SPI mode, the DRDY signal remains high until settled data are

available. After settled data are available, a high-to-low transition on DRDY takes place. In frame-sync mode,

DOUT shifts zeroes until settled data are available. Figure 69 shows the relationship between START to the first

settled available data for SPI and frame-sync interface mode. See the Start Pin (START) section for exact timing

for the START pin to first available data.

START

Command

or

START Pin

DRDY

Settled Data

FSYNC

Figure 69. START to First Available Data

When applying an asynchronous step input to a converting ADS127L01, the output shift register does not gate

data during digital-filter settling. The step-input-setting timing diagram shown in Figure 70 illustrates the converter

step response with an asynchronous step input. The time that the analog input must be stable varies depending

on the OSR. Table 3 summarizes the settling time of the Low-latency filter when a step input is applied to the

input.

Step Input

1

2

DRDY

FSYNC

Figure 70. Asynchronous Step-Input Settling Time

Table 3. Low-Latency Filter Settling Time (Conversion Latency)

OSR

SETTLING TIME FROM START

(t_CLKPeriods)

INPUT SETTLING

(DRDY or FSYNC Pulses)

32

128

512

2048

160

288

5

3

2

672

2208

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8.3.2.2 Wideband Filter

The two Wideband filters use a multistage FIR topology to provide linear phase response with minimal pass-band

ripple and high stop-band attenuation. The filters are well suited for measuring high-frequency ac signals while

still maintaining excellent dc accuracy. Both Wideband filter options offer the same four OSR options; 32, 64,

128, and 256. The difference is in the transition band. When these four OSRs are paired with a 16.384-MHz

clock, four selectable Wideband filter data rates are created: 512 kSPS, 256 kSPS, 128 kSPS, and 64 kSPS.

8.3.2.2.1 Wideband Filters Frequency Response

Figure 71 shows the frequency response of the Wideband 1 filter with a transition band of (0.45 to 0.55) × f_DATA

normalized to the output data rate, f_DATA. Figure 72 shows the frequency response of the Wideband 2 filter with a

transition band of (0.40 to 0.50) × f_DATAnormalized to the output data rate, f_DATA. These plots are valid for all of

the data rates available on the ADS127L01. Substitute the selected data rate, f_DATA(calculated using

Equation 5), to express the x-axis in absolute frequency. Figure 73 overlaps the transition band of the Wideband

1 and Wideband 2 filters, showing the difference in frequency response. The Wideband 2 filter frequency

response is designed to attenuate out-of-band signals more than –116 dB by the Nyquist frequency (0.5 × f_DATA

)

to reduce the effects of aliasing near the transition band.

10

0

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-100

-110

-120

-130

-140

-150

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

Normalized Input Frequency (f_IN/f_DATA

)

Normalized Input Frequency (f_IN/f_DATA)

D007

D008

FILTER[1:0] = 00

FILTER[1:0] = 01

Figure 71. Wideband 1 Filter Frequency Response

Figure 72. Wideband 2 Filter Frequency Response

10

0

-10

WB1 Filter

WB2 Filter

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

0.35

0.4

0.45

0.5

0.55

0.6

Normalized Input Frequency (f_IN/f_DATA

)

D001

Figure 73. Wideband Filters Transition Band

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The pass-band ripple for the two digital filters are shown in Figure 74 and Figure 75.

0.00010

0.00008

0.00006

0.00004

0.00002

0.00000

-0.00002

-0.00004

-0.00006

-0.00008

-0.00010

0.00010

0.00008

0.00006

0.00004

0.00002

0.00000

-0.00002

-0.00004

-0.00006

-0.00008

-0.00010

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55

Normalized Input Frequency (f_IN/f_DATA

)

Normalized Input Frequency (f_IN/f_DATA)

D010

D011

FILTER[1:0] = 00

FILTER[1:0] = 01

Figure 74. Pass Band Ripple for Wideband 1 Filter

Figure 75. Pass Band Ripple for Wideband 2 Filter

The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock

frequency, f_CLK. Figure 76 shows the response with the fastest data rate selected (512 kSPS when f_CLK= 16.384

MHz).

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30 32

Normalized Input Frequency (f_IN/f_DATA

)

D013

Figure 76. Extended Frequency Response of Wideband 1 Filter (OSR 32)

The Wideband filters use a multiple-stage, linear-phase, digital-filter architecture. Linear-phase filters exhibit

constant delay time versus input frequency (also known as constant group delay). This feature of linear phase

filters means that the time delay from any instant of the input signal to the corresponding same instant of the

output data is constant and independent of the input-signal frequency. This behavior results in essentially zero

phase error when measuring multitone signals.

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8.3.2.2.2 Wideband Filters Settling Time

The Wideband filters fully settle before outputting data after the START pin low-to-high transition or a START

command is issued. The settling time of the Wideband filters is 84 conversion cycles; the DRDY signal idles high

and does not assert until new settled data are available in SPI interface mode. In frame-sync interface mode, the

output shift register outputs zeroes in place of the conversion data for 84 conversion cycles until the first settled

data are available. A step input on the analog input requires multiple conversions to settle if START is not

pulsed, or if the START command is not issued. Figure 77 shows the settling response with the x-axis

normalized to conversions or DRDY/FSYNC cycles.

150

Fully Settled Data at 84 Conversions

130

110

90

70

50

30

10

-10

-30

-50

0

10

20

30

40

50

60

70

80

90 100

Conversions (1/f_DATA

)

D012

Figure 77. Step Response For Wideband Filters

Figure 78 and Figure 79 plot the undershoot and overshoot from the Wideband digital filter during an input step

function.

60

65

120

115

110

105

100

95

70

75

80

85

90

95

85

100

105

110

115

120

80

75

70

65

60

40

42

44

46

48

50

52

54

56

58

60

40

42

44

46

48

50

52

54

56

58

60

Conversions (1/f_DATA

)

Conversions (1/f_DATA

)

D001

D00210

Figure 78. Wideband Filters Step-Response Undershoot

Figure 79. Wideband Filters Step-Response Overshoot

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8.3.3 Voltage Reference Inputs (REFP, REFN)

The ADC requires the connection of an external reference voltage for operation. The voltage reference for the

device is the differential voltage between REFP and REFN: V_REF= (V_REFP– V_REFN). The reference inputs are not

buffered and use a sampling structure similar to that of the analog inputs, with the equivalent circuitry on the

reference inputs shown in Figure 80. The load across REFP and REFN is presented by the switched-capacitor in

parallel with a 6.4-kΩ resistor, and is modeled with an effective impedance (Z_eff) proportional to the master clock,

f_CLK, as shown in Figure 81.

REFP

REFN

AVDD

AGND

AVDD

AGND

Figure 80. Equivalent Reference Input Circuitry

REFP

REFN

Z_eff= (3.4 kꢀ × 16.384 MHz / f_CLK) || 6.4 kꢀ

Figure 81. Effective Reference Impedance

ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the

reference pins do not go below AGND by more than 0.3 V, and do not exceed AVDD by 0.3 V. Use external

Schottky clamp diodes or series resistors to limit the input current to safe values if the reference input may

exceed the absolute maximum ratings (see the Absolute Maximum Ratings table).

A high-quality reference voltage with the appropriate drive strength is required for achieving the best

performance from the ADS127L01. Noise and drift on the reference degrade overall system performance. Use a

minimum parallel combination of 10-µF and 0.1-µF ceramic bypass capacitors directly across the reference

inputs, REFP and REFN. Place these capacitors as close as possible to the device on the layout. See the

Application Information section for example reference circuits.

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8.3.4 Clock Input (CLK)

The ADS127L01 requires an external clock for operation. This clock signal is used for the sampling network of

the modulator without any prescalers or dividers, and for the timing for the digital filter. Drive the ADC with an

external clock by applying the clock input to the CLK pin. At the maximum data rate, the clock input is 16.384

MHz for HR mode, 8.192 MHz for LP mode, and 4.096 MHz for VLP mode.

A high-quality, low-jitter clock is essential for optimum performance measuring the high-frequency input signals.

Any uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. For example,

uses an external clock with better than 10 ps_rmsjitter for a 200-kHz f_IN. For a lower f_IN, the target jitter

requirement can be relaxed by –20 dB per decade. At f_IN= 20 kHz, use a clock with better than 100-ps_rmsjitter.

The selection of the external clock frequency (f_CLK) does not affect the resolution of the ADS127L01. The output

data rates scale with f_CLKfrequency down to a minimum clock frequency of f_CLK= 100 kHz. Use a slower f_CLKto

reduce the ADC power consumption and relax the requirements of an external ADC drive circuit on the analog

input and reference input.

Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock

input. A series resistor placed at the external clock buffer output often helps to reduce overshoot.

8.3.5 Out-of-Range-Detect System Monitor

An out-of-range-detect system-monitor bit (INP) is available in the status word (see the Status Word section).

The out-of-range detect bit flags (INP = 1) when the input exceeds the positive or negative full-scale range, set

by V_REF, with each conversion result. The input is monitored using an analog comparator. The flag is issued

when the full-scale range is exceeded without waiting for the conversions to propagate through the digital filter.

The INP bit is used for narrow out-of-range input glitches that may or may not be removed by the ADC digital

filter.

8.3.6 System Calibration

The ADC incorporates optional offset- and gain-calibration registers to system-calibrate the ADC and signal chain

when in SPI interface mode. Enable the offset calibration register by setting FSC bit (bit 5 in the Configuration

register) to 1, and enable the gain calibration register by setting OFC bit (bit 4 in the Configuration register) to 1.

The programmable offset calibration value is 24 bits wide, and the gain calibration value is 16 bits wide. Use

calibration to correct internal ADC errors or overall system errors. Calibration is only supported through direct

user calibration, requiring the user to calculate and write the correction values to the calibration registers.

Perform a system offset calibration before full-scale calibration. After power-up, but before calibrating, wait for the

power supplies and reference voltage to fully settle.

As shown in Figure 82, the value of the offset calibration register is subtracted from the filter output, and then

multiplied by the full-scale register value. The data are then clipped to a 24-bit value to provide the final output.

AINP

+

Digital

Filter

Output Data

Clipped to 24 Bits

Final

Output

ADC

AINN

-

OFC[2:0] registers

(register addresses = 02h, 03h, 04h)

FSC[1:0] registers

(register addresses = 05h, 06h)

> 000000h: negative offset

000000h: no offset

< 000000h: positive offset

< 8000h: gain > 1

8000h: gain = 1

> 8000h: gain < 1

Figure 82. ADC Calibration Block Diagram

Equation 6 shows the internal calibration on the data result.

ADC Final Output Data = (Filter Output – OFC[23:0]) × FSC[15:0] / 8000h

(6)

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The ADC offset calibration word is 24 bits, consisting of three 8-bit registers (OFC2, OFC, 1 OFC0), as shown in

Table 4. The offset value is twos complement format with a maximum positive value equal to 7FFFFFh (for

negative offset), and a maximum negative value equal to 800000h (for positive offset). A register value equal to

000000h has no offset correction. For offset calibration, short the ADC inputs or system inputs, and average the

conversions; averaging reduces noise for a more accurate calibration. Write the average value to the offset

calibration registers. The ADC subtracts the value from the conversion result.

Table 4. Offset Calibration Registers

BYTE

ORDER

REGISTER

ADDRESS

BIT ORDER

OFC_B4 OFC_B3

OFC_B0

(LSB)

OFC0

OFC1

OFC2

LSB

02h

03h

04h

OFC_B7

OFC_B6

OFC_B5

OFC_B2

OFC_B1

MID

OFC_B15 OFC_B14 OFC_B13 OFC_B12 OFC_B11 OFC_B10 OFC_B9

OFC_B23

OFC_B8

MSB

OFC_B22 OFC_B21 OFC_B20 OFC_B19 OFC_B18 OFC_B17 OFC_B16

(MSB)

The ADC gain calibration word is 16 bits consisting of two 8-bit registers (FSC1, FSC0), as shown in Table 5.

The full-scale calibration value is twos compliment, with a unity-gain correction factor at a register value equal to

8000h. Table 6 shows register values for selected gain factors.

Table 5. Gain Calibration Registers

BYTE

ORDER

REGISTER

FSC0

ADDRESS

05h

BIT ORDER

FSC_B4 FSC_B3

FSC_B14 FSC_B13 FSC_B12 FSC_B11 FSC_B10

FSC_B0

(LSB)

LSB

FSC_B7

FSC_B6

FSC_B5

FSC_B2

FSC_B1

FSC_B9

FSC_B15

(MSB)

FSC1

MSB

06h

FSC_B8

Table 6. Gain Calibration Register Values

FSCAL[2:0] REGISTER VALUE

GAIN FACTOR

7FFFh

8000h

0000h

2.00

1.00

0.00

For gain calibration, apply a dc calibration voltage that is less than positive full-scale voltage in order to avoid

clipped codes (V_IN< +FSR), and average the conversions to reduce noise for a more accurate calibration. Gain

calibration is computed as shown in Equation 7, after offset error is removed.

Full-Scale Calibration = Expected Code Value / Actual Code Value

(7)

If the actual code is higher than the expected value, then the calculated calibration value is less than 8000h, and

the ADC gain is subsequently reduced. Write the calibration value to the gain calibration registers.

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8.4 Device Functional Modes

8.4.1 Operating Modes (HR, LP, VLP)

The ADS127L01 offers three operational modes: high-resolution (HR), low-power (LP), and very-low-power

(VLP). These modes optimize power consumption by restricting the maximum master-clock frequency (f_CLK

)

controlling the data rate. The status of the HR pin determines if the device is in HR mode or LP mode. Enter VLP

mode by setting the ADS127L01 in LP mode, and increasing the value of the external R_EXTpower scaling

resistor from 60.4 kΩ to 120 kΩ. The tolerance on the R_EXTpower-scaling resistor must be 1% or better. The

analog current consumed by AVDD and LVDD decreases when in LP mode, and decreases further in VLP mode,

with a tighter restriction on maximum master-clock frequency. Table 7 details the HR pin and REXT settings for

each operating mode in the ADS127L01.

Table 7. Operating Mode Selection

OPERATING MODE

High-Resolution (HR)

Low-Power (LP)

OPERATING MODE SELECTION PIN (HR)

R_EXTVALUE

60.4 kΩ

MAXIMUM f_CLK

17.6 MHz

8.8 MHz

1

0

60.4 kΩ

Very-Low-Power (VLP)

120 kΩ

4.4 MHz

8.4.2 Hardware Mode Pins

The ADS127L01 uses two-state hardware mode pins for ADC configuration. The operating mode, interface

selection, digital filter selection, and oversampling ratio (OSR) are all controlled through hardware pins. These

pins are constantly monitored, and set by either pulling them high to DVDD, or low to DGND. Use pull-up or pull-

down 100-kΩ resistors, or directly tie the pins to microcontroller or DSP I/O lines to set the state of the pins.

When a change is sensed on the hardware mode pins after power-up, the ADC automatically issues a reset. To

ensure synchronization, issue a software reset command, or pulse the RESET/PWDN pin following the mode

change delay, t_d(MD)

.

When using the SPI interface mode, DRDY is held high after a mode change occurs until settled data are ready;

see Figure 83 and Table 8.

MODE

t_d(MD)

ADS127L01

Old Mode

New Mode

t_d(FILT)

Mode

CLK

t_d(NDR)

DRDY

Figure 83. Mode Change Timing (SPI Interface)

Table 8. SPI Interface New Data After Mode Change

SYMBOL

t_d(MD)

DESCRIPTION

MIN

TYP

MAX

3

UNIT

t_CLK

Delay time, MODE pin rising edge to mode change

Delay time, mode change to first modulator sample

t_d(FILT)

3.5

4.5

t_CLK

Wideband filters

Low-latency filter

84

t_DATA

t_d(NDR)

Delay time for new data to be ready

See Table 3

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In Frame-sync intreface mode, the DOUT pins are held low after a mode change occurs until settled data are

ready; see Figure 84 and Table 9. Data can be read from the device to detect when DOUT changes, indicating

that data are valid.

MODE

t_d(MD)

ADS127L01

Old Mode

New Mode

Mode

CLK

t_su(FILT)

FSYNC

DOUT

t_d(NDR)

New Data

Figure 84. Mode Change Timing (Frame-Sync Interface)

Table 9. Frame-Sync Interface New Data After Mode Change

SYMBOL

t_d(MD)

DESCRIPTION

Delay time, MODE pin rising edge to mode change

Setup time, mode change to FSYNC rising edge

MIN

TYP

MAX

UNIT

t_CLK

3

t_su(FILT)

Frame-sync slave

Frame-sync master

Wideband filters

Low-latency filter

5

1

t_CLK

t_d(NDR)

Delay time for new data to be ready

84

t_DATA

See Table 3

8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)

Data are read from the ADS127L01 using one of two selectable interface modes, SPI or frame-sync. Use the

FORMAT input pin to select among the two interface options.

If the frame-sync interface is selected, the ADS127L01 offers either a master or slave option, selectable using

the FSMODE pin. Table 10 lists the available options.

Table 10. Interface Mode Options

FORMAT

FSMODE

INTERFACE MODE

SPI

0

1

0

1

0

1

SPI

Frame-sync slave mode

Frame-sync master mode

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8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])

Three digital filter options are available in the ADS127L01: two Wideband filter options, and a Low-latency filter.

See the Digital Filter section for detailed information on the digital filters and the frequency responses. The

FILTER[1:0] hardware mode pins set the filter path selection for the modulator data, as shown in Table 11.

Select the filter when START is low, or take the START or RESET/PWDN pin low and back high after a filter

path change. If software commands are used to control conversions, use the STOP and START commands after

a change to the filter path selection. If a conversion is in process during a filter path change, the output data are

not valid and must be discarded.

Table 11. Digital-Filter Path Selection

FILTER1

FILTER0

SELECTED FILTER PATH

Wideband 1 filter

FILTER TRANSITION BAND

0.45 × f_DATAto 0.55 × f_DATA

0.40 × f_DATAto 0.50 × f_DATA

SINC5 / SINC

0

1

0

1

0

1

Wideband 2 filter

Low-latency filter

Reserved: do not use

8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])

The ADS127L01 has two hardware oversampling ratio (OSR) pins used to configure the converter data rate. The

rate at which the modulator bit stream data is decimated differs depending on whether the Wideband or the Low-

latency digital filter is used (set using the Digital-Filter Path Selection Pins (FILTER[1:0])). The OSR options and

corresponding maximum data rate at f_CLK= 16.384 MHz are shown in Table 12 for both the Wideband and the

Low-latency filters. Change the OSR when START is low, or take the START or RESET/PWDN pin low and back

high after changing the OSR. If software commands are used to control conversions, use the STOP and START

commands after changing the OSR.

Table 12. OSR Selection

DATA RATE (kSPS)

AT f_CLK= 16.384 MHz

FILTER

OSR1

OSR0

OSR

0

1

0

1

0

1

0

1

0

1

0

1

32

64

512

256

128

64

Wideband filters

128

256

32

512

128

32

128

512

2048

Low-latency filter

8

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8.4.3 Start Pin (START)

The START pin controls the start and stop of ADC conversions used for converter synchronization. Take the

START pin low to stop conversions and reset the digital filter. Pull START high to start or restart the conversions.

Synchronization allows the conversion to be aligned with an external event, such as the changing of an external

multiplexer on the analog inputs. The START pin is also used to synchronize multiple devices to within the same

CLK cycle.

Figure 85 and Figure 86 illustrate the timing requirement for the START pin with respect to CLK in SPI and

frame-sync interface modes. After synchronization, indication of valid data depends on whether SPI or frame-

sync interface mode is used.

In the SPI interface mode, DRDY goes high as soon as START is taken low, as shown in Figure 85. After

START is returned high, DRDY stays high while the digital filter completes reset and settles. After valid data are

ready for retrieval, DRDY goes low.

t_w(STL)

START

t_su(ST)

t_d(FILT)

CLK

t_d(NDR)

DRDY

Figure 85. Synchronization Timing (SPI Interface)

Table 13. SPI Interface Start

SYMBOL

t_w(STL)

DESCRIPTION

MIN

4

TYP

MAX

UNIT

t_CLK

ns

Pulse duration, START low

t_su(ST)

Setup time, START rising edge to CLK rising edge

10

4

t_d(FILT)

Delay time, START rising edge to first modulator sample

5

t_CLK

t_DATA

Wideband filters

Low-latency filter

84

t_d(NDR)

Delay time for new data to be ready

See Table 3

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In frame-sync interface, DOUT goes low as soon as START is taken low, as shown in Figure 86. After START is

returned high, the following FSYNC rising edge releases the digital filter from reset to begin conversions. DOUT

stays low while the digital filter is settling. Data are ready for retrieval on DOUT after the digital filter settles. For

proper synchronization, FSYNC, SCLK, and CLK must be established before taking START high, and must then

remain running. If either CLK, FSYNC or SCLK are interrupted or reset, reassert the START pin.

t_w(STL)

START

t_su(ST)

FSYNC

CLK

t_d(NDR)

Settled

Data

DOUT

Figure 86. Synchronization Timing (Frame-Sync Interface)

Table 14. Frame-Sync Interface Start

SYMBOL

DESCRIPTION

MIN

4

TYP

MAX

UNIT

t_CLK

t_w(STL)

Pulse duration, START low

Frame-sync slave

Frame-sync master

Wideband filters

Low-latency filter

6

t_CLK

Setup time, START rising edge to FSYNC rising

edge

t_su(ST)

5

t_CLK

84

t_DATA

t_d(NDR)

Delay time for new data to be ready

See Table 3

In addition to the START pin, START and STOP commands are also available to control the start and stop of

conversions, but only when using the SPI interface. Using the commands requires that the hardware START pin

is tied low the entire time. The START command is also used to synchronize multiple ADS127L01s sharing the

same SPI interface. See the SPI Commands section for information on using the START and STOP commands

to control ADC conversions.

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8.4.4 Reset and Power-Down Pin (RESET/PWDN)

The RESET/PWDN pin has two functions, depending on the amount of time the pin is held in a low state. If

RESET/PWDN is low for < 2¹⁵– 1 CLK periods, the ADS127L01 resets both the digital filter and register

contents to default settings. The low-to-high transition of the RESET/PWDN pin brings the ADS127L01 out of

reset by completing the digital filter reset, as shown in Figure 87 and Figure 88.

t_w(RSL)

RESET/PWDN

t_su(RS)

t_d(FILT)

CLK

t_d(NDR)

DRDY

Figure 87. Reset Timing (SPI Interface)

Table 15. SPI Interface Reset Timing

SYMBOL

t_w(RSL)

DESCRIPTION

MIN

4

TYP

MAX

2¹⁵– 1

UNIT

t_CLK

ns

Pulse duration RESET/PWDN low

t_su(RS)

Setup time, RESET/PWDN rising edge to CLK rising edge

Delay time, RESET/PWDN rising edge to first modulator sample

10

37

t_d(FILT)

t_CLK

t_DATA

Wideband filters

Delay time for new data to be ready

Low-latency filter

84

t_d(NDR)

See Table 3

t_w(RSL)

RESET/PWDN

t_su(RSS)

FSYNC

t_su(RSM)

t_d(RSM)

CLK

t_d(NDR)

Settled

Data

DOUT

Figure 88. Reset Timing (Frame-Sync Interface)

Table 16. Frame-Sync Interface Reset Timing

SYMBOL

DESCRIPTION

Pulse duration RESET/PWDN low

MIN

TYP

MAX

2¹⁵– 1

UNIT

t_CLK

t_w(RSL)

4

Frame-Sync Slave Mode: Setup time, RESET/PWDN rising edge to

first FSYNC

t_CLK

t_su(RSS)

t_su(RSM)

t_d(RSM)

7

10

4

Frame-Sync Master Mode: Setup time, RESET/PWDN rising edge to

CLK rising edge

ns

Frame-Sync Master Mode: Delay time, CLK rising edge to FSYNC

rising edge

t_CLK

Wideband filters

Delay time for new data to be ready

Low-latency filter

84

t_DATA

t_d(NDR)

See Table 3

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If RESET/PWDN is low for > 2¹⁵– 1 CLK periods, the ADS127L01 enters power-down mode where both the

analog and digital circuitry is completely deactivated. The digital inputs are internally disabled so there is no

concern in driving the pins.

Use individual 1-MΩ pull-down resistors placed on CAP3 to DGND, SCLK to DGND, and DRDY/FSYNC to

DGND if power-down mode is planned to be used. These resistors help discharge voltage when the device is

placed in power-down mode. Shut down the CLK and SCLK in power-down mode to avoid additional power

consumption.

Return the RESET/PWDN pin high to exit power-down mode. As shown in Figure 89 and Figure 90, a minimum

of 2¹⁵+ 37 master clock periods must elapse before the device exits power-down mode and begins sampling

when using SPI interface mode. DRDY stays high after exiting power-down mode while the digital filter settles.

t_w(PWDN)

RESET/PWDN

t_su(PWDN)

t_d(POR)

CLK

t_d(NDR)

DRDY

Figure 89. Power-Down Timing (SPI Interface)

Table 17. SPI Interface Power-Down Timing

SYMBOL

t_w(PWDN)

t_su(PWDN)

DESCRIPTION

Pulse duartionRESET/PWDN low

MIN

2¹⁵

TYP

MAX

UNIT

t_CLK

ns

Setup time, RESET/PWDN rising edge to CLK rising edge

10

Delay time, power-on-reset complete following RESET/PWDN rising

edge

2¹⁵+ 37

t_CLK

t_d(POR)

t_d(NDR)

Wideband filters

Delay time for new data to be ready

Low-latency filter

84

t_DATA

See Table 3

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A minimum of 2¹⁵+ 7 master clock periods must elapse before the device exits power-down mode to begin

sampling, when in Frame-Sync interface mode, as shown in Figure 90 and Table 18. When using Frame-Sync

interface mode, DOUT will read back low while the digital filter settles.

t_w(PWDN)

RESET/PWDN

FSYNC

CLK

t_d(PORS)

t_su(PORM)

t_d(PORM)

t_d(NDR)

Settled

Data

DOUT

Figure 90. Power-Down Timing (Frame-Sync Interface)

Table 18. Frame-Sync Interface Power-Down Timing

SYMBOL

DESCRIPTION

Pulse duration RESET/PWDN low

MIN

2¹⁵

TYP

MAX

UNIT

t_CLK

t_w(PWDN)

Frame-Sync Slave Mode, Delay time, RESET/PWDN rising edge to

FSYNC rising edge

2¹⁵+ 7

t_CLK

t_d(PORS)

t_su(PORM)

t_d(PORM)

Frame-Sync Slave Mode, Setup time, RESET/PWDN rising edge to

CLK rising edge

10

ns

Frame-Sync Slave Mode, Delay time, CLK rising edge to FSYNC

rising edge

2¹⁵+ 7

t_CLK

Wideband filters

Delay time for new data to be ready

Low-latency filter

84

t_DATA

t_d(NDR)

See Table 3

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8.5 Programming

Data are retrieved from the ADS127L01 using a serial interface. To provide easy connection to either

microcontrollers or DSPs, three communication modes are available: SPI, frame-sync master, and frame-sync

slave. The FORMAT and FSMODE hardware mode pins select the interface. The same communication pins are

used for all three interfaces: SCLK, DRDY/FSYNC, DIN, DAISYIN, and DOUT; however, functionality depends

on the interface selected.

When FORMAT = 0, SPI interface is selected, and the DRDY/FSYNC pin becomes a data ready (DRDY) output.

In SPI interface mode, commands and internal registers are available for further device configuration. Tie the

FSMODE pin to DGND when using SPI communication mode.

When FORMAT = 1, frame-sync interface mode is selected, and the DRDY/FSYNC pin becomes an FSYNC

input or output. Frame-sync offers two different modes controlled by the FSMODE pin.

When FSMODE = 0, the interface uses frame-sync slave mode, requiring that the SCLK and FSYNC signals are

driven by the processor to the ADS127L01.

When FSMODE = 1, the interface is set to frame-sync master mode, and the SCLK and FSYNC signals are

generated from the ADC derived from the master clock.

8.5.1 Serial Peripheral Interface (SPI) Programming

The SPI-compatible serial interface of the device is used to read conversion data, read and write the device

configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The

interface consists of five control lines (CS, SCLK, DIN, DOUT, and DRDY/FSYNC), but the interface is

operational with only four control lines. If the serial bus is not shared with any other device, CS can be tied low

permanently so that only signals SCLK, DIN, DOUT and DRDY/FSYNC are required to communicate with the

device.

8.5.1.1 Chip Select (CS)

Chip select (CS) is an active-low input that selects the device for SPI communication. CS must remain low for the

entire duration of the serial communication to complete a command or data readback. When CS is taken high,

the serial interface is reset, SCLK is ignored, and DOUT enters a high-impedance state. If the serial bus is not

shared with another peripheral, CS can be tied low.

8.5.1.2 Serial Clock (SCLK)

The serial clock (SCLK) features a Schmitt-triggered input, and is used to clock data into and out of the device

on DIN and DOUT, respectively. SCLKs can be sent to the ADC continuously or in byte increments. Even though

the input has hysteresis, keep the SCLK signal as clean as possible to prevent glitches from accidentally shifting

data. When the serial interface is idle, hold SCLK low.

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Programming (continued)

8.5.1.3 Data Ready (DRDY/FSYNC)

In SPI interface mode, DRDY/FSYNC is an active-low, new-data-ready indicator for when a new conversion

result is ready for retrieval. When DRDY/FSYNC transitions low, new conversion data are ready. The

DRDY/FSYNC signal transitions from low to high with the first SCLK falling edge, as shown in Figure 91. When

no data are read during continuous conversion mode, DRDY/FSYNC remains low but pulses high for a duration

of 2 · t_CLKbefore the next DRDY/FSYNC falling edge. The DRDY/FSYNC pin is always actively driven, even

when CS is high.

A new conversion result is loaded into the output shift register before DRDY transitions from high to low. The

LSB of the previous data word must be read at least 4 · t_CLKbefore the next DRDY falling edge. This delay is

known as keep-out time (t_KO). Keep SCLK low during t_KOuntil the next conversion result is ready for retrieval, as

shown in Figure 91.

CLK

DRDY

t_KO

SCLK

MSB

MSB œ 1

LSB + 1

LSB

DOUT

MSB

Figure 91. SPI Keep-Out Time (t_KO

)

8.5.1.4 Data Input (DIN)

The data input pin (DIN) is used with SCLK to send data (commands and register data) to the device. The device

latches data on DIN on the SCLK falling edge. The device never drives the DIN pin.

8.5.1.5 Data Output (DOUT)

DOUT is used with SCLK to read conversion and register data from the device. Data on DOUT are shifted out on

the SCLK rising edge, to be read from the host on the SCLK falling edge. DOUT goes to a high-impedance state

when CS is high.

8.5.1.6 Daisy-Chain Input (DAISYIN)

DAISYIN is an optional pin used with SCLK to shift data in from a secondary ADS127L01 device when in a

daisy-chain configuration. Data are shifted out from DOUT of a secondary device into the DAISYIN pin of the first

device. The individual data bits are latched into DAISYIN on the SCLK falling edge. See the Multiple Device

Configuration section for more information on using daisy-chain mode. If not used, tie the DAISYIN pin to DGND.

8.5.1.7 SPI Timeout

The ADS127L01 offers an SPI timeout feature that is used to recover communication when a serial interface

transmission is interrupted. This feature is especially useful in applications where CS is permanently tied low and

is not used to frame a communication sequence.

The timeout feature is disabled by default, but can be enabled in the CONFIG register. The time for the timeout

to issue is also configurable using the CONFIG register. When enabled, and whenever a complete command is

not sent within 2¹⁴· t_CLKor 2¹⁶· t_CLK(configurable by the TOUT_DEL bit in the CONFIG register), the serial

interface resets and the next SCLK pulse starts a new communication cycle. For the RREG and WREG

commands, a complete command includes the command byte plus the register bytes that are read or written.

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Programming (continued)

8.5.1.8 SPI Commands

The ADS127L01 provides flexible configuration, including commands and configurable registers, only when using

the SPI interface. The commands, summarized in Table 19, are stand-alone and configure the operation of the

ADS127L01. Each command is a single byte, except for the register read and write operations that require two or

more bytes. CS must remain low for the entire command operation (especially for multibyte commands). Take

CS high during a opcode command to abort the command.

Table 19. Command Definitions

COMMAND

System Commands

RESET

DESCRIPTION

FIRST BYTE

SECOND BYTE

Reset the device

0000 011x

0000 100x

0000 101x

START

Start or restart (synchronize) conversions

Stop conversion

STOP

Data Read Commands

RDATA

Read data by command

0001 0010

Register Commands

RREG

Read (nnnn + 1) registers starting at address rrrr

Write (nnnn + 1) registers starting at address rrrr

0010 rrrr

0100 rrrr

0000 nnnn

WREG

8.5.1.8.1 RESET (0000 011x)

The RESET command halts conversions and resets the ADC to power-on-reset values. During this time, the

digital filter resets, requiring an additional power-up time for conversions to begin. The RESET command is

decoded by the ADS127L01 on the seventh falling edge of SCLK. For more information, refer to the Reset and

Power-Down Pin (RESET/PWDN) section.

8.5.1.8.2 START (0000 100x)

The START command starts conversions and resynchronize the device. When conversions are stopped, either at

power-up or following a STOP command, issue a START command to begin ADC conversions. Issuing a START

command restarts the conversions by resetting the digital filters. During the reset period, DRDY/FSYNC does not

toggle. The START command is decoded by the ADS127L01 on the seventh falling edge of SCLK. The START

pin must be held low if the START and STOP commands are used. For more information, refer to the Start Pin

(START) section.

8.5.1.8.3 STOP (0000 101x)

The STOP command places the ADC in an idle state where the modulator stops converting. The STOP

command is decoded by the ADS127L01 on the seventh falling edge of SCLK. The START pin must be held low

if the START and STOP commands are used.

8.5.1.8.4 RDATA (0001 0010)

The RDATA command reloads the output shift register to the MSB of the most recent data. The RDATA

command is decoded on the eighth SCLK falling edge, and begins shifting out the MSB of the data word on

DOUT on the ninth SCLK.

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8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)

The RREG command reads the number of bytes specified by nnnn (number of registers to be read – 1) from the

device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes

are clocked out after the RREG command byte. For example, the command to read three registers (nnnn =

0010) starting at register address 00h (rrrr = 0000) is 0010 0000 0000 0010 as shown in Figure 92. The

communication length must be extended by the proper number of SCLKs to shift register contents out.

1^st

2^nd

Command

Byte

Command

Byte

DIN

0010 0000

0000 0010

DOUT

ID

CONFIG

OFC0

Data

Byte

Data

Byte

Data

Byte

Figure 92. Read from Register

8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)

The wREG command writes the number of bytes specified by nnnn (number of registers to be written – 1) to the

device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes

are clocked in after the WREG command byte. For example, the command to write two registers (nnnn = 0001)

starting at register address 01h (rrrr = 0001) is 0100 0001 0000 0001 as shown in Figure 93. Two bytes follow

the command to write the contents to the registers. The frame must extend by the proper number of SCLKs to

write data to the registers.

DIN

0100 0001

0000 0001

CONFIG

OFC0

1^st

2^nd

Command

Byte

Data

Byte

Data

Byte

Command

Byte

Figure 93. Write to Register

8.5.2 Frame-Sync Programming

Frame-sync interface is similar to the interface often used on audio ADCs. The ADS127L01 offers both frame-

sync master and frame-sync slave modes that are selectable using the FSMODE pin. In frame-sync format,

commands and register assignments are not available. Tie DIN low to DGND.

8.5.2.1 Frame-Sync Master Mode

When operating in frame-sync master mode, the ADC acts as the system master, and provides the FSYNC,

SCLK, and DOUT signals. The FSYNC and SCLK signals are derived as a function of the master clock input,

f_CLK. The data are output MSB first on the rising edge of FSYNC.

8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode

CS is not used in frame-sync interface mode.. Tie the CS pin to DGND.

8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode

When operating in frame-sync master mode, the serial clock (SCLK) is derived from the master clock and

provided from the ADC to the microprocessor. Every frame period, t_c(FRAME), includes 32 SCLKs to shift all data

out before new data are ready. This SCLK speed is proportional to the frame size, t_c(FRAME)/ 32 in frame-sync

master mode. The frame size is determined by the data rate setting using the hardware FILTER pin settings,

OSR pin settings, and speed of the master clock, f_CLK. The data on DOUT are clocked out on the falling edge of

SCLK to be latched by the host processor on the rising edge of SCLK.

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8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode

In frame-sync master mode, the FSYNC pin is an output whose period is proportional to the ADC programmed

data rate. Within each FSYNC period are 32 SCLKs to shift out the data on DOUT. The FSYNC duty cycle is

designed to be 50-50, where an FSYNC low-to-high transition takes place before the MSB of new data, and high-

to-low transition takes place before bit 15 on the falling edge of SCLK. For more information on FSYNC master-

mode timing, see the Frame-Sync Master Mode Timing Requirements.

8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode

DIN is not available in frame-sync master mode. Tie DIN to DGND.

8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode

The conversion data are clocked out on the falling edge of SCLK to be latched by the host processor on the

rising edge of SCLK. The MSB data become valid on DOUT after FSYNC goes high. The subsequent bits are

shifted out with each falling edge of SCLK.

8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode

DAISYIN and daisy-chain operation are not supported in frame-sync master mode. Tie DAISYIN to DGND.

8.5.2.2 Frame-Sync Slave Mode

When operating in frame-sync slave mode, the user must supply the framing signal FSYNC (similar to the

left/right clock on stereo audio ADCs) and the serial clock SCLK (similar to the bit clock on audio ADCs). The

data are output MSB first or left-justified on the rising edge of FSYNC. The FSYNC and SCLK inputs must be

continuously running with the relationships shown in the Frame-Sync Timing Requirements.

8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode

CS is not used in frame-sync programming. Tie CS to DGND.

8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode

In frame-sync slave mode, use SCLK to clock data out on DOUT. SCLK must run continuously; if SCLK is shut

down, the data read back is corrupted. The number of SCLKs within a frame period (t_c(FRAME)) can be any power-

of-two ratio of CLK cycles (1, 1/2, 1/4, and so on), as long as the number of cycles is sufficient to shift the data

output within one frame.

Use SCLK to also shift data into DAISYIN when multiple devices are configured for daisy-chain operation. Even

though SCLK has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally shifting the

data.

8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode

In frame-sync slave mode, the FSYNC pin is an input that transitions low to high at the data-rate frequency. The

required number of f_CLKcycles to each FSYNC period depends on the configuration of the FILTER[1:0] and

OSR[1:0] pins. If the FSYNC period is not the proper value, data read back is corrupted. For more information on

frame-sync slave-mode timing, see the Frame-Sync Slave Mode Timing Requirements.

8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode

DIN is not used in frame-sync slave mode. Tie the DIN pin to DGND.

8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode

The conversion data are clocked out on the falling edge of SCLK to be latched by the host processor on the

rising edge of SCLK. The MSB data become valid on DOUT after FSYNC goes high. The subsequent bits are

shifted out with each falling edge of SCLK.

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8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode

DAISYIN is an optional pin used along with SCLK to shift data from a secondary ADS127L01 device. Data are

shifted out from DOUT of a secondary device into the DAISYIN pin of the first device. The data on DOUT is

latched into DAISYIN on the SCLK falling edge. See the Multiple Device Configuration section for more

information on using daisy-chain mode. Tie the DAISYIN pin to DGND if not used.

8.5.3 Data Format

The ADS127L01 provides either a 24-bit or 32-bit output word, 24 bits of which are data in binary twos

complement format with an optional eight LSBs containing status word information. The size of one code (LSB) is

calculated using Equation 8:

1 LSB = (2 x V_REF) / 2²⁴= +FS / 2²³

(8)

A positive full-scale input [V_IN≥ (+FS – 1 LSB) = (V_REF– 1 LSB)] produces an output code of 7FFFFFh, and a

negative full-scale input (V_IN≤ –FS = –V_REF) produces an output code of 800000h. The output clips at these

codes for signals that exceed full-scale.

Table 20 summarizes the ideal output codes for different input signals.

Table 20. Ideal Output Code Versus Input Signal

INPUT SIGNAL, V_IN

(V_AINP– V_AINN

)

IDEAL OUTPUT CODE⁽¹⁾

≥ +FS (2²³– 1) / 2²³

7FFFFFh

000001h

0

+FS / 2²³

0

–FS / 2²³

≤ –FS

FFFFFFh

800000h

(1) Excludes the effects of noise, INL, offset, and gain errors.

8.5.4 Status Word

Trailing the 24 bits of data is an optional 8-bit status word. The status word provides a real-time update of

internal system monitors and data integrity. By default, the contents are a mixture of 4-bit CRC data integrity and

system monitors. Alternatively, the status word can be set to output an 8-bit CRC without the system monitors.

The CRCB bit in the CONFIG regsiter controls the status word contents. Set the CRCB bit to 0 for the status

word to contain 4-bit CRC [bits 7:4], one bit [bit 3] to monitor out of range input (INP), and three bits [bits 2:0] to

read back as 0. Set the CRCB bit to 1 for all eight bits [bits 7:0] of the status word to contain 8-bit CRC. See

Figure 94 for a visual representation of the two modes.

By default, the optional 8-bit status word is enabled, but can be disabled when operating in SPI interface mode

and setting the CS_ENB bit to 1 in the CONFIG register.

SCLK

DOUT

DATA

0

CRC - 4

INP

0

CRCB = 0

DOUT

CRC - 8

CRCB = 1

Figure 94. Status Word

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8.5.5 Cyclic Redundancy Check (CRC)

The ADS127L01 implements two standard CRC algorithms: CRC-4-ITU to provide a 4-bit CRC, and CRC-8-

CCITT for an 8-bit CRC. By default, the CRC-4-ITU option is enabled. Set the CRCB bit to 1 in the CONFIG

register to change the format to CRC-8-CCITT and remove the system monitor bits from the status word.

The CRC is placed after the ADC data. The CRC is calculated using only the ADC output. When the 4-bit CRC is

enabled, the ADS127L01 outputs a 4-bit status block after the CRC that is not used as part of the CRC check.

8.5.5.1 Computing the CRC

To calculate the CRC, divide the data bytes by the CRC polynomial using an XOR operation.

In 4-bit CRC mode, the CRC value is the 4-bit remainder of the division of the data bytes by a CRC polynomial of

P(x) = x⁴+ x + 1.

In 8-bit CRC mode, the CRC value is the 8-bit remainder of the division of the ADC data bytes by a CRC

polynomial of P(x) = x⁸+ x²+ x + 1.

Then compare the calculated CRC values to the provided CRC value in the ADC output.

If the values do not match, a data-transmission error has occurred. In the event of a data-transmission error,

read the data again. The CRC provides a higher level of detection of multiple-bit errors.

The following list shows a general procedure to compute the CRC value. Assume the shift register is n bits wide,

where n is the number of CRC bits:

1. Set the polynomial value to 0x3 for an 4-bit CRC, or 0x07 for an 8-bit CRC .

2. Set the shift register to all zeros.

3. Begin with the MSB in the data stream. For every n bits:

(a) Align the MSB of the data stream with the MSB of the shift register. XOR the data with the shift register, and place

the result in the shift register.

(b) Test the MSB of the shift register n times, and do one of the following each time:

(a) If the most significant bit of the shift register is set, shift the register left by one bit, XOR the result with the

polynomial, and place the result into the shift register.

(b) If the most significant bit of the shift register is not set, shift the register left by one bit.

4. The result in the shift register is the CRC check value.

NOTE

The CRC algorithm used here employs an assumed set high bit. This bit is divided out by

left-shifting the bit out of the register prior to XORing with the polynomial shift register.

This process allows for calculation of the CRC with 8-bit hardware.

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8.6 Register Maps

Table 21 describes the various ADS127L01 registers. Access to the registers is available in SPI interface mode.

Register access is not available in frame-sync master or slave interface modes.

Table 21. ADS127L01 Register Assignments

RESET

VALUE

ADDRESS

Device ID (Read-Only Registers)

00h ID

Configuration Settings

REGISTER

(Hex)

BIT 7

BIT 6

BIT 5

REV_ID[4:0]

FSC

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

x3h⁽¹⁾

DEV_ID[2:0]

CS_ENB

01h

02h

03h

04h

05h

06h

CONFIG

00h

80h

0

OFC

TOUT_DEL

SPI_TOUT

CRCB

OFC0

OFC1

OFC2

FSC0

FSC1

OFC_B[7:0]

OFC_B[15:8]

OFC_B[23:16]

FSC_B[7:0]

FSC_B[15:8]

Device Settings (Read-Only Registers)

07h MODE

xx⁽¹⁾

0

HR

OSR[1:0]

FILTER[1:0]

FORMAT

FSMODE

(1) x is undefined.

8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]

This register is programmed during device manufacture to indicate device characteristics.

Figure 95. ID Register

7

6

5

4

3

2

1

0

REV_ID[4:0]

R-Undefined⁽¹⁾

DEV_ID[2:0]

R-3h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) Reset values are device dependent.

Table 22. ID Register Field Descriptions

Bit

Field

Type

Reset

Description

Revision ID.

7:3

REV_ID[4:0]

R

xh⁽¹⁾

These bits indicate the revision of the device and are subject to

change without notice.

Device Family Identification.

011 = ADS127L01

2:0

DEV_ID[2:0]

R

3h

(1) Reset values are device dependent.

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8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]

This register contains the software controlled device options.

Figure 96. CONFIG Register

7

0

6

0

5

4

3

2

1

0

FSC

OFC

TOUT_DEL

R/W-0h

SPI_TOUT

R/W-0h

CS_ENB

R/W-0h

CRCB

R/W-0h

R-0h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. CONFIG Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

Always write 0

7:6

Reserved

R

0h

System Gain Correction

This bit enables system gain correction using the register

contents from FSC0 and FSC1 registers.

0 = Disable system gain correction

5

4

FSC

OFC

R/W

0h

1 = Enable system gain correction

Offset Correction

This bit enables Offset Correction using the register contents

from OFC0, OFC1, and OFC2 registers.

0 = Disable offset correction

1 = Enable offset correction

SPI Timeout

This bit sets the time limit to hold SCLK in an idle position for the

SPI reset.

3

2

1

0

TOUT_DEL

SPI_TOUT

CS_ENB

CRCB

R/W

0h

0 = SPI timeout delay set to 2¹⁶t_CLK

1 = SPI timeout delay set to 2¹⁴t_CLK

.

SPI Timeout Enable

This bit enables or disables the SPI timeout function.

0 = Disable SPI timeout

1 = Enable SPI timeout

Status Word Enable

This bit enables or disables the status word that is present

following the 24-bit data output.

0 = Enable status word

1 = Disable status word

Status Word Contents

This bit sets the contents used in the status word.

0 = CRC-4 and 4 bits of ADC diagnostics

1 = CRC-8

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8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]

This register contains the least significant byte for the system offset calibration. The system offset calibration is a

total of three bytes or 24 bits.

Figure 97. OFC0 Register

7

6

5

4

3

2

1

0

OFC_B[7:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. OFC0 Register Field Descriptions

Bit

Field

Type

Reset

Description

Offset Correction Bits

These bits set the system offset error correction.

7:0

OFC_B[7:0]

R/W

00h

8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]

This register contains the middle byte for the system offset calibration. The system offset calibration is a total of

three bytes or 24 bits.

Figure 98. OFC1 Register

7

6

5

4

3

2

1

0

OFC_B[15:8]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. OFC1 Register Field Descriptions

Bit

Field

Type

Reset

Description

Offset Correction Bits

These bits set the system offset error correction.

7:0

OFC_B[15:8]

R/W

00h

8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]

This register contains the most significant byte for the system offset calibration. The system offset calibration is a

total of three bytes or 24 bits.

Figure 99. OFC2 Register

7

6

5

4

3

2

1

0

OFC_B[23:16]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. OFC2 Register Field Descriptions

Bit

Field

Type

Reset

Description

Offset Correction Bits

These bits set the system offset error correction.

7:0

OFC_B[23:16]

R/W

00h

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8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]

This register contains the least significant byte for the system gain calibration. The system gain calibration is a

total of two bytes or 16 bits.

Figure 100. FSC0 Register

7

6

5

4

3

2

1

0

FSC_B[7:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. FSC0 Register Field Descriptions

Bit

Field

Type

Reset

Description

Gain Correction Bits

These bits set the system gain calibration value.

7:0

FSC_B[7:0]

R/W

00h

8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]

This register contains the most significant byte for the system gain calibration. The system gain calibration is a

total of two bytes or 16 bits.

Figure 101. FSC1 Register

7

6

5

4

3

2

1

0

FSC_B[15:8]

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. FSC1 Register Field Descriptions

Bit

Field

Type

Reset

Description

Gain Correction Bits

These bits set the system gain calibration value.

7:0

FSC_B[15:8]

R/W

80h

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8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]

This register displays the hardware bit settings.

Figure 102. MODE Register

7

0

6

5

4

3

2

1

0

HR

OSR[1:0]

FILTER[1:0]

FORMAT

R-xh

FSMODE

R-xh

R-0h

R-xh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

Always reads 0

7

RESERVED

R

0h

High-Resolution Setting

This bit shows the readback status of HR (pin 29)

0 = LP Mode

1 = HR mode

6

HR

R

xh

OSR Setting

This bit shows the readback status of OSR1 (pin 15) and OSR2

(pin 16)

If FILTER[1:0] = 00 or 01 (Wideband filters):

00 = 32

01 = 64

5:4

OSR[1:0]

R

xh

10 = 128

11 = 256

If FILTER[1:0] = 10 (Low-latency filter):

00 = 32

01 = 128

10 = 512

11 = 2048

Filter Option Setting

This bit shows the readback status of FILTER1 (pin 12) and

FILTER0 (pin 13)

Digital-filter mode select:

00 = Wideband 1 filter

3:2

FILTER[1:0]

R

xh

01 = Wideband 2 filter

10 = Low-latency filter (SINC5 and SINC)

11 = Reserved

Interface Mode Setting

This bit shows the readback status of FORMAT (pin 30)

0 = SPI interface mode

1 = Frame-sync interface mode

1

0

FORMAT

FSMODE

R

xh

Frame-sync mode setting

This bit shows the readback status of FSMODE (pin 14)

0 = Frame-sync slave interface mode

1 = Frame-sync master interface mode

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Unused Inputs and Outputs

Do not float unused digital inputs because excessive power-supply leakage current might result.

The DIN and CS pins are only used in SPI interface mode. Tie DIN (pin 21) and CS (pin 23) directly to DGND

when in frame-sync master mode or frame-sync slave mode.

If not daisy-chaining devices, tie DAISYIN directly to DGND.

In SPI interface mode, leave the unused DRDY/FSYNC pin floating, or tie the unused pin to DVDD through high

impedance resistors.

9.1.2 Multiple Device Configuration

The ADS127L01 provides configuration flexibility when multiple devices are connected in a system:

•

SPI interface mode supports two methods to synchronize multiple devices: cascaded or daisy-chain.

Frame-sync slave interface mode also supports the same two methods to synchronize multiple devices:

cascaded or daisy-chain.

•

Frame-sync master interface mode only supports the cascaded method to synchronize multiple devices.

Daisy-chain configuration is not available in frame-sync master mode.

9.1.2.1 Cascaded Configuration

Two or more ADS127L01 devices can be cascaded together when using either SPI interface mode or Frame-

Sync interface mode. Cascading devices allows multiple devices to share the same interface bus and reduces

pin connections to the host processor.

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Application Information (continued)

9.1.2.1.1 SPI interface Mode

In SPI interface mode, CLK, SCLK, DIN, and DOUT from each device are shared with independent CS signals.

Monitor the DRDY signal from only one device. Leave the remaining DRDY pins floating. Figure 103 shows the

required connections for cascading multiple devices in SPI interface mode.

CLK

CS

SCLK

DIN

GPIO1

SCLK

MOSI

MISO

INT

START

ADS127L01

(Device 0)

DOUT

HOST

PROCESSOR

DRDY/FSYNC

DAISYIN

GPIO2

CLK

CS

START

SCLK

DIN

ADS127L01

(Device 1)

DOUT

DRDY/FSYNC

DAISYIN

Figure 103. Cascaded Devices in SPI Interface Mode

The host processor must use a separate GPIO to control the CS pins on each ADS127L01 device. When CS is

driven to a logic 1, the DOUT of that device is high-impedance. This structure allows another device to take

control of the DOUT bus. The SCLK frequency must be high enough to read all of the data from each device

before the next DRDY pulse arrives. Alternatively, tie the DOUT pin from each device to a separate pin on the

host processor to collect data from multiple devices in parallel.

Equation 9 calculates the maximum number of devices that can share the same bus in a cascaded configuration

in terms of data rate, SCLK frequency, and total number of bits per device.

Number of Devices ≤ (t_DATA– t_CSDO– t_CSDOZ) / (n × t_SCLK

)

where

•

n = 24 or 32 bits

(9)

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Application Information (continued)

9.1.2.1.2 Frame-Sync interface Mode

In frame-sync interface mode, the CS pin is unused and must be tied to DGND. CLK, SCLK, DIN, and FSYNC

from each device are shared with independent DOUT signals. Connect the DOUT pin from each device to a

separate input pin on the host processor to read the data from multiple devices in parallel. Figure 104 shows the

required connections for cascading multiple devices in frame-sync interface mode.

CLK

CS

SCLK

DIN

SCLK

MOSI

MISO1

INT

START

ADS127L01

(Device 0)

DOUT

HOST

PROCESSOR

DRDY/FSYNC

DAISYIN

MISO2

CLK

CS

START

SCLK

DIN

ADS127L01

(Device 1)

DOUT

DRDY/FSYNC

DAISYIN

Figure 104. Cascaded Devices in Frame-Sync Mode

Only one device can be configured in frame-sync master mode; remaining devices must be configured in frame-

sync slave mode. Otherwise, configure all devices in frame-sync slave mode.

Equation 10 calculates the maximum number of devices that can be daisy-chained for SPI and frame-sync slave

mode in terms of data rate, SCLK frequency, and total number of bits to read from each device.

Number of Devices ≤ (t_DATA) / (n × t_SCLK

)

where

•

n = 24 or 32 bits

(10)

9.1.2.2 Daisy-Chain Configuration

Two or more ADS127L01 devices can be daisy-chained together in either SPI interface mode or frame-sync

slave mode. Frame-sync master mode does not support daisy-chain configurations. For both SPI and frame-sync

slave mode, connect the DOUT pin of the first device in the chain to an input pin on the host processor. Connect

the DOUT pin of the remaining devices to the DAISYIN pin of the next device. Connect the DAISYIN pin on the

last device to DGND.

Equation 11 calculates the maximum number of devices that can share the same bus in a cascaded

configuration in terms of data rate, SCLK frequency, and total number of bits per device.

Number of Devices ≤ (t_DATA) / (n × t_SCLK

)

where

•

n = 32 bits

(11)

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Application Information (continued)

9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode

In SPI interface mode, CLK, SCLK, DIN and CS are shared. Monitor only the DRDY signal from one device.

Leave the remaining DRDY pins floating. The SCLK frequency must be high enough to read all the data from

each device before the next DRDY pulse arrives. Figure 105 shows the required connections for daisy-chaining

multiple devices in SPI interface mode.

CLK

CS

SCLK

DIN

GPIO

SCLK

MOSI

MISO

INT

START

ADS127L01

(Device 0)

DOUT

HOST

PROCESSOR

DRDY/FSYNC

DAISYIN

CLK

CS

START

SCLK

DIN

ADS127L01

(Device 1)

DOUT

DRDY/FSYNC

DAISYIN

Figure 105. Daisy-Chained Devices in SPI Mode

All data from Device 0 is shifted into Device 1 on the DAISYIN pin. The MSB from the Device 0 data immediately

follows the LSB from Device 1 on the DOUT pin of Device 0. Figure 106 illustrates the timing relationship for

daisy-chaining devices in SPI interface mode.

Device 1

MSB

Device 1

LSB

DAISYIN

SCLK

Device 0

MSB

Device 0

LSB

Device 1

MSB

Device 1

LSB

MISO

Figure 106. Daisy-Chain Timing in SPI interface Mode

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Application Information (continued)

9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode

In frame-sync slave mode, CLK, SCLK, DIN and FSYNC are shared. The CS pin is unused and must be tied to

DGND. The SCLK frequency must be high enough to read all the data from each device before the next frame

begins. Figure 107 shows the required connections for daisy-chaining multiple devices in frame-sync slave mode.

CLK

CS

SCLK

DIN

SCLK

MOSI

MISO

INT

START

ADS127L01

(Device 0)

DOUT

HOST

PROCESSOR

DRDY/FSYNC

DAISYIN

CLK

CS

START

SCLK

DIN

ADS127L01

(Device 1)

DOUT

DRDY/FSYNC

DAISYIN

Figure 107. Daisy-Chained Devices in Frame-Sync Slave Mode

All data from Device 1 are shifted into Device 0 on the DAISYIN pin. The MSB from the Device 1 data

immediately follows the LSB from Device 0 on the DOUT pin of Device 1. Figure 108 illustrates the timing

relationship for daisy-chaining devices in frame-sync slave mode.

Device 1

MSB

Device 1

LSB

DAISYIN

SCLK

Device 0

MSB

Device 0

LSB

Device 1

MSB

Device 1

LSB

MISO

Figure 108. Daisy-Chain Timing in Frame-Sync Slave Mode

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Application Information (continued)

9.1.2.3 Synchronizing Devices

Use the START pin or the RESET/PWDN pin to synchronize multiple devices. The START pin does not reset the

device registers to the default settings. The RESET/PWDN pin resets the device to the factory default settings,

and resets the interface when in frame-sync master mode. The delay from the START signal high to the first data

ready is fixed for a given data rate (see the Start Pin (START) section for more details on the delay times).

An alternate way to synchronize multiple devices is using the RESET/PWDN pin. The RESET/PWDN pin resets

the digital interface in addition to the digital filters and registers, making it the recommended synchronization

method for frame-sync master mode. The delay from the RESET/PWDN pin high to the first data ready is fixed

for a given data rate (see the Reset and Power-Down Pin (RESET/PWDN) section for more details on the delay

times). The RESET/PWDN pin is also used to synchronize multiple devices in SPI interface mode or frame-sync

slave mode.

When synchronizing multiple devices, the master clock, f_clk, must be shared from the same signal source.

9.1.3 ADC Input Driver

The input driver circuit for a high-precision delta-sigma ADC consists of two parts: a driving amplifier and a low-

pass, antialiasing filter. The amplifier is used to condition the input signal voltage and provide a low output-

impedance buffer between the signal source and the switched-capacitor inputs of the ADC. The low-pass

antialiasing filter, comprised of series resistors and a differential capacitor, helps to attenuate the voltage

transients created by the ADC switched-capacitor input stage, and also serves to band-limit the wideband noise

contributed by the front-end circuit. Careful design of the input driver circuit is critical to take advantage of the

linearity and noise performance of the ADS127L01.

9.1.3.1 Antialiasing Filter

Signal aliasing in data-acquisition systems occurs when continuous-time signals are discretely sampled at a

constant rate. To properly represent an analog signal in the digital domain, the system must sample the input at

a sampling rate greater than twice the maximum frequency content, known as the Nyquist rate. Frequencies that

are greater than one-half the sampling rate are not represented properly in the digital domain and appear as

aliases of the original input instead.

Delta-sigma ADCs exhibit two Nyquist frequencies, as shown in Figure 109. The first Nyquist frequency occurs in

the analog domain at one-half the modulator sampling rate (f_MOD/ 2). The second Nyquist frequency occurs in

the digital domain at one-half the decimated output data rate (f_DATA/ 2). Frequency content repeats at multiples

of f_MODand f_DATA. Both Nyquist frequencies allow for out-of-band signals to alias into the ADC pass band,

including noise from the front-end driver circuit. This aliasing increases the in-band noise level of the system and

degrades overall performance if not adequately filtered.

ADC INPUT

ûꢀ MODULATOR

DIGITAL FILTER

DECIMATION

H(z)

+

Analog Domain

Aliasing

Digital Domain

Aliasing

Figure 109. Delta-Sigma ADC Internal Signal Chain

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Application Information (continued)

Figure 110 and Figure 111 illustrate the two aliasing domains in delta-sigma ADCs. Figure 110 shows a higher-

frequency, out-of-band signal aliasing around the modulator Nyquist frequency (f_MOD/ 2) into the pass band.

Figure 111 shows a lower-frequency, out-of-band signal aliasing around the data rate Nyquist frequency (f_DATA

2) into the pass band after being attenuated by the digital filter.

/

Digital Domain

Aliasing

Analog Domain

Aliasing

f_DATA/2 f_DATA

f_MOD/2

f_MOD

DC

f_MOD/2

f_MOD

DC

Frequency (Hz)

Figure 111. Digital Domain Aliasing Around f_DATA/ 2

Figure 110. Analog Domain Aliasing Around f_MOD/ 2

To prevent signals from aliasing, use a low-pass antialiasing filter to attenuate the out-of-band signals. The

simplest antialiasing filter is a discrete first-order, low-pass, RC filter. To achieve a higher level of attenuation at

the Nyquist frequency requires a higher-order filter response, usually before the last amplifier stage.

The digital filter in delta-sigma ADCs reduces the attenuation requirement of the antialiasing filter by providing a

high stop-band attenuation between f_DATA/ 2 and f_MOD. At multiples of f_MOD, the digital filter response returns to 0

dB and repeats. This portion of the digital filter response is the sensitive frequency band where an antialiasing

filter is needed. Figure 112 overlays a digital filter response with first-, second-, and third-order antialiasing filters,

attenuating both out-of-band signals.

First-Order Antialiasing Filter

Second-Order Antialiasing Filter

Third-Order Antialiasing Filter

Digital Filter

DC f_DATA/2 f_DATA

f_MOD/2

f_MOD

Frequency (Hz)

Figure 112. Antialiasing and Digital Filters

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Application Information (continued)

The antialiasing RC filter also helps to attenuate the voltage transients from the sampling network at the ADC

inputs. Figure 113 shows a simplified switch-capacitor circuit at the inputs of an ADC modulator. The sampling

network, described in Figure 60, places a transient load on the external drive circuit. The differential capacitor in

the RC filter, C_DIFF, acts as a charge reservoir and transfers charge to the internal sampling capacitor, C_SAMPLE

,

while S1 is closed. The input driver circuit must restore the charge at the input nodes (AINP and AINN) so that

the voltage settles before S1 opens. After S1 opens, S2 closes, discharging the C_SAMPLEcapacitor. The faster the

modulator sampling rate, the less time the input voltage has to settle. An amplifier with a gain-bandwidth product

(GBP) that is too low fails to provide adequate settling because of the higher output impedance over frequency,

and results in increased distortion.

S1

R_FLT

AINP

+

œ

C_SAMPLE

C_DIFF

S2

+

œ

AINN

R_FLT

S1

Figure 113. Delta-Sigma Modulator Sampling Network

The sampling capacitors of the ADS127L01 have an equivalent capacitance of 8 pF. Scale C_DIFFto be at least

100 times larger than C_SAMPLE. Connect C_DIFFdirectly across the ADC input pins to help provide adequate charge

with each ADC sample. C_DIFFmust be C0G or NP0 dielectric type because these components have a high-Q,

low-temperature coefficient, and stable electrical characteristics to withstand varying voltages and frequencies.

Common-mode capacitors, C_CM, can also be added at each input to ground to attenuate common-mode noise

and sampling glitches. Size the common-mode capacitors to be one order of magnitude smaller than C_DIFFin

order to maintain system common-mode rejection (CMR).

Figure 114 shows an example of the voltage transient created by the ADC sampling event at the inputs of an

unbuffered delta-sigma ADC. The larger transients mark the moment when S1 closes to connect C_SAMPLEto the

external front-end circuitry. The smaller transient occurs when the S1 switch opens passing the charge through

the modulator. The sequence repeats at 1 / f_MOD. The data were recorded using a passive 10x probe on the

AINP pin only. The same transient is observed on AINN as well. The differential transient voltage is more than an

order of magnitude smaller.

160

140

120

100

80

9

AINP (mV)

CLK (V)

7.5

6

4.5

3

60

1.5

0

40

20

-1.5

-3

0

-20

-40

-60

-80

-4.5

-6

-7.5

-9

Time

D001

Figure 114. ADC Input During Sampling

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Application Information (continued)

When S1 opens, the input signal is sampled and converted by the modulator. Increasing C_DIFFprovides a larger

charge reservoir to the ADC, and reduces the initial voltage droop. For ADCs with a faster sampling frequency,

there is less time for this voltage transient to fully settle before the next sample. The ADC input relies on a driver

amplifier with sufficient bandwidth and low output impedance at high frequencies to provide recovery charge and

fully settle the voltage transient before S1 opens.

9.1.3.2 Input Driver Selection

Selection criteria for the input amplifiers are highly dependent on the input signal type, as well as the

performance goals of the data-acquisition system. Consider the following amplifier specifications when selecting

the appropriate driver amplifier for the application:

•

Noise. The output noise density of the front-end amplifiers must be kept as low as possible to prevent any

degradation in system SNR performance. The total noise from the input stage is determined by the –3-dB

bandwidth of the ADS127L01 digital filter. Make sure that the total output noise is less than 20% of the input-

referred noise of the ADC, as explained in Equation 12:

SNR(dB)

≈

’

-

∆

«

÷

◊

V_REF

2

1

5

20

e_{o _RMS}ì f_-3dB

Ç

ì

ì10

where

•

e_{o_RMS}= Broadband output noise of the input driver stage in nV/√Hz

f_-3dB= –3-dB bandwidth of the ADS127L01 digital filter in Hz

(12)

Distortion. Keep the distortion from the front-end drivers as low as possible, especially in the presence of a

switching load. Harmonics produced by the amplifier are also compounded by harmonics produced by the

ADC. Minimize the amplifier distortion by using the widest allowable supply voltage and highest output load

resistance for the application. Select an amplifier with high open-loop gain and at least –10 dB better

distortion than the ADC distortion in order to prevent any degradation to system THD performance, as

explained by Equation 13.

THD_AMP£ THD_ADC-10 dB

where

•

THD_AMP= Total harmonic distortion from input driver

THD_ADC= Total harmonic distortion specification of the ADC

(13)

Small-signal bandwidth. Select the small-signal bandwidth of the input amplifiers to be as high as possible,

after meeting the power budget of the system. Higher bandwidth reduces the closed-loop output impedance

of the amplifier, thus allowing the amplifier to more easily drive a larger capacitive load with a smaller series

resistor. For a given low-pass filter cutoff, keep the series resistor as small as possible and increase the

differential capacitor to minimize gain error and distortion (see the Antialiasing Filter section). Higher

bandwidth also minimizes harmonic distortion caused by faster settling of the input transients from the ADC

sampling. The required amplifier bandwidth depends on the size of the sampling capacitor, the sampling

frequency, and the size of the external differential capacitor. TINA-TI simulations help model the small-signal

settling behavior and the stability of the input driver circuit for a given load.

The THS45xx family of fully-differential amplifiers offers the low noise and distortion specifications needed in

high-performance data-acquisition systems. Table 30 shows the power versus performance tradeoff offered

between the THS4531A, THS4551, and the highest performing THS4541.

Table 30. Input Driver Selection

GAIN BANDWIDTH

PRODUCT (MHz)

NOISE DENSITY

QUIESCENT CURRENT

Iq (mA)

NOMINAL R_FAND R_G

DRIVER

THS4531A

THS4551

THS4541

(nV/√Hz)

(Ω)

36

10

3.4

2.2

0.23

1.31

9.7

2 k

1.2 k

402

135

850

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Figure 115 and Figure 116 compare the distortion and noise performance of the THS4531A, THS4541, and

THS4551 as they drive the inputs of the ADS127L01. Each input driver circuit was configured for a gain of one

using the nominal feedback resistor values in Table 30. An AP2700 function generator provided a full-scale, sine

wave input at frequencies of 2 kHz and below, such that at least five harmonics were present in the fast Fourier

transform (FFT) calculated from 8,192 samples. An Agilent 33522A provided the clock input for the ADS127L01

(CLK) to set the modulator clock frequency between 100 kHz and 16.384 MHz.

To quantify the distortion performance of each input driver circuit, the spurious-free dynamic range (SFDR) is

calculated at each modulator clock frequency. A third-order polynomial, best-fit curve is applied to the raw data to

show the overall trend for each amplifier.

Figure 115 illustrates that at slower modulator clock frequencies, a lower power amplifier with less bandwidth can

be used to achieve similar SFDR performance as higher power amplifiers with more bandwidth. However, faster

modulator clock frequencies require the use of a wide-bandwidth amplifier to get the best performance out of the

ADC.

-80

Amplifier

THS4541

THS4551

-90

-100

-110

-120

-130

-140

THS4531A

0

2

4

6

8

10

12

14

16

18

f_MOD(MHz)

D015

Figure 115. SFDR vs f_MOD

In contrast to SFDR, the signal-to-noise ratio (SNR) of a data-acquisition signal chain is more dependent on the

input amplifier noise density, as well as the ADC output data rate. Figure 116 displays the SNR performance of

the ADS127L01 measured while driving the inputs with the THS4531A, THS4541, and THS4551. The digital filter

in the ADS127L01 is configured to use the Wideband 2 transition band and an OSR of 256 throughout the SNR

measurements. An AP2700 provided a small-signal 1 kHz input sine wave of 100 mVpp. An Agilent 33522A

provided the clock input (CLK) for the ADS127L01 to set the modulator clock frequency between 100 kHz and

16.384 MHz. The measured SNR is normalized to full-scale.

120

Amplifier

THS4541

THS4551

THS4531A

115

110

105

0

2

4

6

8

10

12

14

16

18

f_MOD(MHz)

D014

Figure 116. SNR vs f_MOD

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The SNR performance is expected to remain relatively constant for all three amplifiers across modulator

frequencies. However, the improvement in SNR at slower modulator frequencies is because of the reduced

bandwidth of the digital filter as it scales down with modulator clock, limiting the input source broadband noise. At

higher frequencies, noise from the input source dominates as the digital-filter bandwidth increases. The

difference in amplifier noise density, listed in Table 30, has the largest effect on the system noise performance.

9.1.3.3 Amplifier Stability

Driving a capacitive load can degrade the phase margin of the input amplifier, and can make the amplifier

unstable. To prevent the amplifier from becoming unstable, a series isolation resistor (R_FLT) is used at the

amplifier output, as shown in Figure 113. A higher resistance value increases phase margin and makes the

amplifier more stable, but also increases distortion caused by the interaction with the nonlinear input impedance

of the ADC modulator. Distortion increases with source output impedance, input-signal frequency, and input-

signal amplitude.

The selection of R_FLTrequires a balance between distortion and the stability of the input driver design. The use of

1% components is allowed because the C_DIFFmitigates the degradation of CMR caused by input imbalances.

The input amplifier must be selected with a bandwidth higher than the cutoff frequency, f_C, of the antialiasing filter

at the ADC inputs. Use a TINA-TI simulation to confirm that the amplifier has more than 30° of phase margin

when driving the selected filter to verify stability. Simulation is critical because some amplifiers require more

bandwidth than others to drive the same filter. If the input amplifier circuit has less than 20° of phase margin,

consider adding a capacitor at the amplifier inputs to increase phase margin.

9.1.4 Modulator Saturation

The ADS127L01 features a third-order modulator and a 5-bit quantizer in order to achieve excellent SNR

performance, resolution, and linearity. However, as with all high-order, delta-sigma modulators, certain input

conditions may saturate the modulator and increase the quantization noise. These conditions include input

signals that are less than full-scale and contain frequency content that falls within the stop band of the digital

filter. Most notably, a saturated modulator increases the ADC in-band noise floor and degrades SNR

performance.

To prevent the ADS127L01 from reaching a saturated condition, use an antialiasing filter at the inputs to

attenuate out-of-band signals. Table 31 shows the differential input amplitude limits at frequencies from 100 kHz

to 15 MHz for discrete modulator rates in order to prevent saturation. In general, a multiple-order, low-pass

response with a –3-dB cutoff placed one decade beyond the pass band is sufficient for most applications.

Table 31. Differential Input Amplitude Limits (dBFS)

f_MOD

f_IN(MHz)

4.096 MHz

8.192 MHz

12 MHz

—

16.384 MHz

0.1

0.2

1

0

—

0

—

0

—

–3

–2

2

–7

–6.5

–18

–19

–20

–3

–2.5

–18

–19

–20

8

–18

–19

–20

–18

–19

–20

10

15

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9.1.5 ADC Reference Driver

Design the reference driver to provide a precision, low-drift reference voltage to the ADC for best performance.

Similar to the input of the ADC, a switched-capacitor circuit samples the reference voltage between REFP and

REFN. The switched capacitor imposes a transient load on the external reference driver circuit at the modulator

frequency. A reference buffer is required to restore the charge across the differential capacitor at the reference

input pins so that the voltage settles before the next acquisition. The integrated broadband reference noise must

remain significantly less than the ADC integrated noise to minimize SNR degradation. Choose a reference driver

with relatively low noise density. Reference noise can be heavily filtered with a low-pass filter.

Below are two options for driving the reference input of the ADS127L01. Option 1 presents a single-chip solution

with an integrated buffer. Option 2 presents a multichip solution with a precision reference and an external buffer.

9.1.5.1 Single Chip Solution: REF6xxx

The REF6xxx is a family of very high-precision, low-noise, and low-drift voltage references. This single-chip

solution has an integrated high-bandwidth buffer that presents a low output impedance to the ADC reference

input. The REF6025 outputs a fixed 2.5-V output voltage; however, other devices from the same family are

available to offer various output voltages and temperature drift specifications

The ADS127L01 has the ability to maintain a high level of performance at relatively low levels of power

consumption. The REF6025 only adds 750 μA of typical quiescent current to the system power budget, while still

showcasing the performance of the ADS127L01 when sampling at full-speed, making it a great fit for low-power

applications with limited board space.

Figure 117 shows typical connections for the REF6025 as a reference driver circuit to the ADS127L01. The

output of the REF6025 uses a Kelvin connection to correct for the voltage drop between the voltage output pins

and the pads of the output capacitor. A small series resistance is required to keep the reference output stable.

See the REF60xx device datasheet (SBOS708) for more details on the required connections and component

values.

REF6025

VIN

EN

SS

GND_S

GND_F

ADS127L01

REFP REFN

47 mꢁ

47 ꢀF

+

10 ꢀF

VOUT_F

V_SUPPLY

œ

121 kꢁ

FLT VOUT_S

0.1 ꢀF

1 ꢀF

Figure 117. REF6025 Connection to ADS127L01

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9.1.5.2 Multichip Solution: REF50xx + OPA320

The REF50xx is another family of low-noise, low-drift, high-precision voltage references. The REF5025 outputs a

fixed 2.5-V output voltage; however, other devices from the same family are available to offer various output

voltages. Buffer the output of the REF5025 with a low-noise, wide bandwidth amplifier such as the OPA320 to

achieve the best performance with the ADS127L01.

The OPA320 is a precision, low-voltage CMOS operational amplifier optimized for low noise and wide bandwidth

with a typical quiescent current of 1.5 mA. From 0.1 Hz to 10 Hz, the OPA320 features an output noise of 2.8

µV_PP. With a unity gain-bandwidth product of 20 MHz, the OPA320 is able to drive the ADS127L01 reference

inputs while sampling at full-speed without degrading linear performance of the system.

Figure 118 shows an example reference circuit using the REF5025 and the OPA320. The output of the REF5025

is low-pass filtered to less than 2 Hz before the input of the OPA320. The OPA320 is placed in a noninverting

buffer configuration with dual-feedback to compensate for the large capacitive output load and maintain stability.

See the respective device data sheets for more details on the required connections and component values.

1 kꢁ

ADS127L01

2.2 ꢀF

REFP

REFN

REF5025

VIN VOUT

œ

220 mꢁ

0.1 ꢀF

10 kꢁ

+

47 ꢀF

OPA320

10 ꢀF

+

TEMP TRIM

GND

V_SUPPLY

220 mꢁ

10 ꢀF

œ

1 ꢀF

22 ꢀF

Figure 118. REF5025 + OPA320 Connection to ADS127L01

Table 32 compares the performance characteristics of the two reference driver solutions discussed in this

section.

Table 32. Reference Selection

TEMPERATURE

DRIFT TYP (μV/°C)

TEMPERATURE

DRIFT MAX (μV/°C)

TEMPERATURE

RANGE (°C)

(1)

DEVICE

I_Q(μA)

NOISE (μV_PP)

REF5025 + OPA320

REF6025

2300

750

8.0

7.5

22.9

12.5

20

9.04

20.53

-40°C to +125°C

REF6125

750

10.0

(1) Total noise for 230 kHz ADC bandwidth simulated from TINA-TI.

The two reference solutions are capable of driving the ADS127L01 to meet datasheet specifications. While the

multichip solution has a larger PCB footprint, the multichip solution offers similar noise performance, and allows

more customization than the REF6x25, including the ability to low-pass filter the broadband noise of the

REF5025. This multichip solution may provide a lower-cost alternative to the REF6x25 for applications that can

tolerate a higher component count and power consumption. The REF6x25 has a smaller PCB footprint, and

offers tighter drift specifications at a fraction of the power.

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9.1.6 Driving LVDD With an External Supply

A portion of the ADC modulator in the ADS127L01 is powered from a separate low-voltage analog supply

(LVDD) to achieve lower overall power consumption. This supply is nominally 1.8 V and can be sourced by either

an internal LDO (INTLDO = 0) or an external supply (INTLDO = 1). When the internal LDO supply is used, the

LVDD current is sourced from AVDD.

While LDOs are known to be smaller and less noisy than other power supply topologies, LDOs are much less

efficient and can consume large amounts of power. An LDO dissipates excess power as heat in order to regulate

the output voltage. The higher the dropout voltage is between the supply input and the LDO output, the more

power is wasted.

Alternatively, an external switching power supply can drive LVDD. Switching power supplies are much more

efficient and consume less power; however, a small switching ripple could appear on the output. The frequency

content from this ripple can appear in the ADC output if:

•

The switching frequency falls directly in the ADC pass band.

The switching frequency aliases into the ADC pass band from an out-of-band frequency.

Consider carefully when choosing the switching frequency (f_SW) in order to maintain the highest system power-

supply rejection (PSR). The LVDD supply pin offers at least 75 dB of PSR at 60 Hz. Choose an out-of-band

switching frequency that falls within the stop band of the wideband FIR filter, or within the notches of the low-

latency sinc filter, as shown in Figure 119 and Figure 120, respectively. If possible, an ideal design synchronizes

the switching supply frequency to a 1/2ⁿratio of the modulator clock frequency. Any remaining frequency content

that is not suppressed by the LVDD PSR will fall into the nulls of the digital filter or fold back to dc.

f_SW

n • f_MOD

(2n + 1) • f_MOD/ 2

(n + 1) • f_MOD

n • f_MOD

(2n + 1) • f_MOD/ 2

(n + 1) • f_MOD

Frequency (Hz)

Figure 120. Suggested f_SWfor Low-Latency Filter

Figure 119. Suggested f_SWfor Wideband Filters

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9.2 Typical Application

Test and measurement applications interface sensor inputs with a precision data-acquisition signal chain. This

signal chain must be capable of measuring a wide frequency range with very low noise and minimal harmonic

distortion. Figure 121 illustrates the main components of a sensor signal chain, consisting of a conditioning stage

at the sensor output, followed by a high-speed, low-noise amplifier driving a wide-bandwidth, delta-sigma ADC.

+

œ

+

œ

ADS127L01

+

œ

Sensor Output

Signal Conditioning

Differential Driver and ADC

Figure 121. Test and Measurement Block Diagram

In data-acquisition systems, signal distortion can come from the amplifier, the settling of the switched-capacitor

load transients, and the ADC. Choose both the differential drive amplifier and the ADC such that neither one

limits the distortion performance of the signal chain. This section details the design procedure for the fully-

differential input stage to an ADC optimized for low noise and minimal harmonic distortion.

9.2.1 Design Requirements

Table 33. Design Requirements

DESIGN PARAMETER

Analog supply voltage

VALUE

3.0 V

Modulator sampling frequency (f_MOD

)

16 MHz

Filter pass band

DC to 100 kHz (f_DATA= 250 kSPS)

–100 dB at f_MOD

Antialiasing filter rejection

Total harmonic distortion (THD)

–110 dB at –0.5-dBFS input signal amplitude

70 dB at 100-mV input signal amplitude

(104 dB normalized to 2.5-V full-scale)

Signal-to-noise ratio (SNR)

20 mA (50 mW)

ADS127L01, input drive amplifier, reference device

+ drive amplifier

Power consumption

9.2.2 Detailed Design Procedure

The ADS127L01 offers a typical THD level of –110 dB for a modulator frequency of 16.384 MHz. Target the

distortion from the input driver to be at least 10 dB better than the distortion of the ADC. The THS4551 provides

exceptional ac performance with extremely low distortion levels near –120 dB. With a 135-MHz gain-bandwidth

product, the THS4551 can drive the switched-capacitor input stage so that the load transients are mostly settled.

For higher levels of performance, use a faster amplifier with more bandwidth as long as the increased current

consumption fits within the system power budget. At 3.4 nV/√Hz broadband noise density and 1.35 mA of

quiescent current, the THS4551 offers an attractive performance versus power tradeoff that is well-suited for

these applications.

Single-ended inputs have a varying input common-mode, and can produce larger even harmonics and decrease

distortion performance. Use a fully-differential input to the ADC to help suppress even harmonics and provide a

fixed common-mode voltage for the input signal.

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For this design, the THS4551 is placed in a multiple-feedback (MFB) filter configuration, as shown in Figure 122.

Nominal resistance values of 1.2 kΩ are used in the amplifier feedback path to optimize power consumption,

while keeping the added broadband noise of the front-end driver circuit less than that of the ADS127L01. An

MFB filter produces a second-order, low-pass response.

1.2 kꢀ

270 pF

1.2 kꢀ

330 ꢀ

5 ꢀ

10 ꢀ

AP2700

THS4551

AINP

AINN

+

œ

470 pF

1 nF

22 nF

ADS127L01

+

œ

330 ꢀ

270 pF

1.2 kꢀ

Figure 122. Multiple Feedback ADC Drive Circuit

The discrete low-pass RC filter components (10 Ω and 22 nF) are small enough to increase the antialiasing filter

rolloff without adding significant distortion or gain error to the system. Combined with the active MFB filter, the

net result is a third-order antialiasing filter. Figure 123 plots the magnitude response of the front-end driver circuit

and illustrates how it supplements the Wideband 2 FIR filter in the ADS127L01.

40

20

0

-20

-40

-60

-80

-100

-120

-140

MFB Response

Digital Filter Response

-160

-180

1

2 3 5 710 20 50 100

1000

10000

100000

Frequency (kHz)

D001

Figure 123. THS4551 MFB Filter Magnitude Response

The response of the third-order antialiasing filter remains flat beyond the digital filter pass band. Signals within

the bandwidth of interest are left unattenuated by the antialiasing filter. The Wideband 2 filter is used to provide

an average stop-band attenuation of –116 dB beginning at f_DATA/ 2. This transition band prevents signals from

aliasing in the digital domain.

At f_c= 304 kHz, the antialiasing filter reaches –3 dB, and rolls off sharply at a rate of –60 dB per decade. At 16

MHz, the filter response reaches –100 dB of attenuation, effectively eliminating unwanted frequency content

around the modulator rate. The antialiasing filter attenuates the frequency content that alias around the

modulator Nyquist frequency (f_MOD/ 2). The REF6025 circuit proposed in Figure 117 was selected to drive the

ADS127L01 reference. This device enables the design to meet the outlined performance goals while remaining

within the target power budget.

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9.2.3 Application Curves

Figure 124 shows a fast Fourier transform (FFT) of the 32,768 samples collected at 250 kSPS (OSR 64). An

AP2700 generated a 4-kHz sine wave with a differential amplitude of –0.5 dB below full-scale (±2.36 V). The

fundamental input frequency at 4 kHz is the dominate tone in the FFT. The first 15 harmonics are used to

calculate the total harmonic distortion (THD) as –114.4 dB. The input amplifier and the antialiasing filter do not

degrade the overall distortion performance of the signal chain.

SNR was measured with a small-signal 100 mV_PP(–34 dB from full-scale) input sine wave generated by the

AP2700. The SNR result is the difference in magnitude between the fundamental frequency and the integrated

noise of the ADC output up until f_DATA/ 2. Figure 125 shows the FFT of the 32,768 samples collected at 256

kSPS (OSR = 64). The result is then normalized to full-scale to yield 106.3 dB.

0

-20

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

-100

-120

-140

-160

-180

-200

0

20

40

60

80

100

120

0

20

40

60

80

100

120

140

Frequency (kHz)

D017

D018

f_IN= 4 kHz, amplitude = –0.5 dBFS, THD = –114.4 dB

f_IN= 4 kHz, amplitude = 100 mV_PP, SNR = 106.3 dB

(normalized to FS)

Figure 124. THD Results

Figure 125. SNR Results

To verify the effectiveness of an antialiasing filter, input a sine wave at the frequency of interest and measure

how much that signal is attenuated at the output. In order to measure the attenuation at f_MOD= 16 MHz, input a

signal around or at that frequency and measure the alias of the signal that folds into the ADC pass band.

Figure 126 shows the FFT results of the 32,768 samples collected at 64 kSPS (OSR 256) for finer frequency bin

resolution. An Agilent 33522A was used to generate a differential -0.5 dBFS sine wave input at 16.004 MHz.

Because 16.004 MHz is offset from 16 MHz (f_MOD) by 4 kHz, the input signal aliases to 4 kHz. The magnitude of

the frequency tone is the attenuation level of the antialiasing filter.

0

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0

3

6

9

12

15

18

21

24

27

30

Frequency (kHz)

D023

f_MOD= 16 MHz, f_IN= 16.004 MHz, amplitude = –0.5 dBFS, OSR = 256 (64 kSPS)

Figure 126. Antialiasing Filter Attenuation Results

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Table 34 lists the typical current consumption and power dissipation for the ADS127L01, the THS4551, and the

REF6025.

Table 34. Power Consumption

COMPONENT

ADS127L01 (AVDD)

ADS127L01 (DVDD)

THS4551

QUIESCENT CURRENT (mA)

POWER DISSIPATION (mW)

10.6

4.4

31.8

7.8

1.3

3.9

REF6025

0.8

2.3

TOTAL

17.1

45.8

9.3 Do's and Don'ts

•

Do partition the analog, digital, and power supply circuitry into separate sections on the printed circuit board

(PCB).

•

Do use a single ground plane for analog and digital grounds.

Do place the analog components close to the ADC pins using short, direct connections.

Do keep the SCLK pin free of glitches and noise.

Do verify that the analog input voltages are within the specified input voltage range under all input conditions.

Do tie unused digital input pins to DGND to minimize input leakage current.

Do use an LDO to reduce voltage ripple generated by switch-mode power supplies.

Do synchronize clock signals and switching supply frequencies to minimize intermodulation artifacts and

noise degradation.

•

Don't cross analog and digital signals.

Don't route digital clock traces in the vicinity of the analog inputs or CAP1 and CAP2 analog bias voltages.

Don't allow the analog and digital power supply voltages to exceed 3.9 V under any condition, including

during power-up and power-down.

•

Don’t use inductive supply or ground connections.

Don’t isolate analog ground (AGND) from digital ground (DGND).

Figure 127 illustrates examples of correct and incorrect ADC circuit connections.

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Do's and Don'ts (continued)

1.8 V

3 V

CORRECT

INCORRECT

Device

AVDD

DVDD

Device

AVDD

DVDD

24-Bit

ûꢀ ADC

24-Bit

ûꢀ ADC

AGND

DGND

AGND

DGND

Low-impedance supply connections.

Inductive supply or ground connections.

1.8 V

5 V

3 V

f_SW

INCORRECT

Device

CORRECT

AVDD

DVDD

AVDD

LVDD

Device

÷ 2ⁿ

SCLK

CLK

24-Bit

ûꢀ ADC

24-Bit

ûꢀ ADC

AGND

DGND

AGND

DGND

Isolated AGND and DGND.

Synchronized clocks and switching supplies.

Figure 127. Correct and Incorrect Circuit Connections

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9.4 Initialization Setup

Figure 128 illustrates a general procedure to configure the ADS127L01 to collect data.

// Start with power off

Power Off

// Enable or disable analog 1.8-V internal LDO

Set INTLDO

// Pull up or pull down HR, OSR[1:0], FILTER[1:0],

FSMODE, and FORMAT pins to DVDD or DGND

Set Hardware Mode Pins

Power Up

Analog + Digital Supplies

// Analog and digital supplies can come up together

SET

RESET/PWDN = 1

// RESET/PWDN can come up with power supply

// Wait t_su(PWDN)and t_d(POR)for device to exit POR

Y

Using SPI

Interface Mode?

Write

Registers

// Configure ADC registers only if using SPI mode

N

Set START = 1 or

Use START Command

Set START = 1 or

Use START Command

// Bring hardware START pin high to begin conversions

// If using commands to control conversions, use START

command to begin conversions.

// Monitor for DRDY output if in SPI interface mode

// Issue FSYNC input at set data rate if in frame-sync slave interface mode

// Monitor for FSYNC output at set data rate if in frame-sync master interface mode

Monitor for

DRDY

Issue Frame-Sync or

Monitor for Frame-Sync

Collect Data

// Wait for settled data to be available and capture on DOUT

Figure 128. ADS127L01 Configuration Sequence

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10 Power Supply Recommendations

The ADS127L01 requires either two or three power supplies, depending on if the internal LDO is used to supply

the LVDD analog supply. The AVDD analog supply is referenced to AGND, the LVDD analog supply is

referenced to AGND, and the DVDD digital supply is referenced to DGND. The analog power supply can only be

unipolar (for example, AVDD = 3.0 V, AGND = 0 V) and is independent of the digital power supply. If INTLDO =

0, the LVDD supply is internally generated using the AVDD supply. If INTLDO = 1, the internal LDO is disabled

and LVDD supply must be externally supplied. The digital supply sets the digital I/O levels.

10.1 Power-Supply Sequencing

The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the

respective analog or digital power-supply voltage limits. Bring the RESET/PWDN pin high after the analog and

digital supplies are up, or bring the pin high with the DVDD supply (assuming the AVDD and LVDD supplies

come up with or before DVDD). After all supplies are stabilized, wait for the t_d(POR)timing for the power-on-reset

to complete before communicating with the device in order to allow the power-up reset process to complete.

10.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. AVDD, LVDD, and DVDD must be

decoupled with at least a 1-µF capacitor, as shown in Figure 129. Place the bypass capacitors as close to the

power-supply pins of the device as possible using low-impedance connections. Use multilayer ceramic chip

capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for

power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments,

avoid the use of vias for connecting the capacitors to the device pins for superior noise immunity. The use of

multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Connect

analog and digital ground together as close to the device as possible.

3 V

1.8 V

1 ꢀF

AVDD

DVDD

CAP1

1.8-V External

INTLDO = 1

LVDD

1 ꢀF

CAP2

CAP3

ADS127L01

REFP

REFN

10 ꢀF

0.1 ꢀF

1 ꢀF

AGND

DGND

Figure 129. ADS127L01 Recommended Power-Supply Decoupling

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11 Layout

11.1 Layout Guidelines

TI recommends employing best design practices when laying out a printed-circuit board (PCB) for both analog

and digital components. This recommendation generally means that the layout separates analog components

[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog multiplexers] from digital

components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate

arrays (FPGAs), radio-frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching

regulators]. An example of good component placement is shown in Figure 130. Although Figure 130 provides a

good example of component placement, the best placement for each application is unique to the geometries,

components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every

design, and careful consideration must always be used when designing with any analog component.

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Supply

Generation

Signal

Conditioning

(RC filters

and

Interface

Device

Microcontroller

Transceiver

amplifiers)

Connector

or Antenna

Ground Fill or

Ground Plane

Ground Fill or

Ground Plane

Figure 130. System Component Placement

The following bullet items outline some basic recommendations for the layout of the ADS127L01 to get the best

possible performance of the ADC. A good design can be ruined with bad circuit layout.

•

Separate analog and digital signals. To start, partition the board into analog and digital sections where the

layout permits. Route digital traces away from analog traces. This separation prevents digital noise from

coupling back into analog signals.

•

The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this split is not

necessary. Place analog signals over the analog plane and digital signals over the digital plane. As a final

step in the layout, completely remove the split between the analog and digital grounds. If ground plane

separation is necessary, make the connection between AGND and DGND as close to the ADC as possible.

•

Fill void areas on signal layers with ground fill.

Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground

plane is cut or has other traces that block the current from flowing right next to the signal trace, the return

current must find another path to return to the source and complete the circuit. If the return current is forced

into a larger path, the chance is increased that the signal will radiate. Sensitive signals are more susceptible

to EMI interference.

•

Use bypass capacitors on power supplies to reduce high-frequency noise. Do not place vias between bypass

capacitors and the active device. Flow the supply current through the bypass capacitor pins first and then to

the ADC supply pins. Placing the bypass capacitors on the same layer close to the active device yields the

best results. If multiple ADCs are on the same PCB, use wide power-supply traces or dedicated power-supply

planes to minimize the potential of crosstalk between ADCs.

Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react

with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source

signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI

pickup and the high-frequency impedance seen by the device.

•

Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor

may create a parasitic thermocouple that can add an offset to the measurement. Match the differential inputs

for both inputs going to the measurement source.

Analog inputs with differential connections must have a capacitor placed differentially across the inputs. The

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ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

Layout Guidelines (continued)

differential capacitors must be high quality. The best ceramic chip capacitors are C0G (NP0), with both stable

properties and low noise characteristics.

•

When REFN is tied to AGND, run the two traces separately as a star connection back to the AGND pin in

order to minimize coupling between the power-supply trace and reference-return trace.

It is important that the clock inputs are free from noise and glitches. Even with relatively slow clock

frequencies, short digital-signal rise-and-fall times can cause excessive ringing and noise. For best

performance, keep the digital signal traces short, use termination resistors as needed, and make sure all

digital signals are routed directly above the ground plane with minimal use of vias.

11.2 Layout Example

Figure 131 is an example layout of the ADS127L01, input driver circuit, and reference driver circuit using four

PCB layers. In this example, the top and bottom layers are used for analog and digital signals. The first inner

layer is dedicated to the ground plane and the second inner layer is dedicated to the power supplies. The PCB is

partitioned with analog signals routed on the left, and digital signals routed on the right. Polygon pours are used

to provide low-impedance connections between the power supplies and the reference voltage for the ADC.

80

ADS127L01

ZHCSF11B –APRIL 2016–REVISED SEPTEMBER 2016

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档ꢀ


型号：	ADS127L01
厂家：	TEXAS INSTRUMENTS
描述：	24 位、512kSPS、单通道、超低功耗、宽带宽 Δ-Σ ADC
文件：	总90页 (文件大小：2963K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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