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ADS1283

ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

ADS1283 高分辨率模数转换器

1 特性

3 说明

1

•

高分辨率:

ADS1283 是一款性能极高的单芯片模数转换器

(ADC)，配备集成式低噪声可编程增益放大器 (PGA)

和双通道输入多路复用器 (MUX)。ADS1283 可满足地

震监测设备的严苛要求。

–

SNR：130 dB（250 SPS，PGA = 1）

高精度：

–

THD：–122dB

低功耗：

此转换器使用一个固有稳定性的四阶 Δ-Σ 调制器来获

得出色的抗噪性能和线性性能。调制器数字输出由片上

数字滤波器进行数字过滤和抽取，以生成 ADC 转换结

果。

–

18mW（PGA = 1、2、4 或 8）

停机模式：10μW

•

低噪声 PGA：5nV/√Hz

双通道输入多路复用器

输入多路复用器可灵活提供附加的外部输入，用于测量

以及内部自检输入连接。PGA 具有出色的低噪声

(5nV/√Hz) 和极高的输入阻抗，便于轻松连接到具有宽

增益范围的地震检波器和水听器。

固有稳定性的调制器，具有快速响应超范围检测器

灵活的数字滤波器：

–

正弦 + 有限脉冲响应 (FIR) + 无限脉冲响应

(IIR)（可选）

–

线性或最小相位响应

可编程的高通滤波器

数字滤波器提供 250SPS 至 4000SPS 的可选数据速

率。高通滤波器 (HPF) 具有可调节的角频率。片上增

益和偏移调节寄存器支持系统校准。

可选择 FIR 数据速率：

250SPS 至 4kSPS

同步输入 (SYNC) 可用来使多个 ADS1283 器件的转换

同步。

•

偏移和增益校准引擎

SYNC 输入

模拟电源：5V 或 ±2.5V

数字电源：1.8V 至 3.3V

ADS1283 采用紧凑的 24 引线 5mm x 4 mm VQFN 封

装，完全额定工作温度为 –40°C 至 +85°C，最大工作

温度范围为 –50°C 至 +125°C。

2 应用

器件信息⁽¹⁾

•

能量勘探

器件型号

ADS1283

封装

封装尺寸（标称值）

地震监测

高精度仪器

ADS1283A

ADS1283B

VQFN (24)

5.00mm × 4.00mm

简化电路原理图

AVDD

VREFN

DVDD

VREFP

(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附

录。

CLK

CS

4^th-Order

ûꢀ

Modulator

Programmable

Digital

Filter

Input 1

Input 2

SCLK

DOUT

DIN

Serial

Interface

器件比较

Calibration

PGA

THD（典型

V_COM

器件型号

ADS1283

失调电压选项

增益

值）

–122dB

–118dB

–122dB

DRDY

SYNC

Overrange

Control

100mV

1 至 64

1、4、16

1 至 64

RESET

PWDN

ADS1283

ADS1283A

ADS1283B

100mV

AVSS

DGND

75mV、100mV

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBAS565

ADS1283

ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

www.ti.com.cn

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 16

8.4 Device Functional Modes........................................ 32

8.5 Programming........................................................... 44

8.6 Register Maps......................................................... 48

Application and Implementation ........................ 52

9.1 Application Information............................................ 52

9.2 Typical Applications ................................................ 52

9.3 Initialization Set Up ................................................. 55

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings .................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Timing Requirements............................................... 9

6.7 Switching Characteristics.......................................... 9

6.8 Typical Characteristics............................................ 10

Parameter Measurement Information ................ 14

7.1 Noise Performance ................................................. 14

Detailed Description ............................................ 15

9

10 器件和文档支持 ..................................................... 56

10.1 接收文档更新通知 ................................................. 56

10.2 社区资源................................................................ 56

10.3 商标....................................................................... 56

10.4 静电放电警告......................................................... 56

10.5 Glossary................................................................ 56

11 机械、封装和可订购信息....................................... 57

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (December 2017) to Revision C

Page

•

已更改将文档更改为面向 Web 的完整发布版........................................................................................................................ 1

Changes from Revision A (May 2015) to Revision B

Page

•

已添加 ADS1283B 器件及相关内容添加到产品说明书 ........................................................................................................... 1

已添加器件信息和器件比较表................................................................................................................................................ 1

Added Recommended Operating Conditions table; content moved from Electrical Characteristics table. No values

changed.................................................................................................................................................................................. 5

•

Deleted ADS1283A text from test condition in Electrical Characteristic table........................................................................ 6

Added new row for ADS1283B test condition to Offset parameter in the Electrical Characteristics table............................. 7

Added Switching Characteristics table; content moved from Timing Requirements table. No values changed.................... 9

Changed text in Offset section for 75-mV option ................................................................................................................. 22

Changed Figure 45 to include CLK to SYNC timing ............................................................................................................ 32

Deleted t_CSHDand t_SCSUfrom Table 12 ................................................................................................................................ 32

Added CLK to SYNC timing to Table 12 .............................................................................................................................. 32

Changed text in last paragraph of Pulse-Sync Mode section ............................................................................................. 33

Changed pulse-sync timing text to include CLK to SYNC timing ........................................................................................ 33

Changed Figure 46 to include CLK to SYNC timing ........................................................................................................... 33

Changed opcode text of WREG command from 001 to 010 ............................................................................................... 47

Added new OFFSET control bit to ID_CFG (register 00h) for ADS1283B device; no change to ADS1283 and

ADS1283A functionality........................................................................................................................................................ 48

•

Changed format of register description tables ..................................................................................................................... 48

2

ADS1283

www.ti.com.cn

ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

Changes from Original (January 2014) to Revision A

Page

•

已添加 ADS1283A 器件及相关内容添加到产品说明书 ........................................................................................................... 1

Added text regarding CS high to Read Data Requirement section. .................................................................................... 44

Added text regarding CS high to SDATAC: Stop Read Data Continuous section............................................................... 45

3

ADS1283

ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

www.ti.com.cn

5 Pin Configuration and Functions

RHF Package

5-mm × 4-mm 24-Pin VQFN

Top View

DRDY

DOUT

DIN

1

2

3

4

5

6

7

19

18

17

16

15

14

13

RESET

PWDN

VREFP

VREFN

AVSS

Thermal

Pad

CS

SYNC

MFLAG

DGND

AVDD

AINN1

Not to scale

Pin Functions

I/O

DESCRIPTION

NAME

AINN1

AINN2

AINP1

AINP2

AVDD

AVSS

BYPAS

CAPN

CAPP

CLK

NO.

13

11

12

10

14

15

22

8

Analog input

Analog supply

Analog

Negative analog input 1

Negative analog input 2

Positive analog input 1

Positive analog input 2

Positive analog power supply

Negative analog power supply

1.8-V sub-regulator output: connect 1-μF capacitor to DGND

PGA output: connect 10-nF capacitor from CAPP to CAPN

Master clock input (4.096 MHz)

Analog

9

Analog

23

4

Digital input

Ground

CS

Serial interface chip select, active low

Digital ground (tie to digital ground plane)

Serial interface data input

DGND

DIN

7

21

3

Ground

Digital input

Digital output

Digital supply

Digital output

Digital input

Analog input

DOUT

DRDY

DVDD

MFLAG

PWDN

RESET

SCLK

SYNC

VREFN

VREFP

2

Serial Interface data output

1

Data ready output: active low

20

6

Digital power supply: 1.65 V to 3.6 V

Modulator overrange flag: 0 = normal, 1 = modulator overrange

Power-down input, active low

18

19

24

5

Reset input, active low

Serial interface shift clock input

Synchronize input, rising edge active

Negative reference input

16

17

Positive reference input

Do not electrically connect the thermal pad. The thermal pad must be soldered to PCB.

Thermal pad vias are optional and can be removed.

Thermal pad

4

ADS1283

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

MIN

–0.3

MAX

5.5

UNIT

V

AVDD to AVSS

AVSS to DGND

–2.8

0.3

V

DVDD to DGND

–0.3

3.9

V

Analog input voltage

Digital input voltage to DGND

Input current, continuous

Operating temperature

Junction temperature

Storage temperature, T_stg

AVSS – 0.3

–0.3

AVDD + 0.3

DVDD + 0.3

10

V

–10

mA

°C

–50

125

150

–60

150

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

POWER SUPPLY

AVSS

AVDD

DVDD

Negative analog supply (relative to DGND)

–2.6

AVSS + 4.75

1.65

0

AVSS + 5.25

3.6

V

Positive analog supply (relative to AVSS)

Digital supply (relative to DGND)

ANALOG INPUTS

FSR

Full-scale input voltage range (V_IN= AINP – AINN)

±V_REF/ (2 × PGA)

V

Calibration margin⁽¹⁾

106

%FSR

AINP or

AINN

Absolute input voltage range

AVSS + 0.7

AVDD – 1.25

V

VOLTAGE REFERENCE INPUTS

Reference input voltage (V_REF= VREFP – VREFN)

Negative reference input

Positive reference input

1

AVSS – 0.1

VREFN + 1

5

(AVDD – AVSS) + 0.2

VREFP – 1

V

VREFN

VREFP

AVDD + 0.1

DIGITAL INPUTS

V_IH

High-level input voltage

0.8 × DVDD

DVDD

0.2 × DVDD

4.096

V

V_IL

Low-level input voltage

Clock input

DGND

1

V

f_CLK

f_SCLK

MHz

Serial clock rate

f_CLK/ 2

TEMPERATURE

Specified temperature

–40

85

°C

(1) Calibration margin is the maximum allowable input voltage after user calibration of offset and gain errors.

5

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

www.ti.com.cn

6.4 Thermal Information

ADS1283

RHF (VQFN)

24 PINS

30.2

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

27.5

8.5

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.3

ψ_JB

8.6

R_θJC(bot)

1.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,

f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1

(enabled), and f_DATA= 1000 SPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

PGA input voltage noise density

Differential input impedance⁽¹⁾

5

1

nV/√Hz

GΩ

CHOP enabled

CHOP disabled

100

1

Common-mode input impedance

Input bias current

GΩ

nA

dB

Ω

I_IB

1

Crosstalk

f = 31.25 Hz

Each switch

–135

30

Mux switch on-resistance

PGA OUTPUT (CAPP, CAPN)

Absolute output range

AVSS + 0.4

AVDD – 0.4

100

V

PGA differential output impedance

600

±10%

10

Ω

Output impedance tolerance

External bypass capacitance

nF

Modulator differential input impedance

55

kΩ

AC PERFORMANCE

SNR

Signal-to-noise ratio⁽²⁾

120

124

dB

PGA =

1, 2, 4, 8, 16

–122

–114

–110

ADS1283,

ADS1283B

Total harmonic distortion⁽³⁾

Spurious-free dynamic range

PGA = 32

–117

–114

–118

123

THD

PGA = 64

ADS1283A

PGA = 1, 4, 16

–106

SFDR

(1) PGA chop feature is disabled by setting CHOP bit = '0'. See Table 4

(2) Inputs shorted; see Table 1.

(3) Input signal = 31.25 Hz, –0.5 dBFS.

6

ADS1283

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

Electrical Characteristics (continued)

maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,

f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1

(enabled), and f_DATA= 1000 SPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DC PERFORMANCE

Resolution

Data rate

31

250

Bits

FIR filter mode

4000

128,000

±200

f_DATA

SPS

Sinc filter mode

8000

OFFSET disabled

±50

300

µV

OFFSET disabled, CHOP disabled

Offset⁽⁴⁾

95 / PGA

70 / PGA

100 / PGA

75 / PGA

1

105 / PGA

80 / PGA

OFFSET

enabled

mV

μV

ADS1283B only

Offset after calibration⁽⁵⁾

Offset drift

CHOP enabled

CHOP disabled

0.03

μV/°C

0.5

Gain error⁽⁶⁾

Gain error after calibration⁽⁵⁾

–1.5%

–1.0%

0.0002%

2

–0.5%

0.8%

PGA = 1

Gain drift

ppm/°C

PGA = 16

9

Gain matching⁽⁷⁾

0.3%

110

(8)

CMR

PSR

Common-mode rejection

f_CM= 60 Hz, 1.25 V_PP

95

80

90

dB

AVDD, AVSS

90

f_PS= 60 Hz, 100

Power-supply rejection

(8)

mV_PP

DVDD

115

VOLTAGE REFERENCE INPUTS

Reference input impedance

DIGITAL FILTER RESPONSE

Pass-band ripple

85

kΩ

±0.003

10

dB

Hz

dB

Hz

Pass band (–0.01dB)

Bandwidth (–3dB)

0.375 × f_DATA

0.413 × f_DATA

High-pass filter corner

Stop band attenuation⁽⁹⁾

Stop band

0.1

135

0.500 × f_DATA

5 / f_DATA

Minimum phase filter⁽¹⁰⁾

Linear phase filter

Group delay

s

31 / f_DATA

62 / f_DATA

Minimum phase filter

Linear phase filter

Settling time (latency)

(4) Offset specification is input referred. The offset scales by the reference voltage (V_REF).

(5) Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).

(6) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.

(7) Gain match relative to gain = 1.

(8) f_CMis the input common-mode frequency. f_PSis the power-supply frequency.

(9) Input frequencies in the range of Nf_CLK/ 1024 ± f_DATA/ 2 (where N = 1, 2, 3...) can intermodulate with the modulator chopper clock (and

N multiples). At these frequencies, intermodulation = –120 dB, typ.

(10) At dc; see Figure 42.

7

ADS1283

ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

www.ti.com.cn

Electrical Characteristics (continued)

maximum and minimum specifications over –40°C to +85°C; typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V,

f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET bit = 1 (enabled), CHOP bit = 1

(enabled), and f_DATA= 1000 SPS (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS/OUTPUTS

V_OH

V_OL

I_lkg

High-level output voltage

Low-level output voltage

Input leakage

I_OH= 1 mA

0.8 × DVDD

V

I_OL= 1 mA

0.2 × DVDD

±10

0 < V_{DIGITAL IN}< DVDD

μA

POWER SUPPLY

Operating PGA = 1, 2, 4, 8

Operating PGA = 16, 32, 64

Standby mode

3.2

4

5.5

6

|mA|

AVDD, AVSS current

1

15

|μA|

mA

μA

Power-down mode

Operating

1

15

0.6

25

1

0.8

50

DVDD current

Standby mode

Power-down mode⁽¹¹⁾

Operating PGA = 1, 2, 4, 8

Operating PGA = 16, 32, 64

Standby mode

15

18

22

90

10

30

mW

33

Power dissipation

250

125

μW

Power-down mode

(11) CLK input stopped.

8

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

6.6 Timing Requirements

at T_A= –40°C to +85°C and DVDD = 1.65 V to 3.6 V (unless otherwise noted)

MIN

40

MAX

UNIT

ns

t_CSSC

t_SCLK

t_{SPWH, L}

t_DIST

CS low to SCLK high: setup time

SCLK period

SCLK pulse duration, high and low⁽¹⁾

DIN valid to SCLK high: setup time

Valid DIN to SCLK high: hold time

CS high pulse

2

16

10

1 / f_CLK

ns

0.8

50

t_DIHD

50

ns

t_CSH

100

24

ns

t_SCCS

SCLK high to CS high

1/f_CLK

(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CS low to DOUT driven: propagation

delay

t_CSDOD

t_DOPD

60

ns

SCLK low to valid new DOUT:

propagation delay

Load on DOUT = 20 pF || 100 kΩ

100

ns

SCLK low to DOUT invalid: hold

time

t_DOHD

0

ns

t_CSDOZ

CS high to DOUT tristate

40

t_SPWH

t_SCLK

t_CSH

CS

t_SPWL

t_CSSC

t_SCCS

SCLK

t_DIST

B7

DIN

B6

t_DIHD

B5

B4

B3

B2

B1

B0

t_DOPD

DOUT

B7

t_DOHD

t_CSDOD

t_CSDOZ

Figure 1. Serial Interface Timing Diagram

9

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

www.ti.com.cn

6.8 Typical Characteristics

At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1, OFFSET enabled,

CHOP enabled, and f_DATA= 1000 SPS (unless otherwise noted). For ADS1283A, the electrical characteristics apply at PGA = 1, 4, and 16

only.

0

œ20

0

œ20

8192-Point FFT

Shorted Input

PGA = 8

8192-Point FFT

Shorted Input

PGA = 1

œ40

SNR = 121.1 dB

SNR = 123.7 dB

œ60

œ80

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

Frequency (Hz)

C003

C002

Figure 3. Output Spectrum

Figure 2. Output Spectrum

0

œ20

0

œ20

8192-Point FFT

Shorted Input

PGA = 8

CHOP Disabled

SNR = 117.5 dB

8192-Point FFT

Shorted Input

PGA = 1

CHOP DIsabled

SNR = 123.5 dB

œ40

œ60

œ80

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

50 100 150 200 250 300 350 400 450 500

Frequency (Hz)

C004

C005

Figure 4. Output Spectrum

Figure 5. Output Spectrum

0

œ20

0

œ20

8192-Point FFT

V _IN= 31.25 Hz, -0.5 dBFS

PGA = 1

8192-Point FFT

V _IN= 31.25 Hz, -0.5 dBFS

PGA = 8

œ40

THD = -124 dB

THD = -125 dB

œ60

œ80

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

50 100 150 200 250 300 350 400 450 500

Frequency (Hz)

C002

Figure 6. Output Spectrum

Figure 7. Output Spectrum

10

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ZHCSK66C –JANUARY 2014–REVISED AUGUST 2019

Typical Characteristics (continued)

At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,

OFFSET enabled, CHOP enabled, and f_DATA= 1000 SPS (unless otherwise noted). For ADS1283A, the electrical

characteristics apply at PGA = 1, 4, and 16 only.

0

8192-Point FFT

V _IN= 31.25 Hz, -20 dBFS

PGA = 1

8192-Point FFT

V _IN= 31.25 Hz, -20 dBFS

PGA = 8

œ20

œ40

THD = -122 dB

THD = -121 dB

œ60

œ80

œ100

œ120

œ140

œ160

œ180

œ100

œ120

œ140

œ160

œ180

0

50 100 150 200 250 300 350 400 450 500

0

50 100 150 200 250 300 350 400 450 500

Frequency (Hz)

C002

Figure 8. Output Spectrum

Figure 9. Output Spectrum

œ100

œ105

œ110

œ115

œ120

œ125

œ130

œ100

œ105

œ110

œ115

œ120

œ125

œ130

PGA = 1

V_IN= 31.25 Hz, -0.5 dBFS

V _IN= -0.5 dBFS

PGA = 4

PGA = 16

PGA = 64

PGA = 4

PGA = 16

PGA = 64

œ55 œ35 œ15

5

25

45

65

85

105 125

0

10 20 30 40 50 60 70 80 90 100 110 120

Temperature (°C)

Signal Frequency (Hz)

C007

C002

Figure 11. THD vs Temperature

Figure 10. THD vs Signal Frequency

140

130

120

110

100

90

140

120

100

80

PGA = 1

60

40

DVDD

AVDD

AVSS

80

20

PGA = 1

PGA = 8

70

0

10

100

1000

10000

100000

1000000

10

100

1000

10000

100000

1000000

Common Mode Frequency (Hz)

Power Supply Frequency (Hz)

C007

Figure 12. CMR vs Common-Mode Frequency

Figure 13. PSR vs Power-Supply Frequency

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Typical Characteristics (continued)

At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,

OFFSET enabled, CHOP enabled, and f_DATA= 1000 SPS (unless otherwise noted). For ADS1283A, the electrical

characteristics apply at PGA = 1, 4, and 16 only.

100

120

110

100

90

80

70

60

50

40

30

20

10

0

PGA = 1

PGA = 8

30 Units

OFFSET Enabled

30 units based on

20 ^•C intervals

over the range

-40^•C to +85 ^•C

90

80

70

60

50

40

30

20

10

0

Offset Drift (nV/°C)

Offset (mV)

C010

Figure 14. Offset-Voltage Histogram

Figure 15. Offset-Voltage Drift Histogram

100

90

80

70

60

50

40

30

20

10

0

150

140

130

120

110

100

90

PGA = 1,2,4

PGA = 16

30 Units

PGA = 1

30 units based on 20^•C intervals

over the range -40^°C to +85^°•C

PGA = 8,32,64

80

70

60

50

40

30

20

10

0

Gain Drift (ppm/°C)

Gain Error (%)

C010

Figure 16. Gain-Error Histogram

Figure 17. Gain-Error Drift Histogram

125

120

115

110

105

100

95

120

110

100

90

80

70

60

50

40

30

20

10

0

Worst case gain match

30 units, relative PGA = 1

over -40 ^°C to +85°C range

PGA = 1

PGA = 4

PGA = 16

Shorted Input

PGA = 64

œ55 œ35 œ15

90

5

25

45

65

85

105 125

Temperature (°C)

C008

Gain Match (%)

Figure 19. SNR vs Temperature

Figure 18. Gain-Match Histogram

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Typical Characteristics (continued)

At +25°C, AVDD = 2.5 V, AVSS = –2.5 V, f_CLK= 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, PGA = 1,

OFFSET enabled, CHOP enabled, and f_DATA= 1000 SPS (unless otherwise noted). For ADS1283A, the electrical

characteristics apply at PGA = 1, 4, and 16 only.

0

25

20

15

10

5

8192-Point FFT (IN1)

IN1: Shorted

IN2: 31.25 Hz, -0.5 dBFS

PGA = 8

œ20

œ40

œ60

œ80

œ100

œ120

œ140

œ160

œ180

PGA = 1,2,4,8

PGA = 16,32,64

0

50 100 150 200 250 300 350 400 450 500

œ55 œ35 œ15

5

25

45

65

85

105 125

Frequency (Hz)

C005

Temperature (°C)

C009

Figure 20. Crosstalk Output Spectrum

Figure 21. Power vs Temperature

2.0

1.5

2.0

1.5

P Input, T = 25°C

CHOP Enabled

PGA = 1

CHOP Disabled

PGA = 1

N Input, T = 25°C

P Input, T = 85°C

N Input, T = 85°C

N Input, T = 25°C

P Input, T = 85°C

N Input, T = 85°C

1.0

0.5

0.0

œ0.5

œ1.0

œ1.5

œ2.0

œ0.5

œ1.0

œ1.5

œ2.0

œ2.5 œ2.0 œ1.5 œ1.0 œ0.5 0.0 0.5 1.0 1.5 2.0 2.5

Differential Input Voltage (V)

C002

Figure 22. Input Bias Current vs Input Voltage

Figure 23. Input Bias Current vs Input Voltage

86

84

82

80

78

76

œ55 œ35 œ15

5

25

45

65

85

105 125

Temperature (°C)

C002

Figure 24. Reference Input Impedance vs Temperature

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7 Parameter Measurement Information

7.1 Noise Performance

The ADS1283 offers outstanding signal-to-noise ratio (SNR). The SNR depends on the ADC data rate and the

PGA gain selected. As the bandwidth is reduced by decreasing the data rate, the SNR improves

correspondingly. Similarly, as gain is increased, the input-referred noise decreases. The PGA noise is

independent of gain; therefore, as the gain increases, the input range correspondingly decreases, resulting in

decreased SNR.

The ADS1283 provides a chop feature that reduces the PGA 1/f noise. See the Programmable Gain Amplifier

(PGA) section for more information about chopping. Table 1 summarizes the SNR and input noise voltage with

the CHOP bit enabled. Disabling the CHOP bit results in increased low-frequency noise, particularly evident with

high PGA gains and lower sample rates. Table 2 summarizes SNR and input noise voltage with CHOP disabled.

Table 1. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Enabled

PGA (SNR, dB)⁽¹⁾

PGA (Input-Referred Noise, µV RMS)

DATA RATE

(SPS)

1

2

4

8

16

32

64

1

2

4

8

16

32

64

250

500

130

127

124

121

117

129

126

123

120

117

129

126

123

120

117

127

124

121

118

115

125

122

119

116

113

119

116

113

110

107

114

111

108

105

102

0.59

0.84

1.19

1.68

2.40

0.30

0.43

0.60

0.86

1.22

0.16

0.23

0.32

0.46

0.66

0.10

0.14

0.20

0.28

0.40

0.07

0.09

0.13

0.18

0.26

0.06

0.09

0.12

0.17

0.25

0.06

0.08

0.11

0.16

0.23

1000

2000

4000

(1) Typical values at T = +25°C and V_REF= 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis

varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to

PGA = 1, 4, and 16 only.

Table 2. Signal-to-Noise Ratio (dB) and Input Noise (µV), CHOP Bit Disabled

PGA (SNR, dB)⁽¹⁾

PGA (Input-Referred Noise, µV RMS)

DATA RATE

(SPS)

1

2

4

8

16

32

64

1

2

4

8

16

32

64

250

500

129

126

123

120

117

128

125

123

120

117

125

123

121

119

116

120

119

117

116

114

116

114

112

111

110

108

107

105

104

103

102

101

99

0.63

0.87

1.20

1.69

2.41

0.37

0.47

0.65

0.91

1.24

0.26

0.31

0.39

0.51

0.70

0.21

0.25

0.30

0.37

0.46

0.18

0.21

0.22

0.26

0.33

0.17

0.21

0.22

0.25

0.31

0.18

0.20

0.22

0.25

0.30

1000

2000

4000

(1) Typical values at T = +25°C and V_REF= 5 V. SNR values rounded to the nearest dB. Number of ADC conversions used in the analysis

varied to maintain measurement bandwidth = 0.1 Hz to 0.413 × data rate. Note that SNR and input noise data of ADS1283A applies to

PGA = 1, 4, and 16 only.

Input-referred noise is related to SNR by Equation 1:

FSR_RMS

SNR = 20log

N_RMS

where

•

FSR_RMS= Full-scale range RMS = V_REF/ (2 × √2 × PGA)

N_RMS= Noise (RMS, input-referred)

(1)

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8 Detailed Description

8.1 Overview

The ADS1283 is a high-performance analog-to-digital converter (ADC) intended for energy exploration, seismic

monitoring, chromatography, and other exacting performance applications. The converter provides 31-bit

resolution in data rates from 250 SPS to 4000 SPS. See the Functional Block Diagram section for a block

diagram of the ADS1283.

The ADS1283A device is functionally equivalent to the ADS1283, except that the ADS1283A supports PGA

gains of 1, 4, and 16 only. The ADS1283A also relaxes the THD specification of these gains. See the Electrical

Characteristics section for more details. The ADS1283B provides equivalent performance to the ADS1283, but

provides two offset voltage options, 75 mV and 100 mV. See Offset for details.

The two-channel input mux allows five configurations:

1. Input 1

2. Input 2

3. Input 1 and input 2 shorted together

4. Input 1 and input 2 disconnected and PGA input internally shorted with two 400-Ω resistors

5. Input 1 and input 2 shorted to perform input common-mode test

See the Analog Inputs and Multiplexer section for more details.

The input mux is followed by a continuous-time PGA, featuring very low noise of 5 nV/√Hz. The PGA is

controlled by register settings, allowing gains from 1 to 64 for the ADS1283 and ADS1283B, and gains of 1, 4,

and 16 for the ADS1283A.

The inherently-stable, fourth-order, delta-sigma modulator measures the differential input signal

(V_IN= AINP – AINN) against the differential reference (V_REF= VREFP – VREFN). A digital output (MFLAG)

indicates that the modulator is in overload as a result of an overdrive condition. The modulator connects to the

on-chip digital filter that provides the output codes.

The digital filter consists of a variable decimation rate, fifth-order sinc filter, followed by a variable phase,

decimate-by-32, finite-impulse response (FIR) low-pass filter with programmable phase, and then by an

adjustable high-pass filter for dc removal of the output code. The output of the digital filter can be taken from the

sinc or the FIR low-pass, with the FIR option of the infinite impulse response (IIR) high-pass section.

Gain and offset registers scale the digital filter output to produce the final code value. The scaling feature can be

used for calibration and sensor gain matching.

The SYNC input resets the operation of both the digital filter and the modulator, allowing synchronization

conversions of multiple ADS1283 devices to an external event. The SYNC input supports a continuously-toggled

input mode that accepts an external data frame clock locked to the conversion rate.

The RESET input resets the register settings and also restarts the conversion process.

The PWDN input sets the device into a micro-power state. Note that register settings are not retained in PWDN

mode. Use the STANDBY command in its place if it is desired to retain register settings (the quiescent current in

standby mode is slightly higher).

Noise-immune Schmitt-trigger and clock-qualified inputs (RESET and SYNC) provide increased reliability in high-

noise environments. The SPI™-compatible serial interface is used to read conversion data, in addition to reading

from and writing to the configuration registers.

The device allows either unipolar and bipolar analog power-supply operation. The analog supplies may be set to

+5 V for unipolar signals (with the inputs level shifted externally), or set to ±2.5 V to accept true bipolar input

signals (ground referenced). The digital supply is separate and accepts voltages from 1.8 V to 3.3 V,

independent of the analog power supplies used.

An internal subregulator is used to supply the digital core from DVDD. BYPAS (pin 28), is the subregulator output

and requires a 1-μF capacitor for noise reduction. Note that the regulated output voltage on BYPAS is not

available to drive external circuitry.

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8.2 Functional Block Diagram

AVDD

BYPAS DVDD

CLK

+1.8 V

(Digital core)

LDO

AINP2

AINN2

AINP1

AINN1

300

W

CS

4th-Order

ûꢀ

Modulator

SCLK

DIN

Programmable

Digital Filter

Serial

PGA

Calibration

Interface

DOUT

Overrange

Detection

DRDY

SYNC

400 Ω

Control

RESET

PWDN

AVDD + AVSS

2

AVSS

MFLAG

DGND

8.3 Feature Description

8.3.1 Analog Inputs and Multiplexer

A diagram of the input multiplexer is shown in Figure 25.

AVDD

S₁

S₂

AINP1

ESD Diodes

AINP2

(+)

400W

S₃

S₇

AVSS

To PGA

AVDD + AVSS

AVDD

2

400W

S₄

S₅

S₆

AINN1

AINN2

(-)

ESD Diodes

AVSS

Figure 25. Analog Inputs and Multiplexer

ESD diodes protect the multiplexer inputs. If either input is taken below AVSS – 0.3 V, or above AVDD + 0.3 V,

the ESD protection diodes can turn on. If these conditions are possible, use external clamp diodes, series

resistors, or both to limit the input current to safe values (see the Absolute Maximum Ratings table).

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Feature Description (continued)

Also, overdriving one unused input can affect the conversions of the other input. If an overdriven input interacts

with the measured input, clamp the overdriven signal with external Schottky diodes.

The specified input operating range of the PGA is shown in Equation 2:

AVSS + 0.7V < (AINN or AINP) < AVDD - 1.25V

(2)

For best operation, maintain absolute input levels (input signal level and common-mode level) within these limits.

The multiplexer connects one of the two external differential inputs to the preamplifier inputs, in addition to

internal connections for various self-test modes. Table 3 summarizes the multiplexer configurations for Figure 25.

Table 3. Multiplexer Modes

MUX[2:0]

000

SWITCHES

S₁, S₅

DESCRIPTION

AINP1 and AINN1 connected to preamplifier

001

S₂, S₆

AINP2 and AINN2 connected to preamplifier

010

S₃, S₄

Preamplifier inputs shorted together through 400-Ω internal resistors

AINP1, AINN1 and AINP2, AINN2 connected together and to the preamplifier

External short, preamplifier inputs shorted to AINN2 (common-mode test)

011

S₁, S₅, S₂, S₆

S₆, S₇

100

The typical on-resistance (R_ON) of the multiplexer is 30 Ω (each switch). When the multiplexer is used to drive an

external load on one input by a signal generator on the other input, on-resistance and on-resistance amplitude

dependency can lead to measurement errors. Figure 26 shows THD versus load resistance and amplitude. THD

improves with high-impedance loads and with lower-amplitude drive signals. The data are measured with the

circuit from Figure 27 with MUX[2:0] = 011.

0

PGA = 1

PGA = 2

PGA = 4

PGA = 8

-20

-40

PGA = 16

PGA = 32

PGA = 64

-60

-80

-100

-120

-140

0.1k

1k

10k

100k

1M

10M

R_LOAD(W)

Figure 26. THD vs External Load and Signal Magnitude (PGA); See Figure 27

500 Ω

Input 1

Test Signal

500 W

Input 2

R_LOAD

Figure 27. Driving an External Load Through the Multiplexer

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8.3.2 Programmable Gain Amplifier (PGA)

The PGA of the ADS1283 is a low-noise, continuous-time, differential-in and differential-out CMOS amplifier. The

gain is set by register bits PGA[2:0], and is programmable from 1 to 64 for the ADS1283, or can be set to 1, 4,

and 16 for the ADS1283A. The PGA differentially drives the modulator through 300-Ω internal resistors. A C0G

capacitor (10-nF C0G or film dielectric) must be connected to CAPP and CAPN to filter modulator sampling

glitches. The external capacitor also serves as an antialias filter. The corner frequency is given in Equation 3:

1

f_P=

6.3 ´ 600 ´ C

(3)

The ADS1283 PGA provides a chop feature. As shown in Figure 28, amplifiers A₁and A₂are chopper stabilized

to remove the offset, offset drift, and 1/f noise. Chopper stabilization (or chopping) moves the offset and noise to

f_CLK/ 1024 (4 kHz, f_CLK= 4.096 MHz ), which is located safely out of the pass-band frequency. Chopping can be

disabled by setting the CHOP bit = 0. When chopping is disabled, the PGA input impedance increases (see

Differential Input Impedance parameter in the Electrical Characteristics). As shown in Figure 29, chopping

maintains flat noise density, leaving predominantly white noise. However, if chopping is disabled, the PGA input

noise results in a rising 1/f noise profile.

AVDD

MUX (+)

300W

A₁

CAPP

CHOP

Gain Control

10nF

PGA[2:0] Bits

(55kW, typ

Modulator

Effective

Impedance

)

CAPN

300W

A₂

MUX (-)

Chopping Control CHOP Bit

AVSS

(1) Modulator input impedance scales with clock rate.

Figure 28. PGA Block Diagram

100

PGA CHOP Off

PGA CHOP On

10

1

10

100

Frequency (Hz)

1k

Figure 29. PGA Noise

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As a result of the stray capacitance of the input chopping switches, low-level transient currents flow through the

inputs when chopping is enabled. The average value of the transient currents versus the input voltage results in

an effective input impedance. The effective input impedance depends on the PGA gain, as shown in Table 4.

Despite the relatively high input impedance, carefully evaluate applications with high-impedance sensors or high-

impedance termination resistors when chopping is enabled. Table 4 shows the PGA differential input impedance

with CHOP enabled.

Table 4. Differential Input Impedance (CHOP Enabled)

PGA

1

DIFFERENTIAL INPUT IMPEDANCE (GΩ)

7

2

4

8

3

16

32

64

2

1

0.5

The PGA has programmable gains from 1 to 64. Table 5 shows the register bit setting for the PGA and resulting

full-scale differential range.

Table 5. PGA Gain Settings

DIFFERENTIAL INPUT RANGE

PGA[2:0]

000

GAIN⁽¹⁾

(V)⁽²⁾

±2.5

1

2

001

±1.25

010

4

±0.625

±0.312

±0.156

±0.078

±0.039

011

8

100

16

32

64

101

110

(1) The ADS1283A supports gains of 1, 4, and 16 only.

(2) V_REF= 5 V. The input range scales with V_REF

.

The specified range of the PGA output is shown in Equation 4:

AVSS + 0.4V < (CAPN or CAPP) < AVDD - 0.4V

(4)

For best performance, maintain PGA output levels (signal + common-mode) within these limits.

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8.3.3 Analog-to-Digital Converter (ADC)

The ADC block of the ADS1283 is composed of two sections: a high-accuracy modulator and a programmable

digital filter.

8.3.3.1 Modulator

The high-performance modulator is an inherently-stable, fourth-order, ΔΣ, 2 + 2 pipelined structure, as Figure 30

shows. The modulator shifts the quantization noise to a higher frequency (out of the pass band), where the noise

can be easily removed by digital filtering. The modulator data can either be completely filtered by the on-chip

digital filter or partially filtered by the onboard sinc filter in conjunction with external, post-processing filters.

f_CLK/4

f_{MOD =}

1st-Stage

(2nd-Order ûꢀ)

Analog

Signal

Digital

Filter

Math

Block

2nd-Stage

(2nd-Order

ûꢀ)

Figure 30. Fourth-Order Modulator

The modulator performance is optimized for input signals over the dc to 2-kHz bandwidth. As Figure 31 shows,

the effect of PGA and modulator chop result in spectral artifacts at the chop frequency (4 kHz) and related odd-

order harmonics to the chop frequency. When using the sinc filter mode in conjunction with an external post-

decimation filter, design the external digital filter to suppress the modulator chopping artifacts.

0

œ20

œ40

œ60

œ80

œ100

œ120

œ140

œ160

œ180

0

4000 8000 12000 16000 20000 24000 28000 32000

Frequency (Hz)

C001

Figure 31. Sinc Output FFT (64 kSPS)

8.3.3.1.1 Modulator Overrange

The ADS1283 modulator is inherently stable, and therefore, has predictable recovery behavior resulting from an

input overdrive condition. The modulator does not exhibit self-reset cycles, which often results in an unstable

output data stream. The ADS1283 modulator outputs a data stream with 90% duty cycle of ones-to-zeroes

density with the positive full-scale input signal applied (10% duty cycle with the negative full-scale signal). If the

input is overdriven past 90% modulation, but below 100% modulation (10% and 0% for negative overdrive,

respectively), the modulator remains stable and continues to output the 1s density data stream. The digital filter

may or may not clip the output codes to +FS or –FS, depending on the duration of the overdrive. When the input

returns to the normal range from a long-duration overdrive (worst case), the modulator returns immediately to the

normal range, but the group delay of the digital filter delays the return of the conversion result to within the linear

range (31 readings for linear phase FIR). An additional 31 readings (62 total) are required for completely-settled

data.

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If the inputs are sufficiently overdriven to drive the modulator to full duty cycle (that is, all 1s or all 0s), the

modulator enters a stable saturated state. The digital output code may clip to +FS or –FS, again depending on

the duration. A small-duration overdrive condition may not always clip the output code. When the input returns to

the normal range, the modulator requires up to 12 modulator clock cycles (f_MOD) to exit saturation and return to

the linear region. The digital filter requires an additional 62 conversions for fully-settled data (linear-phase FIR).

In the extreme case of input overrange (where either overdriven input exceeds the voltage of the analog supply

voltage plus an internal ESD diode drop), the internal diodes begin to conduct, thus clipping the input signal.

When the input overdrive is removed, the diodes recover quickly. Make sure to limit the input current to 10 mA

(continuous duty) if an overvoltage condition is possible.

8.3.3.1.2 Modulator Input Impedance

The modulator samples the buffered input voltage with an internal capacitor to perform conversions. The

charging of the input sampling capacitor draws a transient current from the PGA output. Use the average value

of the current to calculate an effective input impedance, as shown in Equation 5:

R_EFF= 1 / (f_MOD× C_S)

where

•

f_MOD= Modulator sample frequency = CLK / 4

C_S= Input sampling capacitor = 17 pF (typ)

(5)

The resulting modulator input impedance is 55 kΩ (CLK = 4.096 MHz). The modulator input impedance and the

internal PGA 300-Ω output resistors result in a systematic gain error of –1%. The modulator C_Scan vary ±20%

over production lots, affecting the nominal gain error.

8.3.3.1.3 Modulator Overrange Detection (MFLAG)

The ADS1283 has a fast-responding, overrange detection that indicates when the differential input exceeds

100% or –100% full-scale. The threshold tolerance is ±2.5%.The MFLAG output pin asserts high when in an

overrange condition. As Figure 32 and Figure 33 illustrate, the absolute differential input is compared to 100% of

range. The output of the comparator is sampled at the rate of f_MOD/ 2, yielding the MFLAG output. The minimum

detectable MFLAG pulse duration is f_MOD/ 2.

AINP

å

IABSI

P

100% FS

AINN

Q

MFLAG

f_MOD/2

Figure 32. Modulator Overrange Block Diagram

+100

(AINP - AINN)

0

Time

-100

MFLAG

Figure 33. Modulator Overrange Flag Operation

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8.3.3.1.4 Offset

The ADC modulator can produce low-level idle tones that appear in the spectrum when there is no signal input or

when low-level signal inputs are present to the ADC. The ADC provides an optional dc offset voltage designed to

shift the idle tones to the stop band of digital filter response, where the idle tones are reduced. The internal offset

is applied to the modulator input; therefore, the offset voltage amplitude is independent of PGA gain. For all

ADS1283 versions, the offset option is 100 mV. For the ADS1283B, a second offset option is 75 mV. The 75-mV

offset optimally reduces idle tones under various gain, data rate, and chop mode settings.

The offset is enabled by the OFFSET1 and OFFSET0 bits (default is off). The offset voltage reduces the

available input range 4% (3% for the 75 mV value) before the onset of clipped codes. The offset voltage can be

calibrated by using the offset calibration register (OFC[2:0]). Use the offset calibration register to compensate the

offset voltage, thereby restoring the full input voltage range. See Offset and Full-Scale Calibration Registers and

Calibration Commands (OFSCAL and GANCAL) sections for more details.

8.3.3.1.5 Voltage Reference Inputs (VREFP, VREFN)

The voltage reference for the ADS1283 is the differential voltage between VREFP and VREFN:

V_REF= VREFP – VREFN

(6)

The reference inputs use a structure similar to that of the analog inputs with the circuitry of the reference inputs

shown in Figure 34. The average load presented by the switched-capacitor reference input can be modeled with

an effective differential impedance of:

R_EFF= t_SAMPLE/ C_IN(t_SAMPLE= 1 / f_MOD).

(7)

Note that the effective impedance of the reference inputs loads the external reference.

AVDD

f_MOD= f_CLK/4

ESD

Diodes

1

R_EFF

=

f

_MODx 11.5 pF

VREFP

VREFN

R_EFF: 85 kΩ

11.5pF

ESD

Diodes

AVSS

Figure 34. Simplified Reference Input Circuit

Place a 0.1-µF ceramic capacitor directly between the ADC VREFP and VREFN pins. Multiple ADC applications

can share a single voltage reference, but must have individual capacitors placed for each ADC.

The ADS1283 reference inputs are protected by ESD diodes. In order to prevent these diodes from turning on,

the voltage on either input must stay within the range shown in Equation 8:

AVSS - 300mV < (VREFP or VREFN) < AVDD + 300mV

(8)

The minimum valid input for VREFN is AVSS – 0.1 V, and the maximum valid input for VREFP is AVDD + 0.1 V.

To achieve the best performance from the ADS1283, use a high-quality 5-V reference voltage. A 4-V or 4.5-V

reference voltage can be used; however, this lower reference voltage reduces the signal input range with a

corresponding decrease of SNR. Noise and drift on the reference degrade overall system performance. To

achieve optimum performance, make sure to give special care to the circuitry generating the reference voltages.

See the Application Information section for reference recommendations.

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8.3.3.2 Digital Filter

The digital filter receives the modulator output and decimates the data stream. By adjusting the amount of

filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, filter less for

higher data rate.

The digital filter is comprised of three cascaded filter stages: a variable-decimation, fifth-order sinc filter; a fixed-

decimation FIR, low-pass filter (LPF) with selectable phase; and a programmable, first-order, high-pass filter

(HPF), as shown in Figure 35.

Filter Mode

(Register Select)

Filter

MUX

To Output Register

Sinc Filter

(Decimate by

8 to 128)

Coefficient Filter

(FIR)

(Decimate by 32)

High-Pass Filter

(IIR)

Code

Clip

CAL

Block

From Modulator

Figure 35. Digital Filter and Output Code Processing

The output can be taken from one of the three filter blocks, as Figure 35 shows. For partial filtering by the

ADS1283, select the sinc filter output. For complete on-chip filtering, activate both the sinc + FIR stages. The

HPF can then be included to remove dc and low frequencies from the data. Table 6 shows the filter options.

Table 6. Digital Filter Selection

FILTR[1:0] BITS

DIGITAL FILTERS SELECTED

Reserved (not used)

Sinc

00

01

10

Sinc + FIR

Sinc + FIR + HPF

(low-pass and high-pass)

11

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8.3.3.2.1 Sinc Filter Stage (sinx / x)

The sinc filter is a variable decimation rate, fifth-order, low-pass filter. Data are supplied to this section of the filter

from the modulator at the rate of f_MOD(f_CLK/ 4). The sinc filter attenuates the high-frequency noise of the

modulator, then decimates the data stream into parallel data. The decimation rate affects the overall data rate of

the converter, and is set by the DR[2:0] register bits, as shown in Table 7.

Table 7. Sinc Filter Data Rates

DR[2:0] REGISTER

DECIMATION RATIO (N)

DATA RATE (SPS)

8,000

000

001

010

011

100

128

64

32

16

8

16,000

32,000

64,000

128,000

Equation 9 shows the scaled Z-domain transfer function of the sinc filter.

5

-N

1 - Z

-1

N(1 - Z )

H(Z) =

where

•

N = decimation ratio

(9)

Equation 10 shows the frequency domain transfer function of the sinc filter.

5

pN ´ f

sin

f_MOD

½H(f)½ =

p ´ f

N sin

f_MOD

where

•

N = decimation ratio (see Table 7)

(10)

The sinc filter has notches (or zeros) that occur at the output data rate and multiples thereof. At these

frequencies, the filter has zero gain. Figure 36 shows the frequency response of the sinc filter and Figure 37

shows the roll-off of the sinc filter.

0

-20

0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-40

-60

-80

-100

-120

-140

0

1

2

3

4

5

0

0.05

0.10

0.15

0.20

Normalized Frequency (f_IN/f_DATA

)

Normalized Frequency (f_IN/f_DATA

)

Figure 36. Sinc Filter Frequency Response

(N = 32)

Figure 37. Sinc Filter Roll-Off

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8.3.3.2.2 FIR Stage

The second stage of the ADS1283 digital filter is an FIR low-pass filter. Data are supplied to this stage from the

sinc filter. The FIR stage is segmented into four substages, as shown in Figure 38.

FIR Stage 1

Decimate by 2

FIR Stage 2

Decimate by 2

FIR Stage 3

Decimate by 4

FIR Stage 4

Decimate by 2

Sinc

Filter

Output

Coefficients

Linear

Minimum

PHASE Select

Figure 38. FIR Filter Substages

The first two substages are half-band filters with decimation ratios of two. The third substage decimates by four,

and the fourth substage decimates by two. The overall decimation of the FIR stage is 32. Note that two

coefficient sets are used for the third and fourth sections, depending on the phase selection. Table 8 lists the

data rates and overall decimation ratio of the FIR stage. See Table 9 for the FIR filter coefficients.

Table 8. FIR Filter Data Rates

DR[2:0] REGISTER

DECIMATION RATIO (N)

FIR DATA RATE (SPS)

000

001

010

011

100

4096

2048

1024

512

250

500

1000

2000

4000

256

Table 9. FIR Stage Coefficients

SECTION 1

SECTION 2

SECTION 3

SECTION 4

SCALING = 1 / 134217728

LINEAR PHASE

SCALING =

1 / 512

LINEAR PHASE

SCALING =

1 / 8388608

LINEAR

PHASE

MINIMUM

PHASE

LINEAR

PHASE

MINIMUM

PHASE

COEFFICIENT

b₀

b₁

3

0

–10944

0

819

–132

–432

11767

0

8211

133882

b₂

–25

0

103807

0

–73

44880

–75

769961

b₃

–874

174712

2481

2940447

b₄

150

256

150

0

–507903

0

–4648

536821

6692

8262605

b₅

–16147

–41280

–80934

–120064

–118690

–18203

224751

580196

893263

891396

293598

–987253

–2635779

–3860322

–3572512

1372637

3012996

5788605

9852286

14957445

20301435

24569234

26260385

24247577

18356231

9668991

327749

7419

17902757

30428735

40215494

39260213

23325925

–1757787

–21028126

–21293602

–3886901

14396783

16314388

1518875

b₆

2512192

4194304

2512192

0

–266

b₇

–10663

–8280

10620

22008

348

b₈

–25

0

b₉

b₁₀

b₁₁

b₁₂

b₁₃

b₁₄

b₁₅

b₁₆

b₁₇

b₁₈

b₁₉

3

–507903

0

103807

0

–34123

–25549

33460

61387

–7546

–94192

–50629

101135

–10944

–7171917

–10926627

–10379094

–12979500

–11506007

2769794

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Table 9. FIR Stage Coefficients (continued)

SECTION 1

SECTION 2

SECTION 3

SECTION 4

SCALING = 1 / 134217728

LINEAR PHASE

SCALING =

1 / 512

LINEAR PHASE

SCALING =

1 / 8388608

LINEAR

PHASE

MINIMUM

PHASE

LINEAR

PHASE

MINIMUM

PHASE

COEFFICIENT

b₂₀

b₂₁

b₂₂

b₂₃

b₂₄

b₂₅

b₂₆

b₂₇

b₂₈

b₂₉

b₃₀

b₃₁

b₃₂

b₃₃

b₃₄

b₃₅

b₃₆

b₃₇

b₃₈

b₃₉

b₄₀

b₄₁

b₄₂

b₄₃

b₄₄

b₄₅

b₄₆

b₄₇

b₄₈

b₄₉

b₅₀

b₅₁

b₅₂

b₅₃

b₅₄

b₅₅

b₅₆

b₅₇

b₅₈

b₅₉

b₆₀

b₆₁

b₆₂

b₆₃

b₆₄

–822573

4669054

12153698

19911100

25779390

27966862

25779390

19911100

12153698

4669054

–822573

–3572512

–3860322

–2635779

–987253

293598

891396

893263

580196

224751

–18203

–118690

–120064

–80934

–41280

–16147

–4648

–6505618

–1333678

2972773

5006366

4566808

2505652

126331

–1496514

–1933830

–1410695

–502731

245330

565174

492084

231656

–9196

134826

–56626

12195551

6103823

–6709466

–9882714

–353347

8629331

5597927

–4389168

–7594158

–428064

6566217

4024593

–3679749

–5572954

332589

–220104

–56082

263758

231231

–215231

–430178

34715

580424

283878

–588382

–693209

366118

1084786

132893

5136333

2351253

–3357202

–3767666

1087392

3847821

919792

–125456

–122207

–61813

–4445

–1300087

–878642

1162189

1741565

–522533

–2490395

–688945

2811738

2425494

–2338095

–4511116

641555

22484

22245

10775

–2918303

–2193542

1493873

2595051

–79991

940

–2953

–2599

–1052

–874

–43

–2260106

–963855

1482337

1480417

–586408

–1497356

–168417

1166800

644405

–73

214

6661730

2950811

–8538057

–10537298

9818477

41426374

56835776

41426374

9818477

–10537298

–8538057

2950811

6661730

641555

0

132

0

33

0

–675082

–806095

211391

740896

141976

–527673

–327618

278227

–4511116

–2338095

2425494

363809

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Table 9. FIR Stage Coefficients (continued)

SECTION 1

SECTION 2

SECTION 3

SECTION 4

SCALING = 1 / 134217728

LINEAR PHASE

SCALING =

1 / 512

LINEAR PHASE

SCALING =

1 / 8388608

LINEAR

PHASE

MINIMUM

PHASE

LINEAR

PHASE

MINIMUM

PHASE

COEFFICIENT

b₆₅

2811738

–688945

–2490395

–522533

1741565

1162189

–878642

–1300087

132893

1084786

366118

–693209

–588382

283878

580424

34715

–70646

–304819

–63159

205798

124363

–107173

–131357

31104

107182

15644

–71728

–36319

38331

38783

–13557

–31453

–1230

20983

7729

–11463

–8791

4659

7126

–732

–4687

–976

2551

1339

–1103

–1085

314

b₆₆

b₆₇

b₆₈

b₆₉

b₇₀

b₇₁

b₇₂

b₇₃

b₇₄

b₇₅

b₇₆

b₇₇

b₇₈

b₇₉

b₈₀

b₈₁

–430178

–215231

231231

263758

–56082

–220104

–56626

134826

101135

–50629

–94192

–7546

b₈₂

b₈₃

b₈₄

b₈₅

b₈₆

b₈₇

b₈₈

b₈₉

b₉₀

b₉₁

b₉₂

b₉₃

61387

b₉₄

33460

b₉₅

–25549

–34123

348

b₉₆

681

b₉₇

16

b₉₈

22008

–349

–96

b₉₉

10620

b₁₀₀

b₁₀₁

b₁₀₂

b₁₀₃

b₁₀₄

b₁₀₅

b₁₀₆

b₁₀₇

b₁₀₈

b₁₀₉

–8280

144

–10663

–266

78

–46

7419

–42

6692

9

2481

16

–75

0

–432

–4

–132

0

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As shown in Figure 39, the FIR frequency response provides a flat pass band to 0.375 of the data rate

(±0.003 dB pass-band ripple). Figure 40 shows the transition from pass band to stop band.

2.0

1.5

20

0

-20

1.0

-40

0.5

-60

0

-80

-0.5

-1.0

-1.5

-2.0

-100

-120

-140

-160

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

Normalized Input Frequency (f_IN/f_DATA

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Normalized Input Frequency (f_IN/f_DATA

)

Figure 40. FIR Transition Band Magnitude Response

Figure 39. FIR Pass-Band Magnitude Response (f_DATA

500 Hz)

=

Although not shown in Figure 40, the pass-band response repeats at multiples of the modulator frequency

(Nf_MOD– f₀and Nf_MOD+ f₀, where N = 1, 2, and so on, and f₀= pass band). These image frequencies, if present

in the signal and not externally filtered, fold back (or alias) into the pass band and cause errors. A low-pass

signal filter reduces the effect of aliasing. Often, the RC low-pass filter provided by the PGA output resistors and

the external capacitor connected to CAPP and CAPN provide sufficient signal attenuation.

8.3.3.2.3 Group Delay and Step Response

The FIR block is implemented as a multistage FIR structure with selectable linear or minimum phase response.

The pass band, transition band, and stop band responses of the filters are nearly identical but differ in the

respective phase responses.

8.3.3.2.3.1 Linear Phase Response

Linear phase filters exhibit constant delay time versus input frequency (that is, constant group delay). Linear

phase filters have the property that the time delay is constant from any instant of the input signal to the same

instant of the output data, and is independent of the signal nature. This filter behavior results in essentially zero

phase error when analyzing multitone signals. However, the group delay and settling time of the linear phase

filter are somewhat larger than the minimum phase filter, as shown in Figure 41.

1.4

Minimum Phase Filter

1.2

1.0

0.8

0.6

0.4

0.2

Linear Phase Filter

0

-0.2

0

5

10 15 20 25 30 35 40 45 50 55 60 65

Time Index (1/f_DATA

)

Figure 41. FIR Step Response

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8.3.3.2.3.2 Minimum Phase Response

The minimum phase filter provides a short delay from the arrival of an input signal to the output, but the

relationship (phase) is not constant versus frequency, as shown in Figure 42. The filter phase is selected by the

PHS bit, as Table 10 shows.

35

Linear Phase Filter

30

25

20

15

10

Minimum Phase Filter

5

0

20

40

60

80 100 120 140 160 180 200

Frequency (Hz)

Figure 42. FIR Group Delay (f_DATA= 500Hz)

Table 10. FIR Phase Selection

PHS BIT

FILTER PHASE

Linear

0

1

Minimum

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8.3.3.2.4 HPF Stage

The last stage of the ADS1283 filter block is a first-order HPF implemented as an IIR structure. This filter stage

blocks dc signals, and rolls off low-frequency components below the cutoff frequency. The transfer function for

the filter is shown in Equation 11:

-1

2 - a

1 - Z

HPF(Z) =

´

-1

2

1 - bZ

where

•

b is calculated as shown in Equation 12

(11)

(12)

1 + (1 - a)²

b =

2

The high-pass corner frequency is programmed by registers HPF[1:0], in hexadecimal. Equation 13 is used to set

the high-pass corner frequency. Table 11 lists example values for the high-pass filter.

cos w_N+ sin w_N- 1

HPF[1:0] = 65,536 1 -

1 - 2

cos w_N

where

•

HPF = High-pass filter register value (converted to hexadecimal)

ω_N= 2πf_HP/ f_DATA(normalized frequency, radians)

f_HP= High-pass corner frequency (Hz)

f_DATA= Data rate (Hz)

(13)

Table 11. High-Pass Filter Value Examples

f_HP(Hz)

0.5

DATA RATE (SPS)

HPF[1:0]

0337h

250

500

1.0

0337h

1.0

1000

019Ah

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The HPF causes a small gain error, in which case the magnitude of the error depends on the ratio of f_HP/ f_DATA

.

For many common values of (f_HP/ f_DATA), the gain error is negligible. Figure 43 shows the gain error of the HPF.

0

-0.10

-0.20

-0.30

-0.40

-0.50

0.0001

0.001

0.01

0.1

Frequency Ratio (f_HP/f_DATA

)

Figure 43. HPF Gain Error

The gain error factor is illustrated in Equation 14:

cos w_N+ sin w_N- 1

1 +

1 - 2

cos w_N

HPF Gain =

cos w_N+ sin w_N- 1

cos w_N

2 -

(14)

Figure 44 shows the first-order amplitude and phase response of the HPF. In the case of applying step inputs or

synchronizing, make sure to take the settling time of the filter into account.

0

90

75

60

45

30

-7.5

-15.0

-22.5

-30.0

-37.5

-45.0

Amplitude

Phase

15

0

0.01

0.1

1

10

100

Normalized Frequency (f/f_C)

Figure 44. HPF Amplitude and Phase Response

8.3.4 Master Clock Input (CLK)

The ADS1283 requires a clock for operation. The nominal clock frequency is 4.096 MHz. The clock is applied to

the CLK pin. The ADC data rates scale with CLK frequency, however there is no benefit in noise by reducing the

CLK frequency.

As with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance.

Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock

input; keep the clock trace as short as possible and use a 50-Ω series resistor close to the source.

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8.4 Device Functional Modes

8.4.1 Synchronization (SYNC PIN and SYNC Command)

The ADS1283 can be synchronized to an external event, as well as to other ADS1283 devices if the

synchronization is applied simultaneously.

The ADS1283 has two sources for synchronization: the SYNC input pin and the SYNC command. The ADS1283

also has two synchronizing modes: pulse-sync and continuous-sync. In pulse-sync mode, the ADS1283

synchronizes to a single synchronization. In continuous-sync mode, either a single synchronization is used to

synchronize conversions, or a continuous clock is applied to the pin with a period equal to integer multiples of the

data rate. When the periods of the SYNC input and the DRDY output do not match, the ADS1283 resynchronizes

and conversions are restarted.

8.4.1.1 Pulse-Sync Mode

In pulse-sync mode, when a synchronization occurs (by pin or command), the ADS1283 unconditionally stops

and restarts the conversion process. When the ADC synchronizes, the device resets the internal filter memory,

DRDY goes high, and after the digital filter has settled, new conversion data are available as shown in Figure 45

and Table 12.

t_CSDL

CLK

t_DR

SYNC

t_SPWH

t_SPWL

New Data Ready

DRDY

(Pulse-sync mode)

DOUT

(Pulse-sync mode)

New Data Ready

DRDY

(Continuous-sync mode)

DOUT

(Continuous-sync mode)

Figure 45. Pulse-Sync and Continuous-Sync Timing With Single Synchronization

Table 12. Pulse-Sync Timing for Figure 45 and Figure 46

PARAMETER

CLK rising edge to SYNC rising edge⁽¹⁾

SYNC clock period⁽²⁾

MIN

30

1

MAX

–30

UNIT

ns

t_CSDL

t_SYNC

Infinite

n / f_DATA

1 / f_CLK

t_{SPWH, L}

SYNC pulse width, high or low

Time for data ready (SINC filter)

Time for data ready (FIR filter)

2

See Table 13

t_DR

62.98046875 / f_DATA+ 468 / f_CLK

(1) CLK rising edge to SYNC rising edge timing must not occur within the specified time window.

(2) Continuous-sync mode; a free-running clock applied to the SYNC input without causing resynchronization. See Figure 46

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Table 13. t_DRTime for Data Ready (Sinc Filter)

f_DATA(kSPS)

f_CLKCYCLES⁽¹⁾

128

64

32

16

8

440

616

968

1672

2824

(1) For SYNC and WAKEUP commands, number of f_CLKcycles from next rising CLK edge directly after

eighth rising SCLK edge to DRDY falling edge. For WAKEUP command only, subtract two f_CLKcycles.

Table 13 is referenced by Table 12 and Table 15.

Observe the timing restriction of SYNC rising edge to CLK rising edge as shown in Figure 45 and Table 12.

Synchronization occurs on the next rising CLK edge after the rising edge of the SYNC, or after the eighth rising

SCLK edge when synchronized by command. To synchronize multiple ADCs, broadcast the command to the

ADCs simultaneously.

8.4.1.2 Continuous-Sync Mode

In continuous-sync mode, either a single synchronization pulse or a continuous clock may be applied. When a

single synchronization pulse is applied (rising edge), the device resynchronizes as it does in pulse-sync mode.

ADC resynchronization occurs only under the condition that the time from the previous rising edge of SYNC is

not a multiple of the conversion period. When resynchronization occurs in continuous-sync mode, DRDY

continues to toggle unaffected, and the DOUT output is held low until data are ready (63 DRDY periods later). At

the 63rd reading, conversion data are valid (when the conversion data are non-zero), as shown in Figure 45.

When a continuous clock is applied to the SYNC pin, the period must be an integral multiple of the output data

rate or the device resynchronizes. Note that synchronization results in the restarting of the digital filter and an

interruption of 63 readings (as shown in Table 12).

If a SYNC clock is applied to the ADC, the device resynchronizes only under the condition t_SYNC≠ N / f_DATA

,

where N = 1, 2, 3, and so on. DRDY continues to output, but DOUT is held low until the new data are ready. If a

SYNC clock is applied and the clock period matches an integral multiple of the output data rate, the device freely

runs without resynchronization. Note that the phase of the applied clock and output data rate (DRDY) are not

aligned because of the initial delay of DRDY after the SYNC clock is first applied. Figure 46 shows the timing for

continuous-sync mode.

t_CSDL

CLK

t_SPWH

SYNC

t_SPWL

t_SYNC

DRDY

1/f_DATA

Figure 46. Continuous-Sync Timing With SYNC Clock

Apply a SYNC clock input after the continuous-sync mode is set. The first rising edge of SYNC then causes a

synchronization. Note that subsequent writes to any ADC register results in resynchronization at the time of the

register write operation. The resynchronization leads to loss of the SYNC-pin controlled synchronization

performed previously. Send the STANDBY command followed by the WAKEUP command to reestablish the

SYNC-pin synchronization. Resynchronization to the SYNC pin occurs as long as the time between the

STANDBY and WAKEUP commands is not a multiple integer of the conversion period by at least one clock

cycle.

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8.4.2 Reset (RESET Pin and Reset Command)

The ADS1283 can be reset in two ways: toggle the RESET pin low, or send a RESET command. When using

the RESET pin, take it low and hold for at least 2 / f_CLKto force a reset. The ADS1283 is held in reset until the

pin is released. By command, reset takes effect on the next rising edge of f_CLKafter the eighth rising edge of

SCLK of the command. In order to make certain that the RESET command can function, the SPI interface may

need to be reset; see the Serial Interface section.

When the ADS1283 is reset, registers are set to default and the conversions are synchronized on the next rising

edge of CLK. New conversion data are available, as shown in Figure 47 and Table 14.

Settled

Data

DRDY

t_DR

t_CRHD

System Clock

(f_CLK)

t_RCSU

t_RST

RESET Pin

or

RESET Command

Figure 47. Reset Timing

Table 14. Reset Timing for Figure 47

PARAMETER

MIN

UNIT

ns

t_CRHD

t_RCSU

t_RST

CLK to RESET hold time

RESET to CLK setup time

RESET low

10

ns

2

1 / f_CLK

s

t_DR

Time for data ready

62.98046875 / f_DATA+ 468 / f_CLK

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8.4.3 Power-Down (PWDN Pin and STANDBY Command)

There are two ways to power-down the ADS1283: take the PWDN pin low, or send a STANDBY command.

When the PWDN pin is pulled low, the internal circuitry is disabled to minimize power and the contents of the

register settings are reset.

When in a power-down state, the device outputs remain active and the device inputs must not float. When the

STANDBY command is sent, the SPI port and the configuration registers are kept active. Figure 48 and Table 15

show the timing. Standby mode is cancelled when CS is taken high.

PWDN Pin

Wakeup

Command

DRDY

t_DR

Figure 48. PWDN Pin and Wake-Up Command Timing

(Table 15 shows t_DR

)

Table 15. Power-On, PWDN Pin, and Wake-Up Command Timing for New Data

PARAMETER

FILTER MODE

See Table 13

SINC⁽¹⁾

Time for data ready 2¹⁶CLK cycles after power-on;

and new data ready after PWDN pin or WAKEUP command

t_DR

62.98046875 / f_DATA+ 468 / f_CLK

FIR

(2)

(1) Supply power-on and PWDN pin default is 1000 SPS FIR.

(2) Subtract two CLK cycles for the WAKEUP command. The WAKEUP command is timed from the next rising edge of CLK to after the

eighth rising edge of SCLK during command to DRDY falling.

8.4.4 Power-On Sequence

The ADS1283 has three power supplies: AVDD, AVSS, and DVDD. Figure 49 shows the power-on sequence of

the ADS1283. The power supplies can be sequenced in any order. The supplies [the difference of (AVDD –

AVSS) and DVDD] generate signals that are ANDed together for the internal reset. After the supplies have

crossed the minimum thresholds, 2¹⁶f_CLKcycles are counted before releasing the internal reset. After the internal

reset is released, new conversion data are available, as shown in Figure 49 and Table 15.

3.5V nom

AVDD - AVSS

1V nom

DVDD

CLK

16

2

f_CLK

Internal Reset

DRDY

t_DR

Figure 49. Power-On Sequence

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8.4.5 DVDD Power Supply

The DVDD supply operates over the range of 1.65 V to 3.6 V. If operating DVDD at less than 2.25 V, connect the

DVDD pin to the BYPAS pin. Otherwise, do not connect these pins together. Figure 50 shows this connection.

1.65 V to 3.6 V

DVDD

1 µF

Connect DVDD to BYPAS if DVDD is < 2.25 V.

Otherwise, do not connect these pins together.

BYPAS

1 µF

Figure 50. DVDD Power

8.4.6 Serial Interface

A serial interface is used to read both the conversion data and to access the configuration registers. The

interface is SPI-compatible and consists of four signals: CS, SCLK, DIN, and DOUT. A minimum of 16 ADCs

converting at 4 kSPS can share a common serial bus when operating SCLK at 2 MHz.

8.4.6.1 Chip Select (CS)

Chip select (CS) is an active-low input that enables the ADC serial interface for data transfer. When CS is low,

the serial interface is enabled for communication. When CS is high, the serial interface is disabled. When the

serial interface is disabled, the DOUT (output data pin) is high impedance (tristate or Hi-Z). When CS is high,

SCLK activity is ignored, and data transfers or commands in progress are reset. CS must remain low for the

duration of the data transfer with the ADC. CS can be tied low, which permanently enables the ADC serial

interface. When CS goes high, the ADC idles (STANDBY) and stop read data continuous (SDATAC) modes are

cancelled. See the SDATAC Requirements section for more information about SDATAC mode.

8.4.6.2 Serial Clock (SCLK)

The serial clock (SCLK) is an input pin that is used to clock data into (DIN) and out of (DOUT) the ADC. SCLK is

a Schmitt-trigger input that has a high degree of noise immunity. However, keep SCLK as clean as possible to

prevent possible glitches from inadvertently shifting the data.

Data are shifted into DIN on the rising edge of SCLK and data are shifted out of DOUT on the falling edge of

SCLK. Keep SCLK low when not active. SCLK is ignored when CS is high.

8.4.6.3 Data Input (DIN)

The data input pin (DIN) is used to input register data and commands to the ADS1283. Keep DIN low when

reading conversion data in the read-data-continuous mode (except when issuing a SDATAC command). Data on

DIN are shifted into the converter on the rising edge of SCLK.

8.4.6.4 Data Output (DOUT)

The data output pin (DOUT) is used to output data from the ADS1283. Data are shifted out on the falling edge of

SCLK. When CS is high, the DOUT pin is in tristate.

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8.4.6.5 Serial Port Auto Timeout

The serial interface is reset each time CS is taken high. However, for applications that tie CS low, the serial port

cannot be reset by taking CS high; reset of the serial interface is no longer possible by using CS. The ADS1283

provides a feature that automatically recovers the interface when a transmission is stopped or interrupted, or if an

inadvertent glitch appears on SCLK. To reset the serial interface, hold SCLK low for 64 DRDY cycles. The reset

of the serial interface results in termination of data transfer or commands in progress. After serial port reset

occurs, the next SCLK pulse starts a new communication cycle. To prevent automatic reset from occurring, pulse

SCLK at least once for every 64 DRDY pulses.

8.4.6.6 Data Ready (DRDY)

DRDY is an output that is driven low when new conversion data are ready, as shown in Figure 51. When reading

data in continuous mode, the read operation must be completed before four CLK periods before the next falling

DRDY goes low again, or the data are overwritten with new conversion data. When reading data in command

mode, the read operation can overlap the occurrence of the next DRDY without data corruption.

DRDY

DOUT

SCLK

Bit 31

Bit 30

Bit 29

Figure 51. DRDY With Data Retrieval

DRDY resets high on the first falling edge of SCLK. Figure 51 and Figure 52 show the function of DRDY with and

without data readback, respectively.

If data are not retrieved (no SCLK provided), DRDY pulses high for four f_CLKperiods during the update time, as

shown in Figure 52.

DRDY remains active when CS is high.

Data Updating

4/f_CLK

DRDY

Figure 52. DRDY With No Data Retrieval

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8.4.7 Data Format

The ADS1283 output data is 32-bits in binary twos complement format, as shown in Table 16. The LSB of the

data is a redundant sign bit: 0 for positive numbers and 1 for negative numbers. However, when the output is

clipped to +FS, the LSB = 1, and when the output is clipped to –FS, the LSB = 0. If desired, the data readback

can be stopped at 24 bits. Note that in sinc-filter mode, the output data are scaled by ½.

Table 16. Ideal Output Code Versus Input Signal

32-BIT IDEAL OUTPUT CODE⁽¹⁾

INPUT SIGNAL V_IN

(AINP – AINN)

FIR FILTER

SINC FILTER⁽²⁾

V_REF

(3)

>

7FFFFFFFh

See note

2 x PGA

V_REF

2 x PGA

7FFFFFFEh

3FFFFFFFh

V_REF

2PGA ´ (2³⁰- 1)

00000002h

00000000h

FFFFFFFFh

00000001h

00000000h

FFFFFFFFh

0

-V_REF

2PGA ´ (2³⁰- 1)

2³⁰

-V_REF

´

80000001h

80000000h

C0000000h

2³⁰- 1

2PGA

2³⁰

-V_REF

(3)

<

´

See note

2³⁰- 1

2PGA

(1) Excludes effects of noise, linearity, offset, and gain errors.

(2) Due to the reduction in oversampling ratio (OSR) related to high data rates of the sinc filter, full resolution may not be available.

(3) In sinc-filter mode, the output does not clip at half-scale code when the full-scale range is exceeded.

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8.4.8 Reading Data

The ADS1283 provides two modes to read conversion data: read-data-continuous and read-data-by-command.

8.4.8.1 Read-Data-Continuous Mode

In the read-data-continuous mode, the conversion data are shifted out directly from the device without the need

for sending a read command. This mode is the default mode at power-on. This mode is also enabled by the

RDATAC command. When DRDY goes low, indicating that new data are available, the MSB of data appears on

DOUT, as shown in Figure 53. The data are normally read on the rising edge of SCLK, at the occurrence of the

first falling edge of SCLK, DRDY returns high. After 32 bits of data have been shifted out, further SCLK

transitions cause DOUT to go low. If desired, the read operation may be stopped at 24 bits. The data shift

operation must be completed within four CLK periods before DRDY falls again or the data may be corrupted.

When a SDATAC command is issued, the DRDY output is blocked but the ADS1283 continues conversions. In

stop continuous mode, the data can only be read by command.

CS⁽¹⁾

DRDY

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 25 26 27 28 29 30 31 32

SCLK

DOUT⁽²⁾

DIN

Data Byte 1 (MSB)

t_DDPD

Data Byte 2 (MSB - 1)

Data Byte 4 (LSB)

(1) DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to valid DOUT propagation time.

Figure 53. Read Data Continuous

Table 17. Timing Data for Figure 53

PARAMETER

MIN

TYP

MAX

UNIT

t_DDPD

DRDY to valid MSB on DOUT propagation delay⁽¹⁾

100

ns

(1) DOUT is in tristate when CS is high. Load on DOUT = 20 pF || 100 kΩ.

8.4.8.2 Read-Data-By-Command Mode

Read-data-continuous mode is stopped by the SDATAC command and put into read-data-by-command mode. In

read-data-by-command mode, an RDATA command must be sent to the device for each data conversion (as

shown in Figure 54). When the read data command is received (on the eighth SCLK rising edge), data are

available to read only when DRDY goes low (t_DR). When DRDY goes low, conversion data appear on DOUT. The

data may be read on the rising edge of SCLK.

CS⁽¹⁾

DRDY

t_DR

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 33 34 35 36 37 38 39 40

SCLK

DOUT⁽²⁾

DIN

Don't Care

Command Byte (0001 0010)

Data Byte 1 (MSB)

t_DDPD

Date Byte 4 (LSB)

(1) DOUT is in tristate when CS is high.CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.

Figure 54. Read Data By Command, RDATA (t_DDPDtiming is given in Table 17)

Table 18. Read Data Timing for Figure 54

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

t_DR

Time for new data after data read command

0

1

f_DATA

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8.4.9 One-Shot Operation

The ADS1283 can perform very power-efficient, one-shot conversions using the STANDBY command while

under software control. Figure 55 shows this sequence. First, issue the STANDBY command to set the standby

mode.

When ready to make a measurement, issue the WAKEUP command. When DRDY goes low, the fully-settled

conversion data are ready and can be read directly in read-data-continuous mode. Afterwards, issue another

STANDBY command. When ready for the next measurement, repeat the cycle starting with another WAKEUP

command.

ADC Status

Standby

Performing One-Shot Conversion

Standby

CS

DRDY

(1)

STANDBY

WAKEUP

DIN

STANDBY

DOUT

Settled

Data

See Figure 48 and Table 15 for time to new data.

Figure 55. One-Shot Conversions Using the STANDBY Command

8.4.10 Offset and Full-Scale Calibration Registers

The conversion data can be scaled for offset and gain before yielding the final output code. As shown in

Figure 56, the output of the digital filter is first subtracted by the offset register (OFC) and then multiplied by the

full-scale register (FSC). Equation 15 shows the scaling:

FSC[2:0]

Final Output Data = (Input - OFC[2:0]) ´

400000h

(15)

The values of the offset and full-scale registers are set by writing to them directly, or they are set automatically

by the calibration commands.

The offset and full-scale calibrations apply to specific PGA settings. When the PGA is changed, these registers

generally require recalculation. Calibration is bypassed in the sinc filter mode.

AINP

AINN

+

Output Data

Clipped to 32 Bits

Digital

Filter

´

Final Output

S

Modulator

-

OFC

Register

FSC Register

400000h

Figure 56. Calibration Block Diagram

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8.4.10.1 OFC[2:0] Registers

The 24-bit offset calibration word is composed of three 8-bit registers, as shown in Table 19. The offset register

is left-justified to align with the 32 bits of conversion data. The offset is in twos complement format with a

maximum positive value of 7FFFFFh and a maximum negative value of 800000h. This value is subtracted from

the conversion data. A register value of 00000h has no offset correction (default value).

Table 19. Offset Calibration Word

REGISTER

OFC0

BYTE

LSB

BIT ORDER

B7

B15

B6

B5

B4

B3

B2

B1

B9

B0 (LSB)

B8

OFC1

MID

B14

B22

B13

B21

B12

B20

B11

B19

B10

B18

OFC2

MSB

B23 (MSB)

B17

B16

Although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 20),

in order to avoid input overload, do not exceed the maximum input voltage range of 106% FSR (including

calibration).

Table 20. Offset Calibration Values

OFC REGISTER

7FFFFFh

FINAL OUTPUT CODE(1)

80000000h

000001h

FFFFFF00h

000000h

00000000h

FFFFFFh

800000h

00000100h

7FFFFF00h

(1) Full 32-bit final output code with zero code input.

8.4.10.2 FSC[2:0] Registers

The full-scale calibration is a 24-bit word, composed of three 8-bit registers, as shown in Table 21. The full-scale

calibration value is 24-bit, straight offset binary, normalized to 1.0 at code 400000h.

Table 21. Full-Scale Calibration Word

REGISTER

FSC0

BYTE

LSB

BIT ORDER

B7

B15

B6

B5

B4

B3

B2

B1

B9

B0 (LSB)

B8

FSC1

MID

B14

B22

B13

B21

B12

B20

B11

B19

B10

B18

FSC2

MSB

B23 (MSB)

B17

B16

Table 22 summarizes the scaling of the full-scale register. A register value of 400000h (default value) has no

gain correction (gain = 1). Although the full-scale calibration register value corrects gain errors above one (gain

correction < 1), the full-scale range of the analog inputs must not exceed 106% FSR (including calibration) in

order to avoid input overload.

Table 22. Full-Scale Calibration Register Values

FSC REGISTER

800000h

GAIN CORRECTION

2.0

1.0

0.5

0

400000h

200000h

000000h

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8.4.11 Calibration Commands (OFSCAL and GANCAL)

Use the calibration commands (OFSCAL or GANCAL) to calibrate the conversion data. The values of the offset

and gain calibration registers are internally written to perform calibration. The appropriate input signals must be

applied to the ADS1283 inputs before sending the commands. Use slower data rates to achieve more consistent

calibration results; this effect is a byproduct of the lower noise that these data rates provide. Also, if calibrating at

power-on, be sure the reference voltage is fully settled.

Figure 57 shows the calibration command sequence. After the analog input voltage (and reference) have

stabilized, send the SDATAC command, followed by the SYNC and RDATAC commands. DRDY goes low after

64 data periods. After DRDY goes low, send the SDATAC command, then the calibrate command (OFSCAL or

GANCAL), followed by the RDATAC command. After 16 data periods, calibration is complete and conversion

data can be read at this time. The SYNC input must remain high during the calibration sequence.

V_IN

Fully stable input and reference voltage.

OFSCAL or

Commands

SDATAC

SYNC

RDATAC

SDATAC

RDATAC

GANCAL

Calibration

Complete

16 Data

Periods

DRDY

SYNC

64 Data Periods

Figure 57. Offset and Gain Calibration Timing

The calibration commands apply to specific PGA settings. If the PGA is changed, recalibration is necessary.

Calibration is bypassed in the sinc filter mode.

8.4.11.1 OFSCAL Command

The OFSCAL command performs an offset calibration. Before sending the OFSCAL command sequence

(Figure 57), a zero input signal must be applied to the ADS1283 and the inputs allowed to stabilize. When the

command sequence (Figure 57) is sent, the ADS1283 averages 16 readings, and then writes this value to the

OFC register. The contents of the OFC register can be subsequently read or written. During offset calibration, the

full-scale correction is bypassed. Use the OFSCAL command to calibrate the optional 100-mV offset.

8.4.11.2 GANCAL Command

The GANCAL command performs a gain calibration. Before sending the GANCAL command sequence

(Figure 57), a dc input must be applied (typically full-scale input, but not to exceed 106% full-scale). After the

signal has stabilized, the command sequence can be sent. The ADS1283 averages 16 readings, then computes

a gain value that scales the applied calibration voltage to full-scale. The gain value is written to the FSC register,

where the contents are subsequently read or written.

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8.4.12 User Calibration

System calibration of the ADS1283 can be performed without using the calibration commands. This procedure

requires the calibration values to be externally calculated and then written to the calibration registers. The steps

for this procedure are:

1. Set the OFSCAL[2:0] register = 0h, and GANCAL[2:0] = 400000h. These values set the offset and gain

registers to 0 and 1, respectively.

2. Apply a zero differential input to the input of the system. Wait for the system to settle and then average the

output readings. Higher numbers of averaged readings result in more consistent calibration. Write the

averaged value to the OFC register.

3. Apply a differential dc signal, or an ac signal (typically full-scale, but do not exceed 106% FSR). Wait for the

system to settle and then average the output readings.

The value written to the FSC registers is calculated by Equation 16 or Equation 17.

DC-signal calibration is shown in Equation 16. The expected output code is based on 31-bit output data.

Expected Output Code

FSC[2:0] = 400000h ´

Actual Output Code

(16)

For ac-signal calibration, use an RMS value of collected data, as shown in Equation 17:

Expected RMS Value

FSC[2:0] = 400000h ´

Actual RMS Value

(17)

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8.5 Programming

8.5.1 Commands

The commands listed in Table 23 control the operation of the ADS1283. Most commands are stand-alone (that

is, one byte in length); the register read and write commands are two bytes long in addition to the actual register

data bytes.

Table 23. Command Descriptions

COMMAND

WAKEUP

STANDBY

SYNC

TYPE

Control

Data

DESCRIPTION

Wake-up from standby mode

1st COMMAND BYTE⁽¹⁾⁽²⁾

0000 000X (00h or 01h)

0000 001X (02h or 03h)

0000 010X (04h or 5h)

0000 011X (06h or 07h)

0001 0000 (10h)

2nd COMMAND BYTE⁽³⁾

Enter standby mode

Synchronize the analog-to-digital conversion

Reset registers to default values

Enter read data continuous mode

Stop read data continuous mode

Read data by command⁽⁴⁾

RESET

RDATAC

SDATAC

RDATA

0001 0001 (11h)

0001 0010 (12h)

RREG

Register

Read nnnnn register(s) at address rrrrr⁽⁴⁾

001r rrrr (20h + 000r rrrr)

010r rrrr (40h + 000r rrrr)

0110 0000 (60h)

000n nnnn (00h + n nnnn)

WREG

Write nnnnn register(s) at address rrrrr

OFSCAL

GANCAL

Calibration Offset calibration

Calibration Gain calibration

0110 0001 (61h)

(1) X = don't care.

(2) rrrrr = starting address for register read and write commands.

(3) nnnnn = number of registers to be read from or written to – 1. For example, to read from or write to three registers, set nnnnn = 2

(00010).

(4) Required to cancel read-data-continuous mode before sending a command.

CS must remain low for duration of the command-byte sequence. A delay of 24 f_CLKcycles between commands

and between bytes within a command is required, starting from the last SCLK rising edge of one command to the

first SCLK rising edge of the following command. The required delay is shown in Figure 58.

CS

Command

Byte

Command

Byte

DIN

SCLK

(1)

t_SCLKDLY

(1) t_SCLKDLY= 24 / f_CLK(min).

Figure 58. Consecutive Commands

8.5.1.1 SDATAC Requirements

In read-data-continuous mode, the ADS1283 places conversion data on the DOUT pin as SCLK is applied. As a

result of the potential conflict between conversion data and register data placed on DOUT resulting from a RREG

or RDATA operation, it is necessary to send a stop-read-data-continuous (SDATAC) command before a RREG

or RDATA command. The SDATAC command disables the direct output of conversion data on the DOUT pin.

CS = 1 cancels SDATAC mode; therefore, keep CS held low after sending the SDATAC command to the next

RREG or RDATA command.

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8.5.1.2 WAKEUP: Wake-Up From Standby Mode

The WAKEUP command is used to exit the standby mode. After sending this command, the time for the first data

to be ready is illustrated in Figure 48 and Table 16. Sending this command during normal operation has no

effect; for example, reading data by the read-data-continuous mode with DIN held low.

8.5.1.3 STANDBY: Standby Mode

The STANDBY command places the ADS1283 into standby mode. In standby, the device enters a reduced

power state where a low quiescent current remains to keep the register settings and serial interface active. The

ADC remains in standby mode until CS is taken high or the WAKEUP command is sent. For complete device

shutdown, take the PWDN pin low (register settings are not saved). The operation of standby mode is shown in

Figure 59.

0000 001X

(STANDBY)

0000 000X

(WAKEUP)

DIN

SCLK

Operating

Standby Mode

Operating

Figure 59. STANDBY Command Sequence

8.5.1.4 SYNC: Synchronize the Analog-to-Digital Conversion

The SYNC command synchronizes the analog-to-digital conversion. Upon receiving the command, the reading in

progress is cancelled and the conversion process is restarted. In order to synchronize multiple ADS1283s, the

command must be sent simultaneously to all devices. The SYNC pin must be held high during this command.

8.5.1.5 RESET: Reset the Device

The RESET command resets the registers to default values, enables read-data-continuous mode, and restarts

the conversion process. The RESET command is functionally equivalent to taking the RESET pin low. See

Figure 47 for the RESET command timing.

8.5.1.6 RDATAC: Read Data Continuous

The RDATAC command enables read-data-continuous mode (default mode). In this mode, conversion data is

read from the device directly without the need to supply a data read command. Each time DRDY falls low, new

data are available to read. See the Read-Data-Continuous Mode section for more details.

8.5.1.7 SDATAC: Stop Read Data Continuous

The SDATAC command stops read-data-continuous mode. Exit read-data-continuous mode before sending

register and data read commands. The SDATAC command suppresses the DRDY output, but the ADS1283

continues conversions. Take CS high to cancel SDATAC mode.

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8.5.1.8 RDATA: Read Data by Command

The RDATA command reads the conversion data. See the Read-Data-By-Command Mode section for more

details.

8.5.1.9 RREG: Read Register Data

The RREG command is used to read single- or multiple-register data. The command consists of a two-byte

opcode argument, followed by the output of register data. The first byte of the opcode includes the starting

address, and the second byte specifies the number of registers to read minus one.

First command byte: 001r rrrr, where rrrrr is the starting address of the first register.

Second command byte: 000n nnnn, where nnnnn is the number of registers to read minus one.

Starting with the 16th falling edge of SCLK, the register data appear on DOUT. Read the data on the 17th SCLK

rising edge.

The RREG command is illustrated in Figure 60.

A delay of 24 f_CLKcycles is required between each byte transaction.

CS⁽¹⁾

t_DLY

25 26

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

SCLK

DIN

Command Byte 1

Command Byte 2

DOUT⁽²⁾

Don't Care

Register Data 5

Register Data 6

Example: Read six registers, starting at register 05h (OFC0)

Command Byte 1 = 0010 0101

Command Byte 2 = 0000 0101

(1) DOUT is in tristate when CS is high. CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.

Figure 60. Read Register Data (Table 24 shows t_DLY

)

Table 24. t_DRYValue

PARAMETER

MIN

t_DLY

24 / f_CLK

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8.5.1.10 WREG: Write to Register

The WREG command writes single- or multiple-register data. The command consists of a two-byte op-code

argument followed by the input of register data. The first byte of the op-code contains the starting address and

the second byte specifies the number of registers to write minus one.

First command byte: 010r rrrr, where rrrrr is the starting address of the first register.

Second command byte: 000n nnnn, where nnnnn is the number of registers to write minus one.

Data byte(s): one or more register data bytes, depending on the number of registers specified.

Figure 61 illustrates the WREG command.

A delay of 24 f_CLKcycles is required between each byte transaction.

CS⁽¹⁾

t_DLY

25 26

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

SCLK

DIN

Register Data 6

Command Byte 1

Command Byte 2

Register Data 5

Example: Write six registers, starting at register 05h (OFC0)

Command Byte 1 = 0100 0101

Command Byte 2 = 0000 0101

(1) CS can be tied low. See Figure 1 for CS low to SCLK rising edge time.

Figure 61. Write Register Data (Table 24 shows t_DLY

)

8.5.1.11 OFSCAL: Offset Calibration

The OFSCAL command performs an offset calibration. The inputs to the converter (or the inputs to the external

preamplifier) should be zeroed and allowed to stabilize before sending this command. The offset calibration

register updates after this operation. See the Calibration Commands section for more details.

8.5.1.12 GANCAL: Gain Calibration

The GANCAL command performs a gain calibration. The inputs to the converter should have a stable dc input

(typically full-scale, but not to exceed 106% full-scale). The gain calibration register updates after this operation.

See the Calibration Commands section for more details.

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8.6 Register Maps

Collectively, the registers contain all the information needed to configure the device, such as data rate, filter

selection, calibration, and more. The registers are accessed by the RREG and WREG commands. The registers

can be accessed individually or as a block of registers by sending or receiving consecutive bytes. After a register

write operation, the ADC resets, resulting in an interruption of 63 readings.

Table 25. Register Map

RESET

ADDRESS

00h

REGISTER

ID_CFG

CONFIG0

CONFIG1

HPF0

VALUE

X0h

52h

08h

32h

03h

00h

40h

BIT 7

ID3

BIT 6

ID2

BIT 5

ID1

BIT 4

ID0

BIT 3

0

BIT 2

0

BIT 1

OFFSET1

FILTR1

PGA1

BIT 0

OFFSET0

FILTR0

PGA0

01h

SYNC

0

1

DR2

DR1

DR0

PHASE

PGA2

HPF02

HPF10

OFC02

OFC10

OFC18

FSC02

FSC10

FSC18

02h

MUX2

HPF06

HPF14

OFC06

OFC14

OFC22

FSC06

FSC14

FSC22

MUX1

HPF05

HPF13

OFC05

OFC13

OFC21

FSC05

FSC13

FSC21

MUX0

HPF04

HPF12

OFC04

OFC12

OFC20

FSC04

FSC12

FSC20

CHOP

HPF03

HPF11

OFC03

OFC11

OFC19

FSC03

FSC11

FSC19

03h

HPF07

HPF15

OFC07

OFC15

OFC23

FSC07

FSC15

FSC23

HPF01

HPF09

OFC01

OFC09

OFC17

FSC01

FSC09

FSC17

HPF00

HPF08

OFC00

OFC08

OFC16

FSC00

FSC08

FSC16

04h

HPF1

05h

OFC0

06h

OFC1

07h

OFC2

08h

FSC0

09h

FSC1

0Ah

FSC2

8.6.1 Register Descriptions

8.6.1.1 ID_CFG: ID_Configuration Register (address = 00h) [reset =x0h]

Figure 62. ID_CFG Register

7

6

5

4

3

0

2

0

1

0

ID3

R-xh

ID2

R-xh

ID1

R-xh

ID0

R-xh

OFFSET1

R/W-0h

OFFSET0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit[7:4]

ID[3:0]

Factory-programmed identification bits (read-only). The ID bits are subject to change

without notification.

Bit[3:2]

Bit[1:0]

Reserved

Always write 00

OFFSET[1:0] (see Offset section)

00: Disables offset (default)

01: Reserved

10: Offset = 100/PGA mV (all ADS1283 versions)

11: Offset = 75/PGA mV (ADS1283B only)

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8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]

Figure 63. CONFIG0 Register

7

6

1

5

4

3

2

1

0

SYNC

R/W-0h

DR2

DR1

DR0

PHASE

R/W-0h

FILTR1

R/W -1h

FILTR0

R/W-0h

R/W-1h

R/W-0h

R/W-1h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit[7]

SYNC

Synchronization mode bit.

0: Pulse-sync mode (default)

1: Continuous-sync mode

Bit[6]

RESERVED

Always write 1

DR[2:0]

Bit[5:3]

Data rate select bits.

000: 250 SPS

001: 500 SPS

010: 1000 SPS (default)

011: 2000 SPS

100: 4000 SPS

Bit[2]

PHASE

FIR phase response bit.

0: Linear phase (default)

1: Minimum phase

Bit[1:0]

FILTR[1:0]

Digital filter configuration bits.

00: Reserved

01: Sinc filter block only

10: Sinc + LPF filter blocks (default)

11: Sinc + LPF + HPF filter blocks

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8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]

Figure 64. CONFIG1 Register

7

0

6

5

4

3

2

1

0

MUX2

R/W-0h

MUX1

R/W-0h

MUX0

R/W-0h

CHOP

R/W-1h

PGA2

R/W-0h

PGA1

R/W-0h

PGA0

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit[7]

Reserved

Always write 0

MUX[2:0]

Bit[6:4]

MUX select bits.

000: AINP1 and AINN1 (default)

001: AINP2 and AINN2

010: Internal short through 400-Ω resistor

011: AINP1 and AINN1 connected to AINP2 and AINN2

100: External short to AINN2

Bit[3]

CHOP

PGA chopping enable bit.

0: PGA chopping disabled

1: PGA chopping enabled (default)

Bit[2:0]

PGA[2:0]

PGA gain select bits. Note that ADS1283A supports PGA gains of 1, 4, and 16 only.

000: G = 1 (default)

001: G = 2 (ADS1283 and ADS1283B only)

010: G = 4

011: G = 8 (ADS1283 and ADS1283B only)

100: G = 16

101: G = 32 (ADS1283 and ADS1283B only)

110: G = 64 (ADS1283 and ADS1283B only)

8.6.1.4 HPF0 and HPF1 Registers

These two bytes (high-byte and low-byte, respectively) set the corner frequency of the high-pass filter.

8.6.1.4.1 HPF0: High-Pass Filter Corner Frequency, Low Byte (address = 03h) [reset = 32h]

Figure 65. HPF0 Register

7

6

5

4

3

2

1

0

HPF07

R/W-0h

HPF06

R/W-0h

HPF05

R/W-1h

HPF04

R/W-1h

HPF03

R/W-0h

HPF02

R/W-0h

HPF01

R/W-1h

HPF00

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.4.2 HPF1: High-Pass Filter Corner Frequency, High Byte (address = 04h) [reset = 03h]

Figure 66. HPF1 Register

7

6

5

4

3

2

1

0

HPF15

R/W-0h

HPF14

R/W-0h

HPF13

R/W-0h

HPF12

R/W-0h

HPF11

R/W-0h

HPF10

R/W-0h

HPF09

R/W-1h

HPF08

1R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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8.6.1.5 OFC0, OFC1, OFC2 Registers

These three bytes set the offset calibration value.

8.6.1.5.1 OFC0: Offset Calibration, Low Byte (address = 05h) [reset = 00h]

Figure 67. OFC0 Register

7

6

5

4

3

2

1

0

OFC07

R/W-0h

OFC06

R/W-0h

OFC05

R/W-0h

OFC04

R/W-0h

OFC03

R/W-0h

OFC02

R/W-0h

OFC01

R/W-0h

OFC00

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.5.2 OFC1: Offset Calibration, Mid Byte (address = 06h) [reset = 00h]

Figure 68. OFC1 Register

7

6

5

4

3

2

1

0

OFC15

R/W-0h

OFC14

R/W-0h

OFC13

R/W-0h

OFC12

R/W-0h

OFC11

R/W-0h

OFC10

R/W-0h

OFC09

R/W-0h

OFC08

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.5.3 OFC2: Offset Calibration, High Byte (address = 07h) [reset = 00h]

Figure 69. OFC2 Register

7

6

5

4

3

2

1

0

OFC23

R/W-0h

OFC22

R/W-0h

OFC21

R/W-0h

OFC20

R/W-0h

OFC19

R/W-0h

OFC18

R/W-0h

OFC17

R/W-0h

OFC16

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.6 FSC0, FSC1, FSC2 Registers

These three bytes set the full-scale calibration value.

8.6.1.6.1 FSC0: Full-Scale Calibration, Low Byte (address = 08h) [reset = 00h]

Figure 70. FSC0 Register

7

6

5

4

3

2

1

0

FSC07

R/W-0h

FSC06

R/W-0h

FSC05

R/W-0h

FSC04

R/W-0h

FSC03

R/W-0h

FSC02

R/W-0h

FSC01

R/W-0h

FSC00

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.6.2 FSC1: Full-Scale Calibration, Mid Byte (address = 09h) [reset = 00h]

Figure 71. FSC1 Register

7

6

5

4

3

2

1

0

FSC15

R/W-0h

FSC14

R/W-0h

FSC13

R/W-0h

FSC12

R/W-0h

FSC11

R/W-0h

FSC10

R/W-0h

FSC09

R/W-0h

FSC08

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

8.6.1.6.3 FSC2: Full-Scale Calibration, High Byte (address = 0Ah) [reset = 40h]

Figure 72. FSC2 Register

7

6

5

4

3

2

1

0

FSC23

R/W-0h

FSC22

R/W-1h

FSC21

R/W-0h

FSC20

R/W-0h

FSC19

R/W-0h

FSC18

R/W-0h

FSC17

R/W-0h

FSC16

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The ADS1283 is a very high-resolution ADC. Optimal performance requires giving special attention to the

support circuitry and printed circuit board (PCB) design. Locate noisy digital components (such as

microcontrollers, oscillators, and so on) in an area of the PCB away from the converter and front-end

components. Keep the digital current path short and separate from sensitive analog components by placing the

digital components close to the power-entry point.

9.2 Typical Applications

9.2.1 Geophone Interface

A typical geophone front-end application is shown in Figure 73. The application diagram shows the ADS1283

operation with dual ±2.5-V analog supplies. The ADS1283 can also operate with a single 5-V analog supply.

+2.5V

-

2.5V

1 mF

AVDD

AVSS

AINP2

AINN2

Test

Signal

+2.5V

(1)

R₁

R₃

100 Ω

AINP1

AINN1

C₂

R₅

C₄

10nF

C0G

1 nF, C0G

20 kΩ

Geophone

R₆

R₂

R₄

C₃

20 kΩ 100 Ω

100 Ω

1 nF, C0G

ADC

-2.5V

CAPP

CAPN

C₆

10 nF

C0G

+3.3V

R₇

1 kΩ

(2)

1 mF

VREFP

VREFN

REF5050

+

NR

C₅

100 mF

C₇

0.1 mF

1 mF

DGND

-

2.5V

(1) Optional external diode clamps.

(2) Optional reference noise filter.

Figure 73. Geophone Interface Application

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Typical Applications (continued)

The geophone input signal is filtered by both a differential filter (components C₄and R₁to R₄) and by common-

mode filters (components C₂, C₃and R₁, R₂). The differential filter removes high-frequency normal-mode

components from the input signal. The common-mode filters remove high-frequency components that are

common to both input leads. The input filters are not required for all applications; check the system requirements

for each application.

Resistors R₅and R₆bias the signal input to the midsupply point (ground). For single-supply operation, set the

bias to a low impedance midsupply point (AVDD / 2 = 2.5 V).

Optional diode clamps protect the ADS1283 inputs from high-level voltage transients and overloads. The diodes

provide additional protection if possible high-level input transients and surges exceed the ADC internal ESD

diode rating.

The REF5050 5-V reference provides the reference to the ADC. An optional filter network (R₇and C₅) reduces

the in-band reference noise for improved dynamic performance. However, the RC filter network increases the

filter settling-time (from seconds to possibly minutes) depending on the dielectric absorption properties of

capacitor C₅. Capacitor C₇is mandatory and provides high-frequency bypassing of the reference inputs; place C₇

as close as possible to the ADS1283 pins. Resistor R₇(1 kΩ) results in a 1% systematic gain error. Multiple

ADCs can share a single reference, but if shared, use independent reference filters for each ADC.

As an alternative, the REF5045 (4.5 V) reference can be used. The REF5045 reference has the advantage of

operating directly from the 5-V (total) power supply; however, the 4.5-V reference reduces signal range by 10%

and results in a 1-dB loss of SNR.

Capacitor C₆(10 nF) filters the PGA output glitches caused by sampling of the modulator. This capacitor also

forms an antialias filter with a low-pass cutoff frequency of 26 kHz.

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Typical Applications (continued)

9.2.2 Digital Interface

Figure 74 shows the digital connection to a controller (field programmable gate array or microcontroller). In this

example, two ADCs are shown connected to one controller. The ADCs share the same serial interface (SCLK,

DIN, and DOUT). The ADC is selected for communication by strobing each CS low. The DRDY output from both

ADCs can be used; however, when the devices are synchronized, the DRDY output from only one device is

sufficient.

Clock

ADC #1

Controller

47 Ω

(1)

+3.3V

DVDD

CLK

CLK (input)

47 Ω

RESET (output)

1 µF

RESET

SYNC

SYNC (output)

SS1 (output)

47 Ω

BYPAS

CS

SCLK (output)

SCLK

DIN

DOUT

MOSI (output)

MISO (input)

47 Ω

MFLAG

MFLAG1 (input)

MFLAG2 (input)

DGND

ADC #2

47 Ω

SS2 (output)

DRDY (input)

(1)

DVDD

CLK

RESET

SYNC

+3.3V

1 µF

BYPAS

CS

SCLK

DIN

DOUT

MFLAG

DRDY

DGND

(1) For DVDD < 2.25 V, tie DVDD and BYPASS together. see the DVDD Power Supply section.

Figure 74. Controller Interface with Dual ADCs

The modulator overrange flag (MFLAG) from each device ties to the controller input. For synchronization,

connect all ADCs to the same SYNC signal. For reset, either connect all ADCs to the same RESET signal or

connect the ADCs to individual RESET signals.

Avoid ringing on the digital inputs to the ADCs. Place 47-Ω resistors in series with the digital traces to help

reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Do not float

unused digital inputs; tie them to DVDD or GND.

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9.3 Initialization Set Up

After reset or power-on, configure the registers using the following procedure:

1. Reset the serial interface. Before using the serial interface, it may be necessary to recover the serial

interface (undefined I/O power-up sequencing may cause a false SCLK to occur). To reset the interface,

toggle the CS pin high then low, or toggle the RESET pin high then low, or when in read-data-continuous

mode, hold SCLK low for 64 DRDY periods.

2. Configure the registers. The registers are configured by either writing to them individually or as a group,

and can be configured in either mode. To cancel read-data-continuous mode, send the SDATAC command

before register read and write operations .

3. Verify register data. For verification of device communications, read back the register.

4. Set the data mode. After register configuration, configure the device for read-data-continuous mode by

executing the RDATAC command, or configure for read-data-by-command mode (set in step 2, by the

SDATAC command).

5. Synchronize readings. Whenever SYNC is high, the ADS1283 freely runs the data conversions. To

resynchronize the conversions in pulse-sync mode, take SYNC low and then high. In continuous-sync mode,

apply the synchronizing clock to the SYNC pin with a clock period equal to multiples of the ADC conversion

period.

6. Read data. If read-data-continuous mode is active, the data are read directly after DRDY falls by applying

SCLK pulses. If the read-data-continuous mode is inactive, the data can only be read by executing the

RDATA command. The RDATA command must be sent in this mode to read each conversion result.

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10 器件和文档支持

10.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

10.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

10.3 商标

E2E is a trademark of Texas Instruments.

SPI is a trademark of Motorola Inc.

All other trademarks are the property of their respective owners.

10.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

10.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

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11 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

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60

PACKAGE OUTLINE

RHF0024A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

A

B

PIN 1 INDEX AREA

0.5

0.3

5.1

4.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.65 0.1

2X 2

(0.1) TYP

12

EXPOSED

8

THERMAL PAD

20X 0.5

7

13

3.65 0.1

2X

3

25

SYMM

SEE TERMINAL

DETAIL

19

1

0.30

0.18

24X

0.1

C B A

PIN 1 ID

(OPTIONAL)

24

20

SYMM

0.05

0.5

0.3

24X

4219064 /A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.65)

SYMM

20

24

24X (0.6)

1

19

24X (0.24)

(3.65)

(1.575)

20X (0.5)

25

SYMM

(4.8)

(0.62)

TYP

(R0.05)

TYP

13

7

(

0.2) TYP

VIA

8

12

(1.025)

TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219064 /A 04/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6X (1.17)

(0.685) TYP

20

24

24X (0.6)

1

19

24X (0.24)

(1.24)

TYP

20X (0.5)

SYMM

(4.8)

25

6X (1.04)

13

(R0.05) TYP

7

METAL

TYP

12

8

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219064 /A 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS1283AIRHFR
厂家：	TEXAS INSTRUMENTS
描述：	用于地震监测和能源勘探且具有 PGA 的超高分辨率 4kSPS 2 通道 Δ-Σ ADC \| RHF \| 24 \| -40 to 85 转换器
文件：	总68页 (文件大小：2237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1283AIRHFR [TI]

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