ADS1285IRHBR [TI]
用于地震探测和地球空间探测的 32 位高分辨率双通道 Δ-Σ ADC | RHB | 32 | -40 to 85;
| 型号： | ADS1285IRHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于地震探测和地球空间探测的 32 位高分辨率双通道 Δ-Σ ADC | RHB | 32 | -40 to 85 |
| 文件： | 总63页 (文件大小：2348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1285
ZHCSQZ8A –MAY 2022 –REVISED DECEMBER 2022
ADS1285 适用于地震应用的32 位Δ-Σ ADC
1 特性
3 说明
• 可选择分辨率-功率模式：
ADS1285 是一款 32 位低功耗模数转换器 (ADC)，具
有一个可编程增益放大器 (PGA) 和一个有限脉冲响应
(FIR) 滤波器。该 ADC 可满足地震监测设备的低噪声
精密数字化和更长电池运行时间的严苛要求。
– 动态范围：在2ms、11.5mW 下为134dB
– 动态范围：在2ms、4.8mW 下为129dB
• 灵活的数字滤波器：
– 可选的正弦+ FIR + IIR
– 线性或最小相位
– 高通滤波器
低噪声 PGA 允许直接连接地震检波器和变压器耦合水
听器，无需外部放大器。
该 ADC 包含一个高分辨率 Δ-Σ 调制器和一个具有可
编程相位响应的 FIR 滤波器。高通滤波器可从信号中
移除直流和低频成分。时钟频率误差由分辨率为 7ppb
的采样率转换器进行补偿。
• THD：< -120dB
• CMRR：125dB
• 数据速率：125SPS 至4000SPS
• 可编程增益：1 至64
• PGA 旁路选项
• SYNC 输入
• 时钟误差补偿
通过选择功率模式可优化动态范围和功耗。PGA 旁路
运行可进一步降低功耗。
该ADC 采用紧凑的 5mm × 5mm VQFN 封装，额定工
作状态下的环境温度范围为–40°C 至+85°C。
• 双通道多路转接器
• 偏移和增益校准
封装信息(1)
• 通用数字I/O
• 模拟电源供电：5V、3.3V 或±2.5V
• 基准电压选项：5V、4.096V 或2.5V
封装尺寸（标称值）
器件型号
ADS1285
封装
RHB（VQFN，32） 5.00mm × 5.00mm
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
• 能量勘探
• 无源地震监测
• 地球科学和地质学
• 精密仪表
IOVDD
AVDD1
AVDD2
CLK
ADS1285
DRDY
AIN1P
AIN1N
CS
Serial
Interface
Sample
Rate
Converter
SCLK
DOUT
DIN
Digital
Filter
PGA
BUF
MUX
Modulator
AIN2P
AIN2N
PWDN
RESET
SYNC
Control
Noise/Offset
Test
AVSS
REFN
GPIO0
GND
AGND
REFP
GPIO1
功能方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS559
ADS1285
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ZHCSQZ8A –MAY 2022 –REVISED DECEMBER 2022
Table of Contents
8.1 Overview...................................................................26
8.2 Functional Block Diagram.........................................27
8.3 Feature Description...................................................28
8.4 Device Functional Modes..........................................41
8.5 Programming............................................................ 46
8.6 Register Map.............................................................51
9 Application and Implementation..................................56
9.1 Application Information............................................. 56
9.2 Typical Application.................................................... 56
9.3 Power Supply Recommendations.............................58
9.4 Layout....................................................................... 59
10 Device and Documentation Support..........................60
10.1 接收文档更新通知................................................... 60
10.2 支持资源..................................................................60
10.3 Trademarks.............................................................60
10.4 Electrostatic Discharge Caution..............................60
10.5 术语表..................................................................... 60
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements: 1.65 V ≤IOVDD ≤1.95
V and 2.7 V ≤IOVDD ≤3.6 V...................................10
6.7 Switching Characteristics: 1.65V ≤IOVDD ≤
1.95V and 2.7 V ≤IOVDD ≤3.6 V............................10
6.8 Timing Diagrams....................................................... 11
6.9 Typical Characteristics..............................................13
7 Parameter Measurement Information..........................24
7.1 Noise Performance................................................... 24
8 Detailed Description......................................................26
Information.................................................................... 60
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2022) to Revision A (December 2022)
Page
• 首次公开发布，将文档状态从预告信息更改为量产数据................................................................................... 1
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5 Pin Configuration and Functions
AIN1P
AIN1N
AIN2P
AIN2N
CAPP
1
24
23
22
21
20
19
18
17
DOUT
DIN
2
3
4
5
6
7
8
SCLK
CS
Thermal pad
CLK
CAPN
IOVDD
DGND
CAPD
CAPBP
CAPBN
Not to scale
图5-1. RHB Package, 32-Pin, 5-mm × 5-mm VQFN (Top View)
表5-1. Pin Functions
PIN
NAME
FUNCTION
DESCRIPTION
NO.
1
AIN1P
AIN1N
AIN2P
AIN2N
CAPP
CAPN
CAPBP
CAPBN
CAPC
AVSS
AVDD1
AVDD2
AGND
CAPI
Analog input
Analog input
Analog input
Analog input
Analog internal
Analog internal
Analog internal
Analog internal
Analog internal
Analog supply
Analog supply
Analog supply
Analog ground
Analog internal
Digital I/O
Channel 1 positive input
2
Channel 1 negative input
3
Channel 2 positive input
4
Channel 2 negative input
5
PGA positive capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN.
PGA negative capacitor. Connect a 10-nF C0G capacitor across CAPP and CAPN.
Buffer positive capacitor. Connect a 47-nF C0G capacitor to AVSS.
Buffer negative capacitor. Connect a 47-nF C0G capacitor to AVSS.
Charge-pump capacitor. Connect a 4.7-nF, minimum 10-V rated capacitor to AGND.
PGA negative analog supply. See the Analog Power Supplies section for details.
PGA positive analog supply. See the Analog Power Supplies section for details.
Modulator analog supply. See the Analog Power Supplies section for details.
Analog ground
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Input bias capacitor. Connect a 100-nF ceramic capacitor to AGND.
General-purpose I/O
GPIO0
GPIO1
CAPD
DGND
IOVDD
CLK
Digital I/O
General-purpose I/O
Analog output
Ground
Digital low-dropout regulator (LDO) output. Connect a 220-nF ceramic capacitor to DGND.
Digital ground
Digital supply
Digital input
Digital I/O power supply. See the IOVDD Power Supply section for details.
ADC clock input
CS
Digital input
Serial interface select, active low
SCLK
DIN
Digital input
Serial interface clock
Digital input
Serial interface data in
DOUT
DRDY
SYNC
RESET
PWDN
REFN
REFP
CAPR
AVSS
Digital output
Digital output
Digital input
Serial interface data out
Data ready, active low
ADC synchronization, active high
Digital input
ADC reset, active low
Digital input
ADC power down, active low
Analog input
Analog input
Analog internal
Analog supply
Negative reference input. See the Voltage Reference Input section for details.
Positive reference input. See the Voltage Reference Input section for details.
Reference bias capacitor. Connect a 100-nF ceramic capacitor to AVSS.
PGA negative supply
Connect the thermal pad to AVSS. Thermal vias placed in the printed circuit board (PCB) land are optional for placement of bottom
side components.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
UNIT
AVDD1 to AVSS
AVSS to AGND
5.5
0.3
–2.8
AVDD2 to AGND
Power supply voltages
5.5
–0.3
V
AVDD2 to AVSS
5.5
–0.3
IOVDD to DGND
3.9
–0.3
IOVDD to DGND (IOVDD connected to CAPD)
2.2
0.3
–0.3
Grounds
AGND to DGND
V
V
–0.3
Analog input voltage
Digital input voltage
Input current
AIN1P, AIN1N, AIN2P, AIN2N, REFP, REFN
CLK, DIN, SCLK, CS, GPIO0, GPIO1, SYNC, RESET, PWDN
Continuous, any digital or analog pin (2)
Junction, TJ
AVDD1 + 0.3
IOVDD + 0.3
10
AVSS –0.3
DGND –0.3
–10
V
mA
°C
°C
150
Temperature
Storage, Tstg
150
–60
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional –this may affect device reliability, functionality, performance, and shorten the device
lifetime.
(2) Analog input pins AIN1P, AIN1N, AIN2P, AIN2N, REFP and REFN are diode-clamped to AVDD1 and AVSS. Limit the input current to
10 mA in the event the analog input voltage exceeds AVDD1 + 0.3 V or AVSS –0.3 V. Digital input pins are clamped to IOVDD and
DGND. Limit the input current if the digital input voltage exceeds IOVDD + 0.3 V or DGND –0.3 V.
6.2 ESD Ratings
VALUE
2000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
AVDD1 to AVSS
3
2.375
5.25
V
AVDD1 to AGND
AVSS to AGND
Analog power supplies
0
5.25
5.25
3.6
–2.625
2.375
V
V
AVDD2 to AGND
AVDD2 to AVSS
IOVDD to DGND
IOVDD connected to CAPD
2.7
Digital power supply
ANALOG INPUTS
1.65
1.95
Reference voltage = 5 V
Reference voltage = 4.096 V
Reference voltage = 2.5 V
Buffer operation
±VREF / (2 × Gain)
±VREF / (1.6384 × Gain)
±VREF / Gain
Differential input voltage
VIN = VAINP –VAINN
VIN
V
V
AVSS + 0.1
AVSS + 1.1
AVDD1 –0.1
AVDD1 –0.85
Absolute input voltage
PGA operation
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6.3 Recommended Operating Conditions (continued)
over operating ambient temperature range (unless otherwise noted)
MIN
AVSS + 0.1
AVSS + 0.15
NOM
MAX
AVDD1 –0.1
AVDD1 –0.15
6%
UNIT
V
Buffer operation
Absolute output voltage
PGA operation
Calibration range (1)
FSR
VOLTAGE REFERENCE INPUT
VREFN
VREFP
Negative reference input
Positive reference input
V
V
V
V
V
AVSS –0.05
AVDD1 + 0.1
Reference voltage = 5 V
Reference voltage = 4.096 V
Reference voltage = 2.5 V
4.9
4.0
2.4
5
4.096
2.5
AVDD1 –AVSS + 0.1
VREF
VREF = VREFP –VREFN
4.2
2.6
DIGITAL INPUTS
VINL
VINH
Low-level input voltage
0.2 × IOVDD
V
V
High-level input voltage
0.8 × IOVDD
High-power mode
Mid-power mode
Low-power mode
6
6
3
8.192
8.192
4.096
8.3
8.3
fCLK
Clock input frequency
MHz
4.15
TEMPERATURE
TA Ambient temperature
Operational
Specification
85
85
–50
–40
°C
(1) Calibration range is the sum of the offset and gain error correction.
6.4 Thermal Information
ADS1285
THERMAL METRIC(1)
RHB (VQFN)
32 PINS
30
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.4
10.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJT
10.8
ψJB
RθJC(bot)
1.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1,
fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted)
PARAMETER
ANALOG INPUTS
Input mux on-resistance
PGA OPERATION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input 1 to input 2 cross connection
60
Ω
IB
PGA Input bias current
PGA Input offset current
PGA Gain
High-power mode
High-power mode
45
±3
nA
nA
IOS
1, 2, 4, 8, 16, 32, 64
V/V
High-power mode
5.5
7
en-PGA
PGA Input voltage noise density Mid-power mode
Low-power mode
PGA Gain = 16
nV/√Hz
7
in-PGA
PGA Input current noise density Differential
Antialias filter frequency
2.5
30
pA/√Hz
kHz
BUFFER OPERATION
High-power mode
Mid-power mode
Low-power mode
±1.2
±1.2
±0.3
IB
Input current
VIN = 2.5 V
µA
DC PERFORMANCE
en
Noise
See Noise Performance section for details
PGA operation
Buffer operation
After calibration
PGA operation
Buffer operation
±30/gain + 5
350/gain + 10
600
–350/gain - 10
–600
VOS
Offset error
µV
±50
±1
0.5/gain
1
Offset error drift
Gain error
µV/°C
ppm
PGA operation, gain = 1
After calibration
Buffer operation
Relative to PGA gain = 1
All PGA gains
±0.02%
2
0.05%
–0.05%
±0.05%
±0.06%
2
0.07%
0.2%
–0.07%
–0.2%
Gain match
Gain drift
ppm/°C
dB
CMRR
PSRR
Common-mode rejection ratio
f = 60 Hz
104
80
120
AVDD2
95
dB
Power-supply rejection ratio
AVSS, AVDD1
IOVDD
At dc
85
110
dB
100
120
dB
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6.5 Electrical Characteristics (continued)
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1,
fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
en-MOD
Modulator voltage noise density VREF = 4.096 V
25
–123
–119
–125
–124
–123
–125
–122
–120
–125
–124
–123
–125
–124
–122
–124
–125
–123
–124
–119
–119
–125
–122
–118
–117
–125
–119
–119
–125
–124
–119
–117
–124
–123
–121
–124
–125
–122
–121
–123
115
nV/√Hz
Buffer operation
PGA gain = 2
-114
-116
-116
-113
-118
-115
-117
-116
-115
High-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS
PGA gain = 4
dB
dB
dB
PGA gain = 8
PGA gain = 16
PGA gain = 32 and 64
Buffer operation
PGA gain = 2
Mid-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 32 and 64
Buffer operation
PGA gain = 2
Low-power mode,
VREF = 2.5 V,
AVDD1 = 3.3 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS
PGA gain = 4
PGA gain = 8
PGA gain = 16
PGA gain = 32 and 64
Buffer operation
PGA gain = 1
-114
-111
THD
Total harmonic distortion
High-power mode,
PGA gain = 2
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
VIN = –0.5 dBFS
PGA gain = 4
-114
-111
dB
dB
dB
PGA gain = 8
PGA gain = 16
PGA gain = 32 and 64
Buffer operation
PGA gain = 1
-112
-111
Mid-power mode,
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
PGA gain = 2
PGA gain = 4
-115
-111
PGA gain = 8
VIN = –0.5 dBFS
PGA gain = 16
PGA gain = 32 and 64
Buffer operation
PGA gain = 1
-117
-115
Low-power mode,
VREF = 4.096 V,
AVDD1 = 5 V,
AVSS = 0 V,
fIN = 31.25 Hz,
PGA gain = 2
PGA gain = 4
-115
-113
PGA gain = 8
VIN = –0.5 dBFS
PGA gain = 16
PGA gain = 32 and 64
SFDR
Spurious-free dynamic range
Crosstalk
dB
dB
fIN = 31.25 Hz, VIN = –0.5 dBFS
fIN = 31.25 Hz, VIN = –0.5 dBFS
–140
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6.5 Electrical Characteristics (continued)
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1,
fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REFERENCE INPUT
High-power mode
110
110
80
Reference input current
Mid-power mode
Low-power mode
µA/V
FIR DIGITAL FILTER
High-power mode
Mid-power mode
Low-power mode
250
250
4000
4000
2000
0.003
fDATA
Data rate
SPS
125
Pass-band ripple
dB
Hz
Hz
Hz
dB
–0.003
0.375 × fDATA
0.413 × fDATA
0.5 × fDATA
Pass-band (–0.01 dB)
Bandwidth (–3 dB)
Stop band
Stop-band attenuation (1)
135
Minimum phase filter, at dc
Linear phase filter
5 / fDATA
31/ fDATA
62 / fDATA
62 / fDATA
Group delay
s
s
Minimum phase filter
Linear phase filter
Settling time (latency)
IIR DIGITAL FILTER
High-pass corner frequency
SAMPLE RATE CONVERTER
Clock compensation range
0.1
10
Hz
244 ppm of fCLK
ppb of fCLK
–244
Resolution
7.45
DIGITAL INPUT/OUTPUT
VOH
VOL
Ilkg
High-level output voltage
IOH = 1 mA
0.8 × IOVDD
V
Low-level output voltage
Input leakage
0.2 × IOVDD
V
IOL = –1 mA
1
–1
μA
POWER SUPPLY
PGA operation
1.4
0.25
0.85
0.25
0.8
High-power mode
AVDD1 = 3.3 V
mA
mA
mA
mA
mA
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
Mid-power mode
AVDD1 = 3.3 V
Low-power mode
AVDD1 = 3.3 V
0.2
IAVDD1
IAVSS
,
AVDD1, AVSS current
1.5
1.85
0.45
1.2
0.45
1.1
0.45
5
High-power mode
AVDD1 = 5 V
0.35
0.9
Mid-power mode
AVDD1 = 5 V
0.35
0.85
0.25
1
Low-power mode
AVDD1 = 5 V
mA
µA
Power-down mode
High-power mode
Mid-power mode
Low-power mode
Power-down mode
1.2
1.5
1.5
0.85
5
1.2
mA
µA
IAVDD2
AVDD2 current
AVDD2 = 2.5 V
0.7
1
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ZHCSQZ8A –MAY 2022 –REVISED DECEMBER 2022
6.5 Electrical Characteristics (continued)
minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD1 = 5 V, AVDD2 = 2.5 V to 5 V, AVSS = 0 V, IOVDD = 1.8 V, VREFP = 4.096 V, VREFN = 0 V, VCM = 2.5 V, PGA gain = 1,
fCLK = 8.192 MHz (4.096 MHz low-power mode) and fDATA = 500 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.43
0.43
0.24
1
MAX
0.6
0.6
0.4
10
UNIT
High-power mode
Mid-power mode
Low-power mode
Power-down mode
Standby mode
mA
IOVDD current
IIOVDD
μA
200
1.2
High-power mode
Mid-power mode
Low-power mode
Sample rate converter
operation
IOVDD additional current
1.2
mA
0.6
High-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
PGA operation
Buffer operation
8.3
mW
mW
mW
mW
mW
mW
4.5
6.5
4.5
4.8
2.8
11.5
5.3
8.3
5.3
6.4
3.4
Mid-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V
Low-power mode
AVDD1 = 3.3 V
AVDD2 = 2.5 V
Pd
Power dissipation (2)
High-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V
14.1
6.7
Mid-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V
10.8
6.7
Low-power mode
AVDD1 = 5 V
AVDD2 = 2.5 V
8.4
5.1
(1) Input frequencies at N × 32 kHz (16 kHz low-power mode) ± fDATA / 2 (where N = 1, 2, 3...) intermodulate with the chopper clock. At
these frequencies stop band attenuation = –90 dBFS (typ).
(2) Excluding current consumed by the voltage reference input or by sample rate converter operation. See voltage reference input current
and IOVDD current of sample rate converter operation.
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6.6 Timing Requirements: 1.65 V ≤IOVDD ≤1.95 V and 2.7 V ≤IOVDD ≤3.6 V
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
ns
CLOCK
High-power mode
Mid-power mode
Low-power mode
High-power mode
Mid-power mode
Low-power mode
High-power mode
Mid-power mode
Low-power mode
120.5
120.5
241
55
122.07
122.07
244.14
166
166
332
tc(CLK)
CLK period
tw(CLKH)
Pulse duration, CLK high
Pulse duration, CLK low
55
ns
110
55
tw(CLKL)
55
ns
110
SERIAL INTERFACE
tw(CSH)
Pulse duration, CS high
Delay time, first SCLK rising edge after CS falling edge
20
20
ns
ns
td(CSSC)
tc(SCLK)
tw(SCH)
SCLK period
120
50
ns
Pulse duration, SCLK high
ns
tw(SCL)
Pulse duration, SCLK low
50
ns
tsu(DI)
Setup time, DIN valid before SCLK rising edge
Hold time, DIN valid after SCLK rising edge
Setup time, SRC[1:0] register write before DRDY falling edge
10
ns
th(DI)
10
ns
tsu(SRC-W)
SYNC
256
1 / f(CLK)
tw(SYNL)
tw(SYNH)
tsu(SYNCLK)
th(SYNCLK)
RESET
tw(RSTL)
tsu(RSTCLK)
th(RSTCLK)
Pulse duration, SYNC low
2
2
1 / f(CLK)
1 / f(CLK)
ns
Pulse duration, SYNC high
Setup time, SYNC high before CLK rising edge
Hold time, SYNC high after CLK rising edge
10
10
ns
Pulse duration, RESET low
2
10
10
1 / f(CLK)
ns
Setup time, RESET high before CLK rising edge
Hold time, RESET high after CLK rising edge
ns
6.7 Switching Characteristics: 1.65V ≤IOVDD ≤1.95V and 2.7 V ≤IOVDD ≤3.6 V
over operating ambient temperature range and CLOAD = 20pF (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
SERIAL INTERFACE
tw(DRH)
Pulse duration, DRDY high
8
50
50
1 / f(CLK)
tp(CSDO)
tp(SCDO)
th(SCDO)
SYNC
Propagation delay time, CS falling edge to DOUT driven valid
Propagation delay time, SCLK falling edge to new DOUT valid
Propagation delay time, SCLK falling edge to DOUT invalid
ns
ns
ns
5
tp(SYNDR)
RESET
tp(RSTDR)
PWDN
Propagation delay time, SYNC rising edge to valid data DRDY falling edge
Propagation delay time, RESET rising edge to DRDY falling edge
Propagation delay time, PWDN rising edge to DRDY falling edge
Propagation delay time, power supply and CLK applied to first DRDY pulse
62.98145 / fDATA + 930 / fCLK
516,874
s
1/ fCLK
tp(PDDR)
POWER UP
tp(SUPDR)
62.98145 / fDATA + 946 / f(CLK)
650,000
s
1 / fCLK
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6.8 Timing Diagrams
tc(CLK)
tw(CLKL)
CLK
tw(CLKH)
图6-1. Clock Timing Requirements
tw(CSH)
CS
td(CSSC)
tc(SCLK)
tw(SCH)
SCLK
tsu(DI)
tw(SCL)
DIN
th(DI)
图6-2. Serial Interface Timing Requirements
tw(DRH)
DRDY
CS
SCLK
tp(CSDO)
th(SCDO)
MSB
LSB
DOUT
0
tp(SCDO)
图6-3. Serial Interface Switching Characteristics
CLK
th(SYNCLK)
tsu(SYNCLK)
SYNC
tw(SYNL)
tw(SYNH)
DRDY
(settled data)
tp(SYNDR)
(Pulse sync mode)
(settled data)
DRDY
(Continuous sync mode)
图6-4. SYNC Timing Requirements and Switching Characteristics
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CLK
th(RSTCLK)
tsu(RSTCLK)
RESET
tw(RSTL)
tp(RSTDR)
DRDY
图6-5. RESET Timing Requirements and Switching Characteristics
PWDN
DRDY
tp(PDDR)
图6-6. PWDN Switching Characteristics
DRDY
SRC[1:0] Register Write
SPI
tsu(SCR-W)
图6-7. Sample Rate Converter Register-Write Timing Requirements
AVDD1 – AVSS
1.65 V typ.
+
–
AVDD2 – AGND
1.65 V typ.
+
–
CAPD – DGND
1.35 V typ.
+
–
CLK
DRDY
tp(SUPDR)
图6-8. Power-Up Switching Characteristics
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6.9 Typical Characteristics
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
0
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
Shorted input, PGA gain = 1
Shorted input, PGA gain = 8
图6-9. High-Power Mode FFT Spectrum
图6-10. High-Power Mode FFT Spectrum
0
-20
0
-20
Buffer operation
PGA gain = 1 operation
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
5
10
15
20
25
30
35
40
45
50
Frequency (Hz)
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
RS = 1 kΩ
图6-11. High-Power Mode FFT Spectrum
图6-12. High-Power Mode FFT Spectrum
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
图6-13. High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
图6-14. High-Power Mode FFT Spectrum
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –0.5 dBFS, buffer operation
图6-15. High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V,
AVDD1 = 3.3 V, 2048 data points
图6-16. High-Power Mode FFT Spectrum
0
-20
0
-20
-40
-60
-80
-40
-60
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
图6-17. High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
图6-18. High-Power Mode FFT Spectrum
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
Shorted input, PGA gain = 1
Shorted input, PGA gain = 8
图6-19. Mid-Power Mode FFT Spectrum
图6-20. Mid-Power Mode FFT Spectrum
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
图6-22. Mid-Power Mode FFT Spectrum
图6-21. Mid-Power Mode FFT Spectrum
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
图6-23. Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V,
AVDD1 = 3.3 V, 2048 data points
图6-24. Mid-Power Mode FFT Spectrum
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
0
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
图6-25. Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
图6-26. Mid-Power Mode FFT Spectrum
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
Shorted input, PGA gain = 1
Shorted input, PGA gain = 8
图6-27. Low-Power Mode FFT Spectrum
图6-28. Low-Power Mode FFT Spectrum
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
图6-30. Low-Power Mode FFT Spectrum
图6-29. Low-Power Mode FFT Spectrum
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
图6-31. Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V,
AVDD1 = 3.3 V, 2048 data points
图6-32. Low-Power Mode FFT Spectrum
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
图6-33. Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
图6-34. Low-Power Mode FFT Spectrum
0
-20
140
135
130
125
120
115
110
105
TA = -40C
TA = 25C
TA = 85C
Buffer Operation
-40
-60
-80
-100
-120
-140
-160
-180
0
25
50
75 100 125 150 175 200 225 250
Frequency (Hz)
1
10
100
PGA Gain (V/V)
AIN1 = fIN = 31.25 Hz, –0.5-dBFS signal, AIN2 = shorted
图6-35. Channel-to-Channel Crosstalk
High-power mode
图6-36. Dynamic Range vs PGA Gain
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
140
135
130
125
120
115
110
105
140
135
130
125
120
115
110
105
TA = -40C
TA = 25C
TA = 85C
TA = -40C
TA = 25C
TA = 85C
Buffer operation
Bufferoperation
1
10
100
1
10
100
PGA Gain (V/V)
PGA Gain (V/V)
Mid-power mode
Low-power mode
图6-37. Dynamic Range vs PGA Gain
图6-38. Dynamic Range vs PGA Gain
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PGA gain = 1
PGA gain = 8
Buffer operation
PGA gain = 1
PGA gain = 8
Buffer operation
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Offset Error (V)
Offset Drift (V/C)
30 units
30 units
图6-39. Offset Error Distribution
图6-40. Offset Drift Distribution
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PGA gain = 1
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16, 32 and 64
Buffer operation
Gain Error (ppm)
30 units
Gain Error (ppm)
30 units
图6-41. Gain Error Distribution
图6-42. Gain Error Distribution
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PGA gain = 1
PGA gain = 2
PGA gain = 4
PGA gain = 8
PGA gain = 16, 32 and 64
Buffer operation
Gain Drift (ppm/C)
Gain Drift (ppm/C)
30 units
30 units
图6-43. Gain Drift Distribution
图6-44. Gain Drift Distribution
100
90
80
70
60
50
40
30
20
10
0
Gain Match (%)
30 units
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5
dBFS
图6-45. Gain Match Distribution
图6-46. High-Power Mode THD vs PGA Gain
-105
-105
TA = -40C
TA = 25C
TA = 85C
TA = -40C
TA = 25C
TA = 85C
-110
-115
-120
-125
-130
-110
-115
-120
-125
-130
Buffer operation
Buffer operation
1
10
100
1
10
100
PGA Gain (V/V)
PGA Gain (V/V)
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5
dBFS
dBFS
图6-47. Mid-Power Mode THD vs PGA Gain
图6-48. Low-Power Mode THD vs PGA Gain
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
-105
TA = -40C
TA = 25C
TA = 85C
-110
Buffer operation
-115
-120
-125
-130
1
10
100
PGA Gain (V/V)
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5
dBFS
dBFS
图6-49. High-Power Mode THD vs PGA Gain
图6-50. Mid-Power Mode THD vs PGA Gain
-105
-70
TA = -40C
TA = 25C
TA = 85C
PGA gain = 1
PGA gain = 4
PGA gain = 16
Buffer operation
-80
-90
-110
-115
-120
-125
-130
-100
-110
-120
-130
Buffer operation
1
10
100
0
10
20
30
40
50
60
70
80
90 100
PGA Gain (V/V)
Input Frequency (Hz)
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5
dBFS
dBFS
图6-51. Low-Power Mode THD vs PGA Gain
图6-52. High- and Mid-Power Mode THD vs Input Frequency
-70
PGA gain = 1
PGA gain = 4
PGA gain = 16
Buffer operation
-80
-90
-100
-110
-120
-130
0
10
20
30
40
50
60
70
80
90 100
Input Frequency (Hz)
High-speed mode
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5
dBFS
图6-54. PGA Input Current vs Input Voltage
图6-53. Low-Power Mode THD vs Input Frequency
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
33
30
27
24
21
18
15
12
9
6
3
0
PGA Input Current Noise Density (pA/Hz)
High- and mid-power modes
图6-55. PGA Input Current Noise Distribution
图6-56. Buffer Input Current vs Input Voltage
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
High-power mode
Mid-power mode
Low-power mode
High- and mid-power modes
Low-power mode
-40
-20
0
20
40
60
80
Temperature (C)
Reference Input Current (A)
30 units
图6-57. Reference Input Current vs Temperature
图6-58. Reference Input Current Distribution
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
160
140
120
100
80
100
90
80
70
60
50
40
30
20
10
0
High-power mode, PGA operation
Mid-power mode, PGA operation
Low-power mode, PGA operation
60
PGA gain = 1
Buffer operation
40
10
100
1000
10000
100000
1000000
Common-Mode Input Frequency (Hz)
AVDD1 Current (mA)
30 units
图6-59. CMRR vs Common-Mode Input Frequency
图6-60. AVDD1 Current Distribution
100
2
1.6
1.2
0.8
0.4
High-power mode, buffer
Mid-power mode, buffer
Low-power mode, buffer
High-power mode, PGA operation
Mid-power mode, PGA operation
Low-power mode, PGA operation
90
80
70
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
Temperature (C)
AVDD1 Current (mA)
30 units
图6-61. AVDD1 Current Distribution
图6-62. AVDD1 Current vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode),
VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)
0.5
0.4
0.3
0.2
0.1
100
90
80
70
60
50
40
30
20
10
0
High-power mode, PGA operation
Mid-power mode, PGA operation
Low-power mode, PGA operation
High-power mode
Mid-power mode
Low-power mode
-40
-20
0
20
40
60
80
Temperature (C)
AVDD2 Current (mA)
30 units
图6-63. AVDD1 Current vs Temperature
图6-64. AVDD2 Current Distribution
1.5
1.3
1.1
0.9
0.7
0.5
140
High- and mid-power modes
Low-power mode
120
100
80
60
AVDD1
AVDD2
IOVDD
40
20
10
-40
-20
0
20
40
60
80
100
1000
10000
100000
1000000
Temperature (C)
Power Supply Frequency (Hz)
图6-65. AVDD2 Current vs Temperature
图6-66. PSRR vs Power-Supply Frequency
0.6
High- and mid-power modes
Low-power mode
0.5
0.4
0.3
0.2
0.1
100
500
1000
5000
Data Rate (SPS)
图6-67. IOVDD Current vs Data Rate
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7 Parameter Measurement Information
7.1 Noise Performance
The ADS1285 is a 32-bit ADC providing three power-resolution modes, allowing optimization of noise
performance verses device power consumption. The four determining factors of noise performance are the
power mode, output data rate, PGA gain setting, and reference voltage selection. The high-power mode
operates the PGA and modulator sampling rate at the highest capacity for best overall noise performance. The
mid-power mode scales down the PGA quiescent current to reduce power consumption but results in increased
PGA noise. The low-power mode reduces both the modulator sampling rate and PGA quiescent current. The
result is the low-power mode has the lowest power consumption but the highest level of overall noise.
For all power modes, decreasing the output data rate reduces signal bandwidth, and therefore decreases total
noise. Increasing the PGA gain reduces noise when noise is referred to the input. Dynamic range performance
decreases when PGA gain is increased because the ratio of input voltage range to input-referred noise also
decreases.
Noise performance also depends on the reference voltage. Operation with VREF = 4.096 V or 5 V provides the
best noise performance. Operation with VREF = 2.5 V (required when operating AVDD1 = 3.3 V) reduces noise
performance.
Dynamic range and input noise are equivalent parameters that describe the available resolution of the ADC. 方
程式1 derives dynamic range from the input-referred noise data:
1.768 V
Gain × en
Dynamic Range (dB) = 20×log
(1)
where:
• en = Input-referred voltage noise (RMS)
图 7-1 and 图 7-2 show dynamic range performance at fDATA = 500 SPS for operation with VREF = 4.096 V and
VREF = 2.5 V.
140
135
130
125
120
115
110
105
140
High-power mode
Mid-power mode
Low-power mode
High-power mode
Mid-power mode
Low-power mode
Buffer operation
135 Buffer operation (gain = 1)
130
125
120
115
110
105
1
1
10
100
10
PGA Gain (V/V)
100
PGA Gain (V/V)
fDATA = 500 SPS, VREF = 4.096 V
fDATA = 500 SPS, VREF = 2.5 V
图7-1. Dynamic Range vs PGA Gain
图7-2. Dynamic Range vs PGA Gain
表 7-1 through 表 7-3 list dynamic range and input-referred noise performance with VREF = 4.096 V and AVDD1
= 5 V, tested with input source resistance (RS) = 0 Ω. 表 7-4 through 表 7-6 list dynamic range and input noise
performance with VREF = 2.5 V and AVDD1 = 3.3 V, tested with RS = 0 Ω. Noise data are at TA = 25°C and are
representative of typical ADC performance. The data are the standard deviation of 4096 consecutive ADC
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conversion results with the ADC inputs shorted, measured over the 0.413 × fDATA bandwidth. Because of the
statistical nature of noise, repeated measurements can yield varying noise performance results.
表7-1. High-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
250
135
137
136
134
130
126
120
114
500
1000
129
131
130
128
124
120
114
108
2000
4000
123
125
124
122
118
114
108
102
250
0.31
0.25
0.14
0.09
0.07
0.06
0.06
0.06
500
0.44
0.35
0.20
0.12
0.10
0.08
0.08
0.08
1000
0.63
0.50
0.28
0.18
0.14
0.11
0.11
0.11
2000
0.89
0.70
0.39
0.25
0.20
0.16
0.16
0.16
4000
1.25
0.99
0.56
0.35
0.28
0.22
0.22
0.22
1
1
Buffer
132
134
133
131
127
123
117
111
126
128
127
125
121
117
111
105
PGA
PGA
PGA
PGA
PGA
PGA
PGA
2
4
8
16
32
64
表7-2. Mid-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
1000
0.63
0.50
0.31
0.20
0.18
0.16
0.16
0.16
250
135
137
135
133
128
123
117
111
500
1000
129
131
129
127
122
117
111
2000
126
128
126
124
119
114
108
102
4000
123
125
123
121
116
111
105
99
250
0.31
0.25
0.16
0.10
0.09
0.08
0.08
0.08
500
0.44
0.35
0.22
0.14
0.12
0.11
0.11
0.11
2000
0.89
0.70
0.44
0.28
0.25
0.22
0.22
0.22
4000
1.25
0.99
0.63
0.39
0.35
0.31
0.31
0.31
1
1
Buffer
132
134
132
130
125
120
114
108
PGA
PGA
PGA
PGA
PGA
PGA
PGA
2
4
8
16
32
64
105
表7-3. Low-Power Mode Noise Performance (VREF = 4.096 V, AVDD1 = 5 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
125
135
138
137
135
131
126
120
114
250
500
129
132
131
129
125
120
114
108
1000
126
129
128
126
122
117
111
2000
123
126
125
123
119
114
108
102
125
0.31
0.22
0.12
0.08
0.06
0.06
0.06
0.06
250
0.44
0.31
0.18
0.11
0.09
0.08
0.08
0.08
500
0.63
0.44
0.25
0.16
0.12
0.11
0.11
0.11
1000
0.89
0.63
0.35
0.22
0.18
0.16
0.16
0.16
2000
1.25
0.89
0.50
0.31
0.25
0.22
0.22
0.22
1
1
Buffer
132
135
134
132
128
123
117
111
PGA
PGA
PGA
PGA
PGA
PGA
PGA
2
4
8
16
32
64
105
表7-4. High-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
1000
0.63
0.70
0.39
0.22
0.16
0.12
0.12
250
135
128
133
132
129
125
119
500
1000
129
122
127
126
123
119
113
2000
126
119
124
123
120
116
110
4000
123
116
121
120
117
113
107
250
0.31
0.35
0.20
0.11
0.08
0.06
0.06
500
0.44
0.50
0.28
0.16
0.11
0.09
0.09
2000
0.89
0.99
0.56
0.31
0.22
0.18
0.17
4000
1.25
1.40
0.79
0.44
0.31
0.25
0.25
1
1(1)
2
Buffer
132
125
130
129
126
122
116
PGA
PGA
PGA
PGA
PGA
PGA
4
8
16
32
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表7-4. High-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω) (continued)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
250
500
110
1000
2000
4000
250
500
1000
2000
4000
64
PGA
113
107
104
101
0.06
0.09
0.12
0.17
0.25
表7-5. Mid-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
fDATA
250
135
128
133
131
127
123
117
111
500
1000
129
122
127
125
121
117
111
2000
126
119
124
122
118
114
108
102
4000
123
116
121
119
115
111
105
99
250
0.31
0.35
0.20
0.12
0.10
0.08
0.08
0.08
500
0.44
0.50
0.28
0.18
0.14
0.11
0.11
0.11
1000
0.63
0.70
0.39
0.25
0.20
0.16
0.16
0.16
2000
0.89
0.99
0.56
0.35
0.28
0.22
0.22
0.22
4000
1.25
1.40
0.79
0.50
0.39
0.31
0.31
0.31
1
1(1)
2
Buffer
132
125
130
128
124
120
114
108
PGA
PGA
PGA
PGA
PGA
PGA
PGA
4
8
16
32
64
105
表7-6. Low-Power Mode Noise Performance (VREF = 2.5 V, AVDD1 = 3.3 V, RS = 0 Ω)
DYNAMIC RANGE (dB)
en, INPUT-REFERRED NOISE (μVRMS
)
GAIN
MODE
fDATA
500
129
123
128
127
124
119
113
107
fDATA
125
135
129
134
133
130
125
119
113
250
132
126
131
130
127
122
116
110
1000
126
120
125
124
121
116
110
104
2000
123
117
122
121
118
113
107
101
125
0.31
0.31
0.18
0.10
0.07
0.06
0.06
0.06
250
0.44
0.44
0.25
0.14
0.10
0.09
0.09
0.09
500
0.63
0.83
0.35
0.20
0.14
0.12
0.12
0.12
1000
0.89
0.89
0.50
0.28
0.20
0.17
0.17
0.17
2000
1.25
1.25
0.70
0.39
0.28
0.25
0.25
0.25
1
1(1)
2
Buffer
PGA
PGA
PGA
PGA
PGA
PGA
PGA
4
8
16
32
64
(1) Because of the limited input headroom with AVDD1 = 3.3 V operation, the available input range with PGA gain operation = 1 is ±1.35
VPP. The dynamic range data for PGA gain = 1 and AVDD1 = 3.3 V reflects the reduced input range.
8 Detailed Description
8.1 Overview
The ADS1285 is a high-resolution, low-power analog-to-digital converter (ADC) designed for applications in
energy exploration, geology, and seismic monitoring where low-power consumption and high resolution are
required. The converter provides 32 bits of resolution spanning data rates from 125 SPS to 4000 SPS. The
programmable gain amplifier (PGA) expands the system dynamic range by accepting signals ranging from ±2.5
VPP to ±0.039 VPP
.
As illustrated in the Functional Block Diagram, the ADC consists of the following sections: input multiplexer
(MUX), programmable gain amplifier (PGA), unity-gain buffer, delta-sigma (ΔΣ) modulator, sample rate
converter, infinite impulse response (IIR) high-pass filter (HPF), finite impulse response (FIR) low-pass filter
(LPF), and an SPI-compatible serial interface used for both device configuration and conversion data readback.
The input multiplexer selects between inputs 1 and 2, and internal options designed for self-test, including an
input-short option used to test offset and noise.
The input multiplexer is followed by a low-noise PGA. The PGA gain range is 1 to 16, with gains 32 and 64
provided as digital gains. The PGA is chopper-stabilized to reduce 1/f noise and input offset voltage. The PGA
output connects to a buffer which drives the modulator. An external 10-nF capacitor, connected to PGA output
pins CAPP and CAPN, provides an antialias filter for the input signal.
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The PGA can be disabled to lower device power consumption by operating the ADC with the unity-gain buffer.
External 47-nF capacitors connected to each buffer output filters the modulator sampling pulses.
The ΔΣ modulator measures the differential input signal (VIN) against the differential reference voltage (VREF).
The modulator provides three reference voltage options (2.5 V, 4.096 V, or 5 V). The reference voltage is
programmed by the user.
Modulator data are processed by the digital filter providing the final conversion result. The digital filter consists of
a sinc filter followed by a programmable phase, FIR low-pass filter, and an IIR high-pass filter. The high-pass
filter removes dc and low-frequency components from the data.
The sample rate converter (SRC) compensates clock frequency error by resampling the output data. The clock
frequency compensation range is ±244 ppm with 7-ppb resolution.
User-programmable gain and offset calibration registers correct offset and gain errors.
The SYNC pin synchronizes the ADC. Synchronization has two modes of operation: pulse synchronization and
continuous synchronization. The RESET pin resets the ADC, including user configuration settings. The pins are
noise-resistant, Schmitt-trigger inputs to increase reliability in high-noise environments.
The PWDN pin powers down the ADC when not in use. The software power-down mode (STANDBY) is available
through the serial interface
The 4-wire, SPI-compatible, serial interface reads conversion data and reads or writes device register data.
Two general-purpose digital I/Os are available for system level control.
Power for the PGA and buffer is supplied by AVDD1 and AVSS. A charge pump voltage regulator increases the
input voltage range of the buffer that follows the PGA. Power for the modulator is supplied by AVDD2. IOVDD
supplies the digital logic core through a 1.8-V low-dropout regulator (LDO). IOVDD is the digital I/O supply.
8.2 Functional Block Diagram
AVDD1
CAPC CAPBP CAPBN AVDD2
CAPD IOVDD
LDO
1.8 V
(digital core)
Charge
Pump
AVDD1
CLK
DRDY
AIN1P
AIN1N
CS
Serial
Interface
Sample
Rate
Converter
SCLK
DOUT
DIN
ûꢀ
Modulator
Digital
Filter
PGA
BUF
MUX
AIN2P
AIN2N
AVSS
PWDN
RESET
SYNC
GPIO
Control
2 x 400 Ω
VCM
AGND
AVSS
CAPI REFP
CAPP CAPN
REFN CAPR GPIO1 GPIO0
DGND
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8.3 Feature Description
8.3.1 Analog Input
图8-1 shows the analog input circuit and input multiplexer.
AVDD1
S1
S2
S3
AIN1P
ESD Diodes
(+)
AIN2P
400 ꢀ
AVSS
To PGA
To Buffer
AVDD1 + AVSS
2
S7
AVDD1
400 ꢀ
S4
S5
S6
(-)
AIN1N
ESD Diodes
AIN2N
AVSS
图8-1. Analog Input and Multiplexer
Electrostatic discharge (ESD) diodes are incorporated to protect the ADC inputs from ESD events that occur
during device manufacturing and printed circuit board (PCB) assembly process when assembled in an ESD-
controlled environment. For system-level protection, consider using external ESD protection devices to protect
the input that are exposed to ESD events.
If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes can conduct. If
these conditions are possible, use external clamp diodes, series resistors, or both to limit input current to the
specified maximum value. Overdriving an unused input channel can affect the conversion results of the active
input channel. Clamp the overdriven voltage with Schottky diodes to prevent channel crosstalk.
The ADC incorporates two differential input channels The multiplexer selects between the two differential inputs
for measurement. A test mode to measure noise and offset is also provided by the multiplexer. The shorted input
test configuration is available with or without the 400-Ω resistors to simulate the thermal noise generated by an
800-Ωgeophone. 表8-1 summarizes the multiplexer configurations.
表8-1. Input Multiplexer Modes
MUX[2:0] BITS SWITCHES
DESCRIPTION
000
001
010
011
100
101
S1, S5
Input AIN1P, AIN1N connection
S2, S6
Input AIN2P, AIN2N connection
S3, S4
400-Ω input-short test mode for offset and noise test.
Cross-connection test mode. Inputs AIN1P, AIN2P and AIN2P, AIN2N are connected
Reserved
S1, S5,S2, S6
—
S3,S4,S7
0-Ω input-short test mode for offset and noise test.
To test geophone THD performance, apply a test signal to the test channel through series resistors. The series
resistors are typically half the value of the geophone impedance. Select the multiplexer for the cross-connection
test mode (MUX[2:0] = 011b). In cross-connection mode, the test signal is cross-fed to the geophone input.
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Geophone THD test performance can be affected by the nonlinear on-resistance of the multiplexer (RSW). 图8-2
shows a model of the input multiplexer resistance for the geophone THD test. 图 8-3 shows THD performance
versus a test resistor (RLOAD) used to simulate geophone resistance. Small amplitude test signals (such as, VIN
= 0.221 V), shows less THD performance degradation for geophone resistance < 500 Ω.
-100
½ RLOAD
PGA gain = 1, VIN = 1.77 VRMS
PGA gain = 8, VIN = 0.221 VRMS
Test
Signal
Input2
-105
-110
-115
-120
-125
½ RLOAD
RSW
PGA
RSW
RSW
RSW
RLOAD
Input1
0
2000
4000
6000
8000
10000
Resistive Load ()
图8-3. THD Performance vs RLOAD
图8-2. THD versus RLOAD Test Circuit
8.3.2 PGA and Buffer
图8-4 shows the simplified PGA and buffer block diagram.
4.7 nF
10 nF, C0G
AGND
CAPC
AVDD1
CAPP
CAPN
AVDD1
Charge
Pump
MUX(+)
CAPBP
+
47 nF, C0G
AVSS
GAIN[2:0] bits
of register CONFIG1
(address = 02h)
Buffer mode
GAIN[2:0] = 111b
Modulator
CAPBN
47 nF, C0G
AVSS
+
MUX(-)
AVSS
AVSS
图8-4. PGA and Buffer Block Diagram
The device can be operated with the PGA or the unity-gain buffer. Buffer operation disables the PGA bias,
reducing device power consumption. Because of the limited input headroom for PGA gain = 1 when operating
with AVDD1 = 3.3 V, the buffer must be used under this condition.
8.3.2.1 Programmable Gain Amplifier (PGA)
The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range
performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling.
The PGA output signal is routed to the CAPP and CAPN pins through 270-Ω resistors. Connect an external 10-
nF, C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the
signal level at the modulator aliasing frequency (fMOD).
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As shown in 图 8-4, the buffer is used between the PGA and the modulator. Connect two 47-nF, C0G-dielectric
capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases the buffer
input voltage headroom. Connect an external 4.7-nF capacitor between CAPC and AGND for charge pump
operation.
The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. 表 8-2 shows the PGA gain
settings and buffer selection. The PGA gains and input signal range are irrespective of the voltage reference.
表8-2. PGA Gains
GAIN[2:0] REGISTER BITS
PGA GAIN
INPUT SIGNAL RANGE (VPP)
000
001
010
011
100
101
110
111
1
±2.5
±1.25
2
4
±0.625
8
±0.3125
±0.15625
±0.078125
±0.0390625
±2.5
16
32
64
Buffer mode, gain = 1
Observe the PGA input and output voltage headroom specification. 图 8-5 shows the input and output voltage
headroom when operating with AVDD1 = 5 V, an input common-mode voltage (VCM) = 2.5 V, a differential input
voltage = ±2.5 VPP, and at gain = 1. The absolute minimum and maximum PGA input voltage (1.25 V and 3.75
V) is ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15-V input
voltage margin at the negative peak and 0.4-V input voltage margin at the positive peak. As shown in the figure,
the PGA gain increases by × 1.5 when the ADC is operated with 4.096-V or 5-V voltage references. The PGA
provides 0.475-V output voltage margin at the positive and negative peaks.
PGA Input Headroom
PGA Output Headroom
AVDD1
AVDD1 - 0.15 V
AVDD1
VCM + 1.875 V
AVDD1 - 0.85 V
VCM + 1.25 V
VCM = 2.5 V
VCM - 1.25 V
AVSS + 1.1 V
VCM - 1.875 V
AVSS + 0.15 V
AVSS
AVSS
图8-5. PGA Headroom (AVDD1 = 5 V, PGA Gain = 1)
When operating with AVDD1 = 3.3 V, the PGA cannot support ±2.5-VPP input signals. Use the buffer for ±2.5-VPP
input signals. For ±1.25-VPP input signals (PGA gain = 2), the input headroom is increased by increasing the
common-mode voltage by 0.1 V to AVSS + 1.75 V. 图8-6 illustrates the input and output operating headroom for
AVDD1 = 3.3 V, VCM = 1.75 V, input signal = ±1.25 VPP, and gain = 2. The PGA uses normal gain scaling when
VREF = 2.5 V.
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PGA Input Headroom
PGA Output Headroom
AVDD1
AVDD1 - 0.15 V
AVDD1
VCM + 1.25 V
AVDD1 - 0.85 V
VCM + 0.6125 V
VCM = 1.75 V
VCM - 0.6125 V
AVSS + 1.1 V
VCM - 1.25 V
AVSS + 0.15 V
AVSS
AVSS
图8-6. PGA Headroom (AVDD1 = 3.3 V, Gain = 2)
8.3.2.2 Buffer Operation (PGA Bypass)
The ADC provides a buffer option, bypassing the PGA. Bypassing the PGA reduces device power consumption.
Use the buffer for ±2.5-VPP input signals when operating AVDD1 at 3.3 V. Buffer operation is enabled by setting
the GAIN[2:0] bits = 111b of the CONFIG1 register.
图 8-7 shows the buffer voltage headroom with AVDD1 = 3.3 V, VCM = 1.65 V, and the input signal = ±2.5 VPP
.
The buffer has sufficient voltage headroom for ±2.5-VPP input signals when operating with AVDD1 = 3.3 V.
Buffer Input Headroom
Buffer Output Headroom
AVDD1
AVDD1
AVDD1 - 0.1 V
AVDD1 - 0.1 V
VCM + 1.25 V
V
CM + 1.25 V
VCM = 1.65 V
VCM - 1.25 V
AVSS + 0.1 V
AVSS
VCM - 1.25 V
AVSS + 0.1 V
AVSS
图8-7. Buffer Headroom (3.3-V Operation Shown)
Regardless of PGA or buffer operation, connect two 47-nF, C0G-dielectric capacitors from each buffer output to
AVSS (CAPBP and CAPBN). The voltage charge pump increases the buffer input operating headroom. Connect
an external 4.7-nF capacitor between CAPC and AGND for the charge pump operation.
8.3.3 Voltage Reference Input
The ADC requires a reference voltage for operation. The reference voltage input is differential, defined as the
voltage between the REFP and REFN pins: VREF = VREFP – VREFN. Because of the differential input, the
VREFN trace can be routed to the voltage reference ground terminal to avoid ground noise pickup.
The device offers the choice of three reference voltages: 5 V, 4.096 V, or 2.5 V. Maximum dynamic range
performance is achieved using VREF = 5 V or 4.096 V, which requires AVDD1 = 5 V for operation. If AVDD1 = 3.3
V, the reference voltage is limited to 2.5 V. Program the reference voltage to match the physical voltage by the
REF[1:0] bits of the CONFIG1 register. Use a precision voltage reference with low noise, optimally less than 0.5
μVRMS over the measurement bandwidth.
图 8-8 illustrates a simplified reference input circuit. Similar to the analog inputs, the reference inputs are
protected by ESD diodes. If the reference inputs are driven below AVSS – 0.3 V or above AVDD1 + 0.3 V, the
protection diodes can conduct. If these conditions are possible, use external clamp diodes, series resistors, or
both to limit the reference input current to the specified value.
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AVDD1
CREF
REFP
REFN
AVSS
图8-8. Simplified Voltage Reference Input Circuit
The ADC samples the reference voltage by an internal capacitor (CREF) and then discharges the capacitor at the
modulator sampling frequency (fMOD). The sampling operation results in transient current flow into the reference
inputs. The transient current is filtered by a 0.1-µF ceramic capacitor placed directly at the reference pins with a
larger 10-μF to 47-μF capacitor at the voltage reference output. In applications where the voltage reference
drives multiple ADCs, use 0.1-µF capacitors at each ADC.
The external capacitor filters the current transients, resulting in an average reference current. The average
reference current is 110 μA/V for high- and mid-power operating modes and 80 μA/V for low-power operating
mode. For example, with VREF = 4.096 V, the reference input current is 110 μA / V × 4.096 V = 451 μA.
8.3.4 IOVDD Power Supply
The IOVDD digital supply operates in two voltage ranges: 1.65 V to 1.95 V and 2.7 V to 3.6 V. If operating
IOVDD in the 1.65-V to 1.95-V range, connect IOVDD directly to the CAPD pin. 图 8-9 shows the required
connection if IOVDD is operating in the 1.65-V to 1.95-V range. Otherwise, if operating IOVDD in the 2.7-V to
3.6-V range, do not connect these pins together.
1.65 V to 1.95 V
IOVDD
2.7 V to 3.6 V
Connect IOVDD to CAPD if IOVDD 1.65 V to 1.95 V.
Otherwise, do not connect these pins together.
CAPD
图8-9. IOVDD Power-Supply Connection
8.3.5 Modulator
The modulator is a multibit delta-sigma architecture featuring low power and outstanding dynamic range
performance with very low levels of spurious tones in the frequency spectrum. The modulator shapes the
quantization noise of the internal quantizer to an out-of-band frequency range where the noise is removed by the
digital filter. Noise remaining within the pass-band region is thermal noise with constant density (white noise).
The integrated noise within the pass band is determined by the digital filter OSR.
8.3.5.1 Modulator Overdrive
The modulator is an inherently stable design and, therefore exhibits predictable recovery from input overdrive. If
the modulator is overdriven at the peaks of the input signal, the filter output data may or may not clip depending
on the duration of the signal overdrive resulting from the data averaging of the digital filter. If the modulator is
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heavily overdriven, then the likelihood of clipped conversion data increases. Be aware the group delay of the
digital filter delays the occurrence of an input overdrive event from appearing in the output data.
8.3.6 Digital Filter
The digital filter decimates and filters the modulator data to provide the high-resolution output data. By adjusting
the amount of filtering though the OSR, trade-offs can be made between total noise and bandwidth. Increasing
the OSR lowers total noise while decreasing the signal bandwidth.
As shown in 图 8-10, the sample rate converter (SRC) receives data from the modulator prior to input to the
digital filter block. See the Sample Rate Converter section for details.
SRC Bypass
IIR Bypass
Final Output Data
Sinc Filter
Variable decimation
(8 to 128)
FIR Filter
Fixed decimation
(32)
IIR Filter
No decimation
User calibration
and code clip
From Modulator
SRC
FILTR[1:0] bits 1,0 CONFIG0
(register address = 01h)
00: Reserved
01: Sinc filter
10: FIR filter (default)
11: FIR and IIR filter
图8-10. Digital Filter Block Diagram
The digital filter is comprised of three sections: a variable-decimation sinc filter; a variable-coefficient, fixed-
decimation FIR filter; and a programmable high-pass filter (IIR). The desired filter path is selected by the
FILTER[1:0] bits of the CONFIG0 register. The sinc filter provides partially filtered data, bypassing the FIR and
HPF filters and user calibration. For fully filtered data, select the FIR filter option. The IIR filter stage removes dc
and low-frequency data The FIR and the combined FIR + IIR filter are routed to the user calibration block and
output code clipping block. See the Offset and Gain Calibration section for details of user calibration.
8.3.6.1 Sinc Filter Section
The first section of the digital filter is a variable-decimation, fifth-order sinc filter (sinx/x). Modulator data are
passed through the sample rate converter to the sinc filter at the nominal rate of fMOD = fCLK / 4 = 2.048 MHz
(1.024-MHz low-power mode). The sinc filter partially filters the data for the FIR filter that produces the final
frequency response. The sinc filter data are intended to be used with post-processing filters to shape the final
frequency response.
表 8-3 shows the decimation ratio and the resulting output data rate of the sinc filter. The sinc filter data rate is
programmed by the DR[2:0] bits of the CONFIG0 register.
表8-3. Sinc Filter Data Rates
DATA RATE (SPS)
DR[2:0] BITS
SINC DECIMATION RATIO (N)
HIGH- AND MID-POWER MODES
LOW-POWER MODE
4,000
000
001
010
011
100
256
128
64
8,000
16,000
32,000
64,000
128,000
8,000
16,000
32
32,000
16
64,000
方程式2 shows the Z-domain transfer function of the sinc filter.
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5
-N
1 - Z
-1
N(1 - Z )
H(Z) =
(2)
where:
• N = Decimation ratio of 表8-3
方程式3 shows the frequency domain transfer function of the sinc filter.
5
pN ´ f
sin
fMOD
½H(f)½ =
p ´ f
N sin
fMOD
(3)
where:
• N = Decimation ratio shown in 表8-3
• f = Input signal frequency
• fMOD = Modulator sampling frequency = fCLK / 4 (sample rate converter disabled)
The sinc filter frequency response has notches (or zeros) occurring at the output data rate and multiples thereof.
At these frequencies, the filter has zero gain. 图 8-11 shows the wide-band frequency response of the sinc filter
and 图8-12 shows details of the –3-dB response.
0
-20
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-40
-60
-80
-100
-120
-140
0
1
2
3
4
5
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA
)
Normalized Frequency (fIN/fDATA
)
图8-11. Sinc Filter Frequency Response
图8-12. Sinc Filter –3-dB Response
图 8-13 illustrates the sinc filter frequency response at fDATA = 32 kSPS. The tones at 1 kHz and harmonics are
the result of dither added to the modulator input to suppress idle tones. The frequency of the dither signal is fMOD
divided by the combined decimation ratio shown in 表 8-4. The rise of the noise floor at 2 kHz is resultant of
modulator noise shaping. For sinc filter decimation N = 64 (data rate = 32 kSPS), the usable bandwidth by the
use of external post filtering is 500 Hz.
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0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
2
4
6
8
10
12
14
16
Frequency (kHz)
图8-13. FFT Output of the Sinc Filter (fDATA = 32 kSPS)
The sinc filter data bypasses the data scaling, clip stage, and user calibration, and as a result, the sinc filter data
are scaled differently compared to the FIR filter. See the Conversion Data Format section for details of sinc filter
data scaling.
8.3.6.2 FIR Filter Section
The second section of the digital filter is a multistage, FIR low-pass filter. Partially filtered data from the sinc filter
are input to the FIR filter. The FIR filter determines the final frequency and phase response of the data. 图 8-14
shows that the FIR filter consists of four stages.
FIR Filter 1
2
FIR Filter 2
2
FIR Filter 3
4
FIR Filter 4
2
From sinc filter
To user calibration
PHASE bit 2 of CONFIG0
(register address = 01h)
0: Linear phase coefficients (default)
1: Minimum phase coefficients
图8-14. FIR Filter
The first two FIR stages are half-band filters with decimation = 2 for each stage. The third and fourth FIR stages
determine the final frequency and phase response. Decimation is 4 and 2, for FIR stages three and four. The
overall decimation ratio of the FIR filter is 32. Unique coefficient sets in stage 3 and 4 determine linear and
minimum phase filter response. The phase response is selected by the PHASE bit of the CONFIG0 register. 表
8-4 lists the combined decimation ratio of the sinc and FIR filter stages and the corresponding FIR filter data
rate.
表8-4. FIR Filter Data Rate
DATA RATE (SPS)
DR[2:0] BITS
COMBINED DECIMATION RATIO
HIGH- AND MID-POWER MODES
LOW-POWER MODE
000
001
010
011
100
8192
4096
2048
1024
512
250
500
125
250
1000
2000
4000
500
1000
2000
表8-5 lists the FIR filter coefficients and the data scaling for the linear and minimum phase coefficients.
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表8-5. FIR Filter Coefficients
STAGE 1
STAGE 2
STAGE 3
STAGE 4
SCALE = 1/134217728
COEFFICIENT
SCALE = 1/512
SCALE = 1/8388608
SCALE = 1/134217728
LINEAR PHASE
LINEAR PHASE
LINEAR PHASE
MINIMUM PHASE
819
LINEAR PHASE
–132
MINIMUM PHASE
b0
3
0
0
0
11767
133882
–10944
b1
0
103807
0
8211
–432
b2
44880
769961
–25
0
–73
–75
b3
174712
2481
2940447
–874
b4
150
256
150
0
536821
6692
8262605
–507903
0
–4648
b5
1372637
3012996
5788605
9852286
14957445
20301435
24569234
26260385
24247577
18356231
9668991
327749
7419
17902757
30428735
40215494
39260213
23325925
–1757787
–21028126
–21293602
–3886901
14396783
16314388
1518875
–16147
–41280
–80934
–120064
–118690
–18203
224751
b6
2512192
4194304
2512192
0
–266
b7
–10663
–8280
b8
–25
0
b9
10620
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
b33
b34
b35
b36
b37
b38
b39
b40
b41
b42
b43
b44
b45
b46
b47
b48
b49
b50
3
22008
–507903
0
348
103807
0
580196
–34123
–25549
33460
893263
891396
–10944
293598
61387
–987253
–2635779
–3860322
–3572512
–822573
4669054
12153698
19911100
25779390
27966862
25779390
–7546
–7171917
–10926627
–10379094
–6505618
–1333678
2972773
5006366
4566808
2505652
126331
–94192
–50629
101135
–12979500
–11506007
2769794
134826
–56626
–220104
–56082
263758
231231
–215231
–430178
34715
12195551
6103823
–6709466
–9882714
–353347
8629331
5597927
19911100
12153698
4669054
–822573
–3572512
–3860322
–2635779
–987253
293598
–1496514
–1933830
–1410695
–502731
245330
–4389168
–7594158
–428064
6566217
4024593
–3679749
–5572954
332589
580424
283878
–588382
–693209
366118
565174
492084
231656
1084786
132893
–1300087
–878642
1162189
1741565
–522533
–2490395
–688945
2811738
2425494
–2338095
–4511116
641555
6661730
2950811
–8538057
5136333
2351253
–3357202
–3767666
1087392
3847821
919792
–9196
891396
–125456
–122207
–61813
–4445
893263
580196
224751
22484
–18203
–118690
–120064
–80934
–41280
–16147
–4648
–874
22245
10775
–2918303
–2193542
1493873
2595051
940
–2953
–2599
–1052
–79991
–2260106
–963855
1482337
1480417
–43
214
–73
0
132
0
33
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表8-5. FIR Filter Coefficients (continued)
STAGE 1
STAGE 2
STAGE 3
STAGE 4
COEFFICIENT
SCALE = 1/512
LINEAR PHASE
SCALE = 1/8388608
LINEAR PHASE
SCALE = 1/134217728
SCALE = 1/134217728
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
–586408
–1497356
–168417
1166800
644405
–675082
–806095
211391
b51
b52
b53
b54
b55
b56
b57
b58
b59
b60
b61
b62
b63
b64
b65
b66
b67
b68
b69
b70
b71
b72
b73
b74
b75
b76
b77
b78
b79
b80
b81
b82
b83
b84
b85
b86
b87
b88
b89
b90
b91
b92
b93
b94
b95
b96
b97
b98
b99
b100
b101
0
0
–10537298
9818477
41426374
56835776
41426374
9818477
–10537298
–8538057
2950811
740896
141976
–527673
–327618
278227
363809
–70646
–304819
–63159
205798
124363
–107173
–131357
31104
6661730
641555
–4511116
–2338095
2425494
2811738
–688945
–2490395
–522533
1741565
1162189
–878642
–1300087
132893
107182
15644
1084786
366118
–71728
–36319
38331
–693209
–588382
283878
580424
34715
38783
–13557
–31453
–1230
–430178
–215231
231231
20983
7729
263758
–11463
–8791
–56082
–220104
–56626
134826
101135
–50629
–94192
–7546
61387
4659
7126
–732
–4687
–976
2551
1339
–1103
–1085
314
33460
–25549
–34123
348
681
16
22008
10620
–349
–96
144
–8280
78
–10663
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表8-5. FIR Filter Coefficients (continued)
STAGE 1
STAGE 2
STAGE 3
STAGE 4
SCALE = 1/134217728
COEFFICIENT
SCALE = 1/512
LINEAR PHASE
SCALE = 1/8388608
LINEAR PHASE
SCALE = 1/134217728
LINEAR PHASE
MINIMUM PHASE
LINEAR PHASE
MINIMUM PHASE
b102
b103
b104
b105
b106
b107
b108
b109
–266
7419
6692
2481
–75
–432
–132
0
–46
–42
9
16
0
–4
0
0
图8-15 shows the FIR pass-band frequency response to 0.375 × fDATA with ±0.003-dB pass-band ripple. 图8-16
shows the pass-band, transition-band, and stop-band performance from 0 Hz to fDATA. The filter is designed for
–135-dB stop-band attenuation at the Nyquist frequency.
2.0
1.5
20
0
-20
1.0
-40
0.5
-60
0
-80
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
-160
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Normalized Input Frequency (fIN/fDATA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Input Frequency (fIN/fDATA
)
)
图8-16. FIR Filter Transition Band Response
图8-15. FIR Filter Pass-Band Response
As with many sampled systems, the filter response repeats at multiples of the modulator sample rate (fMOD). The
filter response repeats at frequencies = N × fMOD ± f0, where N = 1, 2, and so on, and f0 = filter pass-band).
These frequencies, if not filtered and are otherwise present in the signal, fold back (or alias) into the pass-band
causing errors. A low-pass input filter reduces the aliasing error. For a band-limited signal typical of many
geophones, a single-pole filter at the PGA output is sufficient to suppress the aliasing frequencies.
8.3.6.3 Group Delay and Step Response
The FIR filter offers linear and minimum phase filter options. The pass-band, transition band, and stop-band
responses of the linear and minimum phase filters are the same but differ in phase and step response behavior.
8.3.6.3.1 Linear Phase Response
A linear phase filter has the unique property that the delay from input to output is constant across all input
frequencies (that is, constant group delay). The constant delay property is independent of the nature of the input
signal (impulse or swept-tone), and therefore the phase is linear across frequency, which can be important when
analyzing multitone signals. However, as depicted in 图 8-17, the group delay is longer for the linear phase filter
compared to minimum phase. For both the linear and minimum filters, fully settled data are available 62
conversions after a step input change occurs.
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1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Minimum Phase Filter
Linear Phase Filter
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA
)
图8-17. FIR Step Response
8.3.6.3.2 Minimum Phase Response
The minimum phase filter provides a short group delay for data from filter input to filter output. 图8-18 shows the
group delay for minimum and linear phase filters. The group delay of the minimum phase filter is a function of
signal frequency. The PHASE bit of the CONFIG0 register programs the filter phase.
35
Linear Phase Filter
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
图8-18. FIR Group Delay (fDATA = 500 SPS)
8.3.6.4 HPF Stage
The last stage of the digital filter is the high-pass filter (HPF). The high-pass filter is implemented as a first-order,
IIR filter. The high-pass filter removes dc and low frequencies from the data. The HPF is enabled by
programming the FILTR[1:0] bits = 11b of the CONFIG0 register.
方程式4 shows the z-domain transfer function of the filter:
2 - a
2
1 - z-1
1 - (1 - a)z-1
H(z) =
(4)
where:
a =
2sin(&N)
cos(&N) + sin(&N)
•
• ωN = π× fC / fDATA (normalized corner frequency, radians)
• fC = Corner frequency (Hz)
• fDATA = Output data rate (Hz)
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Be aware the corner frequency programming is a function of fDATA. As shown by 方程式 5, the value written to
the HPF1, HPF0 registers is value a, computed by 方程式4, × 216.
HPF[15:0] = a × 216
(5)
表8-6 shows examples of the high-pass filter programming.
表8-6. High-Pass Filter Value Examples
HPF[15:0]
0332h
fC (Hz)
fDATA (SPS)
250
0.5
1.0
1.0
0332h
500
019Ah
1000
The HPF accumulates data to perform the high-pass function. Similar to the operation of an analog HPF after a
dc step change is applied to the input, the filter takes time to accumulate data to remove dc from the signal. The
lower the corner frequency, the longer the filter takes to settle.
To shorten the HPF settling time, the offset register is used as a seed value for the HPF accumulator. The
accumulator is loaded with the offset register each time the HPF state is changed from disabled to enabled. The
offset register can be preset with an estimated value, or a calibrated value if the dc level is known. To improve
accuracy, scale the offset value by the inverse value of GAIN[3:0] / 400000h. The normal offset operation is
disabled when the HPF is enabled.
To initialize the HPF accumulator with the OFFSET[2:0] registers:
1. Disable the HPF.
2. Write the desired value to the OFFSET[2:0] registers.
3. Enable the HPF. OFFSET[2:0] is loaded to the HPF data accumulator.
4. The HPF tracks the remaining dc value from the signal.
Subsequent writes to the OFFSET[2:0] registers are ignored. To reload the contents of the OFFSET[2:0]
registers to the HPF, disable and re-enable the HPF.
8.3.7 Clock Input
A clock signal is required for operation. The clock signal is applied to the CLK pin at fCLK = 8.192 MHz for high-
and mid-power modes and 4.096 MHz for low-power mode. As with many precision data converters, a low-jitter
clock is required to achieve data sheet performance. Avoid the use of R-C clock oscillators. A crystal-based
clock source is recommended. Avoid ringing on the clock signal by placing a series resistor in the clock PCB
trace to source-terminate. Keep the clock signal routed away from other clock signals, input pins, and analog
components.
8.3.8 GPIO
The ADC provides two general-purpose I/O (GPIO) pins that can be used as digital inputs or outputs. The GPIO
voltage levels are IOVDD and DGND. 图8-19 illustrates the GPIO block diagram.
The GPIOs are programmed by the GPIO register. The GPIOs are programmed as an input or output by the
GPIOx_DIR bits. The GPIO state is read or written by the GPIOx_DAT bits. When programmed as an output,
reading the GPIOx_DAT bits returns the register bit value previously written. If the GPIOs are unused, terminate
the GPIOs with pulldown resistors to prevent the pins from floating.
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IOVDD
GPIO0_DIR bit 1 of GPIO
(register address = 0Bh)
0: GPIO0 is an input (default)
1: GPIO0 is an output
SW
Write
GPIO0_DAT bit 3 of GPIO
(register address = 0Bh)
GPIO0
0: GPIO0 data is low
1: GPIO0 data is high
100 k
Read
GPIO1_DIR bit 2 of GPIO
(register address = 0Bh)
0: GPIO1 is an input (default)
1: GPIO1 is an output
SW
Write
GPIO1_DAT bit 4 of GPIO
GPIO0
(register address = 0Bh)
0: GPIO1 data is low
1: GPIO1 data is high
100 k
Read
Read
DGND
图8-19. GPIO Operation
8.4 Device Functional Modes
8.4.1 Power Modes
There are three power-resolution modes offering trade-offs between power consumption and dynamic range.
The modes are high power, mid power, and low power. See the Noise Performance section for details of noise
performance. The MODE[1:0] bits of the CONFIG0 register selects the power mode. The clock frequency for
low-power mode is 4.096 MHz (half-speed clock); therefore, the output data rates are also scaled by one half.
8.4.2 Power-Down Mode
Power-down is engaged by taking the PWDN pin low, or by software control, by sending the STANDBY
command. To exit power-down, take PWDN high or send the WAKEUP command to exit software power-down
(with the clock running). Power-down disables the analog circuit; however, the digital LDO (CAPD pin) remains
biased, drawing a small bias current from IOVDD. In comparison, software power-down draws larger IOVDD
bias current. In both power-down modes, the ac signals of the digital outputs are stopped but remain driven high
or low. The digital inputs must not be allowed to float; otherwise, leakage current can flow from the IOVDD
supply. Reset the ADC if the clock is interrupted in power-down. Synchronization is lost in power-down;
therefore, resynchronize the ADC.
8.4.3 Reset
The ADC is reset by three methods: power-on reset (POR), the RESET pin, or the RESET command. Power-on
reset occurs when the power-supply voltages cross the respective thresholds. See Power-Up Switching
Characteristics for details. To reset the ADC by pin, drive RESET low for at least two fCLK cycles and return high
for reset. By command, reset takes effect on the next rising fCLK edge after the eighth rising edge of SCLK of the
reset command. At reset, the filter is restarted and the user registers reset to default. Reset timing is illustrated in
图6-5.
8.4.4 Synchronization
The ADC is synchronized by the SYNC pin or by the SYNC command, resulting in restart of the digital filter
cycle. Synchronization by the pin occurs on the next rising edge of CLK after SYNC is taken high on the falling
edge of CLK. Synchronization by the SYNC command occurs on the rising edge of CLK following the eighth bit
of the command.
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The following results in loss of synchronization:
• Power-up cycle, ADC reset, or when hardware or software power down modes are entered
• The following mode changes:
– DR[2:0] (data rate)
– PHASE (filter phase)
– MODE[1:0] (power mode)
– SYNC (synchronization mode)
– SRC[1:0] (sample rate converter enabled or disabled)
There are two synchronization control modes: pulse sync and continuous sync. The synchronization mode is
programmed by the SYNC bit of the ID/SYNC register.
8.4.4.1 Pulse-Sync Mode
The pulse-sync mode unconditionally synchronizes the ADC on the rising edge of SYNC. When synchronized,
the internal filter memory is reset, DRDY goes high, and the filter cycle restarts. The following 63 DRDY periods
are disabled to allow for digital filter settling. DRDY asserts low when the conversion data are ready. See 图 6-4
for synchronization timing details.
8.4.4.2 Continuous-Sync Mode
The continuous-sync mode offers the option of accepting a continuous clock signal to the SYNC pin. The ADC
compares the period of the SYNC clock signal to N periods of the DRDY signal to qualify resynchronization.
Initially, the first SYNC positive edge synchronizes the ADC. Resynchronization occurs only when the time
period between rising edges of SYNC over N multiple DRDY periods differ by at least ± one fCLK cycle, where N
= 1, 2, 3 and so on. Otherwise, the SYNC clock period is in synchronization with the existing DRDY pulses, so
no resynchronization occurs. Be aware the continuous sync mode cannot be used when the sample rate
converter is enabled.
After synchronization, DRDY continues to pulse; however, data are held low for 63 data periods to allow for the
digital filter to settle. See 图 6-4 for the DRDY behavior. Because of the initial delay of the digital filter, the SYNC
input signal and the DRDY pulses exhibit an offset time. The offset time is a function of the data rate.
8.4.5 Sample Rate Converter
The sample rate converter (SRC) compensates clock frequency error by resampling the modulator data at a new
rate set by the compensation factor written to the SRC registers. The frequency compensation range is ±244
ppm with 7.45-ppb (1 / 227) resolution.
Clock frequency error is compensated by writing a value to the SCR0 and SRC1 registers. The register value is
in 2's-complement format for positive and negative frequency error compensation. Positive register data values
decrease the data rate frequency (increases the period). The new data rate frequency is observed by the
frequency of the DRDY signal.
表 8-7 shows example values of frequency compensation. 8000h disables the sample rate converter. 0000h
passes the data through with no compensation but adds an 8 / fCLK delay to the time delay of SYNC input to the
DRDY pulses.
表8-7. Example SRC Values
SRC[15:0] VALUE
7FFFh
COMPENSATION FACTOR
(1 –32,767 / 227) × fDATA
(1 –1 / 227) × fDATA
1 × fDATA
0001h
0000h
7FFFh
(1 + 1 / 227) × fDATA
8001h
(1 + 32,767 / 227) × fDATA
8000h
1 × fDATA (SRC disabled)
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Resynchronize the ADC after the sample rate converter is enabled or disabled.
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Because the SRC is a digital function, operation is deterministic without error. The SRC trim value can be written
all at the same time, or written incrementally up to a target value to minimize the step change of frequency. Use
the multibyte command operation to write to the SRC registers and complete the write operation 256 CLK cycles
before the DRDY falling edge. This procedure loads the high and low bytes simultaneously before they are
internally processed. See 图6-7 for details.
8.4.6 Offset and Gain Calibration
The ADC integrates calibration registers to correct offset and gain errors. As shown in 方程式 6 and 图 8-20, the
24-bit offset value (OFFSET[23:0]) is subtracted from the filter data before multiplication by the 24-bit gain value
(GAIN[23:0]), divided by 400000h. The data are clipped to 32 bits to yield the final output. The offset operation is
bypassed when the high-pass filter is enabled.
GAIN[23:0]
Output =
(Input - OFFSET[23:0])
400000h
(6)
offset bypassed in HPF mode
output data
clipped to 32 bits
+
from digital filter
X
final output
-
OFFSET[23:0]
GAIN[23:0]
400000h
图8-20. Calibration Block Diagram
8.4.6.1 OFFSET Register
Offset correction is by a 24-bit word consisting of three 8-bit registers (high address is the MSB). The offset
value is left-justified to align to the 32-bit data. The offset value is 2's-complement coding with a maximum
positive value of 7FFFFFh and a maximum negative value of 800000h. OFFSET is subtracted from the
conversion data; see 表 8-8. Offset error is corrected by the offset calibration command with the input-short
multiplexer option, or by collecting shorted-input ADC data and writing the value to the registers.
Although the offset correction range is from –FS to +FS, the sum of offset and gain correction must not exceed
106% of the uncalibrated range.
When the high-pass filter is enabled, offset correction is disabled. The offset value is used instead as a starting
value to shorten the high-pass filter settling time. To reload the offset value to the HPF, disable and re-enable the
high-pass filter. See the HPF Stage section for more details.
表8-8. Offset Calibration Values
OFFSET[31:0]
CALIBRATED OUTPUT CODE (1)
00007Fh
FFFF8100h
000000h
00000000h
FFFF7Fh
00008100h
(1) Ideal code value with no offset error.
8.4.6.2 GAIN Register
Gain correction is through a 24-bit word, consisting of three 8-bit registers (high address = MSB). The gain value
is 24 bits, coded in straight binary and normalized to 1.0 for GAIN[23:0] equal to 400000h. With a calibration
signal applied, gain error is calibrated by either the gain calibration command, or by collecting ADC data and
writing a computed value to the gain registers. 表 8-9 lists examples of the GAIN[23:0] register values. Although
the range of gain values can be much greater or less than 1, the sum of offset and gain correction must not
exceed 106% of the uncalibrated range.
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表8-9. Gain Calibration Values
GAIN[31:0]
GAIN CORRECTION FACTOR
433333h
1.05
400000h
1.00
0.95
3CCCCCh
8.4.6.3 Calibration Procedure
ADC calibration can be performed using the ADC calibration commands or by performing manual calibration.
The calibration procedure is as follows:
1. Select the PGA or buffer operation, input channel, and PGA gain condition for calibration.
2. Preset the OFFSET register = 000000h and the GAIN register = 400000h.
3. Disable the high-pass filter for offset calibration. Short the inputs to the system, or use the input MUX to
provide the input short. A system-level input short can yield more accurate calibration. After the input settles,
either send the OFSCAL command or perform a manual calibration.
a. OFSCAL command. After the command is sent, DRDY is driven low 81 conversion periods later to
indicate calibration is complete. The OFFSET register is updated with the new calibration value. As
shown in 图8-21, the first data output uses the new OFFSET value.
b. Manual calibration. Wait at least 64 conversions for the digital filter to settle then average a number of
data points to improve calibration accuracy. Write the value to the 24-bit OFFSET register.
4. Apply a gain calibration voltage. After the input settles, either send the GANCAL command or perform a
manual calibration.
a. GANCAL command. Apply a positive dc full-scale calibration voltage. After the command is sent, DRDY
is driven low 81 conversion periods later to indicate calibration is complete. The ADC calculates GAIN
such that the full-scale code is equal to the applied calibration signal. As shown in 图8-21, the first data
output uses the new GAIN value.
b. Manual calibration. Apply an ac signal coherent to the sample rate or dc calibration signal that are
slightly below full-scale (for example, 2.4 V for gain = 1). Using a calibration signal less than full-scale
range prevents clipped output codes that otherwise lead to incorrect calibration. Wait 64 conversions for
the digital filter to settle then average a number of data points to improve calibration accuracy. For ac-
signal calibration, use a number of coherent signal periods to compute the RMS value.
方程式7 computes the value of GAIN for manual calibration.
Expected Output Code
GAIN[23:0] = 400000h ‡
Actual Output Code
(7)
DRDY
81 conversion periods
CS
8
SCLK
DIN
CAL Command
DOUT
00h
图8-21. Calibration Command
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8.5 Programming
8.5.1 Serial Interface
Conversion data are read and ADC configuration is made through the SPI-compatible serial interface. The
interface consists of four signals: CS, SCLK, DIN, and DOUT. DRDY asserts low when conversion data are
ready. The serial interface is passive (peripheral mode), where the serial clock (SCLK) is an input. The ADC
operates in SPI mode 0, where CPOL = 0 and CPHA = 0. In mode 0, SCLK idles low and data are updated on
the SCLK falling edges and are read on the SCLK rising edges.
8.5.1.1 Chip Select (CS)
CS is an active-low input that selects the serial interface for communication. A communication frame is started
by taking CS low and is ended by taking CS high. Because only one command per frame is permitted, toggle CS
between commands. Taking CS high before the command is completed resets the operation and blocks further
SCLK inputs. CS high forces DOUT to a high-impedance state. DRDY remains active regardless of the state of
CS.
8.5.1.2 Serial Clock (SCLK)
SCLK is the serial clock input that shifts data into and out of the ADC. The ADC latches DIN data on the rising
edge of SCLK. DOUT data are shifted out on the falling edge of SCLK. Keep SCLK low when not active. The
SCLK pin is a Schmidt-trigger input that reduces sensitivity to SCLK noise. However, keep the SCLK signal as
noise free as possible to prevent inadvertent shifting of the data.
8.5.1.3 Data Input (DIN)
DIN is used to input data to the ADC. DIN data are latched on the rising edge of SCLK.
8.5.1.4 Data Output (DOUT)
DOUT is the data output pin. Data are shifted out on the falling edge of SCLK and are latched by the host on the
rising edge. Because the conversion data MSB is on DOUT when CS is driven low (DRDY low), the MSB of the
data is read on the first rising edge of SCLK. Minimize trace length to reduce load capacitance on the pin. Place
a series termination resistor close to the pin to terminate the PCB trace impedance. Taking CS high forces
DOUT to a high-impedance state.
8.5.1.5 Data Ready (DRDY)
DRDY is an active-low output that indicates conversion data are ready. DRDY is active regardless of the state of
CS. DRDY is driven high on the first falling edge of SCLK, regardless if data is being read or a command is
input. As shown in 图8-22, if data are not retrieved, DRDY pulses high for eight fCLK periods.
Dara Updating
8/fCLK
DRDY
图8-22. DRDY With No Data Retrieval
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8.5.2 Conversion Data Format
As listed in 表 8-10, the conversion data are coded in 32-bit, 2's-complement format to represent positive and
negative numbers. If desired, the data read operation can be shortened to 24 bits by taking CS high. Data
scaling from the Sinc filter is dependent on the value of VREF and whether PGA or buffer operation.
表8-10. Output Data Format
CONVERSION CODES(1)
FIR FILTER
VREF = 2.5 V, 4.096 V or 5 V
7FFFFFFFh
SINC FILTER(2)
VREF = 4.096 V
3A980000h
VIN (V)
≥2.5 V × (231 –1) / 231 / Gain
2.5 V / (Gain × (231 –1))
0
VREF = 2.5 V
3FFFFFFFh
<00000001h
00000000h
>FFFFFFFFh
C0000000h
VREF = 5 V
30000000h
<00000001h
00000000h
>FFFFFFFFh
D0000000h
<00000001h
00000000h
00000001h
00000000h
–2.5 V / (Gain × 231
≤–2.5 V / Gain
)
>FFFFFFFFh
C5680000h
FFFFFFFFh
80000000h
(1) Excluding the effects of reference voltage error, noise, linearity, offset, and gain errors.
(2) In buffer operation when VREF = 4.096 V or 5 V, the data from the sinc filter are scaled 66.6% compared to PGA mode. Because of the
relatively low value of OSR, full 32-bit resolution is not available in sinc filter operation. When overdriven, the sinc filter continues to
output code values beyond nominal ± full-scale until the point of modulator saturation.
8.5.3 Commands
表 8-11 lists the commands for the ADC. Most commands are one byte in length. However, the number of bytes
for the register read and write commands depend on the amount of register data specified in the command.
表8-11. Command Descriptions
MNEMONIC
WAKEUP
STANDBY
SYNC
TYPE
DESCRIPTION
BYTE 1(1)
BYTE 2
Control
Control
Control
Control
Data
Wake from standby mode or NOP
Enter standby (software power-down mode)
Synchronize
0000 000x (00h or 01h)
0000 001x (02h or 03h)
0000 010x (04h or 5h)
0000 011x (06h or 07h)
0001 0010 (12h)
—
—
—
—
—
RESET
Reset
RDATA
Read conversion data
RREG
Register
Register
Calibration
Calibration
Read nnnn registers beginning at address rrrr 0010 rrrr (20h + rrrr)(2)
Write nnnn registers beginning at address rrrr 0100 rrrr (40h + rrrr)(2)
0000 nnnn (00h + nnnn)(3)
WREG
0000 nnnn (00h + nnnn)(3)
OFSCAL
GANCAL
Offset calibration
Gain calibration
0110 0000 (60h)
0110 0001 (61h)
—
—
(1) x = Don't care.
(2) rrrr = Starting address for register read and write commands.
(3) nnnn = Number of registers to be read or written –1. For example, to read or write three registers, nnnn = 2.
8.5.3.1 Single Byte Command
图 8-23 shows the general format of a single byte command (for the response bytes of the RDATA command,
see the RDATA command).
CS
8
SCLK
DIN
Command
图8-23. Single Byte Command Format
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8.5.3.2 WAKEUP: Wake Command
The WAKEUP command exits standby mode to resume normal operation. If the ADC is already powered, the
command is no operation (NOP). When exiting standby mode, the ADC requires resynchronization. See the
Power-Down Mode section for details of power-down mode.
8.5.3.3 STANDBY: Software Power-Down Command
The STANDBY command enters the software power-down mode. The ADC exits software power-down mode by
the WAKEUP command. See the Power-Down Mode section for details of power-down mode.
8.5.3.4 SYNC: Synchronize Command
The SYNC command synchronizes the ADC. Synchronization occurs at the eighth bit of the SYNC command
byte. When synchronized, the current conversion is stopped and restarted. In order to synchronize multiple
ADCs by software command, send the command simultaneously to all devices. The SYNC pin must be high
when using the command. See the Synchronization section for details of synchronization.
8.5.3.5 RESET: Reset Command
The RESET command resets the ADC. See the Reset section for details of the reset operation.
8.5.3.6 Read Data Direct
There are two methods in which to read conversion data: read data direct and read data by command.
Read data direct does not require a command, instead after DRDY falls low, simply apply SCLK to read the data.
图 8-24 shows the read data direct operation. When DRDY falls low, take CS low to start the read operation. CS
low causes DOUT to transition from tri-state mode to the output of the data MSB. Data are read on the rising
edge of SCLK and updated on the falling edge of SCLK. DRDY returns high on the first falling edge of SCLK.
DOUT is low after 32 data bits are read. To read the same data again before new data are available, use the
RDATA command.
Keep DIN low when reading conversion data. If the RDATA (read conversion data) or RREG (read register data)
command is sent, output data are interrupted in response to the command. If DRDY falls low during the read
operation, the new data are lost unless a minimum of three bytes of the old data are read.
DRDY
CS
16
8
24
32
SCLK
DIN
00h
00h
00h
00h
DOUT
MSB-2 Data
MSB Data
MSB-1 Data
LSB Data
图8-24. Read Data Direct
8.5.3.7 RDATA: Read Conversion Data Command
The RDATA command (图 8-25) is useful to re-read data within the same conversion period or to read data
interrupted by a read register command. In both cases, DRDY is high because DRDY is driven high on the first
SCLK of the previous operation. If DRDY is high, the first output byte is zero followed by data. If low, the first
output byte is byte 1 of the conversion data, which is restarted for output byte 2.
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DRDY
CS
16
40
8
24
32
SCLK
DIN
12h
00h
00h
00h
00h
00h
DOUT
MSB-1 Data
MSB Data
MSB-2 Data
LSB Data
图8-25. Read Conversion Data by Command
8.5.3.8 RREG: Read Register Command
The RREG command reads register data. The command is comprised of two bytes followed by output of the
designated number of register bytes. The ADC auto-increments the address up to the number of registers
specified in byte 2 of the command. The incrementing address does not wrap. The first byte of the command is
the opcode added to the register starting address, and the second byte is the number of registers to read minus
one.
• First command byte: 0010 rrrr, where rrrr is the starting register address
• Second command byte: 0000 nnnn, where nnnn is the number of registers to read minus one
图 8-26 shows an example of a three-register read operation starting at register address 01h. The first register
data appears on DOUT at the 16th falling edge of SCLK. The data are latched on the rising edge of SCLK.
CS
16
40
8
24
32
SCLK
DIN
21h
00h
00h
00h
02h
DOUT
don‘t care
Reg 01h Data
don‘t care
Reg 02h Data
Reg 03h Data
图8-26. Read Register Data
8.5.3.9 WREG: Write Register Command
The WREG command is used to write register data. The command is two bytes followed by the designated
number of register bytes to be written. The ADC auto-increments the address up to the number of registers
specified in the command. The incrementing address does not wrap. The first byte of the command is the
opcode added to the register starting address, and the second byte is the number of registers to write minus
one.
First command byte: 0100 rrrr, where rrrr is the starting address of the first register.
Second command byte: 0000 nnnn, where nnnn is the number of registers to write minus one.
Data bytes: Depending on the number of registers specified.
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图8-27 shows an example of a three-register write operation starting at register address 01h.
CS
16
40
8
24
32
SCLK
DIN
Reg 01h Data
41h
02h
Reg 02h Data
Reg 03h Data
图8-27. Write Register Data
8.5.3.10 OFSCAL: Offset Calibration Command
The OFSCAL command performs offset calibration. See the Calibration Procedure section for details of
operation.
8.5.3.11 GANCAL: Gain Calibration Command
The GANCAL command performs a gain calibration. See the Calibration Procedure section for details of
operation.
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8.6 Register Map
Collectively, the registers contain all the information needed to configure the device (such as data rate, filter
mode, specific reference voltage, and so on). The registers are accessed by the read and write commands
(RREG and WREG). Registers can be accessed individually, or accessed in multiples given by the number of
registers specified in the command field.
Changes made to certain register bits result in a filter reset, thus requiring resynchronization of the ADC. See the
Synchronization section for details.
表8-12. Register Map
ADDRESS
00h
REG LINK
ID/SYNC
CONFIG0
CONFIG1
HPF0
RESET
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
DEVID[2:0]
PHASE
BIT 1
BIT 0
xxxx0000b
00010010b
00000000b
00110010h
00000011b
00000000b
00000000b
00000000b
00000000b
00000000b
01000000b
000xx000b
00000000b
10000000b
REVID[3:0]
SYNC
01h
MODE[1:0]
DR[2:0]
FILTR[1:0]
GAIN[2:0]
02h
MUX[2:0]
REF[1:0]
HPF[7:0]
03h
04h
HPF1
HPF[15:8]
OFFSET[7:0]
OFFSET[15:8]
OFFSET[23:16]
GAIN[7:0]
05h
OFFSET0
OFFSET1
OFFSET2
GAIN0
06h
07h
08h
09h
GAIN1
GAIN[15:8]
0Ah
0Bh
0Ch
0Dh
GAIN2
GAIN[23:16]
GPIO
RESERVED
GPIO1_DAT GPIO0_DAT GPIO1_DIR GPIO0_DIR RESERVED
SRC0
SRC[7:0]
SRC1
SRC[15:8]
8.6.1 Register Descriptions
表8-13 shows the register access codes for the ADS1285 registers.
表8-13. ADS1285 Access Codes
Access Type
Code
R
Description
R
Read
R-W
W
R/W
W
Read or write
Write
-n
Value after reset or the default value
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8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
图8-28. ID/SYNC Register
7
6
5
4
3
2
1
0
REVID[3:0]
R-xxxxb
DEVID[2:0]
R-000b
SYNC
R/W-0b
表8-14. ID/SYNC Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
REVID[3:0]
R
xxxxb
Factory-programmed die revision.
These bits identify the revision of the die. The die revision is
subject to change without notification.
3:1
0
DEVID[2:0]
SYNC
R
000b
0b
Factory-programmed device identification.
These bits identify the ADC.
000b = ADS1285
R/W
Synchronization mode selection.
See the Synchronization section for details.
0b = Pulse-sync mode
1b = Continuous-sync mode
8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
图8-29. CONFIG0 Register
7
6
5
4
3
2
1
0
MODE[1:0]
R/W-00b
DR[2:0]
R/W-010b
PHASE
R/W-0b
FILTR[1:0]
R/W-10b
表8-15. CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:6
MODE[1:0]
R/W
00b
Power mode selection.
See the Power Modes section for details.
00b = High
01b = Mid
10b = Low
11b = Reserved
5:3
DR[2:0]
R/W
010b
Data rate selection.
See the Digital Filter section for details.
000b = 250 SPS (125 SPS in low-power mode)
001b = 500 SPS (250 SPS in low-power mode)
010b = 1000 SPS (500 SPS in low-power mode)
011b = 2000 SPS (1000 SPS in low-power mode)
100b = 4000 SPS (2000 SPS in low-power mode)
101b–111b = Reserved
2
PHASE
R/W
R/W
0b
FIR filter phase selection.
See the Digital Filter section for details.
0b = Linear phase
1b = Minimum phase
1:0
FILTR[1:0]
10b
Digital filter configuration.
See the Digital Filter section for details.
00b = Reserved
01b = Sinc filter output
10b = FIR filter output
11b = FIR + IIR filter output
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8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
图8-30. CONFIG1 Register
7
6
5
4
3
2
1
0
MUX[2:0]
R/W-000b
REF[1:0]
R/W-00b
GAIN[2:0]
R/W-000b
表8-16. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7:5
MUX[2:0]
R/W
000b
Input MUX selection.
See the Analog Input section for details.
000b = Input 1
001b = Input 2
010b = Internal short with a 400-Ωresistor
011b = Input 1 and input 2
100b = Reserved
101b = Internal short with a 0-Ωresistor
110b, 111b = Reserved
4:3
2:0
REF[1:0]
R/W
R/W
00b
Select reference voltage operation.
See the Voltage Reference Input section for details.
00b = 5 V
01b = 4.096 V
10b = 2.5 V
11b = Reserved
GAIN[2:0]
000b
PGA gain selection.
See the PGA and Buffer section for details.
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = Buffer operation
8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
图8-31. HPF0 Register
7
6
5
4
3
2
2
1
0
0
HPF[7:0]
R/W-32h
图8-32. HPF1 Register
7
6
5
4
3
1
HPF[15:8]
R/W-03h
表8-17. HPF0, HPF1 Registers Field Description
Bit
15:0
Field
Type
Reset
Description
HPF[15:0]
R/W
0332h
High-pass filter programming.
These registers program the corner frequency of the high-pass
filter. See the HPF Stage section for details.
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8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers
(Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
图8-33. OFFSET0 Register
7
7
7
6
6
6
5
5
5
4
3
2
2
2
1
1
1
0
0
0
OFFSET[7:0]
R/W-00h
图8-34. OFFSET1 Register
4
3
OFFSET[15:8]
R/W-00h
图8-35. OFFSET2 Register
4
3
OFFSET[23:16]
R/W-00h
表8-18. OFFSET0, OFFSET1, OFFSET2 Registers Field Description
Bit
23:0
Field
Type
Reset
Description
OFFSET[23:0]
R/W
000000h
Offset calibration.
These bits are the 24-bit offset calibration word. The format is
2's-complement coding. The ADC subtracts the value of offset
from the conversion result prior to the gain calibration operation.
See the Offset and Gain Calibration section for details.
8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers
(Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
图8-36. GAIN0 Register
7
7
7
6
6
6
5
5
5
4
3
2
2
2
1
1
1
0
0
0
GAIN[7:0]
R/W-00h
图8-37. GAIN1 Register
4
3
GAIN[15:8]
R/W-00h
图8-38. GAIN2 Register
4
3
GAIN[23:16]
R/W-40h
表8-19. GAIN0, GAIN1, GAIN2 Registers Field Description
Bit
23:0
Field
Type
Reset
Description
GAIN[23:0]
R/W
400000h
Gain calibration.
These bits are the 24-bit, gain calibration word. Gain calibration
is straight binary coding. The register value is divided by
400000h (222) and multiplied with the conversion data. The gain
operation occurs after the offset operation. See the Offset and
Gain Calibration section for details.
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8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
图8-39. GPIO Register
7
6
5
4
3
2
1
0
RESERVED
R/W-000b
GPIO1_DAT
R/W-xb
GPIO0_DAT
R/W-xb
GPIO1_DIR
R/W-0b
GPIO0_DIR
R/W-0b
RESERVED
R/W-0b
表8-20. GPIO Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
000b
xb
Description
7:5
4
RESERVED
GPIO1_DAT
Always write 000b.
GPIO1 data.
See the GPIO section for details.
0b = GPIO1 is low
1b = GPIO1 is high
3
2
1
0
GPIO0_DAT
GPIO1_DIR
GPIO0_DIR
RESERVED
R/W
R/W
R/W
R/W
xb
0b
0b
0b
GPIO0 data.
0b = GPIO0 is low
1b = GPIO0 is high
GPIO1 direction.
0b = GPIO1 is an input
1b = GPIO1 is an output
GPIO0 direction.
0b = GPIO0 is an input
1b = GPIO0 is an output
Always write 0b.
8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
图8-40. SRC0 Register
7
6
5
4
3
2
1
0
0
SRC[7:0]
R/W-00h
图8-41. SRC1 Register
7
6
5
4
3
2
1
SRC[15:8]
R/W-80h
表8-21. SRC0, SRC1 Registers Field Description
Bit
15:0
Field
Type
Reset
Description
SRC[15:0]
R/W
8000h
Sample rate converter.
These registers program the sample rate converter. See the
Sample Rate Converter section for details of operation.
8000h = SRC function is disabled
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The ADS1285 is a high-resolution ADC designed for low-power seismic data acquisition equipment. Optimizing
performance requires special attention to the support circuitry and printed-circuit board (PCB) layout. As much
as possible, locate noisy circuit components (such as microcontrollers, oscillators, switching regulators, and so
forth) away from the ADC input circuit components, reference voltage, and the ADC clock signal.
9.2 Typical Application
2.5 V
5 V
1 ꢀF
0.1 ꢀF
0.1 ꢀF
1 ꢀF
11
12
AVDD2
AVDD1
3.3 V
ADS1285
19
17
20
IOVDD
1 ꢀF
5 V
0.1 ꢀF
1
2
CAPD
AINP1
AINN1
CAPI
0.22 ꢀF
DAC SPI
DAC1282
CLK
Clock Input
21
23
BAS70
14
CS
DIN
0.1 µF
ADC SPI
5 V
24
22
DOUT
SCLK
R5
100
R3
100
3
25
AINP2
DRDY
SYNC
R1
20 k
C1
26
27
C3
1000 pF
C0G
100 pF C0G
Geophone
RESET
Control
R4
100
R2
20 k
R6
100
28
15
16
C2
PWDN
GPIO0
GPIO1
100 pF C0G
4
5
AINN2
CAPP
100 k
Optional ESD
Protection
100 k
7
CAPBP
10 nF
C0G
6
47 nF
C0G
CAPN
CAPR
TVS0701
0.1 µF
5 V
–
+
8
31
0.1 µF
CAPBN
1.69 M
2.5 V
47 nF
C0G
0.1 µF
OPA391
1 M
9
R7
100
5 V
CAPC
30
29
VIN
4.7 nF
REF6241SF
REFP
REFN
EN
SS
C4
+
FLT
10 ꢀF
1 ꢀF
THERMAL
PAD
68 µF
0.1 ꢀF
1 ꢀF
60 m
10
32
AVSS
120 k
Optional Reference Voltage
Noise Filter
AGND
13
DGND
18
图9-1. Geophone Input Application Example
9.2.1 Design Requirements
图 9-1 depicts a typical application of a geophone input circuit. The application shows the ADC operating with a
5-V power supply and a 2.5-V level-shift voltage applied to the ADC inputs. The goal of this evaluation is to
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analyze the effect of noise resulting from source resistance. The source resistance is the sum of the series input
resistors and the geophone output resistance.
9.2.2 Detailed Design Procedure
Referring to 图 9-1, Schottky diodes (BAS70 or equivalent) protect the ADC inputs from voltage overloads. The
ADC inputs are protected from ESD events by the optional ESD protection diodes (TVS0701). The geophone
signal is level-shifted to mid-supply by driving the input termination resistors (R1 and R2) common point to 2.5 V.
The level-shift voltage is derived from the reference voltage and is buffered by the OPA391 op amp. The input
termination resistors also provide the input bias current return path for the ADC inputs.
The input signal is filtered to reduce out-of-band noise. The filter is comprised of common-mode and differential
sections. The common-mode section filters noise common to both inputs, consisting of R3, R4, C1, and C2. The
differential section filters differential noise, consisting of R3 through R6 and C3. The resistor values are kept low
to reduce thermal noise.
The REF6241 4.096-V voltage reference is used. The ADC must be programmed to match the value of the
reference voltage. The optional noise filter consisting of R7 and C3 reduces reference noise. Resistor R7
increases gain error resulting from the impedance of the reference input.
The AVDD1 power supply voltage = 5 V, with AVSS connected to AGND. The AVDD2 voltage is 2.5 V to
minimize power consumption. If IOVDD = 1.8V, connect the CAPD pin to IOVDD.
Besides the power supply pins, place additional capacitors at certain pins. Capacitors are required between
CAPP – CAPN, REFP – REFN, and at the CAPBP, CAPBN, CAPI, CAPR, CAPC, and CAPD pins with the
capacitance values given in 图9-1. The CAPP –CAPN, CAPBP, and CAPBN capacitors are C0G type.
The DAC1282 provides a low-distortion signal to test THD performance, and through the DAC1282 dc test
mode, test geophone impulse response. Increase the value of the DAC1282 capacitors CAPP and CAPN to 10
nF to optimize the ADS1285 THD test performance. See the DAC1282 data sheet for additional circuit details.
9.2.3 Application Curves
表 9-1 lists the effect of source resistance (RS) and device input current noise on dynamic range performance.
Selected values of RS and input current noise, obtained from the input current noise distribution of 图 9-2 (1.5
pA/√Hz and 3 pA/√Hz), are evaluated. Thermal noise voltage of the source resistance, input current noise ×
source resistance, and ADC input-referred noise voltage are summed as RMS values to derive the total noise.
Dynamic range is calculated from the total noise result.
33
30
27
24
21
18
15
12
9
6
3
0
PGA Input Current Noise Density (pA/Hz)
图9-2. PGA Input Current Noise Distribution
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表9-1. Source Resistance Noise
GAIN
in NOISE
(pA/√Hz)
RS (Ω)
RS NOISE (μV) in × RS NOISE (μV) ADC SELF-NOISE (μV) TOTAL NOISE (μV)
1.5
3
0
0.44
132.1
132.1
120.1
120.1
132.0
132.0
118.8
118.4
131.5
130.8
114.8
112.0
1
0.44
0.11
0.44
0.11
0.44
0.11
0
0.44
0
0
1.5
3
0
0.11
16
1
0
0.11
1.5
3
0.024
0.048
0.024
0.048
0.11
0.22
0.11
0.21
0.445
0.446
0.127
0.134
0.472
0.508
0.202
0.277
1000
5000
0.06
0.13
1.5
3
16
1
1.5
3
1.5
3
16
Data for the analysis is shown for low-power mode operation over a 206-Hz noise bandwidth (fDATA = 500 SPS).
For PGA gain = 1, 5000-Ω source resistance has a minor effect on dynamic range performance. However, at
PGA gain = 16, dynamic range performance can degrade from –5 dB to –8 dB depending on the level of
device input current noise. 1000-Ω source resistance has 1.6-dB degradation at gain = 16 for input current noise
density = 3 pA/√Hz.
9.3 Power Supply Recommendations
The ADC has four power supplies: AVDD1, AVDD2, AVSS, and IOVDD. Among the power-supply options, the
number of power supplies can be reduced to a single 3.3-V supply used for AVDD1, AVDD2, and IOVDD, with
AVSS connected to ground. Be aware that 3.3-V operation limits the reference voltage to 2.5 V and requires
using the buffer for gain = 1.
The power supplies can be sequenced in any order. The ADC is held in reset until the power supplies have
crossed the retrospective power-on voltage thresholds and the clock signal is applied (see 图 6-8 for details of
the voltage thresholds).
9.3.1 Analog Power Supplies
The ADC has three analog power supplies, AVDD1, AVDD2, and AVSS, all of which must be well regulated and
free from switching power-supply noise (voltage ripple < 1 mV). The AVDD1 power-supply voltage is relative to
AVSS and powers the PGA and buffer. AVSS is the negative power supply. The ADC can be configured for
single-supply operation with AVDD1 = 5 V or 3.3 V with AVSS connected to ground. Because the minimum
voltage of AVDD1 to AGND = 2.375 V, dual-supply operation is only possible when AVDD1 – AVSS = ±2.5 V.
Single-power supply operation requires a level-shift voltage at the geophone input through the input termination
resistors. The level-shift voltage is typically equal to AVDD1 / 2. Bypass AVDD1 with 1-μF and 0.1-μF parallel
capacitors to AVSS.
The AVDD2 power supply powers the modulator. To simplify system power management, AVDD2 can be
connected AVDD1, regardless whether AVDD1 and AVSS are configured for single- or dual-supply operation
(AVDD2 voltage range is 2.375 V to 5.25 V with respect to AGND). Bypass AVDD2 with 1-μF and 0.1-μF
parallel capacitors to AGND.
9.3.2 Digital Power Supply
IOVDD is the digital power supply. IOVDD is the digital pin I/O voltage and also powers the digital core by an
1.8-V low-dropout regulator (LDO). The LDO output is the CAPD pin and is bypassed with a 0.22-µF capacitor to
DGND. Do not externally load the CAPD voltage output. Bypass the IOVDD pin with 1-μF and 0.1-μF parallel
capacitors to DGND.
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If IOVDD is in the range of 1.65 V to 1.95 V, tie the IOVDD and CAPD pins together. This connection forces the
internal LDO off, thereby the IOVDD voltage now directly powers the digital core. Pay close attention to the
absolute maximum voltage rating of IOVDD driving the CAPD pin to avoid damaging the device.
9.3.3 Grounds
The ADC has two ground pins, AGND and DGND. Connect the AGND and DGND pins together at the ADC to a
single ground plane using short direct connections.
9.3.4 Thermal Pad
The thermal pad does not carry device current but must be soldered and connected to the most negative power-
supply voltage (AVSS). Because of the low power dissipation, PCB thermal vias can be omitted to provide space
for bottom layer components under the device.
9.4 Layout
9.4.1 Layout Guidelines
图 9-3 shows the layout of the geophone input application example of 图 9-1. In most cases, a single unbroken
ground plane connecting the grounds of the analog and digital components is preferred. A four-layer PCB is
used, with the inner layers dedicated for ground and power-supply planes. Low resistance power-supply planes
are necessary to maintain THD performance.
Connect the REFN pin of the ADC directly to the ground terminal of the voltage reference to avoid ground noise
coupling. Similarly, avoid ground noise between the tie-points of termination resistors R1 and R2 by connecting
the resistors together first, then connect to ground (dual-supply operation).
Place the smaller of the parallel power-supply bypass capacitors closest to the device supply pins. The thermal
pad of the package connects to the most negative power-supply voltage (AVSS). 图 9-3 shows single-supply
operation, with AVSS tied to AGND. In this case, the thermal pad connects to AGND. For dual-supply operation,
connect the thermal pad to AVSS.
9.4.2 Layout Example
5 V
REF6241
DAC1282
Test Signal
5 V
BAS70
5 V
PWDN
RESET
SYNC
TVS0701
DRDY
-
DOUT
DIN
Signal
ADS1285
SCLK
Input
CS
CLK
3.3 V
IOVDD
TVS0701
GPIO1
GPIO0
BAS70
5 V
5 V
2.5 V
AVDD1
AVDD2
图9-3. Example Layout
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10 Device and Documentation Support
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要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
60
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Product Folder Links: ADS1285
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1285IRHBR
ADS1285IRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jan-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1285IRHBR
ADS1285IRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
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