ADS1286PC [TI]

12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER;


型号：	ADS1286PC
厂家：	TEXAS INSTRUMENTS
描述：	12-Bit Micro Power Sampling ANALOG-TO-DIGITAL CONVERTER 光电二极管转换器
文件：	总17页 (文件大小：509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS1286

12-Bit Micro Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

DESCRIPTION

● SERIAL INTERFACE

The ADS1286 is a 12-bit, 20kHz analog-to-digital

converter with a differential input and sample and hold

amplifier and consumes only 250µA of supply cur-

rent. The ADS1286 offers an SPI and SSI compatible

serial interface for communications over a two or three

wire interface. The combination of a serial two wire

interface and micropower consumption makes the

ADS1286 ideal for remote applications and for those

requiring isolation.

● GUARANTEED NO MISSING CODES

● 20kHz SAMPLING RATE

● LOW SUPPLY CURRENT: 250µA

APPLICATIONS

● REMOTE DATA ACQUISITION

● ISOLATED DATA ACQUISITION

● TRANSDUCER INTERFACE

The ADS1286 is available in a 8-pin plastic mini DIP

and a 8-lead SOIC.

● BATTERY OPERATED SYSTEMS

Control

SAR

V_REF

D_OUT

+In

CDAC

Serial

Interface

DCLOCK

CS/SHDN

–In

Comparator

S/H Amp

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 Internet: http://www.burr-brown.com/

•

Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

PDS-1335B

Printed in U.S.A. October, 1998

SBAS053

SPECIFICATIONS

At T_A= T_MINto T_MAX, +V_CC= +5V, V_REF= +5V, f_SAMPLE= 12.5kHz, , f_CLK= 16 • f_SAMPLE, unless otherwise specified.

ADS1286, ADS1286A

ADS1286K, ADS1286B

ADS1286C, ADS1286L

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ANALOG INPUT

Full-Scale Input Range

Absolute Input Voltage

+In – (–In)

+In

–0.2

V_REF

V_CC+0.2

+0.2

✻

–In

Capacitance

Leakage Current

±1

✻

µA

SYSTEM PERFORMANCE

Resolution

No Missing Codes

Integral Linearity

Differential Linearity

Offset Error

Gain Error

Noise

Power Supply Rejection

✻

Bits

✻

±1

±0.5

0.75

±2

±1.0

±3

✻

±0.75

✻

±0.5

±0.25

✻

±1

±0.75

✻

LSB

µVrms

±8

✻

SAMPLING DYNAMICS

Conversion Time

Acquisition Time

✻

Clk Cycles

kHz

1.5

✻

Small Signal Bandwidth

500

✻

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

_IN= 5.0Vp-p at 1kHz

_IN= 5.0Vp-p at 5kHz

_IN= 5.0Vp-p at 1kHz

–85

–83

✻

SINAD

Spurious Free Dynamic Range

REFERENCE INPUT

REF Input Range

Input Resistance

1.25

2.5

5000

0.01

2.4

V_CC+0.05V

✻

CS = V_CC

CS = GND, f_CLK= 0Hz

CS = V_CC

t_CYC≥ 640µs, f_CLK≤ 25kHz

t_CYC= 80µs, f_CLK= 200kHz

MΩ

µA

Current Drain

2.5

✻

2.4

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels:

V_IH

V_IL

V_OH

CMOS

✻

I_IH= +5µA

I_IL= +5µA

I_OH= 250µA

I_OL= 250µA

0.0

+V_CC

0.8

+V_CC

0.4

✻

V_OL

0.0

Data Format

Straight Binary

✻

POWER SUPPLY REQUIREMENTS

Power Supply Voltage

V_CC

+4.50

200

250

5.25

400

500

✻

Quiescent Current, V_ANA

t_CYC≥ 640µS, f_CLK≤ 25kHz

µA

t_CYC= 90µS, f_CLK= 200kHz

Power Down

CS = V_CC

TEMPERATURE RANGE

Specified Performance

ADS1286, K, L

ADS1286A, B, C

–40

+70

+85

✻

°C

✻ Specifications same as grade to the left.

TIMING CHARACTERISTICS

f_CLK= 200kHz, T_A= T_MINto T_MAX

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

t_SMPL

t_{SMPL (MAX)}

t_CONV

t_dDO

t_dis

Analog Input Sample Time

Maximum Sampling Frequency

Conversion Time

See Operating Sequence

ADS1286

1.5

2.0

Clk Cycles

kHz

See Operating Sequence

See Test Circuits

Clk Cycles

Delay TIme, DCLOCK↓ to D_OUTData Valid

Delay TIme, CS↑ to D_OUTHi-Z

Delay TIme, DCLOCK↓ to D_OUTEnable

Output Data Remains Valid After DCLOCK↓

D_OUTFall Time

150

See Test Circuits

t_en

See Test Circuits

100

t_hDO

t_f

C_LOAD= 100pF

See Test Circuits

100

t_r

D_OUTRise Time

See Test Circuits

t_CSD

t_SUCS

Delay Time, CS↓ to DCLOCK↓

Delay Time, CS↓ to DCLOCK↑

See Operating Sequence

ADS1286

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

ELECTROSTATIC

DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-

formance degradation to complete device failure. Burr-

Brown Corporation recommends that all integrated circuits

be handled and stored using appropriate ESD protection

methods.

+V_CC..................................................................................................... +6V

Analog Input ....................................................... –0.3V to (+V_CC+ 300mV)

Logic Input ......................................................... –0.3V to (+V_CC+ 300mV)

Case Temperature ......................................................................... +100°C

Junction Temperature .................................................................... +150°C

Storage Temperature ..................................................................... +125°C

External Reference Voltage .............................................................. +5.5V

NOTE: (1) Stresses above these ratings may permanently damage the device.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet

published specifications.

PIN CONFIGURATION

V_REF

+In

+V_CC

DCLOCK

D_OUT

ADS1286

–In

GND

CS/SHDN

8-Pin Mini PDIP

8-Lead SOIC

PIN ASSIGNMENTS

NAME

DESCRIPTION

V_REF

+In

Reference Input.

Non Inverting Input.

–In

Inverting Input. Connect to ground or remote ground sense point.

Ground.

GND

CS/SHDN

D_OUT

Chip Select when low, Shutdown Mode when high.

The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The

second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.

Data Clock synchronizes the serial data transfer and determines conversion speed.

DCLOCK

+V_CC

Power Supply.

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING

NUMBER⁽¹⁾

INTEGRAL

LINEARITY

TEMPERATURE

RANGE

PRODUCT

PACKAGE

ADS1286P

±2

±1

±2

±1

±2

±1

±2

±1

0°C to +70°C

Plastic DIP

SOIC

006

182

006

182

ADS1286PK

ADS1286PL

ADS1286U

0°C to +70°C

ADS1286UK

ADS1286UL

ADS1286PA

ADS1286PB

ADS1286PC

ADS1286UA

ADS1286UB

ADS1286UC

0°C to +70°C

SOIC

0°C to +70°C

SOIC

–40°C to +85°C

Plastic DIP

SOIC

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix

C of Burr-Brown IC Data Book.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS1286

TYPICAL PERFORMANCE CURVES

At T_A= +25, V_CC= +5V, V_REF= +5V, f_SAMPLE= 12.5kHz, f_CLK= 16 • f_SAMPLE, unless otherwise specified.

REFERENCE CURRENT vs SAMPLE RATE

REFERENCE CURRENT vs TEMPERATURE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

2.5

2.0

1.5

1.0

0.5

–55

–40

–25

Sample Rate (kHz)

Temperature (°C)

CHANGE IN OFFSET vs TEMPERATURE

CHANGE IN OFFSET vs REFERENCE VOLTAGE

4.5

0.6

0.4

3.5

0.2

2.5

–0.2

–0.4

–0.6

1.5

0.5

–40

–25

Reference Voltage (V)

Temperature (°C)

CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL

LINEARITY vs REFERENCE VOLTAGE

CHANGE IN GAIN vs REFERENCE VOLTAGE

0.10

0.05

3.5

Change in Differential

Linearity (LSB)

0.00

2.5

–0.05

–0.10

–0.15

–0.20

1.5

Change in Integral

Linearity (LSB)

0.5

Reference Voltage (V)

ADS1286

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25, V_CC= +5V, V_REF= +5V, f_SAMPLE= 12.5kHz, f_CLK= 16 • f_SAMPLE, unless otherwise specified.

EFFECTIVE NUMBER OF BITS

vs REFERENCE VOLTAGE

DIFFERENTIAL LINEARITY ERROR vs CODE

11.75

11.5

11.25

3.0

2.0

1.0

10.75

10.5

10.25

–1.0

–2.0

–3.0

0.1

2048

Code

4095

Reference Voltage (V)

SPURIOUS FREE DYNAMIC RANGE

AND SIGNAL-TO-NOISE RATIO vs FREQUENCY

SIGNAL-TO-(NOISE + DISTORTION)

vs FREQUENCY

100

Spurious Free Dynamic Range

Signal-to-Noise Ratio

0.1

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL

TOTAL HARMONIC DISTORTION vs FREQUENCY

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0.1

–40

–35

–30

–25

–20

–15

–10

–5

Frequency (kHz)

Input Level (dB)

ADS1286

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25, V_CC= +5V, V_REF= +5V, f_SAMPLE= 12.5kHz, f_CLK= 16 • f_SAMPLE, unless otherwise specified.

4096 POINT FFT

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

–25

–50

–75

–100

–125

0.1

–55

Frequency (kHz)

Reference Voltage (V)

POWER SUPPLY REJECTION vs RIPPLE FREQUENCY

V_RIPPLE= 20mV

CHANGE GAIN vs TEMPERATURE

–10

–20

–30

–40

–50

–60

–70

–80

–90

0.15

0.1

0.05

–0.05

–0.1

–0.15

–40

–25

100

1000

10000

Ripple Frequency (kHz)

Temperature (°C)

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

SUPPLY CURRENT vs TEMPERATURE

2.5

400

350

300

250

200

150

100

f_SAMPLE= 12.5kHz

1.5

f_SAMPLE= 1.6kHz

0.5

–55

–40

–25

–40

–25

Temperature (°C)

ADS1286

TYPICAL PERFORMANCE CURVES (CONT)

At T_A= +25, V_CC= +5V, V_REF= +5V, f_SAMPLE= 12.5kHz, f_CLK= 16 • f_SAMPLE, unless otherwise specified.

DIGITAL INPUT LINE THRESHOLD

vs SUPPLY VOLTAGE

INTEGRAL LINEARITY ERROR vs CODE

3.0

2.0

2.5

1.0

1.5

–1.0

–2.0

–3.0

0.5

2048

Code

4095

3.25 3.5 3.75

4.25 4.5 4.75

5.25 5.5

Supply Voltage (V)

INPUT LEAKAGE CURRENT vs TEMPERATURE

0.1

0.01

–55

–40

–25

Temperature (°C)

ADS1286

TIMING DIAGRAMS AND TEST CIRCUITS

1.4V

V_OH

V_OL

3kΩ

D_OUT

Test Point

t_r

t_f

100pF

C_LOAD

Voltage Waveforms for D_OUTRise and Fall Times t_r, and t_f

Load Circuit for t_dDO, t_r, and t_f

Test Point

DCLOCK

V_IL

V_CC

t_dDO

_disWaveform 2, t_en

3kΩ

D_OUT

V_OH

V_OL

t_disWaveform 1

D_OUT

100pF

C_LOAD

t_hDO

Voltage Waveforms for D_OUTDelay Times, t_dDO

Load Circuit for t_disand t_den

V_IH

CS/SHDN

DCLOCK

D_OUT

Waveform 1⁽¹⁾

90%

10%

t_dis

D_OUT

Waveform 2⁽²⁾

V_OL

D_OUT

B11

t_en

Voltage Waveforms for t_dis

NOTES: (1) Waveform 1 is for an output with internal conditions such that

the output is HIGH unless disabled by the output control. (2) Waveform 2

is for an output with internal conditions such that the output is LOW unless

disabled by the output control.

Voltage Waveforms for t_en

ADS1286

t_CYC

CS/SHDN

DCLOCK

POWER

DOWN

t_SUCS

t_CSD

NULL

BIT

NULL

BIT

HI-Z

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0⁽¹⁾

B11 B10 B9 B8

D_OUT

(MSB)

t_SMPL

t_CONV

t_DATA

Note: (1) After completing the data transfer, if further clocks are applied with CS

LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.

t_CYC

CS/SHDN

DCLOCK

D_OUT

t_SUCS

POWER DOWN

t_CSD

NULL

HI-Z

BIT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11

(2)

(MSB)

t_SMPL

t_CONV

t_DATA

Note: (2) After completing the data transfer, if further clocks are applied with CS

LOW, the ADC will output zeroes indefinitely.

t_DATA: During this time, the bias current and the comparator power down and the reference input

becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

FIGURE 1. ADS1286 Operating Sequence.

leaving the DCLOCK running to clock out the LSB first

data or zeroes. If the CS input is not running rail-to-rail, the

input logic buffer will draw current. This current may be

large compared to the typical supply current. To obtain the

lowest supply current, bring the CS pin to ground when it is

low and to supply voltage when it is high.

SERIAL INTERFACE

The ADS1286 communicates with microprocessors and other

external digital systems via a synchronous 3-wire serial inter-

face. DCLOCK synchronizes the data transfer with each bit

being transmitted on the falling DCLOCK edge and captured

on the rising DCLOCK edge in the receiving system. A falling

CS initiates data transfer as shown in Figure 1. After CS falls,

the second DCLOCK pulse enables D_OUT. After one null bit,

the A/D conversion result is output on the D_OUTline. Bringing

CS high resets the ADS1286 for the next data exchange.

1000

T_A= 25°C

_CC= 5V

V_REF= 5V

_CLK= 16 • f_SAMPLE

100

MICROPOWER OPERATION

With typical operating currents of 250µA and automatic

shutdown between conversions, the ADS1286 achieves ex-

tremely low power consumption over a wide range of

sample rates (see Figure 2). The auto-shutdown allows the

supply current to drop with sample rate.

0.1k

10k

100k

SHUTDOWN

Sample Rate (kHz)

The ADS1286 is equipped with automatic shutdown fea-

tures. The device draws power when the CS pin is LOW and

shuts down completely when the pin is HIGH. The bias

circuit and comparator powers down and the reference input

becomes high impedance at the end of each conversion

FIGURE 2. Automatic Power Shutdown Between Conver-

sions Allows Power Consumption to Drop with

Sample Rate.

ADS1286

MINIMIZING POWER DISSIPATION

REDUCED REFERENCE

OPERATION

In systems that have significant time between conversions,

the lowest power drain will occur with the minimum CS

LOW time. Bringing CS LOW, transferring data as quickly

as possible, and then bringing it back HIGH will result in the

lowest current drain. This minimizes the amount of time the

device draws power. After a conversion the A/D automati-

cally shuts down even if CS is held LOW. If the clock is left

running to clock out LSB-data or zero, the logic will draw a

small amount of current (see Figure 3).

The effective resolution of the ADS1286 can be increased

by reducing the input span of the converter. The ADS1286

exhibits good linearity and gain over a wide range of

reference voltages (see Typical Performance Curves “ Change

in Linearity vs Reference Voltage” and “Change in Gain vs

Reference Voltage”). However, care must be taken when

operating at low values of V_REFbecause of the reduced LSB

size and the resulting higher accuracy requirement placed on

the converter. The following factors must be considered

when operating at low V_REFvalues:

6.00

T_A= 25°C

V_CC= +5V

1. Offset

2. Noise

5.00

_REF= +5V

_CLK= 16 • f_SAMPLE

4.00

3.00

2.00

1.00

0.00

OFFSET WITH REDUCED V_REF

CS = LOW

(GND)

The offset of the ADS1286 has a larger effect on the output

code. When the ADC is operated with reduced reference

voltage. The offset (which is typically a fixed voltage)

becomes a larger fraction of an LSB as the size of the LSB

is reduced. The Typical Performance Curve “Change in

Offset vs Reference Voltage” shows how offset in LSBs is

related to reference voltage for a typical value of V_OS. For

example, a V_OSof 122µV which is 0.1 LSB with a 5V

reference becomes 0.5LSB with a 1V reference and 2.5LSBs

with a 0.2V reference. If this offset is unacceptable, it can be

corrected digitally by the receiving system or by offsetting

the negative input of the ADS1286.

CS HIGH

(V_CC

)

0.1

100

Sample Rate (kHz)

FIGURE 3. Shutdown Current with CS HIGH is Lower than

with CS LOW.

RC INPUT FILTERING

It is possible to filter the inputs with an RC network as

shown in Figure 4. For large values of C_FILTER(e.g., 1µF),

the capacitive input switching currents are averaged into a

net DC current. Therefore, a filter should be chosen with a

small resistor and large capacitor to prevent DC drops across

the resistor. The magnitude of the DC current is approxi-

mately I_DC= 20pF x V_IN/t_CYCand is roughly proportional to

V_IN. When running at the minimum cycle time of 64µs, the

input current equals 1.56µA at V_IN= 5V. In this case, a filter

resistor of 75Ω will cause 0.1LSB of full-scale error. If a

larger filter resistor must be used, errors can be eliminated

by increasing the cycle time.

NOISE WITH REDUCED V_REF

The total input referred noise of the ADS1286 can be

reduced to approximately 200µV peak-to-peak using a ground

plane, good bypassing, good layout techniques and minimiz-

ing noise on the reference inputs. This noise is insignificant

with a 5V reference but will become a larger fraction of an

LSB as the size of the LSB is reduced.

For operation with a 5V reference, the 200µV noise is only

0.15LSB peak-to-peak. In this case, the ADS1286 noise will

contribute virtually no uncertainty to the output code. How-

ever, for reduced references, the noise may become a signifi-

cant fraction of an LSB and cause undesirable jitter in the

output code. For example, with a 2.5V reference this same

200µV noise is 0.3LSB peak-to-peak. If the reference is

further reduced to 1V, the 200µV noise becomes equal to

0.8LSBs and a stable code may be difficult to achieve. In

this case averaging multiple readings may be necessary.

I_DC

R_FILTER

V_IN

ADS1286

C_FILTER

FIGURE 4. RC Input Filtering.

ADS1286

+5V

R₈

46kΩ

0.4V

0.3V

R₇

10Ω

R₉

1kΩ

R₁

150kΩ

OPA237

D₁

C₂

0.1µF

U₂

R₃

500kΩ

R₁₀

1kΩ

C₁

10µF

MUX

R₆

1MΩ

R₂

59kΩ

V_REF

0.2V

0.1V

DCLOCK

D_OUT

R₁₁

1kΩ

C₃

0.1µF

ADS1286

TC₁

A₀

TC₂

TC₃

CS/SHDN

A₁

Thermocouple

R₁₂

1kΩ

U₁

C₄

10µF

R₄

1kΩ

U₃

C₅

0.1µF

R₅

500Ω

µP

ISO Thermal Block

3-Wire

Interface

U₄

FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286.

+V_CC

REF200

(100µA)

0.1µF

V_REF

DCLOCK

D_OUT

µP

ADS1286

RTD

CS/SHDN

FIGURE 6. ADS1286 with RTD Sensor.

ADS1286

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

ADS1286P

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

N / A for Pkg Type

Level-2-260C-1 YEAR

ADS1286P

ADS1286PA

ACTIVE

Green (RoHS

& no Sb/Br)

ADS1286P

ADS1286PAG4

ADS1286PC

Green (RoHS

& no Sb/Br)

ADS1286P

Green (RoHS

& no Sb/Br)

ADS1286P

ADS1286PG4

ADS1286PK

Green (RoHS

& no Sb/Br)

ADS1286P

Green (RoHS

& no Sb/Br)

ADS1286P

ADS1286PL

Green (RoHS

& no Sb/Br)

ADS1286P

ADS1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

ADS1286U/2K5

ADS1286U/2K5G4

ADS1286UA

2500

Green (RoHS

& no Sb/Br)

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

ADS1286UA/2K5

ADS1286UA/2K5G4

ADS1286UAG4

ADS1286UB

ACTIVE

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ADS1286UBG4

ADS1286UC

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

Level-3-260C-168 HR

-40 to 85

ADS

1286U

ACTIVE

Green (RoHS

& no Sb/Br)

-40 to 85

ADS

1286U

ADS1286UCG4

Green (RoHS

& no Sb/Br)

ADS

1286U

ADS1286UG4

ADS1286UK

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

ADS

1286U

Green (RoHS

& no Sb/Br)

ADS

1286U

ADS1286UL

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

-40 to 85

ADS

1286U

ADS1286UL/2K5

2500

Green (RoHS

& no Sb/Br)

ADS

1286U

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS1286U/2K5

ADS1286UA/2K5

ADS1286UL/2K5

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS1286U/2K5

ADS1286UA/2K5

ADS1286UL/2K5

SOIC

2500

367.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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Applications

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www.ti.com/audio

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TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ADS1286PC [TI]

相关型号：

ADS1286PCG4

ADS1286PG4

ADS1286PG4

ADS1286PK

ADS1286PK

ADS1286PKG4

ADS1286PL

ADS1286PL

ADS1286U

ADS1286U

ADS1286U/2K5

ADS1286U/2K5