ADS1287 [TI]
用于地震监测和能源勘探且具有 PGA 的低功耗 1kSPS 单通道 Δ-Σ ADC;
| 型号： | ADS1287 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于地震监测和能源勘探且具有 PGA 的低功耗 1kSPS 单通道 Δ-Σ ADC |
| 文件： | 总63页 (文件大小：1662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ADS1287
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
配备可编程增益放大器的 ADS1287 低功耗、1000SPS、宽带宽
模数转换器
1 特性
3 说明
1
•
可选择工作模式
高分辨率模式：
ADS1287 器件是一款低功耗模数转换器 (ADC)，配备
集成式可编程增益放大器 (PGA) 和有限脉冲响应 (FIR)
数字滤波器。该 ADC 可满足地震监测设备的严苛要
求，这种设备需要在功耗较低的情况下实现高精度数字
化。
•
–
–
SNR：113dB（1000SPS，增益 = 1）
功耗：4.5mW
•
低功耗模式：
–
–
SNR：110dB（1000SPS，增益 = 1）
功耗：2.4mW
该 ADC 配备 可编程增益的高阻抗互补金属氧化物半
导体 (CMOS) 放大器，适用于通过范围较广的输入信
号（±2.5V 至 ±0.156V）将地震检波器和水听器传感器
直接连接到 ADC。
•
•
•
THD：-115dB
CMRR：115dB
高阻抗 CMOS PGA
该 ADC 包含内在稳定的四阶 Delta-Sigma (ΔΣ) 调制
器。调制器数字输出由内部的 FIR 数字滤波器过滤和
抽取，以生成 ADC 转换结果。
–
增益：1、2、4、8 和 16
•
•
数据传输速率：62.5SPS 至 1000SPS
灵活的数字滤波器：
–
正弦 + 有限脉冲响应 (FIR) + 无限脉冲响应
(IIR)（可选）
FIR 数字滤波器的数据速率高达每秒 1000 个样本
(SPS)。高通滤波器 (HPF) 可从转换结果中移除直流和
低频率分量。片上增益和偏移调节寄存器支持系统校
准。
–
–
线性和最小相位响应
可编程高通滤波器
•
•
•
•
•
偏移和增益校准
在高分辨率模式下，放大器、调制器和数字滤波器共消
耗 4.5mW（低功耗模式下为 2.4mW）。该 ADC 采用
紧凑型 5mm × 4mm VQFN 封装。该 ADC 的完全额
定工作温度范围为 –40°C 至 +85°C。
同步控制
与 SPI 兼容的接口
模拟电源：5V 或 ±2.5V
数字电源：2.5V 至 3.3V
器件信息(1)
2 应用
器件型号
ADS1287
封装
VQFN (24)
封装尺寸（标称值）
•
•
•
能量勘探
5.00mm × 4.00mm
无源地震监测
便携式仪表
(1) 要了解所有可用封装，请参阅数据表末尾的封装选项附录。
空白
功能方框图
AVDD
REFP REFN
CLK SYNC RESET
Control
DVDD
PWDN
DRDY
ADS1287
CS
AINP
AINN
DIN
DOUT
SCLK
Serial
Interface
Digital
Filter
ûꢀ ADC
PGA
VCOM
AVSS
DGND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS778
ADS1287
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 34
8.5 Programming........................................................... 40
8.6 Register Map........................................................... 45
Application and Implementation ........................ 51
9.1 Application Information............................................ 51
9.2 Typical Applications ................................................ 51
9.3 Initialization Set Up ................................................. 54
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 8
6.7 Switching Characteristics.......................................... 8
6.8 Typical Characteristics............................................ 12
Parameter Measurement Information ................ 18
7.1 Noise Performance ................................................. 18
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 20
8.3 Feature Description................................................. 21
9
10 Power Supply Recommendations ..................... 55
10.1 Analog Power Supplies......................................... 55
10.2 Digital Power Supply............................................. 55
10.3 Power-Supply Sequence....................................... 55
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
12 器件和文档支持 ..................................................... 56
12.1 接收文档更新通知 ................................................. 56
12.2 社区资源................................................................ 56
12.3 商标....................................................................... 56
12.4 静电放电警告......................................................... 56
12.5 Glossary................................................................ 56
13 机械、封装和可订购信息....................................... 57
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision A (November 2017) to Revision B
Page
•
已更改 将文档更改为面向 Web 的完整发布版........................................................................................................................ 1
Changes from Original (June 2017) to Revision A
Page
•
•
•
•
•
Added second row to tc(SC) parameter .................................................................................................................................... 8
Changed tw(SCH) and tw(SCL) parameters to be merged together, added second row to tw(SCH), tw(SCL) parameter .................. 8
Changed td(CLSY) unit from 1 / fCLK to ns.................................................................................................................................. 8
Added unit to tp(RSDR) and tp(PWDR) parameters of Switching Characteristics table.................................................................. 9
已更改 sinc filter block of Digital Filter and Output Code Processing figure from Decimate by 8 to 128 to Decimate
by 4 to 128 to include low-power mode setting.................................................................................................................... 25
•
•
已添加 fMOD = fCLK / 8 for low-power mode to first paragraph of Sinc Filter Stage section................................................... 26
已添加 sinc decimation ratio for low-power mode column and added high-resolution mode column header to Sinc
Filter Data Rates table.......................................................................................................................................................... 26
•
•
已更改 fMOD description in Equation 9................................................................................................................................... 26
已添加 sinc decimation ratio for low-power mode column and added high-resolution mode column header to FIR
Filter Data Rates table ......................................................................................................................................................... 27
2
Copyright © 2017–2019, Texas Instruments Incorporated
ADS1287
www.ti.com.cn
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
5 Pin Configuration and Functions
RHF Package
5-mm × 4-mm, 24-Pin VQFN
Top View
DRDY
DOUT
DIN
1
2
3
4
5
6
7
19
18
17
16
15
14
13
RESET
PWDN
REFP
REFN
AVSS
AVDD
AINN
Thermal
Pad
CS
SYNC
NC
DGND
Not to scale
Pin Functions
PIN
FUNCTION
DESCRIPTION
NO.
1
NAME
DRDY
DOUT
DIN
Digital output Data ready, active low
Digital output Serial data output
2
3
Digital input
Digital input
Digital input
—
Serial data input
4
CS
Serial interface select, active low
Synchronize, active high
No connection
5
SYNC
NC
6
7
DGND
CAPN
CAPP
NC
Ground
Digital ground
8
Analog output PGA negative output; connect a 10-nF C0G capacitor from CAPP to CAPN
Analog output PGA positive output; connect a 10-nF C0G capacitor from CAPP to CAPN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
—
—
No connection
No connection
NC
AINP
AINN
AVDD
AVSS
REFN
REFP
PWDN
RESET
DVDD
DGND
BYPAS
CLK
Analog input Positive analog input
Analog input Negative analog input
Analog
Analog
Positive analog power supply
Negative analog power supply
Analog input Negative reference input
Analog input Positive reference input
Digital input
Digital input
Digital
Power-down, active low
Reset, active low
Digital power supply
Ground
Digital ground (tie to digital ground plane)
Analog output Sub-regulator bypass; connect a 1-µF capacitor to DGND
Digital input
Digital input
Master clock input (1.024 MHz)
Serial interface clock input
SCLK
Electrically float the thermal pad. The thermal pad must be soldered to the PCB for optimum
mechanical strength. PCB layout vias are optional.
Thermal pad
—
Copyright © 2017–2019, Texas Instruments Incorporated
3
ADS1287
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
–0.3
–2.8
–0.3
MAX
6
UNIT
AVDD to AVSS
Power-supply voltage
AVSS to DGND
DVDD to DGND
AINx, REFx, CAPx
0.3
3.9
V
Analog input voltage
Digital input voltage
Input current
AVSS – 0.3 AVDD + 0.3
V
V
CS, SCLK, DIN, DOUT, DRDY, SYNC, RESET, CLK, PWDN,
BYPAS
DGND – 0.3 DVDD + 0.3
Continuous
Junction, TJ
Storage, Tstg
10
mA
150
Temperature
°C
–60
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2017–2019, Texas Instruments Incorporated
ADS1287
www.ti.com.cn
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
POWER SUPPLY
AVSS to DGND
Analog power supply
–2.6
4.75
2.25
0
V
AVDD to AVSS
5.25
Digital power supply
DVDD to DGND
3.6
V
PGA INPUT AND OUTPUT
VIN
Differential input voltage
Absolute input voltage(1)
Absolute output voltage
VIN = V(AINP) – V(AINN)
–VREF / Gain
AVSS + 1
VREF / Gain
AVDD – 1.25
AVDD – 0.4
V
V
V
V(AINx)
V(CAPx)
AVSS + 0.4
VOLTAGE REFERENCE INPUT
VREF
Differential reference input voltage
VREF = V(REFP) – V(REFN)
2.45
AVSS – 0.1
2.5
2.55
V(REFP) – 2.45
AVDD + 0.1
V
V
V
V(REFN)
V(REFP)
Negative reference input voltage
Positive reference input voltage
V(REFN) + 2.45
CLOCK INPUT
f(CLK)
External clock frequency
0.4
DGND
–45
1.024
1.05
DVDD
125
MHz
V
DIGITAL INPUTS
Input voltage
TEMPERATURE RANGE
Operating ambient temperature
°C
(1) Absolute input voltage is the signal voltage plus the common-mode voltage; see the Programmable Gain Amplifier (PGA) section.
6.4 Thermal Information
ADS1287
THERMAL METRIC(1)
RHF (VQFN)
24 PINS
30.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27.5
8.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
8.6
RθJC(bot)
1.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
5
ADS1287
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
www.ti.com.cn
6.5 Electrical Characteristics
maximum and minimum specifications apply from –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, f(CLK) = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-resolution
and low-power modes, chop enabled, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Chop disabled
10
50
50
100
20
20
5
Input current
pA
Chop enabled
Common-mode, chop disabled
Differential-mode, chop disabled
Differential-mode, chop enabled
Common-mode
Input resistance
GΩ
pF
Input capacitance
Differential-mode
PGA
High-resolution mode
Low-power mode
Chop disabled
15
25
25
Voltage noise density
nV/√Hz
1/f noise corner
Gain factors
Hz
V/V
kΩ
1, 2, 4, 8, 16
Nominal
1.7
10
Differential output impedance
PGA output capacitor
Tolerance
–15%
31
15%
nF
ADC
Resolution
FIR filter mode
Bits
nV/√Hz
SPS
High-resolution mode
Low-power mode
FIR filter mode
190
275
Voltage noise density
Data rate
fDATA
62.5, 125, 250, 500, 1000
SYSTEM PERFORMANCE
High-resolution mode, gain = 1
High-resolution mode, gain = 2
High-resolution mode, gain = 4
High-resolution mode, gain = 8
High-resolution mode, gain = 16
Low-power mode, gain = 1
Gain = 1
110
113
113
110
108
107
105
106
113
Signal-to-noise ratio
SNR
dB
(see 表 1 through 表 4)
112
110
110
–115
–115
115
–105
300
THD
Total harmonic distortion(1)
Spurious-free dynamic range
dB
dB
Gain = 2, 4, 8, and 16
SFDR
TA = 25°C
–300
±50
VIO
Input offset voltage
Chop disabled, TA = 25°C
After calibration(2)
±300
±1
µV
0.05
1
Input offset voltage drift
Gain error
µV/°C
Chop disabled
High-resolution mode, TA = 25°C
Low-power mode, TA = 25°C
–0.8%
–0.6%
–0.3%
–0.1%
0.0005%
1
0.2%
0.4%
Gain error after calibration(2)
Gain drift
All gains
ppm/°C
Gain match
Calibration margin(3)
All gains relative to gain = 1
–0.5%
–106%
±0.1%
0.5%
106%
(1) Test signal: 31.25 Hz, –0.5 dBFS.
(2) Calibration accuracy is on the level of noise reduced by four (calibration averages 16 readings).
(3) Calibration margin is the maximum allowed input voltage range after calibration operations.
6
Copyright © 2017–2019, Texas Instruments Incorporated
ADS1287
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ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
Electrical Characteristics (continued)
maximum and minimum specifications apply from –40°C to +85°C; typical specifications are at 25°C; all specifications are at
AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, f(CLK) = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-resolution
and low-power modes, chop enabled, and fDATA = 1000 SPS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SYSTEM PERFORMANCE, continued
High-resolution mode, DC to 60 Hz
Low-resolution mode, DC to 60 Hz
Analog supplies, DC to 60 Hz
Digital supply, DC to 60 Hz
100
95
115
110
90
CMRR
PSRR
Common-mode rejection ratio
Power-supply rejection ratio
dB
dB
75
90
105
VOLTAGE REFERENCE INPUT
High-resolution mode
Low-power mode
320
640
Input impedance
kΩ
DIGITAL FILTER RESPONSE
Pass-band ripple
±0.003
10
dB
Hz
Hz
Hz
dB
Hz
Pass band (–0.01 dB)
Bandwidth (–3 dB)
0.375 × f(DATA)
0.413 × f(DATA)
High-pass filter corner
Stop-band attenuation(4)
Stop band
0.1
135
0.500 × fDATA
5 / fDATA
Minimum phase filter
Linear phase filter
Minimum phase filter
Linear phase filter
Group delay
s
s
31 / fDATA
62 / fDATA
62 / fDATA
Settling time (latency)
DIGITAL INPUT/OUTPUTS
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
Input current
DGND
0.8 × DVDD
DGND
0.2 × DVDD
DVDD
V
V
VIH
VOL
VOH
IOL = 1 mA
0.2 × DVDD
DVDD
V
IOH = 1 mA
0.8 × DVDD
–10
V
0 ≤ VDIGITAL IN ≤ DVDD
10
μA
POWER SUPPLY
High-resolution mode
Low-power mode
Standby mode
750
330
1
1100
480
IAVDD,
IAVSS
Analog supply current
µA
µA
Power-down mode
High-resolution mode
Low-power mode
Standby mode(5)
Power-down mode(5)
High-resolution mode
Low-power mode
Standby mode(5)
1
240
220
25
1
320
300
IDVDD
Digital supply current
Power dissipation
4.5
2.4
90
10
6.6
3.4
mW
µW
PD
Power-down mode(5)
(4) Input frequencies are in the range of N × f(CLK) / 1024 ± f(DATA) / 2 (where N = 1, 2, 3, and so forth) intermodulated with the modulator
chopper clock. At these frequencies, intermodulation components are –120 dBFS (typ).
(5) CLK input stopped.
Copyright © 2017–2019, Texas Instruments Incorporated
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6.6 Timing Requirements
over operating ambient temperature range and DVDD = 2.25 V to 3.6 V (unless otherwise noted)
MIN
MAX
UNIT
SERIAL INTERFACE
td(CSSC)
Delay time, CS falling edge to first SCLK rising edge
SCLK period
40
250
2
ns
ns
tc(SC)
SCLK period specific to SYNC and RESET commands
Pulse duration, SCLK high and low(1)
1 / fCLK
ns
100
0.8
50
tw(SCH), tw(SCL)
Pulse duration, SCLK high and low specific to SYNC and RESET commands
Setup time, DIN valid before SCLK rising edge
Hold time, DIN valid after SCLK rising edge
Pulse duration, CS high
1 / fCLK
ns
tsu(DI)
th(DI)
50
ns
tw(CSH)
td(SCCS)
td(CMBT)
100
24
ns
Delay time, last SCLK rising edge to CS rising edge
Delay time, after each byte within and between command sequences(2)
1 / fCLK
1 / fCLK
24
SYNCHRONIZATION
td(CLSY)
Delay time, CLK rising edge to SYNC rising edge(3)
30
2
–30
ns
tw(SYH), tw(SYL) Pulse duration, SYNC high or SYNC low
1 / fCLK
RESET
tsu(RSCL)
tw(RSL)
Setup time, RESET rising edge to a specific CLK rising edge
Pulse duration, RESET low
10
2
ns
1 / fCLK
(1) Holding SCLK low for 64 DRDY periods forces a serial interface reset.
(2) When reading conversion data, the byte-to-byte delay is not required (td(CMBT)).
(3) SYNC rising edge to CLK rising edge must not occur within the specified time window.
6.7 Switching Characteristics
over operating ambient temperature range, DVDD = 2.25 V to 3.6 V, and DOUT loading = 20 pF || 100 kΩ (unless otherwise
noted)
PARAMETER
SERIAL INTERFACE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Propagation delay time,
DRDY falling edge to valid data DOUT
tp(DRDO)
tp(CSDOD)
tp(SCDO1)
tp(SCDO2)
100
60
ns
ns
ns
ns
Propagation delay time,
CS falling edge to DOUT driven
Propagation delay time,
SCLK falling edge to valid new DOUT
100
Propagation delay time,
SCLK falling edge to valid old DOUT
0
0
Propagation delay time,
CS rising edge to DOUT Hi-z
tp(CSDOZ)
tw(DRH)
40
1
ns
Pulse duration, DRDY high
4
1 / fCLK
1 / fDATA
Propagation delay time, RDATA
command to DRDY low (see 图 60)
tp(CMDR)
8
Copyright © 2017–2019, Texas Instruments Incorporated
ADS1287
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ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
Switching Characteristics (continued)
over operating ambient temperature range, DVDD = 2.25 V to 3.6 V, and DOUT loading = 20 pF || 100 kΩ (unless otherwise
noted)
PARAMETER
SYNCHRONIZATION
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-resolution mode, 62.5 SPS
High-resolution mode, 125 SPS
High-resolution mode, 250 SPS
High-resolution mode, 500 SPS
High-resolution mode, 1000 SPS
Low-power mode, 62.5 SPS
Low-power mode, 125 SPS
Low-power mode, 250 SPS
Low-power mode, 500 SPS
Low-power mode, 1000 SPS
1008.145
504.301
252.379
126.419
63.438
1008.390
504.548
252.625
126.665
63.684
Propagation delay time, SYNC rising
edge to DRDY falling edge
tp(SYDR)
ms(1)
Sinc filter and high-resolution mode,
2000 SPS
2.755
1.630
0.942
0.599
0.427
Sinc filter and high-resolution mode,
4000 SPS
Sinc filter and high-resolution mode,
8000 SPS
Sinc filter and high-resolution mode,
16000 SPS
Sinc filter and high-resolution mode,
32000 SPS
RESET
Propagation delay time, RESET pin or
reset command to DRDY falling edge
tp(RSDR)
252.379
252.379(2)
216
ms
ms
POWER-DOWN MODE and STANDBY MODE WAKEUP
Propagation delay time, exit power-down
tp(PWDR)
or standby mode to first data ready
POWER-UP
Propagation delay time, power-on
tp(PUCM)
fCLK
threshold voltage to communication ready
Propagation delay time, power-on
tp(PUDR)
216 / fCLK + 252.379
ms(1)
threshold voltage to first data ready
(1) fCLK = 1.024 MHz.
(2) The exit power-down mode default setting is 250 SPS with the FIR filter mode. Subtract two fCLK cycles for a WAKEUP command. The
WAKEUP command is timed from the rising CLK edge after the eighth rising SCLK edge.
tw(CSH)
CS
td(CSSC)
td(SCCS)
tc(SC)
tw(SCH)
SCLK
DIN
tw(SCL)
tsu(DI)
th(DI)
B3
B2
B6
B5
B4
B1
B0
B7
图 1. Serial Interface Timing Requirements
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Command
Byte
Command
Byte
DIN
SCLK
td(CMBT)
图 2. Serial Interface Command Timing Requirements
DRDY
CS
tp(DRDO)
tp(CSDOD)
SCLK
DOUT
tp(CSDOZ)
tp(SCDO1)
DATA
OLD
th(SCDO2)
图 3. Serial Interface Switching Characteristics
td(CLSY)
CLK
tp(SYDR)
SYNC
tw(SYH)
tw(SYL)
DRDY
(Pulse-sync mode)
tw(DRH)
DOUT
(Pulse-sync mode)
DRDY
(Continuous-sync mode)
tw(DRH)
DOUT
(Continuous-sync mode)
图 4. Synchronization Timing
10
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Settled
Data
DRDY
CLK
tp(RSDR)
tSU(RSCL)
RESET Pin
or
tw(RSL)
RESET Command
图 5. Reset Timing
DRDY
tp(PWDR)
PWDN
Wakeup
Command
图 6. Power-Down and Standby Wake-Up Timing
DVDD
1 V nom
1 V nom
VBYPAS
AVDD - AVSS
3.5 V nom
All voltages reach thresholds and CLK applied
ADC
Communication
disabled
tp(PUCM)
enabled
DRDY
tp(PUDR)
图 7. Power-Up Timing
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6.8 Typical Characteristics
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D005
D006
Shorted input, high-resolution mode,
gain = 1, 8192 points, SNR = 113.2 dB
Shorted input, high-resolution mode,
gain = 8, 8192 points, SNR = 111.8 dB
图 8. Output Spectrum
图 9. Output Spectrum
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D009
D007
Shorted input, chop disabled, high-resolution mode,
gain = 8, 8192 points, SNR = 111.3 dB
Shorted input, low-power mode, offset enabled,
gain = 1, 8192 points, SNR = 110.1 dB
图 10. Output Spectrum
图 11. Output Spectrum
0
0
-20
-20
-40
-60
-40
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D008
D010
Shorted input, low-power mode, offset enabled,
gain = 8, 8192 points, SNR = 108.4 dB
Shorted input, low-power mode, chop disabled,
gain = 8, 8192 points, SNR = 108.0 dB
图 12. Output Spectrum
图 13. Output Spectrum
12
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
0
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
0
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D001
D002
fIN = 31.25 Hz, –0.5 dB, high-resolution mode,
gain = 1, 8192 points
fIN = 31.25 Hz, –20 dB, high-resolution mode,
gain = 1, 8192 points
图 14. Output Spectrum
图 15. Output Spectrum
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D003
D004
fIN = 31.25 Hz, –0.5 dB, high-resolution mode,
gain = 8, 8192 points
fIN = 31.25 Hz, –20 dB, high-resolution mode,
gain = 8, 8192 points
图 16. Output Spectrum
图 17. Output Spectrum
0
-20
0
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D011
D012
fIN = 31.25 Hz, –0.5 dB, low-power mode,
gain = 1, 8192 points
fIN = 31.25 Hz, –20 dB, low-power mode,
gain = 1, 8192 points
图 18. Output Spectrum
图 19. Output Spectrum
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
0
0
-20
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
0
50 100 150 200 250 300 350 400 450 500
Frequency (Hz)
D013
D014
fIN = 31.25 Hz, –0.5 dB, low-power mode,
gain = 8, 8192 points
fIN = 31.25 Hz, –20 dB, low-power mode,
gain = 8, 8192 points
图 20. Output Spectrum
图 21. Output Spectrum
-100
-105
-110
-115
-120
-125
-130
-135
-140
-100
-105
-110
-115
-120
-125
-130
-135
-140
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
0
25
50 75
Input Frequency (Hz)
100
125
0
25
50 75
Input Frequency (Hz)
100
125
D015
D016
High-resolution mode, VIN = –0.5 dB
Low-power mode, VIN = –0.5 dB
图 22. THD vs Input Frequency
图 23. THD vs Input Frequency
-100
-105
-110
-115
-120
-125
-130
-135
-140
-100
-105
-110
-115
-120
-125
-130
-135
-140
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D017
D018
fIN = 31.25 Hz, –0.5 dB, high-resolution mode
fIN = 31.25 Hz, –0.5 dB, low-power mode
图 24. THD vs Temperature
图 25. THD vs Temperature
14
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
116
114
112
110
108
106
104
102
100
114
112
110
108
106
104
102
100
98
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D019
D020
Shorted input, high-resolution mode
Shorted input, low-power mode
图 26. SNR vs Temperature
图 27. SNR vs Temperature
116
114
112
110
108
106
104
102
100
140
130
120
110
100
90
80
70
High-resolution mode
Low-power mode
Gain = 1
Gain = 8
60
50
0.4
0.5
0.6
0.7
0.8
Clock Frequency (MHz)
0.9
1
1.1
1
10
100
1000
Input Frequency (Hz)
10000 100000 1000000
D027
D021
Shorted input
High-resolution mode
图 28. SNR vs Clock Frequency
图 29. CMRR vs Frequency
140
130
120
110
100
90
120
110
100
90
80
70
80
60
70
50
Gain = 1
Gain = 8
High-resolution mode
Low-power mode
60
50
40
1
10
100
1000
Input Frequency (Hz)
10000 100000 1000000
1
10
100
1000
Input Frequency (Hz)
10000 100000 1000000
D022
D023
Low-power mode
图 30. CMRR vs Frequency
图 31. Analog Supply PSRR vs Frequency
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
100
20
15
10
5
80
60
40
20
0
0
-20
-40
-60
-80
-100
-5
-10
-15
-20
P Input, T = 25èC
N Input, T = 25èC
P Input, T = 85èC
N Input, T = 85èC
P Input, T = 25èC
N Input, T = 25èC
P Input, T = 85èC
N Input, T = 85èC
-2.5 -2 -1.5 -1 -0.5
0
0.5
Differential Input Voltage (V)
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
Differential Input Voltage (V)
1
1.5
2
2.5
D028
D029
Chop enabled, gain = 1, high-resolution mode
Chop disabled, gain = 1, high-resolution mode
图 32. Input Current vs Input Voltage
图 33. Input Current vs Input Voltage
20
18
16
14
12
10
8
12
10
8
High-resolution mode
Low-power mode
High-resolution mode
Low-power mode
6
4
6
4
2
2
0
0
D034
D033
Offset (mV)
Offset (mV)
Chop enabled, gain = 1, 30 units
Chop disabled, gain = 1, 30 units
图 34. Offset Error Histogram
图 35. Offset Error Histogram
20
10
9
8
7
6
5
4
3
2
1
0
High-resolution mode
Low-power mode
15
10
5
0
D035
Offset Drift (nV/èC)
D036
Offset (mV)
Offset enabled (50 mV), low-power mode,
gain = 1, 30 units
Chop enabled, gain = 1, 30 units
图 37. Offset Temperature Drift Histogram
图 36. Offset Error Histogram
16
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 2.5 V, AVSS = –2.5 V, DVDD = 3.3 V, fCLK = 1.024 MHz, V(REFP) = 0 V, V(REFN) = –2.5 V, gain = 1, high-
resolution and low-power modes, chop enabled, offset disabled, and fDATA = 1000 SPS (unless otherwise noted)
18
16
14
12
10
8
160
140
120
100
80
High-resolution mode
Low-power mode
60
6
40
4
2
20
0
0
D031
D032
Gain Error (ppm)
Gain Drift (ppm/èC)
Gain = 1, 30 units
Gain = 1, 2, 4, 8 and 16 combined; 30 units;
combined high-resolution and low-power modes
图 38. Gain Error Histogram
图 39. Gain Drift Histogram
10
9
8
7
6
5
4
3
2
1
0
800
700
600
500
400
300
200
High-resolution mode
Low-power mode
-50
-25
0
25
50
75
100
125
D030
Temperature (èC)
D025
Gain Match (ppm)
Gain = 2, 4, 8, 16 match to gain = 1;
30 units
图 41. Reference Input Impedance vs Temperature
图 40. Gain Match Error Histogram
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3
0.25
0.2
0.15
0.1
1000 SPS
500 SPS
250 SPS
125 SPS
62.5 SPS
0.05
High-resolution mode
Low-power mode
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (èC)
Temperature (èC)
D024
D026
High-resolution mode
图 43. Digital Supply Current vs Temperature
图 42. Analog Supply Current vs Temperature
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7 Parameter Measurement Information
7.1 Noise Performance
SNR and input-referred noise are related parameters that define the ADC effective resolution. Use 公式 1 to
calculate SNR from the input-referred noise data:
FSRRMS
SNR = 20log
NRMS
where:
FSRRMS = Full-scale range, root-mean-square = 2.5 V / (√2 · Gain)
NRMS = Input-referred noise voltage
(1)
表 1 through 表 4 list SNR and noise performance data. Noise performance data are listed for high-resolution
and low-power modes, with and without chop enabled. The noise performance data are representative of typical
ADC performance at TA = 25°C. The data are the standard deviation of consecutive ADC conversion results with
the ADC inputs shorted over the signal bandwidth of 0.1 Hz to 0.413 fDATA. Repeated noise measurements can
yield higher or lower noise results because of the statistical nature of noise.
Noise performance depends on several ADC operating parameters: high-resolution or low-power mode, data
rate, PGA gain, and chop mode. Best noise performance is achieved by operating the ADC in high-resolution
mode. Noise performance also depends on the data rate. For example, as the data rate decreases, the ADC
bandwidth and thus total noise decreases. Using higher gain factors improves input-referred noise, but the
calculated SNR decreases because of a 6-dB decrease of input range for each gain step. Chop mode improves
noise performance by removing 1/f noise from the PGA. Chop mode is particularly important for lowest noise
operation when used with low data rates or high gain. Chop mode is the recommended mode for geophone
sensors.
表 1. High-Resolution Mode Noise Performance (Chop Enabled)(1)
SNR (dB)
GAIN
4
INPUT-REFERRED NOISE (µVRMS
)
fDATA (SPS)
GAIN
1
2
8
16
1
2
4
8
16
62.5
125
125
122
119
116
113
125
122
119
116
113
125
124
121
118
115
112
122
119
116
113
110
0.96
1.36
1.90
2.70
3.85
0.49
0.68
0.97
1.36
1.95
0.25
0.35
0.50
0.71
1.00
0.14
0.19
0.28
0.39
0.55
0.09
0.13
0.18
0.25
0.36
122
250
119
500
116
1000
113
(1) Typical performance data at TA = 25°C. SNR data are rounded. Measurement bandwidth: 0.1 Hz to 0.413 fDATA
.
表 2. High-Resolution Mode Noise Performance (Chop Disabled)(1)
SNR (dB)
GAIN
4
INPUT-REFERRED NOISE (µVRMS
)
fDATA (SPS)
GAIN
1
2
8
16
1
2
4
8
16
62.5
125
125
122
119
116
113
125
122
119
116
113
123
120
119
116
114
111
114
114
113
111
109
0.99
1.36
1.90
2.70
3.85
0.52
0.70
0.97
1.38
1.95
0.31
0.39
0.54
0.73
1.03
0.23
0.26
0.34
0.43
0.60
0.23
0.22
0.26
0.32
0.41
121
250
118
500
116
1000
113
(1) Typical performance data at TA = 25°C. SNR data are rounded. Measurement bandwidth: 0.1 Hz to 0.413 fDATA
.
18
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表 3. Low-Power Mode Noise Performance (Chop Enabled, Offset Enabled)(1)
SNR (dB)
GAIN
4
INPUT-REFERRED NOISE (µVRMS
)
fDATA (SPS)
GAIN
1
2
8
16
1
2
4
8
16
62.5
125
123
120
117
113
110
123
119
116
113
110
122
121
118
115
112
109
118
115
112
109
106
1.33
1.86
2.65
3.81
5.50
0.66
0.96
1.36
1.91
2.79
0.36
0.50
0.70
1.01
1.48
0.20
0.29
0.41
0.58
0.84
0.14
0.20
0.29
0.40
0.58
119
250
116
500
113
1000
110
(1) Typical performance data at TA = 25°C. SNR data are rounded. Measurement bandwidth: 0.1 Hz to 0.413 fDATA
.
(1)
表 4. Low-Power Mode Noise Performance (Chop Disabled, Offset Enabled)
SNR (dB)
GAIN
4
INPUT-REFERRED NOISE (µVRMS
)
fDATA (SPS)
GAIN
1
2
8
16
1
2
4
8
16
62.5
125
122
119
116
113
110
122
119
116
113
110
121
118
116
114
111
108
113
112
110
108
105
1.36
1.90
2.67
3.75
5.53
0.71
0.97
1.38
1.93
2.80
0.40
0.53
0.74
1.02
1.48
0.29
0.36
0.46
0.62
0.88
0.24
0.29
0.35
0.46
0.62
118
250
115
500
113
1000
110
(1) Typical performance data at TA = 25°C. SNR data are rounded. Measurement bandwidth: 0.1 Hz to 0.413 fDATA
.
8 Detailed Description
8.1 Overview
The ADS1287 is a low-power, high-resolution analog-to-digital converter (ADC) intended for energy exploration,
low-power seismic-data acquisition nodes, and other exacting applications that require very low power
consumption. The converter provides 31-bit resolution over data rates 62.5 SPS to 1000 SPS, and
programmable gains of 1 to 16 that expand the measurement resolution; see the Functional Block Diagram
section.
The ADC consists of an input multiplexer (MUX), a low-noise complementary metal oxide semiconductor (CMOS)
programmable gain amplifier (PGA), a fourth order delta-sigma (ΔΣ) modulator, an infinite impulse response (IIR)
high-pass filter (HPF), a finite-impulse-response (FIR) low-pass filter (LPF), and an SPI-compatible serial
interface used for both device configuration and conversion data readback.
The signal multiplexer selects between the external input or internal short (via 400-Ω resistors). The internal short
is used for offset calibration and to verify the ADC offset and noise performance. The input multiplexer is followed
by a programmable-gain, CMOS PGA, featuring low noise. The available PGA gains are 1 V/V, 2 V/V, 4 V/V,
8 V/V, and 16 V/V. The PGA is chopped to reduce 1/f noise and input offset voltage. The PGA output is routed to
the modulator and to the CAPP and CAPN pins. An external 10-nF capacitor connected to these pins filters the
modulator sampling pulses and provides the ADC antialias filter.
The inherently-stable, fourth-order, ΔΣ modulator measures the differential input signal VIN = V(AINP) – V(AINN)
against the differential reference VREF = V(REFP) – V(REFN). The ADC requires an external 2.5-V voltage reference.
The modulator output data are processed by an integrated digital filter to provide the final conversion result.
The digital filter consists of a sinc filter followed by a programmable-phase, FIR low-pass filter and
programmable-frequency, IIR high-pass filter. The HPF removes DC and low-frequency components from the
conversion result.
Programmable gain and offset data registers calibrate the conversion result to remove offset and gain errors.
The SYNC input pin synchronizes the ADC. Synchronization has two programable modes of operation: pulse-
synchronization and continuous-synchronization that accepts a synchronizing-clock input. The RESET input
resets the ADC including the register settings.
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Overview (接下页)
The PWDN input powers-down the ADC. The low-power STANDBY mode is engaged by software command.
RESET and SYNC control inputs are noise-resistant, Schmitt-trigger inputs to increase reliability in high-noise
environments.
The ADC has an SPI-compatible serial interface. The interface is 4-wire and is used to read conversion data and
to read and write device registers.
Power to the analog section is provided through AVDD and AVSS. DVDD is the digital and I/O supply. DVDD is
sub-regulated to 1.8 V by an integrated, low-dropout regulator (LDO) to supply the digital core. The BYPAS pin is
the LDO output and requires a 1-µF bypass capacitor.
8.2 Functional Block Diagram
+1.8 V
(Digital)
LDO
CLK
840 ꢀ
840 ꢀ
CS
AINP
AINN
SCLK
DIN
Serial
Interface
Calibration
ûꢁ Modulator
Digital Filter
PGA
DOUT
2 x
400 Ω
DRDY
PWDN
Control
SYNC
VCOM
ADS1287
RESET
AVSS
DGND
20
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8.3 Feature Description
8.3.1 Analog Input and Multiplexer
图 44 shows a diagram of the analog input circuit and multiplexer.
AVDD
AINP
400 Ω
+
_
PGA
AINN
400 Ω
VCOM = (AVDD + AVSS) / 2
AVSS
图 44. Analog Input and Multiplexer
Electrostatic discharge (ESD) diodes are incorporated to protect the ADC inputs from ESD exposure that can
occur during device manufacturing and printed circuit board (PCB) assembly process when assembled in an
ESD-controlled environment. For system-level ESD protection, external ESD protection devices are
recommended to protect device inputs or outputs that may be exposed to ESD events.
If either input is taken below AVSS – 0.3 V, or above AVDD + 0.3 V, the internal protection diodes can conduct.
If these conditions are possible, use external clamp diodes, series resistors, or both to limit the maximum input
current to the specified value.
The input multiplexer selects between the external input or the internal (shorted) input. The internal short is via
two 400-Ω resistors to analog mid-supply voltage (VCOM). The thermal noise of the resistors is equivalent to the
noise produced by common geophones. Use the internal short connection to verify the ADC offset voltage and
noise performance, and to provide an input to calibrate the ADC offset voltage. 表 5 summarizes the register
selections of the multiplexer configurations related to 图 44.
表 5. Input Multiplexer Modes
MUX[1:0] REGISTER BITS
DESCRIPTION
00
01
10
11
External input (default)
Reserved
Internal short; PGA input connected to internal VCOM voltage via 400-Ω resistors
Reserved
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8.3.2 Programmable Gain Amplifier (PGA)
The ADC incorporates a low-noise PGA in order to extend the ADC dynamic range. The PGA is a CMOS,
differential-input and differential-output amplifier. The gain factor is programmable from 1 V/V to 16 V/V and is
controlled by the GAIN[2:0] register bits. The PGA differentially drives the modulator via two 840-Ω internal
resistors. Connect a 10-nF, C0G-dielectric capacitor between the CAPP and CAPN pins. The capacitor filters the
modulator sampling glitches and also functions as a first-order antialias filter. 公式 2 gives the corner frequency
of the antialias filter:
fC = 1/ (2π · 2 · 1.7 kΩ ·10 nF) = 9.3 kHz
(2)
As shown in 图 45, the PGA is composed of two amplifiers. The amplifiers are chopper-stabilized in order to
reduce the PGA 1/f noise, offset, and offset drift. The PGA chop mode can be disabled when used with certain
types of high-impedance sensors, such as hydrophones; see the Chop Mode section for more details.
AVDD
840 ꢀ
+
MUX(+)
CAPP
œ
external
Chop
To ADC
Modulator
Gain Control
PGA[2:0] bits
10 nF
840 ꢀ
œ
CAPN
+
MUX(-)
Chop bit
AVSS
图 45. PGA Block Diagram
The PGA gain factors are programmable from 1 to 16 V/V. 表 6 shows the register bit setting for the PGA gain
and corresponding input voltage range.
表 6. PGA Gain Factors
GAIN[2:0] REGISTER BITS
GAIN (V/V)
DIFFERENTIAL INPUT RANGE
000
001
1
±2.5 V
±1.25 V
±0.625 V
±0.3125 V
±0.15625 V
—
2
010
4
011
8
16
100
101 - 111
Reserved
To maintain linear operation, observe the specified PGA input and PGA output voltage range requirements. The
absolute voltage is defined as the sum of the signal component plus offset voltage (common-mode voltage). 公式
3 shows the specified absolute input voltage range:
AVSS + 1 V < V(AINP) and V(AINN) < AVDD – 1.25 V
(3)
公式 4 shows the specified absolute PGA output voltage range:
AVSS + 0.4 V < V(CAPP) and V(CAPN) < AVDD – 0.4 V
(4)
公式 5 shows that the PGA output voltage is equal to the absolute PGA input voltage plus and minus the
differential input voltage times half the PGA gain factor minus 1:
PGA output voltage = V(CAPx) = V(AINx) ± VIN· (Gain – 1) / 2
(5)
22
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8.3.3 Modulator
图 46 shows that the ΔΣ modulator is an inherently-stable, fourth-order, 2 + 2 pipelined structure. The modulator
shapes the quantization noise to an area outside of the pass band, where the noise is removed by the digital
filter.
fCLK/4
fMOD =
1st-Stage
(2nd-Order ûꢀ)
Analog
Signal
Digital
Filter
Math
Block
2nd-Stage
(2nd-Order
ûꢀ)
图 46. Modulator
The first stage of the modulator converts the analog input voltage into a pulse-code modulated (PCM) stream.
When the input voltage to the modulator is equal to the reference voltage (VREF), the density of the PCM data
stream is at the highest 1 density. When the input voltage is zero, the PCM 1 density is 50%. At the FS and –FS
inputs, the 1 density of the PCM streams is approximately 90% and 10%, respectively.
The modulator second stage produces a digital data stream designed to cancel the quantization noise of the first
stage. The data streams of the two stages are mathematically combined to reduce overall quantization noise.
The combined data are the input to the digital filter block.
8.3.3.1 Modulator Overrange
The ADS1287 modulator is inherently stable, and therefore, has predictable input overdrive recovery. If the input
is overdriven to cause the modulator to produce a 1 density output in the range of 90% to 100% (10% and 0% for
negative overdrive), the output codes may or may not clip resulting from the effect of the digital filter integration.
Clipping depends on the duration of the input overdrive. When the input returns to the normal range from a long-
duration overdrive (worst case), the modulator returns immediately to the normal 1 density range, but the action
of the digital filter delays the return to the normal reading range because of the filter group delay.
In the extreme case of input overdrive (where the overdriven input exceeds the analog supply voltage + VESD
diode drop), the internal ESD diodes begin to conduct, thus clipping the input signal. When the input overdrive is
removed, the diodes recover quickly. Be sure to limit the input current to 10 mA (transient or continuous duty) if
an overvoltage condition is possible.
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8.3.4 Voltage Reference Inputs (REFP, REFN)
The ADC requires an external reference voltage for operation. The specified reference voltage is 2.5 V and is
defined by 公式 6 as the voltage between the REFP and REFN pins:
VREF = V(REFP) – V(REFN)
(6)
图 47 shows the reference input circuit. The ADC samples the reference voltage to an internal capacitor. The
sampled voltage is used in the ADC process. The constant sampling of the reference inputs results in transient
currents that must be filtered by an external capacitor. Place a 0.1-µF ceramic capacitor directly between the
REFP and REFN pins to filter the transient currents.
The input impedance of the reference input is determined by the average value of the transient currents. In
applications where one voltage reference drives multiple ADCs, use individual capacitors at each ADC reference
input. Reference voltage noise can degrade the overall noise performance. Therefore, the selection of the
voltage reference must include the evaluation of noise.
AVDD
REFP
CEFF
REFN
AVSS
图 47. Simplified Reference Input Circuit
The ADC reference inputs are protected by internal ESD diodes. The voltage of reference inputs must stay within
the range shown in 公式 7 in order to prevent these diodes from conducting:
AVSS – 300 mV < VREFP or VREFN < AVDD + 300 mV
(7)
If the voltage on the reference inputs exceeds this range, limit the reference input current to 10 mA or less. See
the Electrical Characteristics section for the specified reference voltage range.
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8.3.5 Digital Filter
The digital filter performs decimation and filtering of the modulator output to provide the final data output. By
adjusting the amount of filtering, tradeoffs can be made between resolution and data rate. Lower data rates yield
lower overall noise resulting from the reduction of bandwidth.
The digital filter is comprised of three filter stages, as shown in 图 48: a variable-decimation, sinc filter; a fixed-
decimation FIR filter; and a programmable frequency high-pass, IIR filter (HPF).
Filter Mode
(Register Select)
Filter
MUX
To Output Register
Sinc Filter
(Decimate by
4 to 128)
Coefficient Filter
(FIR)
(Decimate by 32)
High-Pass Filter
(IIR)
Code
Clip
CAL
Block
From Modulator
图 48. Digital Filter and Output Code Processing
The output data can be taken from one of the three filter blocks. The sinc filter option provides partially filtered
data. The partially filtered sinc data are intended for use with external decimation filters. For complete internal
filtering, activate both the sinc filter and FIR filter stages. The HPF can also be included to remove DC and low
frequencies from the data. 表 7 shows the filter options.
表 7. Digital Filter Selection
FILTR[1:0] REGISTER BITS
DIGITAL FILTERS SELECTION
00
01
10
11
Reserved
Low-pass filter: sinc only
Low-pass filter: sinc + FIR (default)
Low-pass and high-pass filter: sinc + FIR + IIR
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8.3.5.1 Sinc Filter Stage
The sinc filter (sinx/x) is a variable-decimation, fifth-order, low-pass filter. Data are supplied to this filter from the
modulator at the rate of fMOD = fCLK / 4 (high-resolution mode), fCLK / 8 (low-power mode). The sinc filter
attenuates the high-frequency noise of the modulator. The sinc filter provides down-sampled, partially-filtered
data to the FIR filter. The decimation ratio of the sinc filter is variable and determines the overall data rate. 表 8
shows that the decimation ratio of the sinc filter is programmed by the DR[2:0] register bits.
表 8. Sinc Filter Data Rates
SINC DECIMATION RATIO (N)
DR[2:0] REGISTER BITS
HIGH-RESOLUTION MODE
LOW-POWER MODE
SINC DATA RATE (SPS)
000
001
128
64
2,000
4,000
64
32
010
32
16
8,000
011
16
8
8
4
16,000
32,000
Reserved
100
101 - 111
Reserved
Reserved
公式 8 shows the scaled Z-domain transfer function of the sinc filter.
5
-N
1 - Z
-1
N(1 - Z )
H(Z) =
where
•
N = decimation ratio
(8)
公式 9 shows the frequency domain transfer function of the sinc filter.
5
pN ´ f
sin
fMOD
½H(f)½ =
p ´ f
N sin
fMOD
where
•
•
•
N = Decimation ratio (see 表 8)
f = Input signal frequency
fMOD = Modulator sampling frequency = fCLK / 4 (high resolution mode), fCLK / 8 (low-power mode)
(9)
26
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The frequency response of the sinc filter contains notches (or zeros) that occur at the output data rate frequency
and multiples thereof. At these frequencies, the filter has zero gain. 图 49 shows the wide-band frequency
response of the sinc filter and 图 50 shows the –3-dB response.
0
-20
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-40
-60
-80
-100
-120
-140
0
1
2
3
4
5
0
0.05
0.10
0.15
0.20
Normalized Frequency (fIN/fDATA
)
Normalized Frequency (fIN/fDATA
)
图 49. Sinc Filter Frequency Response
图 50. Sinc Filter –3-dB Response
8.3.5.2 FIR Filter Stage
The second stage of the ADS1287 digital filter is the FIR low-pass filter. Data are supplied to the FIR stage from
the pre-filter, sinc stage. The FIR filter performs the final frequency response shaping. 图 51 shows that the FIR
filter is composed of four sub-stages.
FIR Stage 1
Decimate by 2
FIR Stage 2
Decimate by 2
FIR Stage 3
Decimate by 4
FIR Stage 4
Decimate by 2
Sinc
Filter
Output
Coefficients
Linear
Minimum
PHASE Select
图 51. FIR Filter
The first two FIR stages are half-band filters with fixed decimation ratios equal to 2. The third stage decimates by
a ratio equal to 4, and the fourth stage decimates by ratio equal to 2. The overall decimation ratio of the FIR
stage is 32. Two coefficient sets are selectable by register bits for the third and fourth sections, one for the linear
phase and one for the minimum phase response. 表 9 lists the data rates and combined decimation ratios of the
sinc and FIR stage. 表 10 lists the filter coefficients that correspond to each FIR stage.
表 9. FIR Filter Data Rates
COMBINED DECIMATION RATIO (N)
DR[2:0] REGISTER BITS
HIGH-RESOLUTION MODE
LOW-POWER MODE
FIR DATA RATE (SPS)
000
001
4096
2048
2048
1024
62.5
125
010
1024
512
250
011
512
256
500
100
256
128
1000
Reserved
101–111
Reserved
Reserved
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表 10. FIR Stage Coefficients
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
LINEAR MINIMUM
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
b0
PHASE PHASE
3
0
–10944
0
0
819
8211
–132
–432
11767
133882
b1
0
b2
–25
0
103807
0
–73
44880
–75
769961
b3
–874
174712
536821
1372637
3012996
5788605
9852286
14957445
20301435
24569234
26260385
24247577
18356231
9668991
327749
–7171917
–10926627
–10379094
–6505618
–1333678
2972773
5006366
4566808
2505652
126331
–1496514
–1933830
–1410695
–502731
245330
565174
492084
231656
–9196
2481
2940447
8262605
17902757
30428735
40215494
39260213
23325925
–1757787
–21028126
–21293602
–3886901
14396783
16314388
1518875
–12979500
–11506007
2769794
12195551
6103823
–6709466
–9882714
–353347
8629331
5597927
–4389168
–7594158
–428064
6566217
4024593
–3679749
–5572954
332589
b4
150
256
150
0
–507903
0
–4648
6692
b5
–16147
–41280
–80934
–120064
–118690
–18203
224751
580196
893263
891396
293598
–987253
–2635779
–3860322
–3572512
–822573
4669054
12153698
19911100
25779390
27966862
25779390
19911100
12153698
4669054
–822573
–3572512
–3860322
–2635779
–987253
293598
891396
893263
580196
224751
–18203
–118690
–120064
–80934
–41280
–16147
–4648
7419
b6
2512192
4194304
2512192
0
–266
b7
–10663
–8280
b8
–25
0
b9
10620
b10
b11
b12
b13
b14
b15
b16
b17
b18
b19
b20
b21
b22
b23
b24
b25
b26
b27
b28
b29
b30
b31
b32
b33
b34
b35
b36
b37
b38
b39
b40
b41
b42
b43
b44
b45
b46
b47
b48
3
–507903
0
22008
348
103807
0
–34123
–25549
33460
–10944
61387
–7546
–94192
–50629
101135
134826
–56626
–220104
–56082
263758
231231
–215231
–430178
34715
580424
283878
–588382
–693209
366118
1084786
132893
–1300087
–878642
1162189
1741565
–522533
–2490395
–688945
2811738
2425494
–2338095
–4511116
641555
6661730
5136333
2351253
–3357202
–3767666
1087392
3847821
919792
–125456
–122207
–61813
–4445
22484
22245
10775
–2918303
–2193542
1493873
2595051
–79991
940
–2953
–2599
–1052
–874
–43
–2260106
–963855
–73
214
28
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表 10. FIR Stage Coefficients (接下页)
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
b49
b50
b51
b52
b53
b54
b55
b56
b57
b58
b59
b60
b61
b62
b63
b64
b65
b66
b67
b68
b69
b70
b71
b72
b73
b74
b75
b76
b77
b78
b79
b80
b81
b82
b83
b84
b85
b86
b87
b88
b89
b90
b91
b92
b93
b94
b95
b96
b97
0
0
0
132
33
0
2950811
–8538057
–10537298
9818477
41426374
56835776
41426374
9818477
–10537298
–8538057
2950811
6661730
641555
1482337
1480417
–586408
–1497356
–168417
1166800
644405
–675082
–806095
211391
740896
141976
–527673
–327618
278227
363809
–70646
–304819
–63159
205798
124363
–107173
–131357
31104
–4511116
–2338095
2425494
2811738
–688945
–2490395
–522533
1741565
1162189
–878642
–1300087
132893
107182
15644
1084786
366118
–71728
–36319
38331
–693209
–588382
283878
38783
580424
–13557
–31453
–1230
34715
–430178
–215231
231231
20983
7729
263758
–11463
–8791
–56082
–220104
–56626
4659
7126
134826
–732
101135
–4687
–50629
–976
–94192
2551
–7546
1339
61387
–1103
33460
–1085
–25549
314
–34123
681
348
16
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表 10. FIR Stage Coefficients (接下页)
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SCALING = 1 / 134217728
LINEAR MINIMUM
SCALING = 1 / 134217728
LINEAR PHASE
SCALING =
1 / 512
LINEAR PHASE
SCALING =
1 / 8388608
LINEAR
PHASE
MINIMUM
PHASE
COEFFICIENT
PHASE PHASE
b98
b99
22008
10620
–8280
–10663
–266
7419
6692
2481
–75
–349
–96
144
78
–46
–42
9
b100
b101
b102
b103
b104
b105
b106
b107
b108
b109
16
0
–432
–132
0
–4
0
0
As shown in 图 52, the FIR frequency response provides a flat pass-band response (±0.003 dB) to 0.375 fDATA
.
图 53 shows the transition band beginning from the edge of the pass band and ending at the beginning of the
stop band. The stop-band response is typically –135 dB above the Nyquist frequency.
As with all oversampled systems, the pass-band response repeats at the underlying ADC sample rate. In this
case, the response repeats at multiples of the modulator frequency (N·fMOD – f0 and N·fMOD + f0, where N = 1, 2,
and so on, and f0 = filter pass band). These image frequencies, if not filtered and otherwise present in the signal,
fold back (or alias) into the pass band causing errors. A low-pass input filter reduces aliasing. For many
applications, the single-pole filter provided at the PGA output is sufficient to suppress the aliased frequencies.
2.0
1.5
20
0
-20
1.0
-40
0.5
-60
0
-80
-0.5
-1.0
-1.5
-2.0
-100
-120
-140
-160
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Normalized Input Frequency (fIN/fDATA
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized Input Frequency (fIN/fDATA
)
)
图 53. FIR Filter Transition Band Magnitude Response
图 52. FIR Filter Pass-Band Magnitude Response
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8.3.5.3 Group Delay and Step Response
The FIR filter has selectable linear or minimum phase response. The pass-band, transition band, and stop-band
responses of the linear and minimum phase filters are similar but differ in the respective phase response.
8.3.5.3.1 Linear Phase Response
Linear phase filters have the property that the input-to-output delay is constant across all input frequencies (that
is, constant group delay). The constant delay property is independent of the nature of the input signal (pulsed or
swept-tone). This filter provides low phase linearity error across frequency when analyzing multi-tone input
signals. However, as shown in 图 54, the associated group delay is longer than that of the minimum phase filter.
The specified number of conversions to result in fully settled data is the same for the linear and minimum filter
profiles.
1.4
Minimum Phase Filter
1.2
1.0
0.8
0.6
0.4
0.2
Linear Phase Filter
0
-0.2
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Time Index (1/fDATA
)
图 54. FIR Step Response
8.3.5.3.2 Minimum Phase Response
Compared to the linear phase filter, the minimum phase filter provides a shorter delay from the arrival of an input
event to the event appearing in the data output. As shown in 图 55, the relationship (phase) is not constant
versus frequency. 表 11 shows that the filter phase is selected by the PHS bit.
35
Linear Phase Filter
30
25
20
15
10
Minimum Phase Filter
5
0
20
40
60
80 100 120 140 160 180 200
Frequency (Hz)
图 55. FIR Group Delay (fDATA = 500 SPS)
表 11. FIR Phase Selection
PHS REGISTER BIT
FILTER PHASE
Linear
0
1
Minimum
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8.3.5.4 HPF Stage
The last stage of the digital filter is a high-pass filter (HPF) implemented as a first-order, IIR structure. This filter
stage blocks DC signals and rolls off low-frequency components below the cutoff frequency. 公式 10 shows the
transfer function for the filter:
-1
2 - a
1 - Z
HPF(Z) =
´
-1
2
1 - bZ
where
•
b is calculated as shown in 公式 11:
(10)
(11)
1 + (1 - a)2
b =
2
The high-pass filter corner frequency is programmed by the HPF[1:0] register bits, in hexadecimal. 公式 12 is
used to set the high-pass filter corner frequency. 表 12 lists example values for the high-pass filter.
cos wN + sin wN - 1
HPF[1:0] = 65,536 1 -
1 - 2
cos wN
where
•
•
•
•
HPF = High-pass filter register value (converted to hexadecimal)
ωN = 2πfHP / fDATA (normalized frequency, radians)
fHP = High-pass filter corner frequency (Hz)
fDATA = Data rate (Hz)
(12)
表 12. High-Pass Filter Value Examples
HPF1, HPF0
0337h
fHP (Hz)
0.5
DATA RATE (SPS)
250
500
0337h
1.0
019Ah
1.0
1000
32
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公式 13 shows the HPF frequency domain transfer function. The HPF results in a small gain error that depends
on the ratio of fHP / fDATA. For many common values of (fHP / fDATA), the gain error is negligible. 图 56 shows the
gain error of the HPF.
0
-0.10
-0.20
-0.30
-0.40
-0.50
0.0001
0.001
0.01
0.1
Frequency Ratio (fHP/fDATA
)
图 56. HPF Gain Error
cos wN + sin wN - 1
cos wN
1 +
1 - 2
HPF Gain =
cos wN + sin wN - 1
cos wN
2 -
(13)
图 57 shows the first-order amplitude and phase response of the HPF. In the case of applied step input or after
synchronizing, make sure to take the settling time of the filter into account.
0
-7.5
90
75
60
45
30
-15.0
-22.5
-30.0
-37.5
-45.0
Amplitude
Phase
15
0
0.01
0.1
1
10
100
Normalized Frequency (f/fC)
图 57. HPF Amplitude and Phase Response
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8.3.6 Reset (RESET Pin and Reset Command)
The ADC is reset in one of three ways: at power-up, by the RESET pin, or by the RESET command. By pin,
drive RESET low for at least 2 fCLK cycles to force a reset. The ADC is held in reset until the pin is released high.
By command, reset takes effect on the next rising fCLK edge occurring after the eighth rising edge of SCLK. In
order to ensure a functional reset by command, the SPI interface may itself require reset; see the Serial Interface
section for details. When the ADC is reset, registers are reset to default values and the conversions are
synchronized on the next rising edge of CLK. Reset timing is illustrated in 图 5, the Timing Requirements table,
and the Switching Characteristics table.
8.3.7 Master Clock Input (CLK)
The ADC requires an external clock for operation. The nominal clock frequency is 1.024 MHz. The clock is
applied to the CLK pin with an amplitude equal to the DVDD supply. As with many precision data converters, a
high-quality clock free from glitches is essential to achieve rated performance. A crystal- or MEMS-type clock
source is recommended because of good temperature stability and low jitter. Make sure to avoid ringing on the
clock input; keep the clock PCB trace as short as possible and routed away from the analog inputs, the PGA
output pins (CAPP, CAPN), and associated analog components. Use a 50-Ω series resistor to terminate the PCB
trace impedance with the resistor placed close to the clock buffer.
8.4 Device Functional Modes
8.4.1 Operational Mode
The ADC has two modes of operation: high resolution and low power. High-resolution mode provides the lowest
noise (maximum SNR performance), whereas low-power mode offers lower power consumption at the expense
of increased noise. 表 13 summarizes noise performance, power consumption, and associated register setting for
each mode. The three register bits, located in the ID/CFG and CONFIG0 registers, must all be set to the same
value (all 0s or all 1s).
表 13. High-Resolution, Low-Power Modes
REGISTER BITS MODE2, MODE1, MODE0
OPERATIONAL MODE
High resolution
SNR (dB)(1)
POWER (mW)
111
000
113
4.5
2.4
Low power
110
(1) SNR at gain = 1, fDATA = 1000 SPS.
8.4.2 Chop Mode
The chop mode modulates the PGA offset and 1/f noise to a frequency outside the ADC pass band where the
offset and 1/f noise residue is removed by the digital filter. Small transient currents occur on the PGA inputs
because of the stray capacitance associated with the internal chop switches. Although the average value of the
transient currents results in high input impedance (> 20 GΩ), in some cases, the transient currents can interact
with high-impedance sensors leading to degraded performance. For these applications, disable the chop mode.
For common types of geophone sensors, chop mode is recommended. Chop mode is enabled by the CHOP bit
of the CONFIG1 register (default is chop enabled).
8.4.3 Offset
As with most ΔΣ modulators, the ADC can produce low-level idle tones (typically 140 dB below the full-scale
amplitude). The idle tones appear as low-frequency components in the output data when either no- or low-level
signals are present. Typically, idle tones do not occur when high-level signals are present. The ADC incorporates
an internal offset option that is intended to reduce the amplitudes of the tone. The offset is recommended for the
low-power mode operation only and is not recommended for the high-resolution mode operation. Use the
external offset circuit illustrated in the Application Information section for idle tone reduction in high-resolution
mode operation.
The offset is enabled by the OFFSET bit of the ID_CFG register. The offset voltage is 50 mV. The 50-mV offset
leads to 2% reduction of the input range that is restored by calibrating the offset voltage by use of the offset
calibration registers. Offset correction is accomplished by performing offset calibration, or to provide nominal
correction, write 029700h to the calibration registers.
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8.4.4 Power-Down Mode
Power the ADC down by driving the PWDN pin low. In power-down mode, the ADC is powered off, including the
internal LDO. In addition, the LDO output (BYPAS pin) connects to DVDD in order to prevent internal floating
circuit nodes to ensure the ADC draws very low leakage current from the supplies. When powered down, the
device outputs remain powered and the device inputs must not be allowed to float, otherwise DVDD leakage
current can occur. The ADC register settings are reset in power-down mode; see 图 6 for power-down mode
timing details.
8.4.5 Standby Mode
Standby is the software power-down mode. In standby mode, the analog and most of the digital circuit blocks are
powered down while the serial interface and the register banks remain active. See the Electrical Characteristics
table for the DVDD supply current in STANDBY mode. To engage standby mode, send the STANDBY command.
To exit standby mode, send the WAKEUP command. 图 6 and the Switching Characteristics table show the
timing. Standby mode is exited whenever CS is high.
The STANDBY, WAKEUP command sequence restores the previous synchronization timing that is lost as a
result of register write operations (continuous-sync mode). See the Continuous-Sync Mode section for details on
how to restore synchronization.
8.4.6 Synchronization
The ADC is synchronized by either the SYNC pin or by the SYNC command. Synchronization by pin occurs on
the next rising edge of CLK after the rising edge of SYNC. Synchronization by command occurs on the next
rising edge of CLK after the eighth bit of the command is received. The ADS1287 has two functional
synchronization modes: pulse sync and continuous sync.
8.4.6.1 Pulse-Sync Mode
In pulse-sync mode, the ADC unconditionally synchronizes on the rising edge of SYNC. When the ADC
synchronizes, the conversion in progress is stopped and a new conversion is started. The internal filter memory
is reset at the start of the new conversion. As a result of the computational latency of the digital filter, the ADC
suppresses the first 63 conversion results until the digital filter is fully settled. 图 4, the Timing Requirements
table, and the Switching Characteristics table illustrate the SYNC input timing and conversion propagation
delays.
The ADC also synchronizes at the occurrence of a register write operation and the previous synchronization is
lost. To re-synchronize, pulse the SYNC pin (or send the SYNC command) at the desired time, after the register
write operation.
8.4.6.2 Continuous-Sync Mode
In continuous-sync mode, the ADC synchronizes on the first rising edge of the SYNC pin after configuring the
ADC to the continuous-sync mode. On the subsequent rising edges of SYNC, the ADC re-synchronizes only if
the SYNC input period is not equal to an integer multiple of the data rate period by at least ±1 / fCLK (that is, the
SYNC period ≠ N /fDATA ± 1 /fCLK, where N = 1, 2, 3, and so forth). The period of SYNC can be indefinite. If the
periods are not divisible by an integer, the ADC re-synchronizes. In this mode, a periodic synchronizing clock can
be applied to the ADC, resulting in autonomous synchronization.
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When synchronization occurs, DRDY continues to pulse but the ADC forces the data to zero until the data are
settled (approximately 63 DRDY periods later). At the 63rd conversion, valid data are output. See 图 4 for an
illustration of DRDY behavior. The phase relationship between SYNC and DRDY also depends on the data rate
because of the slight dependence of filter group delay to data rate. 图 58 shows an example of the phase
relationship between SYNC and DRDY. The SYNC pin only can be used to control continuous-sync mode.
N / fDATA
SYNC
1 / fDATA
DRDY
图 58. Continuous-Sync Mode
The ADC synchronizes at the occurrence of a register write operation resulting in loss of the previous
synchronization. To re-establish the previous synchronization (in continuous-sync mode), send the STANDBY,
WAKEUP command sequence. The re-synchronization sequence is valid provided the time between the
STANDBY and WAKEUP commands is not equal to the data rate period by at least ± 1 / fCLK period.
8.4.7 Reading Data
The ADC has two modes to read conversion data: read-data-continuous (RDATAC mode) and read-data-by-
command (SDATAC mode).
8.4.7.1 Read-Data-Continuous Mode (RDATAC)
In read-data-continuous mode, conversion data are read without the need of a read data command. When DRDY
asserts low (indicating new data), the MSB of data appears on DOUT. Read data by applying the serial interface
clock on SCLK; see 图 3 for DRDY to DOUT timing.
As shown in 图 59, conversion data are read by first driving CS low and then shifting the data by applying the
serial interface clock to SCLK. Latch the data on the rising edge of SCLK. On the first falling edge of SCLK, the
ADC returns DRDY high. After all 32 bits of conversion data are read, further SCLK transitions result in DOUT
driven low. If desired, the read operation can be stopped after 24 bits. A new read cycle is started when new
conversion data are available. The data read operation must be completed four CLK periods prior to the next
DRDY falling edge, otherwise the data are overwritten with new conversion data.
(1)
CS
DRDY
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 25 26 27 28 29 30 31 32
SCLK
DOUT
DIN
Data Byte 1 (MSB)
Data Byte 2 (MSB - 1)
Data Byte 4 (LSB)
(1) DOUT is in tri-state mode when CS is high. SCLK arrows indicate when the data are latched.
图 59. Read-Data-Continuous Mode
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8.4.7.2 Stop-Read-Data-Continuous-Mode (SDATAC)
In SDATAC mode, a command is required in order to read conversion data. Send the SDATAC command to first
engage the mode. Send an RDATA command, as shown in 图 60, for each data retrieval operation. After the
eighth SCLK rising edge of the RDATA command, conversion data are ready when the ADC drives DRDY low
(see the Switching Characteristics table for tP(CMDR) timing). tP(CMDR) is dependent on the timing of the command
relative to the conversion phase. When DRDY goes low, MSB conversion data appear on DOUT and the data
shift operation can begin (see 图 3 for DRDY to DOUT timing). The RDATA command must be sent at least as
often as the data rate or data are lost. Driving CS high cancels the SDATAC mode; therefore, the SDATAC mode
must be reset if CS is taken high prior to each RDATA operation.
(1)
tp(CMDR)
CS
DRDY
SCLK
td(CMBT)
17 18 19 20 21 22 23 24
41 42 43 44 45 46 47 48
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
DIN
RDATA
SDATAC
DOUT
Data Byte 1 (MSB)
Data Byte 4 (LSB)
Don't Care
(1) If CS taken high, send the SDATAC command prior to the RDATA command. SCLK arrows indicate when the data
are latched.
图 60. Read Data By Command Mode
8.4.8 Conversion Data Format
As shown in 表 14, the conversion data are 32 bits in binary two's complement format. The LSB of the data is a
redundant sign bit: 0 for positive numbers and 1 for negative numbers. However, when the data are clipped to
FS, the LSB = 1 and when the data are clipped to –FS, the LSB = 0. If desired, the data readback can be
stopped after 24 bits. In sinc-filter mode, the data are numerically scaled by half.
表 14. Ideal Output Code Versus Input Signal
32-BIT IDEAL OUTPUT CODE(1)
INPUT SIGNAL VIN
> VREF / Gain
FIR FILTER
7FFFFFFFh
7FFFFFFEh
00000002h
00000000h
FFFFFFFFh
80000001h
80000000h
SINC FILTER(2)
(3)
—
VREF / Gain
3FFFFFFFh
00000001h
00000000h
FFFFFFFFh
C0000000h
VREF / (Gain · 230
)
0
–VREF / (Gain · 230
)
–VREF / (Gain · (230/ (230 – 1)))
< –VREF / (Gain · (230/ (230 – 1)))
(3)
—
(1) Excludes effects of noise, linearity, offset, and gain errors.
(2) As a result of the reduction in oversampling ratio (OSR) related to high data rates of the sinc filter mode, the available ADC resolution
correspondingly reduces.
(3) When the full-scale range is exceeded in sinc filter mode, the conversion data exceeds half-scale code (3FFFFFFFh and C0000000h).
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8.4.9 Offset and Full-Scale Calibration Registers
Offset and gain errors are corrected by the offset and full-scale calibration registers. As shown in 图 61, the
conversion result is first subtracted by the offset register (OFC) and then multiplied by the correction factor
derived from the full-scale register (FSC). These operations occur before the 32-bit clip stage. 公式 14 shows the
offset and full-scale correction.
FSC[2:0]
Final Output Data = (Input - OFC[2:0]) ´
400000h
(14)
AINP
AINN
+
Output Data
Clipped to 32 Bits
Digital
Filter
´
Final Output
Modulator
S
-
OFC
Register
FSC Register
400000h
图 61. Calibration Block Diagram
The offset and full-scale registers are written directly by the user, or the values are determined automatically as a
result of calibration operations. One set of offset and full-scale registers apply for all gain factors. Unique values,
depending on system accuracy requirements, may be required for each gain to improve the gain-matching
performance. The calibration operation is bypassed in the sinc filter mode.
8.4.9.1 OFC[2:0] Registers
表 15 shows that the offset calibration register is a 24-bit word composed of three 8-bit registers. The offset
register is left-justified in order to align with the 32-bit conversion data. The offset value is in two's complement
format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The register data
are subtracted from the conversion data. Register data equal to 00000h perform no offset correction (default).
表 15. Offset Calibration Word
REGISTER
OFC0
BYTE
LSB
BIT ORDER
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
OFC1
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
OFC2
MSB
B23 (MSB)
B17
B16
Although the offset calibration register can accommodate values from –FS to FS (as shown in 表 16), the post-
calibrated input voltage cannot exceed 106% of the nominal input range.
表 16. Offset Calibration Values
OFC[2:0] REGISTERS
00007Fh
FINAL OUTPUT CODE(1)
FFFF8100h
000001h
FFFFFF00h
000000h
00000000h
FFFFFFh
00000100h
FFFF7Fh
00008100h
(1) Ideal post-calibration value with zero voltage input.
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8.4.9.2 FSC[2:0] Registers
表 17 shows that the full-scale calibration register is a 24-bit word, composed of three 8-bit registers. The full-
scale calibration value is 24-bit, straight-offset binary, normalized to a scale factor of 1.0 for a register value of
400000h.
表 17. Full-Scale Calibration Word
REGISTER
FSC0
BYTE
LSB
BIT ORDER
B7
B15
B6
B5
B4
B3
B2
B1
B9
B0 (LSB)
B8
FSC1
MID
B14
B22
B13
B21
B12
B20
B11
B19
B10
B18
FSC2
MSB
B23 (MSB)
B17
B16
表 18 summarizes the scaling of the full-scale calibration register. A register value equal to 400000h (default
value) yields a unity-gain scale factor. Although the full-scale calibration register value can be used to correct
gain errors > 1 (gain scale factor < 1), the post-calibrated input voltage cannot exceed 106% of the nominal input
range.
表 18. Full-Scale Calibration Register Values
FSC[2:0] REGISTERS
433333h
SCALE FACTOR
1.05
1.00
0.95
400000h
3CCCCCh
8.4.10 Calibration Command
The calibration commands (OFSCAL or GANCAL) perform calibration on demand. These commands compute
the offset and gain correction register factors, respectively. The appropriate calibration voltage must be applied
for calibration. Low data rates are able to provide more consistent calibration results resulting from lower noise
compared to high data rates. If calibrating at system power-on, be sure the reference voltage is fully settled.
Calibration is not available when operating in the sinc filter mode.
图 62 shows the calibration command sequence. Apply the appropriate calibration voltage to the ADC. After the
input voltage stabilizes, send the SDATAC, SYNC, and RDATAC commands in sequence (allow 24 / fCLK gaps
between commands). DRDY is then driven low 64 data periods later. After DRDY is driven low, send the
SDATAC command, then the calibration command (OFSCAL or GANCAL), followed by the RDATAC command.
After 16 data periods, calibration completion is indicated when DRDY is driven low. The calibrated conversion
data are available at this time. The SYNC input must remain high during the calibration sequence.
VIN
Fully stable input and reference voltage.
OFSCAL or
Commands
SDATAC
SYNC
RDATAC
SDATAC
RDATAC
GANCAL
Calibration
Complete
16 Data
Periods
DRDY
SYNC
64 Data Periods
图 62. Calibration Command Sequence
8.4.10.1 OFSCAL Command
The OFSCAL command performs the offset calibration. To calibrate, apply a zero voltage input to the ADC or
select the internal shorted input channel via the input multiplexer and allow the inputs to stabilize. Send the
command sequence as illustrated in 图 62. The ADC averages 16 readings to reduce the effects of noise and
then writes the 24-bit truncated result to the OFC register. During offset calibration, the full-scale correction is
bypassed. The optional 50-mV internal offset can be calibrated using the calibration command in order to restore
the full input voltage range.
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8.4.10.2 GANCAL Command
The GANCAL command performs gain calibration. To calibrate, apply a positive full-scale DC input to the ADC
and allow the inputs to stabilize. Send the command sequence as illustrated in 图 62. The ADC averages 16
readings to reduce the effects of noise and then computes a 24-bit scale factor value. This value is written to the
FSC register.
8.4.11 User Calibration
ADC calibration can be performed by the user without using calibration commands. This procedure requires the
user to apply the appropriate calibration voltage as with using calibration commands, but in this case the user
computes the calibration values based on the conversion result and then writes the value to the calibration
registers. The procedure for user calibration is as follows:
1. Set the OFSCAL[2:0] register = 0h, and GANCAL[2:0] = 400000h. These values set the offset and gain
factors to 0 and 1, respectively.
2. Apply zero voltage or short the inputs (example: set the ADC mux to internal short). Wait for the input voltage
and the ADC to settle for a minimum of 63 conversions and then begin averaging of a number of conversion
results. Averaging conversions results in a more accurate calibration. Write the 24-bit averaged value to the
OFC register.
3. Apply a DC or AC calibration voltage at least 5% below full-scale. Be sure not to be near or exceed 100%
FSR otherwise the conversion data clips, resulting in erroneous calibration. Wait for the calibration voltage
and the ADC to settle for a minimum of 63 conversions. Use 公式 15 or 公式 16 to compute the scale factor
value.
公式 15 shows the DC calibration voltage. Use the average value of the ADC data.
Expected Output Code
FSC[2:0] = 400000h ´
Actual Output Code
(15)
公式 16 shows the AC calibration voltage. Use an RMS value of the ADC data.
Expected RMS Value
FSC[2:0] = 400000h ´
Actual RMS Value
(16)
8.5 Programming
8.5.1 Serial Interface
The serial interface is used to read conversion data and to read or write control register data. The interface is
SPI compatible and consists of the following signals: CS, SCLK, DIN, and DOUT.
8.5.1.1 Chip Select (CS)
Chip select is an active-low input that enables the ADC serial interface for communication. CS must remain low
for the duration of the ADC data transfer. When CS is high, SCLK activity is ignored, in-progress data transfer or
commands are terminated, and DOUT (data output pin) enters a high-impedance state. When CS is driven high,
the ADC terminates standby mode and also resets the mode to read data continuous (RDATAC); see the Stop-
Read-Data-Continuous-Mode (SDATAC) section for more information.
8.5.1.2 Serial Clock (SCLK)
The serial interface clock (SCLK) is an input that is used to shift data into and out of the ADC. The ADC latches
data on DIN at the rising edge of SCLK. Data are shifted out on DOUT at the falling edge of SCLK. Keep SCLK
low when not active. The SCLK pin is a noise-resistant, Schmitt-trigger input that reduces the possibility of noise-
induced false edges. However, keep SCLK as clean as possible to prevent possible glitches from inadvertently
shifting the data.
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Programming (接下页)
8.5.1.3 Data Input (DIN)
The data input pin (DIN) is used to input register data and commands to the ADC. The ADC latches input data
on the rising edge of SCLK. In read-data-continuous mode, keep DIN low when clocking out conversion data.
The exception to keeping DIN low is to interrupt the read-data-continuous mode by sending the SDATAC
command.
8.5.1.4 Data Output (DOUT)
The data output pin (DOUT) provides the ADC output data. Data are shifted out on the falling edge of SCLK and
are read by the user on the following rising edge of SCLK. Keep the DOUT trace length to minimum to reduce
the effects of inter-symboling noise effects within the ADC. When CS is high, DOUT is forced to hi-Z.
8.5.1.5 Serial Interface Timeout
When CS is low, the serial interface times-out (resets) if SCLK is held low for 64 DRDY cycles. Reset of the
serial interface terminates commands in progress. When reset, the next SCLK pulse starts a new communication
cycle. To prevent timeout and reset of the serial interface, provide at least one SCLK pulse for every 64 DRDY
pulses.
8.5.1.6 Data Ready (DRDY)
DRDY is an output that indicates when new conversion data are ready. DRDY is always actively driven
regardless whether CS is high or low. When reading data in the read data continuous mode, the read operation
must be completed four CLK periods prior to the next DRDY falling edge, or the data are overwritten by new
conversion data.
During data readback, DRDY is driven high on the first falling edge of SCLK. 图 63 and 图 64 show the function
of DRDY with and without data readback, respectively. If data are not retrieved (no SCLK provided), as shown in
图 64, DRDY pulses high for four fCLK periods during the update time.
Data Updating
4/fCLK
DRDY
DOUT
SCLK
DRDY
Bit 31
Bit 30
Bit 29
图 63. DRDY With Data Retrieval
图 64. DRDY With No Data Retrieval
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Programming (接下页)
8.5.2 Commands
The commands listed in 表 19 control ADC operation. Most commands are stand-alone (that is, one byte in
length); the register read and write command lengths are two bytes, plus additional data bytes that represent the
actual register data.
表 19. Command Descriptions
COMMAND
WAKEUP
STANDBY
SYNC
TYPE
Control
Control
Control
Control
Control
Control
Data
DESCRIPTION
Wake-up from standby mode
Enter standby mode
1ST COMMAND BYTE(1)(2)
0000 000X (00h or 01h)
0000 001X (02h or 03h)
0000 010X (04h or 5h)
0000 011X (06h or 07h)
0001 0000 (10h)
2ND COMMAND BYTE(3)
Synchronize ADC conversions
Reset the ADC
RESET
RDATAC
SDATAC
RDATA
Read data continuous mode
Stop read data continuous mode
Read data by command(4)
Read nnnnn registers at address rrrrr(4)
Write nnnnn registers at address rrrrr
0001 0001 (11h)
0001 0010 (12h)
RREG
Register
Register
001r rrrr (20h + 000r rrrr)
010r rrrr (40h + 000r rrrr)
0110 0000 (60h)
000n nnnn (00h + n nnnn)
000n nnnn (00h + n nnnn)
WREG
OFSCAL
GANCAL
Calibration Offset calibration
Calibration Gain calibration
0110 0001 (61h)
(1) X = don't care.
(2) rrrrr = starting address for register read and write commands.
(3) nnnnn = number of registers to be read from or written to – 1. For example, to read from or write to three registers, set nnnnn = 2
(00010).
(4) Required to cancel read-data-continuous mode before sending a command.
CS must remain low for the duration of the command-byte sequence. Provide a 24 / fCLK delay between
commands, between bytes within a command, and from the last byte of a command prior to returning CS high.
The required delay starts from the last SCLK rising edge of the preceding byte to the first SCLK rising edge of
the following byte; see 图 2. The delay between data bytes is not necessary when reading conversion data.
8.5.2.1 WAKEUP: Wake Up Command
The WAKEUP command is used to exit standby mode and to resume normal operation. The STANDBY,
WAKEUP sequence is illustrated in 图 65. 图 6 illustrates the time for new conversion data. After writing the ADC
registers, the ADC restarts the filter cycle and, as a consequence, results in loss of the previous synchronization.
In continuous synchronization mode, use the STANDBY, WAKEUP command sequence to restore the previous
synchronization; see the Continuous-Sync Mode section for details.
8.5.2.2 STANDBY: Standby Mode Command
The STANDBY command engages standby mode. In standby, ADC conversions are stopped and the ADC
enters a low-power mode. The register settings are retained in this mode. The ADC remains in standby mode
until CS is taken high or the WAKEUP command is sent. For complete device shutdown, take the PWDN pin low.
图 65 shows the operation of the STANDBY, WAKEUP sequence.
0000 001X
(STANDBY)
0000 000X
(WAKEUP)
DIN
SCLK
Operating
Standby Mode
Operating
图 65. STANDBY Command Sequence
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8.5.2.3 SYNC: Synchronize ADC Conversions
The SYNC command synchronizes the analog-to-digital conversion. Upon receiving the SYNC command, the
read in progress is cancelled and the conversion process is restarted. In order to synchronize multiple ADCs, the
command must be sent simultaneously to all devices. The SYNC pin must be held high when this command
used. The SYNC command is also required in the calibration command sequence.
8.5.2.4 RESET: Reset Command
The RESET command resets the ADC. RESET sets the registers back to default, restarts the conversion
process, and engages read-data-continuous mode. The RESET command is functionally equivalent to using the
RESET pin, however toggle the CS pin prior to the RESET command to ensure that the serial interface is reset.
See 图 5 for the RESET command timing.
8.5.2.5 RDATAC: Read Data Continuous Mode Command
The RDATAC command programs the read-data-continuous mode (default mode). In this mode, conversion data
can be read directly by applying serial interface clocks (no read data command is necessary). Each time DRDY
transitions low, new data are available to read; see the Read-Data-Continuous Mode (RDATAC) section for more
details.
8.5.2.6 SDATAC: Stop Read Data Continuous Mode Command
The SDATAC command stops read-data-continuous mode. This mode is required before sending register read or
write commands and before issuing the data read command (RDATA). CS high cancels the SDATAC mode.
Send the RDATAC command to cancel SDATAC mode; see the Stop-Read-Data-Continuous-Mode (SDATAC)
section for more details.
8.5.2.7 RDATA: Read Data Command
The RDATA command is necessary to read the conversion data in SDATAC mode. The RDATA command must
be sent for each read of conversion data; see the Stop-Read-Data-Continuous-Mode (SDATAC) section for
details.
8.5.2.8 RREG: Read Register Data Command
The RREG command is used to read a single register byte or to read multiple register bytes. The command
consists of a two-byte argument followed by the output of register data. The first byte of the command is the
register starting address, and the second byte specifies the number of registers to read minus one.
First command byte: 001r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to read minus one.
In the read register data example sequence shown in 图 66, with the 24th falling edge of SCLK, the first register
data bit appears on DOUT. Read the first bit of register data on the 25th SCLK rising edge.
See the Timing Requirements table for the specification of the td(CMBT) parameter.
CS
td(CMBT)
td(CMBT)
35
36
td(CMBT)
td(CMBT)
37
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
33 34
SCLK
DIN
RREG Byte 1
Don't Care
SDATAC
RREG Byte 2
DOUT(1)
Register Data 5
Register Data 6
Example: Read six registers, starting at register 05h (OFC0)
RREG Byte 1 = 0010 0101
RREG Byte 2 = 0000 0101
(1) DOUT is in tri-state when CS is high.
图 66. Read Register Data
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In read-data-continuous mode, the output data shift register is written with new conversion data just before
DRDY transitions low. To avoid conflicting data between conversion data and register data, send the SDATAC
command before reading register data. The SDATAC command disables loading of conversion data into the
output data shift register. Keep CS low between the SDATAC command and the read register command because
CS high cancels the SDATAC mode.
8.5.2.9 WREG: Write Register Data Command
The WREG command writes a single register byte or writes multiple register bytes. The command consists of a
two-byte argument followed by the register data to write. The first byte of the argument is the register starting
address and the second byte specifies the number of registers to write minus one.
First command byte: 010r rrrr, where rrrrr is the starting address of the first register.
Second command byte: 000n nnnn, where nnnnn is the number of registers to write minus one.
Data bytes: one or more register data bytes, depending on the number of registers specified.
图 67 shows the WREG command. See the Timing Requirements table for the specification of the td(CMBT)
parameter.
CS
td(CMBT)
td(CMBT)
35
36
td(CMBT)
td(CMBT)
37
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32
33 34
SCLK
DIN
SDATAC
WREG Byte 1
Register Data 5
Register Data 6
WREG Byte 2
DOUT(1)
Don't Care
Example: Write six registers, starting at register 05h (OFC0)
WREG Byte 1 = 0100 0101
WREG Byte 2 = 0000 0101
(1) DOUT is in tri-state when CS is high.
图 67. Write Register Data
After writing to the ADC registers, the ADC synchronizes at the time of the write operation. ADC synchronization
is re-established in pulse-sync mode by pulsing the SYNC pin at the desired time mark. In continuous-sinc mode,
the previous synchronization is restored at any time by sending the STANDBY, WAKEUP command sequence;
see the Continuous-Sync Mode section for details.
8.5.2.10 OFSCAL: Offset Calibration Command
The OFSCAL command performs an offset calibration. The inputs to the system (or ADC) must be zeroed and
allowed to stabilize before sending this command. The offset calibration register is updated after this operation;
see the Calibration Command section for more details.
8.5.2.11 GANCAL: Gain Calibration Command
The GANCAL command performs a gain calibration. The inputs to the system (or ADC) is a full-scale, DC
calibration voltage. The gain calibration register is updated after the operation completes; see the Calibration
Command section for more details.
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8.6 Register Map
Collectively, the registers contain all the information needed to configure the device (such as data rate, filter
mode, calibration, and so on). The registers are accessed by the read and write register commands (RREG and
WREG, respectively). The registers are accessed either individually, or as a block by sending or receiving
consecutive register data bytes. After the register write operation is completed, the conversion cycle restarts.
Restart results in loss of the previous synchronization. Re-synchronize after writing the device registers; see the
Synchronization section for details. 表 20 lists the ADS1287 registers.
表 20. Register Map
RESET
ADDRESS
00h
REGISTER
ID/CFG
CONFIG0
CONFIG1
HPF0
VALUE
X0h
52h
08h
32h
03h
00h
00h
00h
00h
00h
40h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ID[3:0]
MODE[2:1](1)
OFFSET
RESERVED
01h
SYNC
BIAS(2)
MODE[0](1)
DR[2:0]
PHASE
FILTR[1:0]
GAIN[2:0]
02h
RESERVED
MUX[1:0]
CHOP
03h
HPF[7:0]
04h
HPF1
HPF[15:8]
OFC[7:0]
05h
OFC0
06h
OFC1
OFC[15:8]
OFC[23:16]
FSC[7:0]
07h
OFC2
08h
FSC0
09h
FSC1
FSC[15:8]
FSC[23:16]
0Ah
FSC2
(1) The MODE[2:1] and MODE[0] bits must be set to all 1s or all 0s; see the Operational Mode section.
(2) The BIAS bit must be written to 1 after power-on or after reset.
8.6.1 Register Descriptions
表 21 lists the register access types for the ADS1287 registers.
表 21. ADS1287 Access Type Codes
Access Type
Code
R
Description
Read
R
R-W
W
R/W
W
Read or write
Write
-n
Value after reset or the default
value
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8.6.1.1 ID/CFG: ID, Configuration Register (address = 00h) [reset = x0h]
图 68. ID/CFG Register
7
6
5
4
3
2
1
0
ID[3:0]
R-x
MODE[2:1]
R/W-0h
OFFSET
R/W-0h
RESERVED
R/W-0h
表 22. ID/CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7:4
ID[3:0]
R
---
Factory-programmed identification bits (read-only).
The ID bits are subject to change without notification.
3:2
MODE[2:1]
R/W
0h
Operating mode.
These bits must be set the same as the MODE[0] bit; see the
CONFIG0 register.
00: Low-power mode
01: Reserved
10: Reserved
11: High-resolution mode
1
0
OFFSET
R/W
R/W
0h
0h
50-mV offset option.
See the Offset section.
0: Offset disabled (default)
1: Offset enabled
RESERVED
Reserved.
Always write 0.
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8.6.1.2 CONFIG0: Configuration Register 0 (address = 01h) [reset = 52h]
图 69. CONFIG0 Register
7
6
5
4
3
2
1
0
SYNC
R/W-0h
MODE[0]
R/W-1h
DR[2:0]
R/W-2h
PHASE
R/W-0h
FILTR[1:0]
R/W-2h
表 23. CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
SYNC
R/W
0h
Synchronization mode configuration bit.
0: Pulse-sync mode (default)
1: Continuous-sync mode
6
MODE[0]
DR[2:0]
R/W
R/W
1h
2h
Operating mode bit.
This bit must be set in coordination with MODE2 and MODE1
bits; see 表 22.
0: Low-power mode
1: High-resolution mode
5:3
Data rate bits.
000: 62.5 SPS
001: 125 SPS
010: 250 SPS (default)
011: 500 SPS
100: 1000 SPS
2
PHASE
R/W
R/W
0h
2h
FIR phase response bit.
0: Linear phase (default)
1: Minimum phase
1:0
FILTR[1:0]
Digital filter configuration bits.
00: Reserved
01: LPF sinc filter only
10: LPF sinc + LPF FIR filter (default)
11: LPF sinc + LPF FIR + HPF filter
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8.6.1.3 CONFIG1: Configuration Register 1 (address = 02h) [reset = 08h]
图 70. CONFIG1 Register
7
6
5
4
3
2
1
0
BIAS
RESERVED
R/W-0h
MUX[1:0]
R/W-0h
CHOP
R/W-1h
PGA[2:0]
R/W-0h
R/W-0h
表 24. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
BIAS
R/W
0h
ADC bias.
Always write 1 to this bit.
0: Bias disabled (default)
1: Bias enabled (always write 1)
6
RESERVED
MUX[1:0]
R/W
R/W
0h
0h
Reserved.
Always write 0.
5:4
Input MUX select bits.
00: External input (default)
01: Reserved
10: Internal input short connection to VCOM
11: Reserved
3
CHOP
R/W
R/W
1h
0h
Chop enable bit.
See the Chop Mode section.
0: Chop disabled
1: Chop enabled (default)
2:0
PGA[2:0]
PGA gain select bits.
000: Gain = 1 V/V (default)
001: Gain = 2 V/V
010: Gain = 4 V/V
011: Gain = 8 V/V
100: Gain = 16 V/V
101–111: Reserved
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8.6.1.4 High-Pass Filter Corner Frequency (HPFx) Registers (address = 03h, 04h) [reset = 32h, 03h]
图 71. HPF0 Register
7
7
6
5
4
3
2
2
1
1
0
0
HPF[7:0]
R/W-32h
图 72. HPF1 Register
6
5
4
3
HPF[15:8]
R/W-03h
表 25. HPF0, HPF1 Registers Field Description
Bit
Field
Type
Reset
Description
High-pass filter corner frequency registers.
7:0
HPF[15:0]
R/W
0332h
These two registers program the corner frequency of the high-
pass filter; see the HPF Stage section for details.
8.6.1.5 Offset Calibration (OFCx) Registers (address = 05h, 06h, 07h) [reset = 00h, 00h, 00h]
图 73. OFC0 Register
7
7
7
6
6
6
5
5
5
4
3
2
2
2
1
1
1
0
0
0
OFC[7:0]
R/W-00h
图 74. OFC1 Register
4
3
OFC[15:8]
R/W-00h
图 75. OFC2 Register
4
3
OFC[23:16]
R/W-00h
表 26. OFC0, OFC1, OFC2 Registers Field Description
Bit
Field
Type
Reset
Description
7:0
OFC[23:0]
R/W
000000h
Offset calibration registers.
These three registers are the 24-bit offset calibration word. The
offset calibration is in two's complement format. The ADC
subtracts the offset value from the conversion result prior to the
full-scale operation.
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8.6.1.6 Full-Scale Calibration (FSCx) Registers (address = 08h, 09h, 0Ah) [reset = 00h, 00h, 40h]
图 76. FSC0 Register
7
7
7
6
6
6
5
5
5
4
3
2
2
2
1
1
1
0
0
0
FSCAL[7:0]
R/W-00h
图 77. FSC1 Register
4
3
FSCAL[15:8]
R/W-00h
图 78. FSC2 Register
4
3
FSCAL[23:16]
R/W-40h
表 27. FSC0, FSC1, FSC2 Registers Field Description
Bit
Field
FSCAL[23:0]
Type
Reset
Description
7:0
R/W
400000h
Full-scale calibration registers.
These three registers are the 24-bit, full-scale calibration word.
The full-scale calibration is in straight binary format. The ADC
divides the register value by 400000h, then multiplies the
conversion data. The scaling operation occurs after the offset
operation.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS1287 is a high-resolution ADC optimized for low-power operation in seismic data acquisition equipment.
Optimum performance requires special attention to the support circuitry and printed-circuit board (PCB) layout.
As much as possible, locate noisy digital components (such as microcontrollers, oscillators, and so forth) in a
PCB area away from the ADC and analog front-end components. Locating the digital components close to the
power-entry point keeps the digital current return path short and separated from sensitive analog components.
9.2 Typical Applications
9.2.1 Geophone Application
图 79 illustrates a typical geophone application circuit. The application shows the ADC operating on a bipolar
±2.5-V analog supply voltage. The power-supply voltages are provided by low-dropout (LDO) regulators to
provide well-regulated, low-noise supply voltages to the ADC. The ADC also operates using with a unipolar 5-V
analog supply voltage. The 6-V zener diode between AVDD and AVSS clamps the ADC supply voltage if the
inputs are driven when the ADC supply voltage is off.
Resistors R1 and R2 bias the floating geophone to mid-supply. The resistors also provide a return path for the
ADC input current. To prevent pickup of PCB ground-related noise, connect the resistors together first, then
connect to ground. For unipolar-supply operation, make this connection to a low-impedance 2.5-V voltage.
The geophone signal is filtered both differentially, by components C3 and R3 through R6, and common-mode
filtered by components C1, C2 and R3, R4. The differential filter removes normal-mode noise. The common-mode
filters remove noise that is common to both inputs. The differential filter high-cut frequency is 10 times lower to
minimize the effects of component mismatch of the common-mode filter that otherwise can lead to degraded
differential-filter performance. Adjust the filter components according to the application requirements. The
protection diodes protect the ADC inputs from system-level ESD transients and signal overrange events.
A low-noise, low-power, 2.5-V voltage reference drives the ADC reference input. The voltage reference ground
terminal is connected to –2.5 V. R9 and C5 form an optional 2-Hz noise filter to reduce voltage reference noise.
Capacitor C6 filters the reference sampling glitches. Place the capacitor directly at the ADC pins. Multiple ADCs
can share a single reference but place a 0.1-µF capacitor at each ADC reference input.
Capacitor C4 (10 nF), located at the CAPP and CAPN pins, filters modulator sampling glitches. The capacitor
also provides a antialiasing filter with a high cutoff corner frequency of approximately 9.5 kHz. Resistors R7 and
R8 provide an offset voltage to the modulator for idle tone reduction when operating in high-resolution mode. Use
the internal offset in low-power mode operation. The resistors are not needed in this case.
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Typical Applications (接下页)
3 V
-3 V
2.5 V
- 2.5 V
2.5 V
LDO
-2.5 V
LDO
6 V
0.1 mF
0.1 mF
0.1 mF
0.1 mF
C7
1 mF
AVSS
2.5 V
AVDD
R3
R5
(1)
100 Ω
100 Ω
AINP
C1
R1
C3
1000 pF
C0G
100 pF, C0G
20 kΩ
ADS1287
Geophone
R2
R4
R6
C2
20 kΩ 100 Ω
100 Ω
100 pF, C0G
AINN
(1) Optional Protection Diodes, See Text
-2.5 V
(2) Optional Offset, See Text
R7
R8
100 kΩ
100 kΩ
CAPP
CAPN
C4
10 nF
C0G
R9
(2)
2 kΩ
2.5 V
Reference
REFP
REFN
2.5 V
C5
47 µF
C
+
6
1 mF
1 mF
0.1 mF
-
2.5 V
(3) Optional Reference Noise Filter,
See Text
DGND
图 79. Geophone Analog Interface
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Typical Applications (接下页)
9.2.2 Digital Interface
图 80 shows the digital connections to a controller, such as a field programmable gate array (FPGA) or
microcontroller. Place the digital bypass capacitors on DVDD and the LDO output (BYPAS) close to the device
pins and directly to the ground plane. Connections to the RESET and PWDN pins are optional. If not used, tie
the inputs to DVDD. Avoid ringing on the digital inputs of the ADC. For long PCB traces, use 47-Ω series
termination resistors to help reduce ringing by controlling the trace impedance. Place the resistors at the source
(output driver).
1.024 MHz
Clock
SYNC
Control
47 Ω
ADS1287
Controller
47 Ω
2.5 V œ 3.3 V
CLK
DVDD
SYNC
1 µF
47 Ω
47 Ω
47 Ω
BYPAS
CS
SS
1 µF
SCLK
SCLK
MOSI
MISO
DIN
47 Ω
DOUT
47 Ω
IRQ
DRDY
47 Ω
47 Ω
RESET
PWDN
Output
Output
DGND
DGND
DGND
图 80. Digital Connections
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9.3 Initialization Set Up
After reset or power-on, configure the ADC using the following procedure:
1. Reset the serial interface. Before beginning communication to the ADC, the serial interface may have to be
recovered (undefined I/O power-up sequencing can cause a false SCLK to occur). To reset the interface,
toggle the CS pin high to low, or toggle the RESET pin.
2. Configure the registers. For proper operation, the MODE[2:0] bits and the BIAS bit must be programmed
appropriately; see the MODE[2:0] bits in 表 20.
3. Verify register data. For verification of device communications, read back the register data.
4. Set the data mode. After register configuration, configure the device for read-data-continuous mode by
sending the RDATAC command.
5. Synchronize readings. After power-on, the ADCs are unsynchronized and conversions freely run. To
synchronize the conversions in pulse-sync mode, take SYNC low and then high. In continuous-sync mode,
apply the synchronizing clock to the SYNC pin under the operating constraint that the SYNC input period is
equal to integer multiples of the ADC conversion period.
6. Read data. In read-data-continuous mode, the data are read after DRDY falls by shifting the data out directly
(no command). If the stop-read-data-continuous mode is selected, read the data by sending the RDATA
command. The RDATA command must be sent in this mode for each conversion result.
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10 Power Supply Recommendations
The ADC has three power supplies: AVDD, AVSS, and DVDD.
10.1 Analog Power Supplies
The analog power supply can be either bipolar ±2.5 V (AVDD and AVSS) or unipolar 5 V (AVDD) with AVSS tied
to ground.
10.2 Digital Power Supply
The DVDD supply range is 2.25 V to 3.6 V. DVDD is the I/O voltage and is also sub-regulated by the internal
1.8-V LDO to power the digital circuitry. The LDO output is the BYPAS pin. Connect a 1-µF capacitor from
BYPAS to DGND and a 1-µF capacitor from DVDD to DGND. Make no other connection or load to the BYPAS
pin.
10.3 Power-Supply Sequence
The power supplies can be sequenced in any order. At power-on, the difference of (AVDD – AVSS) and DVDD
are monitored by internal comparators that are logical AND'd to produce the internal reset signal. After the power
supplies have crossed the respective thresholds, 216 fCLK cycles are counted before the ADC exits the reset state
and is ready for communication. New conversion data are available; see 图 7 and the Switching Characteristics
table.
11 Layout
11.1 Layout Guidelines
In most cases, a single continuous ground plane connecting the analog and digital components is preferred. Use
wide, low-impedance PCB traces or dedicated layers for the power-supply connections because the analog
supply current is partially modulated by the input signal. Also use wide PCB traces or dedicated layers for REFP
and REFN. If REFN and AVSS are connected together, use a Kelvin connection at the voltage regulator ground
terminal. These practices help maintain good THD performance and minimal crosstalk errors when multiple
ADCs are used.
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12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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版权 © 2017–2019, Texas Instruments Incorporated
59
ADS1287
ZHCSK67B –JUNE 2017–REVISED AUGUST 2019
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版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1287IRHFR
ADS1287IRHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
330.0
180.0
12.4
12.4
4.3
4.3
5.3
5.3
1.3
1.3
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS1287IRHFR
ADS1287IRHFT
VQFN
VQFN
RHF
RHF
24
24
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
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