ADS130B04-Q1 [TI]
汽车类 16 位 32kSPS 4 通道同步采样 Δ-Σ ADC;
| 型号： | ADS130B04-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 16 位 32kSPS 4 通道同步采样 Δ-Σ ADC |
| 文件： | 总62页 (文件大小：2088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS130B04-Q1
ZHCSO81 –NOVEMBER 2021
ADS130B04-Q1 汽车类、4 通道、32kSPS、同步采样、
16 位、Δ-Σ ADC
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100 标准：
– 温度等级1：–40°C 至+125°C，TA
• 提供功能安全
• 汽车电池管理系统(BMS)：
– 电流分流测量
– 电压测量使用外部电阻分压器来实现
– 温度测量使用热敏电阻或模拟输出温度传感器来
实现
– 可帮助进行功能安全系统设计的文档
• 4 同步采样差分输入ADC
• 可编程数据速率：高达32kSPS
• 可编程增益: 高达128
• 使用全局斩波模式来去除随温度变化和时间推移而
产生的温漂
• 用于直接传感器连接的高阻抗模拟输入
• 集成的负电荷泵允许输入信号测量低于地电平
• 通道间串扰：-120dB
• 低漂移内部基准：1.2V
• 精密内部振荡器
• 用于通信和寄存器映射的CRC
• 模拟和数字电源：2.7V 至3.6V
• 低功耗：3.3V AVDD 和DVDD 下为5mW
• 电动汽车充电站：
– 直流电子计量
• 能量存储系统(ESS)
3 说明
ADS130B04-Q1 是一款 four 通道、同步采样、16
位、Δ-Σ 模数转换器 (ADC)，具有宽动态范围、低功
耗和缓冲模拟输入，非常适合用于汽车电池管理系统
(BMS)。ADC 输入可以直接连接到分流电阻器以实现
双向电池电流测量，连接到电阻分压器网络以实现高电
压测量，或者连接到温度传感器（例如，热敏电阻或模
拟输出温度传感器）。
AVDD
DVDD
单独 ADC 通道可以根据传感器输入进行独立配置。低
噪声、可编程增益放大器 (PGA) 提供了从 1 到 128 的
增益，以放大低电平信号。该器件采用全局斩波模式来
去除随温度变化和时间推移而产生的温漂。
1.2-V
Reference
Oscillator
AIN0P
AIN0N
+
–
Clock
Selection
ꢀꢁ ADC
ꢀꢁ ADC
ꢀꢁ ADC
Digital Filter
Digital Filter
Digital Filter
Digital Filter
CLKIN
该器件集成了低漂移、1.2V 基准和高精度振荡器，减
小了印刷电路板 (PCB) 面积。数据输入、数据输出和
寄存器映射中可选的循环冗余校验 (CRC) 可以确保通
信完整性。
SYNC/RESET
AIN1P
AIN1N
+
–
CS
SCLK
Control &
Serial Interface
DIN
DOUT
DRDY
AIN2P
AIN2N
+
–
完整的模拟前端 (AFE) 采用 20 引脚 TSSOP 封装，额
定汽车级温度范围为–40°C 至+125°C。
AIN3P
AIN3N
+
–
ꢀꢁ ADC
器件信息(1)
封装尺寸（标称值）
器件型号
封装
AGND
DGND
ADS130B04-Q1
TSSOP (20)
6.50mm × 4.40mm
简化版方框图
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBASAD2
ADS130B04-Q1
ZHCSO81 –NOVEMBER 2021
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Table of Contents
8.5 Programming............................................................ 26
8.6 Register Map.............................................................36
9 Application and Implementation..................................48
9.1 Application Information............................................. 48
9.2 Typical Application.................................................... 51
10 Power Supply Recommendations..............................54
10.1 CAP Pin Capacitor Requirement............................ 54
10.2 Power-Supply Sequencing......................................54
10.3 Power-Supply Decoupling.......................................54
11 Layout...........................................................................54
11.1 Layout Guidelines................................................... 54
11.2 Layout Example...................................................... 55
12 Device and Documentation Support..........................56
12.1 Documentation Support.......................................... 56
12.2 Receiving Notification of Documentation Updates..56
12.3 支持资源..................................................................56
12.4 Trademarks.............................................................56
12.5 Electrostatic Discharge Caution..............................56
12.6 术语表..................................................................... 56
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Switching Characteristics............................................8
6.8 Timing Diagrams.........................................................9
6.9 Typical Characteristics..............................................10
7 Parameter Measurement Information..........................12
7.1 Noise Measurements................................................12
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................22
Information.................................................................... 56
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
November 2021
*
Initial Release
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5 Pin Configuration and Functions
AVDD
AGND
AIN0P
AIN0N
AIN1N
AIN1P
AIN2P
AIN2N
AIN3N
AIN3P
1
20
19
18
17
16
15
14
13
12
11
DVDD
DGND
CAP
2
3
4
CLKIN
DIN
5
6
DOUT
SCLK
DRDY
CS
7
8
9
10
SYNC/RESET
Not to scale
图5-1. PW Package, 20-Pin TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION(1)
NAME
AGND
NO.
2
Supply
Analog ground
AIN0N
AIN0P
AIN1N
AIN1P
AIN2N
AIN2P
AIN3N
AIN3P
AVDD
4
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Supply
Negative analog input 0
Positive analog input 0
3
5
Negative analog input 1
Positive analog input 1
6
8
Negative analog input 2
Positive analog input 2
7
9
Negative analog input 3
Positive analog input 3
10
1
Analog supply. Connect a 1-µF capacitor to AGND.
Digital low-dropout (LDO) regulator output.
Connect a 220-nF capacitor to DGND.
CAP
18
Analog output
CLKIN
CS
17
12
19
16
15
13
20
14
11
Digital input
Digital input
Supply
External clock input
Chip select; active low
Digital ground
DGND
DIN
Digital input
Digital output
Digital output
Supply
Serial data input
DOUT
DRDY
DVDD
SCLK
Serial data output
Data ready; active low
Digital I/O supply. Connect a 1-µF capacitor to DGND.
Serial data clock
Digital input
Digital input
SYNC/RESET
Conversion synchronization or system reset; active low
(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings
See (1)
MIN
–0.3
MAX UNIT
AVDD to AGND
3.9
AGND to DGND
Power-supply voltage
0.3
V
3.9
–0.3
DVDD to DGND
–0.3
CAP to DGND
2.2
–0.3
Analog input voltage
Digital input voltage
Input current
AINxP, AINxN
AVDD + 0.3
V
V
AGND –1.6
DGND –0.3
–10
CS, CLKIN, DIN, SCLK, SYNC/RESET
Continuous, all pins except power-supply pins
Junction, TJ
DVDD + 0.3
10
150
150
mA
Temperature
°C
Storage, Tstg
–60
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional –this may affect device reliability, functionality, performance, and shorten the device
lifetime.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM),
per AEC Q100-002(1)
±2000
HBM ESD classification level 2
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM),
per AEC Q100-011
CDM ESD classification level C4B
Corner pins
±750
±500
All other non-corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
POWER SUPPLY
AVDD to AGND
Analog power supply
2.7
–0.3
2.7
3.3
0
3.6
V
AGND to DGND
0.3
Digital power supply
DVDD to DGND
3.3
3.6
V
ANALOG INPUTS(1)
AGND –
Gain = 1, 2
AVDD –1.2
AVDD –2.4
VREF / Gain
0.1
VAINxP
VAINxN
,
Absolute input voltage
V
V
AGND –
Gain = 4, 8, 16, 32, 64, 128
VIN = VAINxP - VAINxN
0.3
–VREF
/
VIN
Differential input voltage
Gain
EXTERNAL CLOCK SOURCE(2)
High-resolution mode
Low-power mode
0.3
0.3
8.192
4.096
2.048
50%
8.2
fCLKIN
External clock frequency
4.15 MHz
2.08
Very-low-power mode
0.3
Duty cycle
40%
60%
DIGITAL INPUTS
Input voltage
TEMPERATURE
TA Operating ambient temperature
DGND
DVDD
V
125
°C
–40
(1) The subscript "x" signifies the channel. For example, the positive analog input of channel 0 is named AIN0P. See the Pin Configuration
and Functions section for the pin names.
(2) An external clock is not required when the internal oscillator is used.
6.4 Thermal Information
ADS130B04-Q1
THERMAL METRIC(1)
PW (TSSOP)
20 PINS
91.5
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
Rθ
Junction-to-case (top) thermal resistance
31.4
JC(top)
RθJB
ΨJT
Junction-to-board thermal resistance
43.0
2.0
°C/W
°C/W
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
42.5
ΨJB
Rθ
Junction-to-case (bottom) thermal resistance
N/A
°C/W
JC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 3.3 V, DVDD = 3.3 V, external clock, fCLKIN = 8.192 MHz, high-resolution mode, all channels, all
gains, data rate = 4 kSPS, all channels enabled, and global-chop mode disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ANALOG INPUTS
Global-chop disabled
25
MΩ
Global-chop enabled
300
Zin
Differential input impedance
All power modes, all data rates
See 表8-2
Global-chop disabled, VAINxP = VAINxN = 0 V
Global-chop enabled, VAINxP = VAINxN = 0 V
Global-chop disabled, VAINxP = VAINxN = 0 V
Global-chop enabled, VAINxP = VAINxN = 0 V
±1
±1
Absolute input current
Differential input current
nA
pA
±50
±30
ADC CHARACTERISTICS
Resolution
24
Bits
Gain settings
1, 2, 4, 8, 16, 32, 64, 128
High-resolution mode, fCLKIN = 8.192 MHz
Low-power mode, fCLKIN = 4.096 MHz
Very-low-power mode, fCLKIN = 2.048 MHz
250
125
32k
fDATA
Data rate
16k SPS
8k
62.5
ADC PERFORMANCE
ppm of
FSR
INL
Integral nonlinearity (best fit) Differential-ended input
10
Global-chop disabled
±200
±0.4
100
50
800
µV
4
–800
–4
Offset error (input referred)
Offset drift
Global-chop enabled(3)
Global-chop disabled, gain = 1 to 4
Global-chop disabled, gain = 8 to 128
Global-chop enabled
500
200 nV/°C
30
10
1000 hours at TA = 85°C, global-chop
disabled
0.8
0.25
±0.2%
8
Offset error long-term drift
Gain error
μV
1000 hours at TA = 85°C, global-chop
enabled
Including error of internal voltage reference,
TA = 25°C
0.7%
–0.7%
Including drift of internal voltage reference,
TA = –40°C to +85°C, gain = 1 to 4
30
Including drift of internal voltage reference,
TA = –40°C to +85°C, gain = 8 to 128
Gain drift
7
25 ppm/°C
40
Including drift of internal voltage reference,
TA = –40°C to +125°C
13
1000 hours at TA = 85°C, gain = 1,
including drift of internal voltage reference
Gain error long-term drift
250
ppm
At dc, global-chop disabled, gain = 1
At dc, global-chop enabled, gain = 1
96
128
Common-mode rejection
ratio
fCM = 50 Hz or 60 Hz, global-chop disabled,
gain = 1
CMRR
dB
89
fCM = 50 Hz or 60 Hz, global-chop enabled,
gain = 1
106
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6.5 Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all
specifications are at AVDD = 3.3 V, DVDD = 3.3 V, external clock, fCLKIN = 8.192 MHz, high-resolution mode, all channels, all
gains, data rate = 4 kSPS, all channels enabled, and global-chop mode disabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AVDD at dc, global-chop disabled, gain = 1
AVDD at dc, global-chop enabled, gain = 1
DVDD at dc, global-chop disabled, gain = 1
DVDD at dc, global-chop enabled, gain = 1
81
116
109
117
PSRR
Power-supply rejection ratio
dB
Input-referred noise
Crosstalk
See 表7-1
fIN = 50 Hz or 60 Hz
dB
V
–120
INTERNAL VOLTAGE REFERENCE
VREF Internal reference voltage
INTERNAL OSCILLATOR
1.2
fOSC
Frequency
8.192
±0.5%
0.2%
MHz
Accuracy
2.5%
–5%
Frequency long-term drift
1000 hours at TA = 85°C
DIGITAL INPUTS/OUTPUTS
VIL
Logic input level, low
Logic input level, high
Logic output level, low
Logic output level, high
Input current
DGND
0.2 DVDD
V
V
VIH
VOL
VOH
IIN
0.8 DVDD
DVDD
0.2 DVDD
V
IOL = –1 mA
IOH = 1 mA
0.8 DVDD
V
DGND < VDigital Input < DVDD
1
µA
–1
POWER SUPPLY
High-resolution mode, gain = 1, 2
High-resolution mode, gain = 4 to 128
Low-power mode, gain = 1, 2
Low-power mode, gain = 4 to 128
Very-low-power mode, gain = 1, 2
Very-low-power mode, gain = 4 to 128
Standby mode
5.6
6.4
2.8
3.2
1.4
1.6
0.4
140
0.4
0.2
0.1
1.2
19.8
22.4
9.9
5
6.8
8
3.4
mA
µA
IAVDD
Analog supply current
2
Internal oscillator
High-resolution mode
0.5
0.3
0.2
Low-power mode
mA
µA
IDVDD
Digital supply current(1)
Power dissipation
Very-low-power mode
Standby mode(2)
High-resolution mode, gain = 1, 2
High-resolution mode, gain = 4 to 128
Low-power mode, gain = 1, 2
Very-low-power mode, gain = 1, 2
24.1
28.1
12.2
7.3
PD
mW
(1) Currents measured with SPI idle.
(2) External clock stopped.
(3) Offset error may be limited by LSB size in certain OSR and gain configurations.
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MAX UNIT
6.6 Timing Requirements
over operating ambient temperature range, and DOUT load = 20 pF || 100 kΩ (unless otherwise noted)
MIN
2.7 V ≤DVDD ≤3.6 V
tw(CLL)
tw(CLH)
tc(SC)
Pulse duration, CLKIN low
Pulse duration, CLKIN high
SCLK period
49
49
40
20
20
15
16
10
5
ns
ns
ns
tw(SCL)
tw(SCH)
tw(CSH)
Pulse duration, SCLK low
Pulse duration, SCLK high
Pulse duration, CS high
ns
ns
ns
td(CSSC) Delay time, first SCLK rising edge after CS falling edge
td(SCCS) Delay time, CS rising edge after final SCLK falling edge
ns
ns
tsu(DI)
th(DI)
Setup time, DIN valid before SCLK falling edge
ns
Hold time, DIN valid after SCLK falling edge
8
ns
ns
tsu(SY)
tw(SYL)
tw(RSL)
Setup time, SYNC/RESET valid before CLKIN rising edge
Pulse duration, SYNC/RESET low for synchronization
Pulse duration, SYNC/RESET low to generate device reset
10
1
2047 tMCLK
tMCLK
2048
6.7 Switching Characteristics
over operating ambient temperature range, and DOUT load = 20 pF || 100 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
2.7 V ≤DVDD ≤3.6 V
Propagation delay time, CS falling edge to
DOUT driven
tp(CSDO)
tp(SCDO)
tp(CSDOZ)
50
20
75
ns
ns
ns
Progapation delay time, SCLK rising edge to
valid new DOUT
Propagation delay time, CS rising edge to
DOUT high impedance
tw(DRH)
tw(DRL)
Pulse duration, DRDY high
Pulse duration, DRDY low
SPI timeout
4
4
tMCLK
tMCLK
tMCLK
32768
Measured from supplies at 90%
to first DRDY rising edge
tPOR
Power-on-reset time
250
5
µs
µs
tREGACQ Register default acquisition time
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6.8 Timing Diagrams
tw(CLH)
tw(CLL)
CLKIN
DRDY
tw(DRL)
tw(DRH)
CS
SCLK
DIN
tw(SCL)
td(SCCS)
td(CSSC)
tc(SC)
tw(CSH)
tw(SCH)
tsu(DI)
th(DI)
tp(CSDO)
MSB
tp(SCDO)
tw(CSDOZ)
LSB
MSB - 1
LSB + 1
DOUT
SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.
图6-1. SPI Timing Diagram
CLKIN
tsu(SY)
tw(SYL)
tw(RSL)
SYNC/RESET
图6-2. SYNC/RESET Timing Requirements
90%
Supplies
tPOR
DRDY
图6-3. Power-On-Reset Timing
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6.9 Typical Characteristics
at TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted)
300
200
100
0
4
3
Channel 0
Channel 1
Channel 2
Channel 3
2
1
0
-1
-2
-3
-4
-100
-200
-300
Channel 0
Channel 1
Channel 2
Channel 3
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Gain = 8, global-chop mode disabled
图6-4. Offset Error vs Temperature
Gain = 8, global-chop mode enabled
图6-5. Offset Error vs Temperature
300
200
100
0
4
3
Gain = 1
Gain = 4
Gain = 8
Gain = 16
2
1
0
-1
-2
-3
-4
-100
-200
-300
Gain = 1
Gain = 4
Gain = 8
Gain = 16
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Global-chop mode disabled
图6-6. Offset Error vs Temperature
Global-chop mode enabled
图6-7. Offset Error vs Temperature
0
-50
0.5
0.4
0.3
0.2
0.1
0
Gain = 1
Gain = 4
Gain = 8
Gain = 16
-100
-150
-200
-250
-0.1
-0.2
-0.3
-0.4
-0.5
0
100 200 300 400 500 600 700 800 900 1000
Time (hours)
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Gain = 1, including error of internal voltage reference
Including error of internal voltage reference
图6-9. Gain Error Long-Term Drift
图6-8. Gain Error vs Temperature
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6.9 Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, DVDD = 3.3 V, fCLKIN = 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise noted)
3
2
10
HR Mode
LP Mode
VLP Mode
8
1
6
0
4
-1
-2
-3
2
-40
-20
0
20
40
60
80
100 120 140
0
Temperature (°C)
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Gain = 1, OSR = 1024, all four ADC channels enabled
图6-10. Oscillator Frequency Error vs Temperature
图6-11. Analog Supply Current vs Temperature
10
0.6
0.5
0.4
0.3
0.2
0.1
0
HR Mode
LP Mode
VLP Mode
HR Mode
LP Mode
VLP Mode
8
6
4
2
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Gain = 8, OSR = 1024, all four ADC channels enabled
OSR = 1024
图6-12. Analog Supply Current vs Temperature
图6-13. Digital Supply Current vs Temperature
6
IAVDD
IDVDD
5
4
3
2
1
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Standby mode
图6-14. Supply Current vs Temperature
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7 Parameter Measurement Information
7.1 Noise Measurements
Adjust the data rate and gain to optimize the ADS130B04-Q1 noise performance. When averaging is increased
by reducing the data rate, noise drops correspondingly. 表 7-1 summarizes the ADS130B04-Q1 noise
performance using the 1.2-V internal reference and a 3.3-V analog power supply. The data are representative of
typical noise performance at TA = 25°C when fMCLK = 8.192 MHz. The modulator clock frequency fMOD = fMCLK
/
2. The data shown are typical input-referred noise results with the analog inputs shorted together and taking an
average of multiple readings across all channels. A minimum 1 second of consecutive readings are used to
calculate the RMS noise for each reading. 表 7-2 shows the effective resolution calculated from the noise data.
方程式 1 calculates effective resolution. In each case, VREF corresponds to the internal 1.2-V reference. In
global-chop mode, noise is improved by a factor of √2.
The noise performance scales with the oversampling rate (OSR) and gain settings, but is independent from the
configured power mode. Thus, the device exhibits the same noise performance in different power modes when
selecting the same OSR and gain settings. However, the data rate at the OSR settings scales based on the main
clock frequency for the different power modes.
≈
∆
«
’
÷
2ì VREF
Gainì VRMS ◊
Effective Resolution = log2
(1)
表7-1. Noise (μVRMS) at TA = 25°C
GAIN
DATA RATE (kSPS),
OSR
fMCLK = 8.192 MHz
1
2
4
8
16
32
64
128
0.42
0.58
0.80
1.05
1.27
1.80
2.53
3.63
16384
8192
4096
2048
1024
512
0.25
0.5
1
36.62
36.62
36.62
36.62
36.62
36.62
36.62
36.62
18.31
18.31
18.31
18.31
18.31
18.31
18.31
18.31
9.16
9.16
9.16
9.16
9.16
9.16
9.16
13.64
4.58
4.58
4.58
4.58
4.58
4.58
4.58
4.58
2.29
2.29
2.29
2.29
2.29
2.29
2.56
3.73
1.14
1.14
1.14
1.14
1.27
1.80
2.53
3.63
0.57
0.57
0.80
1.05
1.27
1.80
2.53
3.63
2
4
8
256
16
32
128
表7-2. Effective Resolution at TA = 25°C
GAIN
DATA RATE (kSPS),
fMCLK = 8.192 MHz
OSR
1
2
4
16
16
16
16
16
16
16
15.4
8
16
16
32
16
64
128
15.4
15.0
14.5
14.1
13.8
13.3
12.9
12.3
16384
8192
4096
2048
1024
512
0.25
0.5
1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
15.5
15.1
14.8
14.3
13.9
13.3
2
16
16
4
16
15.8
15.3
14.9
14.3
8
16
256
16
32
15.8
15.3
128
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8 Detailed Description
8.1 Overview
The ADS130B04-Q1 is a low-power, four-channel, simultaneous-sampling, 16-bit, delta-sigma (ΔΣ) analog-to-
digital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and
power consumption are optimized for cost-sensitive applications requiring simultaneous sampling.
The ADS130B04-Q1 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can
operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as
0.3 V below AGND, which enables measurements of input signals varying around ground with a unipolar power
supply. The digital power supply (DVDD – DGND) can operate between 2.7 V and 3.6 V. The device features a
high input impedance programmable gain amplifier (PGA) with gains up to 128. The ADC receives its reference
voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as the
reference. Three power-scaling modes allow designers to trade power consumption for noise performance.
Each channel on the ADS130B04-Q1 contains a digital decimation filter that demodulates the output of the ΔΣ
modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. The
Functional Block Diagram provides a detailed diagram of the ADS130B04-Q1.
The device communicates via a serial peripheral interface (SPI)-compatible interface. Several SPI commands
and internal registers control the operation of the ADS130B04-Q1. Other devices can be added to the same SPI
bus by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions
between multiple ADS130B04-Q1 devices as well as to maintain synchronization with external events.
8.2 Functional Block Diagram
AVDD
DVDD
1.2-V
Reference
Oscillator
AIN0P
AIN0N
+
–
Clock
Selection
ꢀꢁ ADC
ꢀꢁ ADC
ꢀꢁ ADC
Digital Filter
Digital Filter
Digital Filter
Digital Filter
CLKIN
SYNC/RESET
AIN1P
AIN1N
+
–
CS
SCLK
Control &
Serial Interface
DIN
DOUT
DRDY
AIN2P
AIN2N
+
–
AIN3P
AIN3N
+
–
ꢀꢁ ADC
AGND
DGND
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8.3 Feature Description
8.3.1 Input ESD Protection Circuitry
Basic electrostatic discharge (ESD) circuitry protects the ADS130B04-Q1 inputs from ESD and overvoltage
events in conjunction with external circuits and assemblies. 图 8-1 shows a simplified representation of the ESD
circuit. The protection for input voltages exceeding AVDD can be modeled as a simple diode.
AVDD
AINnP
To analog inputs
AINnN
AVDD
图8-1. Input ESD Protection Circuitry
The ADS130B04-Q1 has an integrated negative charge pump that allows for input voltages below AGND with a
unipolar supply. Consequently, shunt diodes between the inputs and AGND cannot be used to clamp excessive
negative input voltages. Instead, the same diode that clamps overvoltage is used to clamp undervoltage at the
reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in
the Absolute Maximum Ratings table.
8.3.2 Input Multiplexer
Each channel of the ADS130B04-Q1 has a dedicated input multiplexer. The multiplexer controls which signals
are routed to the ADC channels. Configure the input multiplexer using the MUXn[1:0] bits in the CHn_CFG
register. The input multiplexer allows the following inputs to be connected to the ADC channel:
• The analog input pins corresponding to the given channel
• AGND, which is helpful for offset calibration
• Positive dc test signal
• Negative dc test signal
See the Internal Test Signals section for more information about the test signals. 图 8-2 shows a diagram of the
input multiplexer on the ADS130B04-Q1.
MUXn[1:0] = 00
SW
To Positive
PGA Input
AINnP
MUXn[1:0] = 01
MUXn[1:0] = 10
+
DC Test
Signal
œ
AGND
MUXn[1:0] = 11
MUXn[1:0] = 10
MUXn[1:0] = 01
SW
To Negative
PGA Input
AINnN
MUXn[1:0] = 00
图8-2. Input Multiplexer
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8.3.3 Programmable Gain Amplifier (PGA)
Each channel of the ADS130B04-Q1 features an integrated programmable gain amplifier (PGA) that provides
gains of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn
bits for each channel in the GAIN register.
Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. 方程式 2 describes
the relationship between FSR and gain. 方程式 2 uses the internal reference voltage, 1.2 V, as the scaling factor
without accounting for gain error caused by tolerance in the reference voltage.
FSR = ±1.2 V / Gain
(2)
表8-1 shows the corresponding full-scale ranges for each gain setting.
表8-1. Full-Scale Range
GAIN SETTING
FSR
1
2
±1.2 V
±600 mV
±300 mV
±150 mV
±75 mV
4
8
16
32
64
128
±37.5 mV
±18.75 mV
±9.375 mV
The input impedance of the ADS130B04-Q1 depends on three factors: the main clock frequency (fMCLK), the
selected OSR setting, and the global-chop mode setting. 表8-2 shows typical input impedance values for
fMCLK = 8.192 MHz. The input impedance scales indirectly proportional with the MCLK frequency, which means
that at fMCLK = 4.096 MHz, the impedance values in 表 8-2 increase by a factor of 2. Minimize the output
impedance of the circuit that drives the ADS130B04-Q1 inputs to obtain the best possible gain error, INL, and
distortion performance.
表8-2. Input Impedance
INPUT IMPEDANCE(1)
OSR SETTING
GLOBAL-CHOP DISABLED
GLOBAL-CHOP ENABLED
128
256
6 MΩ
13 MΩ
25 MΩ
25 MΩ
25 MΩ
25 MΩ
25 MΩ
25 MΩ
40 MΩ
75 MΩ
512
150 MΩ
1024
2048
4096
8192
16384
300 MΩ
600 MΩ
≥1 GΩ
≥1 GΩ
≥1 GΩ
(1) fMCLK = 8.192 MHz, default global-chop delay setting.
8.3.4 Voltage Reference
The ADS130B04-Q1 uses an internally generated, low-drift, band-gap voltage to supply the reference for the
ADC. The reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V
to 1.2 V at Gain = 1. The reference circuitry starts up very quickly to accommodate the fast start-up feature of
this device. The device waits until after the reference circuitry is fully settled before generating conversion data.
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8.3.5 Internal Test Signals
The ADS130B04-Q1 features an internal analog test signal that is useful for troubleshooting and diagnosis. A
positive or negative dc test signal can be applied to the channel inputs through the input multiplexer. The
multiplexer is controlled through the MUXn[1:0] bits in the CHn_CFG register. The test signals are created by
internally dividing the reference voltage. The same signal is shared by all channels.
The test signal is nominally 2 / 15 × VREF. The test signal automatically adjusts its voltage level with the gain
setting such that the ADC always measures a signal that is 2 / 15 × VDiff Max. For example, at a gain of 1, this
voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV.
8.3.6 Clocking
The ADS130B04-Q1 requires a main clock (MCLK) to operate. The main clock to the ADS130B04-Q1 is
provided in one of two ways, as shown in 图 8-3: an external clock on the CLKIN pin or the internal oscillator.
The CLK_SEL bit in the CLOCK register selects the according main clock source for the device.
CLK_SEL
PWR[1:0]
DS ADC
fOSC
8.192 MHz
÷ 1, 2 or 4
0
fMOD
Internal Oscillator
MUX
÷ 2
fMOD
fMCLK
1
CLKIN
图8-3. Main Clock Selection Diagram
8.3.6.1 External Clock Using CLKIN Pin
By default, the ADS130B04-Q1 is configured to operate with an external clock, such as at power-up. An
LVCMOS clock must be provided at the CLKIN pin continuously when the ADS130B04-Q1 is running in normal
operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a trade-off
between power consumption and noise performance.
The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-
resolution (HR), low-power (LP), or very-low-power (VLP). Changing the PWR[1:0] bits scales the internal bias
currents to achieve the expected power levels. Follow the guidance for the external clock frequency provided in
the Recommended Operating Conditions table corresponding to the intended power mode in order for the device
to perform according to the specification.
8.3.6.2 Internal Oscillator
The internal oscillator can be selected as the MCLK source by setting the CLK_SEL bit in the CLOCK register. At
device power-up, the internal oscillator is disabled by default.
As shown in 图 8-3 and 表 8-3, the internal oscillator frequency (fOSC) is scaled using a clock divider to provide
the appropriate nominal main clock frequency (fMCLK) for the different power modes. Correspondingly, the
modulator clock frequency (fMOD) scales as well because fMOD = fMCLK / 2.
表8-3. Scaling of the Internal Oscillator Frequency Based on the Selected Power Mode
POWER MODE
CLOCK DIVIDER SETTING
fMCLK
fMOD
HR
LP
1
2
4
8.192 MHz
4.096 MHz
2.048 MHz
4.096 MHz
2.048 MHz
1.024 MHz
VLP
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To switch between a running CLKIN and the internal oscillator as the MCLK source, put the device in standby
mode to avoid creating glitches when switching the clock source because there are no clock sequencers in the
device. Likewise, put the device in standby mode before changing power modes because a change in power
mode changes the MCLK frequency based on the clock divider setting.
When always using the internal oscillator as the MCLK source, tie the CLKIN pin to DGND. Tying the CLKIN pin
to DGND avoids the need to enter standby mode when switching from an external clock to the internal oscillator
at power-up or after a reset.
8.3.7 ΔΣModulator
The ADS130B04-Q1 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density
modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times
greater than the output data rate. The modulator frequency, fMOD, of the ADS130B04-Q1 is equal to half the
main clock frequency (that is, fMOD = fMCLK / 2).
The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a
means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency
domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital
decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization
noise, allowing the device to provide excellent dynamic range.
8.3.8 Digital Filter
The ΔΣmodulator bit-stream feeds into a digital filter. The digital filter is a linear phase, finite impulse response
(FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The
digital filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is
decimated and downsampled, to reduce the rate at which data come out of the modulator (fMOD) to the output
data rate (fDATA). The decimation factor, defined as per 方程式3, is called the oversampling ratio (OSR).
OSR = fMOD / fDATA
(3)
The OSR is configurable and is set by the OSR[2:0] bits in the CLOCK register. There are eight OSR settings in
the ADS130B04-Q1, allowing eight different data rate settings for any given main clock frequency. 表8-4 lists the
OSR settings and their corresponding output data rates for the nominal MCLK frequencies mentioned.
The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the
filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth
results in lower noise, whereas higher bandwidth results in higher noise. See 表 7-1 for the noise specifications
for various OSR settings.
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表8-4. OSR Settings and Data Rates for Nominal Main Clock Frequencies
POWER MODE
NOMINAL fMCLK
fMOD
OSR
OUTPUT DATA RATE
128
32 kSPS
16 kSPS
8 kSPS
4 kSPS
2 kSPS
1 kSPS
500 SPS
250 SPS
16 kSPS
8 kSPS
4 kSPS
2 kSPS
1 kSPS
500 SPS
250 SPS
125 SPS
8 kSPS
4 kSPS
2 kSPS
1 kSPS
500 SPS
250 SPS
125 SPS
62.5 SPS
256
512
1024
2048
4096
8192
16384
128
HR
8.192 MHz
4.096 MHz
256
512
1024
2048
4096
8192
16384
128
LP
4.096 MHz
2.048 MHz
256
512
1024
2048
4096
8192
16384
VLP
2.048 MHz
1.024 MHz
8.3.8.1 Digital Filter Implementation
图 8-4 shows the digital filter implementation of the ADS130B04-Q1. The modulator bitstream feeds two parallel
filter paths, a sinc3 filter, and a fast-settling filter path.
Power-up
or
Reset
OSR[2:0]
OSR 1024
Sinc1 Averager
(OSR > 1024)
Sinc3 Regular Filter
0
0
Global
Chop
Logic
Modulator
Bitstream
MUX
1
Gain scaling
MUX
1
OSR[2:0]
Fast-Settling Filter
OSR = 1024
PGA_GAINx[2:0]
图8-4. Digital Filter Implementation
8.3.8.1.1 Fast-Settling Filter
When the ADCs start converting for the first time after power-up or a device reset, the ADS130B04-Q1 selects
the fast-settling filter to allow for settled output data generation with minimal latency. The fast-settling filter has
the characteristic of a first-order sinc filter (sinc1). After two conversions, the device switches to and remains in
the sinc3 filter path until the next time the device is powered down or reset.
The fast-settling filter exhibits wider bandwidth and less stop-band attenuation than the sinc3 filter. Consequently,
the noise performance when using the fast-settling filter is not as high as with the sinc3 filter. The first two
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samples available from the ADS130B04-Q1 after a supply ramp or reset have the noise performance and
frequency response corresponding to the fast-settling filter as specified in the Electrical Characteristics table,
whereas subsequent samples have the noise performance and frequency response consistent with the sinc3
filter. See the Fast Start-Up Behavior section for more details regarding the fast start-up capabilities of the
ADS130B04-Q1.
8.3.8.1.2 SINC3 and SINC3 + SINC1 Filter
The ADS130B04-Q1 selects the sinc3 filter path two conversions after power-up or device reset. For OSR
settings of 128 to 1024, the sinc3 filter output directly feeds into the global-chop logic. For OSR settings of 2048
and higher, the sinc3 filter is followed by a sinc1 filter. As shown in 表 8-5, the sinc3 filter operates at a fixed OSR
of 1024 in this case while the sinc1 filter implements the additional OSRs of 2 to 16. That means, when an OSR
of 4096 (for example) is selected, the sinc3 filter operates at an OSR of 1024 and the sinc1 filter at an OSR of 4.
The filter has infinite attenuation at integer multiples of the data rate except for integer multiples of fMOD. Like all
digital filters, the digital filter response of the ADS130B04-Q1 repeats at integer multiples of the modulator
frequency, fMOD. The data rate and filter notch frequencies scale with fMOD
.
When possible, plan frequencies for unrelated periodic processes in the application for integer multiples of the
data rate such that any parasitic effect they have on data acquisition is effectively canceled by the notches of the
digital filter. Avoid frequencies near integer multiples of fMOD whenever possible because tones in these bands
can alias to the band of interest.
The sinc3 and sinc3 + sinc1 filters for a given channel require time to settle after a channel is enabled, the
channel multiplexer or gain setting is changed, or a resynchronization event occurs. 表8-5 lists the settling times
of the sinc3 and sinc3 + sinc1 filters for each OSR setting. The ADS130B04-Q1 does not gate unsettled data.
Therefore, the host must account for the filter settling time and disregard unsettled data if any are read. The data
at the next DRDY falling edge after the filter settling time listed in 表 8-5 has expired can be considered fully
settled.
表8-5. Digital Filter Settling Times
OSR (Overall)
128
OSR (SINC3)
OSR (SINC1)
SETTLING TIME (tMOD)
128
N/A
N/A
N/A
N/A
2
432
816
256
256
512
512
1584
3120
6192
10288
18480
34864
1024
1024
2048
1024
4096
1024
4
8192
1024
8
16384
1024
16
8.3.8.2 Digital Filter Characteristic
方程式 4 calculates the z-domain transfer function of a sinc3 filter that is used for OSRs ranging from 128 to
1024:
3
1 - Z -N
H z
( )
=
N 1 - Z -1
(4)
where:
• N is the OSR
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方程式5 calculates the transfer function of a sinc3 filter in terms of the continuous-time frequency parameter f:
3
Npf
sin
fMOD
H(f)½ =
pf
N ´ sin
fMOD
(5)
where:
• N is the OSR
图 8-5 and 图 8-6 show the digital filter response of the fast-settling filter and the sinc3 filter for OSRs ranging
from 128 to 1024. 图8-7 and 图8-8 compare the digital filter responses of the sinc3 filter at an OSR of 1024 and
sinc3 + sinc1 filter for an OSR of 4096.
0
-20
0
-1.5
-3
-40
-4.5
-6
-60
-80
-7.5
-9
-100
-120
-140
-10.5
-12
Fast-settling filter
Sinc3 filter
Fast-settling filter
Sinc3 filter
0
1
2
Frequency (fIN/fDATA
3
4
5
0
0.1
0.2 0.3
Frequency (fIN/fDATA)
0.4
0.5
)
图8-5. Fast-Settling and Sinc3 Digital Filter
图8-6. Fast-Settling and Sinc3 Digital Filter
Response
Response, Pass-Band Detail
0
0
-2
-4
-6
-8
Sinc3 filter (1024)
Sinc3 + Sinc1 filter
-20
-40
-60
-80
-100
-120
-140
-10
Sinc3 filter (1024)
Sinc3 + Sinc1 filter
-12
0
1
2
3
4
5
6
Frequency (f /fDATA
7
8
)
9
10 11 12
0
0.1
0.2 0.3
Frequency (f /fDATA)
0.4
0.5
IN
IN
图8-7. Digital Filter Response for OSR = 1024 and 图8-8. Digital Filter Response for OSR = 1024 and
OSR = 4096 OSR = 4096, Pass-Band Detail
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8.3.9 Register Map CRC
The ADS130B04-Q1 performs a CRC on its own register map as a means to check for unintended changes to
the registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When
enabled, the device constantly calculates the register map CRC across the registers ranging from address 02h
to 1Ch including the reserved registers. The CRC is calculated beginning with the MSB of register 02h and
ending with the LSB of register 1Ch using the polynomial selected in the CRC_TYPE bit in the MODE register.
Two types of CRC polynomials are available: CCITT CRC and ANSI CRC (CRC-16). See 表 8-7 for details on
the CRC polynomials. The CRC calculation is initialized with the seed value of FFFFh.
The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The calculation is done using
one register map bit per MCLK period and constantly checks the result against the previous calculation. The
REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes
resulting from register writes. The REG_MAP bit is cleared by reading the STATUS register, or when the
STATUS register is output as a response to the NULL command.
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8.4 Device Functional Modes
图 8-9 shows a state diagram depicting the major functional modes of the ADS130B04-Q1 and the transitions
between these modes.
POR, pin reset, or
RESET command
Reset
complete
Reset
STANDBY
Standby
Mode
Continuous
Conversion Mode
WAKEUP && GC_EN
STANDBY
GC_EN
WAKEUP
&& GC_EN
GC_EN
Global Chop
Mode
图8-9. State Diagram Depicting Device Functional Modes
8.4.1 Power-Up and Reset
The ADS130B04-Q1 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by a
RESET command. After a reset occurs, the configuration registers are reset to the default values and the device
begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high
transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any
SPI communication before this point.
8.4.1.1 Power-On Reset
Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process
requires tPOR to complete from when the supply voltages reach 90% of their nominal value to allow for the
internal circuitry to power up. The DRDY pin transitions from low to high immediately after tPOR indicating the SPI
interface is ready for communication.
8.4.1.2 SYNC/RESET Pin
The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low for longer
than tw(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at
least tREGACQ after SYNC/RESET is brought high or for the DRDY rising edge before communicating with the
device.
8.4.1.3 RESET Command
The ADS130B04-Q1 can be reset via the SPI RESET command. The device communicates in frames of a fixed
length. Six words are required to complete a frame on the ADS130B04-Q1. The RESET command is transmitted
in the first word of the data frame on DIN, but the command is not latched and executed by the device until the
entire frame is complete. Terminating the frame early causes the RESET command to be ignored. A device reset
occurs immediately after the RESET command is latched. The host must wait for at least tREGACQ or for the
DRDY rising edge before communicating with the device.
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8.4.2 Fast Start-Up Behavior
The ADS130B04-Q1 begins generating conversion data shortly after start-up as soon as a valid MCLK signal is
provided to the ΔΣ modulators. Fast start-up is accomplished via two mechanisms. First, the device internal
power-supply circuitry is designed specifically to enable fast start-up. Second, the digital decimation filter
dynamically switches from a fast-settling filter to a sinc3 filter when the sinc3 filter has settled.
After the supplies are ramped to 90% of their final values, the device requires tPOR for the internal circuitry to
settle. The end of tPOR is indicated by a transition of DRDY from low to high. The transition of DRDY from low to
high also indicates the SPI interface is ready to accept commands.
The ΔΣ modulators of the ADS130B04-Q1 require CLKIN to toggle after tPOR to begin working, or alternatively,
activate the internal oscillator by setting the CLK_SEL bit in the CLOCK register. The modulators begin sampling
the input signal after an initial wait time delay of (256 + 44) × tMOD when MCLK begins toggling. Therefore, when
using an external clock, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to
achieve the fastest possible start-up time.
The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the
fast-settling filter and the sinc3 filter paths. The fast-settling filter requires only one data rate period to provide
settled data. Meanwhile, the sinc3 filter requires three data rate periods to settle. The fast-settling filter generates
the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while
the sinc3 filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc3
filter path for the third and following samples. 图 8-10 shows the behavior of the fast-start-up feature when using
an external clock that is provided to the device right after the supplies have ramped. 表 8-6 shows the values for
the various start-up and settling times relevant to the device start-up.
90%
tSETTLE3
tDATA
Supplies
tPOR
tSETTLE1
tDATA
DRDY
Fast-settling
filter data
Fast-settling
filter data
Sinc3
filter data
Sinc3
filter data
...
...
...
...
CLKIN
图8-10. Fast Start-Up Behavior and Settling Times
表8-6. Fast Start-Up Settling Times for Default OSR = 1024
VALUE (DETAILS)
(tMOD
VALUE
(tMOD
VALUE AT
fMCLK = 8.192 MHz (ms)
PARAMETER
)
)
tDATA = 1/fDATA
tSETTLE1
1024
1024
1324
3372
0.250
0.323
0.823
256 + 44 + 1024
256 + 44 + 3 × 1024
tSETTLE3
The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the
sinc3 filter path, but allows the device to provide settled conversion data during the longer settling time of the
more accurate sinc3 digital filter. If the level of precision provided by the fast-settling filter is insufficient even for
the first samples immediately following start-up, ignore the first two instances of DRDY toggling from high to low
and begin collecting data on the third instance.
The start-up process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what
occurs after power up. However there is no tPOR in the case of a command or pin reset because the supplies are
already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × tMOD before providing
modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples.
Remember to enable the internal oscillator every time again after a reset in case the internal oscillator is to be
used, because the device defaults to using an external clock.
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8.4.3 Conversion Modes
There are two ADC conversion modes on the ADS130B04-Q1: continuous-conversion and global-chop mode.
Continuous-conversion mode is a mode where ADC conversions are generated constantly by the ADC at a rate
defined by fMOD / OSR. Global-chop mode differs from continuous-conversion mode because global-chop
periodically chops (or swaps) the inputs, which reduces system offset errors at the cost of settling time between
the points when the inputs are swapped. In either continuous-conversion or global-chop mode, there are three
power modes that provide flexible options to scale power consumption with bandwidth and dynamic range. The
Power Modes section discusses these power modes in further detail.
8.4.3.1 Continuous-Conversion Mode
Continuous-conversion mode is the mode in which ADC data are generated constantly at the rate of fDATA
=
fMOD / OSR. New data are indicated by a DRDY falling edge at this rate. Continuous-conversion mode is
intended for measuring AC signals because this mode allows for higher output data rates than global-chop
mode.
8.4.3.2 Global-Chop Mode
The ADS130B04-Q1 incorporates a global-chop mode option to reduce offset error and offset drift inherent to the
device resulting from mismatch in the internal circuitry to very low levels. When global-chop mode is enabled by
setting the GC_EN bit in the GLOBAL_CHOP_CFG register, the device uses the conversion results from two
consecutive internal conversions taken with opposite input polarity to cancel the device offset voltage.
Conversion n is taken with normal input polarity. The device then reverses the internal input polarity for
conversion n + 1. The average of two consecutive conversions (n and n + 1, n + 1 and n + 2, and so on) yields
the final offset compensated result.
图 8-11 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC internal
offset voltage is modeled as VOFS. Only this device inherent offset voltage is reduced by global-chop mode.
Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode.
GC_EN
Chop Switch
VOFS
-
+
AINnP
AINnN
A D
Digital
Filter
Global-Chop
Mode Control
PGA
ADC
Conversion Output
图8-11. Global-Chop Mode Implementation
The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled
(tDATA = OSR × tMOD). 图8-12 shows the conversion timing for an ADC channel using global-chop mode.
Global-chop delay
Modulator sampling
1st global-chop
conversion result
2nd global-chop
conversion result
Conversion
start
Data not
settled
Data not
settled
Swap inputs,
digital filter reset
Data not
settled
Data not
settled
ADC overhead
Sampling
n
Sampling
n
Sampling
n
Sampling
n + 1
Sampling
n + 1
Sampling
n + 1
Sampling
n + 2
Sampling
n + 2
Sampling
n + 2
Sampling
n + 3
Sampling
n + 3
Sampling
n + 3
tGC_FIRST
tGC_CONVERSION
tDATA
CONVERSION
图8-12. Conversion Timing With Global-Chop Mode Enabled
Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal
conversions to produce one settled global-chop conversion result.
The ADS130B04-Q1 provides a programmable delay (tGC_DLY) between the end of the previous conversion
period and the beginning of the subsequent conversion period after the input polarity is swapped. This delay
allows for external input circuitry to settle because the chopping switches interface directly with the analog
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inputs. The GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the
inputs. The global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 × tMOD
.
The effective conversion period in global-chop mode follows 方程式 6. A DRDY falling edge is generated each
time a new global-chop conversion becomes available to the host.
The conversion process of all ADC channels in global-chop mode is restarted in the following two conditions so
that all channels start sampling at the same time:
• Falling edge of SYNC/RESET pin
• Change of OSR setting
The conversion period of the first conversion after the ADC channels are reset is considerably longer than the
conversion period of all subsequent conversions mentioned in 方程式 6, because the device first must perform
two fully settled internal conversions with the input polarity swapped. The conversion period for the first
conversion in global-chop mode follows 方程式7.
tGC_CONVERSION = tGC_DLY + 3 × OSR × tMOD
(6)
(7)
tGC_FIRST_CONVERSION = tGC_DLY + 3 × OSR × tMOD + tGC_DLY + 3 × OSR x tMOD + 44 × tMOD
Using global-chop mode reduces the ADC noise shown in 表 7-1 at a given OSR by a factor of √2 because two
consecutive internal conversions are averaged to yield one global-chop conversion result. The dc test signal
cannot be measured in global-chop mode.
8.4.4 Power Modes
In both continuous-conversion and global-chop mode, there are three selectable power modes that allow scaling
of power with bandwidth and performance: high-resolution (HR) mode, low-power (LP) mode, and very-low-
power (VLP) mode. The mode is selected by the PWR[1:0] bits in the CLOCK register. See the Clocking section
for restrictions on the CLKIN frequency for each power mode in case an external clock source is used, or how
the main clock frequency is scaled with each power mode in case the internal oscillator is enabled.
8.4.5 Standby Mode
Standby mode is a low-power state in which all channels are disabled, and the reference, internal oscillator and
other non-essential circuitry are powered down. This mode differs from completely powering down the device
because the device retains its register settings. Enter standby mode by sending the STANDBY command. Stop
toggling CLKIN when the device is in standby mode and an external clock is used to minimize device power
consumption. See the Clocking section for recommendations on how to use standby mode when switching
between internal and external clock generation. Exit standby mode by sending the WAKEUP command.
8.4.6 Synchronization
Synchronization can be performed by the host to make sure the ADC conversions are synchronized to an
external event. For example, synchronization can realign the data capture to the expected timing of the host if a
glitch on the clock causes the host and device to become out of synchronization.
The SYNC/RESET pin is a multifunction digital input pin that allows the host to synchronize conversions to an
external event or to reset the device. See the SYNC/RESET Pin section for more details regarding how the
device is reset.
Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a MCLK
period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its
internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin. If the
negative edge on SYNC/RESET aligns with the internal data rate clock, the device is determined to be
synchronized and therefore no action is taken. If there is misalignment, the digital filters on the device are reset
to be synchronized with the SYNC/RESET pulse.
In global-chop mode conversions are always immediately restarted at the falling edge of the SYNC/RESET pin.
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8.5 Programming
8.5.1 Serial Interface
The ADS130B04-Q1 uses an SPI-compatible interface to configure the device and retrieve conversion data. The
device always acts as an SPI peripheral; SCLK and CS are inputs to the interface. The interface operates in SPI
mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, the SCLK idles low and data are launched or changed
only on SCLK rising edges; data are latched or read by the controller and peripheral on SCLK falling edges. The
interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device
includes the typical SPI signals: SCLK, CS, DIN (MOSI), and DOUT (MISO). In addition, there are two other
digital pins that provide additional functionality. The DRDY pin serves as a flag to the host to indicate new
conversion data are available. The SYNC/RESET pin is a dual-function pin that allows synchronization of
conversions to an external event and allows for a hardware device reset.
8.5.1.1 Chip Select (CS)
The CS pin is an active-low input signal that selects the device for communication. The device ignores any
communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a
communication frame to maintain proper communication. The interface is reset each time CS is taken high.
8.5.1.2 Serial Data Clock (SCLK)
The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin transition
on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK.
8.5.1.3 Serial Data Input (DIN)
The DIN pin is the serial data input pin for the device. Serial commands are shifted in through the DIN pin by the
device with each SCLK falling edge when the CS pin is low.
8.5.1.4 Serial Data Output (DOUT)
The DOUT pin is the serial data output pin for the device. The device shifts out command responses and ADC
conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a high-
impedance state when CS is high.
8.5.1.5 Data Ready (DRDY)
The DRDY pin is an active-low digital output that indicates when new conversion data are available for readout.
Connect the DRDY pin to a digital input on the host to trigger periodic data retrieval in conversion mode.
A high-to-low transition of the DRDY output indicates that new conversion data completed and are ready for
readout. The period between DRDY falling edges is the data-rate period. A low level of the DRDY pin indicates
that the latest conversion data have not yet been read. DRDY transitions high when the conversion data of the
four ADC channels, including those of disabled channels, are shifted out of the device. DRDY stays low if the
data read is incomplete, thus indicating that not all ADC data have been retrieved. In case conversion data are
not read before the next conversion cycle completes, DRDY transitions high tw(DRH) ahead of the next DRDY
falling edge. See the Collecting Data for the First Time or After a Pause in Data Collection section for more
information about the behavior of DRDY when data are not consistently read. The DRDY high pulse is blocked
when new conversions complete while conversion data are read. Therefore, avoid reading ADC data during the
time where new conversions complete in order to achieve consistent DRDY behavior.
The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the
bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY
behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not
asserted.
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8.5.1.6 SPI Communication Frames
SPI communication on the ADS130B04-Q1 is performed in frames. Each SPI communication frame consists of
several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the
WLENGTH[1:0] bits in the MODE register.
The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while
simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a
command. The first word on the output frame that the device transmits on DOUT always begins with the
response to the command that was written on the previous input frame. The number of words in a command
depends on the command provided. For most commands, there are six words in a frame. On DIN, the host
provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled,
and four additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous
frame command, four words of ADC data representing the four ADC channels, and a CRC word. 图 8-13 shows
a typical command frame structure.
DRDY
CS
SCLK
DIN
Command
CRC
Command
CRC
DOUT
Hi-Z
Response
Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data
CRC
Hi-Z
Response
Channel 0 Data
图8-13. Typical Communication Frame
There are some commands that require more or less than six words. In the case of a read register (RREG)
command where more than a single register is read, the response to the command contains the
acknowledgment of the command followed by the register contents requested, which may require a shorter or
longer frame depending on how many registers are read. See the RREG command section for more details on
the RREG command.
In the case of a write register (WREG) command where more than a single register is written, the frame extends
to accommodate the additional data. See the WREG command section for more details on the WREG
command.
See the Commands section for a list of all valid commands and their corresponding responses on the
ADS130B04-Q1.
Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for
more information about artificially shortening communication frames.
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8.5.1.7 SPI Communication Words
An SPI communication frame with the ADS130B04-Q1 is made of words. Words on DIN can contain commands,
register settings during a register write, or a CRC of the input data. Words on DOUT can contain command
responses, register settings during a register read, ADC conversion data, or CRC of the output data.
Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register.
The device defaults to a 24-bit word size. ADC conversion data, commands, responses, CRC, and registers
always contain 16 bits of actual data. All words are most significant bit (MSB) aligned, and therefore the least
significant bits (LSBs) are zero-padded to accommodate 24- or 32-bit word sizes.
图 8-14 through 图 8-16 show the locations of the individual bits in an SPI frame for the different word size
options using a WREG command frame for writing two registers as an example.
CS
DIN
WREG
Register Data 0
Channel 0 Data
Register Data 1
Channel 1 Data
CRC
15
15
0
0
15
15
0
0
15
15
0
0
15
15
0
0
DOUT
Response
Channel 2 Data
Channel 3 Data
CRC
15
0
15
0
图8-14. SPI Frame using 16-bit Word Size
CS
DIN
WREG
Register Data 0
Channel 0 Data
Register Data 1
Channel 1 Data
CRC
23
23
8
8
0
0
23
23
8
8
0
0
23
23
8
8
0
0
23
23
8
8
0
0
DOUT
Response
Channel 2 Data
Channel 3 Data
CRC
23
8
0
23
8
0
图8-15. SPI Frame using 24-bit, zero-padded Word Size
CS
DIN
WREG
Register Data 0
Channel 0 Data
Register Data 1
Channel 1 Data
CRC
31
31
16
0
0
31
31
16
16
0
0
31
31
16
16
0
0
31
31
16
0
DOUT
Response
Channel 2 Data
16
16
0
图8-16. SPI Frame (partial) using 32-bit, zero-padded Word Size
8.5.1.8 Short SPI Frames
The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and
no ADC data are being output by the device. Read out all expected output data words from each sample period
if the ADCs are enabled. Reading all of the data output with each frame provides predictable DRDY pin
behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the
First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from
when the ADCs were last enabled.
A short frame is not possible when using the RESET command. A full frame must be provided for a device reset
to take place when sending the RESET command.
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8.5.1.9 Communication Cyclic Redundancy Check (CRC)
The ADS130B04-Q1 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate
SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all
words in the SPI frame where the CRC is enabled, including zero-padded bits.
CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE
register. Input CRC is disabled by default. When the input CRC is enabled, the device checks the provided input
CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not match.
The device does not execute any commands, except for the WREG command, if the input CRC check fails. A
WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit in the
STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the frame
where the CRC error occurred is that of a NULL command, which means the STATUS register plus the
conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is
output.
The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the
data if the output CRC is not used.
There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting
determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE
bit in the MODE register. 表 8-7 lists the details of the two CRC types. The CRC calculation is initialized with the
seed value of FFFFh to detect errors in the event that DIN or DOUT are stuck low.
表8-7. CRC Types
CRC TYPE
CCITT CRC
ANSI CRC
POLYNOMIAL
x16 + x12 + x5 + 1
x16 + x15 + x2 + 1
BINARY POLYNOMIAL
0001 0000 0010 0001
1000 0000 0000 0101
8.5.1.10 SPI Timeout
The ADS130B04-Q1 features an SPI timeout as a means to recover SPI communication, especially in situations
where CS is permanently tied low. Enable the SPI timeout using the TIMEOUT bit in the MODE register. When
enabled, the entire SPI frame (first SCLK to last SCLK) must complete in 215 MCLK cycles, otherwise the SPI
logic will reset. When a timeout happens the device starts interpreting the data starting with the next SCLK as a
new SPI frame.
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8.5.2 ADC Conversion Data Format
The device provides conversion data for each channel at the data rate. All data are available immediately
following DRDY assertion. The conversion status of all channels is available as the DRDY[3:0] bits in the
STATUS register. The STATUS register content is automatically output as the response to the NULL command.
Conversion data are 16 bits. The LSBs are zero padded when operating with a 24-bit or 32-bit word size.
Data are given in binary two's complement format. Use 方程式8 to calculate the size of one code (LSB).
1 LSB = (2.4 / Gain) / 216 = +FSR / 215
(8)
A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFh and a
negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 8000h. The output clips at
these codes for signals that exceed full-scale.
表8-8 summarizes the ideal output codes for different input signals.
表8-8. Ideal Output Code versus Input Signal
INPUT SIGNAL
(VIN = VAINP –VAINN
IDEAL OUTPUT CODE
)
≥FSR (215 –1) / 215
FSR / 215
7FFFh
0001h
0000h
FFFFh
8000h
0
–FSR / 215
≤–FSR
图8-17 shows the mapping of the analog input signal to the output codes.
0x7FFF
0x7FFE
0x0001
0x0000
0xFFFF
0x8001
0x8000
¼
¼
-FS
-FS
0
FS
Input Voltage (VIN
)
215 - 1
215 - 1
FS
215
215
图8-17. Code Transition Diagram
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8.5.3 Commands
表 8-9 contains a list of all valid commands, a short description of their functionality, their binary command word,
and the expected response that appears in the following frame.
表8-9. Command Definitions
COMMAND
NULL
DESCRIPTION
COMMAND WORD
0000 0000 0000 0000
0000 0000 0001 0001
0000 0000 0010 0010
0000 0000 0011 0011
RESPONSE
No operation
STATUS register
RESET
Reset the device
1111 1111 0101 0100
0000 0000 0010 0010
0000 0000 0011 0011
STANDBY
WAKEUP
Place the device into standby mode
Wake the device from standby mode to conversion mode
Lock the interface such that only the NULL, UNLOCK, and
RREG commands are valid
LOCK
0000 0101 0101 0101
0000 0110 0101 0101
0000 0101 0101 0101
0000 0110 0101 0101
UNLOCK
Unlock the interface after the interface is locked
dddd dddd dddd dddd
or
RREG
WREG
Read nnn nnnn plus 1 registers beginning at address a aaaa a
Write nnn nnnn plus 1 registers beginning at address a aaaa a
101a aaaa annn nnnn
011a aaaa annn nnnn
111a aaaa annn nnnn (1)
010a aaaa ammm mmmm (2)
(1) When nnn nnnn is 0, the response is the requested register data dddd dddd dddd dddd. When nnn nnnn is greater than 0, the
response begins with 111a aaaa annn nnnn, followed by the register data.
(2) In this case, mmm mmmm represents the number of registers that are actually written minus one. This value may be less than nnn
nnnn in some cases.
8.5.3.1 NULL (0000 0000 0000 0000)
The NULL command is the no-operation command that results in no registers read or written, and the state of
the device remains unchanged. The intended use case for the NULL command is to read out ADC conversion
data. The command response for the NULL command is the contents of the STATUS register. Any invalid
command also gives the NULL response.
8.5.3.2 RESET (0000 0000 0001 0001)
The RESET command resets the ADC to its register defaults. The command is latched by the device at the end
of the frame. A reset occurs immediately after the command is latched. The host must wait for tREGACQ after
reset or for the DRDY rising edge before communicating with the device to make sure the registers have
assumed their default settings. The device sends an acknowledgment of FF54h when the ADC is properly
RESET. The device responds with 0011h if the command word is sent but the frame is not completed and
therefore the device is not reset. See the RESET Command section for more information regarding the operation
of the reset command. 图8-18 illustrates a properly sent RESET command frame.
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CS
SCLK
DIN
RESET
CRC
RESET command
latched here
DOUT
Hi-Z
Response
Don‘t Care
Don‘t Care
Don‘t Care
Don‘t Care
Don‘t Care
Hi-Z
图8-18. RESET Command Frame
8.5.3.3 STANDBY (0000 0000 0010 0010)
The STANDBY command places the device in a low-power standby mode. The command is latched by the
device at the end of the frame. The device enters standby mode immediately after the command is latched. See
the Standby Mode section for more information. This command has no effect when the device is already in
standby mode.
8.5.3.4 WAKEUP (0000 0000 0011 0011)
The WAKEUP command returns the device to conversion mode from standby mode. This command has no
effect if the device is already in conversion mode.
8.5.3.5 LOCK (0000 0101 0101 0101)
The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands
that can change the state of the device. When the interface is locked, the device only responds to the NULL,
RREG, and UNLOCK commands. The device continues to output conversion data even when locked.
8.5.3.6 UNLOCK (0000 0110 0110 0110)
The UNLOCK command unlocks the interface if previously locked by the LOCK command.
8.5.3.7 RREG (101a aaaa annn nnnn)
The RREG is used to read the device registers. The binary format of the command word is 101a aaaa annn
nnnn, where a aaaa a is the binary address of the register to begin reading and nnn nnnn is the unsigned binary
number of consecutive registers to read minus one. There are two cases for reading registers on the
ADS130B04-Q1. When reading a single register (nnn nnnn = 000 0000b), the device outputs the register
contents in the command response word of the following frame. If multiple registers are read using a single
command (nnn nnnn > 000 0000b), the device outputs the requested register data sequentially in order of
addresses.
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8.5.3.7.1 Reading a Single Register
Read a single register from the device by specifying nnn nnnn as zero in the RREG command word. As with all
SPI commands on the ADS130B04-Q1, the response occurs on the output in the frame following the command.
Instead of a unique acknowledgment word, the response word is the contents of the register whose address is
specified in the command word. 图8-19 shows an example of reading a single register.
DRDY
CS
SCLK
DIN
RREG
CRC
Command
CRC
Register
Data
DOUT
Hi-Z
Response
Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data
CRC
Hi-Z
Channel 0 Data
图8-19. Reading a Single Register
8.5.3.7.2 Reading Multiple Registers
Multiple registers are read from the device when nnn nnnn is specified as a number greater than zero in the
RREG command word. Like all SPI commands on the ADS130B04-Q1, the response occurs on the output in the
frame following the command. Instead of a single acknowledgment word, the response spans multiple words in
order to shift out all requested registers. Continue toggling SCLK to accommodate outputting the entire data
stream. ADC conversion data are not output in the frame following an RREG command to read multiple
registers. 图8-20 shows an example of reading multiple registers.
CS
SCLK
DIN
RREG
CRC
Command
CRC
RREG
ack
1
st register‘s
data
2
nd register‘s
data
N-1th register‘s
data
N
th register‘s
data
DOUT
Hi-Z
Response
Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data
CRC
Hi-Z
CRC
Hi-Z
图8-20. Reading Multiple Registers
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8.5.3.8 WREG (011a aaaa annn nnnn)
The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the
command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing
and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be
written immediately following the command word. Write the intended contents of each register into individual
words, MSB aligned.
If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as they
are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a
register. An input CRC error during a WREG command sets the CRC_ERR bit in the STATUS register.
The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map
address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them.
The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm
where mmm mmmm is the number of registers actually written minus one. This number can be checked by the
host against nnn nnnn to make sure the expected number of registers are written.
图 8-21 shows a typical WREG sequence. In this example, the number of registers to write is larger than the
number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC
word. Make sure all of the ADC data and output CRC are shifted out during each transaction where new data are
available. Therefore, the frame must be extended beyond the number of words required to send the register data
in some cases.
DRDY
CS
SCLK
1
st register‘s
data
2
nd register‘s
data
3
rd register‘s
data
4
th register‘s
data
5
th register‘s
data
6
th register‘s
data
N-1th register‘s
data
N
th register‘s
data
DIN
WREG
CRC
Command
CRC
DOUT
Hi-Z
Response
Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data
CRC
Don‘t Care
Hi-Z
Response
Channel 0 Data
图8-21. Writing Registers
8.5.4 Collecting Data for the First Time or After a Pause in Data Collection
Take special precaution when collecting data for the first time or when beginning to collect data again after a
pause. The internal mechanism that outputs data contains a first-in-first-out (FIFO) buffer that can store two
samples of data per channel at a time. The DRDY flag for each channel in the STATUS register remains set until
both samples for each channel are read from the device. This condition is not obvious under normal
circumstances when the host is reading each consecutive sample from the device. In that case, the samples are
cleared from the device each time new data are generated so the DRDY flag for each channel in the STATUS
register is cleared with each read. However, both slots of the FIFO are full if a sample is missed or if data are not
read for a period of time. Either strobe the SYNC/RESET pin to resynchronize conversions and clear the FIFOs,
or quickly read two data packets when data are read for the first time or after a gap in reading data. This process
maintains predictable DRDY pin behavior. See the Synchronization section for information about the
synchronization feature. These methods do not need to be employed if each channel data was read for each
output data period from when the ADC was enabled.
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图 8-22 shows an example of how to collect data after a period of the ADC running, but where no data are being
retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the ADS130B04-
Q1 output data with the host.
Time where data is
not being read
DRDY
SYNC / RESET
SYNC Pulse
CS
SCLK
Hi-Z
DOUT
Data
Data
CRC
Status
Data
CRC
图8-22. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin
Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by
reading two samples in quick succession. 图 8-23 depicts this method. There is a very narrow pulse on DRDY
immediately after the first set of data are shifted out of the device. This pulse may be too narrow for some
microcontrollers to detect. Therefore, do not rely upon this pulse, but instead immediately read out the second
data set after the first data set. DRDY transitions high after the second data set is read, which indicates that no
other new data are available for readout.
Time where data is
not being read
Narrow DRDY Pulse
DRDY
CS
SCLK
Hi-Z
DOUT
Data
Data
CRC
Status
Data
CRC
Status
Data
CRC
Data is read a
second time
图8-23. Collecting Data After a Pause in Data Collection by Reading Data Twice
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8.6 Register Map
表 8-10 lists the ADS130B04-Q1 registers. All register addresses not listed in 表 8-10 should be considered as
reserved locations with the default setting of 0000h and the register contents should not be modified from its
default setting.
表8-10. Register Map
BIT 15
BIT 7
BIT 14
BIT 13
BIT 12
BIT 11
BIT 3
BIT 10
BIT 2
BIT 9
BIT 1
BIT 8
BIT 0
RESET
VALUE
ADDRESS
REGISTER
BIT 6
BIT 5
BIT 4
DEVICE SETTINGS AND STATUS INDICATORS (Read-Only Registers)
RESERVED
CHANCNT[3:0]
00h
01h
ID
54xxh
0500h
RESERVED
LOCK
F_RESYNC
REG_MAP
CRC_ERR
CRC_TYPE
DRDY3
RESET
DRDY2
WLENGTH[1:0]
STATUS
RESERVED
DRDY1
DRDY0
GLOBAL SETTINGS ACROSS CHANNELS
RESERVED
RESERVED
RESERVED
RESERVED
PGAGAIN3[2:0]
PGAGAIN1[2:0]
REGCRC_EN
RX_CRC_EN
TIMEOUT
CRC_TYPE
RESET
WLENGTH[1:0]
02h
03h
04h
06h
MODE
CLOCK
GAIN
0510h
0F8Eh
0000h
0600h
RESERVED
DRDY_HiZ
CH1_EN
RESERVED
CH0_EN
CH3_EN
OSR[2:0]
CH2_EN
CLK_SEL
RESERVED
RESERVED
PWR[1:0]
RESERVED
RESERVED
PGAGAIN2[2:0]
PGAGAIN0[2:0]
RESERVED
GC_DLY[3:0]
GC_EN
GLOBAL_CHOP_
CFG
RESERVED
CHANNEL-SPECIFIC SETTINGS
RESERVED
09h
0Ch
0Eh
11h
13h
16h
18h
1Bh
CH0_CFG
RESERVED
CH1_CFG
RESERVED
CH2_CFG
RESERVED
CH3_CFG
RESERVED
0000h
8000h
0000h
8000h
0000h
8000h
0000h
8000h
RESERVED
MUX0[1:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MUX1[1:0]
MUX2[1:0]
MUX3[1:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
REGISTER MAP CRC REGISTER (Read-Only Register)
3Eh REGMAP_CRC 0000h
REG_CRC[15:8]
REG_CRC[7:0]
表8-11 shows the codes that are used for access types in this section.
表8-11. Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default value
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8.6.1 ID Register (Address = 00h) [reset = 54xxh]
The ID register is shown in 图8-24 and described in 表8-12.
Return to the Summary Table.
图8-24. ID Register
15
14
13
12
11
10
CHANCNT[3:0]
R-0100b
9
1
8
0
RESERVED
R-0101b
7
6
5
4
3
2
RESERVED
R-xxxxxxxxb
表8-12. ID Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15:12
11:8
7:0
R
0101b
Reserved
Always reads 0101b
CHANCNT[3:0]
RESERVED
R
R
0100b
Channel count
Always reads 0100b
xxxxxxxxb
Reserved
Values are subject to change without notice
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8.6.2 STATUS Register (Address = 01h) [reset = 0500h]
The STATUS register is shown in 图8-25 and described in 表8-13.
Return to the Summary Table.
图8-25. STATUS Register
15
14
13
12
11
10
9
8
LOCK
R-0b
F_RESYNC
R-0b
REG_MAP
R-0b
CRC_ERR
R-0b
CRC_TYPE
R-0b
RESET
R-1b
WLENGTH[1:0]
R-01b
7
6
5
4
3
2
1
0
RESERVED
R-0000b
DRDY3
R-0b
DRDY2
R-0b
DRDY1
R-0b
DRDY0
R-0b
表8-13. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
LOCK
R
0b
SPI interface lock indicator
0b = Unlocked
1b = Locked
14
F_RESYNC
R
0b
ADC resynchronization indicator
Bit is set each time the ADC resynchronizes.
0b = No resynchronization
1b = Resynchronization occurred
13
12
11
REG_MAP
CRC_ERR
CRC_TYPE
RESET
R
R
R
R
R
0b
0b
0b
1b
01b
Register map CRC fault indicator
0b = No change in the register map CRC
1b = register map CRC changed
SPI input CRC error indicator
0b = No CRC error
1b = Input CRC error occurred
CRC type indicator
0b = 16 bit CCITT
1b = 16 bit ANSI
10
9:8
Reset status indicator
0b = No reset occurred
1b = Reset occurred
WLENGTH[1:0]
Data word length indicator
00b = 16 bit
01b = 24 bits
10b = 32 bits: LSB zero padding
11b = Reserved
7:4
3
RESERVED
DRDY3
R
R
0000b
0b
Reserved
Always reads 0000b
Channel 3 ADC data available indicator
0b = No new data available
1b = New data available
2
1
0
DRDY2
DRDY1
DRDY0
R
R
R
0b
0b
0b
Channel 2 ADC data available indicator
0b = No new data available
1b = New data available
Channel 1 ADC data available indicator
0b = No new data available
1b = New data available
Channel 0 ADC data available indicator
0b = No new data available
1b = New data available
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8.6.3 MODE Register (Address = 02h) [reset = 0510h]
The MODE register is shown in 图8-26 and described in 表8-14.
Return to the Summary Table.
图8-26. MODE Register
15
14
13
12
11
10
9
1
8
RESERVED
R/W-00b
REG_CRC_EN RX_CRC_EN
CRC_TYPE
R/W-0b
RESET
R/W-1b
WLENGTH[1:0]
R/W-01b
R/W-0b
5
R/W-0b
7
6
4
3
2
0
RESERVED
R/W-000b
TIMEOUT
R/W-1b
RESERVED
R/W-00b
DRDY_HiZ
R/W-0b
RESERVED
R/W-0b
表8-14. MODE Register Field Descriptions
Bit
Field
Type
Reset
Description
15:14
RESERVED
R/W
00b
Reserved
Always write 00b
13
REG_CRC_EN
R/W
R/W
R/W
R/W
0b
0b
0b
1b
Register map CRC enable
0b = Disabled
1b = Enabled
12
11
10
RX_CRC_EN
CRC_TYPE
RESET
SPI input CRC enable
0b = Disabled
1b = Enabled
SPI and register map CRC type selection
0b = 16 bit CCITT
1b = 16 bit ANSI
Reset
Write 0b to clear this bit in the STATUS register
0b = No reset occurred
1b = Reset occurred
9:8
WLENGTH[1:0]
R/W
01b
Data word length selection
00b = 16 bits
01b = 24 bits
10b = 32 bits: LSB zero padding
11b = Reserved. Do not use.
7:5
4
RESERVED
TIMEOUT
R/W
R/W
000b
1b
Reserved
Always write 000b
SPI Timeout enable
0b = Disabled
1b = Enabled
3:2
1
RESERVED
DRDY_HiZ
R/W
R/W
00b
0b
Reserved
Always write 00b
DRDY pin state selection when conversion data is not available
0b = Logic high
1b = High impedance
0
RESERVED
R/W
0b
Reserved
Always write 0b
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8.6.4 CLOCK Register (Address = 03h) [reset = 0F8Eh]
The CLOCK register is shown in 图8-27 and described in 表8-15.
Return to the Summary Table.
图8-27. CLOCK Register
15
14
13
12
11
10
9
8
RESERVED
R-0000b
CH3_EN
R/W-1b
CH2_EN
R/W-1b
CH1_EN
R/W-1b
CH0_EN
R/W-1b
7
6
5
4
3
2
1
0
CLK_SEL
R/W-1b
RESERVED
R/W-00b
OSR[2:0]
R/W-011b
PWR[1:0]
R/W-10b
表8-15. CLOCK Register Field Descriptions
Bit
Field
Type
Reset
Description
15:12
RESERVED
R
0000b
Reserved
Always reads 0000b
11
10
9
CH3_EN
R/W
R/W
R/W
R/W
R/W
1b
1b
1b
1b
1b
Channel 3 ADC enable
0b = Disabled
1b = Enabled
CH2_EN
CH1_EN
CH0_EN
CLK_SEL
Channel 2 ADC enable
0b = Disabled
1b = Enabled
Channel 1 ADC enable
0b = Disabled
1b = Enabled
8
Channel 0 ADC enable
0b = Disabled
1b = Enabled
7
Clock source selection
0b = Internal oscillator
1b = External clock
6:5
4:2
RESERVED
OSR[2:0]
R/W
R/W
00b
Reserved
Always write 00b
011b
Modulator oversampling ratio selection
000b = 128
001b = 256
010b = 512
011b = 1024
100b = 2048
101b = 4096
110b = 8192
111b = 16384
1:0
PWR[1:0]
R/W
10b
Power mode selection
00b = Very-low power
01b = Low power
10b = High resolution
11b = High resolution
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8.6.5 GAIN Register (Address = 04h) [reset = 0000h]
The GAIN register is shown in 图8-28 and described in 表8-16.
Return to the Summary Table.
图8-28. GAIN Register
15
14
13
12
11
10
2
9
8
0
RESERVED
R/W-0b
PGAGAIN3[2:0]
R/W-000b
RESERVED
R/W-0b
PGAGAIN2[2:0]
R/W-000b
7
6
5
4
3
1
RESERVED
R/W-0b
PGAGAIN1[2:0]
R/W-000b
RESERVED
R/W-0b
PGAGAIN0[2:0]
R/W-000b
表8-16. GAIN Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R/W
0b
Reserved
Always write 0b
14:12
PGAGAIN3[2:0]
R/W
000b
PGA gain selection for channel 3
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
11
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
10:8
PGAGAIN2[2:0]
000b
PGA gain selection for channel 2
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
7
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
6:4
PGAGAIN1[2:0]
000b
PGA gain selection for channel 1
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
3
RESERVED
R/W
R/W
0b
Reserved
Always write 0b
2:0
PGAGAIN0[2:0]
000b
PGA gain selection for channel 0
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = 64
111b = 128
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8.6.6 GLOBAL_CHOP_CFG Register (Address = 06h) [reset = 0600h]
The GLOBAL_CHOP_CFG register is shown in 图8-29 and described in 表8-17.
Return to the Summary Table.
图8-29. GLOBAL_CHOP_CFG Register
15
14
13
12
11
10
9
1
8
RESERVED
R/W-000b
GC_DLY[3:0]
R/W-0011b
GC_EN
R/W-0b
7
6
5
4
3
2
0
RESERVED
R/W-00000000b
表8-17. GLOBAL_CHOP_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:13
RESERVED
R/W
000b
Reserved
Always write 000b
12:9
GC_DLY[3:0]
R/W
0011b
Global chop delay selection
Delay in modulator clock periods (tMOD) before measurement begins.
0000b = 2
0001b = 4
0010b = 8
0011b = 16
0100b = 32
0101b = 64
0110b = 128
0111b = 256
1000b = 512
1001b = 1024
1010b = 2048
1011b = 4096
1100b = 8192
1101b = 16484
1110b = 32768
1111b = 65536
8
GC_EN
R/W
R/W
0b
Global chop enable
0b = Disabled
1b = Enabled
7:0
RESERVED
00000000b Reserved
Always write 00000000b
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8.6.7 CH0_CFG Register (Address = 09h) [reset = 0000h]
The CH0_CFG register is shown in 图8-30 and described in 表8-18.
Return to the Summary Table.
图8-30. CH0_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-00000000b
7
6
5
4
3
2
RESERVED
R/W-00b
RESERVED
R-000b
RESERVED
R/W-0b
MUX0[1:0]
R/W-00b
表8-18. CH0_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:6
5:3
2
RESERVED
RESERVED
RESERVED
MUX0[1:0]
R/W
00000000
00b
Reserved
Always write 0000000000b
R
000b
Reserved
Always reads 000b
R/W
R/W
0b
Reserved
Always write 0b
1:0
00b
Channel 0 input selection
00b = AIN0P and AIN0N
01b = AIN0 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal
8.6.8 CH1_CFG Register (Address = 0Eh) [reset = 0000h]
The CH1_CFG register is shown in 图8-31 and described in 表8-19.
Return to the Summary Table.
图8-31. CH1_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-00000000b
7
6
5
4
3
2
RESERVED
R/W-00b
RESERVED
R-000b
RESERVED
R/W-0b
MUX1[1:0]
R/W-00b
表8-19. CH1_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:6
5:3
2
RESERVED
RESERVED
RESERVED
R/W
00000000
00b
Reserved
Always write 0000000000b
R
000b
Reserved
Always reads 000b
R/W
0b
Reserved
Always write 0b
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表8-19. CH1_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1:0
MUX1[1:0]
R/W
00b
Channel 1 input selection
00b = AIN1P and AIN1N
01b = AIN1 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal
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8.6.9 CH2_CFG Register (Address = 13h) [reset = 0000h]
The CH2_CFG register is shown in 图8-32 and described in 表8-20.
Return to the Summary Table.
图8-32. CH2_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-00000000b
7
6
5
4
3
2
RESERVED
R/W-00b
RESERVED
R-000b
RESERVED
R/W-0b
MUX2[1:0]
R/W-00b
表8-20. CH2_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:6
5:3
2
RESERVED
RESERVED
RESERVED
MUX2[1:0]
R/W
00000000
00b
Reserved
Always write 0000000000b
R
000b
Reserved
Always reads 000b
R/W
R/W
0b
Reserved
Always write 0b
1:0
00b
Channel 2 input selection
00b = AIN2P and AIN2N
01b = AIN2 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal
8.6.10 CH3_CFG Register (Address = 18h) [reset = 0000h]
The CH3_CFG register is shown in 图8-33 and described in 表8-21.
Return to the Summary Table.
图8-33. CH3_CFG Register
15
14
13
12
11
10
9
1
8
0
RESERVED
R/W-00000000b
7
6
5
4
3
2
RESERVED
R/W-00b
RESERVED
R-000b
RESERVED
R/W-0b
MUX3[1:0]
R/W-00b
表8-21. CH3_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
15:6
5:3
2
RESERVED
RESERVED
RESERVED
R/W
00000000
00b
Reserved
Always write 0000000000b
R
000b
Reserved
Always reads 000b
R/W
0b
Reserved
Always write 0b
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表8-21. CH3_CFG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1:0
MUX3[1:0]
R/W
00b
Channel 3 input selection
00b = AIN3P and AIN3N
01b = AIN3 disconnected, ADC inputs shorted
10b = Positive dc test signal
11b = Negative dc test signal
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8.6.11 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]
The REGMAP_CRC register is shown in 图8-34 and described in 表8-22.
Return to the Summary Table.
图8-34. REGMAP_CRC Register
15
14
13
12
11
10
2
9
1
8
0
REG_CRC[15:8]
R-00000000b
7
6
5
4
3
REG_CRC[7:0]
R-00000000b
表8-22. REGMAP_CRC Register Field Descriptions
Bit
15:0
Field
REG_CRC[15:0]
Type
Reset
Description
R
00000000
Register map CRC value
00000000b
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9 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Troubleshooting
表 9-1 lists common issues faced when designing with the ADS130B04-Q1 and the corresponding solutions.
This list is not comprehensive.
表9-1. Troubleshooting Common Issues Using the ADS130B04-Q1
ISSUE
POSSIBLE ROOT CAUSE
POSSIBLE SOLUTION
The SYNC/RESET pin functions as a
constant synchronization check, rather than a
convert start pin. See the Synchronization
section for more details on the intended
usage of the SYNC/RESET pin.
The F_RESYNC bit is set in the STATUS
word even though this bit was already
cleared.
The SYNC/RESET pin is being toggled
asynchronously to CLKIN.
The entire frame is not being sent to the
device. The device does not recognize data including those for channels that are
as being read. disabled.
Read all data words in the output data frame,
The same ADC conversion data are output
twice before changing.
9.1.2 Unused Inputs and Outputs
Leave any unused analog inputs floating or connect them to AGND.
Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused
digital inputs to the appropriate levels, DVDD or DGND.
Tie the CLKIN pin to DGND if the internal oscillator is used.
Leave the DRDY pin unconnected if unused or connect it to DVDD using a weak pullup resistor.
9.1.3 Antialias Filter
An analog low-pass filter is required in front of each of the ADC channel inputs to prevent out-of-band noise and
interferers from coupling into the band of interest. Because the ADS130B04-Q1 is a delta-sigma ADC, the
integrated digital filter provides substantial attenuation for frequencies outside of the band of interest up to the
frequencies adjacent to fMOD. Therefore, a single-order RC filter with a cutoff frequency set at least two decades
below the modulator frequency provides sufficient antialiasing protection in the vast majority of applications. 图
9-1 shows a typical RC filter that yields a cutoff frequency of fC = 39.8 kHz, which is generally a good starting
point for a design that uses fMOD = 4.096 MHz.
Applications that only need to measure dc signals can use much lower filter-cutoff frequencies by increasing the
resistor or capacitor values. Larger resistor values have the added benefit of limiting the current into the ADC
inputs in case of an overvoltage event.
200 ꢀ
To ADC
Inputs
10 nF
200 ꢀ
图9-1. Antialias Filter Example
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9.1.4 Minimum Interface Connections
图 9-2 depicts how the ADS130B04-Q1 can be configured for the minimum number of interface pins. This
configuration is useful when using data isolation to minimize the number of isolation channels required or when
the microcontroller (MCU) pins are limited.
The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a local
LVCMOS output oscillator when the device is configured for use with an external clock. Otherwise tie the CLKIN
pin to DGND if the internal oscillator is used. Tie the SYNC/RESET pin to DVDD in hardware if unused. The
DRDY pin can be left floating if unused. Connect either SYNC/RESET or DRDY to the MCU to make sure the
MCU stays synchronized to ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to
determine the sample period rather than forcing synchronization using the SYNC/RESET pin or monitoring the
DRDY pin. Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if
the SYNC/RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS130B04-Q1 is the only
device on the SPI bus. Make sure the data input and output CRC are enabled and are used to guard against
faulty register reads and writes if CS is tied low permanently.
Local
Oscillator
DVDD
OR
CLKIN
SYNC/RESET
DRDY
CLKOUT
GPIO
GPIO
CS
OR
Device
MCU
CS
SCLK
DIN
OR
SCLK
MOSI
MISO
DOUT
DGND
图9-2. Minimum Connections Required to Operate the ADS130B04-Q1
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9.1.5 Multiple Device Configuration
Multiple ADS130B04-Q1 devices can be arranged to capture all signals simultaneously. The same clock must be
provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the
sample periods internally between devices.
The devices can share the same SPI bus where only the CS pins for each device are unique. Each device can
be addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT
pin remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices as
long as no two devices sharing the bus simultaneously have their CS pins low. 图 9-3 shows multiple devices
configured for simultaneous data acquisition while sharing the same SPI bus.
Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously.
Device 1
SYNC/RESET
CLKIN
DRDY
SCLK
GPIO
CLKOUT
IRQ
SCLK
MOSI
MISO
CS1
MCU
DIN
DOUT
CS
CS2
CSn
Device 2
SYNC/RESET
CLKIN
DRDY
SCLK
DIN
DOUT
CS
Device n
SYNC/RESET
CLKIN
DRDY
SCLK
DIN
DOUT
CS
图9-3. Multiple Device Configuration
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9.2 Typical Application
This section describes a typical battery management system (BMS) application circuit using the ADS130B04-Q1.
The device serves the following primary functions in this BMS:
• Measure battery current with high resolution and accuracy using a low-side current shunt sensor
• Measure peak currents and detect overcurrent or short-circuit conditions
• Measure battery-pack voltage using a high-voltage resistor divider
• Measure shunt temperature using a linear positive temperature coefficient (PTC) thermistor, the TMP61-Q1
图9-4 shows the front-end for the battery management system circuit design.
PACK+
AVDD = 3.3 V
DVDD = 3.3 V
AVDD
DVDD
AVDD
R1
1 μF
1 μF
ADS130B04-Q1
RH1
RH2
RH3
AIN0P
AIN0N
Supply Voltage
Measurement
R2
AIN1P
AIN1N
CLKIN
DRDY
Battery Pack Voltage
Measurement
RL
CS
SCLK
AIN2P
AIN2N
Current Shunt
Measurement
DIN
DOUT
SYNC/RESET
AVDD
RBIAS
AIN3P
AIN3N
AGND
TMP61-Q1
(PTC)
Shunt Temperature
Measurement
CAP
220 nF
PACK-
DGND
RSHUNT
图9-4. ADS130B04-Q1 in a Typical Battery Management System Application
9.2.1 Design Requirements
表9-2. Design Requirements
DESIGN PARAMETER
Current Measurement
Current measurement range
Current shunt value
Update rate
VALUE
±5 kA
35 μΩ
1 ms
Battery-Pack Voltage Measurement
Voltage measurement range
Shunt Temperature Measurement
Temperature measurement range
Thermistor type
0 V to 800 V
–40°C to +125°C
TMP61-Q1 (10-kΩPTC)
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9.2.2 Detailed Design Procedure
The following sections provide guidelines for selecting the external components and the configuration of the
ADS130B04-Q1 for the various measurements in this application example.
9.2.2.1 Current Shunt Measurement
In a typical BMS, the current through the shunt resistor must be measured in both directions for charging and
discharging the battery pack. In an overcurrent or short-circuit condition, the current can be as high as IBAT_MAX
=
±5 kA in this example application. Therefore, the maximum voltage drop across the shunt is up to VSHUNT
=
RSHUNT × IBAT_MAX = 35 μΩ × ±4 kA = ±140 mV.
In order to measure this shunt voltage, channel 2 of the ADS130B04-Q1 is configured for gain = 8, which allows
differential voltage measurements of VIN2 = VAIN2P – VAIN2N = ±VREF / 8 = ±1.2 V / 8 = ±150 mV. The integrated
charge pump in the device allows voltage measurements 300 mV below AGND for gains of 4 and higher while
using a unipolar analog power supply. This bipolar voltage measurement capability is important because one
side of the shunt is connected to the same GND potential as the AGND pin of the ADS130B04-Q1, which means
that the absolute voltage that the device must measure is up to 140 mV below AGND.
To enable fast overcurrent detection within 1 ms while providing high accuracy and resolution, the ADS130B04-
Q1 is operated at 4 kSPS (OSR = 1024, high-resolution mode) using global-chop mode. Global-chop mode
enables measurements with minimal offset error over temperature and time. The conversion time using these
settings is 0.754 ms according to 方程式6.
Channel 2 is selected for the shunt measurement on purpose because this channel generally shows the best
offset error and offset drift with global-chop mode enabled across all four ADC channels. Of all the
measurements, the offset performance is the most critical for the shunt measurement in a typical BMS.
9.2.2.2 Battery Pack Voltage Measurement
The 800-V battery-pack voltage is divided down to the voltage range of the ADS130B04-Q1 using a high-voltage
resistor divider (RH1, RH2, RH3, and RL). Gain = 1 is used for channel 1 in this case to allow differential voltage
measurements of VIN1 = VAIN1P – VAIN1N = ±1.2 V. The battery-pack voltage measurement is a unipolar, single-
ended measurement. Thus, only the voltage range from 0 V to 1.2 V of the ADS130B04-Q1 is used. 方程式 9
calculates the resistor divider ratio.
VIN / VBAT_MAX = 1.2 V / 800 V = RL / (RL + RH1 + RH2 + RH3
)
(9)
The leakage current drawn by the resistor divider should be less than 100 μA in this example to avoid
unnecessarily draining the battery. The resistance of the divider must therefore be larger than RTOTAL
≥
VBAT_MAX / ILEAKAGE = 800 V / 100 μA = 8 MΩ. The resistor values are chosen as RH1 = RH2 = RH3 = 2.8 MΩ
and RL = 12.4 kΩ. Thus, the maximum voltage across RL is 1.18 V at VBAT_MAX = 800 V, leaving some
headroom to the maximum input voltage of 1.2 V of the ADS130B04-Q1.
The maximum resistance of a single resistor that can be used in an automotive circuit design is often limited to a
certain value. Also, the maximum voltage a single resistor can withstand is limited. These reasons are why the
high-side resistor of the divider is split into multiple resistors (RH1, RH2, and RH3). Another reason is that in case
a single resistor has a short-circuit fault, the remaining resistors still limit the current into the ADS130B04-Q1
analog input pin (AIN1P) to safe levels.
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9.2.2.3 Shunt Temperature Measurement
The shunt temperature in this example is measured using the TMP61-Q1, a linear 10-kΩ PTC, in a typical
voltage divider configuration using the analog supply (AVDD) as excitation. The PTC resistance is calculated
using 方程式11, which is derived from 方程式10:
VIN3 = VAIN3P –VAIN3N = AVDD x RPTC / (RBIAS + RPTC
)
(10)
(11)
RPTC = RBIAS x VIN3 / (AVDD –VIN3
)
The maximum input voltage on AIN3P is limited to 1.2 V when using gain = 1 for channel 3 with AIN3N
connected to AGND. Therefore the value of the precision resistor, RBIAS, must be chosen so that the voltage on
AIN3P stays below 1.2 V for the value range of the PTC across the temperature range that needs to be
measured. The TMP61-Q1 has its largest resistance at the most positive temperature, approximately 18 kΩ at
+125°C. Following 方程式 11, that means RBIAS ≥ 31.5 kΩ. A value of 36.5 kΩ is chosen for RBIAS to allow
variation in the AVDD supply voltage up to 3.6 V without exceeding the maximum AIN3P voltage of 1.2 V.
9.2.2.4 Auxiliary Analog Supply Voltage Measurement
The accuracy of the analog supply directly impacts the measurement accuracy of the PTC in this measurement
implementation. In order to increase the temperature measurement accuracy, channel 0 of ADS130B04-Q1 is
used to measure the analog supply. The measured AVDD value is then used in 方程式11 to calculate RPTC
.
A resistor divider (R1 and R2) is used to attenuate the 3.3-V analog supply voltage down to less than 1.2 V so
that channel 0 can measure the voltage using gain = 1 with AIN0N connected to AGND. The resistor divider
needs to be chosen so that the voltage on AIN0P stays below 1.2 V at the maximum AVDD voltage that can
occur in the application. Following 方程式 12, the resistors are chosen as R1 = 20 kΩ and R2 = 10 kΩ to allow
measurements up to AVDD = 3.6 V.
VIN0 = VAIN0P –VAIN0N = AVDD x R2 / (R1 + R2)
(12)
The analog supply voltage is calculated using 方程式13:
AVDD = VIN0 x (1 + R1 / R2)
(13)
9.2.3 Application Curves
图9-5 shows the measurement accuracy of the current measurement (ADC channel 2) over temperature for a 0-
A current through the shunt. 图 9-6 shows the gain error of the current measurement (ADC channel 2) over
temperature excluding the error of the shunt. The offset and gain error are calibrated at 25°C.
40
30
0.4
0.3
0.2
0.1
0
20
10
0
-10
-20
-30
-40
-0.1
-0.2
-0.3
-0.4
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
图9-5. Offset Current Error vs Temperature
图9-6. Gain Error vs Temperature
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10 Power Supply Recommendations
10.1 CAP Pin Capacitor Requirement
The ADS130B04-Q1 core digital supply voltage of 1.8 V is created by an internal LDO from DVDD. The CAP pin
outputs the LDO voltage created from the DVDD supply and requires an external bypass capacitor. Place a 220-
nF capacitor on the CAP pin to DGND.
10.2 Power-Supply Sequencing
The power supplies can be sequenced in any order but the analog and digital inputs must never exceed the
respective analog or digital power-supply voltage limits.
10.3 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. AVDD and DVDD must each be
decoupled with a 1-µF capacitor. Place the bypass capacitors as close to the power-supply pins of the device as
possible with low-impedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply
decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use
of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple
vias in parallel lowers the overall inductance and is beneficial for connections to ground planes.
11 Layout
11.1 Layout Guidelines
For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces
on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane
may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the
ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground
loops.
Route digital traces away from all analog inputs and associated components in order to minimize interference.
Use C0G capacitors on the analog inputs. Use ceramic capacitors (for example, X7R grade) for the power-
supply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as
close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance
connections on the ground-side connections of the bypass capacitors.
When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination
resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to
noise within the conversion data.
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11.2 Layout Example
图 11-1 shows an example layout of the ADS130B04-Q1 requiring a minimum of two PCB layers. In general,
analog signals and planes are partitioned to the left and digital signals and planes to the right.
+3.3 V
Via to corresponding
voltage plane or pour
+3.3 V
+3.3 V
Via to ground plane
or pour
Place CAP and power supply
decoupling capacitors close to pins
Channel 0
1: AVDD
2: AGND
3: AIN0P
4: AIN0N
5: AIN1N
6: AIN1P
7: AIN2P
8: AIN2N
9: AIN3N
10: AIN3P
20: DVDD
19: DGND
18: CAP
Channel 1
Channel 2
Channel 3
17: CLKIN
16: DIN
Device
15: DOUT
14: SCLK
13: DRDY
12: CS
11: SYNC/RST
Terminate long digital
input lines with resistors to
prevent reflection
Differential RC-filter
per channel
图11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TMP61-Q1 Automotive Grade, ±1% 10-kΩLinear Thermistor With 0402 and 0603
Package Options data sheet
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS130B04QPWRQ1
ACTIVE
TSSOP
PW
20
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
A130B04Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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