ADS131M04IPWT_技术文档

ADS131M04

_{SBAS890C – MARCH 2019 – REVISED}A_JAD_NS_U1_A3_R1_YM₂₀0₂4₁

SBAS890C – MARCH 2019 – REVISED JANUARY 2021

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ADS131M04 4-Channel, Simultaneously-Sampling, 24-Bit, Delta-Sigma ADC

1 Features

3 Description

•

4 simultaneously sampling differential inputs

Programmable data rate up to 32 kSPS

Programmable gain up to 128

The ADS131M04 is a four-channel, simultaneously-

sampling, 24-bit, delta-sigma (ΔΣ), analog-to-digital

converter (ADC) that offers wide dynamic range, low

power, and energy-measurement-specific features,

making the device an excellent fit for energy metering,

power metrology, and circuit breaker applications. The

ADC inputs can be directly interfaced to a resistor-

divider network or a power transformer to measure

voltage or to a current transformer, shunt, or a

Rogowski coil to measure current.

Noise performance:

– 102-dB dynamic range at gain = 1, 4 kSPS

– 80-dB dynamic range at gain = 64, 4 kSPS

Total harmonic distortion: –100 dB

High-impedance inputs for direct sensor

connection:

•

– 330-kΩ input impedance for gains of

1, 2, and 4

– 1-MΩ input impedance for gains of

8, 16, 32, and 64

Programmable channel-to-channel phase delay

calibration:

– 244-ns resolution, 8.192-MHz f_CLKIN

Current-detect mode allows for extremely low

power tamper detection

Fast startup: first data within 0.5 ms of supply

ramp

Integrated negative charge pump allows input

signals below ground

The individual ADC channels can be independently

configured depending on the sensor input. A low-

noise, programmable gain amplifier (PGA) provides

gains ranging from 1 to 128 to amplify low-level

signals. Additionally, this device integrates channel-to-

channel phase calibration and offset and gain

calibration registers to help remove signal-chain

errors.

•

A low-drift, 1.2-V reference is integrated into the

device reducing printed circuit board (PCB) area.

Cyclic redundancy check (CRC) options can be

individually enabled on the data input, data output,

and register map to ensure communication integrity.

•

Crosstalk between channels: –120 dB

Low-drift internal voltage reference

Cyclic redundancy check (CRC) on

communications and register map

2.7-V to 3.6-V analog and digital supplies

Low power consumption: 3.3 mW at 3-V AVDD

and DVDD

The complete analog front-end (AFE) is offered in a

20-pin TSSOP or leadless 20-pin WQFN package and

is specified over the industrial temperature range of

–40°C to +125°C.

•

Device Information ⁽¹⁾

PART NUMBER

PACKAGE

TSSOP (20)

WQFN (20)

BODY SIZE (NOM)

6.50 mm × 4.40 mm

3.00 mm × 3.00 mm

•

Packages: 20-pin TSSOP or 20-pin WQFN

Operating temperature range: –40°C to +125°C

ADS131M04

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

•

Electricity meters: commercial and residential

Circuit breakers

Protection relays

Power quality meters

Battery test equipment

AVDD

DVDD

1.2-V

Reference

AIN0P

AIN0N

+

Phase Shift

Digital Filters

&

Gain

& Offset

Calibration

DS ADC

œ

SYNC / RESET

AIN1P

AIN1N

+

Phase Shift

Digital Filters

&

Gain & Offset

Calibration

CS

Battery management systems

œ

SCLK

Control &

Serial Interface

DIN

DOUT

DRDY

AIN2P

AIN2N

+

Phase Shift

Digital Filters

&

Gain & Offset

Calibration

œ

Clock

Generation

AIN3P

AIN3N

+

CLKIN

Phase Shift

Digital Filters

&

Gain &

Calibration

Offset

œ

AGND

DGND

Simplified Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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ADS131M04

SBAS890C – MARCH 2019 – REVISED JANUARY 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics ............................................7

6.6 Timing Requirements .................................................9

6.7 Switching Characteristics ...........................................9

6.8 Timing Diagrams.......................................................10

6.9 Typical Characteristics.............................................. 11

7 Parameter Measurement Information..........................16

7.1 Noise Measurements................................................16

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................18

8.4 Device Functional Modes..........................................29

8.5 Programming............................................................ 35

8.6 ADS131M04 Registers............................................. 45

9 Application and Implementation..................................74

9.1 Application Information............................................. 74

9.2 Typical Application.................................................... 82

10 Power Supply Recommendations..............................89

10.1 CAP Pin Behavior................................................... 89

10.2 Power-Supply Sequencing......................................89

10.3 Power-Supply Decoupling.......................................89

11 Layout...........................................................................90

11.1 Layout Guidelines................................................... 90

11.2 Layout Example...................................................... 91

12 Device and Documentation Support..........................92

12.1 Documentation Support.......................................... 92

12.2 Receiving Notification of Documentation Updates..92

12.3 Support Resources................................................. 92

12.4 Trademarks.............................................................92

12.5 Electrostatic Discharge Caution..............................92

12.6 Glossary..................................................................92

13 Mechanical, Packaging, and Orderable

Information.................................................................... 92

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (June 2020) to Revision C (January 2021)

Page

•

Changed RUK (WQFN) package from preview to production data.................................................................... 1

Added thermal pad to RUK pin out and Pin Functions table ............................................................................. 4

Added Offset Error time drift and Gain Error time drift........................................................................................7

Changed SPI timing diagram and SYNC/RESET diagram...............................................................................10

Added typical characteristics plots and corrected test condition of Typical Characteristics section ................ 11

Added f_MODequation in the ΔΣ Modulator section............................................................................................20

Changed description in SINC³and SINC³+ SINC¹Filter section.................................................................... 22

Changed captions for figures in the Digital Filter Characteristic section...........................................................22

Changed CRC seed value and description in the Communication Cyclic Redundancy Check (CRC) section....

27

•

Added DRDY transitions in Power-Up and Reset section................................................................................ 29

Moved Fast Startup Behavior section to Device Functional Modes section, and changed values for wait time

delays in text and figures..................................................................................................................................30

Added global chop mode block diagram, global chop mode conversion timing diagram, and Equation 9 ......31

Added description for new conversions when reading data in the Data Ready (DRDY) section......................35

Changed Register Map table............................................................................................................................45

Added pullup resistor option for DRDY in the Unused Inputs and Outputs section..........................................74

Changed Number of phases row in Key System Specifications table..............................................................83

Changed layout example image....................................................................................................................... 91

•

Changes from Revision A (July 2019) to Revision B (June 2020)

Page

Changed 300-kΩ to 330-kΩ in input impedance Features bullet........................................................................1

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

•

2

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•

Changed Applications section............................................................................................................................ 1

Added Input bias current Gain = 1,2, or 4...........................................................................................................7

Added Input bias current Gain = 8,16,32, 64 or 128...........................................................................................7

Changed typcial value for Offset Error (global chop mode, channel 0) to ±35µV ..............................................7

Changed typical value for Offset Error (global chop mode, channels 1-3) to ±15µV.........................................7

Changed typical value for Offset drift (global chop mode) to 200nV/°C............................................................. 7

Changed title of Input Offset Current vs Gain figure.........................................................................................11

Changed Input Offset Voltage vs Gain figure....................................................................................................11

Changed DC AVDD PSRR vs Temperature figure............................................................................................11

Changed THD vs AVDD figure..........................................................................................................................11

Added Single Device Noise Histogram at 4 kSPS and Single Device Noise Histogram at 32 kSPS figures....11

Changed description of global-chop mode improvement and second paragraph to Noise Measurements

section.............................................................................................................................................................. 16

Changed second bullet in Input Multiplexer section......................................................................................... 18

Changed 317 kΩ to 330 kΩ in Equation 4 ....................................................................................................... 19

Deleted sentence regarding delay after first conversion result in Voltage Reference section .........................19

Changed description of modulator frequency in ΔΣ Modulator section............................................................ 20

Changed Digital Filter section...........................................................................................................................20

Changed Digital Filter Implementation title and section....................................................................................21

Added last two sentences to DC Block Filter section....................................................................................... 23

Added programmable delay to programmable delay (t_{GC_DLY}) in Global-Chop Mode mode............................31

Changed Standby Mode section.......................................................................................................................32

Changed t_SRLRSTto t_w(RSL)in first paragraph of Current-Detect Mode section.................................................32

Changed writes to transmits in second paragraph of SPI Communication Frames section.............................36

Added second paragraph to SPI Communication Frames section ..................................................................36

Changed DRDY_FMT bit setting from 0 to 0b in Collecting Data for the First Time or After a Pause in Data

Collection section..............................................................................................................................................38

Changed opcode to command word in RESET (0000 0000 0001 0001) section............................................. 40

Changed t_SRLRSTto t_w(RSL)in Synchronization section.....................................................................................44

Changed Register Map table............................................................................................................................45

Changed AVSS to AGND in Unused Inputs and Outputs section.................................................................... 74

Added reference to TIDA-010037 design guide in Typical Application section................................................ 82

Deleted discussion of voltage to current crosstalk from Voltage Measurement Front-End section..................83

Changed discussion of burden resistor in Current Measurement Front-End section....................................... 84

Deleted Test Methodology and Results sections .............................................................................................85

Added Application Curves section ...................................................................................................................85

Changed CAP Pin title to CAP Pin Behavior ................................................................................................... 89

Changed required capacitor for AVDD and DVDD from at least a 100-nF capacitor to a 1-µF capacitor in

Power-Supply Decoupling section....................................................................................................................89

•

Changes from Revision * (March 2019) to Revision A (July 2019)

Page

Changed document status from advance information to production data.......................................................... 1

Added Protection relays and Power quality meters to Applications section....................................................... 1

•

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5 Pin Configuration and Functions

AVDD

AGND

AIN0P

AIN0N

AIN1N

AIN1P

AIN2P

AIN2N

AIN3N

AIN3P

1

20

19

18

17

16

15

14

13

12

11

DVDD

2

DGND

CAP

3

AIN0P

AIN0N

AIN1N

AIN1P

AIN2P

1

2

3

4

5

15

14

13

12

11

CLKIN

DIN

4

CLKIN

DIN

5

Thermal

Pad

DOUT

SCLK

DRDY

6

DOUT

SCLK

DRDY

CS

7

8

9

10

SYNC/RESET

Not to scale

Figure 5-2. PW Package, 20-Pin TSSOP, Top View

Figure 5-1. RUK Package), 20-Pin WQFN, Top View

Table 5-1. Pin Functions

NO.

I/O

DESCRIPTION⁽¹⁾

NAME

AGND

WQFN

TSSOP

20

2

4

Supply

Analog ground

AIN0N

AIN0P

AIN1N

AIN1P

AIN2N

AIN2P

AIN3N

AIN3P

AVDD

Analog input Negative analog input 1

Analog input Positive analog input 1

Analog input Negative analog input 2

Analog input Positive analog input 2

Analog input Negative analog input 3

Analog input Positive analog input 3

Analog input Negative analog input 4

Analog input Positive analog input 4

1

3

5

4

6

8

5

7

9

8

10

1

19

Supply

Analog supply. Connect a 1-µF capacitor to AGND.

Digital low-dropout (LDO) regulator output.

Connect a 220-nF capacitor to DGND.

CAP

16

18

Analog output

CLKIN

CS

15

10

17

14

13

11

18

12

9

17

12

19

16

15

13

20

14

11

—

Digital input

Supply

Master clock input

Chip select; active low

Digital ground

DGND

DIN

Digital input

Serial data input

DOUT

Digital output Serial data output

DRDY

Digital output Data ready; active low

DVDD

Supply

Digital input

—

Digital I/O supply. Connect a 1-µF capacitor to DGND.

SCLK

Serial data clock

SYNC/RESET

Thermal pad

Conversion synchronization or system reset; active low

Thermal pad; connect to AGND

(1) See the Unused Inputs and Outputs section for details on how to connect unused pins.

4

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6 Specifications

6.1 Absolute Maximum Ratings

MIN

–0.3

MAX UNIT

AVDD to AGND

AGND to DGND

3.9

V

–0.3

0.3

Power-supply voltage

DVDD to DGND

–0.3

3.9

2.2

V

DVDD to DGND, CAP tied to DVDD

CAP to DGND

–0.3

V

–0.3

2.2

V

Analog input voltage

Digital input voltage

Input current

AINxP, AINxN

AGND – 1.6

DGND – 0.3

–10

AVDD + 0.3

DVDD + 0.3

10

V

CS, CLKIN, DIN, SCLK, SYNC/RESET

Continuous, all pins except power-supply pins

Junction, T_J

V

mA

150

Temperature

°C

Storage, T_stg

–60

150

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX UNIT

POWER SUPPLY

AVDD to AGND, normal operating modes

2.7

2.4

3.0

3.6

AVDD to AGND, standby and current-detect

Analog power supply

modes

V

AGND to DGND

DVDD to DGND

–0.3

2.7

0

0.3

3.6

3.0

Digital power supply

DVDD to DGND, DVDD shorted to CAP

(digital LDO bypassed)

1.65

1.8

2

ANALOG INPUTS⁽¹⁾

Gain = 1, 2, or 4

AGND – 1.3

–V_REF/ Gain

AVDD

AVDD – 1.8

V_REF/ Gain

V_AINxP

V_AINxN

,

Absolute input voltage

V

Gain = 8, 16, 32, 64 or 128

V_IN= V_AINxP- V_AINxN

V_IN

Differential input voltage

EXTERNAL CLOCK SOURCE

High-resolution mode

Low-power mode

0.3

8.192

4.096

2.048

50%

8.4

f_CLKIN

External clock frequency

4.15 MHz

2.08

Very-low-power mode

0.3

Duty cycle

40%

60%

DIGITAL INPUTS

Input voltage

TEMPERATURE RANGE

T_AOperating ambient temperature

DGND

–40

DVDD

V

125

°C

(1) The subscript "x" signifies the channel. For example, the positive analog input to channel 0 is named AIN0P. See the Pin

Configurations and Functions section for the pin names.

6.4 Thermal Information

ADS131M04

THERMAL METRIC⁽¹⁾

RUK (WQFN)

20 PINS

94.1

PW (TSSOP)

20 PINS

94.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

58.1

34.9

R_θJB

Ψ_JT

Ψ_JB

Junction-to-board thermal resistance

64.3

46.4

Junction-to-top characterization parameter

Junction-to-board characterization parameter

31.8

2.7

58.0

46.0

R_θJC(bot)Junction-to-case (bottom) thermal resistance

5.9

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C; all

specifications are at AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

ANALOG INPUTS

Gain = 1, 2, or 4, V_INP= V_INN= 0 V,

I_B= (I_BP+ I_BN) / 2

Input bias current

0.6

0.2

I_B

µA

Gain = 8, 16, 32, 64 or 128, V_INP= V_INN

0 V, I_B= (I_BP+ I_BN) / 2

=

Gain = 1, 2, or 4

300

kΩ

Z_in

Differential input impedance

Gain = 8, 16, 32, 64, or 128

±1 ⁽²⁾

µA/V

ADC CHARACTERISTICS

Resolution

24

Bits

Gain settings

1, 2, 4, 8, 16, 32, 64, 128

High-resolution mode, f_CLKIN= 8.192 MHz

Low-power mode, f_CLKIN= 4.096 MHz

Very-low-power mode, f_CLKIN= 2.048 MHz

250

125

32k

f_DATA

Data rate

16k SPS

8k

62.5

Measured from supplies at 90% to first

DRDY falling edge

Startup time

0.5

6

ms

ADC PERFORMANCE

ppm of

FSR

INL

Integral nonlinearity (best fit)

±175

±35

±15

300

200

4

Offset error (input referred) Global-chop mode, channel 0

µV

Global-chop mode, channels 1-3

Offset drift

nV/°C

μV

Global-chop mode

1000 hours at 85°C, TSSOP package

1000 hours at 85°C, QFN package

Offset error time drift

Gain error

4

±0.1%

1

Gain drift

ppm/°C

ppm

Including internal reference

1000 hours at 85°C, TSSOP package

1000 hours at 85°C, QFN package

At dc

8.5

400

120

100

94

Gain error time drift

Common-mode rejection

ratio

CMRR

PSRR

dB

f_CM= 50 Hz or 60 Hz

AVDD at dc

75

DVDD at dc

88

Power-supply rejection ratio

Input-referred noise

dB

AVDD supply, f_PS= 50 Hz or 60 Hz

DVDD supply, f_PS= 50 Hz or 60 Hz

78

85

5.35

55.0

µV_RMS

dB

During fast-startup

Gain = 1

99

102

80

Dynamic range

Crosstalk

Gain = 64

All other gain settings

f_IN= 50 Hz or 60 Hz

See Table 2

–120

dB

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6.5 Electrical Characteristics (continued)

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A= 25°C; all

specifications are at AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f_IN= 50 Hz or 60 Hz, gain = 1, V_IN= –0.5

dBFS,

100

normalized

SNR

Signal-to-noise ratio

dB

f_IN= 50 Hz or 60 Hz, gain = 64, V_IN= –0.5

dBFS,

79

normalized

f_IN= 50 Hz or 60 Hz (up to 50 harmonics),

V_IN= –0.5 dBFS

THD

Total harmonic distortion

–100

105

dB

Spurious-free dynamic

range

f_IN= 50 Hz or 60 Hz (up to 50 harmonics),

V_IN= –0.5 dBFS

SFDR

INTERNAL VOLTAGE REFERENCE

V_REF

Internal reference voltage

Accuracy

1.2

±0.1%

7.5

V

T_A= 25°C

Temperature drift

20 ppm/°C

DIGITAL INPUTS/OUTPUTS

V_IL

Logic input level, low

Logic input level, high

Logic output level, low

Logic output level, high

Input current

DGND

0.2 DVDD

V

V_IH

V_OL

V_OH

I_IN

0.8 DVDD

DVDD

I_OL= –1 mA

0.2 DVDD

V

I_OH= 1 mA

0.8 DVDD

–1

V

DGND < V_{Digital Input}< DVDD

1

µA

POWER SUPPLY

High-resolution mode

Low-power mode

Very-low-power mode

Current-detect mode

Standy mode

3.5

2.0

1.0

900

0.3

0.4

0.2

0.1

65

4.0

2.2

1.2

mA

µA

I_AVDD

I_DVDD

P_D

Analog supply current

High-resolution mode

Low-power mode

Very-low-power mode

Current-detect mode

Standy mode

0.5

0.3

0.2

mA

µA

Digital supply current⁽¹⁾

1

High-resolution mode

Low-power mode

Very-low-power mode

Current-detect mode

Standy mode

12

6.6

3.3

2.9

3.9

mW

µW

Power dissipation

(1) Currents measured with SPI idle.

(2) Specified in µA/V because current can flow either into or out of the input pin.

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6.6 Timing Requirements

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)

MIN

MAX UNIT

1.65 V ≤ DVDD ≤ 2.0 V

t_w(CLH)

t_w(CLL)

t_c(SC)

Pulse duration, CLKIN high

49

64

32

16

10

20

5

ns

Pulse duration, CLKIN low

SCLK period

ns

t_w(SCL)

t_w(SCH)

Pulse duration, SCLK low

Pulse duration, SCLK high

ns

t_d(CSSC)Delay time, first SCLK rising edge after CS falling edge

t_d(SCCS)Delay time, CS rising edge after final SCLK falling edge

ns

t_w(CSH)

t_su(DI)

t_h(DI)

Pulse duration, CS high

ns

Setup time, DIN valid before SCLK falling egde

Hold time, DIN valid after SCLK falling edge

Pulse duration, SYNC/RESET low to generate device reset

Pulse duration, SYNC/RESET low for synchronization

Setup time, SYNC/RESET valid before CLKIN rising edge

ns

8

ns

t_CLKIN

t_w(RSL)

t_w(SYL)

t_su(SY)

2048

1

2047 t_CLKIN

ns

10

2.7 V ≤ DVDD ≤ 3.6 V

t_w(CLL)

t_w(CLH)

t_c(SC)

Pulse duration, CLKIN low

49

40

20

16

10

15

5

ns

Pulse duration, CLKIN high

SCLK period

ns

t_w(SCL)

t_w(SCH)

Pulse duration, SCLK low

Pulse duration, SCLK high

ns

t_d(CSSC)Delay time, first SCLK rising edge after CS falling edge

t_d(SCCS)Delay time, CS rising edge after final SCLK falling edge

ns

t_w(CSH)

t_su(DI)

t_h(DI)

Pulse duration, CS high

ns

Setup time, DIN valid before SCLK falling egde

Hold time, DIN valid after SCLK falling edge

Pulse duration, SYNC/RESET low to generate device reset

Pulse duration, SYNC/RESET low for synchronization

Setup time, SYNC/RESET valid before CLKIN rising edge

ns

8

ns

t_CLKIN

t_w(RSL)

t_w(SYL)

t_su(SY)

2048

1

2047 t_CLKIN

ns

10

6.7 Switching Characteristics

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

1.65 V ≤ DVDD ≤ 2.0 V

Propagation delay time, CS falling edge to

DOUT driven

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

50

32

75

ns

Progapation delay time, SCLK rising edge to

valid new DOUT

Propagation delay time, CS rising edge to DOUT

high impedance

t_w(DRH)

t_w(DRL)

Pulse duration, DRDY high

Pulse duration, DRDY low

SPI timeout

4

t_CLKIN

32768

Measured from supplies at

90%

t_POR

Power-on-reset time

250

5

µs

t_REGACQRegister default acquisition time

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6.7 Switching Characteristics (continued)

over operating ambient temperature range, DOUT load: 20 pF || 100 kΩ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

2.7 V ≤ DVDD ≤ 3.6 V

Propagation delay time, CS falling edge to

DOUT driven

t_p(CSDO)

t_p(SCDO)

t_p(CSDOZ)

50

20

75

ns

Progapation delay time, SCLK rising edge to

valid new DOUT

Propagation delay time, CS rising edge to DOUT

high impedance

t_w(DRH)

t_w(DRL)

Pulse duration, DRDY high

Pulse duration, DRDY low

SPI timeout

4

t_CLKIN

32768

Measured from supplies at

90%

t_POR

Power-on-reset time

250

5

µs

t_REGACQRegister default acquisition time

6.8 Timing Diagrams

t_w(CLH)

t_w(CLL)

CLKIN

DRDY

t_w(DRL)

t_w(DRH)

CS

SCLK

DIN

t_w(SCL)

t_d(SCCS)

t_d(CSSC)

t_c(SC)

t_w(CSH)

t_w(SCH)

t_su(DI)

t_h(DI)

t_p(CSDO)

MSB

t_p(SCDO)

t_w(CSDOZ)

LSB

MSB - 1

LSB + 1

DOUT

SPI settings are CPOL = 0 and CPHA = 1. CS transitions must take place when SCLK is low.

Figure 6-1. SPI Timing Diagram

CLKIN

t_su(SY)

t_w(SYL)

t_w(RSL)

SYNC/RESET

Figure 6-2. SYNC/ RESET Timing Requirements

90%

Supplies

t_POR

DRDY

Figure 6-3. Power-On-Reset Timing

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6.9 Typical Characteristics

at T_A= 25°C, AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global chop mode

disabled (unless otherwise noted)

350

300

250

200

150

100

50

100

50

HR Mode

LP Mode

VLP Mode

LP Mode

HR Mode

30

20

10

5

3

2

1

0.5

0.3

0.2

0

8

16

32

Gain

64

128

1

2

4

8

16

32

64

128

Gain

Gains of 8, 16, 32, 64, and 128 only

Figure 6-4. Input Offset Current vs Gain

Figure 6-5. Input Impedance vs Gain

4

2

120

100

80

60

40

20

0

94

0

81

-2

-4

-6

-8

24

Ta = -40

Ta = 25

Ta = 125

-10

-12

1

-1.25 -1 -0.75 -0.5 -0.25

0

INL (LSB)

0.25 0.5 0.75

1

1.25

Time (ms)

ADS1

Figure 6-7. INL vs V_IN

Figure 6-6. Startup Time Histogram

350

200

180

160

140

120

100

300

250

200

150

100

50

0

-40

-20

0

20

40

60

80

100 120 140

1

2

4

8

16

32

64

128

Temperature (èC)

Gain

ADS1

30 units, channel 1

Figure 6-8. Input Offset Voltage vs Gain

Figure 6-9. Input Offset Voltage vs Temperature

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6.9 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global chop mode

disabled (unless otherwise noted)

0

-100

-200

-300

-400

-500

-600

0

-25

18 units, all channels

-50

-75

-100

-125

-150

0

200

400 600

Time (Hours)

800

1000

0

200

400 600

Time (Hours)

800

1000

Figure 6-10. Gain Error vs Time (TSSOP Package)

Figure 6-11. Gain Error vs Time (WQFN Package)

300 100

0

100

Humidity (%)

-300

80

60

40

20

0

150

0

80

60

40

20

0

-600

18 units, all channels

-900

-150

-300

-450

18 units, all channels

-1200

-1500

0

20

40

Time (Hours)

60

80

0

20

40

Time (Hours)

60

80

Figure 6-12. Gain Error vs Humidity (TSSOP Package)

Figure 6-13. Gain Error vs Humidity (WQFN Package)

0.2

115

Gain

1

Gain

1

0.15

110

2

4

8

16

4

8

16

32

0.1

105

0.05

32

64

128

64

128

0

100

-0.05

-0.1

95

90

-0.15

-0.2

85

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

Temperature

80 100 120 140 160

Temperature (èC)

ADS1

Includes internal reference error

Figure 6-14. Gain Error vs Temperature

Figure 6-15. DC CMRR vs Temperature

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6.9 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global chop mode

disabled (unless otherwise noted)

110

108

106

104

102

100

98

110

109

108

107

106

105

104

103

102

101

100

Gain

1

2

4

8

16

32

64

128

96

94

92

90

2.7 2.8 2.9

3

3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8

AVDD Voltage (V)

10

20 30 50 70100 200

500 1000 2000 500010000

Frequency (Hz)

ADS1

Figure 6-16. DC CMRR vs AVDD

Figure 6-17. AVDD CMRR vs Frequency

110

120

110

100

90

109

108

107

106

105

104

103

102

101

100

80

70

60

-40

2.7

2.8

2.9

3

3.1

3.2

AVDD Voltage (V)

3.3

3.4

3.5

3.6

-20

0

20

40

60

80

100 120 140

Temperature (èC)

ADS1

Figure 6-18. AC CMRR vs AVDD

Figure 6-19. DC AVDD PSRR vs Temperature

15000

14000

13000

12000

11000

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

110

105

100

95

90

85

80

-24

-18

-12

-6

0

6

12

18

24

-40 -20

0

20

40

60

80

100 120 140

Input Referred Voltage (mV)

Temperature (èC)

ADS1

Gain = 1, inputs shorted

Figure 6-21. Single Device Noise Histogram at 4 kSPS

Figure 6-20. DC DVDD PSRR vs Temperature

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6.9 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global chop mode

disabled (unless otherwise noted)

33000

30000

27000

24000

21000

18000

15000

12000

9000

6.2

6

Channel 0

Channel 1

Channel 2

Channel 3

5.8

5.6

5.4

5.2

5

6000

3000

0

-100 -80 -60 -40 -20

4.8

-40

0

20

40

60

80 100

-20

0

20

40

60

80

100 120 140

Input Referred Voltage (mV)

Temperature (èC)

Gain = 1, inputs shorted

Figure 6-22. Single Device Noise Histogram at 32 kSPS

Figure 6-23. Noise vs Temperature

110

100

90

HR Mode

LP Mode

VLP Mode

Channel

0

1

2

3

100

90

80

70

60

80

70

60

1

2

4

8

16

32

64

128

1

2

4

8

16

32

64

128

Gain

ADS1

Figure 6-24. Dynamic Range at 4 kSPS vs Gain

Figure 6-25. Dynamic Range vs Gain

120

-100

-105

-110

-115

-120

-125

-130

-135

-140

110

100

90

80

70

60

50

40

30

20

10

0

OSR

128

256

512

1024

2048

4096

8192

16384

1

2

4

8

16

32

64

128

0

1

2

3

Gain

Channel

ADS1

Figure 6-27. Crosstalk vs Channel

Figure 6-26. Dynamic Range vs Gain

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6.9 Typical Characteristics (continued)

at T_A= 25°C, AVDD = 3 V, DVDD = 3 V, f_CLKIN= 8.192 MHz, data rate = 4 kSPS, and gain = 1 with global chop mode

disabled (unless otherwise noted)

-100

-102.5

-105

-80

-85

Channel

OSR

16384

0

1

2

3

8192

4096

2048

1024

512

-90

-95

265

128

-107.5

-110

-100

-105

-110

-115

-112.5

-115

2.7

2.8

2.9

3

3.1

3.2

AVDD Voltage (V)

3.3

3.4

3.5

3.6

1

2

4

8

16

32

64

128

Gain

ADS1

Figure 6-29. THD vs AVDD

Figure 6-28. THD vs Gain

5

3.5

3

HR Mode

LP Mode

VLP Mode

4.5

4

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

HR Mode

LP Mode

VLP Mode

0.5

0

0.5

0

1

2

4

8

16

32

64

128

1

2

3

4

Frequency (MHz)

5

6

7

8 8.5

Gain

ADS1

Figure 6-30. AVDD Current vs Gain

Figure 6-31. AVDD Current vs CLKIN Frequency

400

350

300

250

200

150

100

50

HR Mode

LP Mode

VLP Mode

0

1

2

3

4

5

Frequency (MHz)

6

7

8 8.5

ADS1

Figure 6-32. DVDD Current vs CLKIN Frequency

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7 Parameter Measurement Information

7.1 Noise Measurements

Adjust the data rate and gain to optimize the ADS131M04 noise performance. When averaging is increased by

reducing the data rate, noise drops correspondingly. Table 7-1 summarizes the ADS131M04 noise performance

using the 1.2-V internal reference and a 3.0-V analog power supply. The data are representative of typical noise

performance at T_A= 25°C when f_CLKIN= 8.192 MHz. The modulator clock frequency f_MOD= f_CLKIN/ 2. The data

shown are typical input-referred noise results with the analog inputs shorted together and taking an average of

multiple readings across all channels. A minimum 1 second of consecutive readings are used to calculate the

RMS noise for each reading. Table 7-2 shows the dynamic range and effective resolution calculated from the

noise data. Equation 1 calculates dynamic range. Equation 2 calculates effective resolution. In each case, V_REF

corresponds to the internal 1.2-V reference. In global-chop mode, noise is improved by a factor of √ 2.

The noise performance scales with the OSR and gain settings, but is independent from the configured power

mode. Thus, the device exhibits the same noise performance in different power modes when selecting the same

OSR and gain settings. However, the data rate at the OSR settings scales based on the applied clock frequency

for the different power modes.

≈

’

V_REF

Dynamic Range = 20ìlog

∆

«

÷

2 ìGainì V_{RMS ◊}

(1)

(2)

≈

∆

«

’

÷

2ì V_REF

Gainì V_{RMS ◊}

Effective Resolution = log₂

Table 7-1. Noise (µV_RMS) at T_A= 25°C

GAIN

DATA RATE (kSPS),

OSR

f_CLKIN= 8.192 MHz

1

2

4

8

16

32

64

128

0.42

0.57

0.77

1.00

1.20

1.69

2.40

3.42

16384

8192

4096

2048

1024

512

0.25

0.5

1

1.90

2.39

3.38

4.25

5.35

7.56

10.68

21.31

1.69

2.13

2.99

3.91

4.68

6.62

9.56

15.26

1.56

2.13

2.88

3.79

4.52

6.37

9.09

13.52

0.95

1.29

1.74

2.27

2.70

3.82

5.42

7.89

0.64

0.86

1.17

1.52

1.82

2.55

3.63

5.21

0.42

0.57

0.77

1.00

1.20

1.69

2.39

3.41

0.42

0.57

0.77

1.00

1.20

1.69

2.39

3.42

2

4

8

256

16

32

128

Table 7-2. Dynamic Range (Effective Resolution) at T_A= 25°C

GAIN

DATA RATE (kSPS),

f_CLKIN= 8.192 MHz

OSR

1

2

4

8

16

32

64

128

16384

8192

4096

2048

1024

512

0.25

0.5

1

113 (20.3) 108 (19.4) 103 (18.6) 101 (18.3) 98 (17.8)

96 (17.5)

93 (17.0)

91 (16.6)

88 (16.2)

87 (15.9)

84 (15.4)

81 (14.9)

78 (14.4)

90 (16.5)

87 (16.0)

85 (15.6)

82 (15.2)

81 (14.9)

78 (14.4)

75 (13.9)

72 (13.4)

84 (15.4)

81 (15.0)

79 (14.6)

76 (14.2)

75 (13.9)

72 (13.4)

69 (12.9)

65 (12.4)

111 (19.9) 106 (19.1) 100 (18.1) 98 (17.8)

96 (17.4)

93 (17.0)

91 (16.6)

89 (16.3)

86 (15.8)

83 (15.3)

80 (14.8)

108 (19.4) 103 (18.6) 97 (17.7)

106 (19.1) 101 (18.2) 95 (17.3)

96 (17.4)

93 (17.0)

92 (16.8)

89 (16.3)

86 (15.8)

83 (15.2)

2

4

104 (18.8) 99 (18.0)

101 (18.3) 96 (17.5)

93 (17.0)

90 (16.5)

87 (16.0)

84 (15.4)

8

256

16

32

98 (17.8)

92 (16.8)

93 (16.9)

89 (16.3)

128

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8 Detailed Description

8.1 Overview

The ADS131M04 is a low-power, four-channel, simultaneously sampling, 24-bit, delta-sigma (ΔΣ) analog-to-

digital converter (ADC) with a low-drift internal reference voltage. The dynamic range, size, feature set, and

power consumption are optimized for cost-sensitive applications requiring simultaneous sampling.

The ADS131M04 requires both analog and digital supplies. The analog power supply (AVDD – AGND) can

operate between 2.7 V and 3.6 V. An integrated negative charge pump allows absolute input voltages as low as

1.3 V below AGND, which enables measurements of input signals varying around ground with a single-ended

power supply. The digital power supply (DVDD – DGND) accepts both 1.8-V and 3.3-V supplies. The device

features a programmable gain amplifier (PGA) with gains up to 128. An integrated input precharge buffer

enabled at gains greater than 4 ensures high input impedance at high PGA gain settings. The ADC receives its

reference voltage from an integrated 1.2-V reference. The device allows differential input voltages as large as

the reference. Three power-scaling modes allow designers to trade power consumption for ADC dynamic range.

Each channel on the ADS131M04 contains a digital decimation filter that demodulates the output of the ΔΣ

modulators. The filter enables data rates as high as 32 kSPS per channel in high-resolution mode. The relative

phase of the samples can be configured between channels, thus enabling an accurate compensation for the

sensor phase response. Offset and gain calibration registers can be programmed to automatically adjust output

samples for measured offset and gain errors. The Functional Block Diagram provides a detailed diagram of the

ADS131M04.

The device communicates via a serial programming interface (SPI)-compatible interface. Several SPI commands

and internal registers control the operation of the ADS131M04. Other devices can be added to the same SPI bus

by adding discrete CS control lines. The SYNC/RESET pin can be used to synchronize conversions between

multiple ADS131M04 devices as well as to maintain synchronization with external events.

8.2 Functional Block Diagram

AVDD

DVDD

1.2-V

Reference

AIN0P

AIN0N

+

Phase Shift &

Digital Filters

Gain & Offset

Calibration

DS ADC

œ

SYNC / RESET

AIN1P

AIN1N

+

Phase Shift &

Digital Filters

Gain & Offset

Calibration

CS

œ

SCLK

Control &

Serial Interface

DIN

DOUT

DRDY

AIN2P

AIN2N

+

Phase Shift &

Digital Filters

Gain & Offset

Calibration

œ

Clock

Generation

CLKIN

AIN3P

AIN3N

+

Phase Shift &

Digital Filters

Gain & Offset

Calibration

œ

AGND

DGND

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8.3 Feature Description

8.3.1 Input ESD Protection Circuitry

Basic electrostatic discharge (ESD) circuitry protects the ADS131M04 inputs from ESD and overvoltage events

in conjunction with external circuits and assemblies. Figure 8-1 depicts a simplified representation of the ESD

circuit. The protection for input voltages exceeding AVDD can be modeled as a simple diode.

AVDD

AINnP

To analog inputs

AINnN

AVDD

Figure 8-1. Input ESD Protection Circuitry

The ADS131M04 has an integrated negative charge pump that allows for input voltages below AGND with a

unipolar supply. Consequently, shunt diodes between the inputs and AGND cannot be used to clamp excessive

negative input voltages. Instead, the same diode that clamps overvoltage is used to clamp undervoltage at its

reverse breakdown voltage. Take care to prevent input voltages or currents from exceeding the limits provided in

the Absolute Maximum Ratings table in the Specifications section.

8.3.2 Input Multiplexer

Each channel of the ADS131M04 has a dedicated input multiplexer. The multiplexer controls which signals are

routed to the ADC channels. Configure the input multiplexer using the MUXn[1:0] bits in the CHn_CFG register.

The input multiplexer allows the following inputs to be connected to the ADC channel:

•

The analog input pins corresponding to the given channel

AGND, which is helpful for offset calibration

Positive DC test signal

Negative DC test signal

See the Internal Test Signals section for more information about the test signals. Figure 8-2 shows a diagram of

the input multiplexer on the ADS131M04.

MUXn[1:0] = 00

SW

To Positive

PGA Input

AINnP

MUXn[1:0] = 01

MUXn[1:0] = 10

+

DC Test

Signal

œ

AGND

MUXn[1:0] = 11

MUXn[1:0] = 10

MUXn[1:0] = 01

SW

To Negative

PGA Input

AINnN

MUXn[1:0] = 00

Figure 8-2. Input Multiplexer

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8.3.3 Programmable Gain Amplifier (PGA)

Each channel of the ADS131M04 features an integrated programmable gain amplifier (PGA) that provides gains

of 1, 2, 4, 8, 16, 32, 64, and 128. The gains for all channels are individually controlled by the PGAGAINn bits for

each channel in the GAIN1 register.

Varying the PGA gain scales the differential full-scale input voltage range (FSR) of the ADC. Equation 3

describes the relationship between FSR and gain. Equation 3 uses the internal reference voltage, 1.2 V, as the

scaling factor without accounting for gain error caused by tolerance in the reference voltage.

FSR = ±1.2 V / Gain

(3)

Table 8-1 shows the corresponding full-scale ranges for each gain setting.

Table 8-1. Full-Scale Range

GAIN SETTING

FSR

1

2

±1.2 V

±600 mV

±300 mV

±150 mV

±75 mV

4

8

16

32

64

128

±37.5 mV

±18.75 mV

±9.375 mV

The input impedance of the PGA dominates the input impedance characteristics of the ADS131M04. The PGA

input impedance for gain settings up to 4 behaves according to Equation 4 without accounting for device

tolerance and change over temperature. Minimize the output impedance of the circuit that drives the

ADS131M04 inputs to obtain the best possible gain error, INL, and distortion performance.

330 kΩ × 4.096 MHz / f_MOD

(4)

where:

f_MODis the ΔΣ modulator frequency, f_CLKIN/ 2

•

The device uses an input precharge buffer for PGA gain settings of 8 and higher. The input impedance at these

gain settings is very high. Specifying the input bias current for these gain settings is therefore more useful. A plot

of input bias current for the high gain settings is provided in Figure 6-5.

8.3.4 Voltage Reference

The ADS131M04 uses an internally-generated, low-drift, band-gap voltage to supply the reference for the ADC.

The reference has a nominal voltage of 1.2 V, allowing the differential input voltage to swing from –1.2 V to 1.2 V.

The reference circuitry starts up very quickly to accommodate the fast-startup feature of this device. The device

waits until after the reference circuitry is fully settled before generating conversion data.

8.3.5 Clocking and Power Modes

An LVCMOS clock must be provided at the CLKIN pin continuously when the ADS131M04 is running in normal

operation. The frequency of the clock can be scaled in conjunction with the power mode to provide a tradeoff

between power consumption and dynamic range.

The PWR[1:0] bits in the CLOCK register allow the device to be configured in one of three power modes: high-

resolution (HR) mode, low-power (LP) mode, and very low-power (VLP) mode. Changing the PWR[1:0] bits

scales the internal bias currents to achieve the expected power levels. The external clock frequency must follow

the guidance provided in the Recommended Operating Conditions table in the Specifications section

corresponding to the intended power mode in order for the device to perform according to the specification.

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8.3.6 ΔΣ Modulator

The ADS131M04 uses a delta-sigma (ΔΣ) modulator to convert the analog input voltage to a one's density

modulated digital bit-stream. The ΔΣ modulator oversamples the input voltage at a frequency many times

greater than the output data rate. The modulator frequency, f_MOD, of the ADS131M04 is equal to half the master

clock frequency, that is, f_MOD= f_CLKIN/ 2.

The output of the modulator is fed back to the modulator input through a digital-to-analog converter (DAC) as a

means of error correction. This feedback mechanism shapes the modulator quantization noise in the frequency

domain to make the noise more dense at higher frequencies and less dense in the band of interest. The digital

decimation filter following the ΔΣ modulator significantly attenuates the out-of-band modulator quantization

noise, allowing the device to provide excellent dynamic range.

8.3.7 Digital Filter

The ΔΣ modulator bit-stream feeds into a digital filter. The digital filter is a linear phase, finite impulse response

(FIR), low-pass sinc-type filter that attenuates the out-of-band quantization noise of the ΔΣ modulator. The digital

filter demodulates the output of the ΔΣ modulator by averaging. The data passing through the filter is decimated

and downsampled, to reduce the rate at which data come out of the modulator (f_MOD) to the output data rate

(f_DATA). The decimation factor is defined as per Equation 5 and is called the oversampling ratio (OSR).

OSR = f_MOD/ f_DATA

(5)

The OSR is configurable and set by the OSR[2:0] bits in the CLOCK register. There are eight OSR settings in

the ADS131M04, allowing eight different data rate settings for any given master clock frequency. Table 8-2 lists

the OSR settings and their corresponding output data rates for the nominal CLKIN frequencies mentioned.

The OSR determines the amount of averaging of the modulator output in the digital filter and therefore also the

filter bandwidth. The filter bandwidth directly affects the noise performance of the ADC because lower bandwidth

results in lower noise whereas higher bandwidth results in higher noise. See Table 7-1 for the noise

specifications for various OSR settings.

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Table 8-2. OSR Settings and Data Rates for Nominal Master Clock Frequencies

NOMINAL MASTER CLOCK

FREQUENCY

POWER MODE

f_MOD

OSR

OUTPUT DATA RATE

128

256

32 kSPS

16 kSPS

8 kSPS

4 kSPS

2 kSPS

1 kSPS

500 SPS

250 SPS

16 kSPS

8 kSPS

4 kSPS

2 kSPS

1 kSPS

500 SPS

250 SPS

125 SPS

8 kSPS

4 kSPS

2 kSPS

1 kSPS

500 SPS

250 SPS

125 SPS

62.5 SPS

512

1024

2048

4096

8192

16384

128

HR

8.192 MHz

4.096 MHz

2.048 MHz

4.096 MHz

256

512

1024

2048

4096

8192

16384

128

LP

2.048 MHz

256

512

1024

2048

4096

8192

16384

VLP

1.024 MHz

8.3.7.1 Digital Filter Implementation

Figure 8-3 shows the digital filter implementation of the ADS131M04. The modulator bit-stream feeds two

parallel filter paths, a sinc³filter, and a fast-settling filter path.

Power-up

or

Reset

OSR[2:0]

PHASEx[9:0]

OSR ≤ 1024

Sinc³

Regular

Filter

Sinc¹Averager

(OSR>1024)

Phase

Delay

0

Calibration

Logic,

Gain scaling

Global

Chop

Logic

Modulator

Bitstream

MUX

1

MUX

1

OSR[2:0]

Fast-Settling Filter

OSR = 1024

PGA_GAINx[2:0]

Figure 8-3. Digital Filter Implementation

8.3.7.1.1 Fast-Settling Filter

At power-up or after a device reset, the ADS131M04 selects the fast-settling filter to allow for settled output data

generation with minimal latency. The fast-settling filter has the characteristic of a first-order sinc filter (sinc¹).

After two conversions, the device switches to and remains in the sinc³filter path until the next time the device is

reset or powered cycled.

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The fast-settling filter exhibits wider bandwidth and less stop-band attenuation than the sinc³filter. Consequently,

the noise performance when using the fast-settling filter is not as high as with the sinc³filter. The first two

samples available from the ADS131M04 after a supply ramp or reset have the noise performance and frequency

response corresponding to the fast-settling filter as specified in the Electrical Characteristics table, whereas

subsequent samples have the noise performance and frequency response consistent with the sinc³filter. See

the Fast Startup Behavior section for more details regarding the fast startup capabilities of the ADS131M04.

8.3.7.1.2 SINC³and SINC³+ SINC¹Filter

The ADS131M04 selects the sinc³filter path two conversion after power-up or device reset. For OSR settings of

128 to 1024 the sinc³filter output directly feeds into the global chop and calibration logic. For OSR settings of

2048 and higher the sinc³filter is followed by a sinc¹filter. As shown in Table 8-3, the sinc³filter operates at a

fixed OSR of 1024 in this case while the sinc¹filter implements the additional OSRs of 2 to 16. That means when

an OSR of 4096 (for example) is selected, the sinc³filter operates at an OSR of 1024 and the sinc¹filter at an

OSR of 4.

The filter has infinite attenuation at integer multiples of the data rate except for integer multiples of f_MOD. Like all

digital filters, the digital filter response of the ADS131M04 repeats at integer multiples of the modulator

frequency, f_MOD. The data rate and filter notch frequencies scale with f_MOD

.

When possible, plan frequencies for unrelated periodic processes in the application for integer multiples of the

data rate such that any parasitic effect they have on data acquisition is effectively cancelled by the notches of

the digital filter. Avoid frequencies near integer multiples of f_MODwhenever possible because tones in these

bands can alias to the band of interest.

The sinc³and sinc³+ sinc¹filters for a given channel require time to settle after a channel is enabled, the

channel multiplexer or gain setting is changed, or a resynchronization event occurs. See the Synchronization

section for more details on resynchronization. Table 8-3 lists the settling times of the sinc³and sinc³+ sinc¹

filters for each OSR setting. The ADS131M04 does not gate unsettled data. Therefore, the host must account for

the filter settling time and disregard unsettled data if any are read. The data at the next DRDY falling edge after

the filter settling time listed in Table 8-3 has expired can be considered fully settled.

Table 8-3. Digital Filter Startup Times after powerup or resynchronization

OSR (OVERALL)

OSR (SINC³)

OSR (SINC¹)

SETTLING TIME (t_CLKIN

)

128

256

128

N/A

2

856

1112

256

512

1624

2648

4696

8792

16984

33368

1024

2048

4096

8192

16384

1024

4

1024

8

1024

16

8.3.7.2 Digital Filter Characteristic

Equation 6 calculates the z-domain transfer function of a sinc³filter that is used for OSRs of 1024 and lower.

3

1 - Z ^-N

H z

( )

=

N 1 - Z ^-1

(

)

(6)

where N is the OSR.

Equation 7 calculates the transfer function of a sinc³filter in terms of the continuous-time frequency parameter f.

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3

Npf

f_MOD

sin

H(f)½ =

pf

f_MOD

N ´ sin

(7)

where N is the OSR.

Figure 8-4 through Figure 8-7 show the digital filter response of the fast-settling filter and the sinc³filter for OSRs

of 1024 and lower. Figure 8-6 and Figure 8-7 show the digital filter response of the sinc³+ sinc¹filter for an OSR

of 4096.

0

-20

0

-1.5

-3

-40

-4.5

-6

-60

-80

-7.5

-9

-100

-120

-140

-10.5

-12

Fast-settling filter

Sinc³filter

Fast-settling filter

Sinc³filter

0

0.1

0.2 0.3

Frequency (f_IN/f_DATA

0.4

0.5

0

1

2

3

Frequency (f_IN/f_DATA

4

5

)

Figure 8-5. Fast-Settling and Sinc³Digital Filter

Response, Pass-Band Detail

Figure 8-4. Fast-Settling and Sinc³Digital Filter

Response

0

-2

-4

-6

-8

Sinc³filter (1024)

Sinc³+ Sinc¹filter

-20

-40

-60

-80

-100

-120

-140

-10

Sinc³filter (1024)

Sinc³+ Sinc¹filter

-12

0

1

2

3

4

5

6

7

Frequency (f /f_DATA

8

)

9

10 11 12

0

0.1

0.2 0.3

Frequency (f /f_DATA

0.4

0.5

IN

)

IN

Figure 8-6. Digital Filter Response for OSR = 1024

and OSR = 4096

Figure 8-7. Digital Filter Response for OSR = 1024

and OSR = 4096, Pass-Band Detail

8.3.8 DC Block Filter

The ADS131M04 includes an optional high-pass filter to eliminate any systematic offset or low-frequency noise.

The filter is enabled by writing any value in the DCBLOCK[3:0] bits in the CD_TH_LSB register besides 0h. The

DC block filter can be enabled and disabled on a channel-by-channel basis by the DCBLKn_DIS bit in the

CHn_CFG register for each respective channel.

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Figure 8-8 shows the topology of the DC block filter. Coefficient a represents a register configurable value that

configures the cutoff frequency of the filter. The cutoff frequency is configured using the DCBLOCK[3:0] bits in

the CD_TH_LSB register. Table 8-4 describes the characteristics of the filter for various DCBLOCK[3:0] settings.

The data provided in Table 8-4 is provided for an 8.192-MHz CLKIN frequency and a 4-kSPS data rate. The

frequency response of the filter response scales directly with the frequency of CLKIN and the data rate.

a

2

1Å

Input

Output

z^-1

1-z^-1

Åa

Figure 8-8. DC Block Filter Topology

Table 8-4. DC Block Filter Characteristics

PASS-BAND ATTENUATION⁽¹⁾

SETTLING TIME (Samples)

SETTLED >99% FULLY SETTLED

–3-dB

DCBLOCK[3:0] a COEFFICIENT

CORNER⁽¹⁾

50 Hz

60 Hz

0h

DC block filter disabled

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Ch

Dh

Eh

Fh

1/4

1/8

181 Hz

84.8 Hz

11.5 dB

10.1 dB

4.77 dB

17

88

5.89 dB

2.24 dB

36

72

187

387

1/16

41.1 Hz

1.67 dB

1/32

20.2 Hz

657 mdB

171 mdB

43.1 mdB

10.8 mdB

2.69 mdB

671 µdB

168 µdB

41.9 µdB

10.5 µdB

2.63 µdB

655 ndB

164 ndB

466 mdB

119 mdB

29.9 mdB

7.47 mdB

1.87 mdB

466 µdB

116 µdB

29.1 µdB

7.27 µdB

1.82 µdB

455 ndB

114 ndB

146

786

1/64

10.0 Hz

293

1585

1/128

1/256

1/512

1/1024

1/2048

1/4096

1/8192

1/16384

1/32768

1/65536

4.99 Hz

588

3182

2.49 Hz

1178

2357

4714

9430

18861

37724

75450

150901

301803

6376

1.24 Hz

12764

25540

51093

102202

204447

409156

820188

1627730

622 mHz

311 mHz

155 mHz

77.7 mHz

38.9 mHz

19.4 mHz

9.70 mHz

(1) Values given are for a 4-kSPS data rate with a 8.192-MHz CLKIN frequency.

8.3.9 Internal Test Signals

The ADS131M04 features an internal analog test signal that is useful for troubleshooting and diagnosis. A

positive or negative DC test signal can be applied to the channel inputs through the input multiplexer. The

multiplexer is controlled through the MUXn[1:0] bits in the CHn_CFG register. The test signals are created by

internally dividing the reference voltage. The same signal is shared by all channels.

The test signal is nominally 2 / 15 × V_REF. The test signal automatically adjusts its voltage level with the gain

setting such that the ADC always measures a signal that is 2 / 15 × V_{Diff Max}. For example, at a gain of 1, this

voltage equates to 160 mV. At a gain of 2, this voltage is 80 mV.

8.3.10 Channel Phase Calibration

The ADS131M04 allows fine adjustment of the sample phase between channels through the use of channel

phase calibration. This feature is helpful when different channels are measuring the outputs of different types of

sensors that have different phase responses. For example, in power metrology applications, voltage can be

measured by a voltage divider, whereas current is measured using a current transformer that exhibits a phase

difference between its input and output signals. The differences in phase between the voltage and current

measurement must be compensated to measure the power and related parameters accurately.

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The phase setting of the different channels is configured by the PHASEn[9:0] bits in the CHn_CFG register

corresponding to the channel whose phase adjustment is desired. The register value is a 10-bit two's

complement value corresponding to the number of modulator clock cycles of phase offset compared to a

reference phase of 0 degrees.

The mechanism for achieving phase adjustment derives from the ΔΣ architecture. The ΔΣ modulator produces

samples continuously at the modulator frequency, f_MOD. These samples are filtered and decimated to the output

data rate by the digital filter. The ratio between f_MODand the data rate is the oversampling ratio (OSR). Each

conversion result corresponds to an OSR number of modulator samples provided to the digital filter. When the

different channels of the ADS131M04 have no programmed phase offset between them, the modulator clock

cycles corresponding to the conversion results of the different channels are aligned in the time domain. Figure

8-9 depicts an example scenario where the voltage input to channel 1 has no phase offset from channel 0.

Sample

Period

CH0 Input

CH1 Input

Figure 8-9. Two Channel Outputs With Equal Phase Settings

However, the sample period of one channel can be shifted with respect to another. If the inputs to both channels

are sinusoids of the same frequency and the samples for these channels are retrieved by the host at the same

time, the effect is that the phase of the channel with the modified sample period appears shifted. Figure 8-10

depicts how the period corresponding to the samples are shifted between channels. Figure 8-11 illustrates how

the samples appear as having generated a phase shift when they are retrieved by the host.

Sample

Period

CH0 Input

CH1 Input

Sample Period

Offset

Figure 8-10. Channel 1 With a Positive Sample Phase Shift With Respect to Channel 0

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CH0 Output

CH1 Output

Figure 8-11. Channels 1 and 0 From the Perspective of the Host

The valid setting range is from –OSR / 2 to (OSR / 2) – 1, except for OSRs greater than 1024, where the phase

calibration setting is limited to –512 to 511. If a value outside of –OSR / 2 and (OSR / 2) – 1 is programmed, the

device internally clips the value to the nearest limit. For example, if the OSR setting is programmed to 128 and

the PHASEn[9:0] bits are programmed to 0001100100b corresponding to 100 modulator clock cycles, the device

sets the phase of the channel to 63 because that value is the upper limit of phase calibration for that OSR

setting. Table 8-5 gives the range of phase calibration settings for various OSR settings.

Table 8-5. Phase Calibration Setting Limits for Different OSR Settings

OSR SETTING

PHASE OFFSET RANGE (t_MOD

)

PHASEn[9:0] BITS RANGE

11 1100 0000b to 00 0011 1111b

11 1000 0000b to 00 0111 1111b

11 0000 0000b to 00 1111 1111b

10 0000 0000b to 01 1111 1111b

128

–64 to 63

256

–128 to 127

512

–256 to 255

1024

–512 to 511

2048

–512 to 511

4096

–512 to 511

8192

–512 to 511

16384

–512 to 511

Follow these steps to create a phase shift larger than half the sample period for OSRs less than 2048:

•

Create a phase shift corresponding to an integer number of sample periods by modifying the indices between

channel data in software

•

Use the phase calibration function of the ADS131M04 to create the remaining fractional sample period phase

shift

For example, to create a phase shift of 2.25 samples between channels 0 and 1, create a phase shift of two

samples by aligning sample N in the channel 0 output data stream with sample N+2 in the channel 1 output data

stream in the host software. Make the remaining 0.25 sample adjustment using the ADS131M04 phase

calibration function.

The phase calibration settings of the channels affect the timing of the data-ready interrupt signal, DRDY. See the

Data Ready (DRDY) section for more details regarding how phase calibration affects the DRDY signal.

8.3.11 Calibration Registers

The calibration registers allow for the automatic computation of calibrated ADC conversion results from pre-

programmed values. The host can rely on the device to automatically correct for system gain and offset after the

error correction terms are programmed into the corresponding device registers. The measured calibration

coefficients must be store in external non-volatile memory and programmed into the registers each time the

ADS131M04 powers up because the ADS131M04 registers are volatile.

The offset calibration registers are used to correct for system offset error, otherwise known as zero error. Offset

error corresponds to the ADC output when the input to the system is zero. The ADS131M04 corrects for offset

errors by subtracting the contents of the OCALn[23:0] register bits in the CHn_OCAL_MSB and

CHn_OCAL_LSB registers from the conversion result for that channel before being output. There are separate

CHn_OCAL_MSB and CHnOCAL_LSB registers for each channel, which allows separate offset calibration

coefficients to be programmed for each channel. The contents of the OCALn[23:0] bits are interpreted by the

device as 24-bit two's complement values, which is the same format as the ADC data.

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The gain calibration registers are used to correct for system gain error. Gain error corresponds to the deviation of

gain of the system from its ideal value. The ADS131M04 corrects for gain errors by multiplying the ADC

conversion result by the value given by the contents of the GCALn[23:0] register bits in the CHn_GCAL_MSB

and CHn_GCAL_LSB registers before being output. There are separate CHn_GCAL_MSB and

CHn_GCAL_LSB registers for each channel, which allows separate gain calibration coefficients to be

programmed for each channel. The contents of the GCALn[23:0] bits are interpreted by the device as 24-bit

unsigned values corresponding to linear steps ranging from gains of 0 to 2 – (1 / 2²³). Table 8-6 describes the

relationship between the GCALn[23:0] bit values and the gain calibration factor.

Table 8-6. GCALn[23:0] Bit Mapping

GCALn[23:0] VALUE

GAIN CALIBRATION FACTOR

000000h

0

000001h

1.19 × 10^–7

800000h

1

FFFFFEh

2 – 2.38 × 10^–7

2 – 1.19 × 10^–7

FFFFFFh

The calibration registers do not need to be enabled because they are always in use. The OCALn[23:0] bits have

a default value of 000000h resulting in no offset correction. Similarly, the GCALn[23:0] bits default to 800000h

resulting in a gain calibration factor of 1.

Figure 8-12 shows a block diagram illustrating the mechanics of the calibration registers on one channel of the

ADS131M04.

ûꢀ

Modulator

Digital

Filter

To Interface

Å

1

2²³

OCALn[23:0]

GCALn[23:0]

Figure 8-12. Calibration Block Diagram

8.3.12 Communication Cyclic Redundancy Check (CRC)

The ADS131M04 features a cyclic redundancy check (CRC) engine on both input and output data to mitigate

SPI communication errors. The CRC word is 16 bits wide for either input or output CRC. Coverage includes all

words in the SPI frame where the CRC is enabled, including padded bits in a 32-bit word size.

CRC on the SPI input is optional and can be enabled and disabled by writing the RX_CRC_EN bit in the MODE

register. Input CRC is disabled by default. When the input CRC is enabled, the device checks the provided input

CRC against the CRC generated based on the input data. A CRC error occurs if the CRC words do not match.

The device does not execute any commands, except for the WREG command, if the input CRC check fails. A

WREG command always executes even when the CRC check fails. The device sets the CRC_ERR bit in the

STATUS register for all cases of a CRC error. The response on the output in the SPI frame following the frame

where the CRC error occurred is that of a NULL command, which means the STATUS register plus the

conversion data are output in the following SPI frame. The CRC_ERR bit is cleared when the STATUS register is

output.

The output CRC cannot be disabled and always appears at the end of the output frame. The host can ignore the

data if the output CRC is not used.

There are two types of CRC polynomials available: CCITT CRC and ANSI CRC (CRC-16). The CRC setting

determines the algorithm for both the input and output CRC. The CRC type is programmed by the CRC_TYPE

bit in the MODE register. Table 8-7 lists the details of the two CRC types.

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The seed value of the CRC calculation is FFFFh.

Table 8-7. CRC Types

CRC TYPE

CCITT CRC

ANSI CRC

POLYNOMIAL

x¹⁶+ x¹²+ x⁵+ 1

x¹⁶+ x¹⁵+ x²+ 1

BINARY POLYNOMIAL

0001 0000 0010 0001

1000 0000 0000 0101

8.3.13 Register Map CRC

The ADS131M04 performs a CRC on its own register map as a means to check for unintended changes to the

registers. Enable the register map CRC by setting the REG_CRC_EN bit in the MODE register. When enabled,

the device constantly calculates the register map CRC using each bit in the writable register space. The register

addresses covered by the register map CRC on the ADS131M04 are 02h through 1Ch. The CRC is calculated

beginning with the MSB of register 02h and ending with the LSB of register 1Ch using the polynomial selected in

the CRC_TYPE bit in the MODE register.

The calculated CRC is a 16-bit value and is stored in the REGMAP_CRC register. The calculation is done using

one register map bit per CLKIN period and constantly checks the result against the previous calculation. The

REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes

resulting from register writes. The bit is cleared by reading the STATUS register, or by the STATUS register being

output as a response to the NULL command.

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8.4 Device Functional Modes

Figure 8-13 shows a state diagram depicting the major functional modes of the ADS131M04 and the transitions

between them.

POR, pin reset, or

RESET command

Reset

complete

Reset

STANDBY

Standby

Mode

Continuous

Conversion Mode

WAKEUP && GC_EN

STANDBY

Current detection

complete

GC_EN

WAKEUP

&& GC_EN

GC_EN

Current

Detect Mode

Global Chop

Mode

SYNC

Figure 8-13. State Diagram Depicting Device Functional Modes

8.4.1 Power-Up and Reset

The ADS131M04 is reset in one of three ways: by a power-on reset (POR), by the SYNC/RESET pin, or by a

RESET command. After a reset occurs, the configuration registers are reset to the default values and the device

begins generating conversion data as soon as a valid MCLK is provided. In all three cases a low to high

transition on the DRDY pin indicates that the SPI interface is ready for communication. The device ignores any

SPI communication before this point.

8.4.1.1 Power-On Reset

Power-on reset (POR) is the reset that occurs when a valid supply voltage is first applied. The POR process

requires t_PORfrom when the supply voltages reach 90% of their nominal value. Internal circuitry powers up and

the registers are set to their default state during this time. The DRDY pin transitions from low to high immediately

after t_PORindicating the SPI interface is ready for communication. The device ignores any SPI communication

before this point.

8.4.1.2 SYNC/RESET Pin

The SYNC/RESET pin is an active low, dual-function pin that generates a reset if the pin is held low longer than

t_w(RSL). The device maintains a reset state until SYNC/RESET is returned high. The host must wait for at least

t_REGACQafter SYNC/RESET is brought high or for the DRDY rising edge before communicating with the device.

Conversion data are generated immediately after the registers are reset to their default values, as described in

the Fast Startup Behavior section.

8.4.1.3 RESET Command

The ADS131M04 can be reset via the SPI RESET command (0011h). The device communicates in frames of a

fixed length. See the SPI Communication Frames section for details regarding SPI data framing on the

ADS131M04. The RESET command occurs in the first word of the data frame, but the command is not latched

by the device until the entire frame is complete. After the response completes channel data and CRC words are

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clocked out. Terminating the frame early causes the RESET command to be ignored. Six words are required to

complete a frame on the ADS131M04.

A reset occurs immediately after the command is latched. The host must wait for t_REGACQbefore communicating

with the device to ensure the registers have assumed their default settings. Conversion data are generated

immediately after the registers are reset to their default values, as described in the Fast Startup Behavior

section.

8.4.2 Fast Startup Behavior

The ADS131M04 begins generating conversion data shortly after startup as soon as a valid CLKIN signal is

provided to the ΔΣ modulators. The fast startup feature is useful for applications such as circuit breakers

powered from the mains that require a fast determination of the input voltage soon after power is applied to the

device. Fast startup is accomplished via two mechanisms. First, the device internal power-supply circuitry is

designed specifically to enable fast startup. Second, the digital decimation filter dynamically switches from a fast-

settling filter to a sinc³filter when the sinc³filter has had time to settle.

After the supplies are ramped to 90% of their final values, the device requires t_PORfor the internal circuitry to

settle. The end of t_PORis indicated by a transition of DRDY from low to high. The transition of DRDY from low to

high also indicates the SPI interface is ready to accept commands.

The ΔΣ modulators of the ADS131M04 require CLKIN to toggle after t_PORto begin working. The modulators

begin sampling the input signal after an initial wait time delay of (256 + 44) × t_MODwhen CLKIN begins toggling.

Therefore, provide a valid clock signal on CLKIN as soon as possible after the supply ramp to achieve the fastest

possible startup time.

The data generated by the ΔΣ modulators are fed to the digital filter blocks. The data are provided to both the

fast-settling filter and the sinc³filter paths. The fast-settling filter requires only one data rate period to provide

settled data. Meanwhile, the sinc³filter requires three data rate periods to settle. The fast-settling filter generates

the output data for the two interim ADC output samples indicated by DRDY transitioning from high to low while

the sinc³filter is settling. The device disables the fast-settling filter and provides conversion data from the sinc³

filter path for the third and following samples. Figure 8-14 shows the behavior of the fast-startup feature when

using an external clock that is provided to the device right after the supplies have ramped. Table 8-8 shows the

values for the various startup and settling times relevant to the device startup.

90%

t_SETTLE3

t_DATA

Supplies

t_POR

t_SETTLE1

t_DATA

DRDY

Fast-settling

filter data

Fast-settling

filter data

Sinc³

filter data

Sinc³

filter data

...

CLKIN

Figure 8-14. Fast Startup Behavior and Settling Times

Table 8-8. Fast Startup Settling Times for Default OSR = 1024

VALUE (DETAILS)

(t_MOD

VALUE

(t_MOD

VALUE AT

F_CLKIN= 8.192 MHz (ms)

PARAMETER

)

t_DATA= 1/f_DATA

t_SETTLE1

1024

1324

3372

0.250

0.323

0.823

256 + 44 + 1024

256 + 44 + 3 x 1024

t_SETTLE3

The fast-settling filter provides conversion data that are significantly noisier than the data that comes from the

sinc³filter path, but allows the device to provide settled conversion data during the longer settling time of the

more accurate sinc³digital filter. If the level of precision provided by the fast-settling filter is insufficient even for

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the first samples immediately following startup, ignore the first two instances of DRDY toggling from high to low

and begin collecting data on the third instance.

The startup process following a RESET command or a pin reset using the SYNC/RESET pin is similar to what

occurs after power up. However there is no t_PORin the case of a command or pin reset because the supplies are

already ramped. After reset, the device waits for the initial wait time delay of (256 + 44) × t_MODbefore providing

modulator samples to the two digital filters. The fast-settling filter is enabled for the first two output samples.

8.4.3 Conversion Modes

There are two ADC conversion modes on the ADS131M04: continuous-conversion and global-chop mode.

Continuous-conversion mode is a mode where ADC conversions are generated constantly by the ADC at a rate

defined by f_MOD/ OSR. Global-chop mode differs from continuous-conversion mode because global-chop

periodically chops (or swaps) the inputs, which reduces system offset errors at the cost of settling time between

the points when the inputs are swapped. In either continuous-conversion or global-chop mode, there are three

power modes that provide flexible options to scale power consumption with bandwidth and dynamic range. The

Power Modes section discusses these power modes in further detail.

8.4.3.1 Continuous-Conversion Mode

Continuous-conversion mode is the mode in which ADC data are generated constantly at the rate of f_MOD/ OSR.

New data are indicated by a DRDY falling edge at this rate. Continuous-conversion mode is intended for

measuring AC signals because this mode allows for higher output data rates than global-chop mode.

8.4.3.2 Global-Chop Mode

The ADS131M04 incorporates a global-chop mode option to reduce offset error and offset drift inherent to the

device due to mismatch in the internal circuitry to very low levels. When global-chop mode is enabled by setting

the GC_EN bit in the GLOBAL_CHOP_CFG register, the device uses the conversion results from two

consecutive internal conversions taken with opposite input polarity to cancel the device offset voltage.

Conversion n is taken with normal input polarity. The device then reverses the internal input polarity for

conversion n + 1. The average of two consecutive conversions (n and n + 1, n + 1 and n + 2 and so on) yields

the final offset compensated result.

Figure 8-15 shows a block diagram of the global-chop mode implementation. The combined PGA and ADC

internal offset voltage is modeled as V_OFS. Only this device inherent offset voltage is reduced by global-chop

mode. Offset in the external circuitry connected to the analog inputs is not affected by global-chop mode.

GC_EN

Chop Switch

V_OFS

-

+

AINnP

AINnN

C

A D

Digital

Filter

Global-Chop

Mode Control

PGA

ADC

Conversion Output

Figure 8-15. Global-Chop Mode Implementation

The conversion period in global-chop mode differs from the conversion time when global-chop mode is disabled

(t_DATA= OSR x t_MOD). Figure 8-16 shows the conversion timing for an ADC channel using global-chop mode.

Global-chop delay

Modulator sampling

1^stglobal-chop

conversion result

2^ndglobal-chop

conversion result

Conversion

start

Data not

settled

Data not

settled

Swap inputs,

digital filter reset

Data not

settled

Data not

settled

ADC overhead

Sampling

n

Sampling

n

Sampling

n

Sampling

n + 1

Sampling

n + 1

Sampling

n + 1

Sampling

n + 2

Sampling

n + 2

Sampling

n + 2

Sampling

n + 3

Sampling

n + 3

Sampling

n + 3

t_{GC_FIRST}

t_{GC_CONVERSION}

t_DATA

CONVERSION

Figure 8-16. Conversion Timing With Global-Chop Mode Enabled

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Every time the device swaps the input polarity, the digital filter is reset. The ADC then always takes three internal

conversions to produce one settled global-chop conversion result.

The ADS131M04 provides a programmable delay (t_{GC_DLY}) between the end of the previous conversion period

and the beginning of the subsequent conversion period after the input polarity is swapped. This delay is to allow

for external input circuitry to settle because the chopping switches interface directly with the analog inputs. The

GC_DLY[3:0] bits in the GLOBAL_CHOP_CFG register configure the delay after chopping the inputs. The

global-chop delay is selected in terms of modulator clock periods from 2 to 65,536 x t_MOD

.

The effective conversion period in global-chop mode follows Equation 8. A DRDY falling edge is generated each

time a new global-chop conversion becomes available to the host.

The conversion process of all ADC channels in global-chop mode is restarted in the following two conditions so

that all channels start sampling at the same time:

•

Falling edge of SYNC/RESET pin

Change of OSR setting

The conversion period of the first conversion after the ADC channels have been reset is considerably longer

than the conversion period of all subsequent conversions mentioned in Equation 8, because the device first

needs to perform two fully settled internal conversions with the input polarity swapped. The conversion period for

the first conversion in global-chop mode follows Equation 9.

t_{GC_CONVERSION}= t_{GC_DLY}+ 3 × OSR x t_MOD

(8)

(9)

t_{GC_FIRST_CONVERSION}= t_{GC_DLY}+ 3 × OSR x t_MOD+ t_{GC_DLY}+ 3 × OSR x t_MOD+ 44 x t_MOD

Using global-chop mode reduces the ADC noise shown in Table 7-1 at a given OSR by a factor of √2 because

two consecutive internal conversions are averaged to yield one global-chop conversion result. The DC test

signal cannot be measured in global-chop mode.

Phase calibration is automatically disabled in global-chop mode.

8.4.4 Power Modes

In both continuous-conversion and global-chop mode, there are three selectable power modes that allow scaling

of power with bandwidth and performance: high-resolution (HR) mode, low-power (LP) mode, and very-low-

power (VLP) mode. The mode is selected by the PWR[1:0] bits in the CLOCK register. See the Recommended

Operating Conditions table in the Specifications section for restrictions on the CLKIN frequency for each power

mode.

8.4.5 Standby Mode

Standby mode is a low-power state in which all channels are disabled, and the reference and other non-

essential circuitry are powered down. This mode differs from completely powering down the device because the

device retains its register settings. Enter standby mode by sending the STANDBY command (0022h). Stop

toggling CLKIN when the device is in standby mode to minimize device power consumption. Exit standby mode

by sending the WAKEUP command (0033h). After exiting standby mode, the modulators begin sampling the

input signal after a modulator settling time of 8 × t_MODwhen CLKIN begins toggling.

8.4.6 Current-Detect Mode

Current-detect mode is a special mode that is helpful for applications requiring tamper detection when the

equipment is in a low-power state. In this mode, the ADS131M04 collects a configurable number of samples at a

nominal data rate of 2.7 kSPS and compares the absolute value of the results to a programmable threshold. If a

configurable number of results exceed the threshold, the host is notified via a DRDY falling edge and the device

returns to standby mode. Enter current-detect mode by providing a negative pulse on SYNC/RESET with a pulse

duration less than t_w(RSL)when in standby mode. Current-detect mode can only be entered from standby mode.

The device uses a limited power operating mode to generate conversions in current-detect mode. The

conversion results are only used for comparison by the internal digital threshold comparator and are not

accessible by the host. The device uses an internal oscillator that enables the device to capture the data without

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the use of the external clock input. Do not toggle CLKIN when in current-detect mode to minimize device power

consumption.

Current-detect mode is configured in the CFG, THRSHLD_MSB, and THRSHLD_LSB registers. Enable and

disable current-detect mode by toggling the CD_EN bit in the CFG register. The THRSHLD_MSB and

THRSHLD_LSB registers contain the CD_THRSH[23:0] bits that represent the digital comparator threshold

value during current detection.

The number of samples used for current detection are programmed by the CD_LEN[2:0] bits in the CFG register.

The number of samples used for current detection range from 128 to 3584.

The programmable values in CD_NUM[2:0] configure the number of samples that must exceed the threshold for

a detection to occur. The purpose of requiring multiple samples for detection is to control noisy values that may

exceed the threshold, but do not represent a high enough power level to warrant action by the host. In summary,

the conversion result must exceed the value programmed in CD_THRSH[23:0] a number of times as

represented by the value stored in CD_NUM[2:0].

The device can be configured to notify the host based on any of the results from either individual channels , all

channels, or any combination of channels. The CD_ALLCH bit in the CFG register determines how many

channels are required to exceed the programmed thresholds to trigger a current detection. When the bit is 1, all

enabled channels are required to meet the current detection requirements in order for the host to be notified. If

the bit is 0, any enabled channel triggers a current detection notification if the requirements are met. Enable and

disable channels using the CHn_EN bits in the CLK register to control which combination of channels must meet

the requirements to trigger a current-detection notification.

Figure 8-17 illustrates a flow chart depicting the current-detection process on the ADS131M04.

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Continuous Conversion

Mode

WAKEUP Command

No

STANDY Command?

Yes

Standby Mode

No

SYNC

Asserted?

Yes

Current Detection Mode

Yes

Samples Collected =

CD_LEN?

No

Measurement >

CD_THRSHLD?

Yes

Increment threshold

counter

No

Threshold counter >

CD_NUM?

Yes

No

Assert DRDY

CD_ALLCH?

Yes

No

Current detected on all

enabled channels?

Figure 8-17. Current-Detect Mode Flow Chart

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8.5 Programming

8.5.1 Interface

The ADS131M04 uses an SPI-compatible interface to configure the device and retrieve conversion data. The

device always acts as an SPI slave; SCLK and CS are inputs to the interface. The interface operates in SPI

mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, the SCLK idles low and data are launched or changed

only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. The

interface is full-duplex, meaning data can be sent and received simultaneously by the interface. The device

includes the typical SPI signals: SCLK, CS, DIN (MOSI), and DOUT (MISO). In addition, there are two other

digital pins that provide additional functionality. The DRDY pin serves as a flag to the host to indicate new

conversion data are available. The SYNC/RESET pin is a dual-function pin that allows synchronization of

conversions to an external event and allows for a hardware device reset.

8.5.1.1 Chip Select (CS)

The CS pin is an active low input signal that selects the device for communication. The device ignores any

communication and DOUT is high impedance when CS is held high. Hold CS low for the duration of a

communication frame to ensure proper communication. The interface is reset each time CS is taken high.

8.5.1.2 Serial Data Clock (SCLK)

The SCLK pin is an input that serves as the serial clock for the interface. Output data on the DOUT pin transition

on the rising edge of SCLK and input data on DIN are latched on the falling edge of SCLK.

8.5.1.3 Serial Data Input (DIN)

The DIN pin is the master out, slave in (MOSI) pin for the device. Serial commands are shifted in through the

DIN pin by the device with each SCLK falling edge when the CS pin is low.

8.5.1.4 Serial Data Output (DOUT)

The DOUT pin is the master in, slave out (MISO) pin for the device. The device shifts out command responses

and ADC conversion data serially with each rising SCLK edge when the CS pin is low. This pin assumes a high-

impedance state when CS is high.

8.5.1.5 Data Ready (DRDY)

The DRDY pin is an active low output that indicates when new conversion data are ready in conversion mode or

that the requirements are met for current detection when in current-detect mode. Connect the DRDY pin to a

digital input on the host to trigger periodic data retrieval in conversion mode. The period between each DRDY

falling edge is the data rate period.

The timing of DRDY with respect to the sampling of a given channel on the ADS131M04 depends on the phase

calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting the

DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase

calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts

DRDY each time any channel data are ready. Finally, setting the bits to either 10b or 11b configures the device to

assert DRDY when the channel with the most negative phase calibration setting, or the most leading, has new

conversion data. Changing the DRDY_SEL[1:0] bits has no effect on DRDY behavior in global-chop mode

because phase calibration is automatically disabled in global-chop mode.

The timing of the first DRDY assertion after channels are enabled or after a synchronization pulse is provided

depends on the phase calibration setting. If the channel that causes DRDY to assert has a phase calibration

setting less than zero, the first DRDY assertion can be less than one sample period from the channel being

enabled or the occurrence of the synchronization pulse. However, DRDY asserts in the next sample period if the

phase setting puts the output timing too close to the beginning of the sample period.

Table 8-9 lists the phase calibration setting boundary at which DRDY either first asserts within a sample period,

or in the next sample period. If the setting for the channel configured to control DRDY assertion is greater than

the value listed in Table 8-9 for each OSR, DRDY asserts for the first time within a sample period of the channel

being enabled or the synchronization pulse. If the phase setting value is equal to or more negative than the

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value in Table 8-9, DRDY asserts in the following sample period. See the Synchronization section for more

information about synchronization.

Table 8-9. Phase Setting First DRDY Assertion Boundary

OSR

128

PHASE SETTING BOUNDARY

PHASEn[9:0] BIT SETTING BOUNDARY

–19

–83

3EDh

3ADh

32Dh

22Dh

N/A

256

512

–211

–467

None

1024

>1024

The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the

bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY

behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not

asserted.

The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new

data are indicated by DRDY changing from high to low and remaining low until either all of the conversion data

are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low.

When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If the host

does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a conversion

result and does not provide another DRDY pulse until the second following instance when data are ready

because of how the pulse is generated. See the Collecting Data for the First Time or After a Pause in Data

Collection section for more information about the behavior of DRDY when data are not consistently read.

The DRDY pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid

reading ADC data during the time where new conversions complete in order to achieve consistent DRDY

behavior.

8.5.1.6 Conversion Synchronization or System Reset (SYNC/RESET)

The SYNC/RESET pin is a multi-function digital input pin that serves primarily to allow the host to synchronize

conversions to an external process or to reset the device. See the Synchronization section for more details

regarding the synchronization function. See the SYNC/RESET Pin section for more details regarding how the

device is reset.

8.5.1.7 SPI Communication Frames

SPI communication on the ADS131M04 is performed in frames. Each SPI communication frame consists of

several words. The word size is configurable as either 16 bits, 24 bits, or 32 bits by programming the

WLENGTH[1:0] bits in the MODE register.

The ADS131M04 implements a timeout feature for the SPI communication. Enable or disable the timeout using

the TIMEOUT bit in the MODE register. When enabled, the entire SPI frame (first SCLK to last SCLK) must

complete within 2¹⁵CLKIN cycles otherwise the SPI will reset. This feature is provided as a means to recover

SPI synchronization for cases where CS is tied low.

The interface is full duplex, meaning that the interface is capable of transmitting data on DOUT while

simultaneously receiving data on DIN. The input frame that the host sends on DIN always begins with a

command. The first word on the output frame that the device transmits on DOUT always begins with the

response to the command that was written on the previous input frame. The number of words in a command

depends on the command provided. For most commands, there are six words in a frame. On DIN, the host

provides the command, the command CRC if input CRC is enabled or a word of zeros if input CRC is disabled,

and four additional words of zeros. Simultaneously on DOUT, the device outputs the response from the previous

frame command, four words of ADC data representing the four ADC channels, and a CRC word. Figure 8-18

illustrates a typical command frame structure.

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DRDY

CS

SCLK

DIN

Command

CRC

Command

CRC

DOUT

Hi-Z

Response

Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data

CRC

Hi-Z

Response

Channel 0 Data

Figure 8-18. Typical Communication Frame

There are some commands that require more than six words. In the case of a read register (RREG) command

where more than a single register is read, the response to the command contains the acknowledgment of the

command followed by the register contents requested, which may require a larger frame depending on how

many registers are read. See the RREG (101a aaaa annn nnnn) section for more details on the RREG

command.

In the case of a write register (WREG) command where more than a single register is written, the frame extends

to accommodate the additional data. See the WREG (011a aaaa annn nnnn) section for more details on the

WREG command.

See the Commands section for a list of all valid commands and their corresponding responses on the

ADS131M04.

Under special circumstances, a data frame can be shortened by the host. See the Short SPI Frames section for

more information about artificially shortening communication frames.

8.5.1.8 SPI Communication Words

An SPI communication frame with the ADS131M04 is made of words. Words on DIN can contain commands,

register settings during a register write, or a CRC of the input data. Words on DOUT can contain command

responses, register settings during a register read, ADC conversion data, or CRC of the output data.

Words can be 16, 24, or 32 bits. The word size is configured by the WLENGTH[1:0] bits in the MODE register.

The device defaults to a 24-bit word size. Commands, responses, CRC, and registers always contain 16 bits of

actual data. These words are always most significant bit (MSB) aligned, and therefore the least significant bits

(LSBs) are zero-padded to accommodate 24- or 32-bit word sizes. ADC conversion data are nominally 24 bits.

The ADC truncates its eight LSBs when the device is configured for 16-bit communication. There are two options

for 32-bit communication available for ADC data that are configured by the WLENGTH[1:0] bits in the MODE

register. Either the ADC data can be LSB padded with zeros or the data can be MSB sign extended.

8.5.1.9 ADC Conversion Data

The device provides conversion data for each channel at the data rate. The time when data are available relative

to DRDY asserting is determined by the channel phase calibration setting and the DRDY_SEL[1:0] bits in the

MODE register when in continuous-conversion mode. All data are available immediately following DRDY

assertion in global-chop mode. The conversion status of all channels is available as the DRDY[3:0] bits in the

STATUS register. The STATUS register content is automatically output as the response to the NULL command.

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Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The

LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the

setting of the WLENGTH[1:0] bits in the MODE register.

Data are given in binary two's complement format. Use Equation 10 to calculate the size of one code (LSB).

1 LSB = (2.4 / Gain) / 2²⁴= +FSR / 2²³

(10)

A positive full-scale input V_IN≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and a

negative full-scale input (V_IN≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at

these codes for signals that exceed full-scale.

Table 8-10 summarizes the ideal output codes for different input signals.

Table 8-10. Ideal Output Code versus Input Signal

INPUT SIGNAL,

IDEAL OUTPUT CODE

V_IN= V_AINP– V_AINN

≥ FSR (2²³– 1) / 2²³

FSR / 2²³

0

7FFFFFh

000001h

000000h

FFFFFFh

800000h

–FSR / 2²³

≤ –FSR

Figure 8-19 shows the mapping of the analog input signal to the output codes.

7FFFFFh

7FFFFEh

000001h

000000h

FFFFFFh

800001h

800000h

¼

-FS

0

FS

Input Voltage V_IN

2²³- 1

FS

2²³

Figure 8-19. Code Transition Diagram

8.5.1.9.1 Collecting Data for the First Time or After a Pause in Data Collection

Take special precaution when collecting data for the first time or when beginning to collect data again after a

pause. The internal mechanism that outputs data contains a first-in-first-out (FIFO) buffer that can store two

samples of data per channel at a time. The DRDY flag for each channel in the STATUS register remains set until

both samples for each channel are read from the device. This condition is not obvious under normal

circumstances when the host is reading each consecutive sample from the device. In that case, the samples are

cleared from the device each time new data are generated so the DRDY flag for each channel in the STATUS

register is cleared with each read. However, both slots of the FIFO are full if a sample is missed or if data are not

read for a period of time. Either strobe the SYNC/RESET pin to re-synchronize conversions and clear the FIFOs,

or quickly read two data packets when data are read for the first time or after a gap in reading data. This process

ensures predictable DRDY pin behavior. See the Synchronization section for information about the

synchronization feature. These methods do not need to be employed if each channel data was read for each

output data period from when the ADC was enabled.

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Figure 8-20 depicts an example of how to collect data after a period of the ADC running, but where no data are

being retrieved. In this instance, the SYNC/RESET pin is used to clear the internal FIFOs and realign the

ADS131M04 output data with the host.

Time where data is

not being read

DRDY

SYNC / RESET

SYNC Pulse

CS

SCLK

Hi-Z

DOUT

Data

CRC

Status

Data

CRC

Figure 8-20. Collecting Data After a Pause in Data Collection Using the SYNC/RESET Pin

Another functionally equivalent method for clearing the FIFO after a pause in collecting data is to begin by

reading two samples in quick succession. Figure 8-21 depicts this method. This example shows when the

DRDY_FMT bit in the MODE register is set to 0b indicating DRDY is a level output. There is a very narrow pulse

on DRDY immediately after the first set of data are shifted out of the device. This pulse may be too narrow for

some microcontrollers to detect. Therefore, do not rely upon this pulse but instead immediately read out the

second data set after the first data set. The host operates synchronous to the device after the second word is

read from the device.

Time where data is

not being read

Narrow DRDY Pulse

DRDY

CS

SCLK

Hi-Z

DOUT

Data

CRC

Status

Data

CRC

Status

Data

CRC

Data is read a

second time

Figure 8-21. Collecting Data After a Pause in Data Collection by Reading Data Twice

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8.5.1.10 Commands

Table 8-11 contains a list of all valid commands, a short description of their functionality, their binary command

word, and the expected response that appears in the following frame.

Table 8-11. Command Definitions

COMMAND

NULL

DESCRIPTION

COMMAND WORD

0000 0000 0000 0000

0000 0000 0001 0001

0000 0000 0010 0010

RESPONSE

No operation

STATUS register

RESET

Reset the device

1111 1111 0010 0100

0000 0000 0010 0010

STANDBY

Place the device into standby mode

Wake the device from standby mode to conversion

mode

WAKEUP

0000 0000 0011 0011

Lock the interface such that only the NULL, UNLOCK,

and RREG commands are valid

LOCK

0000 0101 0101 0101

0000 0110 0101 0101

0000 0101 0101 0101

0000 0110 0101 0101

UNLOCK

Unlock the interface after the interface is locked

dddd dddd dddd dddd

or

Read nnn nnnn plus 1 registers beginning at address a

aaaa a

RREG

WREG

101a aaaa annn nnnn

011a aaaa annn nnnn

111a aaa annn nnnn ⁽¹⁾

Write nnn nnnn plus 1 registers beginning at address a

aaaa a

010a aaaa ammm mmmm

(2)

(1) When nnn nnnn is 0, the response is the requested register data dddd dddd dddd dddd. When nnn nnnn is greater than 0, the

response begins with 111a aaaa annn nnnn, followed by the register data.

(2) In this case mmm mmmm represents the number of registers that are actually written minus one. This value may be less than nnn

nnnn in some cases.

8.5.1.10.1 NULL (0000 0000 0000 0000)

The NULL command is the no-operation command that results in no registers read or written, and the state of

the device remains unchanged. The intended use case for the NULL command is during ADC data capture. The

command response for the NULL command is the contents of the STATUS register. Any invalid command also

gives the NULL response.

8.5.1.10.2 RESET (0000 0000 0001 0001)

The RESET command resets the ADC to its register defaults. The command is latched by the device at the end

of the frame. A reset occurs immediately after the command is latched. The host must wait for t_REGACQafter

reset before communicating with the device to ensure the registers have assumed their default settings. The

device sends an acknowledgment of FF24h when the ADC is properly RESET. The device responds with 0011h

if the command word is sent but the frame is not completed and therefore the device is not reset. See the

RESET Command section for more information regarding the operation of the reset command. Figure 8-22

illustrates a properly sent RESET command frame.

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CS

SCLK

DIN

RESET

CRC

RESET command

latched here

DOUT

Hi-Z

Response

Don‘t Care

Hi-Z

Figure 8-22. RESET Command Frame

8.5.1.10.3 STANDBY (0000 0000 0010 0010)

The STANDBY command places the device in a low-power standby mode. The command is latched by the

device at the end of the frame. The device enters standby mode immediately after the command is latched. See

the Standby Mode section for more information. This command has no effect if the device is already in standby

mode.

8.5.1.10.4 WAKEUP (0000 0000 0011 0011)

The WAKEUP command returns the device to conversion mode from standby mode. This command has no

effect if the device is already in conversion mode.

8.5.1.10.5 LOCK (0000 0101 0101 0101)

The LOCK command locks the interface, preventing the device from accidentally latching unwanted commands

that can change the state of the device. When the interface is locked, the device only responds to the NULL,

RREG, and UNLOCK commands. The device continues to output conversion data even when locked.

8.5.1.10.6 UNLOCK (0000 0110 0110 0110)

The UNLOCK command unlocks the interface if previously locked by the LOCK command.

8.5.1.10.7 RREG (101a aaaa annn nnnn)

The RREG is used to read the device registers. The binary format of the command word is 101a aaaa annn

nnnn, where a aaaa a is the binary address of the register to begin reading and nnn nnnn is the unsigned binary

number of consecutive registers to read minus one. There are two cases for reading registers on the

ADS131M04. When reading a single register (nnn nnnn = 000 0000b), the device outputs the register contents in

the command response word of the following frame. If multiple registers are read using a single command (nnn

nnnn > 000 0000b), the device outputs the requested register data sequentially in order of addresses.

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8.5.1.10.7.1 Reading a Single Register

Read a single register from the device by specifying nnn nnnn as zero in the RREG command word. As with all

SPI commands on the ADS131M04, the response occurs on the output in the frame following the command.

Instead of a unique acknowledgment word, the response word is the contents of the register whose address is

specified in the command word. Figure 8-23 shows an example of reading a single register.

DRDY

CS

SCLK

DIN

RREG

CRC

Command

CRC

Register

Data

DOUT

Hi-Z

Response

Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data

CRC

Hi-Z

Channel 0 Data

Figure 8-23. Reading a Single Register

8.5.1.10.7.2 Reading Multiple Registers

Multiple registers are read from the device when nnn nnnn is specified as a number greater than zero in the

RREG command word. Like all SPI commands on the ADS131M04, the response occurs on the output in the

frame following the command. Instead of a single acknowledgment word, the response spans multiple words in

order to shift out all requested registers. Continue toggling SCLK to accommodate outputting the entire data

stream. ADC conversion data are not output in the frame following an RREG command to read multiple

registers. Figure 8-24 shows an example of reading multiple registers.

CS

SCLK

DIN

RREG

CRC

Command

CRC

RREG

ack

1

^stregister‘s

data

2

^ndregister‘s

data

N-1^thregister‘s

data

N

^thregister‘s

data

DOUT

Hi-Z

Response

Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data

CRC

Hi-Z

CRC

Hi-Z

Figure 8-24. Reading Multiple Registers

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8.5.1.10.8 WREG (011a aaaa annn nnnn)

The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the

command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing

and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be

written immediately following the command word. Write the intended contents of each register into individual

words, MSB aligned.

If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as they

are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a

register. An input CRC error during a WREG command sets the CRC_ERR bit in the STATUS register.

The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map

address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them.

The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm

where mmm mmmm is the number of registers actually written minus one. This number can be checked by the

host against nnn nnnn to ensure the expected number of registers are written.

Figure 8-25 shows a typical WREG sequence. In this example, the number of registers to write is larger than the

number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC

word. Ensure all of the ADC data and output CRC are shifted out during each transaction where new data are

available. Therefore, the frame must be extended beyond the number of words required to send the register data

in some cases.

DRDY

CS

SCLK

1

^stregister‘s

data

2

^ndregister‘s

data

3

^rdregister‘s

data

4

^thregister‘s

data

5

^thregister‘s

data

6

^thregister‘s

data

N-1^thregister‘s

data

N

^thregister‘s

data

DIN

WREG

CRC

Command

CRC

DOUT

Hi-Z

Response

Channel 0 Data Channel 1 Data Channel 2 Data Channel 3 Data

CRC

Don‘t Care

Hi-Z

Response

Channel 0 Data

Figure 8-25. Writing Registers

8.5.1.11 Short SPI Frames

The SPI frame can be shortened to only send commands and receive responses if the ADCs are disabled and

no ADC data are being output by the device. Read out all of the expected output data words from each sample

period if the ADCs are enabled. Reading all of the data output with each frame ensures predictable DRDY pin

behavior. If reading out all the data on each output data period is not feasible, see the Collecting Data for the

First Time or After a Pause in Data Collection section on how to begin reading data again after a pause from

when the ADCs were last enabled.

A short frame is not possible when using the RESET command. A full frame must be provided for a device reset

to take place when providing the RESET command.

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8.5.2 Synchronization

Synchronization can be performed by the host to ensure the ADC conversions are synchronized to an external

event. For example, synchronization can realign the data capture to the expected timing of the host if a glitch on

the clock causes the host and device to become out of synchronization.

Provide a negative pulse on the SYNC/RESET pin with a duration less than t_w(RSL)but greater than a CLKIN

period to trigger synchronization. The device internally compares the leading negative edge of the pulse to its

internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin if

configured to assert with a phase calibration setting of 0b. If the negative edge on SYNC/RESET aligns with the

internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If there is

misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse.

Conversions are immediately restarted when the SYNC/RESET pin is toggled in global-chop mode.

The phase calibration settings on all channels are retained during synchronization. Thus, channels with non-zero

phase calibration settings generate conversion results less than a data rate period after the synchronization

event occurs. However, the results can be corrupted and are not settled until the respective channels have at

least three conversion cycles for the sinc³filter to settle.

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8.6 ADS131M04 Registers

Table 8-12 lists the ADS131M04 registers. All register offset addresses not listed in Table 8-12 should be

considered as reserved locations and the register contents should not be modified.

Table 8-12. Register Map

BIT 15

BIT 7

BIT 14

BIT 13

BIT 12

BIT 11

BIT 3

BIT 10

BIT 2

BIT 9

BIT 1

BIT 8

BIT 0

RESET

VALUE

ADDRESS

REGISTER

BIT 6

BIT 5

BIT 4

DEVICE SETTINGS AND INDICATORS (Read-Only Registers)

0

1

0

CHANCNT[3:0]

00h

01h

ID

24xxh

0500h

RESERVED

LOCK

0

F_RESYNC

0

REG_MAP

0

CRC_ERR

0

CRC_TYPE

DRDY3

RESET

DRDY2

WLENGTH[1:0]

STATUS

DRDY1

DRDY0

GLOBAL SETTINGS ACROSS CHANNELS

0

REGCRC_EN

RX_CRC_EN

TIMEOUT

0

CRC_TYPE

RESET

WLENGTH[1:0]

02h

03h

04h

06h

07h

08h

MODE

CLOCK

0510h

0F0Eh

0000h

0600h

0000h

0

DRDY_SEL[1:0]

DRDY_HiZ

CH1_EN

DRDY_FMT

CH0_EN

0

CH3_EN

CH2_EN

0

OSR

PWR

0

PGAGAIN3[2:0]

PGAGAIN1[2:0]

0

PGAGAIN2[2:0]

PGAGAIN0[2:0]

GAIN

0

GC_DLY[3:0]

CD_LEN[2:0]

GC_EN

CD_EN

CFG

CD_ALLCH

CD_NUM[2:0]

CD_TH_MSB[15:8]

THRSHLD_MSB

THRSHLD_LSB

CD_TH_MSB[7:0]

CD_TH_LSB[7:0]

0

DCBLOCK[3:0]

CHANNEL-SPECIFIC SETTINGS

PHASE0[9:2]

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

CH0_CFG

0000h

8000h

0000h

8000h

0000h

8000h

0000h

PHASE0[1:0]

0

DCBLK0_DIS0

MUX0[1:0]

OCAL0_MSB[15:8]

OCAL0_MSB[7:0]

OCAL0_LSB[7:0]

CH0_OCAL_MSB

CH0_OCAL_LSB

CH0_GCAL_MSB

CH0_GCAL_LSB

CH1_CFG

0

GCAL0_MSB[15:8]

GCAL0_MSB[7:0]

GCAL0_LSB[7:0]

0

PHASE1[9:2]

PHASE1[1:0]

0

DCBLK1_DIS0

MUX1[1:0]

OCAL1_MSB[15:8]

OCAL1_MSB[7:0]

OCAL1_LSB[7:0]

CH1_OCAL_MSB

CH1_OCAL_LSB

CH1_GCAL_MSB

CH1_GCAL_LSB

CH2_CFG

0

GCAL1_MSB[15:8]

GCAL1_MSB[7:0]

GCAL1_LSB[7:0]

0

PHASE2[9:2]

PHASE2[1:0]

0

DCBLK2_DIS0

MUX2[1:0]

OCAL2_MSB[15:8]

OCAL2_MSB[7:0]

OCAL2_LSB[7:0]

CH2_OCAL_MSB

CH2_OCAL_LSB

CH2_GCAL_MSB

CH2_GCAL_LSB

0

GCAL2_MSB[15:8]

GCAL2_MSB[7:0]

GCAL2_LSB[7:0]

0

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Table 8-12. Register Map (continued)

BIT 15

BIT 7

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 2

BIT 9

BIT 1

BIT 8

BIT 0

RESET

VALUE

ADDRESS

REGISTER

BIT 6

BIT 5

BIT 4

BIT 3

PHASE3[9:2]

18h

CH3_CFG

0000h

8000h

0000h

PHASE3[1:0]

0

DCBLK3_DIS0

MUX3[1:0]

OCAL3_MSB[15:8]

OCAL3_MSB[7:0]

OCAL3_LSB[7:0]

19h

1Ah

1Bh

1Ch

CH3_OCAL_MSB

CH3_OCAL_LSB

CH3_GCAL_MSB

CH3_GCAL_LSB

0

GCAL3_MSB[15:8]

GCAL3_MSB[7:0]

GCAL3_LSB[7:0]

0

REGISTER MAP CRC AND RESERVED REGISTERS

REG_CRC[15:8]

REG_CRC[7:0]

3Eh

3Fh

REGMAP_CRC

RESERVED

0000h

0

Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for

access types in this section.

Table 8-13. Access Type Codes

Access Type

Code

Description

Read Type

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default value

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8.6.1 ID Register (Address = 0h) [reset = 24xxh]

The ID register is shown in Figure 8-26 and described in Table 8-14.

Return to the Summary Table.

Figure 8-26. ID Register

15

14

13

12

11

10

2

9

1

8

0

RESERVED

R-0010b

CHANCNT

R-0100b

7

6

5

4

3

RESERVED

R-xxxxxxxxb

Table 8-14. ID Register Field Descriptions

Bit

Field

Type

Reset

Description

15:12

RESERVED

R

0010b

Reserved

Always reads 0010b

11:8

7:0

CHANCNT

R

0100b

Channel count Always reads 0100b

RESERVED

xxxxxxxxb

Reserved

Values are subject to change without notice.

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8.6.2 STATUS Register (Address = 1h) [reset = 0500h]

The STATUS register is shown in Figure 8-27 and described in Table 8-15.

Return to the Summary Table.

Figure 8-27. STATUS Register

15

14

13

12

11

10

9

8

0

LOCK

R-0b

F_RESYNC

R-0b

REG_MAP

R-0b

CRC_ERR

R-0b

CRC_TYPE

R-0b

RESET

R-1b

WLENGTH

R-01b

7

6

5

4

3

2

1

RESERVED

R-0000b

DRDY3

R-0b

DRDY2

R-0b

DRDY1

R-0b

DRDY0

R-0b

Table 8-15. STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

15

LOCK

R

0b

SPI interface lock indicator

0b = Unlocked (default)

1b = Locked

14

F_RESYNC

R

0b

ADC resynchronization indicator.

This bit is set each time the ADC resynchronizes.

0b = No resynchronization (default)

1b = Resynchronization occurred

13

12

11

REG_MAP

CRC_ERR

CRC_TYPE

RESET

R

0b

1b

01b

Register map CRC fault indicator

0b = No change in the register map CRC (default)

1b = Register map CRC changed

SPI input CRC error indicator

0b = No CRC error (default)

1b = Input CRC error occured

CRC type

0b = 16 bit CCITT (default)

1b = 16 bit ANSI

10

9:8

Reset status

0b = Not reset

1b = Reset occurred (default)

WLENGTH

Data word length

00b = 16 bit

01b = 24 bits (default)

10b = 32 bits; zero padding

11b = 32 bits; sign extension for 24-bit ADC data

7:4

3

RESERVED

DRDY3

R

0000b

0b

Reserved

Always reads 0000b

Channel 3 ADC data available indicator

0b = No new data available

1b = New data are available

2

DRDY2

R

0b

Channel 2 ADC data available indicator

0b = No new data available

1b = New data are available

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Table 8-15. STATUS Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

DRDY1

R

0b

Channel 1 ADC data available indicator

0b = No new data available

1b = New data are available

0

DRDY0

R

0b

Channel 0 ADC data available indicator

0b = No new data available

1b = New data are available

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8.6.3 MODE Register (Address = 2h) [reset = 0510h]

The MODE register is shown in Figure 8-28 and described in Table 8-16.

Return to the Summary Table.

Figure 8-28. MODE Register

15

14

13

12

11

10

9

1

8

0

RESERVED

R/W-00b

REG_CRC_EN RX_CRC_EN

CRC_TYPE

R/W-0b

RESET

R/W-1b

WLENGTH

R/W-01b

R/W-0b

5

R/W-0b

7

6

4

3

2

RESERVED

R/W-000b

TIMEOUT

R/W-1b

DRDY_SEL

R/W-00b

DRDY_HiZ

R/W-0b

DRDY_FMT

R/W-0b

Table 8-16. MODE Register Field Descriptions

Bit

Field

Type

Reset

Description

15:14

RESERVED

R/W

00b

Reserved

Always write 00b

13

REG_CRC_EN

R/W

0b

1b

Register map CRC enable

0b = Register CRC disabled (default)

1b = Register CRC enabled

12

11

10

RX_CRC_EN

CRC_TYPE

RESET

SPI input CRC enable

0b = Disabled (default)

1b = Enabled

SPI input and output, register map CRC type

0b = 16-bit CCITT (default)

1b = 16-bit ANSI

Reset

Write 0b to clear this bit in the STATUS register

0b = No reset

1b = Reset occurred (default by definition)

9:8

WLENGTH

R/W

01b

Data word length selection

00b = 16 bits

01b = 24 bits (default)

10b = 32 bits; LSB zero padding

11b = 32 bits; MSB sign extension

7:5

4

RESERVED

TIMEOUT

R/W

000b

1b

Reserved

Always write 000b

SPI Timeout enable

0b = Disabled

1b = Enabled (default)

3:2

DRDY_SEL

R/W

00b

DRDY pin signal source selection

00b = Most lagging enabled channel (default)

01b = Logic OR of all the enabled channels

10b = Most leading enabled channel

11b = Most leading enabled channel

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Table 8-16. MODE Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

DRDY_HiZ

R/W

0b

DRDY pin state when conversion data are not available

0b = Logic high (default)

1b = High impedance

0

DRDY_FMT

R/W

0b

DRDY signal format when conversion data are available

0b = Logic low (default)

1b = Low pulse with a fixed duration

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8.6.4 CLOCK Register (Address = 3h) [reset = 0F0Eh]

The CLOCK register is shown in Figure 8-29 and described in Table 8-17.

Return to the Summary Table.

Figure 8-29. CLOCK Register

15

7

14

6

13

12

11

CH3_EN

R/W-1b

3

10

CH2_EN

R/W-1b

2

9

8

RESERVED

R-0000b

CH1_EN

R/W-1b

1

CH0_EN

R/W-1b

0

5

4

RESERVED

R/W-00b

RESERVED

R/W-0b

OSR

PWR

R/W-011b

R/W-10b

Table 8-17. CLOCK Register Field Descriptions

Bit

Field

Type

Reset

Description

15:12

RESERVED

R

0000b

Reserved

Always reads 0000b

11

CH3_EN

R/W

1b

Channel 3 ADC enable

0b = Disabled

1b = Enabled (default)

10

9

CH2_EN

CH1_EN

CH0_EN

Channel 2 ADC enable

0b = Disabled

1b = Enabled (default)

Channel 1 ADC enable

0b = Disabled

1b = Enabled (default)

8

Channel 0 ADC enable

0b = Disabled

1b = Enabled (default)

7:6

5

RESERVED

OSR

R/W

00b

0b

Reserved

Always write 00b

Reserved

Always write 0b

4:2

011b

Modulator oversampling ratio selection

000b = 128

001b = 256

010b = 512

011b = 1024 (default)

100b = 2048

101b = 4096

110b = 8192

111b = 16256

1:0

PWR

R/W

10b

Power mode selection

00b = Very-low-power

01b = Low-power

10b = High-resolution (default)

11b = High-resolution

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8.6.5 GAIN1 Register (Address = 4h) [reset = 0000h]

The GAIN1 register is shown in Figure 8-30 and described in Table 8-18.

Return to the Summary Table.

Figure 8-30. GAIN1 Register

15

RESERVED

R/W-0b

7

14

6

13

12

11

10

2

9

8

0

PGAGAIN3

R/W-000b

5

RESERVED

R/W-0b

3

PGAGAIN2

R/W-000b

1

4

RESERVED

R/W-0b

PGAGAIN1

R/W-000b

RESERVED

R/W-0b

PGAGAIN0

R/W-000b

Table 8-18. GAIN1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

RESERVED

R/W

0b

Reserved

Always write 0b

14:12

PGAGAIN3

R/W

000b

PGA gain selection for channel 3

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

11

RESERVED

PGAGAIN2

R/W

0b

Reserved

Always write 0b

10:8

000b

PGA gain selection for channel 2

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

7

RESERVED

PGAGAIN1

R/W

0b

Reserved

Always write 0b

6:4

000b

PGA gain selection for channel 1

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

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Table 8-18. GAIN1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

RESERVED

R/W

0b

Reserved

Always write 0b

2:0

PGAGAIN0

R/W

000b

PGA gain selection for channel 0

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = G64

111b = 128

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8.6.6 RESERVED Register (Address = 5h) [reset = 0000h]

The RESERVED register is shown in Figure 8-31 and described in Table 8-19.

Return to the Summary Table.

Figure 8-31. RESERVED Register

15

14

13

12

11

10

9

1

8

0

RESERVED

R/W-00000000b

7

6

5

4

3

2

RESERVED

R/W-00000000b

Table 8-19. RESERVED Register Field Descriptions

Bit

15:0

Field

RESERVED

Type

Reset

Description

R/W

0000000000 Reserved

000000b

Always write 0000000000000000b

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8.6.7 CFG Register (Address = 6h) [reset = 0600h]

The CFG register is shown in Figure 8-32 and described in Table 8-20.

Return to the Summary Table.

Figure 8-32. CFG Register

15

14

13

12

11

10

2

9

1

8

RESERVED

R/W-000b

GC_DLY

GC_EN

R/W-0b

R/W-0011b

7

6

5

4

3

0

CD_ALLCH

R/W-0b

CD_NUM

R/W-000b

CD_LEN

CD_EN

R/W-0b

R/W-000b

Table 8-20. CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:13

RESERVED

R/W

000b

Reserved

Always write 000b

12:9

GC_DLY

R/W

0011b

Global-chop delay selection

Delay in modulator clock periods before measurement begins

0000b = 2

0001b = 4

0010b = 8

0011b = 16 (default)

0100b = 32

0101b = 64

0110b = 128

0111b = 256

1000b = 512

1001b = 1024

1010b = 2048

1011b = 4096

1100b = 8192

1101b = 16384

1110b = 32768

1111b = 65536

8

7

GC_EN

R/W

0b

Global-chop enable

0b = Disabled (default)

1b = Enabled

CD_ALLCH

Current-detect channel selection

Channels required to trigger current-detect

0b = Any channel (default)

1b = All channels

56

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Table 8-20. CFG Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

6:4

CD_NUM

R/W

000b

Number of current-detect exceeded thresholds selection

Number of current-detect exceeded thresholds to trigger a detection

000b = 1 (default)

001b = 2

010b = 4

011b = 8

100b = 16

101b = 32

110b = 64

111b = 128

3:1

CD_LEN

R/W

000b

Current-detect measurement length selection

Current-detect measurement length in conversion periods

000b = 128 (default)

001b = 256

010b = 512

011b = 768

100b = 1280

101b = 1792

110b = 2560

111b = 3584

0

CD_EN

R/W

0b

Current-detect mode enable

0b = Disabled (default)

1b = Enabled

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8.6.8 THRSHLD_MSB Register (Address = 7h) [reset = 0000h]

The THRSHLD_MSB register is shown in Figure 8-33 and described in Table 8-21.

Return to the Summary Table.

Figure 8-33. THRSHLD_MSB Register

15

14

13

12

11

10

9

1

8

0

CD_TH_MSB

R/W-00000000b

7

6

5

4

3

2

CD_TH_MSB

R/W-00000000b

Table 8-21. THRSHLD_MSB Register Field Descriptions

Bit

15:0

Field

CD_TH_MSB

Type

Reset

Description

R/W

0000000000 Current-detect mode threshold MSB

000000b

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8.6.9 THRSHLD_LSB Register (Address = 8h) [reset = 0000h]

The THRSHLD_LSB register is shown in Figure 8-34 and described in Table 8-22.

Return to the Summary Table.

Figure 8-34. THRSHLD_LSB Register

15

14

13

12

11

10

9

1

8

0

CD_TH_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-0000b

DCBLOCK

R/W-0000b

Table 8-22. THRSHLD_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:4

CD_TH_LSB

RESERVED

00000000b Current-detect mode threshold LSB

0000b

Reserved

Always write 0000b

3:0

DCBLOCK

R/W

DC block filter setting, see Table 8-4for details.

Value of coefficient a

0000b = DC block filter disabled

0001b = 1/4

0010b = 1/8

0011b = 1/16

0100b = 1/32

0101b = 1/64

0110b = 1/128

0111b = 1/256

1000b = 1/512

1001b = 1/1024

1010b = 1/2048

1011b = 1/4096

1100b = 1/8192

1101b = 1/16384

1110b = 1/32768

1111b = 1/65536

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8.6.10 CH0_CFG Register (Address = 9h) [reset = 0000h]

The CH0_CFG register is shown in Figure 8-35 and described in Table 8-23.

Return to the Summary Table.

Figure 8-35. CH0_CFG Register

15

14

13

12

11

10

9

1

8

0

PHASE0

R/W-0000000000b

7

6

5

4

3

2

PHASE0

R/W-0000000000b

RESERVED

R-000b

DCBLK0_DIS0

R/W-0b

MUX0

R/W-00b

Table 8-23. CH0_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:6

PHASE0

R/W

0000000000 Channel 0 phase delay

b

Phase delay in modulator clock cycles provided in two's complement

format. See Table 8-5 for details.

5:3

2

RESERVED

R

000b

0b

Reserved

Always write 000b

DCBLK0_DIS0

R/W

DC block filter for channel 0 disable

0b = Controlled by DCBLOCK[3:0] (detault)

1b = Disabled for this channel

1:0

MUX0

R/W

00b

Channel 0 input selection

00b = AIN0P and AIN0N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.11 CH0_OCAL_MSB Register (Address = Ah) [reset = 0000h]

The CH0_OCAL_MSB register is shown in Figure 8-36 and described in Table 8-24.

Return to the Summary Table.

Figure 8-36. CH0_OCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

OCAL0_MSB

R/W-00000000b

7

6

5

4

3

2

OCAL0_MSB

R/W-00000000b

Table 8-24. CH0_OCAL_MSB Register Field Descriptions

Bit

15:0

Field

OCAL0_MSB

Type

Reset

Description

R/W

0000000000 Channel 0 offset calibration register bits [23:8]

000000b

8.6.12 CH0_OCAL_LSB Register (Address = Bh) [reset = 0000h]

The CH0_OCAL_LSB register is shown in Figure 8-37 and described in Table 8-25.

Return to the Summary Table.

Figure 8-37. CH0_OCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

OCAL0_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-25. CH0_OCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

OCAL0_LSB

RESERVED

00000000b Channel 0 offset calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.13 CH0_GCAL_MSB Register (Address = Ch) [reset = 8000h]

The CH0_GCAL_MSB register is shown in Figure 8-38 and described in Table 8-26.

Return to the Summary Table.

Figure 8-38. CH0_GCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

GCAL0_MSB

R/W-10000000b

7

6

5

4

3

2

GCAL0_MSB

R/W-00000000b

Table 8-26. CH0_GCAL_MSB Register Field Descriptions

Bit

15:0

Field

GCAL0_MSB

Type

Reset

Description

R/W

1000000000 Channel 0 gain calibration register bits [23:8]

000000b

8.6.14 CH0_GCAL_LSB Register (Address = Dh) [reset = 0000h]

The CH0_GCAL_LSB register is shown in Figure 8-39 and described in Table 8-27.

Return to the Summary Table.

Figure 8-39. CH0_GCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

GCAL0_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-27. CH0_GCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

GCAL0_LSB

RESERVED

00000000b Channel 0 gain calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.15 CH1_CFG Register (Address = Eh) [reset = 0000h]

The CH1_CFG register is shown in Figure 8-40 and described in Table 8-28.

Return to the Summary Table.

Figure 8-40. CH1_CFG Register

15

14

13

12

11

10

9

1

8

0

PHASE1

R/W-0000000000b

7

6

5

4

3

2

PHASE1

R/W-0000000000b

RESERVED

R-000b

DCBLK1_DIS0

R/W-0b

MUX1

R/W-00b

Table 8-28. CH1_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:6

PHASE1

R/W

0000000000 Channel 1 phase delay

b

Phase delay in modulator clock cycles provided in two's complement

format. See Table 8-5 for details.

5:3

2

RESERVED

R

000b

0b

Reserved

Always reads 000b

DCBLK1_DIS0

R/W

DC block filter for channel 1 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0

MUX1

R/W

00b

Channel 1 input selection

00b = AIN1P and AIN1N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.16 CH1_OCAL_MSB Register (Address = Fh) [reset = 0000h]

The CH1_OCAL_MSB register is shown in Figure 8-41 and described in Table 8-29.

Return to the Summary Table.

Figure 8-41. CH1_OCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

OCAL1_MSB

R/W-00000000b

7

6

5

4

3

2

OCAL1_MSB

R/W-00000000b

Table 8-29. CH1_OCAL_MSB Register Field Descriptions

Bit

15:0

Field

OCAL1_MSB

Type

Reset

Description

R/W

0000000000 Channel 1 offset calibration register bits [23:8]

000000b

8.6.17 CH1_OCAL_LSB Register (Address = 10h) [reset = 0000h]

The CH1_OCAL_LSB register is shown in Figure 8-42 and described in Table 8-30.

Return to the Summary Table.

Figure 8-42. CH1_OCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

OCAL1_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-30. CH1_OCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

OCAL1_LSB

RESERVED

00000000b Channel 1 offset calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.18 CH1_GCAL_MSB Register (Address = 11h) [reset = 8000h]

The CH1_GCAL_MSB register is shown in Figure 8-43 and described in Table 8-31.

Return to the Summary Table.

Figure 8-43. CH1_GCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

GCAL1_MSB

R/W-10000000b

7

6

5

4

3

2

GCAL1_MSB

R/W-00000000b

Table 8-31. CH1_GCAL_MSB Register Field Descriptions

Bit

15:0

Field

GCAL1_MSB

Type

Reset

Description

R/W

1000000000 Channel 1 gain calibration register bits [23:8]

000000b

8.6.19 CH1_GCAL_LSB Register (Address = 12h) [reset = 0000h]

The CH1_GCAL_LSB register is shown in Figure 8-44 and described in Table 8-32.

Return to the Summary Table.

Figure 8-44. CH1_GCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

GCAL1_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-32. CH1_GCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

GCAL1_LSB

RESERVED

00000000b Channel 1 gain calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.20 CH2_CFG Register (Address = 13h) [reset = 0000h]

The CH2_CFG register is shown in Figure 8-45 and described in Table 8-33.

Return to the Summary Table.

Figure 8-45. CH2_CFG Register

15

14

13

12

11

10

9

1

8

0

PHASE2

R/W-0000000000b

7

6

5

4

3

2

PHASE2

R/W-0000000000b

RESERVED

R-000b

DCBLK2_DIS0

R/W-0b

MUX2

R/W-00b

Table 8-33. CH2_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:6

PHASE2

R/W

0000000000 Channel 2 phase delay

b

Phase delay in modulator clock cycles provided in two's complement

format. See Table 8-5 for details.

5:3

2

RESERVED

R

000b

0b

Reserved

Always reads 000b

DCBLK2_DIS0

R/W

DC block filter for channel 2 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0

MUX2

R/W

00b

Channel 2 input selection

00b = AIN2P and AIN2N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.21 CH2_OCAL_MSB Register (Address = 14h) [reset = 0000h]

The CH2_OCAL_MSB register is shown in Figure 8-46 and described in Table 8-34.

Return to the Summary Table.

Figure 8-46. CH2_OCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

OCAL2_MSB

R/W-00000000b

7

6

5

4

3

2

OCAL2_MSB

R/W-00000000b

Table 8-34. CH2_OCAL_MSB Register Field Descriptions

Bit

15:0

Field

OCAL2_MSB

Type

Reset

Description

R/W

0000000000 Channel 2 offset calibration register bits [23:8]

000000b

8.6.22 CH2_OCAL_LSB Register (Address = 15h) [reset = 0000h]

The CH2_OCAL_LSB register is shown in Figure 8-47 and described in Table 8-35.

Return to the Summary Table.

Figure 8-47. CH2_OCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

OCAL2_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-35. CH2_OCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

OCAL2_LSB

RESERVED

00000000b Channel 2 offset calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.23 CH2_GCAL_MSB Register (Address = 16h) [reset = 8000h]

The CH2_GCAL_MSB register is shown in Figure 8-48 and described in Table 8-36.

Return to the Summary Table.

Figure 8-48. CH2_GCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

GCAL2_MSB

R/W-10000000b

7

6

5

4

3

2

GCAL2_MSB

R/W-00000000b

Table 8-36. CH2_GCAL_MSB Register Field Descriptions

Bit

15:0

Field

GCAL2_MSB

Type

Reset

Description

R/W

1000000000 Channel 2 gain calibration register bits [23:8]

000000b

8.6.24 CH2_GCAL_LSB Register (Address = 17h) [reset = 0000h]

The CH2_GCAL_LSB register is shown in Figure 8-49 and described in Table 8-37.

Return to the Summary Table.

Figure 8-49. CH2_GCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

GCAL2_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-37. CH2_GCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

GCAL2_LSB

RESERVED

00000000b Channel 2 gain calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.25 CH3_CFG Register (Address = 18h) [reset = 0000h]

The CH3_CFG register is shown in Figure 8-50 and described in Table 8-38.

Return to the Summary Table.

Figure 8-50. CH3_CFG Register

15

14

13

12

11

10

9

1

8

0

PHASE3

R/W-0000000000b

7

6

5

4

3

2

PHASE3

R/W-0000000000b

RESERVED

R-000b

DCBLK3_DIS0

R/W-0b

MUX3

R/W-00b

Table 8-38. CH3_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

15:6

PHASE3

R/W

0000000000 Channel 3 phase delay

b

Phase delay in modulator clock cycles provided in two's complement

format. See Table 8-5 for details.

5:3

2

RESERVED

R

000b

0b

Reserved

Always reads 000b

DCBLK3_DIS0

R/W

DC block filter for channel 3 disable

0b = Controlled by DCBLOCK[3:0] (default)

1b = Disabled for this channel

1:0

MUX3

R/W

00b

Channel 3 input selection

00b = AIN3P and AIN3N (default)

01b = ADC inputs shorted

10b = Positive DC test signal

11b = Negative DC test signal

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8.6.26 CH3_OCAL_MSB Register (Address = 19h) [reset = 0000h]

The CH3_OCAL_MSB register is shown in Figure 8-51 and described in Table 8-39.

Return to the Summary Table.

Figure 8-51. CH3_OCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

OCAL3_MSB

R/W-00000000b

7

6

5

4

3

2

OCAL3_MSB

R/W-00000000b

Table 8-39. CH3_OCAL_MSB Register Field Descriptions

Bit

15:0

Field

OCAL3_MSB

Type

Reset

Description

R/W

0000000000 Channel 3 offset calibration register bits [23:8]

000000b

8.6.27 CH3_OCAL_LSB Register (Address = 1Ah) [reset = 0000h]

The CH3_OCAL_LSB register is shown in Figure 8-52 and described in Table 8-40.

Return to the Summary Table.

Figure 8-52. CH3_OCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

OCAL3_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-40. CH3_OCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

OCAL3_LSB

RESERVED

00000000b Channel 3 offset calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.28 CH3_GCAL_MSB Register (Address = 1Bh) [reset = 8000h]

The CH3_GCAL_MSB register is shown in Figure 8-53 and described in Table 8-41.

Return to the Summary Table.

Figure 8-53. CH3_GCAL_MSB Register

15

14

13

12

11

10

9

1

8

0

GCAL3_MSB

R/W-10000000b

7

6

5

4

3

2

GCAL3_MSB

R/W-00000000b

Table 8-41. CH3_GCAL_MSB Register Field Descriptions

Bit

15:0

Field

GCAL3_MSB

Type

Reset

Description

R/W

1000000000 Channel 3 gain calibration register bits [23:8]

000000b

8.6.29 CH3_GCAL_LSB Register (Address = 1Ch) [reset = 0000h]

The CH3_GCAL_LSB register is shown in Figure 8-54 and described in Table 8-42.

Return to the Summary Table.

Figure 8-54. CH3_GCAL_LSB Register

15

14

13

12

11

10

9

1

8

0

GCAL3_LSB

R/W-00000000b

7

6

5

4

3

2

RESERVED

R-00000000b

Table 8-42. CH3_GCAL_LSB Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

15:8

7:0

GCAL3_LSB

RESERVED

00000000b Channel 3 gain calibration register bits [7:0]

00000000b Reserved

Always reads 00000000b

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8.6.30 REGMAP_CRC Register (Address = 3Eh) [reset = 0000h]

The REGMAP_CRC register is shown in Figure 8-55 and described in Table 8-43.

Return to the Summary Table.

Figure 8-55. REGMAP_CRC Register

15

14

13

12

11

10

9

1

8

0

REG_CRC

R-0000000000000000b

7

6

5

4

3

2

REG_CRC

R-0000000000000000b

Table 8-43. REGMAP_CRC Register Field Descriptions

Bit

15:0

Field

REG_CRC

Type

Reset

Description

R

0000000000 Register map CRC

000000b

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8.6.31 RESERVED Register (Address = 3Fh) [reset = 0000h]

The RESERVED register is shown in Figure 8-56 and described in Table 8-44.

Return to the Summary Table.

Figure 8-56. RESERVED Register

15

14

13

12

11

10

9

1

8

0

RESERVED

R/W-00000000b

7

6

5

4

3

2

RESERVED

R/W-00000000b

Table 8-44. RESERVED Register Field Descriptions

Bit

15:0

Field

RESERVED

Type

Reset

Description

R/W

0000000000 Reserved,

000000b

Always write 0000000000000000b

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Unused Inputs and Outputs

Leave any unused analog inputs floating or connect them to AGND.

Do not float unused digital inputs because excessive power-supply leakage current can result. Tie all unused

digital inputs to the appropriate levels, DVDD or DGND. Leave the DRDY pin unconnected or connect it to

DVDD using a weak pullup resistor if unused.

9.1.2 Antialiasing

An analog low-pass filter is required in front of each of the channel inputs to prevent out-of-band noise and

interferers from coupling into the band of interest. Because the ADS131M04 is a delta-sigma ADC, the

integrated digital filter provides substantial attenuation for frequencies outside of the band of interest up to the

frequencies adjacent to f_MOD. Therefore, a single-order RC filter provides sufficient antialiasing protection in the

vast majority of applications.

Choosing the values of the resistor and capacitor depends on the desired cutoff frequency, limiting source

impedance for the ADC inputs, and providing enough instantaneous charge to the ADC input sampling circuit

through the filter capacitor. Figure 9-1 shows the recommended filter component values. These

recommendations are sufficient for CLKIN frequencies between 2 MHz and 8.2 MHz.

1 kꢀ

To ADC

Inputs

10 nF

1 kꢀ

Figure 9-1. Recommended Antialiasing Circuitry

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9.1.3 Minimum Interface Connections

Figure 9-2 depicts how the ADS131M04 can be configured for the minimum number of interface pins. This

configuration is useful when using data isolation to minimize the number of isolation channels required or when

the microcontroller (MCU) pins are limited.

The CLKIN pin requires an LVCMOS clock that can be either generated by the MCU or created using a local

LVCMOS output device. Tie the SYNC/RESET pin to DVDD in hardware if unused. The DRDY pin can be left

floating if unused. Connect either SYNC/RESET or DRDY to the MCU to ensure the MCU stays synchronized to

ADC conversions. If the MCU provides CLKIN, the CLKIN periods can be counted to determine the sample

period rather than forcing synchronization using the SYNC/RESET pin or monitoring the DRDY pin.

Synchronization cannot be regained if a bit error occurs on the clock and samples can be missed if the SYNC/

RESET or DRDY pins are not used. CS can be tied low in hardware if the ADS131M04 is the only device on the

SPI bus. Ensure the data input and output CRC are enabled and are used to guard against faulty register reads

and writes if CS is tied low permanently.

Local

Oscillator

DVDD

OR

CLKIN

SYNC/RESET

DRDY

CLKOUT

GPIO

CS

OR

Device

MCU

CS

SCLK

DIN

OR

SCLK

MOSI

MISO

DOUT

DGND

Figure 9-2. Minimum Connections Required to Operate the ADS131M04

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9.1.4 Multiple Device Configuration

Multiple ADS131M04 devices can be arranged to capture all signals simultaneously. The same clock must be

provided to all devices and the SYNC/RESET pins must be strobed simultaneously at least one time to align the

sample periods internally between devices. The phase settings of each device can be changed uniquely, but the

host must take care to record which channel in the group of devices represents the zero phase.

The devices can also share the SPI bus where only the CS pins for each device are unique. Each device can be

addressed sequentially by asserting CS for the device that the host wishes to communicate with. The DOUT pin

remains high impedance when the CS pin is high, allowing the DOUT lines to be shared between devices as

long as no two devices sharing the bus simultaneously have their CS pins low. Figure 9-3 shows multiple

devices configured for simultaneous data acquisition while sharing the SPI bus.

Monitoring the DRDY output of only one of the devices is sufficient because all devices convert simultaneously.

Device 1

SYNC/RESET

CLKIN

DRDY

SCLK

GPIO

CLKOUT

IRQ

SCLK

MOSI

MISO

CS1

MCU

DIN

DOUT

CS

CS2

CSn

Device 2

SYNC/RESET

CLKIN

DRDY

SCLK

DIN

DOUT

CS

Device n

SYNC/RESET

CLKIN

DRDY

SCLK

DIN

DOUT

CS

Figure 9-3. Multiple Device Configuration

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9.1.5 Power Metrology Applications

Each channel of the ADS131M04 is identical, giving designers the flexibility to sense voltage or current with any

channel. Simultaneous sampling allows the application to calculate instantaneous power for any simultaneous

voltage and current measurement. This section provides several diagrams depicting the common energy

metrology configurations that can be used with the ADS131M04. A Rogowski coil can alternatively be used to

sense current in the following examples wherever a CT is used. The integration to determine the current flowing

through the Rogowski coil is done digitally if that modification is made. RC antialiasing filters are not shown in

the following diagrams for simplicity, but are recommended for all channels.

Figure 9-4 shows a two-phase (or split phase) metrology front-end that uses current transformers (CTs) to

measure the current on two live phases and two resistor voltage dividers to measure the voltage between the

live phases and neutral. Figure 9-5 shows a configuration similar to Figure 9-4, but with the voltage measured

between the phases and the neutral current measured directly with a CT.

Load

VDD

AVDD

AIN0N

AVDD

AIN0N

AIN0P

AIN1P

AIN0P

AIN1P

AIN1N

AIN2N

AIN1N

AIN2N

ADS131M04

AIN2P

AIN3P

AIN2P

AIN3P

AIN3N

AGND

AIN3N

AGND

Phase

Neutral

Phase

Neutral

Phase

Figure 9-4. Two-Phase CTs for Live Currents, With

Voltages Measured to Neutral

Figure 9-5. Two-Phase CTs for Live and Neutral

Currents, With Voltages Measured Between

Phases

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Figure 9-6 shows a single phase configuration where live and neutral currents are monitored using CTs, the live

phase voltage is measured using a voltage divider, and the final channel is used for an auxiliary measurement.

This auxiliary measurement can be temperature if connected to an external thermistor or other voltage output

temperature sensor. Otherwise this measurement can sense any other signal that requires monitoring on the

board. Figure 9-7 is similar to Figure 9-6 but shows a configuration where the live current is measured using a

CT and the neutral current is measured using a shunt. The reverse configuration, where the shunt is used for live

and the CT for neutral, is also valid.

Load

VDD

AVDD

AIN0N

AVDD

AIN0N

AIN0P

AIN1P

AIN0P

AIN1P

AIN1N

AIN2N

AIN1N

AIN2N

ADS131M04

AIN2P

AIN3P

AIN2P

AIN3P

Aux

AIN3N

AGND

AIN3N

AGND

Phase

Neutral

Phase

Neutral

Figure 9-6. Single-Phase CT for Live and Neutral

Currents, With Phase and Auxiliary Voltages

Measured

Figure 9-7. Single-Phase, Shunt for Live Current,

CT for Neutral Current, With Phase and Auxiliary

Voltages Measured

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9.1.6 Code Example

This section contains example pseudocode for a simple program that configures and streams data from the

ADS131M04. The pseudocode is written to resemble C code. The code uses several descriptive precompiler-

defined constants that are indicated in upper case. The definitions are not included for brevity. The program

works in three sections: MCU initialization, ADC configuration, and data streaming. This code is not optimized for

using the fast startup feature of the ADS131M04.

The MCU is initialized by enabling the necessary peripherals for this example. These peripherals include an SPI

port, a GPIO configured as an input for the ADS131M04 DRDY output, a clock output to connect to the

ADS131M04 CLKIN input, and a direct memory access (DMA) module that streams data from the SPI port into

memory without significant processor intervention. The SPI port is configured to a 24-bit word size because the

ADC default SPI word size is 24 bits. The CS pin is configured to remain low as long as the SPI port is busy so

that it does not de-assert in the middle of a frame.

The ADC is configured through register writes. A function referred to as adcRegisterWrite writes an ADC register

using the SPI peripheral. No CRC data integrity is used in this example for simplicity, but is recommended. The

ADC outputs are initially disabled so short frames can be written during initialization consistent with the guidance

provided in the Short SPI Frames section. The ADC is configured to output DRDY as pulses, the gain is changed

to 32 for channels 1 and 3, and the DC block filter is used with a corner frequency of 622 mHz. Finally, the ADC

word size is changed to 32 bits with an MSB sign extension to accommodate the MCU memory length and to

allow for 32-bit DMA transfers. All other settings are left as defaults.

Data streaming is performed by using an interrupt that is configured to trigger on a negative edge received on

the GPIO connected to the DRDY pin. The interrupt service routine, referred to as DRDYinterrupt, sends six 32-

bit dummy words to assert CS and to toggle SCLK for the length of the entire ADC output frame. The ADC

output frame consists of one 32-bit status word, four 32-bit ADC conversion data words, and an optional 32-bit

CRC word. The frame is long enough for output CRC even though the CRC word is disabled in this example.

The DMA module is configured to trigger upon receiving data on the SPI input. The DMA automatically sends the

ADC data to a predetermined memory location as soon as the data are shifted into the MCU through the SPI

input.

numFrameWords = 6;

unsigned long spiDummyWord[numFrameWords] =

0x00000000,

// Number of words in a full ADS131M04 SPI frame

{

0x00000000,

0x00000000};

// Dummy word frame to write ADC during ADC data reads

bool firstRead = true; // Flag to tell us if we are reading ADC data for the// first time

signed long adcData;

// Location where DMA will store ADC data in memory,

// length defined elsewhere/*

Interrupt the MCU each time DRDY asserts when collecting data

*/

DRDYinterupt(){

if(firstRead){

// Clear the ADC's 2-deep FIFO on the first read

for(i=0; i<numFrameWords; i++){

SPI.write(spiDummyWord + i);

}

for(i=0; i<numFrameWords; i++){

SPI.read();

}

firstRead = false; // Clear the flag

DMA.enable();

}

// Let the DMA start sending ADC data to memory

for (i=0; i<numFrameWords; i++){// Send the dummy data to the ADC to get// the ADC data

SPI.write(spiDummyWord + i);

}

/*

adcRegisterWrite

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Short function that writes one ADC register at a time. Blocks return until SPI

is idle. Returns false if the word length is wrong.

param

addrMask:

data:

16-bit register address mask

data to write

adcWordLength: word length which ADC expects. Either 16, 24 or 32.

return

true if word length was valid

false if not

*/

bool adcRegisterWrite(unsigned short addrMask, unsigned short data,

unsigned char adcWordLength){

unsigned char shiftValue;

// Stores the amount of bit shift based on

// ADC word length

if(adcWordLength==16){

shiftValue = 0;

}else if(adcWordLength==24){

shiftValue = 8;

// If length is 16, no shift

// If length is 24, shift left by 8

// If length is 32, shift left by 16

// If not, invalid length

}else if(adcWordLength==32){

shiftValue = 16;

}else{

return false;

}

SPI.write((WREG_OPCODE |

// Write address and opcode

addrMask) << shiftValue);// Shift to accommodate ADC word length

SPI.write(data << shiftValue);// Write register data

while(SPI.isBusy());

// Wait for data to complete sending

return true;

}

/*

main routine

*/

main(){

enableSupplies();

GPIO.inputEnable('input'); // Enable GPIO connected to DRDY

clkout.enable(8192000);

SPI.enable();

SPI.wordLengthSet(24);

// Enable 8.192 MHz clock to CLKIN

// Enable SPI port

// ADC default word length is 24 bits

SPI.configCS(STAY_ASSERTED);// Configure CS to remain asserted until frame// is complete

while(!GPIO.read()){}

// Wait for DRDY to go high indicating it is ok// to talk to ADC

// Write CLOCK register

adcRegisterWrite(CLOCK_ADDR,

ALL_CH_DISABLE_MASK

during// config

|

// Turn off all channels so short// frames can be written

OSR_1024_MASK | PWR_HR_MASK, 24);

adcRegisterWrite(MODE_ADDR,

// Re-write defaults for other bits// in CLOCK register

// Write MODE register

RESET_MASK | DRDY_FMT_PULSE_MASK | // Clear the RESET flag, make DRDY// active low pulse

WLENGTH_24_MASK |

// Re-write defaults for other bits

// in MODE register

// Write GAIN1 register

// Set channels 1 and 3 PGA gain to

// 32 in this example// Leave channels 0 and 2 at default// gain

SPI_TIMEOUT_MASK, 24;

adcRegisterWrite(GAIN1_ADDR,

PGAGAIN3_32_MASK |

PGAGAIN1_32_MASK, 24);

of 1

adcRegisterWrite(THRSHLD_LSB_ADDR,

0x09, 24);

// Write THRSHLD_LSB register

// Set DCBLOCK filter to have a// corner frequency of 622 mHz

DMA.triggerSet(SPI);// Configure DMA to trigger when data comes in// on the MCU SPI port

DMA.txAddrSet(SPI.rxAddr());// Set the DMA to take from the incoming SPI

// port

DMA.rxAddrSet(&adcData);// Set the DMA to send ADC data to a predefined

// memory location

adcRegisterWrite(MODE_ADDR,

WLENGTH_32_SIGN_EXTEND_MASK |

DRDY_FMT_PULSE_MASK |

// Write MODE register

// Make ADC word size 32 bits to// accommodate DMA

// Re-write other set bits in MODE

// register

SPI_TIMEOUT_MASK, 24);

SPI.wordLengthSet(32);

// Set SPI word size to 32 bits to// accomodate DMA

// Write CLOCK register

// Turn on all ADC channels

// Re-write defaults for other bits// in CLOCK register

adcRegisterWrite(CLOCK_ADDR,

ALL_CH_ENABLE_MASK |

OSR_1024_MASK | PWR_HR_MASK, 32);

GPIO.interuptEnable();// Enable DRDY interrupt and begin streaming data

}

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9.1.7 Troubleshooting

Table 9-1 lists common issues faced when designing with the ADS131M04 and the corresponding solutions. This

list is not comprehensive.

Table 9-1. Troubleshooting Common Issues Using the ADS131M04

ISSUE

POSSIBLE ROOT CAUSE

ADC conversion data are not being read. The Read data after each DRDY falling edge after

two-deep ADC data FIFO overflows and following the recommendations given in the

triggers DRDY one time every two ADC data Collecting Data for the First Time or After a

POSSIBLE SOLUTION

The DRDY pin is toggling at half the

expected frequency.

periods.

Pause in Data Collection section.

The SYNC/RESET pin functions as a

constant synchronization check, rather than a

convert start pin. See the Synchronization

section for more details on the intended

usage of the SYNC/RESET pin.

The F_RESYNC bit is set in the STATUS

word even though this bit was already

cleared.

The SYNC/RESET pin is being toggled

asynchronously to CLKIN.

The entire frame is not being sent to the

ADC. The ADC does not recognize data as

being read. Therefore, the two-deep ADC

data FIFO overflows one time every two data disabled.

periods.

Read all data words in the output data frame,

including those for channels that are

The same ADC conversion data are output

twice before changing.

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9.2 Typical Application

This section describes a class 0.1 split-phase energy measurement front-end using the ADS131M04. The ADC

samples the outputs of the CTs and voltage dividers to measure the current and voltage (respectively) of each

leg of the AC mains. The design can achieve high accuracy across a wide input current range (0.05 A – 100 A)

and supports high sampling frequencies necessary for advanced power quality features such as individual

harmonic analysis. Using the ADS131M04 to sample the CT output provides designers greater flexibility in the

choice of metrology microcontrollers when compared to an integrated system-on-a-chip (SoC) and dedicated

application-specific products.

The design and results shown in this section are discussed in much greater detail as part of the TIDA-010037:

High accuracy split-phase CT electricity meter reference design using standalone ADCs design guide.

Figure 9-8 shows the front-end for the split-phase energy measurement design.

Load

ADS131M04

AVDD

VDD

AIN0N

MCU

DVDD

VDD

AIN0P

AIN1P

CLKIN

DRDY

SCLK

CS

CLKOUT

Interruptible GPIO

SPI CLK

AIN1N

AIN2N

SPI CS

DIN

SPI MOSI

SPI MISO

GND

DOUT

DGND

AIN2P

AIN3P

AIN3N

AGND

Phase

Neutral

Phase

Figure 9-8. Split-Phase Metrology Design Front-End

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9.2.1 Design Requirements

Table 9-2. Key System Specifications

FEATURES

Number of phases

DESCRIPTION

1 phase (split-phase with two voltages measured)

E-meter accuracy class

Current sensor

Class 0.1

Current transformer

0.05 A to 100 A

50 Hz or 60 Hz

Current range

System nominal frequency

•

Active, reactive, apparent power, and energy

Root mean square (RMS) current and voltage

Power factor

Measured parameters

Line frequency

9.2.2 Detailed Design Procedure

A current sensor connects to the current channels and a simple voltage divider is used for the corresponding

voltage measurement. The CT has an associated burden resistor that must be connected at all times to protect

the measuring device. The selection of the CT and the burden resistor is made based on the manufacturer and

current range required for energy measurements. The voltage divider resistors for the voltage channel are

selected to ensure the mains voltage is divided down to adhere to the normal input voltage ranges of the

ADS131M04.

In this design, the ADS131M04 interacts with a microcontroller (MCU) in the following manner:

•

The CLKIN clock used by the ADS131M04 device is provided by the MCU

When new ADC samples are ready, the ADS131M04 device asserts its DRDY pin, which alerts the MCU that

new samples are available

•

After being alerted of new samples, the MCU uses one of its SPI interfaces to retrieve the voltage and current

samples from the ADS131M04

9.2.2.1 Voltage Measurement Front-End

The nominal voltage from the mains is from 100 V – 240 V so this voltage must be scaled down to be sensed by

an ADC. Figure 9-9 shows the analog front-end used for this voltage scaling.

R_HI

R_FILT

Live

AINxP

C_FILT

R_V

R_LO

R_FILT

Neutral

AINxN

Figure 9-9. Voltage Measurement Front-End

The analog front-end for voltage consists of a spike protection varistor (R_V), a voltage divider network (R_HIand

R_LO), and an RC low-pass filter (R_FILTand C_FILT).

Equation 11 shows how to calculate the range of differential voltages fed to the voltage ADC channel for a given

mains voltage and the selected voltage divider resistor values.

R_LO

V_ADC= ê V_RMS

ì 2 ì

3R_HI+ R_LO

(11)

R_HIis 300 kΩ and R_LOis 750 Ω in this design. For a mains voltage of 120 V (as measured between the line and

neutral), the input signal to the voltage ADC has a voltage swing of ±128 mV (91 mV_RMS) based on Equation 11

and the selected resistor values. This voltage is well within the ±1.2-V input voltage range that can be sensed by

the ADS131M04 for the selected PGA gain value of 1 that is used for the voltage channels.

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9.2.2.2 Current Measurement Front-End

The analog front-end for current inputs is different from the analog front-end for the voltage inputs. Figure 9-10

shows the analog front-end used for a current channel.

R_FILT

AINxP

R_B

C_FILT

R_B

R_FILT

AINxN

Live

Figure 9-10. Current Measurement Front-End

The analog front-end for current consists of burden resistors for the current transformers (R_B) and an RC low-

pass filter (R_FILTand C_FILT) that functions as an antialias filter.

Two identical burden resistors in series are used with the common point being connected to GND instead of

using one burden resistor for best THD performance. This split-burden resistor configuration ensures that the

waveforms fed to the positive and negative terminals of the ADC are 180 degrees out-of-phase with each other,

which provides the best THD results with this ADC. The total burden resistance is selected based on the current

range used and the turns ratio specification of the CT (this design uses CTs with a turns ratio of 2000). The total

value of the effective burden resistor (2R_B) for this design is 12.98 Ω.

Equation 12 shows how to calculate the range of differential voltages fed to the current ADC channel for a given

maximum current, CT turns ratio, and burden resistor value.

V_ADC= ê I_RMSì 2R_Bì 2 N_CT

(12)

Based on the maximum RMS current of 100 A, a CT turns ratio N_CTof 2000, and an effective burden resistor

2R_Bbetween AINxP and AINxN of 12.98 Ω for this design, the input signal to the current ADC has a voltage

swing of ±918 mV maximum (649 mV_RMS) when the maximum current rating of the meter (100 A) is applied. This

±918-mV maximum input voltage is well within the ±1.2-V input range of the device for the selected PGA gain of

1 that is used for the current channels.

9.2.2.3 ADC Setup

The ADS131M04 receives its clock from the MCU in this design. The ADS131M04 is configured in HR mode and

the MCU provides an 8.192-MHz master clock, which is within the allowable clock frequency range for HR mode.

The MCU SPI port that is used to communicate with the ADS131M04 is configured to CPOL = 0 and CPHA = 1.

The SPI clock frequency is configured to be 8.192 MHz so that all conversion data can be shifted out of the

device successfully within the sample period. When powered on, the MCU configures the ADS131M04 registers

with the following settings using SPI register writes.

•

GAIN1 register settings: PGA gain of 1 is used for all ADC channels.

CHx_CNG register settings (where x is the channel number): All ADC channel inputs are connected to the

external ADC pins and the channel phase delay set to 0 for each channel. The channel phase setting can

also be configured in this register. This design uses an integer number of output samples for phase

calibration so the processing is done in software completely.

•

CLOCK register settings: OSR = 512, all channels enabled, and HR mode.

After the ADS131M04 registers are properly initialized, the MCU is configured to generate a GPIO interrupt

whenever a falling edge occurs on the DRDY pin, which indicates that the ADS131M04 has new samples

available.

The clock fed to the CLKIN pin of the ADS131M04 is internally divided by two to generate the modulator clock.

The output data rate of the ADS131M04 is therefore f_MOD/ OSR = f_CLKIN/ (2 × OSR) = 8 kSPS.

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9.2.2.4 Calibration

Certain signal chain errors can be corrected through a single room temperature calibration. The ADS131M04

has the capability to store calibration values and use the values to correct the results in real time. Among those

errors that can be corrected in real time with the ADS131M04 are offset error, gain error, and phase error.

Offset calibration is performed by determining the measured output of the signal chain when the input is zero

voltage for a voltage channel or zero current for a current channel. The value can be measured and recorded in

external non-volatile memory for each channel. When the system is deployed, these values can be provided to

the CHn_OCAL_MSB and CHn_OCAL_LSB registers for the corresponding channels. The ADS131M04 then

subtracts these values from its conversion results prior to providing them to the host. Alternatively, the integrated

DC block filter can be used to implement offset correction.

Similar to offset error correction, system gain error can be determined prior to deployment and can be used to

correct the gain error on each channel in real time. Gain error is defined as the percentage difference in the ADC

transfer function from its PGA gain corrected ideal value of 1. This error can be determined by measuring the

results from both a maximum and minimum input signal, finding the difference between these results, and

dividing by the difference between the ideal difference. Equation 13 describes how to calculate gain error.

V,I _Max,Measured- V,I _Min,Measured

Gain Error = 1 -

V,I _Max- V,I _Min

(13)

To correct for gain error, divide each offset-corrected conversion result by the measured gain. The ADS131M04

multiplies each conversion result by the calibration factor stored in the CHn_GCAL_MSB and CHn_GCAL_LSB

registers according to the method described in the Calibration Registers section. The host can program the

measured inverted gain values for each channel into these registers to have them automatically corrected for

each sample.

The ADS131M04 can also correct for system phase error introduced by sensors. For this design, the CT

introduces some phase error into the system. This design uses a software method for phase correction, but the

ADS131M04 can perform this function in real time. The system must first measure the phase relationships

between the various channels. Then, define one channel as phase 0. Subsequently, the PHASEn bits in the

CHn_CFG registers corresponding to the various other channels can be edited to correct their phase relationship

relative to the phase 0 channels.

9.2.2.5 Formulae

This section describes the formulas used for the power and energy calculations. Voltage and current samples

are obtained at a sampling rate of 8000 Hz. All samples that are taken in approximately one-second (1 sec)

frames are kept and used to obtain the RMS values for voltage and current for each phase.

Power and energy are calculated for active and reactive energy samples of one frame. These samples are

phase-corrected. Then phase active and reactive powers are calculated through the following formulas:

N_samples-1

1

P_Actual.ph

=

v n ì i n

[ ] [ ]

ƒ

N_samples

n = 0

(14)

N_samples-1

1

=

»

ÿ

P_Reactive.ph

v n - n₉₀ì i n

[ ]

°

ƒ

⁄

N_samples

n = 0

(15)

(16)

P_A²_pparent.ph= P_A²_ctual.ph+ P_R²_eactive.ph

where:

•

v[n] = Voltage sample

i[n] = Current sample

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•

N_samples= Number of samples in the approximately 1-second frame

v[n-n_90°] = Voltage sample with a 90° phase shift

P_ACTUAL,ph= Instantaneous actual power for the measured phase

P_REACTIVE= Instantaneous reactive power for the measured phase

P_APPARENT,ph= Instantaneous apparent power for the measured phase

The 90° phase shift approach is used for two reasons:

1. This approach allows accurate measurement of the reactive power for very small currents

2. This approach conforms to the measurement method specified by IEC and ANSI standards

The calculated mains frequency is used to calculate the 90° shifted voltage sample. Because the frequency of

the mains varies, the mains frequency is first measured accurately to phase shift the voltage samples

accordingly.

To get an exact 90° phase shift, interpolation is used between two samples. For these two samples, a voltage

sample slightly more than 90 degrees before the current sample and a voltage sample slightly less than 90°

before the current sample are used. The phase shift implementation of the application consists of an integer part

and a fractional part. The integer part is realized by providing an N samples delay. The fractional part is realized

by a one-tap FIR filter.

The cumulative power values can be calculated by summing the per phase power results. The cumulative

energy can be calculated by multiplying the cumulative power by the number of samples in the packet.

The host calculates the frequency in terms of samples-per-mains cycle by counting zero crossings of the sine

wave. Equation 17 converts this result from a samples-per-mains cycle to Hertz.

Frequency (Hz) = Data rate (samples / second) / Frequency (samples / cycle)

(17)

After the active power and apparent power are calculated, the absolute value of the power factor is calculated. In

the internal representation of power factor of the system, a positive power factor corresponds to a capacitive

load and a negative power factor corresponds to an inductive load. The sign of the internal representation of

power factor is determined by whether the current leads or lags voltage, which is determined in the background

process. Therefore, Equation 18 and Equation 19 calculate the internal representation of the power factor:

PF = P_ACTUAL/ P_APPARENT, if capacitive load

PF = -P_ACTUAL/ P_APPARENT, if inductive load

(18)

(19)

9.2.3 Application Curves

A source generator was used to provide the voltages and currents to the system. In this design, a nominal

voltage of 240 V between the line and neutral, a calibration current of 10 A, and a nominal frequency of 60 Hz

were used for each phase.

When the voltages and currents are applied to the system, the design outputs the cumulative active energy

pulses and cumulative reactive energy pulses at a rate of 6400 pulses per kilowatt hour. This pulse output was

fed into a reference meter that determined the energy percentage error based on the actual energy provided to

the system and the measured energy as determined by the active and reactive energy output pulse of the

system.

The current was varied from 50 mA to 100 A for the cumulative active energy error and cumulative reactive

energy error testing. A phase shift of 0°, 60°, and −60° was applied between the voltage and current waveforms

fed to the design for cumulative active energy testing. Based on the error from the active energy output pulse,

several plots of active energy percentage error versus current were created for 0°, 60°, and –60° phase shifts.

For the cumulative reactive energy error testing, a similar process was followed except that 30°, 60°, –30°, and –

60° phase shifts were used, and the cumulative reactive energy error was plotted instead of the cumulative

active energy error. In the cumulative active and reactive energy testing, the sum of the energy reading of each

phase was tested for accuracy.

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In addition to testing active energy by varying current, active energy was also tested by varying the RMS voltage

from 240 V to 15 V and measuring the active energy percentage error.

The front-end was calibrated before obtaining the following results. The active energy results are within 0.1% at

0° phase shift. At 60° and –60° phase shift, which is allowed to have relaxed accuracy in electricity meter

standards, the trend where the results deviate at higher currents is from the CT phase shift varying across

current.

This design and results are discussed in much greater detail in the TIDA-010037: High accuracy split-phase CT

electricity meter reference design using standalone ADCs design guide.

Table 9-3 shows the cumulative active energy accuracy results with changing voltage. Table 9-4 shows the

cumulative active energy results with varying current. Figure 9-11 shows a plot of the values in Table 9-4.

Table 9-3. Cumulative Phase Active Energy % Error

Versus Voltage, Two-Voltage Mode

VOLTAGE (V)

% ERROR

240

120

60

0.0353

0.022

0.016

0.014

0.013

30

15

Table 9-4. Cumulative Phase Active Energy % Error

Versus Current

CURRENT (A) 0°

60°

–60°

0.05

0.019

0.006

0.0125

0.006

0.015

0.003

0.006

0.01

0.045

0.058

0.045

0.032

0.045

0.024

0.0165

0.002

–0.007

–0.016

–0.035

–0.047

–0.05

–0.045

–0.04

–0.032

0.10

0.25

–0.0385

–0.032

–0.019

–0.039

–0.012

0

0.50

1.00

2.00

5.00

10.00

20.00

30.00

40.00

50.00

60.00

70.00

80.00.

90.00

100.00

–0.007

0.002

0

–0.013

0.0085

0.019

0.042

0.053

0.063

0.067

0.08

–0.003

0.002

0.009

0.007

0.013

0.0223

0.092

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0.5

0.4

0.3

0.2

0.1

0

0°

60°

-60°

-0.1

-0.2

-0.3

-0.4

-0.5

0

10

20

30

40

50

Current (A)

60

70

80

90 100

D003

Figure 9-11. Cumulative Phase Active Energy % Error Versus Current

Table 9-5 shows the cumulative reactive energy accuracy results with changing current. Figure 9-12 shows a plot

of the values in Table 9-4.

Table 9-5. Cumulative Reactive Energy % Error Versus Current

CURRENT (A)

30°

60°

–30°

–60°

0.05

–0.003

–0.037

–0.067

–0.044

–0.036

–0.03

0.004

–0.013

–0.027

–0.021

–0.0183

–0.012

–0.026

–0.016

–0.0007

0.0085

0.02

–0.023

0.011

–0.027

–0.008

0.002

0.10

0.25

0.043

1.00

0.0415

0.022

0.011

5.00

0.001

10.00

20.00

40.00

60.00

80.00

100.00

0.014

–0.003

–0.013

–0.016

–0.0247

–0.021

–0.012

–0.041

–0.01

–0.0035

–0.021

–0.047

–0.048

–0.044

0.025

0.041

0.054

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0.5

0.4

0.3

0.2

0.1

0

30°

60°

-30°

-60°

-0.1

-0.2

-0.3

-0.4

-0.5

0

10

20

30

40

50

Current (A)

60

70

80

90 100

D005

Figure 9-12. Cumulative Reactive Energy % Error Versus Current

10 Power Supply Recommendations

10.1 CAP Pin Behavior

The ADS131M04 core digital voltage of 1.8 V is created from an internal LDO from DVDD. The CAP pin outputs

the LDO voltage created from the DVDD supply and requires an external bypass capacitor. When operating from

DVDD > 2.7 V, place a 220-nF capacitor on the CAP pin to DGND. If DVDD ≤ 2 V, tie the CAP pin directly to the

DVDD pin and decouple the star-connected pins using a 100-nF capacitor to DGND.

10.2 Power-Supply Sequencing

The power supplies can be sequenced in any order but the analog and digital inputs must never exceed the

respective analog or digital power-supply voltage limits.

10.3 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. AVDD and DVDD must each be

decoupled with a 1-µF capacitor. Place the bypass capacitors as close to the power-supply pins of the device as

possible with low-impedance connections. Using multi-layer ceramic chip capacitors (MLCCs) that offer low

equivalent series resistance (ESR) and inductance (ESL) characteristics are recommended for power-supply

decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use

of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple

vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. The analog and

digital ground are recommended to be connected together as close to the device as possible.

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11 Layout

11.1 Layout Guidelines

For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces

on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane

may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the

ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground

loops.

Route digital traces away from all analog inputs and associated components in order to minimize interference.

Use C0G capacitors on the analog inputs. Use ceramic capacitors (for example, X7R grade) for the power-

supply decoupling capacitors. High-K capacitors (Y5V) are not recommended. Place the required capacitors as

close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance

connections on the ground-side connections of the bypass capacitors.

When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination

resistor placed at the clock buffer often helps reduce overshoot. Glitches present on the clock input can lead to

noise within the conversion data.

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11.2 Layout Example

Figure 11-1 shows an example layout of the ADS131M04 requiring a minimum of two PCB layers. In general,

analog signals and planes are partitioned to the left and digital signals and planes to the right.

+3.3 V

Via to corresponding

voltage plane or pour

+3.3 V

Via to ground plane

or pour

Place CAP and power supply

decoupling capacitors close to pins

Channel 0

1: AVDD

2: AGND

3: AIN0P

4: AIN0N

5: AIN1N

6: AIN1P

7: AIN2P

8: AIN2N

9: AIN3N

10: AIN3P

20: DVDD

19: DGND

18: CAP

Channel 1

Channel 2

Channel 3

17: CLKIN

16: DIN

Device

15: DOUT

14: SCLK

13: DRDY

12: CS

11: SYNC/RST

Terminate long digital

input lines with resistors to

prevent reflection

Differential RC-filter

per channel

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, One-phase shunt electricity meter reference design using standalone ADCs design guide

Texas Instruments, High accuracy split-phase CT electricity meter reference design using standalone ADCs

design guide

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS131M04IPWR

ADS131M04IPWT

TSSOP

PW

20

2000

250

330.0

180.0

16.4

6.95

7.0

1.4

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS131M04IPWR

ADS131M04IPWT

TSSOP

PW

20

2000

250

853.0

210.0

449.0

185.0

35.0

Pack Materials-Page 2

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	ADS131M04IPWT
厂家：	TEXAS INSTRUMENTS
描述：	四通道、24 位、64kSPS、同步采样 Δ-Σ ADC \| PW \| 20 \| -40 to 125 光电二极管转换器
文件：	总99页 (文件大小：2919K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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