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ADS4149IRGZ25 [TI]

14-/12-Bit, 160/250MSPS, Ultralow-Power ADC; 14位/ 12位， 160 / 250MSPS ，超低功耗ADC
ADS4149IRGZ25
型号： ADS4149IRGZ25
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

14-/12-Bit, 160/250MSPS, Ultralow-Power ADC
14位/ 12位， 160 / 250MSPS ，超低功耗ADC

转换器 模数转换器
文件： 总79页 (文件大小：2042K)
中文：  中文翻译
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ADS4126, ADS4129  
ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
14-/12-Bit, 160/250MSPS, Ultralow-Power ADC  
Check for Samples: ADS4126, ADS4129, ADS4146, ADS4149  
1
FEATURES  
•
•
DC Offset Correction  
23  
•
Maximum Sample Rate: 250MSPS  
Supports Low Input Clock Amplitude Down To  
200mVPP  
•
Ultralow Power with 1.8V Single Supply:  
•
Package: QFN-48 (7mm × 7mm)  
–
–
200mW Total Power at 160MSPS  
265mW Total Power at 250MSPS  
DESCRIPTION  
•
High Dynamic Performance:  
The ADS414x/2x are  
a family of 14-bit/12-bit  
–
–
SNR: 70.6dBFS at 170MHz  
SFDR: 84dBc at 170MHz  
analog-to-digital converters (ADCs) with sampling  
rates up to 250MSPS. These devices use innovative  
design techniques to achieve high dynamic  
performance, while consuming extremely low power  
at 1.8V supply. The devices are well-suited for  
multi-carrier,  
applications.  
•
•
Dynamic Power Scaling with Sample Rate  
Output Interface  
–
Double Data Rate (DDR) LVDS with  
Programmable Swing and Strength  
wide  
bandwidth  
communications  
–
–
–
–
Standard Swing: 350mV  
The ADS414x/2x have fine gain options that can be  
used to improve SFDR performance at lower  
full-scale input ranges, especially at high input  
frequencies. They include a dc offset correction loop  
that can be used to cancel the ADC offset. At lower  
sampling rates, the ADC automatically operates at  
scaled down power with no loss in performance.  
Low Swing: 200mV  
Default Strength: 100Ω Termination  
2x Strength: 50Ω Termination  
–
1.8V Parallel CMOS Interface Also  
Supported  
•
Programmable Gain up to 6dB for SNR/SFDR  
Trade-Off  
The ADS414x/2x are available in a compact QFN-48  
pacakge and are specified over the industrial  
temperature range (–40°C to +85°C).  
ADS412x/ADS414x Family Comparison  
WITH ANALOG INPUT BUFFERS  
FAMILY  
250MSPS  
160MSPS  
250MSPS  
200MSPS  
ADS414x  
14-Bit Family  
ADS4149  
ADS4146  
ADS41B49  
—
ADS412x  
12-Bit Family  
ADS4129  
ADS4126  
ADS41B29  
—
11-Bit  
9-Bit  
—
—
—
—
—
ADS58B18  
—
ADS58B19  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
PowerPAD is a trademark of Texas Instruments Incorporated.  
All other trademarks are the property of their respective owners.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
FUNCTIONAL BLOCK DIAGRAM  
DDR LVDS  
Interface  
AVDD  
AGND  
DRVDD DRGND  
CLKP  
CLKM  
CLKOUTP  
CLKOUTM  
CLOCKGEN  
D0_D1_P  
D0_D1_M  
D2_D3_P  
D2_D3_M  
Low-Latency Mode  
(Default After Reset)  
D4_D5_P  
D4_D5_M  
INP  
INM  
12-Bit  
ADC  
DDR  
Serializer  
Sampling  
Circuit  
Common  
Digital Functions  
D6_D7_P  
D6_D7_M  
D8_D9_P  
D8_D9_M  
Control  
Interface  
VCM  
Reference  
D10_D11_P  
D10_D11_M  
OVR_SDOUT  
ADS4129  
OE  
Figure 1. ADS412x Block Diagram  
2
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Copyright © 2009–2010, Texas Instruments Incorporated  
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
DDR LVDS  
Interface  
AVDD  
AGND  
DRVDD DRGND  
CLKP  
CLKM  
CLKOUTP  
CLKOUTM  
CLOCKGEN  
D0_D1_P  
D0_D1_M  
D2_D3_P  
D2_D3_M  
D4_D5_P  
D4_D5_M  
Low-Latency Mode  
(Default After Reset)  
D6_D7_P  
D6_D7_M  
INP  
INM  
14-Bit  
ADC  
DDR  
Serializer  
D8_D9_P  
Sampling  
Circuit  
Common  
Digital Functions  
D8_D9_M  
D10_D11_P  
D10_D11_M  
Control  
Interface  
D12_D13_P  
D12_D13_M  
VCM  
Reference  
OVR_SDOUT  
ADS4149  
OE  
Figure 2. ADS414x Block Diagram  
Copyright © 2009–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
ORDERING INFORMATION(1)  
SPECIFIED  
PACKAGE-  
LEAD  
PACKAGE  
DESIGNATOR  
TEMPERATURE  
RANGE  
LEAD/BALL PACKAGE  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
ECO PLAN(2)  
FINISH  
MARKING  
ADS4126IRGZR Tape and reel, 2500  
ADS4126IRGZT Tape and reel, 250  
ADS4129IRGZR Tape and reel, 2500  
ADS4129IRGZT Tape and reel, 250  
ADS4146IRGZR Tape and reel, 2500  
ADS4146IRGZT Tape and reel, 250  
ADS4149IRGZR Tape and reel, 2500  
ADS4149IRGZT Tape and reel, 250  
GREEN (RoHS,  
no Sb/Br)  
ADS4126(3)  
QFN-48  
QFN-48  
QFN-48  
QFN-48  
RGZ  
RGZ  
RGZ  
RGZ  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
Cu/NiPdAu  
AZ4126  
GREEN (RoHS,  
no Sb/Br)  
ADS4129(3)  
ADS4146(3)  
ADS4149  
Cu/NiPdAu  
Cu/NiPdAu  
Cu/NiPdAu  
AZ4129  
AZ4146  
AZ4149  
GREEN (RoHS,  
no Sb/Br)  
GREEN (RoHS,  
no Sb/Br)  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the  
device product folder at www.ti.com.  
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and  
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more  
information.  
(3) Shaded rows indicate product preview device.  
The ADS414x/2x family is pin-compatible to the previous generation ADS6149 family; this architecture enables  
easy migration. However, there are some important differences between the generations, summarized in Table 1.  
Table 1. MIGRATING FROM THE ADS6149 FAMILY  
ADS6149 FAMILY  
ADS4149 FAMILY  
PINS  
Pin 21 is NC (not connected)  
Pin 23 is MODE  
Pin 21 is NC (not connected)  
Pin 23 is RESERVED in the ADS4149 family. It is reserved as a digital control pin for an (as yet)  
undefined function in the next-generation ADC series.  
SUPPLY  
AVDD is 3.3V  
AVDD is 1.8V  
No change  
DRVDD is 1.8V  
INPUT COMMON-MODE VOLTAGE  
VCM is 1.5V  
VCM is 0.95V  
SERIAL INTERFACE  
Protocol: 8-bit register address and 8-bit register  
data  
No change in protocol  
New serial register map  
EXTERNAL REFERENCE MODE  
Supported  
Not supported  
ADS61B49 FAMILY  
PINS  
ADS41B29/B49/ADS58B18 FAMILY  
Pin 21 is NC (not connected)  
Pin 21 is 3.3V AVDD_BUF (supply for the analog input buffers)  
Pin 23 is a digital control pin for the RESERVED function.  
Pin 23 functions as SNR Boost enable (B18 only).  
Pin 23 is MODE  
SUPPLY  
AVDD is 3.3V  
AVDD is 1.8V, AVDD_BUF is 3.3V  
No change  
DRVDD is 1.8V  
INPUT COMMON-MODE VOLTAGE  
VCM is 1.5V  
VCM is 1.7V  
SERIAL INTERFACE  
Protocol: 8-bit register address and 8-bit register  
data  
No change in protocol  
New serial register map  
EXTERNAL REFERENCE MODE  
Supported  
Not supported  
4
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Copyright © 2009–2010, Texas Instruments Incorporated  
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
 
ADS4126, ADS4129  
ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating free-air temperature range, unless otherwise noted.  
VALUE  
UNIT  
V
Supply voltage range, AVDD  
–0.3 to 2.1  
Supply voltage range, DRVDD  
–0.3 to 2.1  
V
Voltage between AGND and DRGND  
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)  
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)  
INP, INM  
–0.3 to 0.3  
V
0 to 2.1  
V
0 to 2.1  
V
–0.3 to minimum (1.9, AVDD + 0.3)  
V
Voltage applied to input pins  
CLKP, CLKM(2), DFS, OE  
–0.3 to AVDD + 0.3  
–0.3 to 3.9  
–40 to +85  
+125  
V
RESET, SCLK, SDATA, SEN  
V
Operating free-air temperature range, TA  
Operating junction temperature range, TJ  
Storage temperature range, TSTG  
°C  
°C  
°C  
kV  
–65 to +150  
2
ESD, human body model (HBM)  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied.  
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.  
This prevents the ESD protection diodes at the clock input pins from turning on.  
THERMAL CHARACTERISTICS(1)  
PARAMETER  
TEST CONDITIONS  
TYPICAL VALUE  
UNIT  
°C/W  
°C/W  
°C/W  
Soldered thermal pad, no airflow  
Soldered thermal pad, 200LFM  
Bottom of package (thermal pad)  
29  
22  
(2)  
RqJA  
(3)  
RqJT  
1.13  
(1) With a JEDEC standard high-K board and 5×5 via array. See the Exposed Pad section in the Application Information.  
(2)  
(3)  
R
qJA is the thermal resistance from junction to ambient.  
RqJT is the thermal resistance from junction to the thermal pads.  
Copyright © 2009–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
RECOMMENDED OPERATING CONDITIONS  
Over operating free-air temperature range, unless otherwise noted.  
ADS412x, ADS414x  
TYP  
MIN  
MAX  
UNIT  
SUPPLIES  
AVDD  
Analog supply voltage  
Digital supply voltage  
1.7  
1.7  
1.8  
1.8  
1.9  
1.9  
V
V
DRVDD  
ANALOG INPUTS  
Differential input voltage range(1)  
Input common-mode voltage  
Maximum analog input frequency with 2VPP input amplitude(2)  
Maximum analog input frequency with 1VPP input amplitude(2)  
CLOCK INPUT  
2
VCM ± 0.05  
400  
VPP  
V
MHz  
MHz  
800  
Input clock sample rate  
ADS4129/ADS4149  
1
1
250  
160  
MSPS  
MSPS  
ADS4126/ADS4146  
Input clock amplitude differential (VCLKP – VCLKM  
Sine wave, ac-coupled  
)
0.2  
1.5  
1.6  
0.7  
1.8  
50  
VPP  
VPP  
VPP  
V
LVPECL, ac-coupled  
LVDS, ac-coupled  
LVCMOS, single-ended, ac-coupled  
Input clock duty cycle  
DIGITAL OUTPUTS  
%
CLOAD  
RLOAD  
TA  
Maximum external load capacitance from each output pin to DRGND  
5
pF  
Ω
Differential load resistance between the LVDS output pairs (LVDS  
mode)  
100  
Operating free-air temperature  
–40  
+85  
°C  
HIGH PERFORMANCE MODES(3)(4)(5)  
Set the MODE 1 register bits to get best performance across sample  
clock and input signal frequencies.  
Mode 1  
Register address = 0x03, register data = 0x03  
Set the MODE 2 register bit to get best performance at high input  
signal frequencies.  
Mode 2  
Register address = 0x4A, register data = 0x01  
(1) With 0dB gain. See the Fine Gain section in the Application Information for relation between input voltage range and gain.  
(2) See the Theory of Operation section in the Application Information.  
(3) It is recommended to use these modes to get best performance. These modes can be set using the serial interface only.  
(4) See the Serial Interface section for details on register programming.  
(5) Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device  
Configuration section.  
6
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Copyright © 2009–2010, Texas Instruments Incorporated  
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
ELECTRICAL CHARACTERISTICS: ADS4146/ADS4149  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain,  
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:  
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. Note that after reset, the device is in 0dB gain mode.  
ADS4146 (160MSPS)(1)  
ADS4149 (250MSPS)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
14  
MIN  
TYP  
MAX  
14  
UNIT  
Bits  
Resolution  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
72.2  
72  
71.9  
71.4  
71.4  
70.6  
69  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBc  
SNR (signal-to-noise ratio), LVDS  
71.5  
70.5  
69  
67.5  
72  
71.6  
71  
71.8  
71.4  
70.4  
68.2  
88  
SINAD (signal-to-noise and distortion ratio),  
LVDS  
70.9  
69.4  
67.4  
87  
66  
87  
82  
dBc  
Spurious-free dynamic range  
Total harmonic distortion  
Second-harmonic distortion  
SFDR  
THD  
HD2  
HD3  
86  
81  
dBc  
82  
72  
84  
dBc  
77  
75  
dBc  
86.5  
85  
85  
dBc  
80  
dBc  
84  
79  
dBc  
81  
71  
80.5  
71.5  
89  
dBc  
74.5  
91  
dBc  
dBc  
90  
85  
dBc  
88  
84  
dBc  
88  
72  
84  
dBc  
79  
75  
dBc  
88  
87  
dBc  
87  
82  
dBc  
Third-harmonic distortion  
86  
81  
dBc  
82  
72  
82  
dBc  
77  
75  
dBc  
91  
90  
dBc  
90  
88  
dBc  
Worst spur  
(other than second and third harmonics)  
90  
90  
dBc  
90  
77  
88  
dBc  
88  
88  
dBc  
f1 = 46MHz, f2 = 50MHz,  
each tone at –7dBFS  
–88  
–86  
–88  
–86  
dBFS  
dBFS  
Two-tone intermodulation  
distortion  
IMD  
f1 = 185MHz, f2 = 190MHz,  
each tone at –7dBFS  
Recovery to within 1% (of final  
value) for 6dB overload with  
sine-wave input  
Clock  
cycles  
Input overload recovery  
1
1
For 100mVPP signal on AVDD  
supply, up to 10MHz  
AC power-supply rejection ratio  
PSRR  
> 30  
> 30  
dB  
Effective number of bits  
Differential nonlinearity  
Integrated nonlinearity  
ENOB  
DNL  
INL  
fIN = 170MHz  
fIN = 170MHz  
fIN = 170MHz  
11.5  
±0.5  
±2  
11.3  
±0.5  
±2  
LSBs  
LSBs  
LSBs  
–0.95  
±5  
(1) The ADS4146 is a product preview device.  
Copyright © 2009–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
ELECTRICAL CHARACTERISTICS: ADS4126/ADS4129  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain,  
and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range:  
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V. Note that after reset, the device is in 0dB gain mode.  
ADS4126 (160MSPS)(1)  
ADS4129 (250MSPS)(1)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
12  
MIN  
TYP  
MAX  
12  
UNIT  
Bits  
Resolution  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
fIN = 10MHz  
fIN = 70MHz  
fIN = 100MHz  
fIN = 170MHz  
fIN = 300MHz  
70.2  
70  
69.8  
69.7  
69.6  
69  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBFS  
dBc  
SNR (signal-to-noise ratio), LVDS  
69.7  
69  
68  
68  
70.1  
70  
69.7  
69.4  
69.3  
68.8  
66.8  
87  
SINAD (signal-to-noise and distortion ratio),  
LVDS  
69.5  
68.7  
67.3  
88  
87  
82  
dBc  
Spurious-free dynamic range  
Total harmonic distortion  
Second-harmonic distortion  
SFDR  
THD  
HD2  
HD3  
86.3  
82.5  
77.5  
87  
81  
dBc  
84  
dBc  
75  
dBc  
85  
dBc  
85  
80  
dBc  
84  
79  
dBc  
81  
80.5  
71.5  
90  
dBc  
74.5  
92  
dBc  
dBc  
90  
85  
dBc  
88  
84  
dBc  
88  
84  
dBc  
78  
74  
dBc  
88  
87  
dBc  
87  
82  
dBc  
Third-harmonic distortion  
86  
81  
dBc  
82.5  
77  
84  
dBc  
75  
dBc  
92  
90  
dBc  
91  
88  
dBc  
Worst spur  
(other than second and third harmonics)  
90  
90  
dBc  
90  
88  
dBc  
88  
88  
dBc  
f1 = 46MHz, f2 = 50MHz,  
each tone at –7dBFS  
–88  
–86  
–88  
–86  
dBFS  
dBFS  
Two-tone intermodulation  
distortion  
IMD  
f1 = 185MHz, f2 = 190MHz,  
each tone at –7dBFS  
Recovery to within 1% (of final  
value) for 6dB overload with  
sine-wave input  
Clock  
cycles  
Input overload recovery  
1
1
For 100mVPP signal on AVDD  
supply, up to 10MHz  
AC power-supply rejection ratio  
PSRR  
> 30  
> 30  
dB  
Effective number of bits  
Differential nonlinearity  
Integrated nonlinearity  
ENOB  
DNL  
INL  
fIN = 170MHz  
fIN = 170MHz  
fIN = 170MHz  
11.2  
±0.2  
11.2  
±0.2  
LSBs  
LSBs  
LSBs  
±0.25  
±0.25  
(1) The ADS4126 and ADS4129 are product preview devices.  
8
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
ELECTRICAL CHARACTERISTICS: GENERAL  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and 0dB gain, unless otherwise noted.  
Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and  
DRVDD = 1.8V.  
ADS4126/ADS4146 (160MSPS)(1)  
ADS4129/ADS4149 (250MSPS)(1)  
PARAMETER  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNIT  
ANALOG INPUTS  
Differential input voltage range  
Differential input resistance (at dc); see Figure 114  
Differential input capacitance; see Figure 115  
Analog input bandwidth  
2.0  
> 1  
4
2.0  
> 1  
4
VPP  
MΩ  
pF  
550  
0.6  
0.95  
4
550  
0.6  
0.95  
4
MHz  
µA/MSPS  
V
Analog input common-mode current (per input pin)  
Common-mode output voltage  
VCM output current capability  
VCM  
mA  
DC ACCURACY  
Offset error  
2.5  
–15  
–2  
2.5  
15  
mV  
Temperature coefficient of offset error  
0.003  
0.003  
mV/°C  
Gain error as a result of internal reference  
inaccuracy alone  
EGREF  
–2  
2
2
%FS  
Gain error of channel alone  
Temperature coefficient of EGCHAN  
POWER SUPPLY  
EGCHAN  
–0.2  
–0.2  
–1  
%FS  
0.001  
0.001  
Δ%/°C  
IAVDD  
Analog supply current  
IDRVDD(2)  
Output buffer supply current  
LVDS interface with 100Ω external termination  
Low LVDS swing (200mV)  
73  
38  
99  
47  
113  
mA  
mA  
IDRVDD  
Output buffer supply current  
LVDS interface with 100Ω external termination  
Standard LVDS swing (350mV)  
50  
26  
59  
35  
72  
mA  
mA  
IDRVDD output buffer supply current(2)(3)  
CMOS interface(3)  
8pF external load capacitance  
fIN = 2.5MHz  
Analog power  
Digital power  
131  
179  
mW  
mW  
68.7  
84.6  
LVDS interface, low LVDS swing  
Digital power  
CMOS interface(3)  
47  
63  
mW  
8pF external load capacitance  
fIN = 2.5MHz  
Global power-down  
Standby  
10  
10  
25  
mW  
mW  
185  
185  
(1) The ADS4126, ADS4129, and ADS4146 are product preview devices.  
(2) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the  
maximum recommended load capacitance on each digital output line is 10pF.  
(3) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the  
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).  
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DIGITAL CHARACTERISTICS  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise noted. Minimum and  
maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.  
ADS4126, ADS4129, ADS4146, ADS4149(1)  
PARAMETER  
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)  
High-level input voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
RESET, SCLK, SDATA, and  
SEN support 1.8V and 3.3V  
CMOS logic levels  
1.3  
V
V
Low-level input voltage  
0.4  
0.4  
High-level input voltage  
1.3  
V
OE only supports 1.8V CMOS  
logic levels  
Low-level input voltage  
V
High-level input current: SDATA, SCLK(2)  
High-level input current: SEN  
Low-level input current: SDATA, SCLK  
Low-level input current: SEN  
VHIGH = 1.8V  
VHIGH = 1.8V  
VLOW = 0V  
10  
0
µA  
µA  
µA  
µA  
0
VLOW = 0V  
10  
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)  
High-level output voltage  
DRVDD – 0.1  
DRVDD  
0
V
V
Low-level output voltage  
0.1  
DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M)  
High-level output voltage(3)  
Low-level output voltage(3)  
High-level output voltage(3)  
Low-level output voltage(3)  
Output common-mode voltage  
VODH  
VODL  
VODH  
VODL  
VOCM  
Standard swing LVDS  
Standard swing LVDS  
Low swing LVDS  
270  
+350  
–350  
+200  
–200  
1.05  
430  
mV  
mV  
mV  
mV  
V
–430  
–270  
Low swing LVDS  
0.85  
1.25  
(1) The ADS4126, ADS4129, and ADS4146 are product preview devices.  
(2) SDATA and SCLK have an internal 180kΩ pull-down resistor.  
(3) With an external 100Ω termination.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TIMING CHARACTERISTICS  
Dn_Dn + 1_P  
Logic 0  
VODL  
Logic 1  
VODH  
Dn_Dn + 1_M  
VOCM  
GND  
(1) With external 100Ω termination.  
Figure 3. LVDS Output Voltage Levels  
TIMING REQUIREMENTS: LVDS and CMOS Modes(1)  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,  
CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature  
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
tA  
Aperture delay  
0.6  
0.8  
1.2  
ns  
Variation of aperture  
delay  
Between two devices at the same temperature and  
DRVDD supply  
±100  
100  
5
ps  
fS rms  
µs  
tJ  
Aperture jitter  
Time to valid data after coming out of STANDBY  
mode  
25  
Wakeup time  
Time to valid data after coming out of PDN GLOBAL  
mode  
100  
10  
500  
µs  
Clock  
cycles  
Low-latency mode (default after reset)  
Low-latency mode disabled (gain enabled, offset  
correction disabled)  
Clock  
cycles  
ADC latency(4)  
16  
Low-latency mode disabled (gain and offset  
correction enabled)  
Clock  
cycles  
17  
DDR LVDS MODE(5)(6)  
tSU  
Data setup time(3)  
Data valid(7) to zero-crossing of CLKOUTP  
0.75  
0.35  
1.1  
ns  
ns  
Zero-crossing of CLKOUTP to data becoming  
invalid(7)  
tH  
Data hold time(3)  
0.60  
Input clock rising edge cross-over to output clock  
rising edge cross-over  
Clock propagation  
delay  
tPDI  
3
4.2  
5.4  
ns  
ns  
1MSPS ≤ sampling frequency ≤ 250MSPS  
Between two devices at the same temperature and  
DRVDD supply  
Variation of tPDI  
±0.6  
(1) Timing parameters are ensured by design and characterization but are not production tested.  
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.  
(3) RLOAD is the differential load resistance between the LVDS output pair.  
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.  
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold  
time specifications take into account the effect of jitter on the output data and clock.  
(6) The LVDS timings are unchanged for low latency disabled and enabled.  
(7) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.  
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TIMING REQUIREMENTS: LVDS and CMOS Modes (1) (continued)  
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, sampling frequency = 250 MSPS, sine wave input clock,  
CLOAD = 5pF (2), and RLOAD = 100Ω (3), unless otherwise noted. Minimum and maximum values are across the full temperature  
range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DDR LVDS MODE (continued)  
Duty cycle of differential clock, (CLKOUTP –  
CLKOUTM)  
1MSPS ≤ sampling frequency ≤ 250MSPS  
LVDS bit clock duty  
cycle  
42  
48  
54  
%
Rise time measured from –100mV to +100mV  
Fall time measured from +100mV to –100mV  
1MSPS ≤ sampling frequency ≤ 250MSPS  
Data rise time,  
tRISE, tFALL  
0.14  
ns  
Data fall time  
Output clock rise  
time,  
Output clock fall time  
Rise time measured from –100mV to +100mV  
Fall time measured from +100mV to –100mV  
1MSPS ≤ sampling frequency ≤ 250MSPS  
tCLKRISE  
tCLKFALL  
,
0.14  
50  
ns  
ns  
Output enable (OE) to  
data delay  
PARALLEL CMOS MODE(8)(9)  
tOE  
Time to valid data after OE becomes active  
100  
1.1  
Input clock to data  
Input clock rising edge cross-over to start of data  
valid(10)  
tSTART  
delay  
ns  
ns  
tDV  
Data valid time  
Time interval of valid data(10)  
2.5  
4
3.2  
5.5  
Input clock rising edge cross-over to output clock  
rising edge cross-over  
Clock propagation  
delay  
tPDI  
7
ns  
%
1MSPS ≤ sampling frequency ≤ 200MSPS  
Output clock duty  
cycle  
Duty cycle of output clock, CLKOUT  
1MSPS ≤ sampling frequency ≤ 200MSPS  
47  
Rise time measured from 20% to 80% of DRVDD  
Fall time measured from 80% to 20% of DRVDD  
1 ≤ sampling frequency ≤ 250MSPS  
Data rise time,  
Data fall time  
tRISE, tFALL  
0.35  
ns  
Output clock rise  
time,  
Output clock fall time  
Rise time measured from 20% to 80% of DRVDD  
Fall time measured from 80% to 20% of DRVDD  
1 ≤ sampling frequency ≤ 200MSPS  
tCLKRISE  
tCLKFALL  
,
0.35  
20  
ns  
ns  
Output enable (OE) to  
data delay  
tOE  
Time to valid data after OE becomes active  
40  
(8) For fS > 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).  
(9) Low latency mode enabled.  
(10) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
Table 2. LVDS Timing Across Sampling Frequencies  
SAMPLING  
SETUP TIME (ns)  
HOLD TIME (ns)  
FREQUENCY  
(MSPS)  
MIN  
0.85  
1.05  
1.10  
1.60  
2.30  
4.50  
TYP  
1.25  
1.55  
1.70  
2.10  
3.00  
5.20  
MAX  
MIN  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
TYP  
0.60  
0.60  
0.60  
0.60  
0.60  
0.60  
MAX  
230  
200  
185  
160  
125  
80  
Table 3. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)  
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK  
SAMPLING  
FREQUENCY  
(MSPS)  
tSETUP (ns)  
TYP  
2.2  
tHOLD (ns)  
TYP  
2.5  
tPDI (ns)  
TYP  
5.5  
MIN  
1.6  
1.8  
2.3  
3.1  
5.4  
MAX  
MIN  
1.8  
1.9  
2.2  
3.2  
5.4  
MAX  
MIN  
4.0  
4.0  
4.0  
4.0  
4.0  
MAX  
200  
185  
160  
125  
80  
7.0  
7.0  
7.0  
7.0  
7.0  
2.4  
2.7  
5.5  
2.9  
3.0  
5.5  
3.7  
4.0  
5.5  
6.0  
6.0  
5.5  
Table 4. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)  
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK  
SAMPLING  
FREQUENCY  
(MSPS)  
tSETUP (ns)  
TYP  
1.6  
tHOLD (ns)  
TYP  
2.8  
tPDI (ns)  
TYP  
5.5  
MIN  
1.0  
1.3  
1.8  
2.5  
4.8  
MAX  
MIN  
2.0  
2.2  
2.5  
3.5  
5.7  
MAX  
MIN  
4.0  
4.0  
4.0  
4.0  
4.0  
MAX  
7.0  
7.0  
7.0  
7.0  
7.0  
200  
185  
160  
125  
80  
2.0  
3.0  
5.5  
2.5  
3.3  
5.5  
3.2  
4.3  
5.5  
5.5  
6.5  
5.5  
Table 5. CMOS Timing Across Sampling Frequencies (Low Latency Enabled)  
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK  
tSTART (ns)  
TYP  
tDV (ns)  
TYP  
3.2  
SAMPLING FREQUENCY  
(MSPS)  
MIN  
MAX  
1.1  
MIN  
2.5  
2.9  
3.5  
3.9  
4.3  
MAX  
250  
230  
200  
185  
170  
0.7  
3.5  
–0.3  
–1  
4.2  
4.5  
–1.5  
5.0  
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Table 6. CMOS Timing Across Sampling Frequencies (Low Latency Disabled)  
TIMING SPECIFIED WITH RESPECT TO INPUT CLOCK  
tSTART (ns) tDV (ns)  
TYP  
SAMPLING FREQUENCY  
(MSPS)  
MIN  
MAX  
1.6  
1.1  
0.3  
0
MIN  
2.5  
2.9  
3.5  
3.9  
4.3  
TYP  
3.2  
3.5  
4.2  
4.5  
5.0  
MAX  
250  
230  
200  
185  
170  
–1.3  
N + 12  
N + 3  
N + 4  
N + 11  
N + 2  
N + 1  
N + 10  
Sample N  
Input Signal  
tA  
CLKP  
Input Clock  
CLKM  
CLKOUTM  
CLKOUTP  
tPDI  
tH  
10 Clock Cycles(1)  
tSU  
DDR LVDS  
Output Data(2)  
(DXP, DXM)  
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
N - 10  
N - 9  
N - 8  
N - 7  
N - 6  
N + 1  
N + 2  
N
tPDI  
CLKOUT  
tSU  
Parallel CMOS  
10 Clock Cycles(1)  
tH  
Output Data  
N - 10  
N - 9  
N - 8  
N - 7  
N - 1  
N
N + 1  
(1) ADC latency in low-latency mode. At higher sampling frequencies, tDPI is greater than one clock cycle which then makes the overall  
latency = ADC latency + 1.  
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).  
Figure 4. Latency Diagram  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
CLKM  
Input  
Clock  
CLKP  
tPDI  
CLKOUTP  
Output  
Clock  
CLKOUTM  
tSU  
tH  
tSU  
tH  
Dn_Dn + 1_P  
Dn_Dn + 1_M  
Output  
Data Pair  
Dn(1)  
Dn + 1(1)  
(1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc.  
Figure 5. LVDS Mode Timing  
CLKM  
Input  
Clock  
CLKP  
tPDI  
Output  
Clock  
CLKOUT  
tSU  
tH  
Output  
Data  
Dn(1)  
Dn  
CLKM  
CLKP  
Input  
Clock  
tSTART  
tDV  
Output  
Data  
Dn(1)  
Dn  
Dn = bits D0, D1, D2, etc.  
Figure 6. CMOS Mode Timing  
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DEVICE CONFIGURATION  
The ADS414x/2x have several modes that can be configured using a serial programming interface, as described  
in Table 7, Table 8, and Table 9. In addition, the devices have two dedicated parallel pins for quickly configuring  
commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The  
analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).  
Table 7. DFS: Analog Control Pin  
DESCRIPTION  
VOLTAGE APPLIED ON DFS  
0, +100mV/–0mV  
(Data Format/Output Interface)  
Twos complement/DDR LVDS  
Twos complement/parallel CMOS  
Offset binary/parallel CMOS  
Offset binary/DDR LVDS  
(3/8) AVDD ± 100mV  
(5/8) AVDD ± 100mV  
AVDD, +0mV/–100mV  
Table 8. OE: Digital Control Pin  
VOLTAGE APPLIED ON OE  
DESCRIPTION  
0
Output data buffers disabled  
Output data buffers enabled  
AVDD  
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device  
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have  
any alternative functions. Keep SEN tied high and SCLK tied low on the board.  
Table 9. SDATA: Digital Control Pin  
VOLTAGE APPLIED ON SDATA  
DESCRIPTION  
Normal operation  
0
Logic high  
Device enters standby  
AVDD  
(5/8) AVDD  
3R  
(5/8) AVDD  
(3/8) AVDD  
GND  
AVDD  
2R  
3R  
(3/8) AVDD  
To Parallel Pin  
Figure 7. Simplified Diagram to Configure DFS Pin  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
SERIAL INTERFACE  
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface  
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)  
pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every  
falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK  
falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.  
Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the  
register address and the remaining eight bits are the register data. The interface can work with SCLK frequency  
from 20MHz down to very low speeds (a few Hertz) and also with non-50% SCLK duty cycle.  
Register Initialization  
After power-up, the internal registers must be initialized to the default values. This initialization can be  
accomplished in one of two ways:  
1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown  
in Figure 8; or  
2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 0x00) high.  
This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In  
this case, the RESET pin is kept low.  
Register Address  
A4  
A3  
Register Data  
SDATA  
SCLK  
A7  
A6  
A5  
A2  
A1  
A0  
D7  
D6  
D5  
D4  
D3  
D2  
tDH  
D1  
D0  
tSCLK  
tDSU  
tSLOADS  
tSLOADH  
SEN  
RESET  
Figure 8. Serial Interface Timing  
SERIAL INTERFACE TIMING CHARACTERISTICS  
Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,  
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.  
PARAMETER  
SCLK frequency (equal to 1/tSCLK  
SEN to SCLK setup time  
SCLK to SEN hold time  
SDATA setup time  
MIN  
> DC  
25  
TYP  
MAX  
UNIT  
MHz  
ns  
fSCLK  
tSLOADS  
tSLOADH  
tDSU  
)
20  
25  
ns  
25  
ns  
tDH  
SDATA hold time  
25  
ns  
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Serial Register Readout  
The serial register readout function allows the contents of the internal registers to be read back on the  
OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface  
communication between the external controller and the ADC.  
After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When  
the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:  
1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any  
further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is  
also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of  
the register at address 0 cannot be read in the register readout mode.  
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be  
read.  
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.  
4. The external controller can latch the contents at the falling edge of SCLK.  
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the  
device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.  
Register Address A[7:0] = 0x00  
Register Data D[7:0] = 0x01  
SDATA  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK  
SEN  
OVR_SDOUT(1)  
a) Enable Serial Readout (READOUT = 1)  
Register Address A[7:0] = 0x43  
A4 A2  
A5 A3  
Register Data D[7:0] = XX (don’t care)  
D4 D2 D1  
D6 D5 D3  
SDATA  
SCLK  
A7  
A6  
A1  
A0  
D7  
D0  
SEN  
OVR_SDOUT(2)  
0
1
0
0
0
0
0
0
b) Read Contents of Register 0x43. This Register Has Been Initialized with 0x40 (device is put in global power-down mode).  
(1) The OVR_SDOUT pin finctions as OVR (READOUT = 0).  
(2) The OVR_SDOUT pin finctions as a serial readout (READOUT = 1).  
Figure 9. Serial Readout Timing Diagram  
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RESET TIMING CHARACTERISTICS  
Power Supply  
AVDD, DRVDD  
t1  
RESET  
t2  
t3  
SEN  
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel  
interface operation, RESET must be permanently tied high.  
Figure 10. Reset Timing Diagram  
RESET TIMING REQUIREMENTS  
Typical values at +25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,  
unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Delay from power-up of AVDD and DRVDD to RESET  
pulse active  
t1  
Power-on delay  
1
ms  
10  
ns  
µs  
ns  
Pulse width of active RESET signal that resets the  
serial registers  
t2  
t3  
Reset pulse width  
1(1)  
Delay from RESET disable to SEN active  
100  
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could  
enter the parallel configuration mode briefly and then return back to serial interface mode.  
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SERIAL REGISTER MAP  
Table 10 summarizes the functions supported by the serial interface.  
Table 10. Serial Interface Register Map(1)  
REGISTER  
ADDRESS  
DEFAULT VALUE  
AFTER RESET  
REGISTER DATA  
A[7:0] (Hex)  
D[7:0] (Hex)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
RESET  
0
D0  
READOUT  
0
00  
01  
03  
00  
00  
00  
0
0
0
0
0
0
LVDS SWING  
0
0
0
0
0
0
0
0
0
HIGH PERF MODE 1  
TEST PATTERNS  
DISABLE  
GAIN  
25  
26  
00  
00  
GAIN  
LVDS  
CLKOUT  
STRENGTH  
LVDS DATA  
STRENGTH  
0
0
0
0
0
0
EN  
OFFSET  
CORR  
3D  
00  
DATA FORMAT  
0
0
0
3F  
40  
00  
00  
CUSTOM PATTERN HIGH D[13:6]  
CUSTOM PATTERN D[5:0]  
0
EN  
CLKOUT  
RISE  
EN  
CLKOUT  
FALL  
CMOS CLKOUT  
STRENGTH  
41  
00  
LVDS CMOS  
CLKOUT RISE POSN  
DIS LOW  
LATENCY  
42  
43  
00  
00  
CLKOUT FALL POSN  
0
0
0
0
STBY  
0
0
PDN  
GLOBAL  
0
PDN OBUF  
0
0
0
0
0
EN LVDS SWING  
HIGH PERF  
MODE 2  
4A  
BF  
00  
00  
0
0
0
0
OFFSET PEDESTAL  
OFFSET CORR TIME CONSTANT  
0
FREEZE  
OFFSET  
CORR  
CF  
00  
0
0
0
(1) Multiple functions in a register can be programmed in a single write operation.  
DESCRIPTION OF SERIAL REGISTERS  
For best performance, two special mode register bits must be enabled: HI PERF MODE 1 and HI PERF MODE  
2.  
Register Address 0x00 (Default = 00h)  
7
0
6
0
5
0
4
3
2
0
1
0
0
0
RESET  
READOUT  
Bits[7:2]  
Bit 1  
Always write '0'  
RESET: Software reset applied  
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).  
READOUT: Serial readout  
Bit 0  
This bit sets the serial readout of the registers.  
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage  
indicator.  
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.  
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Register Address 0x01 (Default = 00h)  
7
6
5
4
3
2
1
0
0
0
LVDS SWING  
Bits[7:2]  
LVDS SWING: LVDS swing programmability(1)  
000000 = Default LVDS swing; ±350mV with external 100Ω termination  
011011 = LVDS swing increases to ±410mV  
110010 = LVDS swing increases to ±465mV  
010100 = LVDS swing increases to ±570mV  
111110 = LVDS swing decreases to ±200mV  
001111 = LVDS swing decreases to ±125mV  
Bits[1:0]  
Always write '0'  
(1) The EN LVDS SWING register bits must be set to enable LVDS swing control.  
Register Address 0x03 (Default = 00h)  
7
0
6
0
5
0
4
3
2
0
1
0
0
0
HI PERF MODE 1  
Bits[7:2]  
Bits[1:0]  
Always write '0'  
HI PERF MODE 1: High performance mode 1  
00 = Default performance after reset  
01 = Do not use  
10 = Do not use  
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF  
MODE 1 bits  
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Register Address 0x25 (Default = 00h)  
7
6
5
4
3
2
1
0
GAIN  
DISABLE GAIN  
TEST PATTERNS  
Bits[7:4]  
GAIN: Gain programmability  
These bits set the gain programmability in 0.5dB steps.  
0000 = 0dB gain (default after reset)  
0001 = 0.5dB gain  
0010 = 1.0dB gain  
0011 = 1.5dB gain  
0100 = 2.0dB gain  
0111 = 3.5dB gain  
1000 = 4.0dB gain  
1001 = 4.5dB gain  
1010 = 5.0dB gain  
1011 = 5.5dB gain  
1100 = 6dB gain  
0101 = 2.5dB gain  
0110 = 3.0dB gain  
Bit 3  
DISABLE GAIN: Gain setting  
This bit sets the gain.  
0 = Gain enabled; gain is set by the GAIN bits only if low-latency mode is disabled  
1 = Gain disabled  
Bits[2:0]  
TEST PATTERNS: Data capture  
These bits verify data capture.  
000 = Normal operation  
001 = Outputs all 0s  
010 = Outputs all 1s  
011 = Outputs toggle pattern  
In the ADS4146/49, output data D[13:0] is an alternating sequence of 01010101010101 and  
10101010101010.  
In the ADS4126/29, output data D[11:0] is an alternating sequence of 010101010101 and  
101010101010.  
100 = Outputs digital ramp  
In ADS4149/46, output data increments by one LSB (14-bit) every clock cycle from code 0 to  
code 16383  
In ADS4129/26, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to  
code 4095  
101 = Output custom pattern (use registers 0x3F and 0x40 for setting the custom pattern)  
110 = Unused  
111 = Unused  
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Register Address 0x26 (Default = 00h)  
7
0
6
0
5
0
4
3
2
0
1
0
LVDS CLKOUT  
STRENGTH  
LVDS DATA  
STRENGTH  
0
0
Bits[7:2]  
Bit 1  
Always write '0'  
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength  
This bit determines the external termination to be used with the LVDS output clock buffer.  
0 = 100Ω external termination (default strength)  
1 = 50Ω external termination (2x strength)  
Bit 0  
LVDS DATA STRENGTH: LVDS data buffer strength  
This bit determines the external termination to be used with all of the LVDS data buffers.  
0 = 100Ω external termination (default strength)  
1 = 50Ω external termination (2x strength)  
Register Address 0x3D (Default = 00h)  
7
6
5
4
3
2
0
1
0
0
0
EN OFFSET  
CORR  
DATA FORMAT  
0
0
Bits[7:6]  
DATA FORMAT: Data format selection  
These bits selects the data format.  
00 = The DFS pin controls data format selection  
10 = Twos complement  
11 = Offset binary  
Bit 5  
ENABLE OFFSET CORR: Offset correction setting  
This bit sets the offset correction.  
0 = Offset correction disabled  
1 = Offset correction enabled  
Bits[4:0]  
Always write '0'  
Register Address 0x3F (Default = 00h)  
7
6
5
4
3
2
1
0
CUSTOM  
CUSTOM  
CUSTOM  
CUSTOM  
CUSTOM  
CUSTOM  
CUSTOM  
CUSTOM  
PATTERN D13 PATTERN D12 PATTERN D11 PATTERN D10 PATTERN D9  
PATTERN D8  
PATTERN D7  
PATTERN D6  
Bits[7:0]  
CUSTOM PATTERN(1)  
These bits set the custom pattern.  
(1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM  
PATTERN D[13:2].  
Register Address 0x40 (Default = 00h)  
7
6
5
4
3
2
1
0
0
0
CUSTOM  
PATTERN D5  
CUSTOM  
PATTERN D4  
CUSTOM  
PATTERN D3  
CUSTOM  
PATTERN D2  
CUSTOM  
PATTERN D1  
CUSTOM  
PATTERN D0  
Bits[7:2]  
CUSTOM PATTERN(1)  
These bits set the custom pattern.  
Bits[1:0]  
Always write '0'  
(1) For the ADS414x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS412x, output data bits 11 to 0 are CUSTOM  
PATTERN D[13:2].  
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Register Address 0x41 (Default = 00h)  
7
6
5
4
3
2
1
0
EN CLKOUT  
RISE  
EN CLKOUT  
FALL  
LVDS CMOS  
CMOS CLKOUT STRENGTH  
CLKOUT RISE POSN  
Bits[7:6]  
LVDS CMOS: Interface selection  
These bits select the interface.  
00 = The DFS pin controls the selection of either LVDS or CMOS interface  
10 = The DFS pin controls the selection of either LVDS or CMOS interface  
01 = DDR LVDS interface  
11 = Parallel CMOS interface  
Bits[5:4]  
CMOS CLKOUT STRENGTH  
Controls strength of CMOS output clock only.  
00 = Maximum strength (recommended and used for specified timings)  
01 = Medium strength  
10 = Low strength  
11 Very low strength  
Bit 3  
ENABLE CLKOUT RISE  
0 = Disables control of output clock rising edge  
1 = Enables control of output clock rising edge  
Bits[2:1]  
CLKOUT RISE POSN: CLKOUT rise control  
Controls position of output clock rising edge  
LVDS interface:  
00 = Default position (timings are specified in this condition)  
01 = Setup reduces by 500ps, hold increases by 500ps  
10 = Data transition is aligned with rising edge  
11 = Setup reduces by 200ps, hold increases by 200ps  
CMOS interface:  
00 = Default position (timings are specified in this condition)  
01 = Setup reduces by 100ps, hold increases by 100ps  
10 = Setup reduces by 200ps, hold increases by 200ps  
11 = Setup reduces by 1.5ns, hold increases by 1.5ns  
Bit 0  
ENABLE CLKOUT FALL  
0 Disables control of output clock fall edge  
1 Enables control of output clock fall edge  
Register Address 0x42 (Default = 00h)  
7
6
5
0
4
3
2
1
0
0
0
DIS LOW  
LATENCY  
CLKOUT FALL CTRL  
0
STBY  
Bits[7:6]  
CLKOUT FALL CTRL  
Controls position of output clock falling edge  
LVDS interface:  
00 = Default position (timings are specified in this condition)  
01 = Setup reduces by 400ps, hold increases by 400ps  
10 = Data transition is aligned with rising edge  
11 = Setup reduces by 200ps, hold increases by 200ps  
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CMOS interface:  
00 = Default position (timings are specified in this condition)  
01 = Falling edge is advanced by 100ps  
10 = Falling edge is advanced by 200ps  
11 = Falling edge is advanced by 1.5ns  
Bits[5:4]  
Bit 3  
Always write '0'  
DIS LOW LATENCY: Disable low latency  
This bit disables low-latency mode,  
0 = Low latency mode is enabled. Digital functions such as gain, test patterns and offset correction  
are disabled  
1 = Low-latency mode is disabled. This setting enables the digital functions. See the Digital  
Functions and Low Latency Mode section.  
Bit 2  
STBY: Standby mode  
This bit sets the standby mode.  
0 = Normal operation  
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time  
from standby is fast  
Bits[1:0]  
Always write '0'  
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Register Address 0x43 (Default = 00h)  
7
0
6
5
0
4
3
2
0
1
0
PDN GLOBAL  
PDN OBUF  
0
EN LVDS SWING  
Bit 0  
Bit 6  
Always write '0'  
PDN GLOBAL: Power-down  
This bit sets the state of operation.  
0 = Normal operation  
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow  
wake-up time.  
Bit 5  
Bit 4  
Always write '0'  
PDN OBUF: Power-down output buffer  
This bit set the output data and clock pins.  
0 = Output data and clock pins enabled  
1 = Output data and clock pins powered down and put in high- impedance state  
Bits[3:2]  
Bits[1:0]  
Always write '0'  
EN LVDS SWING: LVDS swing control  
00 = LVDS swing control using LVDS SWING register bits is disabled  
01 = Do not use  
10 = Do not use  
11 = LVDS swing control using LVDS SWING register bits is enabled  
Register Address 0x4A (Default = 00h)  
7
0
6
0
5
0
4
3
2
0
1
0
0
HI PERF  
MODE 2  
0
0
Bits[7:1]  
Bit[0]  
Always write '0'  
HI PERF MODE 2: High performance mode 2  
This bit is recommended for high input signal frequencies greater than 230MHz.  
0 = Default performance after reset  
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit  
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Register Address 0xBF (Default = 00h)  
7
6
5
4
3
2
1
0
0
0
OFFSET PEDESTAL  
Bits[7:2]  
OFFSET PEDESTAL  
These bits set the offset pedestal.  
When the offset correction is enabled, the final converged value after the offset is corrected is the  
ADC mid-code value. A pedestal can be added to the final converged value by programming these  
bits.  
ADS414x VALUE  
PEDESTAL  
011111  
011110  
011101  
—
31LSB  
30LSB  
29LSB  
—
000000  
—
0LSB  
—
111111  
111110  
—
–1LSB  
–2LSB  
—
100000  
–32LSB  
Bits[1:0]  
Always write '0'  
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Register Address 0xCF (Default = 00h)  
7
6
5
4
3
2
1
0
0
0
FREEZE  
OFFSET  
CORR  
BYPASS  
OFFSET  
CORR  
OFFSET CORR TIME CONSTANT  
Bit 7  
FREEZE OFFSET CORR  
This bit sets the freeze offset correction.  
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)  
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the  
last estimated value is used for offset correction every clock cycle. See OFFSET CORRECTION,  
Offset Correction.  
Bit 6  
Always write '0'  
Bits[5:2]  
OFFSET CORR TIME CONSTANT  
These bits set the offset correction time constant for the correction loop time constant in number of  
clock cycles.  
VALUE  
TIME CONSTANT (Number of Clock Cycles)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1M  
2M  
4M  
8M  
16M  
32M  
64M  
128M  
256M  
512M  
1G  
2G  
Bits[1:0]  
Always write '0'  
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PIN CONFIGURATION (LVDS MODE)  
RGZ PACKAGE(1)  
QFN-48  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
DRGND  
DRVDD  
OVR_SDOUT  
CLKOUTM  
CLKOUTP  
DFS  
1
2
3
4
5
6
7
8
9
36 DRGND  
35 DRVDD  
34 D0_D1_P  
33 D0_D1_M  
32 NC  
31 NC  
OE  
30 RESET  
29 SCLK  
28 SDATA  
27 SEN  
AVDD  
AGND  
CLKP 10  
CLKM 11  
AGND 12  
26 AVDD  
25 AGND  
13 14 15 16 17 18 19 20 21 22 23 24  
(1) The PowerPAD™ is connected to DRGND.  
(2) The ADS4146 is a product preview device.  
Figure 11. ADS414x LVDS Pinout(2)  
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RGZ PACKAGE(2)  
QFN-48  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
DRGND  
DRVDD  
OVR_SDOUT  
CLKOUTM  
CLKOUTP  
DFS  
1
2
3
4
5
6
7
8
9
36 DRGND  
35 DRVDD  
34 NC  
33 NC  
32 NC  
31 NC  
OE  
30 RESET  
29 SCLK  
28 SDATA  
27 SEN  
26 AVDD  
25 AGND  
AVDD  
AGND  
CLKP 10  
CLKM 11  
AGND 12  
13 14 15 16 17 18 19 20 21 22 23 24  
(3) The PowerPAD is connected to DRGND.  
(4) The ADS4126 and ADS4129 are product preview devices.  
Figure 12. ADS412x LVDS Pinout(2)  
ADS414x, ADS412x Pin Assignments (LVDS Mode)  
# OF  
PIN NAME  
AVDD  
AGND  
CLKP  
CLKM  
INP  
PIN NUMBER  
PINS  
FUNCTION  
DESCRIPTION  
8, 18, 20, 22, 24, 26  
6
6
1
1
1
1
I
I
I
I
I
I
1.8V analog power supply  
Analog ground  
9, 12, 14, 17, 19, 25  
10  
11  
15  
16  
Differential clock input, positive  
Differential clock input, negative  
Differential analog input, positive  
Differential analog input, negative  
INM  
Outputs the common-mode voltage (0.95V) that can be used externally to bias the  
analog input pins.  
VCM  
13  
1
O
Serial interface RESET input.  
When using the serial interface mode, the internal registers must initialize through  
hardware RESET by applying a high pulse on this pin or by using the software reset  
option; refer to the Serial Interface section.  
RESET  
30  
1
I
When RESET is tied high, the internal registers are reset to the default values. In this  
condition, SEN can be used as an analog control pin.  
RESET has an internal 180kΩ pull-down resistor.  
This pin functions as a serial interface clock input when RESET is low. When RESET is  
high, SCLK has no function and should be tied to ground. This pin has an internal  
180kΩ pull-down resistor.  
SCLK  
29  
28  
1
1
I
I
This pin functions as a serial interface data input when RESET is low. When RESET is  
high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an  
internal 180kΩ pull-down resistor.  
SDATA  
30  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
ADS414x, ADS412x Pin Assignments (LVDS Mode) (continued)  
# OF  
PINS  
PIN NAME  
PIN NUMBER  
FUNCTION  
DESCRIPTION  
This pin functions as a serial interface enable input when RESET is low. When RESET  
is high, SEN has no function and should be tied to AVDD. This pin has an internal  
180kΩ pull-up resistor to AVDD.  
SEN  
27  
1
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to  
DRVDD.  
OE  
7
6
1
1
I
I
Data format select input. This pin sets the DATA FORMAT (twos complement or offset  
binary) and the LVDS/CMOS output interface type. See Table 7 for detailed information.  
DFS  
RESERVED  
CLKOUTP  
CLKOUTM  
23  
5
1
1
1
I
Digital control pin, reserved for future use  
Differential output clock, true  
O
O
4
Differential output clock, complement  
Refer to Figure 11  
and Figure 12  
D0_D1_P  
D0_D1_M  
D2_D3_P  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential output data D0 and D1 multiplexed, true  
Differential output data D0 and D1 multiplexed, complement  
Differential output data D2 and D3 multiplexed, true  
Differential output data D2 and D3 multiplexed, complement  
Differential output data D4 and D5 multiplexed, true  
Differential output data D4 and D5 multiplexed, complement  
Differential output data D6 and D7 multiplexed, true  
Differential output data D6 and D7 multiplexed, complement  
Differential output data D8 and D9 multiplexed, true  
Differential output data D8 and D9 multiplexed, complement  
Differential output data D10 and D11 multiplexed, true  
Differential output data D10 and D11 multiplexed, complement  
Differential output data D12 and D13 multiplexed, true  
Differential output data D12 and D13 multiplexed, complement  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
D2_D3_M  
D4_D5_P  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
D4_D5_M  
D6_D7_P  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
D6_D7_M  
D8_D9_P  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
D8_D9_M  
D10_D11_P  
D10_D11_M  
D12_D13_P  
D12_D13_M  
OVR_SDOUT  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
Refer to Figure 11  
and Figure 12  
This pin functions as an out-of-range indicator after reset, when register bit  
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.  
3
DRVDD  
DRGND  
2, 35  
2
2
I
I
1.8V digital and output buffer supply  
Digital and output buffer ground  
1, 36, PAD  
Refer to Figure 11  
and Figure 12  
NC  
—
—
Do not connect  
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PIN CONFIGURATION (CMOS MODE)  
RGZ PACKAGE(3)  
QFN-48  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
DRGND  
DRVDD  
OVR_SDOUT  
UNUSED  
CLKOUT  
DFS  
1
2
3
4
5
6
7
8
9
36 DRGND  
35 DRVDD  
34 D1  
33 D0  
32 NC  
31 NC  
OE  
30 RESET  
29 SCLK  
28 SDATA  
27 SEN  
26 AVDD  
25 AGND  
AVDD  
AGND  
CLKP 10  
CLKM 11  
AGND 12  
13 14 15 16 17 18 19 20 21 22 23 24  
(5) The PowerPAD is connected to DRGND.  
(6) The ADS4146 is a product preview device.  
Figure 13. ADS414x CMOS Pinout(2)  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
RGZ PACKAGE(4)  
QFN-48  
(TOP VIEW)  
48 47 46 45 44 43 42 41 40 39 38 37  
DRGND  
DRVDD  
OVR_SDOUT  
UNUSED  
CLKOUT  
DFS  
1
2
3
4
5
6
7
8
9
36 DRGND  
35 DRVDD  
34 NC  
33 NC  
32 NC  
31 NC  
OE  
30 RESET  
29 SCLK  
28 SDATA  
27 SEN  
26 AVDD  
25 AGND  
AVDD  
AGND  
CLKP 10  
CLKM 11  
AGND 12  
13 14 15 16 17 18 19 20 21 22 23 24  
(7) The PowerPAD is connected to DRGND.  
(8) The ADS4126 and ADS4129 are product preview devices.  
Figure 14. ADS412x CMOS Pinout(2)  
ADS414x, ADS412x Pin Assignments (CMOS Mode)  
# OF  
PIN NAME  
AVDD  
AGND  
CLKP  
CLKM  
INP  
PIN NUMBER  
PINS  
FUNCTION  
DESCRIPTION  
8, 18, 20, 22, 24, 26  
6
6
1
1
1
1
I
I
I
I
I
I
1.8V analog power supply  
Analog ground  
9, 12, 14, 17, 19, 25  
10  
11  
15  
16  
Differential clock input, positive  
Differential clock input, negative  
Differential analog input, positive  
Differential analog input, negative  
INM  
Outputs the common-mode voltage (0.95V) that can be used externally to bias the  
analog input pins.  
VCM  
13  
1
O
Serial interface RESET input.  
When using the serial interface mode, the internal registers must initialize through  
hardware RESET by applying a high pulse on this pin or by using the software reset  
option; refer to the Serial Interface section.  
RESET  
30  
1
I
When RESET is tied high, the internal registers are reset to the default values. In this  
condition, SEN can be used as an analog control pin.  
RESET has an internal 180kΩ pull-down resistor.  
This pin functions as a serial interface clock input when RESET is low. When RESET is  
high, SCLK has no function and should be tied to ground. This pin has an internal  
180kΩ pull-down resistor.  
SCLK  
SDATA  
SEN  
29  
28  
27  
1
1
1
I
I
I
This pin functions as a serial interface data input when RESET is low. When RESET is  
high, SDATA functions as a STANDBY control pin (see Table 9). This pin has an  
internal 180kΩ pull-down resistor.  
This pin functions as a serial interface enable input when RESET is low. When RESET  
is high, SEN has no function and should be tied to AVDD. This pin has an internal  
180kΩ pull-up resistor to AVDD.  
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ADS414x, ADS412x Pin Assignments (CMOS Mode) (continued)  
# OF  
PINS  
PIN NAME  
PIN NUMBER  
FUNCTION  
DESCRIPTION  
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up resistor to  
DRVDD.  
OE  
7
1
1
I
Data format select input. This pin sets the DATA FORMAT (twos complement or offset  
binary) and the LVDS/CMOS output interface type. See Table 7 for detailed information.  
DFS  
6
I
RESERVED  
CLKOUT  
23  
5
1
1
I
Digital control pin, reserved for future use  
CMOS output clock  
O
Refer to Figure 13  
and Figure 14  
D0  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
Refer to Figure 13  
and Figure 14  
D1  
Refer to Figure 13  
and Figure 14  
D2  
Refer to Figure 13  
and Figure 14  
D3  
Refer to Figure 13  
and Figure 14  
D4  
Refer to Figure 13  
and Figure 14  
D5  
Refer to Figure 13  
and Figure 14  
D6  
Refer to Figure 13  
and Figure 14  
D7  
D8  
Refer to Figure 13  
and Figure 14  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
Refer to Figure 13  
and Figure 14  
D9  
Refer to Figure 13  
and Figure 14  
D10  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
14-bit/12-bit CMOS output data  
Refer to Figure 13  
and Figure 14  
D11  
Refer to Figure 13  
and Figure 14  
D12  
Refer to Figure 13  
and Figure 14  
D13  
This pin functions as an out-of-range indicator after reset, when register bit  
READOUT = 0, and functions as a serial register readout pin when READOUT = 1.  
OVR_SDOUT  
3
DRVDD  
DRGND  
UNUSED  
2, 35  
1, 36, PAD  
4
2
2
1
I
I
1.8V digital and output buffer supply  
Digital and output buffer ground  
Unused pin in CMOS mode  
—
Refer to Figure 13  
and Figure 14  
NC  
—
—
Do not connect  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4149  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
FFT FOR 10MHz INPUT SIGNAL  
FFT FOR 170MHz INPUT SIGNAL  
0
-20  
0
-20  
SFDR = 87.2dBc  
SNR = 71.3dBFS  
SINAD = 71.2dBFS  
THD = 84.7dBc  
SFDR = 88.3dBc  
SNR = 72.4dBFS  
SINAD = 72.2dBFS  
THD = 84dBc  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
100  
125  
100  
125  
0
25  
50  
75  
0
25  
50  
75  
Frequency (MHz)  
Frequency (MHz)  
Figure 15.  
Figure 16.  
FFT FOR 300MHz INPUT SIGNAL  
FFT FOR TWO-TONE INPUT SIGNAL  
0
-10  
0
-10  
SFDR = 78.9dBc  
SNR = 68.8dBFS  
SINAD = 68.3dBFS  
THD = 76.6dBc  
Each Tone at  
-7dBFS Amplitude  
fIN1 = 185MHz  
-20  
-20  
-30  
-30  
fIN2 = 190MHz  
-40  
-40  
Two-Tone IMD = 89.5dBFS  
SFDR = 95dBFS  
-50  
-50  
-60  
-70  
-60  
-80  
-70  
-90  
-80  
-100  
-110  
-120  
-130  
-140  
-90  
-100  
-110  
-120  
100  
125  
125  
0
25  
50  
75  
0
25  
50  
75  
100  
Frequency (MHz)  
Frequency (MHz)  
Figure 17.  
Figure 18.  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
90  
86  
82  
78  
74  
70  
66  
74  
73  
72  
71  
70  
69  
68  
67  
66  
-2dBFS Input, 0dB Gain  
-1dBFS Input, 1dB Gain  
-1dBFS Input, 1dB Gain  
-2dBFS Input, 0dB Gain  
500  
0
50 100 150 200 250 300 350 400 450 500  
Input Frequency (MHz)  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
Figure 19.  
Figure 20.  
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www.ti.com  
TYPICAL CHARACTERISTICS: ADS4149 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
ACROSS INPUT AMPLITUDES (CMOS)  
ACROSS INPUT AMPLITUDES (CMOS)  
90  
86  
82  
78  
74  
70  
74  
73  
72  
71  
70  
69  
68  
67  
350  
0
50  
100  
150  
200  
250  
300  
350  
0
50  
100  
150  
200  
250  
300  
Input Frequency (MHz)  
Input Frequency (MHz)  
Figure 21.  
Figure 22.  
SFDR ACROSS GAIN AND INPUT FREQUENCY  
SINAD ACROSS GAIN AND INPUT FREQUENCY  
90  
73  
150MHz  
170MHz  
170MHz  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
150MHz  
86  
82  
78  
74  
70  
66  
220MHz  
220MHz  
300MHz  
300MHz  
500MHz  
400MHz  
400MHz  
500MHz  
6.0  
6.0  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
Figure 23.  
Figure 24.  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
76  
75  
74  
73  
72  
71  
70  
69  
68  
100  
90  
80  
70  
60  
50  
40  
30  
20  
76  
75  
74  
73  
72  
71  
70  
69  
68  
SFDR (dBFS)  
SFDR (dBFS)  
SNR (dBFS)  
SNR (dBFS)  
SFDR (dBc)  
SFDR (dBc)  
Input Frequency = 40.1MHz  
-30 -20 -10  
Input Frequency = 170.1MHz  
-30 -20 -10 0  
-60  
-50  
-40  
0
-60  
-50  
-40  
Input Amplitude (dBFS)  
Input Amplitude (dBFS)  
Figure 25.  
Figure 26.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4149 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE  
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY  
92  
75.0  
88  
Input Frequency = 40MHz  
AVDD = 1.8V  
90  
88  
86  
84  
82  
80  
78  
76  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
71.5  
71.0  
87  
86  
AVDD = 1.9V  
SFDR  
85  
AVDD = 1.75V  
84  
AVDD = 1.85V  
83  
SNR  
82  
AVDD = 1.7V  
81  
fIN = 40MHz  
80  
1.10  
85  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
-40  
-15  
10  
35  
60  
Input Common-Mode Voltage (V)  
Temperature (°C)  
Figure 27.  
Figure 28.  
SNR ACROSS TEMPERATURE vs AVDD SUPPLY  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE  
74.0  
89  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
88  
87  
86  
85  
84  
83  
73.5  
73.0  
72.5  
72.0  
71.5  
71.0  
AVDD = 1.85V  
AVDD = 1.75V  
AVDD = 1.8V, 1.9V  
SFDR  
SNR  
AVDD = 1.7V  
fIN = 40MHz  
fIN = 40MHz  
-40 -15  
1.90  
1.70  
1.75  
1.80  
1.85  
85  
10  
35  
60  
DRVDD Supply (V)  
Temperature (°C)  
Figure 29.  
Figure 30.  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE (CMOS)  
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE  
90  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
89  
88  
87  
86  
85  
84  
83  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
SFDR (dBc)  
SFDR  
SNR (dBFS)  
SNR  
Input Frequency = 170MHz  
0.15 0.37 0.75 1.00 1.25 1.60 1.90 2.20 2.40 2.60  
1.90  
1.70  
1.75  
1.80  
1.85  
DRVDD Supply (V)  
Differential Clock Amplitude (VPP  
)
Figure 31.  
Figure 32.  
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www.ti.com  
TYPICAL CHARACTERISTICS: ADS4149 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE  
INTEGRAL NONLINEARITY  
88  
74.0  
73.5  
73.0  
72.5  
72.0  
71.5  
71.0  
70.5  
70.0  
1.5  
1.0  
87  
86  
85  
84  
83  
82  
81  
80  
SNR  
0.5  
0
THD  
-0.5  
-1.0  
-1.5  
Input Frequency = 10MHz  
25 30 35 40 45  
75  
16k  
50  
55  
60  
65  
70  
0
2k  
4k  
6k  
8k  
10k  
12k  
14k  
Input Clock Duty Cycle (%)  
Output Code (LSB)  
Figure 33.  
Figure 34.  
DIFFERENTIAL NONLINEARITY  
OUTPUT HISTOGRAM WITH INPUTS SHORTED  
0.5  
44  
RMS = 0.999LSB  
39.7  
40  
36  
32  
28  
24  
20  
16  
12  
8
0.4  
0.3  
35.7  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
12.6  
6.0  
3.8  
4
1.4  
0.2  
0.7  
0
16k  
0
2k  
4k  
6k  
8k  
10k  
12k  
14k  
Output Code (LSB)  
Output Code (LSB)  
Figure 35.  
Figure 36.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4146  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(1)  
FFT FOR 10MHz INPUT SIGNAL  
FFT FOR 170MHz INPUT SIGNAL  
0
-10  
0
-10  
SFDR = 94dBc  
SFDR = 82.5dBc  
SNR = 72.25dBFS  
SINAD = 72.20dBFS  
THD = 91.29dBc  
SNR = 70.8dBFS  
SINAD = 70.4dBFS  
THD = 80.6dBc  
-20  
-20  
-30  
-30  
-40  
-40  
-50  
-50  
-60  
-60  
-70  
-70  
-80  
-80  
-90  
-90  
-100  
-110  
-120  
-100  
-110  
-120  
80  
80  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
Frequency (MHz)  
Frequency (MHz)  
Figure 37.  
Figure 38.  
FFT FOR 300MHz INPUT SIGNAL  
FFT FOR TWO-TONE INPUT SIGNAL  
0
-10  
0
-10  
SFDR = 78.1dBc  
SNR = 68.4dBFS  
SINAD = 67.8dBFS  
THD = 75.2dBc  
Each Tone at  
-7dBFS Amplitude  
fIN1 = 185MHz  
-20  
-20  
-30  
-30  
fIN2 = 190MHz  
-40  
-40  
Two-Tone IMD = 89.5dBFS  
SFDR = 95dBFS  
-50  
-50  
-60  
-70  
-60  
-80  
-70  
-90  
-80  
-100  
-110  
-120  
-130  
-140  
-90  
-100  
-110  
-120  
80  
125  
0
10  
20  
30  
40  
50  
60  
70  
0
25  
50  
75  
100  
Frequency (MHz)  
Frequency (MHz)  
Figure 39.  
Figure 40.  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
95  
90  
85  
80  
75  
70  
65  
60  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
-2dBFS Input, 0dB Gain  
-2dBFS Input, 0dB Gain  
-1dBFS Input, 1dB Gain  
-1dBFS Input, 1dB Gain  
600  
0
100  
200  
300  
400  
500  
500  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
Input Frequency (MHz)  
Figure 41.  
Figure 42.  
(1) The ADS4146 is a product preview device.  
Copyright © 2009–2010, Texas Instruments Incorporated  
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ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
TYPICAL CHARACTERISTICS: ADS4146 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
ACROSS INPUT AMPLITUDES (CMOS)  
ACROSS INPUT AMPLITUDES (CMOS)  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
68  
74  
73  
72  
71  
70  
69  
68  
350  
0
50  
100  
150  
200  
250  
300  
350  
0
50  
100  
150  
200  
250  
300  
Input Frequency (MHz)  
Input Frequency (MHz)  
Figure 43.  
Figure 44.  
SFDR ACROSS GAIN AND INPUT FREQUENCY  
SINAD ACROSS GAIN AND INPUT FREQUENCY  
88  
73  
150MHz  
170MHz  
170MHz  
84  
80  
76  
72  
68  
64  
71  
69  
67  
65  
63  
61  
220MHz  
150MHz  
220MHz  
300MHz  
300MHz  
400MHz  
400MHz  
500MHz  
500MHz  
6.0  
6.0  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
Figure 45.  
Figure 46.  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
100  
90  
80  
70  
60  
50  
40  
30  
20  
76  
75  
74  
73  
72  
71  
70  
69  
68  
105  
95  
85  
75  
65  
55  
45  
35  
25  
76  
75  
74  
73  
72  
71  
70  
69  
68  
SFDR (dBFS)  
SFDR (dBFS)  
SNR (dBFS)  
SFDR (dBc)  
SNR (dBFS)  
SFDR (dBc)  
Input Frequency = 40.1MHz  
Input Frequency = 170.1MHz  
-30 -20 -10 0  
-60  
-50  
-40  
-30  
-20  
-10  
0
-60  
-50  
-40  
Input Amplitude (dBFS)  
Input Amplitude (dBFS)  
Figure 47.  
Figure 48.  
40  
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ADS4146, ADS4149  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4146 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE  
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY  
90  
75.5  
88  
Input Frequency = 40MHz  
88  
86  
84  
82  
80  
78  
76  
74  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
71.5  
87  
AVDD = 1.85V  
AVDD = 1.8V  
86  
SFDR  
SNR  
AVDD = 1.9V  
85  
84  
83  
AVDD = 1.75V  
AVDD = 1.7V  
82  
81  
fIN = 40MHz  
80  
1.10  
85  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
-40  
-15  
10  
35  
60  
Input Common-Mode Voltage (V)  
Temperature (°C)  
Figure 49.  
Figure 50.  
SNR ACROSS TEMPERATURE vs AVDD SUPPLY  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE  
75.0  
88  
75.5  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
71.5  
71.0  
87  
86  
85  
84  
83  
82  
AVDD = 1.8V  
AVDD = 1.7V  
SFDR  
AVDD = 1.75V, 1.85V  
AVDD = 1.9V  
SNR  
fIN = 40MHz  
fIN = 40MHz  
1.90  
1.70  
1.75  
1.80  
1.85  
85  
-40  
-15  
10  
35  
60  
DRVDD Supply (V)  
Temperature (°C)  
Figure 51.  
Figure 52.  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE (CMOS)  
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE  
89  
88  
87  
86  
85  
84  
83  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
90  
78  
76  
74  
72  
70  
68  
66  
64  
62  
60  
86  
82  
78  
74  
70  
66  
62  
58  
54  
SFDR (dBc)  
SFDR  
SNR (dBFS)  
SNR  
Input Frequency = 170MHz  
1.90  
1.70  
1.75  
1.80  
1.85  
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3  
DRVDD Supply (V)  
Differential Clock Amplitude (VPP  
)
Figure 53.  
Figure 54.  
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ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
TYPICAL CHARACTERISTICS: ADS4146 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE  
INTEGRAL NONLINEARITY  
88  
75.0  
74.5  
74.0  
73.5  
73.0  
72.5  
72.0  
71.5  
71.0  
1.0  
0.8  
87  
86  
85  
84  
83  
82  
81  
80  
0.6  
0.4  
0.2  
SNR  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
THD  
Input Frequency = 10MHz  
25 30 35 40 45  
75  
16k  
50  
55  
60  
65  
70  
0
2k  
4k  
6k  
8k  
10k  
12k  
14k  
Input Clock Duty Cycle (%)  
Output Code (LSB)  
Figure 55.  
Figure 56.  
DIFFERENTIAL NONLINEARITY  
OUTPUT HISTOGRAM WITH INPUTS SHORTED  
0.5  
36  
RMS = 1.137LSB  
31.1  
0.4  
0.3  
32  
28  
24  
20  
16  
12  
8
27.5  
0.2  
23.1  
0.1  
0
-0.1  
-0.2  
-0.3  
-0.4  
-0.5  
12.2  
4.8  
4
1.0  
0.3  
0
16k  
0
2k  
4k  
6k  
8k  
10k  
12k  
14k  
Output Code (LSB)  
Output Code (LSB)  
Figure 57.  
Figure 58.  
42  
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ADS4146, ADS4149  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4129  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(1)  
FFT FOR 10MHz INPUT SIGNAL  
FFT FOR 170MHz INPUT SIGNAL  
0
-20  
0
-20  
SFDR = 87.7dBc  
SFDR = 87.2dBc  
SNR = 69.6dBFS  
SINAD = 69.4dBFS  
THD = 83.9dBc  
SNR = 70.3dBFS  
SINAD = 70.2dBFS  
THD = 83.5dBc  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
100  
125  
100  
125  
0
25  
50  
75  
0
25  
50  
75  
Frequency (MHz)  
Frequency (MHz)  
Figure 59.  
Figure 60.  
FFT FOR 300MHz INPUT SIGNAL  
FFT FOR TWO-TONE INPUT SIGNAL  
0
-20  
0
-10  
SFDR = 79.3dBc  
SNR = 68dBFS  
SINAD = 67.5dBFS  
THD = 76.3dBc  
Each Tone at  
-7dBFS Amplitude  
-20  
fIN1 = 185MHz  
-30  
fIN2 = 190MHz  
-40  
-40  
Two-Tone IMD = 90dBFS  
SFDR = 94dBFS  
-50  
-60  
-60  
-70  
-80  
-90  
-80  
-100  
-110  
-120  
-130  
-140  
-100  
-120  
100  
125  
125  
0
25  
50  
75  
0
25  
50  
75  
100  
Frequency (MHz)  
Frequency (GHz)  
Figure 61.  
Figure 62.  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
95  
90  
85  
80  
75  
70  
65  
60  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
67.5  
67.0  
66.5  
66.0  
65.5  
-2dBFS Input, 0dB Gain  
-1dBFS Input, 1dB Gain  
-1dBFS Input, 1dB Gain  
-2dBFS Input, 0dB Gain  
500  
500  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
Figure 63.  
Figure 64.  
(1) The ADS4129 is a product preview device.  
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ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
TYPICAL CHARACTERISTICS: ADS4129 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
ACROSS INPUT AMPLITUDES (CMOS)  
ACROSS INPUT AMPLITUDES (CMOS)  
90  
86  
82  
78  
74  
70  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
67.5  
67.0  
350  
350  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Input Frequency (MHz)  
Input Frequency (MHz)  
Figure 65.  
Figure 66.  
SFDR ACROSS GAIN AND INPUT FREQUENCY  
SINAD ACROSS GAIN AND INPUT FREQUENCY  
90  
71  
170MHz  
150MHz  
70  
69  
68  
67  
66  
65  
64  
63  
86  
82  
78  
74  
70  
66  
150MHz  
220MHz  
170MHz  
220MHz  
300MHz  
300MHz  
400MHz  
400MHz  
500MHz  
500MHz  
6.0  
6.0  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
Figure 67.  
Figure 68.  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
105  
95  
85  
75  
65  
55  
45  
35  
72.0  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
105  
95  
85  
75  
65  
55  
45  
35  
74  
73  
72  
71  
70  
69  
68  
67  
SFDR (dBFS)  
SFDR (dBFS)  
SNR (dBFS)  
SFDR (dBc)  
SFDR (dBc)  
SNR (dBFS)  
Input Frequency = 40.1MHz  
-20 -10 0  
Input Frequency = 170.1MHz  
-20 -10 0  
-50  
-40  
-30  
-50  
-40  
-30  
Input Amplitude (dBFS)  
Input Amplitude (dBFS)  
Figure 69.  
Figure 70.  
44  
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ADS4146, ADS4149  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4129 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE  
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY  
94  
72.0  
87  
Input Frequency = 40MHz  
AVDD = 1.8V  
92  
90  
88  
86  
84  
82  
80  
78  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
86  
85  
AVDD = 1.9V  
84  
SNR  
AVDD = 1.85V  
83  
82  
AVDD = 1.75V  
SFDR  
81  
AVDD = 1.7V  
fIN = 40MHz  
80  
1.10  
85  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
-40  
-15  
10  
35  
60  
Input Common-Mode Voltage (V)  
Temperature (°C)  
Figure 71.  
Figure 72.  
SNR ACROSS TEMPERATURE vs AVDD SUPPLY  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE  
72.0  
88  
72.0  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
fIN = 40MHz  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
87  
86  
85  
84  
83  
82  
SFDR  
SNR  
AVDD = 1.7V  
AVDD = 1.75V  
AVDD = 1.8V  
AVDD = 1.85V  
AVDD = 1.9V  
fIN = 40MHz  
1.90  
1.85  
1.70  
1.75  
1.80  
85  
-40  
-15  
10  
35  
60  
DRVDD Supply (V)  
Temperature (°C)  
Figure 73.  
Figure 74.  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE (CMOS)  
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE  
90  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
88  
87  
86  
85  
84  
83  
82  
72.0  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
SFDR (dBc)  
SFDR  
SNR  
SNR (dBFS)  
Input Frequency = 170MHz  
0.15 0.37 0.75 1.00 1.25 1.60 1.90 2.20 2.40 2.60  
1.90  
1.70  
1.75  
1.80  
1.85  
DRVDD Supply (V)  
Differential Clock Amplitude (VPP  
)
Figure 75.  
Figure 76.  
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ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
TYPICAL CHARACTERISTICS: ADS4129 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE  
INTEGRAL NONLINEARITY  
86  
73.0  
72.5  
72.0  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
0.3  
0.2  
85  
84  
83  
82  
81  
80  
79  
78  
0.1  
THD  
SNR  
0
-0.1  
-0.2  
-0.3  
Input Frequency = 10MHz  
25 30 35 40 45  
75  
4000  
50  
55  
60  
65  
70  
0
500 1000 1500 2000 2500 3000 3500  
Output Code (LSB)  
Input Clock Duty Cycle (%)  
Figure 77.  
Figure 78.  
DIFFERENTIAL NONLINEARITY  
0.3  
0.2  
0.1  
0
-0.1  
-0.2  
-0.3  
4000  
0
500 1000 1500 2000 2500 3000 3500  
Output Code (LSB)  
Figure 79.  
46  
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ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4126  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(1)  
FFT FOR 10MHz INPUT SIGNAL  
FFT FOR 170MHz INPUT SIGNAL  
0
-20  
0
-20  
SFDR = 94dBc  
SFDR = 82.5dBc  
SNR = 70dBFS  
SINAD = 70dBFS  
THD = 93dBc  
SNR = 69.2dBFS  
SINAD = 68.9dBFS  
THD = 80.7dBc  
-40  
-40  
-60  
-60  
-80  
-80  
-100  
-120  
-100  
-120  
80  
80  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
Frequency (MHz)  
Frequency (MHz)  
Figure 80.  
Figure 81.  
FFT FOR 300MHz INPUT SIGNAL  
FFT FOR TWO-TONE INPUT SIGNAL  
0
-20  
0
-10  
SFDR = 78.3dBc  
SNR = 67.6dBFS  
SINAD = 67dBFS  
THD = 75.3dBc  
Each Tone at -7dBFS Amplitude  
fIN1 = 185MHz  
-20  
fIN2 = 190MHz  
-30  
Two-Tone IMD = 89dBFS  
SFDR = 93dBFS  
-40  
-40  
-50  
-60  
-60  
-70  
-80  
-90  
-80  
-100  
-110  
-120  
-130  
-140  
-100  
-120  
80  
80  
0
10  
20  
30  
40  
50  
60  
70  
0
10  
20  
30  
40  
50  
60  
70  
Frequency (MHz)  
Frequency (MHz)  
Figure 82.  
Figure 83.  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
95  
90  
85  
80  
75  
70  
65  
60  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
67.5  
67.0  
66.5  
66.0  
65.5  
65.0  
-2dBFS Input, 0dB Gain  
-1dBFS Input, 1dB Gain  
-1dBFS Input, 1dB Gain  
-2dBFS Input, 0dB Gain  
500  
500  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
0
50 100 150 200 250 300 350 400 450  
Input Frequency (MHz)  
Figure 84.  
Figure 85.  
(1) The ADS4126 is a product preview device.  
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TYPICAL CHARACTERISTICS: ADS4126 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
SFDR vs INPUT FREQUENCY  
SNR vs INPUT FREQUENCY  
ACROSS INPUT AMPLITUDES (CMOS)  
ACROSS INPUT AMPLITUDES (CMOS)  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
68  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
67.5  
67.0  
350  
350  
0
50  
100  
150  
200  
250  
300  
0
50  
100  
150  
200  
250  
300  
Input Frequency (MHz)  
Input Frequency (MHz)  
Figure 86.  
Figure 87.  
SFDR ACROSS GAIN AND INPUT FREQUENCY  
SINAD ACROSS GAIN AND INPUT FREQUENCY  
88  
71  
170MHz  
150MHz  
170MHz  
70  
69  
68  
67  
66  
65  
64  
63  
62  
84  
80  
76  
72  
68  
64  
150MHz  
220MHz  
300MHz  
220MHz  
400MHz  
300MHz  
400MHz  
500MHz  
500MHz  
6.0  
6.0  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Gain (dB)  
Figure 88.  
Figure 89.  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
PERFORMANCE ACROSS INPUT AMPLITUDE (Single Tone)  
105  
95  
85  
75  
65  
55  
45  
35  
74  
73  
72  
71  
70  
69  
68  
67  
105  
95  
85  
75  
65  
55  
45  
35  
74  
73  
72  
71  
70  
69  
68  
67  
SFDR (dBFS)  
SFDR (dBFS)  
SNR (dBFS)  
SNR (dBFS)  
SFDR (dBc)  
SFDR (dBc)  
Input Frequency = 40.1MHz  
Input Frequency = 170.1MHz  
-20 -10 0  
-50  
-40  
-30  
-20  
-10  
0
-50  
-40  
-30  
Input Amplitude (dBFS)  
Input Amplitude (dBFS)  
Figure 90.  
Figure 91.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: ADS4126 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE  
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY  
90  
71.0  
88  
SNR  
87  
86  
88  
86  
84  
82  
80  
78  
70.5  
70.0  
69.5  
69.0  
68.5  
68.0  
AVDD = 1.85V  
AVDD = 1.8V  
AVDD = 1.9V  
85  
84  
83  
82  
81  
80  
SFDR  
AVDD = 1.75V  
fIN = 40MHz  
AVDD = 1.7V  
Input Frequency = 40MHz  
1.10  
85  
0.80  
0.85  
0.90  
0.95  
1.00  
1.05  
-40  
-15  
10  
35  
60  
Input Common-Mode Voltage (V)  
Temperature (°C)  
Figure 92.  
Figure 93.  
SNR ACROSS TEMPERATURE vs AVDD SUPPLY  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE  
72.0  
87  
73.0  
72.5  
72.0  
71.5  
71.0  
70.5  
70.0  
fIN = 40MHz  
86  
85  
84  
83  
82  
81  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
SFDR  
AVDD = 1.7V, 1.85V  
AVDD = 1.75V, 1.8V, 1.9V  
SNR  
fIN = 40MHz  
1.90  
1.85  
1.70  
1.75  
1.80  
85  
-40  
-15  
10  
35  
60  
DRVDD Supply (V)  
Temperature (°C)  
Figure 94.  
Figure 95.  
PERFORMANCE ACROSS DRVDD SUPPLY VOLTAGE (CMOS)  
PERFORMANCE ACROSS INPUT CLOCK AMPLITUDE  
90  
78  
76  
74  
72  
70  
68  
66  
64  
62  
60  
87  
86  
85  
84  
83  
82  
81  
73.0  
72.5  
72.0  
71.5  
71.0  
70.5  
70.0  
86  
82  
78  
74  
70  
66  
62  
58  
54  
SFDR (dBc)  
SFDR  
SNR (dBFS)  
SNR  
Input Frequency = 170MHz  
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3  
1.90  
1.70  
1.75  
1.80  
1.85  
DRVDD Supply (V)  
Differential Clock Amplitude (VPP  
)
Figure 96.  
Figure 97.  
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TYPICAL CHARACTERISTICS: ADS4126 (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.(2)  
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE  
INTEGRAL NONLINEARITY  
86  
72.0  
71.5  
71.0  
70.5  
70.0  
69.5  
69.0  
0.3  
0.2  
85  
84  
83  
82  
81  
80  
0.1  
SNR  
0
THD  
-0.1  
-0.2  
-0.3  
Input Frequency = 10MHz  
75  
4000  
25  
30  
35  
40  
45  
50  
55  
60  
65  
70  
0
500 1000 1500 2000 2500 3000 3500  
Output Code (LSB)  
Input Clock Duty Cycle (%)  
Figure 98.  
Figure 99.  
DIFFERENTIAL NONLINEARITY  
0.20  
0.15  
0.10  
0.05  
0
-0.05  
-0.10  
-0.15  
-0.20  
4000  
0
500 1000 1500 2000 2500 3000 3500  
Output Code (LSB)  
Figure 100.  
50  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: COMMON  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
CMRR ACROSS FREQUENCY  
CMRR SPECTRUM  
-20  
-25  
0
-20  
Input Frequency = 70MHz  
50mVPP Signal Superimposed  
on Input Common-Mode Voltage  
fIN = 70MHz  
fCM = 10MHz, 100mVPP  
SFDR = 81dBc  
fIN = 70MHz  
Amplitude (fIN) = -1dBFS  
Amplitude (fCM) = -74dBFS  
Amplitude (fIN + fCM) = -87dBFS  
Amplitude (fIN - fCM) = -86dBFS  
-30 (0.95V)  
-40  
fIN - fCM = 60MHz  
-35  
-40  
-45  
-50  
-55  
-60  
fIN + fCM = 80MHz  
-80  
fCM = 10MHz  
-100  
-120  
-140  
-60  
0
50  
100  
150  
200  
250  
300  
125  
0
25  
50  
75  
100  
Frequency of Input Common-Mode Signal (MHz)  
Frequency (MHz)  
Figure 101.  
Figure 102.  
PSRR ACROSS FREQUENCY  
ZOOMED VIEW OF SPECTRUM WITH PSRR SIGNAL  
-20  
-25  
-30  
-35  
-40  
-45  
-50  
-55  
0
fIN = 10MHz  
fPSRR = 1MHz  
Amplitude (fIN) = -1dBFS  
fIN  
Input Frequency = 10MHz  
50mVPP Signal Applied on AVDD  
-20  
-40  
Amplitude (fPSRR) = -81dBFS  
Amplitude (fIN + fPSRR) = -67.7dBFS  
Amplitude (fIN - fPSRR) = -68.8dBFS  
fIN - fPSRR  
-60  
fIN + fPSRR  
-80  
fPSRR  
PSRR (dB) on AVDD Supply  
-100  
-120  
-140  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
50  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
Frequency of Signal on AVDD (MHz)  
Frequency (MHz)  
Figure 103.  
Figure 104.  
POWER ACROSS SAMPLING FREQUENCY  
DRVDD CURRENT ACROSS SAMPLING FREQUENCY  
200  
180  
160  
140  
120  
100  
80  
70  
AVDD Power (mW)  
60  
LVDS, 350mV Swing  
50  
LVDS, 200mV Swing  
40  
30  
20  
DRVDD Power  
200mV LVDS  
60  
CMOS, 8pF Load Capacitor  
10  
40  
DRVDD Power  
350mV LVDS  
20  
CMOS, 6pF Load Capacitor  
0
0
0
25  
50  
75 100 125 150 175 200 225 250  
Sampling Frequency (MSPS)  
0
25  
50  
75 100 125 150 175 200 225 250  
Sampling Frequency (MSPS)  
Figure 105.  
Figure 106.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
TYPICAL CHARACTERISTICS: CONTOUR  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (1dB Gain)  
Applies to ADS414x and ADS412x  
250  
88  
86  
84  
78  
82  
84  
240  
220  
200  
180  
160  
140  
120  
100  
82  
84  
70  
82  
74  
84  
86  
84  
66  
84  
86  
78  
88  
82  
82  
78  
70  
74  
86  
88  
84  
82  
74  
66  
84  
70  
88  
88  
74  
70  
80  
65  
88  
62  
78  
66  
86  
10  
50  
100  
150  
200  
250  
300  
350  
80  
400  
450  
500  
90  
fIN - Input Frequency - MHz  
60  
65  
70  
75  
85  
SFDR - dBFS  
Figure 107.  
SFDR ACROSS INPUT AND SAMPLING FREQUENCIES (6dB Gain)  
Applies to ADS414x and ADS412x  
250  
240  
86  
72  
84  
82  
76  
86  
80  
220  
200  
180  
160  
140  
120  
100  
84  
82  
84  
68  
84  
72  
82  
82  
84  
80  
76  
86  
88  
84  
82  
86  
76  
80  
86  
86  
72  
88  
72  
88  
84  
88  
76  
80  
65  
86  
64  
80  
82  
84  
72  
250  
10  
50  
100  
150  
200  
300  
350  
400  
450  
500  
90  
fIN - Input Frequency - MHz  
60  
65  
70  
75  
80  
85  
SFDR - dBFS  
Figure 108.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
TYPICAL CHARACTERISTICS: CONTOUR (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES  
(1dB Gain)  
250  
68  
240  
220  
200  
180  
160  
140  
120  
100  
71  
69  
70  
71.5  
70.5  
67  
68  
71  
70  
71.5  
69  
72  
70.5  
67  
70  
66  
68  
71  
69  
71.5  
100  
72  
80  
65  
70  
72.5  
67  
70.5  
65  
66  
68  
200  
fIN - Input Frequency - MHz  
64  
10  
63  
50  
150  
250  
300  
350  
70  
400  
71  
450  
72  
500  
73  
64  
65  
66  
67  
68  
69  
SNR - dBFS  
Figure 109.  
ADS414x: SNR ACROSS INPUT AND SAMPLING FREQUENCIES  
(6dB Gain)  
250  
240  
66  
65  
67  
66.5  
65.5  
220  
200  
180  
160  
140  
120  
100  
66.5  
67  
65  
66  
67.5  
65.5  
67  
66.5  
65  
66.5  
66  
67.5  
65.5  
67  
80  
65  
64.5  
400  
66  
65  
65.5  
64  
63.5  
450  
10  
62  
50  
100  
150  
200  
250  
300  
350  
500  
68  
fIN - Input Frequency - MHz  
63  
64  
65  
66  
67  
SNR - dBFS  
Figure 110.  
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www.ti.com  
TYPICAL CHARACTERISTICS: CONTOUR (continued)  
At +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock  
amplitude, 50% clock duty cycle, –1dBFS differential analog input, 1dB gain, low-latency mode, DDR LVDS output interface,  
and 32k-point FFT, unless otherwise noted. Note that after reset, the device is in 0dB gain mode.  
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES  
(1dB Gain)  
250  
69.5  
240  
220  
200  
180  
160  
140  
120  
100  
68.5  
67  
69  
68  
68.5  
66  
69.5  
70  
69  
67  
68  
68.5  
66  
69.5  
70  
67  
69  
80  
65  
68  
68.5  
66  
350  
65  
67  
200  
fIN - Input Frequency - MHz  
64  
10  
62  
50  
100  
150  
250  
300  
400  
450  
500  
71  
63  
64  
65  
66 67  
68  
69  
70  
SNR - dBFS  
Figure 111.  
ADS412x SNR ACROSS INPUT AND SAMPLING FREQUENCIES  
(6dB Gain)  
250  
240  
66  
65  
65.5  
64.5  
220  
200  
180  
160  
140  
120  
100  
66  
66.5  
65.5  
66  
65  
64.5  
66.5  
67  
65.5  
65  
66  
64  
65.5  
64.5  
80  
65  
63.5  
66  
150  
67  
65  
63  
10  
62  
50  
100  
200  
250  
300  
350  
400  
450  
500  
68  
fIN - Input Frequency - MHz  
63  
64  
65  
66  
67  
SNR - dBFS  
Figure 112.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
APPLICATION INFORMATION  
THEORY OF OPERATION  
The ADS414x/2x is a family of high-performance and low-power 12-bit and 14-bit ADCs with maximum sampling  
rates up to 250MSPS. The conversion process is initiated by a rising edge of the external input clock and the  
analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution  
stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates  
through the pipeline, resulting in a data latency of 10 clock cycles. The output is available as 14-bit data or 12-bit  
data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement  
format.  
ANALOG INPUT  
The analog input consists of a switched-capacitor-based, differential, sample-and-hold architecture. This  
differential topology results in very good ac performance even for high input frequencies at high sampling rates.  
The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the  
VCM pin. For a full-scale differential input, each input INP and INM pin must swing symmetrically between (VCM  
+ 0.5V) and (VCM – 0.5V), resulting in a 2VPP differential input swing. The input sampling circuit has a high 3dB  
bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 113 shows  
an equivalent circuit for the analog input.  
Sampling  
Switch  
LPKG  
Sampling  
Capacitor  
2nH  
10W  
RCR Filter  
INP  
RON  
CBOND  
1pF  
CPAR2  
1pF  
CSAMP  
2pF  
100W  
15W  
RESR  
3pF  
200W  
CPAR1  
0.5pF  
RON  
15W  
3pF  
LPKG  
2nH  
CSAMP  
2pF  
100W  
RON  
15W  
INM  
CBOND  
1pF  
CPAR2  
1pF  
Sampling  
Capacitor  
RESR  
Sampling  
Switch  
200W  
Figure 113. Analog Input Equivalent Circuit  
Drive Circuit Requirements  
For optimum performance, the analog inputs must be driven differentially. This technique improves the  
common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input  
pin is recommended to damp out ringing caused by package parasitics. It is also necessary to present low  
impedance (less than 50Ω) for the common-mode switching currents. This impedance can be achieved by using  
two resistors from each input terminated to the common-mode voltage (VCM).  
Note that the device includes an internal R-C filter from each input to ground. The purpose of this filter is to  
absorb the glitches caused by the opening and closing of the sampling capacitors. The cutoff frequency of the  
R-C filter involves a trade-off. A lower cutoff frequency (larger C) absorbs glitches better, but also reduces the  
input bandwidth and the maximum input frequency that can be supported. On the other hand, with no internal  
R-C filter, high input frequency can be supported but now the sampling glitches must be supplied by the external  
driving circuit. The inductance of the package bond wires limits the ability of the external driving circuit to support  
the sampling glitches.  
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In the ADS414x/2x, the R-C component values have been optimized while supporting high input bandwidth  
(550MHz). However, in applications where very high input frequency support is not required, filtering of the  
glitches can be improved further with an external R-C-R filter; see Figure 116 and Figure 117).  
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency  
range and matched impedance to the source. While designing the drive circuit, the ADC impedance must be  
considered. Figure 114 and Figure 115 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.  
100.00  
10.00  
1.00  
0.10  
0.01  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0  
Input Frequency (GHz)  
Figure 114. ADC Analog Input Resistance (RIN) Across Frequency  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0  
Input Frequency (GHz)  
Figure 115. ADC Analog Input Capacitance (CIN) Across Frequency  
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Driving Circuit  
Two example driving circuit configurations are shown in Figure 116 and Figure 117—one optimized for low  
bandwidth (tlow input frequencies) and the other one for high bandwidth to support higher input frequencies. In  
Figure 116, an external R-C-R filter with 3.3pF is used to help absorb sampling glitches. The R-C-R filter limits  
the bandwidth of the drive circuit, making it suitable for low input frequencies (up to 250MHz). Transformers such  
as ADT1-1WT or WBC1-1 can be used up to 250MHz.  
For higher input frequencies, the R-C-R filter can be dropped. Together with the lower series resistors (5Ω to  
10Ω), this drive circuit provides higher bandwidth to support frequencies up to 500MHz (as shown in Figure 117).  
A transmission line transformer such as ADTL2-18 can be used.  
Note that both the drive circuits have been terminated by 50Ω near the ADC side. The termination is  
accomplished by a 25Ω resistor from each input to the 0.95V common-mode (VCM) from the device. This  
termination allows the analog inputs to be biased around the required common-mode voltage.  
3.6nH  
10W to 15W  
INP  
T2  
T1  
0.1mF  
25W  
25W  
50W  
0.1mF  
RIN  
CIN  
3.3pF  
50W  
INM  
VCM  
1:1  
1:1  
10W to 15W  
3.6nH  
ADS41xx  
Figure 116. Drive Circuit with Low Bandwidth (for Low Input Frequencies)  
5W to 10W  
INP  
T2  
T1  
0.1mF  
25W  
25W  
0.1mF  
RIN  
CIN  
INM  
1:1  
1:1  
5W to 10W  
VCM  
ADS41xx  
Figure 117. Drive Circuit with High Bandwidth (for High Input Frequencies)  
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The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order  
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and  
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be  
required between the two transformers, as shown in Figure 116 and Figure 117. The center point of this  
termination is connected to ground to improve the balance between the P (positive) and M (negative) sides. The  
values of the terminations between the transformers and on the secondary side must be chosen to obtain an  
effective 50Ω (for a 50Ω source impedance).  
Figure 116 and Figure 117 use 1:1 transformers with a 50Ω source. As explained in the Drive Circuit  
Requirements section, this architecture helps to present a low source impedance to absorb sampling glitches.  
With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to absorb the  
sampling glitches effectively and can lead to degradation in performance (compared to using 1:1 transformers).  
In almost all cases, either a bandpass or low-pass filter is needed to get the desired dynamic performance, as  
shown in Figure 118. Such a filter presents low source impedance at the high frequencies corresponding to the  
sampling glitch and helps avoid the performance loss with the high source impedance.  
10W  
INP  
100W  
0.1mF  
Bandpass or  
Low-Pass  
Filter  
Differential  
Input Signal  
ADS41xx  
100W  
INM  
10W  
VCM  
Figure 118. Drive Circuit with 1:4 Transformer  
Input Common-Mode  
To ensure a low-noise, common-mode reference, the VCM pin is filtered with a 0.1µF low-inductance capacitor  
connected to ground. The VCM pin is designed to directly drive the ADC inputs. Each ADC input pin sinks a  
common-mode current of approximately 0.6µA per MSPS of clock frequency.  
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CLOCK INPUT  
The ADS414x/2x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),  
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to  
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave  
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 119 shows an equivalent circuit for the input  
clock.  
Clock Buffer  
LPKG  
1nH  
20W  
CLKP  
CBOND  
CEQ  
CEQ  
5kW  
1pF  
RESR  
100W  
2pF  
VCM  
LPKG  
1nH  
5kW  
20W  
CLKM  
CBOND  
1pF  
RESR  
100W  
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.  
Figure 119. Input Clock Equivalent Circuit  
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1mF  
capacitor, as shown in Figure 120. For best performance, the clock inputs must be driven differentially, reducing  
susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock  
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no  
change in performance with a non-50% duty cycle clock input. Figure 121 shows a differential circuit.  
0.1mF  
CMOS  
0.1mF  
CLKP  
Clock Input  
CLKP  
Differential Sine-Wave,  
PECL, or LVDS  
Clock Input  
VCM  
0.1mF  
0.1mF  
CLKM  
CLKM  
Figure 120. Single-Ended Clock Driving Circuit  
Figure 121. Differential Clock Driving Circuit  
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DIGITAL FUNCTIONS AND LOW LATENCY MODE  
The device has several useful digital functions such as test patterns, gain, and offset correction. All of these  
functions require extra clock cycles for operation and increase the overall latency and power of the device.  
Alternately, the device has a low-latency mode in which the raw ADC output is routed to the output data pins with  
a latency of 10 clock cycles. In this mode, the digital functions are bypassed. Figure 122 shows more details of  
the processing after the ADC.  
The device is in low-latency mode after reset. In order to use any of the digital functions, first the low-latency  
mode must be disabled by setting the DIS LOW LATENCY register bit to '1'. After this, the respective register bits  
must be programmed as described in the following sections and in the Serial Register Map section.  
Output  
Interface  
14-Bit  
ADC  
14b  
14b  
Digital Functions  
(Gain, Offset Correction, Test Patterns)  
DDR LVDS  
or CMOS  
DIS LOW LATENCY Pin  
Figure 122. Digital Processing Block Diagram  
FINE GAIN FOR SFDR/SNR TRADE-OFF  
The ADS414x/2x include gain settings that can be used to get improved SFDR performance. The gain is  
programmable from 0dB to 6dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog  
input full-scale range scales proportionally, as shown in Table 11.  
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades  
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,  
the fine gain is very useful at high input frequencies because the SFDR improvement is significant with marginal  
degradation in SNR. Therefore, the fine gain can be used to trade-off between SFDR and SNR.  
After a reset, the device is in low-latency mode and gain function is disabled. To use fine gain:  
•
•
•
First, disable the low-latency mode (DIS LOW LATENCY = 1).  
This setting enables the gain and puts the device in a 0dB gain mode.  
For other gain settings, program the GAIN bits.  
Table 11. Full-Scale Range Across Gains  
GAIN (dB)  
TYPE  
FULL-SCALE (VPP)  
0
1
2
3
4
5
6
Default after reset  
Fine, programmable  
Fine, programmable  
Fine, programmable  
Fine, programmable  
Fine, programmable  
Fine, programmable  
2
1.78  
1.59  
1.42  
1.26  
1.12  
1.00  
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OFFSET CORRECTION  
The ADS414x/2x has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV.  
The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm  
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction  
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR  
TIME CONSTANT register bits, as described in Table 12.  
Table 12. Time Constant of Offset Correction Loop  
TIME CONSTANT, TCCLK  
(Number of Clock Cycles)  
OFFSET CORR TIME CONSTANT  
TIME CONSTANT, TCCLK × 1/fS (sec)(1)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
1M  
2M  
4ms  
8ms  
4M  
16.7ms  
33.5ms  
67ms  
134ms  
268ms  
537ms  
1.1s  
8M  
16M  
32M  
64M  
128M  
256M  
512M  
1G  
2.15s  
4.3s  
2G  
8.6s  
Reserved  
Reserved  
Reserved  
Reserved  
—
—
—
—
(1) Sampling frequency, fS = 250MSPS.  
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,  
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is  
disabled by a default after reset.  
After a reset, the device is in low-latency mode and offset correction is disabled. To use offset correction:  
•
•
First, disable the low-latency mode (DIS LOW LATENCY = 1).  
Then set EN OFFSET CORR to '1' and program the required time constant.  
Figure 123 shows the time response of the offset correction algorithm after it is enabled.  
OFFSET CORRECTION  
Time Response  
8200  
8190  
8180  
8170  
8181  
Offset of  
10 LSBs  
8192  
Final converged value  
Offset correction  
converges to output  
code of 8192  
8160  
8150  
Offset correction  
begins  
8140  
8130  
8120  
8110  
8100  
8090  
8080  
8070  
8060  
8050  
-5  
5
15 25 35 45 55 65 75 85 95 105  
Time (ms)  
Figure 123. Time Response of Offset Correction  
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POWER DOWN  
The ADS414x/2x has three power-down modes: power-down global, standby, and output buffer disable.  
Power-Down Global  
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) are powered down,  
resulting in reduced total power dissipation of about 10mW. The output buffers are in a high-impedance state.  
The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To  
enter the global power-down mode, set the PDN GLOBAL register bit.  
Standby  
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up  
time of 5µs. The total power dissipation in standby mode is approximately 185mW. To enter the standby mode,  
set the STBY register bit.  
Output Buffer Disable  
The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,  
approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.  
Input Clock Stop  
In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The  
power dissipation is approximately 80mW.  
POWER-SUPPLY SEQUENCE  
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are  
separated in the device. Externally, they can be driven from separate supplies or from a single supply.  
DIGITAL OUTPUT INFORMATION  
The ADS414x/2x provide either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the  
data.  
Output Interface  
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be  
selected using the LVDS CMOS serial interface register bit or using the DFS pin.  
DDR LVDS Outputs  
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits  
are multiplexed and output on each LVDS differential pair, as shown in Figure 124 and Figure 125.  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
Pins  
Pins  
CLKOUTP  
CLKOUTM  
Output Clock  
CLKOUTP  
Output Clock  
CLKOUTM  
D0_D1_P  
D0_D1_M  
Data Bits D0, D1  
Data Bits D2, D3  
Data Bits D4, D5  
Data Bits D6, D7  
Data Bits D8, D9  
Data Bits D10, D11  
D0_D1_P  
Data Bits D0, D1  
D0_D1_M  
D2_D3_P  
D2_D3_M  
D2_D3_P  
Data Bits D2, D3  
D2_D3_M  
D4_D5_P  
D4_D5_M  
D4_D5_P  
12-Bit  
ADC Data  
Data Bits D4, D5  
14-Bit  
ADC Data  
D4_D5_M  
D6_D7_P  
D6_D7_M  
D6_D7_P  
Data Bits D6, D7  
D6_D7_M  
D8_D9_P  
D8_D9_M  
D8_D9_P  
Data Bits D8, D9  
D8_D9_M  
D10_D11_P  
D10_D11_M  
D10_D11_P  
Data Bits D10, D11  
D10_D11_M  
ADS4129  
D12_D13_P  
Data Bits D12, D13  
Figure 124. ADS412x LVDS Data Outputs  
D12_D13_M  
ADS4149  
Figure 125. ADS414x LVDS Data Outputs  
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Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5,  
etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to  
capture all 14 data bits, as shown in Figure 126.  
CLKOUTP  
CLKOUTM  
D0_D1_P,  
D0_D1_M  
D0  
D2  
D4  
D1  
D3  
D5  
D0  
D2  
D4  
D1  
D3  
D5  
D2_D3_P,  
D2_D3_M  
D4_D5_P,  
D4_D5_M  
D6_D7_P,  
D6_D7_M  
D6  
D8  
D7  
D9  
D6  
D8  
D7  
D9  
D8_D9_P,  
D8_D9_M  
D10_D11_P,  
D10_D11_M  
D10  
D11  
D10  
D11  
D12_D13_P,  
D12_D13_M  
D12  
D13  
D12  
D13  
Sample N  
Sample N + 1  
Figure 126. DDR LVDS Interface  
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LVDS Output Data and Clock Buffers  
The equivalent circuit of each LVDS output buffer is shown in Figure 127. After reset, the buffer presents an  
output impedance of 100Ω to match with the external 100Ω termination.  
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.  
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.  
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This  
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω  
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH  
register bits for data and output clock buffers, respectively.  
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing  
reflections from the receiver end, it helps to improve signal integrity.  
VDIFF  
High  
Low  
OUTP  
OUTM  
External  
100W Load  
1.1V  
ROUT  
VDIFF  
High  
Low  
NOTE: Use the default buffer strength to match 100Ω external termination (ROUT = 100Ω). To match with a 50Ω external termination, set the  
LVDS STRENGTH bit (ROUT = 50Ω).  
Figure 127. LVDS Buffer Equivalent Circuit  
Parallel CMOS Interface  
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The  
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 128 depicts the CMOS  
output interface.  
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.  
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this  
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength  
ensures a wide data stable window (even at 250MSPS) is provided so the data outputs have minimal load  
capacitance. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less  
than 5pF load capacitance, as shown in Figure 129.  
For sampling frequencies greater than 200MSPS, it is recommended to use an external clock to capture data.  
The delay from input clock to output data and the data valid times are specified for higher sampling frequencies.  
These timings can be used to delay the input clock appropriately and use it to capture data.  
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Pins  
OVR  
CLKOUT  
D0  
D1  
D2  
D3  
14-Bit  
ADC Data  
D11  
D12  
D13  
ADS4149  
Figure 128. CMOS Output Interface  
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Use External Clock Buffer  
(> 200MSPS)  
Input Clock  
Receiver (FPGA, ASIC, etc.)  
Flip-Flops  
CLKIN  
CLKOUT  
D0  
D1  
D2  
D0_In  
D1_In  
D2_In  
14-Bit ADC Data  
D12  
D13  
D12_In  
D13_In  
ADS4149  
Use short traces between  
ADC output and receiver pins (1 to 2 inches).  
Figure 129. Using the CMOS Data Outputs  
CMOS Interface Power Dissipation  
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every  
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock  
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined  
by the average number of output bits switching, which is a function of the sampling frequency and the nature of  
the analog input signal.  
Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG  
)
where:  
CL = load capacitance,  
N × FAVG = average number of output bits switching.  
(1)  
Figure 106 shows the current across sampling frequencies at 2 MHz analog input frequency.  
Input Over-Voltage Indication (OVR Pin)  
The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the  
sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR  
remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off  
DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).  
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For a positive overload, the D[13:0] output data bits are 0x3FFF in offset binary output format and 0x1FFF in  
twos complement output format. For a negative input overload, the output code is 0x0000 in offset binary output  
format and 0x2000 in twos complement output format.  
Output Data Format  
Two output data formats are supported: twos complement and offset binary. They can be selected using the  
DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event  
of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.  
BOARD DESIGN CONSIDERATIONS  
Grounding  
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of  
the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout  
and grounding.  
Supply Decoupling  
Because the ADS414x/2x already include internal decoupling, minimal external decoupling can be used without  
loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum  
number of capacitors depends on the actual application. The decoupling capacitors should be placed very close  
to the converter supply pins.  
Exposed Pad  
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the  
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and  
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and  
QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).  
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SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
DEFINITION OF SPECIFICATIONS  
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with  
respect to the low-frequency value.  
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at  
which the sampling occurs. This delay is different across channels. The maximum variation is specified as  
aperture delay variation (channel-to-channel).  
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.  
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains  
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a  
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.  
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric  
testing is performed at this sampling rate unless otherwise noted.  
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.  
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly  
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.  
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined  
by a least squares curve fit of that transfer function, measured in units of LSBs.  
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain  
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a  
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as  
EGREF and EGCHAN  
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN  
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal  
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle  
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.  
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the  
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation  
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN  
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),  
excluding the power at dc and the first nine harmonics.  
PS  
SNR = 10Log10  
PN  
(2)  
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the  
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter  
full-scale range.  
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power  
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.  
PS  
SINAD = 10Log10  
PN + PD  
(3)  
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the  
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter  
full-scale range.  
Copyright © 2009–2010, Texas Instruments Incorporated  
Submit Documentation Feedback  
69  
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ADS4126, ADS4129  
ADS4146, ADS4149  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
www.ti.com  
Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the  
theoretical limit based on quantization noise.  
SINAD - 1.76  
ENOB =  
6.02  
(4)  
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the  
first nine harmonics (PD).  
PS  
THD = 10Log10  
PN  
(5)  
THD is typically given in units of dBc (dB to carrier).  
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other  
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).  
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1  
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given  
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB  
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.  
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change  
in analog supply voltage. The dc PSRR is typically given in units of mV/V.  
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the  
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the  
ADC output code (referred to the input), then:  
DVOUT  
PSRR = 20Log10  
(Expressed in dBc)  
DVSUP  
(6)  
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an  
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and  
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.  
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input  
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is  
the resulting change of the ADC output code (referred to the input), then:  
DVOUT  
10  
CMRR = 20Log  
(Expressed in dBc)  
DVCM  
(7)  
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an  
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate  
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually  
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the  
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the  
adjacent channel input. It is typically expressed in dBc.  
70  
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Copyright © 2009–2010, Texas Instruments Incorporated  
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
ADS4126, ADS4129  
ADS4146, ADS4149  
www.ti.com  
SBAS483D – NOVEMBER 2009–REVISED APRIL 2010  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision C (March 2010) to Revision D  
Page  
•
Updated Figure 106 ............................................................................................................................................................ 51  
Copyright © 2009–2010, Texas Instruments Incorporated  
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71  
Product Folder Link(s): ADS4126 ADS4129 ADS4146 ADS4149  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
Samples Not Available  
Call Local Sales Office  
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Samples Not Available  
Call Local Sales Office  
Call Local Sales Office  
Samples Not Available  
Call Local Sales Office  
Call Local Sales Office  
Purchase Samples  
ADS4126IRGZ25  
ADS4126IRGZR  
ADS4126IRGZT  
ADS4129IRGZ25  
ADS4129IRGZR  
ADS4129IRGZT  
ADS4146IRGZ25  
ADS4146IRGZR  
ADS4146IRGZT  
ADS4149IRGZ25  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
PREVIEW  
ACTIVE  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
VQFN  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
RGZ  
48  
48  
48  
48  
48  
48  
48  
48  
48  
48  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
Call TI  
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2500  
250  
2500  
250  
2500  
250  
25  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
CU NIPDAU Level-3-260C-168 HR  
ADS4149IRGZR  
ADS4149IRGZT  
ACTIVE  
ACTIVE  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
Green (RoHS  
& no Sb/Br)  
Purchase Samples  
Green (RoHS  
& no Sb/Br)  
Request Free Samples  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
28-May-2010  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
ADS4149IRGZR  
ADS4149IRGZT  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
330.0  
330.0  
16.4  
16.4  
7.3  
7.3  
7.3  
7.3  
1.5  
1.5  
12.0  
12.0  
16.0  
16.0  
Q2  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
20-Jul-2010  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
ADS4149IRGZR  
ADS4149IRGZT  
VQFN  
VQFN  
RGZ  
RGZ  
48  
48  
2500  
250  
333.2  
333.2  
345.9  
345.9  
28.6  
28.6  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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