ADS41B25IRGZT [TI]
12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer; 12位， 125MSPS ，超低功耗ADC模拟缓冲器
| 型号： | ADS41B25IRGZT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer |
| 文件： | 总57页 (文件大小：1322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS41B25
www.ti.com
SBAS548 –JUNE 2011
12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer
Check for Samples: ADS41B25
1
FEATURES
DESCRIPTION
The ADS41B25 is a member of the ultralow-power
ADS4xxx analog-to-digital converter (ADC) family,
featuring integrated analog input buffers. This device
uses innovative design techniques to achieve high
dynamic performance, while consuming extremely
low power. The analog input pins have buffers, with
the benefits of constant performance and input
impedance across a wide frequency range. The
device is well-suited for multi-carrier, wide bandwidth
23
•
Resolution: 12-Bit, 125MSPS
Integrated High-Impedance
Analog Input Buffer:
•
–
–
Input Capacitance at dc: 3.5pF
Input Resistance at dc: 10kΩ
•
•
Maximum Sample Rate: 125MSPS
Ultralow Power:
–
–
–
1.8V Analog Power: 114mW
3.3V Buffer Power: 96mW
I/O Power: 100mW (DDR LVDS)
communications
linearization.
applications
such
as
PA
The ADS41B25 has features such as digital gain and
offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
•
•
High Dynamic Performance:
–
–
SNR: 68.3dBFS at 170MHz
SFDR: 87dBc at 170MHz
Output Interface:
–
Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
–
–
–
–
Standard Swing: 350mV
Low Swing: 200mV
Default Strength: 100Ω Termination
2x Strength: 50Ω Termination
The device supports both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
makes it possible to use low-cost field-programmable
gate array (FPGA)-based receivers. The device has a
low-swing LVDS mode that can be used to further
reduce the power consumption. The strength of the
LVDS output buffers can also be increased to support
50Ω differential termination.
–
1.8V Parallel CMOS Interface Also
Supported
•
•
•
•
Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)
The device is available in a compact QFN-48
package and is specified over the industrial
temperature range (–40°C to +85°C).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS41B25
SBAS548 –JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
LEAD/BALL PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
ECO PLAN(2)
FINISH
MARKING
ADS41B25IRGZR
ADS41B25IRGZT
Tape and reel
Tape and reel
GREEN (RoHS,
no Sb/Br)
ADS41B25
QFN-48
RGZ
–40°C to +85°C
Cu/NiPdAu
AZ41B25
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
ABSOLUTE MAXIMUM RATINGS(1)
ADS41B25
MIN
–0.3
–0.3
–0.3
–0.3
–2.4
–2.4
–4.2
MAX
2.1
3.9
2.1
0.3
2.4
2.4
4.2
UNIT
V
Supply voltage range, AVDD
Supply voltage range, AVDD_BUF
V
Supply voltage range, DRVDD
V
Voltage between AGND and DRGND
V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
Voltage between AVDD_BUF to DRVDD/AVDD
V
V
V
Minimum
(1.9, AVDD + 0.3)
INP, INM
–0.3
V
V
Voltage applied to input pins
CLKP, CLKM(2), RESET, SCLK,
SDATA, SEN, DFS
–0.3
–40
AVDD + 0.3
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, Tstg
+85
+125
+150
2
°C
°C
°C
kV
–65
ESD, human body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|.
Doing so prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS41B25
THERMAL METRIC(1)
RGZ
48 PINS
27.9
15.1
5.4
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
5.4
θJCbot
1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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SBAS548 –JUNE 2011
RECOMMENDED OPERATING CONDITIONS
ADS41B25
TYP
MIN
MAX
UNIT
SUPPLIES
AVDD
Analog supply voltage
Analog buffer supply voltage
Digital supply voltage
1.7
3
1.8
3.3
1.8
1.9
3.6
1.9
V
V
V
AVDD_BUF
DRVDD
1.7
ANALOG INPUTS
Differential input voltage range(1)
1.5
1.7 ± 0.05
400
VPP
V
Input common-mode voltage
Maximum analog input frequency with 1.5VPP input amplitude(2)
Maximum analog input frequency with 1VPP input amplitude(2)
CLOCK INPUT
MHz
MHz
600
Low-speed mode enabled(3)
Low-speed mode disabled(3)
20
80
80
MSPS
MSPS
125
Input clock amplitude differential (VCLKP – VCLKM
)
Sine wave, ac-coupled
0.2
1.5
1.6
0.7
1.8
50
VPP
VPP
VPP
V
LVPECL, ac-coupled
LVDS, ac-coupled
LVCMOS, single-ended, ac-coupled
Low-speed mode enabled
40
35
60
65
%
Input clock duty
cycle
Low-speed mode disabled
50
%
DIGITAL OUTPUTS
CLOAD
RLOAD
TA
Maximum external load capacitance from each output pin to DRGND
5
pF
Ω
Differential load resistance between the LVDS output pairs
(LVDS mode)
100
Operating free-air temperature
–40
+85
°C
(1) With 0dB gain. See the Gain for SFDR/SNR Trade-Off section in Application Information for the relationship between input voltage range
and gain.
(2) See the Theory of Operation section in the Application Information.
(3) See the Serial Interface section for details on the low-speed mode.
HIGH-PERFORMANCE MODES(1)(2)(3)
PARAMETER
MODE 1
MODE 2
DESCRIPTION
Set the MODE 1 register bits to get the best performance across sample clock and input signal frequencies.
Register address = 03h, register data = 03h.
Set the MODE 2 register bit to get the best performance at high input signal frequencies greater than 230MHz.
Register address = 4Ah, register data = 01h.
(1) It is recommended to use these modes to get best performance. These modes can only be set with the serial interface.
(2) See the Serial Interface section for details on register programming.
(3) Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Device
Configuration section.
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ELECTRICAL CHARACTERISTICS: ADS41B25
Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 1.5VPP clock amplitude, 50% clock duty
cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are
across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V.
ADS41B25
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bits
Resolution
12
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
68.8
68.7
68.6
68.3
67
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
66.5
SNR (signal-to-noise ratio), LVDS
68.8
68.6
68.5
68.2
65.4
89
65.5
SINAD
(signal-to-noise and distortion ratio), LVDS
78
88
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
Third-harmonic distortion
SFDR
THD
HD2
HD3
89
dBc
87
dBc
71
dBc
86
dBc
77
86
dBc
85
dBc
83
dBc
69
dBc
89
dBc
78
88
dBc
89
dBc
90
dBc
78
dBc
100
93
dBc
78
dBc
91
dBc
87
dBc
71
dBc
93
dBc
82.5
94
dBc
Worst spur
(other than second and third harmonics)
94
dBc
95
dBc
91
dBc
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
Two-tone intermodulation distortion
Input overload recovery
IMD
–86
1
dBFS
Clock cycle
dB
Recovery to within 1% (of final value) for
6dB overload with sine-wave input
For 100mVPP signal on AVDD supply,
up to 10MHz
AC power-supply rejection ratio
PSRR
30
Effective number of bits
Integrated nonlinearity
ENOB
INL
fIN = 70MHz
fIN = 70MHz
11.1
LSBs
LSBs
±1.5
±3.5
4
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SBAS548 –JUNE 2011
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, and 50% clock duty cycle, unless otherwise
noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V,
AVDD_BUF = 3.3V, and DRVDD = 1.8V.
ADS41B25
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
1.5
10
VPP
kΩ
Differential input resistance, at dc (see Figure 42)
Differential input capacitance, at dc (see Figure 43)
Analog input bandwidth
3.5
800
0.04
1.7
4
pF
MHz
µA
Analog input common-mode current (per input pin)
Common-mode output voltage
VCM
V
VCM output current capability
mA
DC ACCURACY
Offset error
–15
–2
2.5
15
2
mV
Temperature coefficient of offset error
0.003
mV/°C
Gain error as a result of
internal reference inaccuracy alone
EGREF
%FS
%FS
Gain error of channel alone
EGCHAN
2.5
POWER SUPPLY
IAVDD
Analog supply current
64
29
73
42
mA
mA
IAVDD_BUF
Analog input buffer supply current
IDRVDD(1)
Output buffer supply current
LVDS interface with 100Ω external termination
Low LVDS swing (200mV)
42
mA
IDRVDD
Output buffer supply current
LVDS interface with 100Ω external termination
Standard LVDS swing (350mV)
55
32
65
25
mA
mA
IDRVDD output buffer supply current(1)(2)
CMOS interface(2)
fIN = 2.5MHz
Global power-down
Standby
10
mW
mW
145
(1) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the
maximum recommended load capacitance on each digital output line is 10pF.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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DIGITAL CHARACTERISTICS
Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.8V, unless otherwise noted. Minimum and
maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V,
and DRVDD = 1.8V.
ADS41B25
PARAMETER
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
High-level input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET, SCLK, SDATA, and
SEN support 1.8V and 3.3V
CMOS logic levels
1.3
V
V
Low-level input voltage
0.4
0.4
High-level input voltage
1.3
V
OE only supports 1.8V CMOS
logic levels
Low-level input voltage
V
High-level input current: SDATA, SCLK(1)
High-level input current: SEN(2)
Low-level input current: SDATA, SCLK
Low-level input current: SEN
VHIGH = 1.8V
VHIGH = 1.8V
VLOW = 0V
10
0
µA
µA
µA
µA
0
VLOW = 0V
–10
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
0
V
V
Low-level output voltage
0.1
DIGITAL OUTPUTS (LVDS INTERFACE: D0_D1_P/M to D12_D13_P/M, CLKOUTP/M)
High-level output voltage(3)
Low-level output voltage(3)
High-level output voltage(3)
Low-level output voltage(3)
Output common-mode voltage
VODH
VODL
VODH
VODL
VOCM
Standard swing LVDS
Standard swing LVDS
Low swing LVDS
270
+350
–350
+200
–200
1.05
430
mV
mV
mV
mV
V
–430
–270
Low swing LVDS
0.85
1.25
(1) SDATA and SCLK have an internal 180kΩ pull-down resistor.
(2) SEN has an internal 180kΩ pull-up resistor to AVDD.
(3) With an external 100Ω termination.
6
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SBAS548 –JUNE 2011
PIN CONFIGURATION (CMOS MODE)
RGZ PACKAGE
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
UNUSED
CLKOUT
DFS
1
36 DRGND
35 DRVDD
34 NC
2
3
4
5
6
7
8
9
33 NC
32 NC
31 NC
PowerPAD
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
26 AVDD
25 AGND
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
13 14 15 16 17 18 19 20 21 22 23 24
NOTE: The PowerPAD™ is connected to DRGND.
Figure 1. CMOS Pinout
Pin Descriptions (CMOS Mode)
# OF
PIN NAME
AVDD
PIN NUMBER
PINS
FUNCTION
DESCRIPTION
8, 18, 20, 22, 24, 26
6
1
6
1
1
1
1
I
I
I
I
I
I
I
1.8V analog power supply
3.3V input buffer supply
AVDD_BUF
AGND
CLKP
21
9, 12, 14, 17, 19, 25
Analog ground
10
11
15
16
Differential clock input, positive
Differential clock input, negative
Differential analog input, positive
Differential analog input, negative
CLKM
INP
INM
Outputs the common-mode voltage that can be used externally to bias the analog
input pins.
VCM
13
1
O
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software
reset option; refer to the Serial Interface section.
RESET
30
1
I
When RESET is tied high, the internal registers are reset to the default values. In
this condition, SEN can be used as a control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When
RESET is high, SCLK has no function and should be tied to ground.
This pin has an internal 180kΩ pull-down resistor
SCLK
29
28
1
1
I
I
This pin functions as a serial interface data input when RESET is low. When
RESET is high, SDATA functions as a STANDBY control pin (see Table 5).
This pin has an internal 180kΩ pull-down resistor.
SDATA
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Pin Descriptions (CMOS Mode) (continued)
# OF
PIN NAME
PIN NUMBER
PINS
FUNCTION
DESCRIPTION
This pin functions as a serial interface enable input when RESET is low. When
RESET is high, SEN has no function and should be tied to AVDD. This pin has an
internal 180kΩ pull-up resistor to AVDD.
SEN
27
1
I
Data format select input. This pin sets the DATA FORMAT (twos complement or
offset binary) and the LVDS/CMOS output interface type. See Table 3 for detailed
information.
DFS
6
1
I
CLKOUT
OE
5
7
1
1
O
I
CMOS output clock
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up
resistor to AVDD.
RESERVED
D0 to D11
23
1
I
Digital control pin, reserved for future use
12-bit CMOS output data
Refer to Figure 1
12
O
This pin functions as an out-of-range indicator after reset, when register bit
SERIAL READOUT = 0, and functions as a serial register readout pin when
SERIAL READOUT = 1. This pin is a CMOS output level pin (powered from
DRVDD).
OVR_SDOUT
3
1
O
DRVDD
DRGND
UNUSED
NC
2, 35
1, 36, PAD
4
2
2
1
4
I
1.8V digital and output buffer supply
Digital and output buffer ground
Not used
I
—
—
Refer to Figure 1
Do not connect
8
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SBAS548 –JUNE 2011
PIN CONFIGURATION (LVDS MODE)
RGZ PACKAGE
QFN-48
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DRGND
DRVDD
OVR_SDOUT
CLKOUTM
CLKOUTP
DFS
1
36 DRGND
35 DRVDD
34 NC
2
3
4
5
6
7
8
9
33 NC
32 NC
31 NC
PowerPAD
OE
30 RESET
29 SCLK
28 SDATA
27 SEN
26 AVDD
25 AGND
AVDD
AGND
CLKP 10
CLKM 11
AGND 12
13 14 15 16 17 18 19 20 21 22 23 24
NOTE: The PowerPAD is connected to DRGND.
Figure 2. LVDS Pinout
Pin Descriptions (LVDS Mode)
# OF
PIN NAME
AVDD
PIN NUMBER
PINS
FUNCTION
DESCRIPTION
8, 18, 20, 22, 24, 26
6
1
6
1
1
1
1
I
I
I
I
I
I
I
1.8V analog power supply
3.3V input buffer supply
AVDD_BUF
AGND
CLKP
21
9, 12, 14, 17, 19, 25
Analog ground
10
11
15
16
Differential clock input, positive
Differential clock input, negative
Differential analog input, positive
Differential analog input, negative
CLKM
INP
INM
Outputs the common-mode voltage that can be used externally to bias the analog
input pins.
VCM
13
1
O
Serial interface RESET input.
When using the serial interface mode, the internal registers must initialize through
hardware RESET by applying a high pulse on this pin or by using the software
reset option; refer to the Serial Interface section.
RESET
30
1
I
When RESET is tied high, the internal registers are reset to the default values. In
this condition, SDATA can be used as a control pin.
RESET has an internal 180kΩ pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. When
RESET is high, SCLK has no function and should be tied to ground. This pin has
an internal 180kΩ pull-down resistor
SCLK
29
28
1
1
I
I
This pin functions as a serial interface data input when RESET is low. When
RESET is high, SDATA functions as a STANDBY control pin (see Table 6). This
pin has an internal 180kΩ pull-down resistor.
SDATA
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Pin Descriptions (LVDS Mode) (continued)
# OF
PIN NAME
PIN NUMBER
PINS
FUNCTION
DESCRIPTION
This pin functions as a serial interface enable input when RESET is low. When
RESET is high, SEN has no function and should be tied to AVDD. This pin has an
internal 180kΩ pull-up resistor to AVDD.
SEN
27
1
I
Output buffer enable input, active high; this pin has an internal 180kΩ pull-up
resistor to AVDD.
OE
7
6
1
1
I
I
Data format select input. This pin sets the DATA FORMAT (twos complement or
offset binary) and the LVDS/CMOS output interface type (see Table 3).
DFS
RESERVED
CLKOUTP
CLKOUTM
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
D4_D5_P
D4_D5_M
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
D10_D11_P
D10_D11_M
23
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
Digital control pin, reserved for future use
5
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Differential output clock, true
4
Differential output clock, complement
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Refer to Figure 2
Differential output data D0 and D1 multiplexed, true
Differential output data D0 and D1 multiplexed, complement
Differential output data D2 and D3 multiplexed, true
Differential output data D2 and D3 multiplexed, complement
Differential output data D4 and D5 multiplexed, true
Differential output data D4 and D5 multiplexed, complement
Differential output data D6 and D7 multiplexed, true
Differential output data D6 and D7 multiplexed, complement
Differential output data D8 and D9 multiplexed, true
Differential output data D8 and D9 multiplexed, complement
Differential output data D10 and D11 multiplexed, true
Differential output data D10 and D11 multiplexed, complement
This pin functions as an out-of-range indicator after reset, when register bit
READOUT = 0, and functions as a serial register readout pin when
READOUT = 1. This pin is a 1.8V CMOS output pin (powered from DRVDD).
OVR_SDOUT
3
1
O
DRVDD
DRGND
NC
2, 35
2
2
4
I
I
1.8V digital and output buffer supply
Digital and output buffer ground
Do not connect
1, 36, PAD
Refer to Figure 2
—
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FUNCTIONAL BLOCK DIAGRAM
DDR LVDS
Interface
AVDD
AGND
DRVDD DRGND
CLKP
CLKM
CLKOUTP
CLKOUTM
CLOCKGEN
D0_D1_P
D0_D1_M
D2_D3_P
D2_D3_M
AVDD_BUF
D4_D5_P
D4_D5_M
INP
INM
Common
Digital Functions
12-Bit
ADC
DDR
Serializer
Sampling
Circuit
D6_D7_P
D6_D7_M
D8_D9_P
D8_D9_M
Analog Buffers
Control
Interface
VCM
Reference
D10_D11_P
D10_D11_M
OVR_SDOUT
ADS41B25
OE
Figure 3. Block Diagram
TIMING CHARACTERISTICS
Dn_Dn + 1_P
Logic 0
VODL
Logic 1
VODH
Dn_Dn + 1_M
VOCM
GND
(1) With external 100Ω termination.
Figure 4. LVDS Output Voltage Levels
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TIMING REQUIREMENTS: LVDS and CMOS Modes(1)
Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, sampling frequency = 125MSPS, sine wave
input clock, CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the full
temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, AVDD_BUF = 3.3V, and DRVDD = 1.7V to 1.9V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
tA
Aperture delay
0.6
0.8
1.2
ns
Variation of
aperture delay
Between two devices at
the same temperature and DRVDD supply
±100
ps
tJ
Aperture jitter
100
5
fS rms
µs
Time to valid data after coming out of STANDBY mode
Time to valid data after coming out of PDN GLOBAL mode
25
Wakeup time
100
500
µs
Clock
cycles
Gain enabled (default after reset)
Gain and offset correction enabled
21
22
ADC latency(4)
Clock
cycles
DDR LVDS MODE
tSU
Data setup time(3)
tH
Data valid(5) to zero-crossing of CLKOUTP
Zero-crossing of CLKOUTP to data becoming invalid(5)
2.3
3.0
0.6
ns
ns
Data hold time(3)
0.35
Input clock rising edge cross-over to
output clock rising edge cross-over
1MSPS ≤ sampling frequency ≤ 125MSPS
tPDI
Clock propagation delay
3
4.2
5.4
54
ns
Between two devices at
the same temperature and DRVDD supply
Variation of tPDI
±0.6
ns
%
LVDS bit
clock duty cycle
Duty cycle of differential clock, (CLKOUTP – CLKOUTM)
1MSPS ≤ sampling frequency ≤ 125MSPS
42
48
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ sampling frequency ≤ 125MSPS
Data rise time,
Data fall time
tRISE, tFALL
0.14
ns
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ sampling frequency ≤ 125MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
0.14
50
ns
ns
Output enable (OE) to
data delay
tOE
Time to valid data after OE becomes active
100
PARALLEL CMOS MODE(6)
tSETUP
tHOLD
Data setup time
Data hold time
Data valid(5) to 50% of CLKOUT rising edge
Time interval of valid data(5)
2.5
3.5
3.2
4.3
ns
ns
Input clock rising edge cross-over to
output clock rising edge cross-over
1MSPS ≤ sampling frequency ≤ 125MSPS
tPDI
Clock propagation delay
Output clock duty cycle
4
5.5
47
7
ns
%
Duty cycle of output clock, CLKOUT
1MSPS ≤ sampling frequency ≤ 125MSPS
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ sampling frequency ≤ 125MSPS
Data rise time,
Data fall time
tRISE, tFALL
0.35
ns
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ sampling frequency ≤ 125MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
0.35
20
ns
ns
Output enable (OE) to
data delay
tOE
Time to valid data after OE becomes active
40
(1) Timing parameters are ensured by design and characterization but are not production tested.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground.
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
(5) Data valid refers to a logic high of 1.26V and a logic low of 0.54V.
(6) For fS > 200MSPS, it is recommended to use an external clock for data capture instead of the device output clock signal (CLKOUT).
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Table 1. LVDS Timing Across Sampling Frequencies
SAMPLING
SETUP TIME (ns)
HOLD TIME (ns)
FREQUENCY
(MSPS)
MIN
4.5
TYP
5.2
MAX
MIN
0.35
0.35
TYP
0.6
MAX
80
65
5.5
6.5
0.6
Table 2. CMOS Timing Across Sampling Frequencies
TIMING SPECIFIED WITH RESPECT TO OUTPUT CLOCK
tHOLD (ns)
SAMPLING
FREQUENCY
(MSPS)
tSETUP (ns)
TYP
tPDI (ns)
MIN
4.8
MAX
MIN
5.7
TYP
6.5
MAX
MIN
4
TYP
5.5
MAX
80
65
5.5
7
7
6.0
7.0
7.0
8.0
4
5.5
N + 23
N + 3
N + 4
N + 22
N + 2
N + 1
N + 21
Sample N
Input Signal
Input Clock
tA
CLKP
CLKM
CLKOUTM
CLKOUTP
tPDI
tH
21 Clock Cycles(1)
tSU
DDR LVDS
Output Data(2)
(DXP, DXM)
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
N - 21
N - 21
N - 19
N - 18
N - 17
N + 1
N + 2
N
tPDI
CLKOUT
tSU
Parallel CMOS
21 Clock Cycles(1)
tH
Output Data
N - 21
N - 20
N - 19
N - 18
N - 1
N
N + 1
(1) At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC latency + 1.
(2) E = Even bits (D0, D2, D4, etc). O = Odd bits (D1, D3, D5, etc).
Figure 5. Latency Diagram
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CLKM
Input
Clock
CLKP
tPDI
CLKOUTP
Output
Clock
CLKOUTM
tSU
tH
tSU
tH
Dn_Dn + 1_P
Dn_Dn + 1_M
Output
Data Pair
Dn(1)
Dn + 1(1)
(1) Dn = bits D0, D2, D4, etc. Dn + 1 = Bits D1, D3, D5, etc.
Figure 6. LVDS Mode Timing
CLKM
Input
Clock
CLKP
tPDI
Output
Clock
CLKOUT
tSU
tH
Output
Data
Dn(1)
Dn
CLKM
CLKP
Input
Clock
tSTART
tDV
Output
Data
Dn(1)
Dn
Dn = bits D0, D1, D2, etc.
Figure 7. CMOS Mode Timing
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DEVICE CONFIGURATION
The ADS41B25 has several modes that can be configured using a serial programming interface, as described in
Table 3, Table 4, and Table 5. In addition, the device has two dedicated parallel pins to quickly configure
commonly-used functions. The parallel pins are DFS (analog four-level control pin) and OE (digital control pin).
The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).
Table 3. DFS: Analog Control Pin
DESCRIPTION
VOLTAGE APPLIED ON DFS
0, +100mV/0mV
(Data Format/Output Interface)
Twos complement/DDR LVDS
Twos complement/parallel CMOS
Offset binary/parallel CMOS
Offset binary/DDR LVDS
(3/8) AVDD ± 100mV
(5/8) AVDD ± 100mV
AVDD, 0mV/–100mV
Table 4. OE: Digital Control Pin
VOLTAGE APPLIED ON OE
DESCRIPTION
0
Output data buffers disabled
Output data buffers enabled
AVDD
When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device
in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have
any alternative functions. Keep SEN tied high and SCLK tied low on the board.
Table 5. SDATA: Digital Control Pin
VOLTAGE APPLIED ON SDATA
DESCRIPTION
Normal operation
0
Logic high
Device enters standby
AVDD
(5/8) AVDD
3R
(5/8) AVDD
(3/8) AVDD
GND
AVDD
2R
3R
(3/8) AVDD
To Parallel Pin
Figure 8. Simplified Diagram to Configure DFS Pin
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SERIAL INTERFACE
The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface
formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data)
pins. Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA are latched at every
falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK
falling edge when SEN is low. If the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data
can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register
address and the remaining eight bits are the register data. The interface can work with SCLK frequency from
20MHz down to very low speeds (a few Hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. This initialization can be
accomplished in one of two ways:
1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10ns), as shown
in Figure 9; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low.
Register Address
A4
A3
Register Data
SDATA
SCLK
A7
A6
A5
A2
A1
A0
D7
D6
D5
D4
D3
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
SEN
RESET
Figure 9. Serial Interface Timing
SERIAL INTERFACE TIMING CHARACTERISTICS
Typical values at +25°C, minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
PARAMETER
SCLK frequency (equal to 1/tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
MIN
> dc
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
)
20
25
ns
25
ns
tDH
SDATA hold time
25
ns
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Serial Register Readout
The serial register readout function allows the contents of the internal registers to be read back on the
OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface
communication between the external controller and the ADC.
After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When
the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially, as shown in
Figure 10:
1. Set the READOUT register bit to '1'. This setting puts the device in serial readout mode and disables any
further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is
also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of
the register at address 0 cannot be read in the register readout mode.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
4. The external controller can latch the contents at the falling edge of SCLK.
5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the
device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.
Register Address A[7:0] = 00h
Register Data D[7:0] = 01h
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
OVR_SDOUT(1)
a) Enable Serial Readout (READOUT = 1)
Register Address A[7:0] = 43h
A4 A2
A5 A3
Register Data D[7:0] = XX (don’t care)
D4 D2 D1
D6 D5 D3
SDATA
SCLK
A7
A6
A1
A0
D7
D0
SEN
OVR_SDOUT(2)
0
1
0
0
0
0
0
0
b) Read Contents of Register 43h. This Register Has Been Initialized with 40h (device is put in global power-down mode).
(1) The OVR_SDOUT pin functions as OVR (READOUT = 0).
(2) The OVR_SDOUT pin functions as a serial readout (READOUT = 1).
Figure 10. Serial Readout Timing Diagram
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RESET TIMING CHARACTERISTICS
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 11. Reset Timing Diagram
RESET TIMING REQUIREMENTS
Typical values at +25°C and minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
1
TYP
MAX
UNIT
Delay from power-up of AVDD and DRVDD to RESET
pulse active
t1
Power-on delay
ms
10
ns
µs
ns
Pulse width of active RESET signal that resets the
serial registers
t2
t3
Reset pulse width
1(1)
Delay from RESET disable to SEN active
100
(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could
enter the parallel configuration mode briefly and then return back to serial interface mode.
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SERIAL REGISTER MAP
Table 6 summarizes the functions supported by the serial interface.
Table 6. Serial Interface Register Map(1)
REGISTER
ADDRESS
DEFAULT VALUE
AFTER RESET
REGISTER DATA
A[7:0] (Hex)
D[7:0] (Hex)
D7
D6
D5
D4
D3
D2
D1
RESET
0
D0
READOUT
0
00
01
03
25
00
00
00
50
0
0
0
0
0
0
LVDS SWING
0
0
0
0
0
0
0
0
0
HIGH PERF MODE 1
TEST PATTERNS
GAIN
LVDS
CLKOUT
STRENGTH
LVDS DATA
STRENGTH
26
00
00
0
0
0
0
0
0
0
EN
OFFSET
CORR
3D
DATA FORMAT
0
0
0
3F
40
00
00
0
0
CUSTOM PATTERN D[11:6]
CUSTOM PATTERN D[5:0]
0
EN
CLKOUT
RISE
EN
CLKOUT
FALL
CMOS CLKOUT
STRENGTH
41
00
LVDS CMOS
CLKOUT RISE POSN
42
43
08
00
CLKOUT FALL POSN
0
0
0
1
0
STBY
0
0
0
PDN
0
PDN OBUF
EN LVDS SWING
GLOBAL
HIGH PERF
MODE 2
4A
BF
00
00
0
0
0
0
0
0
0
0
0
0
OFFSET PEDESTAL
0
0
FREEZE
OFFSET
CORR
CF
DF
00
00
OFFSET CORR TIME CONSTANT
0
0
0
0
0
0
0
LOW SPEED
0
(1) Multiple functions in a register can be programmed in a single write operation.
DESCRIPTION OF SERIAL REGISTERS
For best performance, two special mode register bits must be enabled:
•
•
HI PERF MODE 1 and
HI PERF MODE 2
Register Address 00h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
RESET
READOUT
Bits[7:2]
Bit 1
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
Bit 0
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage
indicator.
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.
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Register Address 01h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS SWING
Bits[7:2]
LVDS SWING: LVDS swing programmability(1)
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing decreases to ±200mV
001111 = LVDS swing decreases to ±125mV
Bits[1:0]
Always write '0'
(1) The EN LVDS SWING register bits must be set to enable LVDS swing control.
Register Address 03h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
HI PERF MODE 1
Bits[7:2]
Bits[1:0]
Always write '0'
HI PERF MODE 1: High performance mode 1
00 = Default performance after reset
01 = Do not use
10 = Do not use
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF
MODE 1 bits
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Register Address 25h (Default = 50h)
7
6
5
4
3
2
1
0
GAIN
0
TEST PATTERNS
Bits[7:4]
GAIN: Gain programmability
These bits set the gain programmability in 0.5dB steps.
0000, 0001, 0010, 0011, 0100 = Do not use
0101 = 0dB gain (default after reset)
0110 = 0.5dB gain
0111 = 1dB gain
1000 = 1.5dB gain
1001 = 2dB gain
1010 = 2.5dB gain
1011 = 3dB gain
1100 = 3.5dB gain
Bit 3
Always write '0'
Bits[2:0]
TEST PATTERNS: Data capture
These bits verify data capture.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
Output data D[11:0] is an alternating sequence of 010101010101 and 101010101010.
100 = Outputs digital ramp
Output data increments by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095
101 = Output custom pattern (use registers 3Fh and 40h for setting the custom pattern)
110 = Unused
111 = Unused
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Register Address 26h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
0
0
Bits[7:2]
Bit 1
Always write '0'
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Bit 0
LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100Ω external termination (default strength)
1 = 50Ω external termination (2x strength)
Register Address 3Dh (Default = 00h)
7
6
5
4
3
2
0
1
0
0
0
EN OFFSET
CORR
DATA FORMAT
0
0
Bits[7:6]
DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5
ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
0
6
0
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D8
CUSTOM
PATTERN D7
CUSTOM
PATTERN D6
PATTERN D11 PATTERN D10 PATTERN D9
Bits[7:6]
Bits[5:0]
Always write '0'
CUSTOM PATTERN
These bits set the custom pattern.
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CUSTOM
PATTERN D5
CUSTOM
PATTERN D4
CUSTOM
PATTERN D3
CUSTOM
PATTERN D2
CUSTOM
PATTERN D1
CUSTOM
PATTERN D0
Bits[7:2]
Bits[1:0]
CUSTOM PATTERN
These bits set the custom pattern.
Always write '0'
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Register Address 41h (Default = 00h)
7
6
5
4
3
2
1
0
EN CLKOUT
RISE
EN CLKOUT
FALL
LVDS CMOS
CMOS CLKOUT STRENGTH
CLKOUT RISE POSN
Bits[7:6]
LVDS CMOS: Interface selection
These bits select the interface.
00, 10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3
ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits[2:1]
CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500ps, hold increases by 500ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100ps, hold increases by 100ps
10 = Setup reduces by 200ps, hold increases by 200ps
11 = Setup reduces by 1.5ns, hold increases by 1.5ns
Bit 0
ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge
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Register Address 42h (Default = 08h)
7
6
5
0
4
3
2
1
0
0
0
CLKOUT FALL POSN
0
1
STBY
Bits[7:6]
CLKOUT FALL POSN
Controls position of output clock falling edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400ps, hold increases by 400ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200ps, hold increases by 200ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100ps
10 = Falling edge is advanced by 200ps
11 = Falling edge is advanced by 1.5ns
Bits[5:4]
Bit 3
Always write '0'
Always write '1'
Bit 2
STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time
from standby is fast
Bits[1:0]
Always write '0'
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Register Address 43h (Default = 00h)
7
0
6
5
0
4
3
2
0
1
0
PDN GLOBAL
PDN OBUF
0
EN LVDS SWING
Bit 0
Bit 6
Always write '0'
PDN GLOBAL: Power-down
This bit sets the state of operation.
0 = Normal operation
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow
wake-up time.
Bit 5
Bit 4
Always write '0'
PDN OBUF: Power-down output buffer
This bit set the output data and clock pins.
0 = Output data and clock pins enabled
1 = Output data and clock pins powered down and put in high- impedance state
Bits[3:2]
Bits[1:0]
Always write '0'
EN LVDS SWING: LVDS swing control
00 = LVDS swing control using LVDS SWING register bits is disabled
01, 10 = Do not use
11 = LVDS swing control using LVDS SWING register bits is enabled
Register Address 4Ah (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
HI PERF
MODE 2
0
0
Bits[7:1]
Bit[0]
Always write '0'
HI PERF MODE 2: High performance mode 2
This bit is recommended for high input signal frequencies greater than 230MHz.
0 = Default performance after reset
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit
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Register Address BFh (Default = 00h)
7
6
5
4
3
2
0
1
0
0
0
OFFSET PEDESTAL
0
Bits[7:4]
OFFSET PEDESTAL
These bits set the offset pedestal.
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC mid-code value. A pedestal can be added to the final converged value by programming these
bits.
VALUE
PEDESTAL
0111
0110
0101
—
7LSB
6LSB
5LSB
—
0000
—
0LSB
—
1111
1110
—
–1LSB
–2LSB
—
1000
–8LSB
Bits[3:0]
Always write '0'
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Register Address CFh (Default = 00h)
7
6
0
5
4
3
2
1
0
0
0
FREEZE OFFSET CORR
OFFSET CORR TIME CONSTANT
Bit 7
FREEZE OFFSET CORR
This bit sets the freeze offset correction.
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the
last estimated value is used for offset correction every clock cycle; see the OFFSET
CORRECTION section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
These bits set the offset correction time constant for the correction loop time constant in number of
clock cycles.
VALUE
TIME CONSTANT (Number of Clock Cycles)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Bits[1:0]
Always write '0'
Register Address DFh (Default = 00h)
7
0
6
0
5
4
3
2
0
1
0
0
0
LOW SPEED
0
Bits[7:6]
Bits[5:4]
Always write '0'
LOW SPEED: Low-speed mode
00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for
sampling rates greater than 80MSPS.
11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal
to 80MSPS.
Bits[3:0]
Always write '0'
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TYPICAL CHARACTERISTICS
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
FFT FOR 10MHz INPUT SIGNAL
FFT FOR 70MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 94.3dBc
SFDR = 93.5dBc
SINAD = 68.8dBFS
SNR = 68.9dBFS
THD = 89.7dBc
SINAD = 68.7dBFS
SNR = 68.7dBFS
THD = 89.3dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 12.
Figure 13.
FFT FOR 170MHz INPUT SIGNAL
FFT FOR 300MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 93.7dBc
SFDR = 71.2dBc
SINAD = 68.2dBFS
SNR = 68.3dBFS
THD = 88.9dBc
SINAD = 66dBFS
SNR = 67.2dBFS
THD = 70.9dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
Each Tone at
Each Tone at
−7dBFS Amplitude
fIN1=100.1MHz
fIN2=105.1MHz
−36dBFS Amplitude
fIN1=100.1MHz
fIN2=105.1MHz
TwoTone IMD = 97.7dBFS
SFDR = 105.7dBFS
TwoTone IMD = 94.9dBFS
SFDR = 100.4dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 16.
Figure 17.
SFDR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY
95
90
85
80
75
70
65
60
55
50
69
68
68
68
67
66
66
66
65
64
64
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
105
100
95
90
85
80
75
70
65
60
72
70
68
66
64
62
60
58
150MHz
170MHz
220MHz
300MHz
400MHz
150MHz
170MHz
220MHz
300MHz
400MHz
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
Digital Gain (dB)
Digital Gain (dB)
Figure 20.
Figure 21.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
110
71
110
100
90
80
70
60
50
40
30
20
71
Input Frequency = 70MHz
Input Frequency = 170MHz
100
90
80
70
60
50
40
30
20
70.5
70
70.5
70
69.5
69
69.5
69
68.5
68
68.5
68
67.5
67
67.5
67
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
66.5
66.5
−50 −45 −40 −35 −30 −25 −20 −15 −10 −5
Amplitude (dBFS)
0
−50 −45 −40 −35 −30 −25 −20 −15 −10 −5
Amplitude (dBFS)
0
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR ACROSS TEMPERATURE vs AVDD SUPPLY
94
70
100
98
96
94
92
90
88
86
84
82
80
Input Frequency = 70MHz
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.8
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
92
90
88
86
84
82
69.5
69
68.5
68
67.5
67
SFDR
SNR
1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Input Common−Mode Voltage (V)
2
Input Frequency = 70MHz
35 60 85
−40
−15
10
Temperature (°C)
Figure 24.
Figure 25.
SNR ACROSS TEMPERATURE vs AVDD SUPPLY
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
92
70.5
SFDR
SNR
70
69.8
69.6
69.4
69.2
69
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.8
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
91
90
89
88
87
86
70
69.5
69
68.8
68.6
68.4
68.2
68
68.5
68
Input Frequency = 70MHz
67.5
Input Frequency = 70MHz
35 60 85
1.65
1.7
1.75
1.8
1.85
1.9
1.95
DRVDD Supply (V)
−40
−15
10
Temperature (°C)
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
95
93
91
89
87
85
83
70
SFDR
SNR
95
93
91
89
87
85
83
70
SFDR
SNR
69.5
69
69.5
69
68.5
68
68.5
68
67.5
67.5
Input Frequency = 70MHz
67
Input Frequency = 70MHz
67
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
Differential Clock Amplitude (VPP
)
Differential Clock Amplitude (VPP)
Figure 28.
Figure 29.
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
CMRR vs FREQUENCY
96
94
92
90
88
86
84
70
SNR
THD
0
−10
−20
−30
−40
−50
−60
Input Frequency = 170MHz
50mVPP Signal Superimposed
on Input Common−Mode Voltage (1.7V)
69.5
69
68.5
68
67.5
Input Frequency = 10MHz
67
10
20
30
40
50
60
70
80
90
Input Clock Duty Cycle (%)
0
50
100
150
200
250
300
Frequency of Input Common−Mode Signal (MHz)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
CMRR SPECTRUM
PSRR vs FREQUENCY
0
0
−10
−20
−30
−40
−50
−60
−70
−80
fIN = 70MHz
fIN = 70MHz
PSRR on AVDD Supply 50mVPP
PSRR on AVDD_BUF Supply 100mVPP
fCM = 10MHz, 50mVPP
SFDR = 85.3dBc
Amplitude (fIN) = -1dBFS
-20
Amplitude (fCM) = -94.9
Amplitude (fIN + fCM) = -86.3
Amplitude (fIN - fCM) = -87.4
-40
fIN - fCM = 60MHz
-60
fIN + fCM = 80MHz
-80
fCM = 10MHz
-100
-120
0
12.5
25
37.5
50
62.5
0
10
20
30
40
50
60
70
80
90 100
Frequency (MHz)
Frequency of Signal on Supply (MHz)
Figure 32.
Figure 33.
ZOOMED VIEW OF SPECTRUM WITH PSRR SIGNAL
POWER vs SAMPLING FREQUENCY
0
250
230
210
190
170
150
130
110
90
fIN = 10MHz
fPSRR = 10MHz, 50mVPP
fIN
Analog Power (AVDD Power + BUF Power)
DRVDD Power
Amplitude (fIN) = -1dBFS
Amplitude (fPSRR) = -65.6
Amplitude (fIN + fPSRR) = -67.5
Amplitude (fIN - fPSRR) = -68.3
-20
-40
fPSRR
-60
fIN - fPSRR
fIN + fPSRR
-80
-100
-120
70
50
0
5
10
15
20
25
30
0
25
50
75
100
125
Frequency (MHz)
Sampling Speed (MSPS)
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
DRVDD CURRENT vs SAMPLING FREQUENCY
60
LVDS 350mV Swing
LVDS 200mV Swing
CMOS Default
50
40
30
20
10
0
0
25
50
75
100
125
Sampling Speed (MSPS)
Figure 36.
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TYPICAL CHARACTERISTICS: CONTOUR
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
SFDR CONTOUR
(0dB Gain)
125
89
89
120
110
100
90
75
70
80
65
83
86
80
89
89
75
70
83
65
86
80
89
89
70
80
75
65
70
65
86
83
150
10
50
100
200
250
300
350
400
Input Frequency (MHz)
75
65
70
80
85
SFDR (dBc)
Figure 37.
SFDR CONTOUR
(3.5dB Gain)
125
120
89
89
82
74
88
78
70
87
110
100
90
89
88
86
89
88
82
78
88
89
88
89
74
70
87
88
80
86
88
88
87
150
88
87
86
70
70
65
74
82
78
300
10
50
100
200
250
350
400
Input Frequency (MHz)
70
75
80
85
SFDR (dBc)
Figure 38.
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TYPICAL CHARACTERISTICS: CONTOUR (continued)
At +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock,
1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, DDR LVDS output interface, and
32k-point FFT, unless otherwise noted.
SNR CONTOUR
(0dB Gain)
125
68.8
68.6
68.4
68.2
68
67.5
67
66.5
120
110
100
90
66
65.5
66.5
68.8
68.6
68.4 68.2
65
66
65.5
67.5
68
67
66.5
66
80
68.4
68.2
65.5
65
68.8
68.6
68
67.5
67
70
65
64.5
64
65
10
50
100
150
200
250
300
350
400
Input Frequency (MHz)
66
64
65
67
68
SNR (dBFS)
Figure 39.
SNR CONTOUR
(3.5dB Gain)
125
120
66.4
66.2
66
65.8
65.3
64.8
64.3
110
100
90
66.4
66.2
66
65.8
64.8
65.3
64.3
80
64.8
63.8
64.3
65.8
70
65
63.3
66.4
66.2
100
66
150
65.3
63.8
300
10
50
200
Input Frequency (MHz)
250
350
400
62.5
63
63.5
64
64.5
65
65.5
66
SNR (dBFS)
Figure 40.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS41B25 is a buffered analog input and ultralow power ADC with maximum sampling rates up to
125MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input
signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the
outputs combined in a digital correction logic block. At every clock edge the sample propagates through the
pipeline, resulting in a data latency of 21 clock cycles. The output is available as 12-bit data, in DDR LVDS mode
or CMOS mode, and coded in either straight offset binary or binary twos complement format.
ANALOG INPUT
The analog input pins have analog buffers (powered from the AVDD_BUF supply) that internally drive the
differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the
external driving source (10kΩ dc resistance and 3.5pF input capacitance). The buffer helps to isolate the external
driving source from the switching currents of the sampling circuit. This buffering makes it easy to drive the
buffered inputs compared to an ADC without the buffer.
The input common-mode is set internally using a 5kΩ resistor from each input pin to 1.7V, so the input signal can
be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.375V) and
(VCM – 0.375V), resulting in a 1.5VPP differential input swing.
The input sampling circuit has a high 3dB bandwidth that extends up to 800MHz (measured from the input pins
to the sampled voltage). Figure 41 shows an equivalent circuit for the analog input.
LPKG
RROUTING
1nH
Buffer
23W
INP
CPAD
CPIN
2.5pF
RBIAS
CEQ
0.5pF
RPAD
5kW
200W
Sampling
Circuit
REQ
VCM = 1.7V
RBIAS
LPKG
1nH
RROUTING
5kW
23W
INM
CPAD
CPIN
Buffer
2.5pF
CEQ
0.5pF
RPAD
200W
REQ
(1) CEQ refers to the equivalent input capacitance of the buffer = 4pF.
(2) REQ refers to the REQ buffer = 10Ω.
(3) This equivalent circuit is an approximation and valid for frequencies less than 700MHz.
Figure 41. Analog Input Equivalent Circuit(3)
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This technique improves the
common-mode noise immunity and even-order harmonic rejection. A small resistor (5Ω to 10Ω) in series with
each input pin is recommended to damp out ringing caused by package parasitics.
Figure 42 and Figure 43 show the differential impedance (ZIN = RIN || CIN) seen by looking into the ADC input
pins. The presence of the analog input buffer produces an almost constant input capacitance, as shown in
Figure 42.
10
1
0.1
RIN Simulation
RIN Measurement
0.01
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (GHz)
Figure 42. ADC Analog Input Resistance (RIN) Across Frequency
5
4
3
2
1
CIN Simulation
CIN Measurement
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency (GHz)
Figure 43. ADC Analog Input Capacitance (CIN) Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 44 and Figure 45—one optimized for low input
frequencies and the other optimized for high input frequencies.
In Figure 44, a single transformer is used and is suited for low input frequencies. To optimize even-harmonic
performance at high input frequencies (greater than the first Nyquist), the use of back-to-back transformers is
recommended (see Figure 45). Note that both drive circuits have been terminated by 50Ω near the ADC side.
The ac-coupling capacitors allow the analog inputs to self-bias around the required common-mode voltage.
5W
INP
T1
0.1mF
25W
0.1mF
25W
INM
1:1
5W
Figure 44. Drive Circuit for Low Input Frequencies
5W
INP
T2
T1
0.1mF
50W
50W
50W
50W
0.1mF
INM
1:1
1:1
5W
Figure 45. Drive Circuit for High Input Frequencies
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch and
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 44 and Figure 45. The center point of this termination
is connected to ground to improve the balance between the P (positive) and M (negative) sides. The values of
the terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω
(for a 50Ω source impedance).
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CLOCK INPUT
The ADS41B25 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS),
with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to
VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave
clock or ac-coupling for LVPECL and LVDS clock sources. Figure 46 shows an equivalent circuit for the input
clock.
Clock Buffer
LPKG
1nH
20W
CLKP
CBOND
CEQ
CEQ
5kW
1pF
RESR
100W
2pF
0.95V
LPKG
1nH
5kW
20W
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 46. Input Clock Equivalent Circuit
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF
capacitor, as shown in Figure 47. For best performance, the clock inputs must be driven differentially, reducing
susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a clock
source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no
change in performance with a non-50% duty cycle clock input. Figure 48 shows a differential circuit.
0.1mF
CMOS
0.1mF
CLKP
Clock Input
CLKP
Differential Sine-Wave,
PECL, or LVDS
Clock Input
VCM
0.1mF
0.1mF
CLKM
CLKM
Figure 47. Single-Ended Clock Driving Circuit
Figure 48. Differential Clock Driving Circuit
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GAIN FOR SFDR/SNR TRADE-OFF
The ADS41B25 includes gain settings that can be used to get improved SFDR performance. The gain is
programmable from 0dB to 3.5dB (in 0.5dB steps) using the GAIN register bits. For each gain setting, the analog
input full-scale range scales proportionally, as shown in Table 7.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.
After a reset, the gain is enabled with 0dB gain setting. For other gain settings, program the GAIN register bits.
Table 7. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
0.5
1
Default after reset
Programmable gain
Programmable gain
Programmable gain
Programmable gain
Programmable gain
Programmable gain
Programmable gain
1.5
1.41
1.33
1.26
1.19
1.12
1.06
1
1.5
2
2.5
3
3.5
OFFSET CORRECTION
The ADS41B25 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The
correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 8.
Table 8. Time Constant of Offset Correction Loop
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK × 1/fS (sec)(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1M
2M
8ms
16ms
33.5ms
67ms
134ms
268ms
537ms
1.1s
2.2s
4.3s
8.6s
17s
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Reserved
Reserved
Reserved
Reserved
—
—
—
—
(1) Sampling frequency, fS = 125MSPS.
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After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by a default after reset.
After a reset, the offset correction is disabled. To use offset correction set EN OFFSET CORR to '1' and program
the required time constant. Figure 49 shows the time response of the offset correction algorithm after it is
enabled.
OFFSET CORRECTION
Time Response
2050
2047
2044
Offset Correction
2041
Converges to Output
2038
Code of 2048
2035
2045
Offset of
3 LSBs
2032
2029
2026
2023
2020
2017
2014
2011
2008
2005
2002
1999
2048
Final Converged Value
Offset Correction
Begins
-5
5
15 25 35 45 55 65 75 85 95 105
Time (ms)
Figure 49. Time Response of Offset Correction
POWER DOWN
The ADS41B25 has three power-down modes: power-down global, standby, and output buffer disable.
Power-Down Global
In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down,
resulting in reduced total power dissipation of about 7mW. The output buffers are in a high-impedance state. The
wake-up time from the global power-down to data becoming valid in normal mode is typically 100µs. To enter the
global power-down mode, set the PDN GLOBAL register bit.
Standby
In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up
time of 5µs. The total power dissipation in standby mode is approximately 145mW. To enter the standby mode,
set the STBY register bit.
Output Buffer Disable
The output buffers can be disabled and put in a high-impedance state; wakeup time from this mode is fast,
approximately 100ns. This can be controlled using the PDN OBUF register bit or using the OE pin.
Input Clock Stop
In addition, the converter enters a low-power mode when the input clock frequency falls below 1MSPS. The
power dissipation is approximately 92mW.
POWER-SUPPLY SEQUENCE
During power-up, the AVDD, AVDD_BUF, and DRVDD supplies can come up in any sequence. These supplies
are separated in the device. Externally, they can be driven from separate supplies or from a single supply.
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DIGITAL OUTPUT INFORMATION
The ADS41B25 provides 12-bit data and an output clock synchronized with the data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the LVDS CMOS serial interface register bit or using the DFS pin.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 50.
Pins
CLKOUTP
Output Clock
CLKOUTM
D0_D1_P
Data Bits D0, D1
D0_D1_M
D2_D3_P
Data Bits D2, D3
D2_D3_M
D4_D5_P
Data Bits D4, D5
12-Bit
D4_D5_M
ADC Data
D6_D7_P
Data Bits D6, D7
D6_D7_M
D8_D9_P
Data Bits D8, D9
D8_D9_M
D10_D11_P
Data Bits D10, D11
D10_D11_M
ADS41B25
Figure 50. ADS41B25 LVDS Data Outputs
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Even data bits (D0, D2, D4, etc.) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5,
etc.) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to
capture all 12 data bits, as shown in Figure 51.
CLKOUTP
CLKOUTM
D0_D1_P,
D0_D1_M
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
D2_D3_P,
D2_D3_M
D4_D5_P,
D4_D5_M
D6_D7_P,
D6_D7_M
D6
D8
D7
D9
D6
D8
D7
D9
D8_D9_P,
D8_D9_M
D10_D11_P,
D10_D11_M
D10
D11
D10
D11
Sample N
Sample N + 1
Figure 51. DDR LVDS Interface
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LVDS Output Data and Clock Buffers
The equivalent circuit of each LVDS output buffer is shown in Figure 52. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination. This
mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a 100Ω
termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH
register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
VDIFF
High
Low
OUTP
OUTM
External
100W Load
1.1V
ROUT
VDIFF
High
Low
NOTE: Use the default buffer strength to match 100Ω external termination (ROUT = 100Ω). To match with a 50Ω external termination, set the
LVDS STRENGTH bit (ROUT = 50Ω).
Figure 52. LVDS Buffer Equivalent Circuit
Parallel CMOS Interface
In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The
rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 53 depicts the CMOS
output interface.
Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR.
The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this
degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength
ensures a wide data stable window (even at 125MSPS) is provided so the data outputs have minimal load
capacitance. It is recommended to use short traces (one to two inches or 2,54cm to 5,08cm) terminated with less
than 5pF load capacitance, as shown in Figure 54.
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Pins
OVR
CLKOUT
D0
D1
D2
D3
12-Bit
ADC Data
D9
D10
D11
ADS41B25
Figure 53. CMOS Output Interface
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Input Clock
CLKOUT
Receiver (FPGA, ASIC, etc.)
Flip-Flops
CLKIN
D0
D1
D2
D0_In
D1_In
D2_In
12-Bit ADC Data
D10
D11
D10_In
D11_In
ADS41B25
Use short traces between
ADC output and receiver pins (1 to 2 inches).
Figure 54. Using the CMOS Data Outputs
CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between '0' and '1' every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal.
Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG
)
where:
CL = load capacitance,
N × FAVG = average number of output bits switching.
(1)
Figure 36 illustrates the current across sampling frequencies at 2MHz analog input frequency.
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Input Over-Voltage Indication (OVR Pin)
The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the
sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR
remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off
DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).
For a positive overload, the D[11:0] output data bits are FFFh in offset binary output format and 7FFh in twos
complement output format. For a negative input overload, the output code is 000h in offset binary output format
and 800h in twos complement output format.
Output Data Format
Two output data formats are supported: twos complement and offset binary. They can be selected using the
DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event
of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.
BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS414x, ADS412x EVM User Guide (SLWU067) for details on layout
and grounding.
Supply Decoupling
Because the ADS41B25 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum
number of capacitors depends on the actual application. The decoupling capacitors should be placed very close
to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically internally connected to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271), both available for download at the TI web site (www.ti.com).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1 LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy and error as a result of the channel. Both errors are specified independently as
EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(2)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(3)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
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Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(4)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(5)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(6)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(7)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
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PACKAGE OPTION ADDENDUM
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4-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS41B25IRGZR
ADS41B25IRGZT
ACTIVE
ACTIVE
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS41B25IRGZR
ADS41B25IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
330.0
330.0
16.4
16.4
7.3
7.3
7.3
7.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS41B25IRGZR
ADS41B25IRGZT
VQFN
VQFN
RGZ
RGZ
48
48
2500
250
333.2
333.2
345.9
345.9
28.6
28.6
Pack Materials-Page 2
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