ADS4229_14 [TI]
Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC;
| 型号： | ADS4229_14 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual-Channel, 12-Bit, 250-MSPS Ultralow-Power ADC |
| 文件： | 总104页 (文件大小：3808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
Dual-Channel, 14-/12-Bit, 160/125/65MSPS Ultralow-Power ADC
Check for Samples: ADS4222, ADS4225, ADS4226, ADS4242, ADS4245, ADS4246
1
FEATURES
APPLICATIONS
23
•
Ultralow Power with Single 1.8V Supply,
CMOS Output:
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
–
–
–
183mW total power at 65MSPS
277mW total power at 125MSPS
332mW total power at 160MSPS
DESCRIPTION
•
High Dynamic Performance:
The ADS424x/422x are low-speed variants of the
ADS42xx ultralow-power family of dual-channel,
14-bit/12-bit analog-to-digital converters (ADCs).
Innovative design techniques are used to achieve
–
–
88dBc SFDR at 170MHz
71.4dBFS SNR at 170MHz
•
•
Crosstalk: > 90dB at 185MHz
Programmable Gain up to 6dB for
SNR/SFDR Trade-off
DC Offset Correction
Output Interface Options:
high-dynamic
performance,
while
consuming
extremely low power with 1.8V supply. This topology
makes the ADS424x/422x well-suited for multi-carrier,
wide-bandwidth communications applications.
•
•
The ADS424x/422x have gain options that can be
used to improve SFDR performance at lower
full-scale input ranges. These devices include a dc
offset correction loop that can be used to cancel the
ADC offset. Both DDR (double data rate) LVDS and
parallel CMOS digital output interfaces are available
in a compact QFN-64 PowerPAD™ package.
–
–
1.8V parallel CMOS interface
Double data rate (DDR) LVDS with
programmable swing:
–
–
Standard swing: 350mV
Low swing: 200mV
•
•
Supports Low Input Clock Amplitude
Down to 200mVPP
Package: QFN-64 (9mm × 9mm)
The devices include internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. All devices are
specified over the industrial temperature range
(–40°C to +85°C).
ADS424x/422x FAMILY COMPARISON(1)
250MSPS
160MSPS
125MSPS
65MSPS
ADS424x
14-bit family
ADS4249
ADS4246
ADS4245
ADS4242
ADS422x
12-bit family
ADS4229
ADS4226
ADS4225
ADS4222
(1) See for details on migrating from the ADS62P49 family.
PERFORMANCE SUMMARY
ADS4246
86
ADS4245
ADS4242
ADS4226
ADS4225
88
ADS4222
SFDR (dBc), fIN = 20MHz
SFDR (dBc), fIN = 170MHz
SNR (dBFS), fIN = 20MHz
SNR (dBFS), fIN = 170MHz
Total power (mW/channel)
88
91
86
82
91
85
82
88
85
88
72.8
70.4
166
73.4
71.4
138
73.6
71.2
91
70.5
69.5
166
70.8
69.9
138
70.9
69.9
91
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
LEAD/BALL
FINISH
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
ECO PLAN(2)
TRANSPORT MEDIA
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
ADS4246IRGCT
ADS4246IRGCR
ADS4245IRGCT
ADS4245IRGCR
ADS4242IRGCT
ADS4242IRGCR
ADS4226IRGCT
ADS4226IRGCR
ADS4225IRGCT
ADS4225IRGCR
ADS4222IRGCT
ADS4222IRGCR
GREEN (RoHS, no
Sb/Br)
ADS4246
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
QFN-64
RGC
RGC
RGC
RGC
RGC
RGC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Cu/NiPdAu
Cu/NiPdAu
Cu/NiPdAu
Cu/NiPdAu
Cu/NiPdAu
Cu/NiPdAu
AZ4246
AZ4245
AZ4242
AZ4226
AZ4225
AZ4222
GREEN (RoHS, no
Sb/Br)
ADS4245
ADS4242
ADS4226
ADS4225
ADS4222
GREEN (RoHS, no
Sb/Br)
GREEN (RoHS, no
Sb/Br)
GREEN (RoHS, no
Sb/Br)
GREEN (RoHS, no
Sb/Br)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS424x/422x are pin-compatible with the previous generation ADS62P49 family of data converters; this
architecture enables easy migration. However, there are some important differences between the two device
generations, summarized in Table 1.
Table 1. Migrating from the ADS62P49
ADS62P49 FAMILY
ADS424x/422x FAMILY
PINS
Pin 22 is NC (not connected)
Pins 38 and 58 are DRVDD
Pins 39 and 59 are DRGND
SUPPLY
Pin 22 is AVDD
Pins 38 and 58 are NC (do not connect, must be floated)
Pins 39 and 59 are NC (do not connect, must be floated)
AVDD is 3.3V
AVDD is 1.8V
No change
DRVDD is 1.8V
INPUT COMMON-MODE VOLTAGE
VCM is 1.5V
VCM is 0.95V
SERIAL INTERFACE
No change in protocol
New serial register map
Protocol: 8-bit register address and 8-bit register data
EXTERNAL REFERENCE
Supported
Not supported
2
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
ABSOLUTE MAXIMUM RATINGS(1)
ADS424x/422x
MIN
–0.3
–0.3
–0.3
–2.4
–2.4
MAX
2.1
2.1
0.3
2.4
2.4
UNIT
Supply voltage range, AVDD
V
V
V
V
V
Supply voltage range, DRVDD
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
Minimum
(1.9, AVDD + 0.3)
INP_A, INM_A, INP_B, INM_B
CLKP, CLKM(2)
–0.3
–0.3
–0.3
–40
V
V
V
Voltage applied to input pins
AVDD + 0.3
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
3.9
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, Tstg
ESD rating
+85
+125
+150
2
°C
°C
°C
kV
–65
Human body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3V|).
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS42xx
THERMAL METRIC(1)
RGC
64 PINS
23.9
10.9
4.3
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
4.4
θJCbot
0.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2011, Texas Instruments Incorporated
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS424x/422x
PARAMETER
MIN NOM MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Digital supply voltage, DRVDD
ANALOG INPUTS
Differential input voltage range
2
VPP
V
Input common-mode voltage
VCM ± 0.05
400
Maximum analog input frequency with 2VPP input amplitude(1)
Maximum analog input frequency with 1VPP input amplitude(1)
CLOCK INPUT
MHz
MHz
600
Input clock sample rate (ADS4242/ADS4222)
Low-speed mode enabled (by default after reset)
Input clock sample rate (ADS4245/ADS4225)
Low-speed mode enabled(2)
Low-speed mode disabled(2) (by default after reset)
Input clock sample rate (ADS4246/ADS4226)
Low-speed mode enabled(2)
1
1
65
MSPS
80
MSPS
MSPS
80
125
1
80
80
MSPS
MSPS
VPP
Low-speed mode disabled(2) (by default after reset)
160
Sine wave, ac-coupled
0.2
1.5
1.6
0.7
1.5
LVPECL, ac-coupled
VPP
Input clock amplitude differential
(VCLKP – VCLKM
)
LVDS, ac-coupled
VPP
LVCMOS, single-ended, ac-coupled
V
Input clock duty cycle
Low-speed mode disabled
Low-speed mode enabled
DIGITAL OUTPUTS
35
40
50
50
65
60
%
%
Maximum external load capacitance from each output pin to DRGND, CLOAD
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD
Operating free-air temperature, TA
5
pF
Ω
100
–40
+85
°C
(1) See the Theory of Operation section in the Application Information.
(2) See the Serial Interface Configuration section for details on programming the low-speed mode.
HIGH-PERFORMANCE MODES(1)(2)
PARAMETER
High-performance mode
DESCRIPTION
Set the HIGH PERF MODE register bit to obtain best performance across sample clock and
input signal frequencies.
Register address = 03h, data = 03h
Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input
signal frequencies greater than 200MHz.
Register address = 4Ah, data = 01h
High-frequency mode
Register address = 58h, data = 01h
(1) It is recommended to use these modes to obtain best performance.
(2) See the Serial Interface Configuration section for details on register programming.
4
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS: ADS4246/ADS4245/ADS4242
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS
interface, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4246 (160MSPS)
ADS4245 (125MSPS)
ADS4242 (65MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Bits
Resolution
14
14
14
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
72.8
72.5
72.2
71.2
69.4
72.6
72.1
71.7
70.8
68
73.4
72.9
72.6
71.4
69.3
73.2
72.6
72.3
71.2
68.5
88
73.6
72.5
72.3
70.4
69.4
73.5
72.3
72.1
70.2
68.2
91
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
70
69.5
Signal-to-noise ratio
SNR
SINAD
SFDR
THD
69
69
73.5
72
68.5
73.5
72
Signal-to-noise and
distortion ratio
67.5
86
84
86
88
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
82
85
87
dBc
72
82
88
85
dBc
78
78
74
dBc
84
86
88
dBc
81
84
85
dBc
81
83
85
dBc
70
80
84
82
dBc
76
75
73
dBc
86
88
91
dBc
84
73.5
73.5
78
86
73.5
73.5
79
88
dBc
HD2
82
85
87
dBc
72
82
88
85
dBc
78
78
74
dBc
92
93
95
dBc
86
89
90
dBc
Third-harmonic distortion
HD3
93
89
96
dBc
72
94
90
87
dBc
80
81
81
dBc
90
95
98
dBc
92
94
97
dBc
Worst spur
(other than second and third harmonics)
89
93
95
dBc
77
89
91
93
dBc
91
89
92
dBc
f1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS
96
83
96
92
98
92
dBFS
dBFS
Two-tone intermodulation
distortion
IMD
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS4246/ADS4245/ADS4242 (continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS
interface, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4246 (160MSPS)
ADS4245 (125MSPS)
ADS4242 (65MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
20-MHz full-scale signal on
channel under observation;
170-MHz full-scale signal on
other channel
Crosstalk
95
95
95
dB
Recovery to within 1%
(of full-scale) for 6dB overload
with sine-wave input
Clock
cycle
Input overload recovery
1
> 30
11.5
1
> 30
11.5
1
> 30
11.4
AC power-supply rejection
ratio
For 100mVPP signal on AVDD
supply, up to 10MHz
PSRR
ENOB
dB
fIN = 70MHz
(ADS4245, ADS4242)
fIN = 170MHz (ADS4246)
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
LSBs
fIN = 70MHz
(ADS4245, ADS4242)
fIN = 170MHz (ADS4246)
DNL
INL
–0.97
±0.5
±2
1.7
–0.97
±0.5
±2
1.7
–0.97
±0.5
±2
1.7
LSBs
LSBs
fIN = 70MHz
(ADS4245, ADS4242)
fIN = 170MHz (ADS4246)
±5
±5
±5
6
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS: ADS4226/ADS4225/ADS4222
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS
interface, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4226 (160MSPS)
ADS4225 (125MSPS)
ADS4222 (65MSPS)
PARAMETER
TEST CONDITIONS
MIN
67.5
66.5
70
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
Bits
Resolution
12
12
12
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
fIN = 20MHz
fIN = 70MHz
fIN = 100MHz
fIN = 170MHz
fIN = 300MHz
70.5
70.3
70.1
69.5
68.2
70.4
70.1
69.8
69.3
67.6
86
70.8
70.5
70.3
69.9
68.1
70.7
70.3
70.1
69.5
67.5
88
70.9
70.3
70.2
69.9
68.2
70.8
70.2
70.1
68.7
67.2
91
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
68.0
68.0
Signal-to-noise ratio
SNR
SINAD
SFDR
THD
67.0
72.5
70.0
72.5
72.5
76.0
67.0
72.5
71.0
72.5
72.5
77.0
Signal-to-noise and
distortion ratio
84
86
88
dBc
Spurious-free dynamic range
Total harmonic distortion
Second-harmonic distortion
82
85
87
dBc
82
88
85
dBc
78
78
74
dBc
84
86
88
dBc
81
84
85
dBc
81
83
85
dBc
68
80
84
82
dBc
76
75
73
dBc
86
88
91
dBc
84
86
88
dBc
HD2
82
85
87
dBc
70
82
88
85
dBc
78
78
74
dBc
92
93
95
dBc
86
89
90
dBc
Third-harmonic distortion
HD3
93
89
96
dBc
70
94
90
87
dBc
80
81
81
dBc
90
95
98
dBc
92
94
97
dBc
Worst spur
89
93
95
dBc
(other than second and third harmonics)
75
89
91
93
dBc
91
89
92
dBc
f1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS
96
83
96
92
98
92
dBFS
dBFS
Two-tone intermodulation
distortion
IMD
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
ELECTRICAL CHARACTERISTICS: ADS4226/ADS4225/ADS4222 (continued)
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS
interface, and 0dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.8V.
ADS4226 (160MSPS)
ADS4225 (125MSPS)
ADS4222 (65MSPS)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
20MHz full-scale signal on
channel under observation;
170MHz full-scale signal on
other channel
Crosstalk
95
95
95
dB
Recovery to within 1%
(of full-scale) for 6dB overload
with sine-wave input
Clock
cycle
Input overload recovery
1
30
1
30
1
30
AC power-supply rejection
ratio
For 100mVPP signal on AVDD
supply, up to 10MHz
PSRR
ENOB
dB
fIN = 70MHz
(ADS4225, ADS4222)
fIN = 170MHz (ADS4226)
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
11.2
11.3
11.1
LSBs
fIN = 70MHz
(ADS4225, ADS4222)
fIN = 170MHz (ADS4226)
DNL
INL
–0.8
±0.13
±0.5
1.5
–0.8
±0.13
±0.5
1.5
–0.8
±0.13
±0.5
1.2
LSBs
LSBs
fIN = 70MHz
(ADS4225, ADS4222)
fIN = 170MHz (ADS4226)
±3.5
±3.5
±2.5
8
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SBAS533C –MARCH 2011–REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, and –1dBFS differential analog input,
unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V.
ADS4246/ADS4226 (160MSPS)
ADS4245/ADS4225 (125MSPS)
ADS4242/ADS4222 (65MSPS)
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range (0dB gain)
Differential input resistance (at 200MHz)
Differential input capacitance (at 200MHz)
2
0.75
3.7
2
0.75
3.7
2
0.75
3.7
VPP
kΩ
pF
Analog input bandwidth
(with 50Ω source impedance, and 50Ω termination)
550
1.5
550
1.5
550
1.5
MHz
Analog input common-mode current
(per input pin of each channel)
µA/MSPS
Common-mode output voltage
VCM output current capability
DC ACCURACY
VCM
0.95
4
0.95
4
0.95
4
V
mA
Offset error
–15
–2
2.5
15
–15
–2
2.5
15
2
–15
–2
2.5
15
mV
Temperature coefficient of offset error
0.003
0.003
0.003
mV/°C
Gain error as a result of internal
reference inaccuracy alone
EGREF
2
2
%FS
Gain error of channel alone
Temperature coefficient of EGCHAN
POWER SUPPLY
EGCHAN
±0.1
–1
±0.1
±0.1
–1
%FS
0.002
0.002
0.002
Δ%/°C
IAVDD
Analog supply current
123
111
150
135
105
99
130
73
78
85
mA
mA
IDRVDD
Output buffer supply current
LVDS interface, 350mV swing with 100Ω external
120
95
termination, fIN = 2.5MHz
IDRVDD
Output buffer supply current
CMOS interface, no load capacitance(1)
fIN = 2.5MHz
61
49
28
mA
Analog power
222
199
189
179
133
131
mW
mW
Digital power
LVDS interface, 350mV swing with 100Ω external
termination, fIN = 2.5MHz
Digital power
CMOS interface, no load capacitance(1)
fIN = 2.5MHz
109
88
50
mW
mW
Global power-down
25
25
25
(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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DIGITAL CHARACTERISTICS
At AVDD = 1.8V and DRVDD = 1.8V, unless otherwise noted. DC specifications refer to the condition where the digital
outputs do not switch, but are permanently at a valid logic level '0' or '1'.
ADS424x/422x
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1)
High-level input voltage
1.3
V
All digital inputs support 1.8V
and 3.3V CMOS logic levels
Low-level input voltage
0.4
V
SDATA, SCLK(2)
SEN(3)
VHIGH = 1.8V
VHIGH = 1.8V
VLOW = 0V
10
0
µA
µA
µA
µA
High-level input current
SDATA, SCLK
SEN
0
Low-level input current
VLOW = 0V
10
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
0
V
V
Low-level output voltage
0.1
Output capacitance (internal to device)
pF
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output
differential voltage
With an external
100Ω termination
VODH
270
350
430
mV
Low-level output
differential voltage
With an external
100Ω termination
VODL
VOCM
–430
–350
–270
mV
V
Output common-mode voltage
0.9
1.05
1.25
(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
(2) SDATA, SCLK have internal 150kΩ pull-down resistor.
(3) SEN has an internal 150kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS
buffers.
DAn_P
DBn_P
Logic 0
VODL = -350mV(1)
Logic 1
ODH = +350mV(1)
V
DAn_M
DBn_M
VOCM
GND
(1) With external 100Ω termination.
Figure 1. LVDS Output Voltage Levels
10
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SBAS533C –MARCH 2011–REVISED JUNE 2011
PIN CONFIGURATION: LVDS MODE
RGC PACKAGE(2)
QFN-64
(TOP VIEW)
DRVDD
DB4M
DB4P
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA6P
46 DA6M
45 DA4P
44 DA4M
43 DA2P
42 DA2M
41 DA0P
40 DA0M
39 NC
DB6M
DB6P
DB8M
DB8P
DB10M
DB10P
Thermal Pad
(Connected to DRGND)
DB12M 10
DB12P 11
RESET 12
SCLK 13
SDATA 14
SEN 15
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(2) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 2. ADS4246/ADS4245/ADS4242 LVDS Mode
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RGC PACKAGE(3)
QFN-64
(TOP VIEW)
DRVDD
DB2M
DB2P
DB4M
DB4P
DB6M
DB6P
DB8M
DB8P
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA4P
46 DA4M
45 DA2P
44 DA2M
43 DA0P
42 DA0M
41 NC
Thermal Pad
(Connected to DRGND)
40 NC
DB10M 10
DB10P 11
RESET 12
SCLK 13
SDATA 14
SEN 15
39 NC
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(3) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 3. ADS4226/ADS4225/ADS4222 LVDS Mode
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Pin Descriptions: LVDS Mode
PIN NUMBER
PIN NAME
# OF PINS
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK
and SEN are used as parallel control pins in this mode. This pin has an internal
150kΩ pull-down resistor.
12
RESET
1
Input
This pin functions as a serial interface clock input when RESET is low. It controls
the low-speed mode selection when RESET is tied high; see Table 5 for detailed
information. This pin has an internal 150kΩ pull-down resistor.
13
14
SCLK
1
1
Input
Input
SDATA
Serial interface data input; this pin has an internal 150kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. It
controls the output interface and data format selection when RESET is tied high;
see Table 6 for detailed information. This pin has an internal 150kΩ pull-up
resistor to AVDD.
15
SEN
1
Input
16, 22, 33, 34
AVDD
AGND
4
8
Input
Input
Analog power supply
Analog ground
17, 18, 21, 24,
27, 28, 31, 32
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
This pin outputs the common-mode voltage (0.95V) that can be used externally to
bias the analog input pins
23
VCM
1
Output
25
26
CLKP
CLKM
1
1
1
1
1
1
1
2
1
1
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Differential clock positive input
Differential clock negative input
29
INP_A
Differential analog positive input, channel A
Differential analog negative input, channel A
Digital control input pins. Together, they control the various power-down modes.
Digital control input pins. Together, they control the various power-down modes.
Digital control input pins. Together, they control the various power-down modes.
Output buffer ground
30
INM_A
35
CTRL1
36
CTRL2
37
CTRL3
49, PAD
56
DRGND
CLKOUTM
CLKOUTP
Differential output clock, complement
57
Differential output clock, true
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
64
SDOUT
1
2
Output
Output
Refer to
Figure 2 and
Figure 3
DA0P, DA0M
Channel A differential output data pair, D0 and D1 multiplexed
Channel A differential output data D2 and D3 multiplexed
Channel A differential output data D4 and D5 multiplexed
Channel A differential output data D6 and D7 multiplexed
Channel A differential output data D8 and D9 multiplexed
Channel A differential output data D10 and D11 multiplexed
Channel A differential output data D12 and D13 multiplexed (ADS424x only)
Channel B differential output data pair, D0 and D1 multiplexed
Channel B differential output data D2 and D3 multiplexed
Refer to
Figure 2 and
Figure 3
DA2P, DA2M
DA4P, DA4M
DA6P, DA6M
DA8P, DA8M
DA10P, DA10M
DA12P, DA12M
DB0P, DB0M
DB2P, DB2M
2
2
2
2
2
2
2
2
Output
Output
Output
Output
Output
Output
Output
Output
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
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Pin Descriptions: LVDS Mode (continued)
PIN NUMBER
PIN NAME
# OF PINS
FUNCTION
DESCRIPTION
Refer to
Figure 2 and
Figure 3
DB4P, DB4M
2
2
2
2
2
Output
Channel B differential output data D4 and D5 multiplexed
Refer to
Figure 2 and
Figure 3
DB6P, DB6M
DB8P, DB8M
Output
Output
Output
Output
Channel B differential output data D6 and D7 multiplexed
Channel B differential output data D8 and D9 multiplexed
Channel B differential output data D10 and D11 multiplexed
Refer to
Figure 2 and
Figure 3
Refer to
Figure 2 and
Figure 3
DB10P, DB10M
DB12P, DB12M
Refer to
Figure 2 and
Figure 3
Channel B differential output data D12 and D13 multiplexed (ADS424x only)
Do not connect, must be floated
Refer to
Figure 38,
Figure 39,
Figure 56, and
Figure 57
8 (ADS422x)
4 (ADS424x)
NC
—
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SBAS533C –MARCH 2011–REVISED JUNE 2011
PIN CONFIGURATION: CMOS MODE
RGC PACKAGE(4)
QFN-64
(TOP VIEW)
DRVDD
DB4
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA7
46 DA6
45 DA5
44 DA4
43 DA3
42 DA2
41 DA1
40 DA0
39 NC
DB5
DB6
DB7
DB8
DB9
DB10
DB11
Thermal Pad
(Connected to DRGND)
DB12 10
DB13 11
RESET 12
SCLK 13
SDATA 14
SEN 15
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(4) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 4. ADS4246/ADS4245/ADS4242 CMOS Mode
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RGC PACKAGE(5)
QFN-64
(TOP VIEW)
DRVDD
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA5
46 DA4
45 DA3
44 DA2
43 DA1
42 DA0
41 NC
Thermal Pad
(Connected to DRGND)
40 NC
DB10 10
DB11 11
RESET 12
SCLK 13
SDATA 14
SEN 15
39 NC
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(5) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 5. ADS4226/ADS4225/ADS4222 CMOS Mode
16
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Pin Descriptions: CMOS Mode
# OF
PINS
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface Configuration section.
12
RESET
1
Input
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and
SEN are used as parallel control pins in this mode. This pin has an internal 150kΩ
pull-down resistor.
This pin functions as a serial interface clock input when RESET is low. It controls the
low-speed mode when RESET is tied high; see Table 5 for detailed information. This pin
has an internal 150kΩ pull-down resistor.
13
SCLK
SDATA
SEN
1
1
1
Input
Input
Input
14
15
Serial interface data input; this pin has an internal 150kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. It controls the
output interface and data format selection when RESET is tied high; see Table 6 for
detailed information. This pin has an internal 150kΩ pull-up resistor to AVDD.
16, 22, 33, 34
AVDD
AGND
4
8
Input
Input
Analog power supply
Analog ground
17, 18, 21, 24, 27, 28,
31, 32
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
This pin outputs the common-mode voltage (0.95V) that can be used externally to bias
the analog input pins
23
VCM
1
Output
25
26
CLKP
CLKM
1
1
1
1
1
1
1
2
1
1
Input
Input
Input
Input
Input
Input
Input
Input
—
Differential clock positive input
Differential clock negative input
29
INP_A
Differential analog positive input, channel A
Differential analog negative input, channel A
Digital control input pins. Together, they control various power-down modes.
Digital control input pins. Together, they control various power-down modes.
Digital control input pins. Together, they control various power-down modes.
Output buffer ground
30
INM_A
CTRL1
CTRL2
CTRL3
DRGND
UNUSED
CLKOUT
35
36
37
49, PAD
56
This pin is not used in the CMOS interface
CMOS output clock
57
Output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
64
SDOUT
1
Output
Refer to Figure 4 and
Figure 5
DA0 to DA11
DA12 to DA13
DB0 to DB11
12
2
Output
Output
Output
Channel A ADC output data bits, CMOS levels
Refer to Figure 4
Channel A ADC output data bits, CMOS levels (ADS424x only)
Channel B ADC output data bits, CMOS levels
Refer to Figure 4 and
Figure 5
12
Refer to Figure 4
DB12 to DB13
NC
2
1
Output
Channel B ADC output data bits, CMOS levels (ADS424x only)
Do not connect, must be floated
—
—
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FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
LVDS Interface
DA0P
DA0M
DA2P
DA2M
DA4P
INP_A
Digital and
DDR
Serializer
DA4M
DA6P
14-Bit
ADC
Sampling
Circuit
INM_A
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKP
CLKM
CLKOUTP
CLKOUTM
Output
Clock Buffer
CLOCKGEN
DB0P
DB0M
DB2P
DB2M
DB4P
INP_B
INM_B
Digital and
DDR
Serializer
DB4M
DB6P
14-Bit
ADC
Sampling
Circuit
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
Control
Interface
VCM
Reference
SDOUT
ADS424x
Figure 6. ADS4246/45/42 Block Diagram
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SBAS533C –MARCH 2011–REVISED JUNE 2011
AVDD
AGND
DRVDD DRGND
LVDS Interface
DA0P
DA0M
DA2P
DA2M
DA4P
INP_A
INM_A
Digital and
DDR
Serializer
DA4M
DA6P
12-Bit
ADC
Sampling
Circuit
DA6M
DA8P
DA8M
DA10P
DA10M
CLKP
CLKM
CLKOUTP
CLKOUTM
Output
Clock Buffer
CLOCKGEN
DB0P
DB0M
DB2P
DB2M
DB4P
INP_B
INM_B
Digital and
DDR
Serializer
DB4M
DB6P
12-Bit
ADC
Sampling
Circuit
DB6M
DB8P
DB8M
DB10P
DB10M
Control
Interface
VCM
Reference
SDOUT
ADS422x
Figure 7. ADS4226/25/22 Block Diagram
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TIMING CHARACTERISTICS: LVDS AND CMOS MODES(1)
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8V, sampling frequency = 160MSPS, sine wave input clock, 1.5VPP
clock amplitude, CLOAD = 5pF(2), and RLOAD = 100Ω(3), unless otherwise noted. Minimum and maximum values are across the
full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8V, and DRVDD = 1.7V to 1.9V.
PARAMETER
DESCRIPTION
MIN
TYP
0.8
MAX
UNIT
ns
tA
Aperture delay
0.5
1.1
Aperture delay matching
Between the two channels of the same device
±70
ps
Between two devices at the same temperature and
DRVDD supply
Variation of aperture delay
Aperture jitter
±150
140
50
ps
fS rms
µs
tJ
Time to valid data after coming out of STANDBY
mode
100
500
Wakeup time
Time to valid data after coming out of GLOBAL
power-down mode
100
16
µs
Clock
cycles
Default latency after reset
ADC latency(4)
Clock
cycles
Digital functions enabled (EN DIGITAL = 1)
24
DDR LVDS MODE(5)
tSU Data setup time
Data valid(6) to zero-crossing of CLKOUTP
1.5
2.0
0.6
ns
ns
Zero-crossing of CLKOUTP to data becoming
invalid(6)
tH
Data hold time
0.35
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
LVDS bit clock duty cycle
5.0
6.1
49
7.5
ns
%
Duty cycle of differential clock,
(CLKOUTP-CLKOUTM)
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 160MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
0.13
0.13
ns
ns
Rise time measured from –100mV to +100mV
Fall time measured from +100mV to –100mV
1MSPS ≤ Sampling frequency ≤ 160MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
PARALLEL CMOS MODE
tSU
tH
Data setup time
Data hold time
Data valid(7) to zero-crossing of CLKOUT
Zero-crossing of CLKOUT to data becoming invalid(7)
1.6
2.3
2.5
2.7
ns
ns
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
Output clock duty cycle
4.5
6.4
46
8.5
ns
%
Duty cycle of output clock, CLKOUT
1MSPS ≤ Sampling frequency ≤ 160MSPS
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
1
1
ns
ns
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time
Output clock fall time
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
(5) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(6) Data valid refers to a logic high of +100mV and a logic low of –100mV.
(7) Data valid refers to a logic high of 1.26V and a logic low of 0.54V
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Table 2. LVDS Timings at Lower Sampling Frequencies
tPDI, CLOCK PROPAGATION
DELAY (ns)
SAMPLING
FREQUENCY
(MSPS)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
5.9
4.5
3.1
2.3
1.7
TYP
6.6
5.2
3.6
2.9
2.2
MAX
MIN
0.35
0.35
0.35
0.35
0.35
TYP
0.6
0.6
0.6
0.6
0.6
MAX
MIN
5.0
5.0
5.0
5.0
5.0
TYP
6.1
6.1
6.1
6.1
6.1
MAX
7.5
7.5
7.5
7.5
7.5
65
80
105
125
150
Table 3. CMOS Timings at Lower Sampling Frequencies
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING
FREQUENCY
(MSPS)
tPDI, CLOCK PROPAGATION
DELAY (ns)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
6.1
4.7
3.4
2.7
1.9
TYP
7.2
5.8
4.3
3.6
2.8
MAX
MIN
6.7
5.3
3.8
3.1
2.5
TYP
7.1
5.8
4.3
3.6
2.9
MAX
MIN
4.5
4.5
4.5
4.5
4.5
TYP
6.4
6.4
6.4
6.4
6.4
MAX
8.5
8.5
8.5
8.5
8.5
65
80
105
125
150
CLKM
CLKP
Input
Clock
tPDI
Output
Clock
CLKOUT
tSU
tH
DAn,
DBn
Output
Data
Dn(1)
(1) Dn = bits D0, D1, D2, etc. of channels A and B.
Figure 8. CMOS Interface Timing Diagram
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N + 4
N + 18
N + 3
N + 17
N + 2
N + 16
N + 1
Sample
N
Input
Signal
tA
CLKP
CLKM
Input
Clock
CLKOUTM
CLKOUTP
tPDI
tH
DDR
LVDS
tSU
O
16 Clock Cycles(1)
Output Data(2)
DAnP/M, DBnP/M
O
E
O
E
O
E
O
E
O
E
O
E
O
E
E
O
E
O
E
O
N - 16
N - 15
N - 14
N - 13
N - 12
N - 1
N
N + 1
tPDI
CLKOUT
tSU
Parallel
CMOS
tH
16 Clock Cycles(1)
N - 14
N - 13
Output Data
DAn, DBn
N - 16
N - 15
N - 1
N
N + 1
(1) ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC
latency + 1.
(2) E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).
Figure 9. Latency Timing Diagram
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CLKOUTM
CLKOUTP
DA0, DB0
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA2, DB2
DA4, DB4
DA6, DB6
DA8, DB8
D6
D8
D7
D9
D6
D8
D7
D9
DA10, DB10
DA12, DB12
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
Figure 10. ADS4246/45/42 LVDS Interface Timing Diagram
CLKOUTM
CLKOUTP
DA0, DB0
DA2, DB2
DA4, DB4
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA6, DB6
DA8, DB8
D6
D8
D7
D9
D6
D8
D7
D9
DA10, DB10
D10
D11
D10
D11
Sample N
Sample N + 1
Figure 11. ADS4226/25/22 LVDS Interface Timing Diagram
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DEVICE CONFIGURATION
The ADS424x/422x can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 4 to Table 7).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 4 describes the modes controlled by the parallel pins.
Table 4. Parallel Pin Definition
PIN
CONTROL MODE
SCLK
SEN
Low-speed mode selection
Output data format and output interface selection
CTRL1
CTRL2
CTRL3
Together, these pins control the power-down modes
SERIAL INTERFACE CONFIGURATION ONLY
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Register Map section describes the register programming and the register
reset process in more detail.
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control
pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the
voltage settings on these pins (see Table 7). SEN, SDATA, and SCLK function as serial interface digital pins and
are used to access the internal registers of the ADC. The registers must first be reset to the default values either
by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must be kept
low. The Serial Register Map section describes register programming and the register reset process in more
detail.
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PARALLEL CONFIGURATION DETAILS
The functions controlled by each parallel pin are described in Table 5, Table 6, and Table 7. A simple way of
configuring the parallel pins is shown in Figure 12.
Table 5. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low
Low-speed mode is disabled
Low-speed mode is enabled(1)
High
(1) Low-speed mode is enabled in the ADS4222/42 by default.
Table 6. SEN Control Pin
VOLTAGE APPLIED ON SEN
DESCRIPTION
0
Twos complement and parallel CMOS output
(+50mV/0mV)
(3/8) AVDD
(±50mV)
Offset binary and parallel CMOS output
Offset binary and DDR LVDS output
(5/8) 2AVDD
(±50mV)
AVDD
(0mV/–50mV)
Twos complement and DDR LVDS output
Table 7. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
CTRL2
CTRL3
Low
DESCRIPTION
Low
Low
Low
Low
High
High
High
Low
Low
High
High
Low
Low
High
Normal operation
Not available
High
Low
Not available
High
Low
Not available
Global power-down
High
Low
Channel A standby, channel B is active
Not available
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] pins.
High
High
High
AVDD
(5/8) AVDD
3R
2R
3R
(5/8) AVDD
(3/8) AVDD
GND
AVDD
(3/8) AVDD
To Parallel Pin
Figure 12. Simple Scheme to Configure the Parallel Pins
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SERIAL INTERFACE DETAILS
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of
16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining
eight bits are the register data. The interface can work with SCLK frequencies from 20MHz down to very low
speeds (of a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Either through hardware reset by applying a high pulse on the RESET pin (of width greater than 10ns), as
shown in Figure 13; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low.
Register Address
Register Data
SDATA
SCLK
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
SEN
RESET
Figure 13. Serial Interface Timing
Table 8. Serial Interface Timing Characteristics(1)
PARAMETER
SCLK frequency (equal to 1/tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
MIN
> DC
25
TYP
MAX
UNIT
fSCLK
tSLOADS
tSLOADH
tDSU
)
20
MHz
ns
25
ns
25
ns
tDH
SDATA hold time
25
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8V, and DRVDD = 1.8V, unless otherwise noted.
Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on pin 64.
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When READOUT is disabled, the SDOUT pin is in high-impedance state. If serial readout is not used, the
SDOUT pin must float.
Register Address A[7:0] = 00h
Register Data D[7:0] = 01h
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
A4 A2
A5 A3
Register Data D[7:0] = XX (don’t care)
D4 D2 D1
D6 D5 D3
SDATA
SCLK
A7
A6
A1
A0
D7
D0
SEN
0
0
0
0
0
1
0
0
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
Figure 14. Serial Readout Timing Diagram
Table 9. Reset Timing (Only when Serial Interface is Used)(1)
PARAMETER
CONDITIONS
MIN
TYP MAX UNIT
Delay from AVDD and DRVDD power-up to active RESET
pulse
1
ms
t1
Power-on delay
10
ns
t2
t3
Reset pulse width
Active RESET signal pulse width
1
µs
Register write delay
Delay from RESET disable to SEN active
100
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 15. Reset Timing Diagram
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SERIAL REGISTER MAP
Table 10 summarizes the functions supported by the serial interface.
Table 10. Serial Interface Register Map(1)
REGISTER
ADDRESS
REGISTER DATA
D4 D3
A[7:0] (Hex)
D7
D6
D5
D2
D1
RESET
0
D0
READOUT
0
00
01
03
25
29
2B
0
0
0
0
0
0
LVDS SWING
0
0
0
0
0
0
0
0
0
0
0
HIGH PERF MODE
CH A GAIN
CH B GAIN
CH A TEST PATTERNS
DATA FORMAT
0
0
0
0
CH B TEST PATTERNS
ENABLE
OFFSET
CORR
3D
0
0
0
0
0
0
0
0
3F
40
41
42
CUSTOM PATTERN D[13:8]
CUSTOM PATTERN D[7:0]
LVDS CMOS
CMOS CLKOUT STRENGTH
CLKOUT RISE POSN
0
0
0
DIS OBUF
CLKOUT FALL POSN
LVDS
EN DIGITAL
0
0
0
0
LVDS DATA
0
45
STBY
CLKOUT
STRENGTH
0
PDN GLOBAL
STRENGTH
HIGH FREQ
4A
58
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MODE CH B(2)
HIGH FREQ
MODE CH A(2)
BF
C1
CH A OFFSET PEDESTAL
CH B OFFSET PEDESTAL
0
0
0
0
FREEZE
OFFSET
CORR
CF
DB
EF
0
0
0
OFFSET CORR TIME CONSTANT
0
0
0
0
LOW SPEED
0
0
0
0
0
0
0
0
MODE CH B(3)
EN LOW
SPEED
0
0
0
MODE(3)
F1
F2
0
0
0
0
0
0
0
0
0
0
EN LVDS SWING
LOW SPEED
0
0
MODE CH A(3)
(1) Multiple functions in a register can be programmed in a single write operation. All registers default to '0' after reset.
(2) These bits improve SFDR on high frequencies. The frequency limit is 200MHz.
(3) Low-speed mode is not applicable for the ADS4242 and ADS4222.
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DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
RESET
READOUT
Bits[7:2]
Bit 1
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
Bit 0
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic
levels running from the DRVDD supply. See the Serial Register Readout section.
Register Address 01h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS SWING
Bits[7:2]
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350mV with external 100Ω termination
011011 = LVDS swing increases to ±410mV
110010 = LVDS swing increases to ±465mV
010100 = LVDS swing increases to ±570mV
111110 = LVDS swing decreases to ±200mV
001111 = LVDS swing decreases to ±125mV
Bits[1:0]
Always write '0'
Register Address 03h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
HIGH PERF MODE
Bits[7:2]
Bits[1:0]
Always write '0'
HIGH PERF MODE: High-performance mode
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
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Register Address 25h (Default = 00h)
7
6
5
4
3
2
1
0
CH A GAIN
0
CH A TEST PATTERNS
Bits[7:4]
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5dB steps for channel A.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
For the ADS424x, output data D[13:0] are an alternating sequence of 10101010101010 and
01010101010101.
For the ADS422x, the output data D[11:0] are an alternating sequence of 101010101010 and
010101010101.
100 = Outputs digital ramp.
For the ADS424x, output data increment by one LSB (14-bit) every clock cycle from code 0 to code
16383.
For the ADS422x, output data increment by one LSB (12-bit) every fourth clock cycle from code 0
to code 4095.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
Register Address 29h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
DATA FORMAT
Bits[7:5]
Bits[4:3]
Always write '0'
DATA FORMAT: Data format selection
00 = Twos complement
01 = Twos complement
10 = Twos complement
11 = Offset binary
Bits[2:0]
Always write '0'
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Register Address 2Bh (Default = 00h)
7
6
5
4
3
2
1
0
CH B GAIN
0
CH B TEST PATTERNS
Bits[7:4]
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5dB steps for channel B.
0000 = 0dB gain (default after reset)
0001 = 0.5dB gain
0010 = 1dB gain
0011 = 1.5dB gain
0100 = 2dB gain
0101 = 2.5dB gain
0110 = 3dB gain
0111 = 3.5dB gain
1000 = 4dB gain
1001 = 4.5dB gain
1010 = 5dB gain
1011 = 5.5dB gain
1100 = 6dB gain
Bit 3
Always write '0'
Bits[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
For the ADS424x, output data D[13:0] are an alternating sequence of 10101010101010 and
01010101010101.
For the ADS422x, the output data D[11:0] are an alternating sequence of 101010101010 and
010101010101.
100 = Outputs digital ramp.
For the ADS424x, output data increment by one LSB (14-bit) every clock cycle from code 0 to code
16383.
For the ADS422x, output data increment by one LSB (12-bit) every fourth clock cycle from code 0
to code 4095.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
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Register Address 3Dh (Default = 00h)
7
0
6
0
5
4
3
2
0
1
0
0
0
ENABLE OFFSET CORR
0
0
Bits[7:6]
Bit 5
Always write '0'
ENABLE OFFSET CORR: Offset correction setting
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
0
6
0
5
4
3
2
1
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
Bits[7:6]
Bits[5:0]
Always write '0'
CUSTOM PATTERN D[13:8]
These are the six upper bits of the custom pattern available at the output instead of ADC data.
Note that for the ADS424x, the custom pattern is 14-bit. The ADS422x custom pattern is 12-bit.
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D7
PATTERN D6
PATTERN D5
PATTERN D4
PATTERN D3
PATTERN D2
PATTERN D1
PATTERN D0
Bits[7:0]
CUSTOM PATTERN D[7:0]
These are the eight upper bits of the custom pattern available at the output instead of ADC data.
Note that for the ADS424x, the custom pattern is 14-bit. The ADS422x custom pattern is 12-bit;
use the CUSTOM PATTERN D[13:2] register bits.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Register Address 41h (Default = 00h)
7
6
5
4
3
2
0
1
0
LVDS CMOS
CMOS CLKOUT STRENGTH
0
DIS OBUF
Bits[7:6]
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:2]
Bits[1:0]
Always write '0'
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output
interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
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Register Address 42h (Default = 00h)
7
6
5
4
3
2
0
1
0
0
0
CLKOUT FALL POSN
CLKOUT RISE POSN
EN DIGITAL
Bits[7:6]
CLKOUT FALL POSN
In LVDS mode:
00 = Default
01 = The falling edge of the output clock advances by 450 ps
10 = The falling edge of the output clock advances by 150 ps
11 = The falling edge of the output clock is delayed by 550 ps
In CMOS mode:
00 = Default
01 = The falling edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The falling edge of the output clock advances by 100 ps
Bits[5:6]
CLKOUT RISE POSN
In LVDS mode:
00 = Default
01 = The rising edge of the output clock advances by 450 ps
10 = The rising edge of the output clock advances by 150 ps
11 = The rising edge of the output clock is delayed by 250 ps
In CMOS mode:
00 = Default
01 = The rising edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The rising edge of the output clock advances by 100 ps
Bit 3
EN DIGITAL: Digital function enable
0 = All digital functions disabled
1 = All digital functions (such as test patterns, gain, and offset correction) enabled
Bits[2:0]
Always write '0'
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Register Address 45h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
STBY
0
0
PDN GLOBAL
Bit 7
Bit 6
Bit 5
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50µs).
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50Ω external termination
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100Ω external termination
1 = All LVDS data buffers have double strength to be used with 50Ω external termination
Bits[4:3]
Bit 2
Always write '0'
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wakeup time from this mode is slow (typically 100µs).
Bits[1:0]
Always write '0'
Register Address 4Ah (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
HIGH FREQ MODE CH B
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH B: High-frequency mode for channel B
0 = Default
1 = Use this mode for high input frequencies
Register Address 58h (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
HIGH FREQ MODE CH A
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH A: High-frequency mode for channel A
0 = Default
1 = Use this mode for high input frequencies
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Register Address BFh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CH A OFFSET PEDESTAL
Bits[7:2]
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC midcode value. A pedestal can be added to the final converged value by programming these
bits. See the Offset Correction section. Channels can be independently programmed for different
offset pedestals by choosing the relevant register address.
For the ADS424x, the pedestal ranges from –32 to +31, so the output code can vary from
midcode-32 to midcode+32 by adding pedestal D7-D2.
For the ADS422x, the pedestal ranges from –8 to +7, so the output code can vary from midcode-8
to midcode+7 by adding pedestal D7-D4.
ADS422x (Program Bits D[7:4])
ADS424x (Program Bits D[7:2])
0111 = Midcode+7
0110 = Midcode+6
0101 = Midcode+5
…
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
0000 = Midcode
1111 = Midcode-1
1110 = Midcode-2
1101 = Midcode-3
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
1000 = Midcode-8
100000 = Midcode-32
Bits[1:0]
Always write '0'
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Register Address C1h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CH B OFFSET PEDESTAL
Bits[7:2]
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is the ADC
midcode value. A pedestal can be added to the final converged value by programming these bits;
see the Offset Correction section. Channels can be independently programmed for different offset
pedestals by choosing the relevant register address.
For the ADS424x, the pedestal ranges from –32 to +31, so the output code can vary from
midcode-32 to midcode+32 by adding pedestal D[7:2]. For the ADS422x, the pedestal ranges
from –8 to +7, so the output code can vary from midcode-8 to midcode+7 by adding pedestal
D[7:4].
ADS422x (Program Bits D[7:4])
ADS424x (Program Bits D[7:2])
0111 = Midcode+7
0110 = Midcode+6
0101 = Midcode+5
…
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
0000 = Midcode
1111 = Midcode-1
1110 = Midcode-2
1101 = Midcode-3
…
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
111101 = Midcode-3
…
1000 = Midcode-8
100000 = Midcode-32
Bits[1:0]
Always write '0'
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Register Address CFh (Default = 00h)
7
6
0
5
4
3
2
1
0
0
0
FREEZE OFFSET CORR
OFFSET CORR TIME CONSTANT
Bit 7
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen,
the last estimated value is used for offset correction of every clock cycle. See the Offset Correction
section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction
section.
Bits[1:0]
Always write '0'
Register Address DBh (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
LOW SPEED MODE CH B
Bits[7:1]
Bit 0
Always write '0'
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
Register Address EFh (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
EN LOW SPEED MODE
0
Bits[7:5]
Bit 4
Always write '0'
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
(ADS42x5 and ADS42x6 only)
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW
SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits[3:0]
Always write '0'
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Register Address F1h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
EN LVDS SWING
Bits[7:2]
Bits[1:0]
Always write '0'
EN LVDS SWING: LVDS swing enable
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
Register Address F2h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
LOW SPEED MODE CH A
Bits[7:4]
Bit 3
Always write '0'
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0]
Always write '0'
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TYPICAL CHARACTERISTICS: ADS4246
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89.8dBc
SFDR = 89.8dBc
SINAD = 72.8dBFS
SNR = 72.9dBFS
THD = 87.9dBc
SINAD = 71.3dBFS
SNR = 71.2dBFS
THD = 88.2dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
Figure 16.
Figure 17.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 76.5dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 185.1MHz
fIN2 = 190.1MHz
SINAD = 68.4dBFS
SNR = 69.3dBFS
THD = 74.5dBc
Two−Tone IMD = 83.6dBFS
SFDR = 95.1dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
Figure 18.
Figure 19.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4246 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 = 46.1MHz
fIN2 = 50.1MHz
Two−Tone IMD = 96.2dBFS
SFDR = 103.2dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
10
20
30
40
50
60
70
80
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 20.
Figure 21.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
74
73
72
71
70
69
68
67
66
65
64
63
74
73
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS: ADS4246 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
90
86
82
78
74
70
66
72
71
70
69
68
67
66
65
64
63
62
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
Figure 24.
Figure 25.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
120
110
100
90
78
77
76
75
74
73
72
71
70
69
68
120
110
100
90
77
76
75
74
73
72
71
70
69
68
67
Input Frequency = 40MHz
Input Frequency = 150MHz
80
80
70
70
60
60
50
50
40
40
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR (dBc)
SFDR (dBFS)
SNR
30
30
20
−70
20
−70
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 26.
Figure 27.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4246 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
88
75
120
77
76
75
74
73
72
71
70
69
68
67
Input Frequency = 40MHz
Input Frequency = 150MHz
110
100
90
80
70
60
50
40
30
20
87
86
85
84
83
82
81
80
74.5
74
73.5
73
72.5
72
SFDR (dBc)
SFDR (dBFS)
SNR
71.5
SFDR
SNR
71
1.1
0.8
0.85
0.9
0.95
1
1.05
−70
−60
−50
−40
−30
−20
−10
0
Input CommonMode Voltage (V)
Amplitude (dBFS)
Figure 28.
Figure 29.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
91
89
87
85
83
81
79
77
75
73
71
72
71.5
71
Input Frequency = 150MHz
Input Frequency = 150MHz
70.5
70
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
69.5
69
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: ADS4246 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
86
85
84
83
82
81
73
88
87
86
85
84
83
82
74.5
Input Frequency = 150MHz
Input Frequency = 40MHz
74
72.5
72
73.5
73
71.5
71
72.5
72
SFDR
SNR
70.5
SFDR
SNR
71.5
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 32.
Figure 33.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
85
84
83
82
81
80
79
78
77
75
88.5
88
74
Input Frequency = 150MHz
Input Frequency = 10MHz
74
73
72
71
70
69
73.5
73
87.5
87
72.5
72
86.5
86
71.5
68
SFDR
SNR
THD
71
SNR
67
85.5
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 34.
Figure 35.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4246 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
OUTPUT NOISE HISTOGRAM
INTEGRATED NONLINEARITY
(WITH INPUTS SHORTED TO VCM)
80
70
60
50
40
30
20
10
0
1.5
1.2
74.11
Input Frequency=20MHz
RMS Noise = 1.17LSB
0.9
0.6
51.98
0.3
43.17
0
−0.3
−0.6
−0.9
−1.2
−1.5
13.88
13.08
1.69
1.33
0.01 0.11
0.06
0
4000
8000
12000
16000
8211 8212 8213 8214 8215 8216 8217 8218 8219 8220
Output Code (LSB)
Output Code (LSB)
Figure 36.
Figure 37.
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ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4245
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89.7dBc
SFDR = 86.7dBc
SINAD = 73dBFS
SNR = 73.1dBFS
THD = 88.4dBc
SINAD = 71.2dBFS
SNR = 71.4dBFS
THD = 83.8dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 38.
Figure 39.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 73.4dBc
Each Tone at
−7dBFS Amplitude
fIN1 =185MHz
fIN2 =190MHz
SINAD = 67.7dBFS
SNR = 69.2dBFS
THD = 72.3dBc
Two−Tone IMD = 94dBFS
SFDR = 92.8dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 40.
Figure 41.
46
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4245 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 =46MHz
fIN2 =50MHz
Two−Tone IMD = 96.9dBFS
SFDR = 105.3dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
10
20
30
40
50
60
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 42.
Figure 43.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
74
73
72
71
70
69
68
67
66
65
64
63
74
73
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 44.
Figure 45.
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4245 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
72
71
70
69
68
67
66
65
64
63
62
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
Figure 46.
Figure 47.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
110
100
90
76.5
76
110
100
90
77
76
75
74
73
72
71
70
69
Input Frequency = 40MHz
Input Frequency = 150MHz
75.5
75
80
80
70
74.5
74
70
60
60
50
73.5
73
50
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
40
40
30
−70
72.5
30
−70
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 48.
Figure 49.
48
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4245 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
90
73.8
73.7
73.6
73.5
73.4
73.3
73.2
73.1
73
89
73
Input Frequency = 40MHz
Input Frequency = 150MHz
89
88
87
86
85
84
83
82
87
85
83
81
79
77
75
73
72.75
72.5
72.25
72
71.75
71.5
71.25
71
SFDR
SNR
SFDR
SNR
0.8
0.85
0.9
0.95
1
1.05
1.1
0.8
0.85
0.9
0.95
1
1.05
1.1
Input CommonMode (V)
Input CommonMode Voltage (V)
Figure 50.
Figure 51.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
91
89
87
85
83
81
79
77
75
73
71
73
72.5
72
Input Frequency = 150MHz
Input Frequency = 150MHz
71.5
71
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.65
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.9
AVDD = 1.95
70.5
70
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 52.
Figure 53.
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4245 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
88
87
86
85
84
83
82
73
90
89
88
87
86
85
84
74.5
Input Frequency = 150MHz
Input Frequency = 40MHz
72.5
72
74
73.5
73
71.5
71
72.5
70.5
72
SFDR
SNR
70
SFDR
SNR
71.5
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 54.
Figure 55.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
90
88
86
84
82
80
78
76
74
72
70
68
75
Input Frequency = 150MHz
74
89
88
87
86
85
84
83
75
Input Frequency = 10MHz
74.5
74
73
72
71
70
69
68
67
66
73.5
73
72.5
65
64
SFDR
SNR
SNR
THD
72
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 56.
Figure 57.
50
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4245 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
OUTPUT NOISE HISTOGRAM
INTEGRATED NONLINEARITY
(WITH INPUTS SHORTED TO VCM)
40
35
30
25
20
15
10
5
1.5
1.2
RMS Noise = 1.1LSB
Input Frequency=20MHz
33.31
0.9
28.49
0.6
0.3
0
18.26
−0.3
−0.6
−0.9
−1.2
−1.5
12.23
4.52
2.46
0.47
0.01 0.23
0
0
4000
8000
12000
16000
8212 8213 8214 8215 8216 8217 8218 8219 8220 8221
Output Code (LSB)
Output Code (LSB)
Figure 58.
Figure 59.
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4242
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 91.6dBc
SFDR = 88.6dBc
SINAD = 73.2dBFS
SNR = 73.3dBFS
THD = 88.9dBc
SINAD = 71.2dBFS
SNR = 71.4dBFS
THD = 84.2dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 60.
Figure 61.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 76.7dBc
Each Tone at
−7dBFS Amplitude
fIN1 =185MHz
fIN2 =190MHz
SINAD = 68.8dBFS
SNR = 69.4dBFS
THD = 76.3dBc
Two−Tone IMD = 92.2dBFS
SFDR = 93.4dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 62.
Figure 63.
52
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4242 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
95
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 =46MHz
fIN2 =50MHz
Two−Tone IMD = 98dBFS
SFDR = 102.7dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
5
10
15
20
25
30 32.5
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 64.
Figure 65.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
74
73
72
71
70
69
68
67
66
65
64
63
74
73
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 66.
Figure 67.
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4242 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
72
71
70
69
68
67
66
65
64
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
Figure 68.
Figure 69.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
120
110
100
90
77
120
110
100
90
79
78
77
76
75
74
73
72
71
70
69
Input Frequency = 40MHz
Input Frequency = 150MHz
76.5
76
75.5
75
80
80
70
74.5
74
70
60
60
50
73.5
73
50
40
40
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
30
72.5
72
30
20
−70
20
−70
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 70.
Figure 71.
54
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4242 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
91
74.2
74.1
74
85
72
Input Frequency = 40MHz
Input Frequency = 150MHz
90.5
90
84
83
82
81
80
79
78
77
76
75
71.9
71.8
71.7
71.6
71.5
71.4
71.3
71.2
71.1
71
89.5
89
73.9
73.8
73.7
73.6
73.5
73.4
73.3
73.2
88.5
88
87.5
87
86.5
SFDR
SNR
SFDR
SNR
86
0.8
0.85
0.9
0.95
1
1.05
1.1
0.8
0.85
0.9
0.95
1
1.05
1.1
Input CommonMode Voltage (V)
Input CommonMode Voltage (V)
Figure 72.
Figure 73.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
88
86
84
82
80
78
76
72
71.5
71
Input Frequency = 150MHz
Input Frequency = 150MHz
70.5
70
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
69.5
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 74.
Figure 75.
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4242 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
87
86
85
84
83
82
81
75
92
91
90
89
88
87
86
85
84
83
77
Input Frequency = 150MHz
Input Frequency = 40MHz
76
75
74
73
72
71
70
74
73
72
71
70
69
SFDR
SNR
69
SFDR
SNR
68
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 76.
Figure 77.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE ACROSS INPUT CLOCK DUTY CYCLE
88
86
84
82
80
78
76
74
72
70
68
66
64
62
75
91
75
Input Frequency = 150MHz
Input Frequency = 10MHz
74
73
72
71
70
69
68
67
66
65
64
90
89
88
87
86
85
74.5
74
73.5
73
72.5
72
SFDR
63
SNR
THD
SNR
62
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 78.
Figure 79.
56
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Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
www.ti.com
SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4242 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
OUTPUT NOISE HISTOGRAM
INTEGRATED NONLINEARITY
(WITH INPUTS SHORTED TO VCM)
40
35
30
25
20
15
10
5
1.5
1.2
RMS Noise = 1.1LSB
33.31
0.9
28.49
0.6
0.3
0
18.26
−0.3
−0.6
−0.9
−1.2
−1.5
12.23
4.52
0.23
0.47
0.01
0
0
4000
8000
12000
16000
8212 8213 8214 8215 8216 8217 8218 8219 8220 8221
Output Code (LSB)
Output Code (LSB)
Figure 80.
Figure 81.
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ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
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TYPICAL CHARACTERISTICS: ADS4226
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89.7dBc
SFDR = 90.1dBc
SINAD = 70.5dBFS
SNR = 70.6dBFS
THD = 80.0dBc
SINAD = 69.5dBFS
SNR = 69.6dBFS
THD = 88.1dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
Figure 82.
Figure 83.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 76.2dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 185.1MHz
fIN2 = 190.1MHz
SINAD = 67.3dBFS
SNR = 67.9dBFS
THD = 74.4dBc
Two−Tone IMD = 86.5dBFS
SFDR = 92.1dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
Frequency (MHz)
Frequency (MHz)
Figure 84.
Figure 85.
58
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4226 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 = 46.1MHz
fIN2 = 50.1MHz
Two−Tone IMD = 98.2dBFS
SFDR = 101.7dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
10
20
30
40
50
60
70
80
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 86.
Figure 87.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
72
71
70
69
68
67
66
65
64
63
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 88.
Figure 89.
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ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4226 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
90
86
82
78
74
70
66
70
69
68
67
66
65
64
63
62
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
Figure 90.
Figure 91.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
110
100
90
73
110
100
90
80
70
60
50
40
30
20
73
Input Frequency = 40MHz
Input Frequency = 150MHz
72.5
72.5
72
72
71.5
71
80
71.5
71
70
70.5
70
60
70.5
70
50
69.5
69
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
40
69.5
69
30
−70
68.5
−60
−50
−40
−30
−20
−10
0
−70
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 92.
Figure 93.
60
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4226 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
88
73
84
72
Input Frequency = 40MHz
Input Frequency = 150MHz
87
86
85
84
83
82
81
80
72.5
72
83
82
81
80
79
78
77
76
71.5
71
71.5
71
70.5
70
70.5
70
69.5
69
69.5
68.5
SFDR
SNR
SFDR
SNR
69
1.1
68
1.1
0.8
0.85
0.9
0.95
1
1.05
0.8
0.85
0.9
0.95
1
1.05
Input CommonMode Voltage (V)
Input CommonMode Voltage (V)
Figure 94.
Figure 95.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
91
89
87
85
83
81
79
77
75
73
71
70
69.8
69.6
69.4
69.2
69
Input Frequency = 150MHz
Input Frequency = 150MHz
68.8
68.6
68.4
68.2
68
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 96.
Figure 97.
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ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
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TYPICAL CHARACTERISTICS: ADS4226 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
87
86
85
84
83
82
81
71.5
88
87
86
85
84
83
82
72
Input Frequency = 150MHz
Input Frequency = 40MHz
71
71.5
71
70.5
70
70.5
70
69.5
69
69.5
SFDR
SNR
68.5
SFDR
SNR
69
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 98.
Figure 99.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
85
84
83
82
81
80
79
78
77
76
75
71.5
88
88
87
86
86
86
85
84
84
73
Input Frequency = 150MHz
Input Frequency = 10MHz
71
72.5
72
70.5
70
71.5
71
69.5
69
68.5
68
70.5
70
67.5
69.5
SNR
THD
69
67
SFDR
SNR
66.5
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 100.
Figure 101.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4225
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 89.7dBc
SFDR = 86.8dBc
SINAD = 70.6dBFS
SNR = 72.6dBFS
THD = 89.2dBc
SINAD = 69.5dBFS
SNR = 69.6dBFS
THD = 83.7dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 102.
Figure 103.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 73.5dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 185.1MHz
fIN2 = 190.1MHz
SINAD = 66.9dBFS
SNR = 67.9dBFS
THD = 72.7dBc
Two−Tone IMD = 93.4dBFS
SFDR = 91.1dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
Figure 104.
Figure 105.
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4225 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 = 46.1MHz
fIN2 = 50.1MHz
Two−Tone IMD = 96.2dBFS
SFDR = 101.9dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
10
20
30
40
50
60
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 106.
Figure 107.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
72
71
70
69
68
67
66
65
64
63
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 108.
Figure 109.
64
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ADS4222, ADS4225, ADS4226
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4225 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
71
70
68
66
64
62
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Digital Gain (dB)
Figure 110.
Figure 111.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
120
110
100
90
74
120
110
100
90
73.5
Input Frequency = 40MHz
Input Frequency = 150MHz
73.5
73
73
72.5
72
72.5
72
80
80
71.5
71
70
71.5
71
70
60
60
70.5
70
50
70.5
70
50
40
40
69.5
69
SFDR (dBc)
SFDR (dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
30
69.5
69
30
20
−70
20
−70
68.5
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 112.
Figure 113.
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ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4225 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
94
72
89
72
Input Frequency = 40MHz
Input Frequency = 150MHz
92
90
88
86
84
82
80
78
71.8
71.5
71.2
71
87
85
83
81
79
77
75
73
71.5
71
70.5
70
70.8
70.5
70.2
70
69.5
69
68.5
SFDR
SNR
SFDR
SNR
68
1.1
0.8
0.85
0.9
0.95
1
1.05
1.1
0.8
0.85
0.9
0.95
1
1.05
Input CommonMode (V)
Input CommonMode Voltage (V)
Figure 114.
Figure 115.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
90
88
86
84
82
80
78
76
74
72
70
70.5
70.2
70
Input Frequency = 150MHz
Input Frequency = 150MHz
69.8
69.5
69.2
69
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
68.8
68.5
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 116.
Figure 117.
66
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ADS4222, ADS4225, ADS4226
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4225 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
88
87
86
85
84
83
82
72
90
89
88
87
86
85
84
72
Input Frequency = 150MHz
Input Frequency = 40MHz
71.5
71
71.5
71
70.5
70
70.5
70
69.5
69.5
SFDR
SNR
69
SFDR
SNR
69
1.65
1.7
1.75
1.8
1.85
1.9
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 118.
Figure 119.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
72
90
89
88
87
86
85
84
83
82
73
Input Frequency = 40MHz
Input Frequency = 10MHz
71.5
71
72.5
72
70.5
70
69.5
69
71.5
71
68.5
68
67.5
67
70.5
70
66.5
66
65.5
65
69.5
THD
SNR
69
SFDR
SNR
64.5
64
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 120.
Figure 121.
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ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
TYPICAL CHARACTERISTICS: ADS4222
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR 20MHz INPUT SIGNAL
FFT FOR 170MHz INPUT SIGNAL
0
−20
0
−20
SFDR = 90.9dBc
SFDR = 88.2dBc
SINAD = 70.8dBFS
SNR = 70.9dBFS
THD = 88.1dBc
SINAD = 69.5dBFS
SNR = 69.7dBFS
THD = 84.9dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 122.
Figure 123.
FFT FOR 300MHz INPUT SIGNAL
FFT FOR TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 88.8dBc
Each Tone at
−7dBFS Amplitude
fIN1 = 185.1MHz
fIN2 = 190.1MHz
SINAD = 72.6dBFS
SNR = 72.6dBFS
THD = 89.2dBc
Two−Tone IMD = 91.6dBFS
SFDR = 94.9dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
5
10
15
20
25
30 32.5
0
5
10
15
20
25
30 32.5
Frequency (MHz)
Frequency (MHz)
Figure 124.
Figure 125.
68
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4222 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
FFT FOR TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
−20
95
90
85
80
75
70
65
Each Tone at
−7dBFS Amplitude
fIN1 = 46.1MHz
fIN2 = 50.1MHz
Two−Tone IMD =
98.9 dBFS
SFDR = 100.4 dBFS
−40
−60
−80
−100
−120
Gain = 0dB
Gain = 6dB
0
5
10
15
20
25
30 32
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Frequency (MHz)
Figure 126.
Figure 127.
SNR vs INPUT FREQUENCY
SNR vs INPUT FREQUENCY (CMOS)
72
71
70
69
68
67
66
65
64
63
72
71
70
69
68
67
66
65
64
63
Gain = 0dB
Gain = 6dB
Gain = 0dB
Gain = 6dB
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
0
50 100 150 200 250 300 350 400 450 500
Input Frequency (MHz)
Figure 128.
Figure 129.
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TYPICAL CHARACTERISTICS: ADS4222 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
SFDR vs GAIN AND INPUT FREQUENCY
SINAD vs GAIN AND INPUT FREQUENCY
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
71
70
69
68
67
66
65
64
63
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
150MHz
170MHz
220MHz
300MHz
400MHz
470MHz
Input Frequency = 150MHz
3.5 4.5 5.5 6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
4
5
Digital Gain (dB)
Digital Gain (dB)
Figure 130.
Figure 131.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT AMPLITUDE
120
110
100
90
73.5
120
110
100
90
73.5
Input Frequency = 40MHz
Input Frequency = 150MHz
73
73
72.5
72
72.5
72
80
80
71.5
71
70
71.5
71
70
60
60
70.5
70
50
50
70.5
70
40
40
69.5
69
SFDR(dBc)
SFDR(dBFS)
SNR
SFDR(dBc)
SFDR(dBFS)
SNR
30
30
20
−70
69.5
20
−70
68.5
−60
−50
−40
−30
−20
−10
0
−60
−50
−40
−30
−20
−10
0
Amplitude (dBFS)
Amplitude (dBFS)
Figure 132.
Figure 133.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: ADS4222 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
92
72
85
70.8
70.6
70.4
70.2
70
Input Frequency = 40MHz
Input Frequency = 150MHz
91
90
89
88
87
86
85
84
83
82
71.8
71.6
71.4
71.2
71
84
83
82
81
80
79
78
77
76
75
69.8
69.6
69.4
69.2
69
70.8
70.6
70.4
70.2
70
SFDR
SNR
SFDR
SNR
68.8
1.1
0.8
0.85
0.9
0.95
1
1.05
1.1
0.8
0.85
0.9
0.95
1
1.05
Input Common−Mode Voltage (V)
Input Common−Mode Voltage (V)
Figure 134.
Figure 135.
SFDR vs TEMPERATURE AND AVDD SUPPLY
SNR vs TEMPERATURE AND AVDD SUPPLY
88
87
86
85
84
83
82
81
80
79
78
77
70
69.8
69.5
69.2
69
Input Frequency = 150MHz
Input Frequency = 150MHz
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
AVDD = 1.7
AVDD = 1.75
AVDD = 1.80
AVDD = 1.85
AVDD = 1.90
AVDD = 1.95
68.8
−40
−15
10
35
60
85
−40
−15
10
35
60
85
Temperature (°C)
Temperature (°C)
Figure 136.
Figure 137.
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TYPICAL CHARACTERISTICS: ADS4222 (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
87
86
85
84
83
82
71
92
91
90
89
88
87
86
85
84
83
82
72.5
Input Frequency = 150MHz
Input Frequency = 40MHz
72
70.5
70
71.5
71
70.5
70
69.5
69
69.5
69
68.5
68
SFDR
SNR
68.5
SFDR
SNR
67.5
1.65
1.70
1.75
1.80
1.85
1.90
1.95
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
DRVDD Supply (V)
Differential Clock Amplitude (VPP
)
Figure 138.
Figure 139.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
93
90
87
84
81
78
75
72
69
66
63
60
71
Input Frequency = 150MHz
70
94
93
92
91
90
89
88
87
86
85
84
72
Input Frequency = 10MHz
71.5
71
69
68
67
66
65
64
63
62
70.5
70
69.5
69
68.5
68
67.5
SNR
THD
67
61
60
SFDR
SNR
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2
30
35
40
45
50
55
60
65
70
Input Clock Duty Cycle (%)
Differential Clock Amplitude (VPP
)
Figure 140.
Figure 141.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: General
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
CMRR vs TEST SIGNAL FREQUENCY
PSRR vs TEST SIGNAL FREQUENCY
0
−5
0
−5
Input Frequency = 40MHz
50mVPP Signal Superimposed
on Input Common−Mode Voltage 0.95V
Input Frequency = 10MHz
50mVPP Signal Superimposed on AVDD Supply
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
−10
−15
−20
−25
−30
−35
−40
−45
−50
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Frequency of Input Common−Mode Signal (MHz)
Frequency of Signal on Supply (MHz)
Figure 142.
Figure 143.
ANALOG POWER vs SAMPLING FREQUENCY
DIGITAL POWER LVDS CMOS
240
220
200
180
160
140
120
100
80
240
220
200
180
160
140
120
100
80
fIN = 2.5 MHz
AVDD = 1.8V
Input Frequency = 2.5MHz
60
40
LVDS, 350mV Swing
CMOS
20
60
0
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100 120
140
160
Sampling Speed (MSPS)
Sampling Speed (MSPS)
Figure 144.
Figure 145.
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TYPICAL CHARACTERISTICS: General (continued)
At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential
clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR
LVDS output interface, and 32k point FFT, unless otherwise noted.
DIGITAL POWER IN VARIOUS MODES (LVDS)
260
Default
EN Digital = 1
EN Digital = 1, Offset Correction Enabled
240
220
200
180
160
140
120
100
80
0
20
40
60
80
100
120
140
160
Sampling Speed (MSPS)
Figure 146.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: Contour
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE (0dB Gain)
160
79
76
83
73
150
140
130
120
110
100
90
83
87
87
87
79
76
73
87
87
79
83
76
80
83
73
73
83
87
100
70
65
91
10
50
150
200
250
300
350
400
450
90
Input Frequency (MHz)
80
75
85
70
SFDR (dBc)
Figure 147.
SPURIOUS-FREE DYNAMIC RANGE (6dB Gain)
160
150
140
130
120
110
100
90
77
79
83
81
83
86
83
86
86
79
81
83
83
79
86
83
89
79
89
79
81
80
89
83
86
79
70
65
79
92
10
50
100
150
200
250
300
86
350
400
450
Input Frequency (MHz)
84
80
82
88
90
92
78
SFDR (dBc)
Figure 148.
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TYPICAL CHARACTERISTICS: Contour (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
ADS424x SIGNAL-TO-NOISE RATIO (0dB Gain)
160
150
71
73
72
70
69
67
68
68
140
130
120
110
100
90
73
71
72
70
69
67
71
72
73
68
70
80
67
69
70
65
10
50
100
150
200
250
300
350
400
72
450
Input Frequency (MHz)
70
68
69
71
73
67
SNR (dBFS)
Figure 149.
ADS424x SIGNAL-TO-NOISE RATIO (6dB Gain)
160
150
140
130
120
110
100
90
67
64.5
65
65
65
66.5
66.75
67
65.5
66
66.25
66.25
67
67.25
66.75
66
65.5
66.5
67.25
67
67.5
66.75
66
66.25
65.5
66.5
80
67.25
64.5
67
67.5
50
70
65
10
100
150
200
250
300
350
400
67
450
Input Frequency (MHz)
66
65
65.5
66.5
67.5
64.5
SNR (dBFS)
Figure 150.
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SBAS533C –MARCH 2011–REVISED JUNE 2011
TYPICAL CHARACTERISTICS: Contour (continued)
All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP
differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
ADS422x SIGNAL-TO-NOISE RATIO (0dB Gain)
160
70
67
150
140
130
120
110
100
90
70.5
69
67.5
68
66.5
68.5
69.5
69.5
70
67
68
67.5
68.5
69
66
66.5
70.5
67
69.5
150
69
80
70
66.5
68.5
70.5
67.5
68
66
69
70
65
10
50
100
200
250
300
350
400
450
Input Frequency (MHz)
66.5
67
67.5
68
68.5
69
69.5
70
70.5
66
SNR (dBFS)
Figure 151.
ADS422x SIGNAL-TO-NOISE RATIO (6dB Gain)
160
150
140
130
120
110
100
90
65.75
66
66.25
65.75
65.75
65.5
64.5
64.5
65
66.25
66.5
66
65.5
66.5
65
66
66.25
65.5
80
66.75
65
64.5
400
65.75
66.5
70
65
10
64
50
100
150
200
250
300
350
66
450
Input Frequency (MHz)
65.5
64.5
65
66.5
SNR (dBFS)
Figure 152.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS424x/422x belong to TI's ultralow-power family of dual-channel 12-bit and 14-bit analog-to-digital
converters (ADCs). At every rising edge of the input clock, the analog input signal of each channel is
simultaneously sampled. The sampled signal in each channel is converted by a pipeline of low-resolution stages.
In each stage, the sampled/held signal is converted by a high-speed, low-resolution, flash sub-ADC. The
difference between the stage input and the quantized equivalent is gained and propagates to the next stage. At
every clock, each succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all
stages are combined in a digital correction logic block and digitally processed to create the final code after a data
latency of 16 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in
either straight offset binary or binary twos complement format. The dynamic offset of the first stage sub-ADC
limits the maximum analog input frequency to approximately 400MHz (with 2VPP amplitude) or approximately
600MHz (with 1VPP amplitude).
ANALOG INPUT
The analog input consists of a switched-capacitor based, differential sample-and-hold (S/H) architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 0.95V, available on the
VCM pin. For a full-scale differential input, each input pin (INP and INM) must swing symmetrically between
VCM + 0.5V and VCM – 0.5V, resulting in a 2VPP differential input swing. The input sampling circuit has a high
3dB bandwidth that extends up to 550MHz (measured from the input pins to the sampled voltage). Figure 153
shows an equivalent circuit for the analog input.
Sampling
Switch
LPKG
Sampling
Capacitor
2nH
10W
RCR Filter
INP
RON
CBOND
1pF
CPAR2
1pF
CSAMP
2pF
100W
15W
RESR
3pF
200W
CPAR1
0.5pF
RON
10W
3pF
LPKG
2nH
CSAMP
2pF
100W
RON
10W
15W
INM
CBOND
1pF
CPAR2
1pF
Sampling
Capacitor
RESR
Sampling
Switch
200W
Figure 153. Analog Input Equivalent Circuit
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SBAS533C –MARCH 2011–REVISED JUNE 2011
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This operation improves the
common-mode noise immunity and even-order harmonic rejection. A 5Ω to 15Ω resistor in series with each input
pin is recommended to damp out ringing caused by package parasitics.
SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;
nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending
on the input frequency, sample rate, and input amplitude, one of these factors plays a dominant part in limiting
performance. At very high input frequencies (greater than approximately 300MHz), SFDR is determined largely
by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits
performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low
input frequencies (up to approximately 200MHz). It is also necessary to present low impedance (less than 50Ω)
for the common-mode switching currents. This configuration can be achieved by using two resistors from each
input terminated to the common-mode voltage (VCM).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches now must be
supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package
bond-wire inductance.
In the ADS424x/422x, the R-C component values have been optimized while supporting high input bandwidth (up
to 550MHz). However, in applications with input frequencies up to 200MHz to 300MHz, the filtering of the glitches
can be improved further using an external R-C-R filter; see Figure 156 and Figure 157.
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. Furthermore, the ADC input impedance must be considered.
Figure 154 and Figure 155 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
100
5
4.5
4
10
3.5
3
1
2.5
2
0.1
0.01
1.5
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
Figure 154. ADC Analog Input Resistance (RIN)
Across Frequency
Figure 155. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
Two example driving circuit configurations are shown in Figure 156 and Figure 157—one optimized for low
bandwidth (low input frequencies) and the other one for high bandwidth to support higher input frequencies. Note
that both of the drive circuits have been terminated by 50Ω near the ADC side. The termination is accomplished
by a 25Ω resistor from each input to the 1.5V common-mode (VCM) from the device. This architecture allows the
analog inputs to be biased around the required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch;
good performance is obtained for high-frequency input signals. An additional termination resistor pair may be
required between the two transformers, as shown in Figure 156, Figure 157, and Figure 158. The center point of
this termination is connected to ground to improve the balance between the P and M sides. The values of the
terminations between the transformers and on the secondary side must be chosen to obtain an effective 50Ω (in
the case of 50Ω source impedance).
0.1mF
15W
INx_P
T1
T2
0.1mF
25W
25W
25W
0.1mF
3.3pF
25W
RIN
CIN
INx_M
VCM
1:1
1:1
15W
0.1mF
ADS42xx
Figure 156. Drive Circuit with Low Bandwidth (for Low Input Frequencies Less Than 150MHz)
0.1mF
5W
INx_P
T1
T2
0.1mF
25W
25W
50W
0.1mF
3.3pF
50W
RIN
CIN
INx_M
VCM
1:1
1:1
5W
0.1mF
ADS42xx
Figure 157. Drive Circuit with High Bandwidth (for High Input Frequencies Greater Than 150MHz and
Less Than 270MHz)
0.1mF
5W
INx_P
T1
T2
0.1mF
25W
25W
0.1mF
RIN
CIN
INx_M
VCM
1:1
1:1
5W
0.1mF
ADS42xx
Figure 158. Drive Circuit with Very High Bandwidth (Greater than 270MHz)
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All of these examples show 1:1 transformers being used with a 50Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200Ω. The higher source impedance is unable to
absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1
transformers).
In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance,
as shown in Figure 159. Such filters present low source impedance at the high frequencies corresponding to the
sampling glitch and help avoid the performance loss with the high source impedance.
5W
INx_P
T1
100W
Band-Pass
or
0.1mF
0.1mF
Differential
Input Signal
RIN
CIN
Low-Pass
Filter
100W
INx_M
VCM
1:4
5W
ADS42xx
Figure 159. Drive Circuit with a 1:4 Transformer
CLOCK INPUT
The ADS424x/422x clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended
(LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock
inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits
for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 160, Figure 161
and Figure 162. The internal clock buffer is shown in Figure 163.
(1) RT = termination resister, if necessary.
0.1mF
0.1mF
Zo
CLKP
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100W
0.1mF
CLKM
ADS42xx
0.1mF
Zo
CLKM
ADS42xx
Figure 160. Differential Sine-Wave Clock Driving
Circuit
Zo
Figure 161. LVDS Clock Driving Circuit
0.1mF
CLKP
150W
Typical LVPECL
Clock Input
100W
0.1mF
Zo
CLKM
ADS42xx
150W
Figure 162. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2nH
20W
CLKP
CBOND
CEQ
CEQ
5kW
1pF
RESR
100W
2pF
VCM
LPKG
2nH
5kW
20W
CLKM
CBOND
1pF
RESR
100W
NOTE: CEQ is 1pF to 3pF and is the equivalent input capacitance of the clock buffer.
Figure 163. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1μF
capacitor, as shown in Figure 164. For best performance, the clock inputs must be driven differentially, thereby
reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a
clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There
is no change in performance with a non-50% duty cycle clock input.
0.1mF
CMOS
Clock Input
CLKP
VCM
0.1mF
CLKM
ADS42xx
Figure 164. Single-Ended Clock Driving Circuit
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DIGITAL FUNCTIONS
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device. These
digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with
a latency of 16 clock cycles. Figure 165 shows more details of the processing after the ADC. In order to use any
of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be
programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
12-/14-Bit
ADC
12-Bit (ADS422x)
14-Bit (ADS424x)
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
Figure 165. Digital Processing Block
GAIN FOR SFDR/SNR TRADE-OFF
The ADS424x/422x include gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0dB to 6dB (in 0.5dB steps). For each gain setting, the analog input
full-scale range scales proportionally, as shown in Table 11.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5dB and 1dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0dB.
Table 11. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
1
2
3
4
5
6
Default after reset
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
2
1.78
1.59
1.42
1.26
1.12
1
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OFFSET CORRECTION
The ADS424x/422x have an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV.
The correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the
algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the
correction loop is a function of the sampling clock frequency. The time constant can be controlled using the
OFFSET CORR TIME CONSTANT register bits, as described in Table 12.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
Table 12. Time Constant of Offset Correction Algorithm
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK × 1/fS (ms)(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1M
2M
7
13
4M
26
8M
52
16M
105
210
419
839
1678
3355
6711
13422
—
32M
64M
128M
256M
512M
1G
2G
Reserved
Reserved
Reserved
Reserved
—
—
—
(1) Sampling frequency, fS = 160MSPS.
POWER-DOWN
The ADS424x/422x have two power-down modes: global power-down and channel standby. These modes can
be set using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 13).
Table 13. Power-Down Settings
CTRL1
Low
CTRL2
Low
CTRL3
Low
DESCRIPTION
Default
Low
Low
High
Low
Not available
Not available
Not available
Global power-down
Low
High
High
Low
Low
High
Low
High
High
High
Low
High
Low
Channel A powered down, channel B is active
Not available
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[10:0] pins
High
High
High
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Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of approximately 20mW when the CTRL pins are used and 3mW when the
PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time from
global power-down to data becoming valid in normal mode is typically 100µs.
Channel Standby
In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick
wake-up time of 50µs. The total power dissipation in standby is approximately 200mW at 160MSPS.
Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1MSPS. The power dissipation is approximately 160mW.
DIGITAL OUTPUT INFORMATION
The ADS424x/422x provide 14-bit/12-bit digital data for each channel and an output clock synchronized with the
data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel
configuration mode.
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DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 166.
Pins
CLKOUTP
Output
Clock
CLKOUTM
DB0_P
Data Bits
D0, D1
DB0_M
DB2_P
Data Bits
D2, D3
DB2_M
DB4_P
Data Bits
D4, D5
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
Data Bits
D6, D7
DB8_P
DB8_M
Data Bits
D8, D9
DB10_P
DB10_M
Data Bits
D10, D11
DB12_P
DB12_M
Data Bits
D12, D13
Figure 166. LVDS Interface
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Even data bits (D0, D2, D4, etc.) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, etc.)
are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all
the data bits, as shown in Figure 167.
CLKOUTM
CLKOUTP
DA0P/M, DB0P/M
DA2P/M, DB2P/M
DA4P/M, DB4P/M
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA6P/M, DB6P/M
DA8P/M, DB8P/M
D6
D8
D7
D9
D6
D8
D7
D9
DA10P/M, DB10P/M
DA12P/M, DB12P/M
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
Figure 167. DDR LVDS Interface Timing
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LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 168. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100Ω termination.
VDIFF
High
Low
OUTP
OUTM
External
100W Load
VOCM
ROUT
VDIFF
High
Low
NOTE: Default swing across 100Ω load is ±350mV. Use the LVDS SWING bits to change the swing.
Figure 168. LVDS Buffer Equivalent Circuit
The VDIFF voltage is nominally 350mV, resulting in an output swing of ±350mV with 100Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125mV to ±570mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50Ω differential termination, as
shown in Figure 169. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1
100W
CLKOUTP
CLKOUTM
CLKIN2
100W
DBnP/M
Receiver Chip # 2
ADS42xx
Make LVDS CLKOUT STRENGTH = 1
Figure 169. LVDS Buffer Differential Termination
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Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as
Figure 170 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is
recommended to minimize the load capacitance of the data and clock output pins by using short traces to the
receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
DB1
DB2
14-Bit ADC Data,
Channel B
DB11
DB12
DB13
SDOUT
CLKOUT
DA0
DA1
DA2
14-Bit ADC Data,
Channel A
DA11
DA12
DA13
Figure 170. CMOS Outputs
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CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal. This relationship is shown by the formula:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[13:0] pins), as
shown in Figure 171. The channel A output pins (DA[13:0]) are in 3-state. Because the output data rate on the
DB bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 80MSPS).
This mode can be enabled using the POWER-DOWN MODE register bits or using the CTRL[3:1] parallel pins.
CLKM
Input
Clock
CLKP
tPDI
Output
CLKOUT
Clock
tSU
tH
Channel A
DAn(2)
Channel B
DBn(2)
Channel A
DAn(2)
Output
Data
DBn(1)
(1) In multiplexed mode, both channels outputs come on the channel B output pins.
(2) Dn = bits D0, D1, D2, etc.
Figure 171. Multiplexed Mode Timing Diagram
Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit or by controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is FFFh for the ADS422x and 3FFFh for the ADS424x in offset binary output format;
the output code is 7FFh for the ADS422x and 1FFFh for the ADS424x in twos complement output format. For a
negative input overdrive, the output code is 0000h in offset binary output format and 800h for the ADS422x and
2000h for the ADS424x in twos complement output format.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
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Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter
full-scale range.
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Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(3)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
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BOARD DESIGN CONSIDERATIONS
Grounding
A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and
grounding.
Supply Decoupling
Because the ADS424x/422x already include internal decoupling, minimal external decoupling can be used
without loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus,
the optimum number of capacitors depends on the actual application. The decoupling capacitors should be
placed very close to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
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Routing Analog Inputs
It is advisable to route differential analog input pairs (INP_x and INM_x) close to each other. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
should be routed perpendicular to the sampling clock. See the ADS4226 Evaluation Module (SLAU333) for
reference routing. Figure 172 shows a snapshot of the PCB layout from the ADS424x EVM.
Figure 172. ADS42xx EVM PCB Layout
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2011) to Revision C
Page
•
•
•
•
•
•
Changed device status from Mixed Status to Production Data ............................................................................................ 1
Changed 125MSPS sub-bullet of first Features bullet .......................................................................................................... 1
Changed sub-bullets of second Features bullet ................................................................................................................... 1
Changed status of ADS4222 and ADS4225 from Product Preview to Production Data ...................................................... 2
Moved High-Performance Modes into separate table .......................................................................................................... 4
Changed ADS4246 fIN = 170MHz Worst spur typical spcification in the ADS4246/ADS4245/ADS4242 Electrical
Characteristics table ............................................................................................................................................................. 5
•
•
•
•
•
Added ADS4225/ADS4222 fIN = 70MHz SNR, SINAD, SFDR, THD, HD2, HD3, and Worst spur minimum and typical
spcifications in the ADS4226/ADS4225/ADS4222 Electrical Characteristics table .............................................................. 7
Added ADS4225/ADS4222 DNL minimum and maximum spcifications in the ADS4226/ADS4225/ADS4222
Electrical Characteristics table .............................................................................................................................................. 8
Added ADS4225/ADS4222 INL maximum spcifications in the ADS4226/ADS4225/ADS4222 Electrical
Characteristics table ............................................................................................................................................................. 8
Changed ADS4242/ADS4222 Power Supply, Digital power LVDS interface typical specification in Electrical
Characteristics: General table .............................................................................................................................................. 9
Changed ADS4245/ADS4225 Power Supply, Digital power CMOS interface typical specification in Electrical
Characteristics: General table .............................................................................................................................................. 9
•
•
•
•
•
•
Changed description of pin 64 in Pin Descriptions: LVDS Mode table .............................................................................. 13
Changed description of pin 64 in Pin Descriptions: CMOS Mode table ............................................................................. 17
Changed description of READOUT disabled in Serial Register Readout section .............................................................. 27
Updated Figure 14 .............................................................................................................................................................. 27
Changed READOUT desciption in Register Address 00h section ..................................................................................... 29
Changed CLKOUT FALL POSN and CLKOUT RISE POSN description in Register Address 42h section ....................... 34
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
95
Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
ADS4222, ADS4225, ADS4226
ADS4242, ADS4245, ADS4246
SBAS533C –MARCH 2011–REVISED JUNE 2011
www.ti.com
Changes from Revision A (May 2011) to Revision B
Page
•
•
•
•
•
•
•
•
•
Changed sub-bullets of first Features bullet ......................................................................................................................... 1
Changed last row of Performance Summary table ............................................................................................................... 1
Updated ADS424x/422x Family Pins section in Table 1 ...................................................................................................... 2
Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 table ...... 6
Deleted INL minimum specifications from Electrical Characteristics: ADS4246/ADS4245/ADS4242 table ......................... 6
Changed INL maximum specifications in the Electrical Characteristics: ADS4246/ADS4245/ADS4242 table .................... 6
Changed ENOB, DNL, and INL test conditions in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 table ...... 8
Changed ADS4226 INL maximum specification in the Electrical Characteristics: ADS4226/ADS4225/ADS4222 table ..... 8
Changed Power Supply, IDRVDD and Digital power CMOS interface rows in the Electrical Characteristics: General
table ...................................................................................................................................................................................... 9
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated Figure 2 NC note .................................................................................................................................................. 11
Updated Figure 3 NC note .................................................................................................................................................. 12
Updated description of NC pin in LVDS Pin Descriptions table ......................................................................................... 14
Updated Figure 4 NC note .................................................................................................................................................. 15
Updated Figure 5 NC note .................................................................................................................................................. 16
Updated description of NC pin in CMOS Pin Descriptions table ........................................................................................ 17
Changed 111110 and 001111 LVDS SWING description in Register Address 01h .......................................................... 29
Updated Figure 26 .............................................................................................................................................................. 42
Updated Figure 28 .............................................................................................................................................................. 43
Updated Figure 48 and Figure 49 ....................................................................................................................................... 48
Updated Figure 50 and Figure 51 ....................................................................................................................................... 49
Updated Figure 70 and Figure 71 ....................................................................................................................................... 54
Updated Figure 72 and Figure 73 ....................................................................................................................................... 55
Updated Figure 92 and Figure 93 ....................................................................................................................................... 60
Updated Figure 94 and Figure 95 ....................................................................................................................................... 61
Updated Figure 113 ............................................................................................................................................................ 65
Updated Figure 114 and Figure 115 ................................................................................................................................... 66
Updated Figure 133 ............................................................................................................................................................ 70
Updated Figure 145 ............................................................................................................................................................ 73
Changed title of Figure 146 ................................................................................................................................................ 74
96
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Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS4222IRGCR
ADS4222IRGCT
ADS4225IRGC25
ADS4225IRGCR
ADS4225IRGCT
ADS4226IRGC25
PREVIEW
PREVIEW
PREVIEW
PREVIEW
PREVIEW
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
2000
250
25
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
2000
250
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
ADS4226IRGCR
ADS4226IRGCT
ADS4242IRGCR
ADS4242IRGCT
ADS4245IRGC25
ADS4245IRGCR
ADS4245IRGCT
ADS4246IRGC25
ADS4246IRGCR
ADS4246IRGCT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
64
64
2000
250
2000
250
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
250
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2011
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS4226IRGCR
ADS4226IRGCT
ADS4242IRGCR
ADS4242IRGCT
ADS4245IRGCR
ADS4245IRGCT
ADS4246IRGCR
ADS4246IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
9.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
2000
250
2000
250
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS4226IRGCR
ADS4226IRGCT
ADS4242IRGCR
ADS4242IRGCT
ADS4245IRGCR
ADS4245IRGCT
ADS4246IRGCR
ADS4246IRGCT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RGC
RGC
RGC
RGC
RGC
RGC
RGC
RGC
64
64
64
64
64
64
64
64
2000
250
333.2
333.2
333.2
333.2
333.2
333.2
333.2
333.2
345.9
345.9
345.9
345.9
345.9
345.9
345.9
345.9
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
2000
250
2000
250
2000
250
Pack Materials-Page 2
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