ADS4249_16 [TI]
Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC;
| 型号： | ADS4249_16 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC |
| 文件： | 总67页 (文件大小：1528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS4249
www.ti.com
SBAS534C –JULY 2011–REVISED JULY 2012
Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC
Check for Samples: ADS4249
1
FEATURES
APPLICATIONS
23
•
Maximum Sample Rate: 250 MSPS
•
•
•
Wireless Communications Infrastructure
Software Defined Radio
•
Ultralow Power with Single 1.8-V Supply:
–
560-mW Total Power at 250 MSPS
Power Amplifier Linearization
•
High Dynamic Performance:
DESCRIPTION
–
–
80-dBc SFDR at 170 MHz
71.7-dBFS SNR at 170 MHz
The ADS4249 is a member of the ADS42xx ultralow-
power family of dual-channel, 12-bit/14-bit analog-to-
digital converters (ADCs). Innovative design
techniques are used to achieve high dynamic
performance, while consuming extremely low power
with a 1.8-V supply. This topology makes the
ADS4249 well-suited for multi-carrier, wide-bandwidth
communications applications.
•
•
Crosstalk: > 90 dB at 185 MHz
Programmable Gain Up to 6 dB for
SNR/SFDR Trade-off
•
•
DC Offset Correction
Output Interface Options:
–
–
1.8-V Parallel CMOS Interface
The ADS4249 has gain options that can be used to
improve SFDR performance at lower full-scale input
ranges. This device also includes
Double Data Rate (DDR) LVDS with
Programmable Swing:
a dc offset
correction loop that can be used to cancel the ADC
offset. Both DDR LVDS and parallel CMOS digital
output interfaces are available in a compact QFN-64
PowerPAD™ package.
–
–
Standard Swing: 350 mV
Low Swing: 200 mV
•
•
Supports Low Input Clock Amplitude
Down to 200 mVPP
The device includes internal references while the
traditional reference pins and associated decoupling
capacitors have been eliminated. The ADS4249 is
specified over the industrial temperature range
(–40°C to +85°C).
Package: 9-mm × 9-mm, 64-Pin Quad Flat No-
Lead (QFN) Package
ADS424x/2x Family Comparison(1)
65 MSPS
125 MSPS
160 MSPS
250 MSPS
ADS422x
12-bit family
ADS4222
ADS4225
ADS4226
ADS4229
ADS424x
14-bit family
ADS4242
ADS4245
ADS4246
ADS4249
(1) See Table 1 for details on migrating from the ADS62P49 family.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
2
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
ADS4249
SBAS534C –JULY 2011–REVISED JULY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE-
LEAD
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
LEAD/BALL
FINISH
PACKAGE
MARKING
ORDERING
NUMBER
PRODUCT
ECO PLAN(2)
TRANSPORT MEDIA
Tape and reel
ADS4249IRGCT
ADS4249IRGCR
GREEN (RoHS,
no Sb/Br)
ADS4249
QFN-64
RGC
–40°C to +85°C
Cu/NiPdAu
AZ4249
Tape and reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Eco Plan is the planned eco-friendly classification. Green (RoHS, no Sb/Br): TI defines Green to mean Pb-Free (RoHS compatible) and
free of Bromine- (Br) and Antimony- (Sb) based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more
information.
The ADS4249 is pin-compatible with the previous generation ADS62P49 data converter; this similar architecture
enables easy migration. However, there are some important differences between the two device generations,
summarized in Table 1.
Table 1. Migrating from the ADS62P49
ADS62P49
ADS4249
PINS
Pin 22 is NC (not connected)
Pins 38 and 58 are DRVDD
Pins 39 and 59 are DRGND
SUPPLY
Pin 22 is AVDD
Pins 38 and 58 are NC (do not connect, must be floated)
Pins 39 and 59 are NC (do not connect, must be floated)
AVDD is 3.3 V
AVDD is 1.8 V
No change
DRVDD is 1.8 V
INPUT COMMON-MODE VOLTAGE
VCM is 1.5 V
VCM is 0.95 V
SERIAL INTERFACE
No change in protocol
New serial register map
Protocol: 8-bit register address and 8-bit register data
EXTERNAL REFERENCE
Supported
Not supported
2
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SBAS534C –JULY 2011–REVISED JULY 2012
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
MIN
–0.3
–0.3
–0.3
–2.4
–2.4
MAX
2.1
2.1
0.3
2.4
2.4
UNIT
Supply voltage range, AVDD
V
V
V
V
V
Supply voltage range, DRVDD
Voltage between AGND and DRGND
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)
Minimum
(1.9, AVDD + 0.3)
INP_A, INM_A, INP_B, INM_B
CLKP, CLKM(2)
–0.3
–0.3
–0.3
–40
V
V
V
Voltage applied to input pins
AVDD + 0.3
RESET, SCLK, SDATA, SEN,
CTRL1, CTRL2, CTRL3
3.9
Operating free-air temperature range, TA
Operating junction temperature range, TJ
Storage temperature range, Tstg
ESD rating
+85
+125
+150
2
°C
°C
°C
kV
–65
Human body model (HBM)
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3 V|).
This configuration prevents the ESD protection diodes at the clock input pins from turning on.
THERMAL INFORMATION
ADS4249
THERMAL METRIC(1)
RGC
64 PINS
23.9
10.9
4.3
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.1
ψJB
4.4
θJCbot
0.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
ADS4249
NOM
PARAMETER
MIN
MAX
UNIT
SUPPLIES
Analog supply voltage, AVDD
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Digital supply voltage, DRVDD
ANALOG INPUTS
Differential input voltage range
2
VPP
V
Input common-mode voltage
VCM ± 0.05
400
Maximum analog input frequency with 2-VPP input amplitude(1)
Maximum analog input frequency with 1-VPP input amplitude(1)
CLOCK INPUT
MHz
MHz
600
Input clock sample rate
Low-speed mode enabled(2)
Low-speed mode disabled(2) (by default after reset)
1
80
MSPS
MSPS
VPP
80
250
Sine wave, ac-coupled
0.2
1.5
1.6
0.7
1.5
LVPECL, ac-coupled
VPP
Input clock amplitude differential
(VCLKP – VCLKM
)
LVDS, ac-coupled
VPP
LVCMOS, single-ended, ac-coupled
V
Input clock duty cycle
Low-speed mode disabled
Low-speed mode enabled
DIGITAL OUTPUTS
35
40
50
50
65
60
%
%
Maximum external load capacitance from each output pin to DRGND, CLOAD
Differential load resistance between the LVDS output pairs (LVDS mode), RLOAD
Operating free-air temperature, TA
5
pF
Ω
100
–40
+85
°C
(1) See the Theory of Operation section in the Application Information.
(2) See the Serial Interface Configuration section for details on programming the low-speed mode.
HIGH-PERFORMANCE MODES(1)(2)
PARAMETER
DESCRIPTION
Set the HIGH PERF MODE[2:1] register bit to obtain best performance across sample clock and input signal
High-performance mode
frequencies.
Register address = 03h, data = 03h
Set the HIGH FREQ MODE CH A and HIGH FREQ MODE CH B register bits for high input signal frequencies
greater than 200 MHz.
Register address = 4Ah, data = 01h
Register address = 58h, data = 01h
High-frequency mode
High-speed mode
Set the HIGH PERF MODE[8:3] bits to obtain best performance across input signal frequencies for sampling
rates greater than 160 MSPS.
Note that this mode changes VCM to 0.87 V from its default value of 0.95 V.
Register address = 2h, data = 40h
Register address = D5h, data = 18h
Register address = D7h, data = 0Ch
Register address = DBh, data = 20h
(1) It is recommended to use these modes to obtain best performance.
(2) See the Serial Interface Configuration section for details on register programming.
4
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SBAS534C –JULY 2011–REVISED JULY 2012
ELECTRICAL CHARACTERISTICS: ADS4249
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1 dBFS differential analog input, LVDS
interface, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range:
TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
ADS4249 (250 MSPS)
PARAMETER
TEST CONDITIONS
MIN
67.5
66.5
71
TYP
MAX
UNIT
Bits
Resolution
14
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
fIN = 20 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
fIN = 300 MHz
72.8
72.5
72.2
71.7
69.4
72
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
Signal-to-noise ratio
SNR
SINAD
SFDR
THD
71.6
71.6
70.7
68.7
80
Signal-to-noise and
distortion ratio
79
dBc
Spurious-free dynamic
range
82
dBc
80
dBc
76
dBc
78
dBc
77
dBc
Total harmonic distortion
79
dBc
69
76
dBc
75
dBc
80
dBc
79
dBc
Second-harmonic
distortion
HD2
81
dBc
71
80
dBc
76
dBc
85
dBc
87
dBc
Third-harmonic distortion
HD3
96
dBc
71
80
dBc
84
dBc
92
dBc
95
dBc
Worst spur
94
dBc
(other than second and third harmonics)
77
88
dBc
85
dBc
f1 = 46 MHz, f2 = 50 MHz,
each tone at –7 dBFS
95
82
95
1
dBFS
dBFS
Two-tone intermodulation
distortion
IMD
f1 = 185 MHz, f2 = 190 MHz,
each tone at –7 dBFS
20-MHz full-scale signal on channel under observation;
170-MHz full-scale signal on other channel
Crosstalk
dB
Recovery to within 1%
(of full-scale) for 6 dB overload with sine-wave input
Input overload recovery
Clock cycle
dB
AC power-supply rejection
ratio
PSRR
For 50-mVPP signal on AVDD supply, up to 10 MHz
30
Effective number of bits
Differential nonlinearity
Integrated nonlinearity
ENOB
DNL
INL
fIN = 170 MHz
fIN = 170 MHz
fIN = 170 MHz
11.45
±0.5
±2
LSBs
LSBs
LSBs
–0.95
1.7
±4.5
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ELECTRICAL CHARACTERISTICS: GENERAL
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and –1 dBFS differential analog input,
unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V.
ADS4249
PARAMETER
MIN
TYP
MAX
UNIT
ANALOG INPUTS
Differential input voltage range
Differential input resistance (at 200 MHz)
2
0.75
3.7
VPP
kΩ
pF
Differential input capacitance (at 200 MHz)
Analog input bandwidth
(with 50-Ω source impedance, and 50-Ω termination)
550
MHz
Analog input common-mode current
(per input pin of each channel)
1.5
µA/MSPS
Common-mode output voltage
VCM output current capability
DC ACCURACY
VCM
0.95(1)
4
V
mA
Offset error
–15
–2
2.5
15
mV
Temperature coefficient of offset error
Gain error as a result of internal reference inaccuracy alone
Gain error of channel alone
Temperature coefficient of EGCHAN
POWER SUPPLY
0.003
mV/°C
%FS
EGREF
2
1
EGCHAN
±0.1
%FS
0.002
Δ%/°C
IAVDD
Analog supply current
167
144
190
160
mA
mA
IDRVDD
Output buffer supply current
LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
IDRVDD
Output buffer supply current
94
mA
CMOS interface, no load capacitance, fIN = 2.5 MHz(2)
Analog power
301
259
342
288
mW
mW
Digital power
LVDS interface, 350-mV swing with 100-Ω external termination, fIN = 2.5 MHz
Digital power
CMOS interface, 8-pF external load capacitance(2)
fIN = 2.5 MHz
169
mW
mW
Global power-down
25
(1) VCM changes to 0.87 V when serial register bits HIGH PERF MODE[7:2] are set.
(2) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the
supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).
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SBAS534C –JULY 2011–REVISED JULY 2012
DIGITAL CHARACTERISTICS
At AVDD = 1.8 V and DRVDD = 1.8 V, unless otherwise noted. DC specifications refer to the condition where the digital
outputs do not switch, but are permanently at a valid logic level '0' or '1'.
ADS4249
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1)
High-level input voltage
1.3
V
All digital inputs support 1.8-V
and 3.3-V CMOS logic levels
Low-level input voltage
0.4
V
SDATA, SCLK(2)
SEN(3)
VHIGH = 1.8 V
VHIGH = 1.8 V
VLOW = 0 V
10
0
µA
µA
µA
µA
High-level input current
SDATA, SCLK
SEN
0
Low-level input current
VLOW = 0 V
10
DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
0
V
V
Low-level output voltage
0.1
DIGITAL OUTPUTS, LVDS INTERFACE
High-level output
differential voltage
With an external
100-Ω termination
VODH
270
350
430
mV
Low-level output
differential voltage
With an external
100-Ω termination
VODL
VOCM
–430
0.9
–350
1.05
–270
1.25
mV
V
Output common-mode voltage
(1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode.
(2) SDATA, SCLK have internal 150-kΩ pull-down resistor.
(3) SEN has an internal 150-kΩ pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8 V or 3.3 V CMOS
buffers.
DAn_P
DBn_P
Logic 0
VODL = -350 mV(1)
Logic 1
VODH = +350 mV(1)
DAn_M
DBn_M
VOCM
GND
(1) With external 100-Ω termination.
Figure 1. LVDS Output Voltage Levels
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TIMING REQUIREMENTS: LVDS and CMOS Modes
Typical values are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 250 MSPS, sine wave input
clock, CLOAD = 5 pF, and RLOAD = 100 Ω, unless otherwise noted. Minimum and maximum values are across the
full temperature range: TMIN = –40°C to TMAX = +85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
Table 2. LVDS and CMOS Modes(1)
PARAMETER
DESCRIPTION
MIN
TYP
0.8
MAX
UNIT
ns
tA
Aperture delay
0.5
1.1
Aperture delay matching
Between the two channels of the same device
±70
ps
Between two devices at the same temperature and
DRVDD supply
Variation of aperture delay
Aperture jitter
±150
140
50
ps
fS rms
µs
tJ
Time to valid data after coming out of STANDBY
mode
100
500
Wakeup time
Time to valid data after coming out of GLOBAL
power-down mode
100
16
µs
Clock
cycles
Default latency after reset
ADC latency(2)
Clock
cycles
Digital functions enabled (EN DIGITAL = 1)
24
DDR LVDS MODE(3)
tSU Data setup time
Data valid(4) to zero-crossing of CLKOUTP
0.6
0.88
0.55
ns
ns
Zero-crossing of CLKOUTP to data becoming
invalid(4)
tH
Data hold time
0.33
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
LVDS bit clock duty cycle
5.0
6.0
48
7.5
ns
%
Duty cycle of differential clock, (CLKOUTP-
CLKOUTM)
Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
0.13
0.13
ns
ns
Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1 MSPS ≤ Sampling frequency ≤ 250 MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time,
Output clock fall time
PARALLEL CMOS MODE
Input clock rising edge cross-over to output clock
rising edge cross-over
tPDI
Clock propagation delay
4.5
6.2
50
8.5
ns
%
Duty cycle of output clock, CLKOUT
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
Output clock duty cycle
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
tRISE
tFALL
,
Data rise time,
Data fall time
0.7
0.7
ns
ns
Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1 MSPS ≤ Sampling frequency ≤ 200 MSPS
tCLKRISE
tCLKFALL
,
Output clock rise time
Output clock fall time
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.
(3) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold
time specifications take into account the effect of jitter on the output data and clock.
(4) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
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Table 3. LVDS Timings at Lower Sampling Frequencies
tPDI, CLOCK PROPAGATION
DELAY (ns)
SAMPLING
FREQUENCY
(MSPS)
SETUP TIME (ns)
HOLD TIME (ns)
MIN
5.9
4.5
2.3
1.5
1.3
1.1
0.76
TYP
6.6
5.2
2.9
2
MAX
MIN
0.35
0.35
0.35
0.33
0.33
0.33
0.33
TYP
0.6
MAX
MIN
5.0
5.0
5.0
5.0
5.0
5.0
5.0
TYP
6.0
6.0
6.0
6.0
6.0
6.0
6.0
MAX
7.5
7.5
7.5
7.5
7.5
7.5
7.5
65
80
0.6
125
160
185
200
230
0.6
0.55
0.55
0.55
0.55
1.6
1.4
1.06
Table 4. CMOS Timings at Lower Sampling Frequencies
TIMINGS SPECIFIED WITH RESPECT TO CLKOUT
SAMPLING
FREQUENCY
(MSPS)
tPDI, CLOCK PROPAGATION
DELAY (ns)
SETUP TIME(1) (ns)
HOLD TIME(1) (ns)
MIN
6.1
4.7
2.7
1.6
1.1
1
TYP
6.7
5.2
3.1
2.1
1.6
1.4
MAX
MIN
6.7
5.3
3.1
2.3
1.9
1.7
TYP
7.5
6
MAX
MIN
4.5
4.5
4.5
4.5
4.5
4.5
TYP
6.2
6.2
6.2
6.2
6.2
6.2
MAX
8.5
8.5
8.5
8.5
8.5
8.5
65
80
125
160
185
200
3.6
2.8
2.4
2.2
(1) In CMOS mode, setup time is measured from the beginning of data valid to 50% of the CLKOUT rising edge, whereas hold time is
measured from 50% of the CLKOUT rising edge to data becoming invalid. Data valid refers to a logic high of 1.26 V and a logic low of
0.54 V.
CLKM
Input
Clock
CLKP
tPDI
Output
CLKOUT
Clock
tSU
tH
DAn,
DBn
Output
Data
Dn(1)
(1) Dn = bits D0, D1, D2, etc. of channels A and B.
Figure 2. CMOS Interface Timing Diagram
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N + 4
N + 18
N + 3
N + 17
N + 2
N + 16
N + 1
Sample
N
Input
Signal
tA
CLKP
CLKM
Input
Clock
CLKOUTM
CLKOUTP
tPDI
tH
DDR
LVDS
tSU
16 Clock Cycles(1)
Output Data(2)
DAnP/M, DBnP/M
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
N - 16
N - 15
N - 14
N - 13
N - 12
N - 1
N
N + 1
tPDI
CLKOUT
tSU
Parallel
CMOS
tH
16 Clock Cycles(1)
N - 14
N - 13
Output Data
DAn, DBn
N - 16
N - 15
N - 1
N
N + 1
(1) ADC latency after reset. At higher sampling frequencies, tPDI is greater than one clock cycle, which then makes the overall latency = ADC
latency + 1.
(2) E = even bits (D0, D2, D4, etc.); O = odd bits (D1, D3, D5, etc.).
Figure 3. Latency Timing Diagram
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CLKOUTM
CLKOUTP
DA0, DB0
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA2, DB2
DA4, DB4
DA6, DB6
DA8, DB8
D6
D8
D7
D9
D6
D8
D7
D9
DA10, DB10
DA12, DB12
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
Figure 4. LVDS Interface Timing Diagram
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PIN CONFIGURATION: LVDS MODE
RGC PACKAGE(1)
QFN-64
(TOP VIEW)
DRVDD
DB4M
DB4P
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA6P
46 DA6M
45 DA4P
44 DA4M
43 DA2P
42 DA2M
41 DA0P
40 DA0M
39 NC
DB6M
DB6P
DB8M
DB8P
DB10M
DB10P
Thermal Pad
(Connected to DRGND)
DB12M 10
DB12P 11
RESET 12
SCLK 13
SDATA 14
SEN 15
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(1) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 5. LVDS Mode
Pin Descriptions: LVDS Mode
PIN NUMBER
PIN NAME
# OF PINS
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized
through a hardware RESET by applying a high pulse on this pin or by using the
software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK
and SEN are used as parallel control pins in this mode. This pin has an internal
150-kΩ pull-down resistor.
12
RESET
1
Input
This pin functions as a serial interface clock input when RESET is low. It controls
the low-speed mode selection when RESET is tied high; see Table 6 for detailed
information. This pin has an internal 150-kΩ pull-down resistor.
13
14
SCLK
1
1
Input
Input
SDATA
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. It
controls the output interface and data format selection when RESET is tied high;
see Table 7 for detailed information. This pin has an internal 150-kΩ pull-up
resistor to AVDD.
15
SEN
1
Input
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Pin Descriptions: LVDS Mode (continued)
PIN NUMBER
PIN NAME
# OF PINS
FUNCTION
DESCRIPTION
16, 22, 33, 34
AVDD
4
8
Input
Analog power supply
Analog ground
17, 18, 21, 24,
27, 28, 31, 32
AGND
Input
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
This pin outputs the common-mode voltage (0.95 V) that can be used externally
to bias the analog input pins
23
VCM
1
Output
25
26
CLKP
CLKM
1
1
1
1
1
1
1
2
1
1
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Differential clock positive input
Differential clock negative input
29
INP_A
Differential analog positive input, channel A
Differential analog negative input, channel A
Digital control input pins. Together, they control the various power-down modes.
Digital control input pins. Together, they control the various power-down modes.
Digital control input pins. Together, they control the various power-down modes.
Output buffer ground
30
INM_A
35
CTRL1
36
CTRL2
37
CTRL3
49, PAD
56
DRGND
CLKOUTM
CLKOUTP
Differential clock negative output
57
Differential clock positive output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
64
SDOUT
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
—
Refer to
Figure 5
DA0P, DA0M
DA2P, DA2M
DA4P, DA4M
DA6P, DA6M
DA8P, DA8M
DA10P, DA10M
DA12P, DA12M
DB0P, DB0M
DB2P, DB2M
DB4P, DB4M
DB6P, DB6M
DB8P, DB8M
DB10P, DB10M
DB12P, DB12M
NC
Channel A differential output data pair, D0 and D1 multiplexed
Channel A differential output data D2 and D3 multiplexed
Channel A differential output data D4 and D5 multiplexed
Channel A differential output data D6 and D7 multiplexed
Channel A differential output data D8 and D9 multiplexed
Channel A differential output data D10 and D11 multiplexed
Channel A differential output data D12 and D13 multiplexed
Channel B differential output data pair, D0 and D1 multiplexed
Channel B differential output data D2 and D3 multiplexed
Channel B differential output data D4 and D5 multiplexed
Channel B differential output data D6 and D7 multiplexed
Channel B differential output data D8 and D9 multiplexed
Channel B differential output data D10 and D11 multiplexed
Channel B differential output data D12 and D13 multiplexed
Do not connect, must be floated
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
Refer to
Figure 5
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PIN CONFIGURATION: CMOS MODE
RGC PACKAGE(2)
QFN-64
(TOP VIEW)
DRVDD
DB4
1
2
3
4
5
6
7
8
9
48 DRVDD
47 DA7
46 DA6
45 DA5
44 DA4
43 DA3
42 DA2
41 DA1
40 DA0
39 NC
DB5
DB6
DB7
DB8
DB9
DB10
DB11
Thermal Pad
(Connected to DRGND)
DB12 10
DB13 11
RESET 12
SCLK 13
SDATA 14
SEN 15
38 NC
37 CTRL3
36 CTRL2
35 CTRL1
34 AVDD
33 AVDD
AVDD 16
(2) The PowerPAD is connected to DRGND.
NOTE: NC = do not connect; must float.
Figure 6. CMOS Mode
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Pin Descriptions: CMOS Mode
# OF
PINS
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
1, 48
DRVDD
2
Input
Output buffer supply
Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a
hardware RESET by applying a high pulse on this pin or by using the software reset
option; refer to the Serial Interface Configuration section.
12
RESET
1
Input
In parallel interface mode, the RESET pin must be permanently tied high. SDATA and
SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pull-
down resistor.
This pin functions as a serial interface clock input when RESET is low. It controls the
low-speed mode when RESET is tied high; see Table 6 for detailed information. This pin
has an internal 150-kΩ pull-down resistor.
13
SCLK
SDATA
SEN
1
1
1
Input
Input
Input
14
15
Serial interface data input; this pin has an internal 150-kΩ pull-down resistor.
This pin functions as a serial interface enable input when RESET is low. It controls the
output interface and data format selection when RESET is tied high; see Table 7 for
detailed information. This pin has an internal 150-kΩ pull-up resistor to AVDD.
16, 22, 33, 34
AVDD
AGND
4
8
Input
Input
Analog power supply
Analog ground
17, 18, 21, 24, 27, 28,
31, 32
19
20
INP_B
INM_B
1
1
Input
Input
Differential analog positive input, channel B
Differential analog negative input, channel B
This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias
the analog input pins
23
VCM
1
Output
25
26
CLKP
CLKM
1
1
1
1
1
1
1
2
1
1
Input
Input
Input
Input
Input
Input
Input
Input
—
Differential clock positive input
Differential clock negative input
29
INP_A
Differential analog positive input, channel A
Differential analog negative input, channel A
Digital control input pins. Together, they control various power-down modes.
Digital control input pins. Together, they control various power-down modes.
Digital control input pins. Together, they control various power-down modes.
Output buffer ground
30
INM_A
CTRL1
CTRL2
CTRL3
DRGND
UNUSED
CLKOUT
35
36
37
49, PAD
56
This pin is not used in the CMOS interface
CMOS output clock
57
Output
This pin functions as a serial interface register readout when the READOUT bit is
enabled. When READOUT = 0, this pin is in high-impedance state.
64
SDOUT
1
Output
Refer to Figure 6
Refer to Figure 6
Refer to Figure 6
Refer to Figure 6
—
DA0 to DA11
DA12 to DA13
DB0 to DB11
DB12 to DB13
NC
12
2
Output
Output
Output
Output
—
Channel A ADC output data bits, CMOS levels
Channel A ADC output data bits, CMOS levels
Channel B ADC output data bits, CMOS levels
Channel B ADC output data bits, CMOS levels
Do not connect, must be floated
12
2
4
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FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD DRGND
LVDS Interface
DA0P
DA0M
DA2P
DA2M
DA4P
INP_A
INM_A
Digital and
DDR
Serializer
DA4M
DA6P
14-Bit
ADC
Sampling
Circuit
DA6M
DA8P
DA8M
DA10P
DA10M
DA12P
DA12M
CLKP
CLKM
CLKOUTP
CLKOUTM
Output
Clock Buffer
CLOCKGEN
DB0P
DB0M
DB2P
DB2M
DB4P
INP_B
INM_B
Digital and
DDR
Serializer
DB4M
DB6P
14-Bit
ADC
Sampling
Circuit
DB6M
DB8P
DB8M
DB10P
DB10M
DB12P
DB12M
Control
Interface
VCM
Reference
SDOUT
Device
Figure 7. Block Diagram
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DEVICE CONFIGURATION
The ADS4249 can be configured independently using either parallel interface control or serial interface
programming.
PARALLEL CONFIGURATION ONLY
To put the device into parallel configuration mode, keep RESET tied high (AVDD). Then, use the SEN, SCLK,
CTRL1, CTRL2, and CTRL3 pins to directly control certain modes of the ADC. The device can be easily
configured by connecting the parallel pins to the correct voltage levels (as described in Table 5 to Table 8).
There is no need to apply a reset and SDATA can be connected to ground.
In this mode, SEN and SCLK function as parallel interface control pins. Some frequently-used functions can be
controlled using these pins. Table 5 describes the modes controlled by the parallel pins.
Table 5. Parallel Pin Definition
PIN
CONTROL MODE
Low-speed mode selection
SCLK
SEN
Output data format and output interface selection
CTRL1
CTRL2
CTRL3
Together, these pins control the power-down modes
SERIAL INTERFACE CONFIGURATION ONLY
To enable this mode, the serial registers must first be reset to the default values and the RESET pin must be
kept low. SEN, SDATA, and SCLK function as serial interface pins in this mode and can be used to access the
internal registers of the ADC. The registers can be reset either by applying a pulse on the RESET pin or by
setting the RESET bit high. The Serial Register Map section describes the register programming and the register
reset process in more detail.
USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS
For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To enable this option, keep RESET low. The parallel interface control
pins CTRL1 to CTRL3 are available. After power-up, the device is automatically configured according to the
voltage settings on these pins (see Table 8). SEN, SDATA, and SCLK function as serial interface digital pins and
are used to access the internal registers of the ADC. The registers must first be reset to the default values either
by applying a pulse on the RESET pin or by setting the RESET bit to '1'. After reset, the RESET pin must be kept
low. The Serial Register Map section describes register programming and the register reset process in more
detail.
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PARALLEL CONFIGURATION DETAILS
The functions controlled by each parallel pin are described in Table 6, Table 7, and Table 8. A simple way of
configuring the parallel pins is shown in Figure 8.
Table 6. SCLK Control Pin
VOLTAGE APPLIED ON SCLK
DESCRIPTION
Low-speed mode is disabled
Low
High
Low-speed mode is enabled
Table 7. SEN Control Pin
VOLTAGE APPLIED ON SEN
DESCRIPTION
0
Twos complement and parallel CMOS output
Offset binary and parallel CMOS output
Offset binary and DDR LVDS output
(+50mV/0mV)
(3/8) AVDD
(±50mV)
(5/8) 2AVDD
(±50mV)
AVDD
(0mV/–50mV)
Twos complement and DDR LVDS output
Table 8. CTRL1, CTRL2, and CTRL3 Pins
CTRL1
Low
CTRL2
CTRL3
Low
DESCRIPTION
Low
Low
High
High
Low
Low
High
Normal operation
Not available
Low
High
Low
Low
Not available
Low
High
Low
Not available
High
High
High
Global power-down
High
Low
Channel A standby, channel B is active
Not available
MUX mode of operation, channel A and B data are
multiplexed and output on the DB[13:0] pins. See the
Multiplexed Mode of Operation section in the
Application Information for further details.
High
High
High
AVDD
(5/8) AVDD
3R
2R
3R
(5/8) AVDD
(3/8) AVDD
GND
AVDD
(3/8) AVDD
To Parallel Pin
Figure 8. Simple Scheme to Configure the Parallel Pins
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SERIAL INTERFACE DETAILS
The ADC has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial
interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serial shift of bits into the
device is enabled when SEN is low. Serial data SDATA are latched at every SCLK falling edge when SEN is
active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. When
the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-
bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight
bits are the register data. The interface can work with SCLK frequencies from 20 MHz down to very low speeds
(of a few hertz) and also with non-50% SCLK duty cycle.
Register Initialization
After power-up, the internal registers must be initialized to the default values. Initialization can be accomplished
in one of two ways:
1. Through a hardware reset by applying a high pulse on the RESET pin (of width greater than 10 ns), as
shown in Figure 9 and Table 9; or
2. By applying a software reset. When using the serial interface, set the RESET bit high. This setting initializes
the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET
pin is kept low. See Table 10 and Figure 10 for reset timing.
Register Address
Register Data
SDATA
SCLK
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
tDH
D1
D0
tSCLK
tDSU
tSLOADS
tSLOADH
SEN
RESET
Figure 9. Serial Interface Timing
Table 9. Serial Interface Timing Characteristics(1)
PARAMETER
SCLK frequency (equal to 1/tSCLK
SEN to SCLK setup time
SCLK to SEN hold time
SDATA setup time
MIN
> DC
25
TYP
MAX
UNIT
MHz
ns
fSCLK
tSLOADS
tSLOADH
tDSU
)
20
25
ns
25
ns
tDH
SDATA hold time
25
ns
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C,
AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.
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Power Supply
AVDD, DRVDD
t1
RESET
t2
t3
SEN
NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel
interface operation, RESET must be permanently tied high.
Figure 10. Reset Timing Diagram
Table 10. Reset Timing (Only when Serial Interface is Used)(1)
PARAMETER
CONDITIONS
MIN
TYP MAX UNIT
Delay from AVDD and DRVDD power-up to active RESET
pulse
1
ms
t1
Power-on delay
10
ns
t2
t3
Reset pulse width
Active RESET signal pulse width
1
µs
ns
Register write delay
Delay from RESET disable to SEN active
100
(1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless
otherwise noted.
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Serial Register Readout
The device includes a mode where the contents of the internal registers can be read back. This readback mode
may be useful as a diagnostic check to verify the serial interface communication between the external controller
and the ADC. To use readback mode, follow this procedure:
1. Set the READOUT register bit to '1'. This setting disables any further writes to the registers.
2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be
read.
3. The device outputs the contents (D7 to D0) of the selected register on the SDOUT pin (pin 64).
4. The external controller can latch the contents at the SCLK falling edge.
5. To enable register writes, reset the READOUT register bit to '0'.
The serial register readout works with both CMOS and LVDS interfaces on pin 64. See Figure 11 for serial
readout timing diagram.
When READOUT is disabled, the SDOUT pin is in high-impedance state.
Register Address A[7:0] = 00h
Register Data D[7:0] = 01h
SDATA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
SCLK
SEN
The SDOUT pin is in high-impedance state.
SDOUT
a) Enable serial readout (READOUT = 1)
Register Address A[7:0] = 45h
A4 A2
A5 A3
Register Data D[7:0] = XX (don’t care)
D4 D2 D1
D6 D5 D3
SDATA
SCLK
A7
A6
A1
A0
D7
D0
SEN
0
0
0
0
0
1
0
0
SDOUT
The SDOUT pin functions as serial readout (READOUT = 1).
b) Read contents of Register 45h. This register has been initialized with 04h (device is put into global power-down mode.)
Figure 11. Serial Readout Timing Diagram
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SERIAL REGISTER MAP
Table 11 summarizes the functions supported by the serial interface.
Table 11. Serial Interface Register Map(1)
REGISTER
ADDRESS
REGISTER DATA
D4 D3
A[7:0] (Hex)
D7
D6
D5
D2
D1
RESET
0
D0
READOUT
0
00
01
0
0
0
0
0
0
LVDS SWING
HIGH PERF
MODE 2
HIGH PERF
MODE 1
03
0
0
0
0
0
0
0
0
0
0
0
25
29
2B
CH A GAIN
CH B GAIN
CH A TEST PATTERNS
DATA FORMAT
0
0
0
0
CH B TEST PATTERNS
ENABLE
OFFSET
CORR
3D
0
0
0
0
0
0
0
0
3F
40
41
42
CUSTOM PATTERN D[13:8]
CUSTOM PATTERN D[7:0]
LVDS CMOS
CMOS CLKOUT STRENGTH
CLKOUT RISE POSN
0
0
0
DIS OBUF
0
CLKOUT FALL POSN
LVDS
EN DIGITAL
0
0
LVDS DATA
0
45
STBY
CLKOUT
STRENGTH
0
PDN GLOBAL
0
STRENGTH
HIGH FREQ
MODE CH B
4A
58
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HIGH FREQ
MODE CH A
BF
C1
CH A OFFSET PEDESTAL
CH B OFFSET PEDESTAL
0
0
0
0
FREEZE
OFFSET
CORR
CF
0
OFFSET CORR TIME CONSTANT
0
0
0
0
EN LOW
0
EF
F1
F2
0
0
0
0
0
0
0
0
0
0
0
0
SPEED MODE
0
0
0
EN LVDS SWING
LOW SPEED
MODE CH A
0
0
0
0
0
0
0
0
0
HIGH PERF
MODE3
2
0
0
0
0
0
0
0
0
0
0
0
HIGH PERF
MODE4
HIGH PERF
MODE5
D5
D7
DB
0
0
0
HIGH PERF
MODE6
HIGH PERF
MODE7
0
0
HIGH PERF
MODE8
LOW SPEED
MODE CH B
0
0
(1) Multiple functions in a register can be programmed in a single write operation. All registers default to '0' after reset.
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DESCRIPTION OF SERIAL REGISTERS
Register Address 00h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
RESET
READOUT
Bits[7:2]
Bit 1
Always write '0'
RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
READOUT: Serial readout
Bit 0
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the SDOUT pin is placed in a high-impedance state.
1 = Serial readout enabled; the SDOUT pin functions as a serial data readout with CMOS logic
levels running from the DRVDD supply. See the Serial Register Readout section.
Register Address 01h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS SWING
Bits[7:2]
LVDS SWING: LVDS swing programmability
These bits program the LVDS swing. Set the EN LVDS SWING bit to '1' before programming
swing.
000000 = Default LVDS swing; ±350 mV with external 100-Ω termination
011011 = LVDS swing ±410 mV
110010 = LVDS swing ±465 mV
010100 = LVDS swing ±570 mV
111110 = LVDS swing ±200 mV
001111 = LVDS swing ±125 mV
Bits[1:0]
Always write '0'
Register Address 03h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
HIGH PERF
MODE 2
HIGH PERF
MODE 1
0
0
Bits[7:2]
Bits[1:0]
Always write '0'
HIGH PERF MODE[2:1]: High-performance mode
00 = Default performance
01 = Do not use
10 = Do not use
11 = Obtain best performance across sample clock and input signal frequencies
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Register Address 25h (Default = 00h)
7
6
5
4
3
2
1
0
CH A GAIN
0
CH A TEST PATTERNS
Bits[7:4]
CH A GAIN: Channel A gain programmability
These bits set the gain programmability in 0.5-dB steps for channel A.
0000 = 0-dB gain (default after reset)
0001 = 0.5-dB gain
0010 = 1-dB gain
0011 = 1.5-dB gain
0100 = 2-dB gain
0101 = 2.5-dB gain
0110 = 3-dB gain
0111 = 3.5-dB gain
1000 = 4-dB gain
1001 = 4.5-dB gain
1010 = 5-dB gain
1011 = 5.5-dB gain
1100 = 6-dB gain
Bit 3
Always write '0'
Bits[2:0]
CH A TEST PATTERNS: Channel A data capture
These bits verify data capture for channel A.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
Register Address 29h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
DATA FORMAT
Bits[7:5]
Bits[4:3]
Always write '0'
DATA FORMAT: Data format selection
00 = Twos complement
01 = Twos complement
10 = Twos complement
11 = Offset binary
Bits[2:0]
Always write '0'
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Register Address 2Bh (Default = 00h)
7
6
5
4
3
2
1
0
CH B GAIN
0
CH B TEST PATTERNS
Bits[7:4]
CH B GAIN: Channel B gain programmability
These bits set the gain programmability in 0.5-dB steps for channel B.
0000 = 0-dB gain (default after reset)
0001 = 0.5-dB gain
0010 = 1-dB gain
0011 = 1.5-dB gain
0100 = 2-dB gain
0101 = 2.5-dB gain
0110 = 3-dB gain
0111 = 3.5-dB gain
1000 = 4-dB gain
1001 = 4.5-dB gain
1010 = 5-dB gain
1011 = 5.5-dB gain
1100 = 6-dB gain
Bit 3
Always write '0'
Bits[2:0]
CH B TEST PATTERNS: Channel B data capture
These bits verify data capture for channel B.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern.
The output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101.
100 = Outputs digital ramp.
101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern
110 = Unused
111 = Unused
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Register Address 3Dh (Default = 00h)
7
0
6
0
5
4
3
2
0
1
0
0
0
ENABLE OFFSET CORR
0
0
Bits[7:6]
Bit 5
Always write '0'
ENABLE OFFSET CORR: Offset correction setting
This bit enables the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits[4:0]
Always write '0'
Register Address 3Fh (Default = 00h)
7
0
6
0
5
4
3
2
1
0
CUSTOM
PATTERN D13
CUSTOM
PATTERN D12
CUSTOM
PATTERN D11
CUSTOM
PATTERN D10
CUSTOM
PATTERN D9
CUSTOM
PATTERN D8
Bits[7:6]
Bits[5:0]
Always write '0'
CUSTOM PATTERN D[13:8]
These are the six upper bits of the custom pattern available at the output instead of ADC data.
The ADS4249 custom pattern is 14-bit.
Register Address 40h (Default = 00h)
7
6
5
4
3
2
1
0
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
CUSTOM
PATTERN D7
PATTERN D6
PATTERN D5
PATTERN D4
PATTERN D3
PATTERN D2
PATTERN D1
PATTERN D0
Bits[7:0]
CUSTOM PATTERN D[7:0]
These are the eight lower bits of the custom pattern available at the output instead of ADC data.
The ADS4249 custom pattern is 14-bit; use the CUSTOM PATTERN D[13:0] register bits.
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Register Address 41h (Default = 00h)
7
6
5
4
3
2
0
1
0
LVDS CMOS
CMOS CLKOUT STRENGTH
0
DIS OBUF
Bits[7:6]
LVDS CMOS: Interface selection
These bits select the interface.
00 = DDR LVDS interface
01 = DDR LVDS interface
10 = DDR LVDS interface
11 = Parallel CMOS interface
Bits[5:4]
CMOS CLKOUT STRENGTH
These bits control the strength of the CMOS output clock.
00 = Maximum strength (recommended)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bits[3:2]
Bits[1:0]
Always write '0'
DIS OBUF
These bits power down data and clock output buffers for both the CMOS and LVDS output
interface. When powered down, the output buffers are in 3-state.
00 = Default
01 = Power-down data output buffers for channel B
10 = Power-down data output buffers for channel A
11 = Power-down data output buffers for both channels as well as the clock output buffer
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Register Address 42h (Default = 00h)
7
6
5
4
3
2
0
1
0
0
0
CLKOUT FALL POSN
CLKOUT RISE POSN
EN DIGITAL
Bits[7:6]
CLKOUT FALL POSN
In LVDS mode:
00 = Default
01 = The falling edge of the output clock advances by 450 ps
10 = The falling edge of the output clock advances by 150 ps
11 = The falling edge of the output clock is delayed by 550 ps
In CMOS mode:
00 = Default
01 = The falling edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The falling edge of the output clock advances by 100 ps
Bits[5:6]
CLKOUT RISE POSN
In LVDS mode:
00 = Default
01 = The rising edge of the output clock advances by 450 ps
10 = The rising edge of the output clock advances by 150 ps
11 = The rising edge of the output clock is delayed by 250 ps
In CMOS mode:
00 = Default
01 = The rising edge of the output clock is delayed by 150 ps
10 = Do not use
11 = The rising edge of the output clock advances by 100 ps
Bit 3
EN DIGITAL: Digital function enable
0 = All digital functions disabled
1 = All digital functions (such as test patterns, gain, and offset correction) enabled
Bits[2:0]
Always write '0'
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Register Address 45h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
LVDS CLKOUT
STRENGTH
LVDS DATA
STRENGTH
STBY
0
0
PDN GLOBAL
Bit 7
Bit 6
Bit 5
STBY: Standby setting
0 = Normal operation
1 = Both channels are put in standby; wakeup time from this mode is fast (typically 50 µs).
LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting
0 = LVDS output clock buffer at default strength to be used with 100-Ω external termination
1 = LVDS output clock buffer has double strength to be used with 50-Ω external termination
LVDS DATA STRENGTH
0 = All LVDS data buffers at default strength to be used with 100-Ω external termination
1 = All LVDS data buffers have double strength to be used with 50-Ω external termination
Bits[4:3]
Bit 2
Always write '0'
PDN GLOBAL
0 = Normal operation
1 = Total power down; all ADC channels, internal references, and output buffers are powered
down. Wakeup time from this mode is slow (typically 100 µs).
Bits[1:0]
Always write '0'
Register Address 4Ah (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
HIGH FREQ MODE CH B
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH B: High-frequency mode for channel B
0 = Default
1 = Use this mode for high input frequencies greater than 200 MHz
Register Address 58h (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
0
0
HIGH FREQ MODE CH A
Bits[7:1]
Bit 0
Always write '0'
HIGH FREQ MODE CH A: High-frequency mode for channel A
0 = Default
1 = Use this mode for high input frequencies greater than 200 MHz
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Register Address BFh (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CH A OFFSET PEDESTAL
Bits[7:4]
CH A OFFSET PEDESTAL: Channel A offset pedestal selection
When the offset correction is enabled, the final converged value after the offset is corrected is the
ADC midcode value. A pedestal can be added to the final converged value by programming these
bits. See the Offset Correction section. Channels can be independently programmed for different
offset pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits[3:0]
Always write '0'
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Register Address C1h (Default = 00h)
7
6
5
4
3
2
1
0
0
0
CH B OFFSET PEDESTAL
Bits[7:4]
CH B OFFSET PEDESTAL: Channel B offset pedestal selection
When offset correction is enabled, the final converged value after the offset is corrected is the ADC
midcode value. A pedestal can be added to the final converged value by programming these bits;
see the Offset Correction section. Channels can be independently programmed for different offset
pedestals by choosing the relevant register address.
The pedestal ranges from –32 to +31, so the output code can vary from midcode-32 to
midcode+31 by adding pedestal D7-D2.
Program Bits D[7:2]
011111 = Midcode+31
011110 = Midcode+30
011101 = Midcode+29
…
000010 = Midcode+2
000001 = Midcode+1
000000 = Midcode
111111 = Midcode-1
111110 = Midcode-2
…
100000 = Midcode-32
Bits[3:0]
Always write '0'
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Register Address CFh (Default = 00h)
7
6
0
5
4
3
2
1
0
0
0
FREEZE OFFSET CORR
OFFSET CORR TIME CONSTANT
Bit 7
FREEZE OFFSET CORR: Freeze offset correction setting
This bit sets the freeze offset correction estimation.
0 = Estimation of offset correction is not frozen (the EN OFFSET CORR bit must be set)
1 = Estimation of offset correction is frozen (the EN OFFSET CORR bit must be set); when frozen,
the last estimated value is used for offset correction of every clock cycle. See the Offset Correction
section.
Bit 6
Always write '0'
Bits[5:2]
OFFSET CORR TIME CONSTANT
The offset correction loop time constant in number of clock cycles. Refer to the Offset Correction
section.
Bits[1:0]
Always write '0'
Register Address EFh (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
EN LOW SPEED MODE
0
Bits[7:5]
Bit 4
Always write '0'
EN LOW SPEED MODE: Enable control of low-speed mode through serial register bits
This bit enables the control of the low-speed mode using the LOW SPEED MODE CH B and LOW
SPEED MODE CH A register bits.
0 = Low-speed mode is disabled
1 = Low-speed mode is controlled by serial register bits
Bits[3:0]
Always write '0'
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Register Address F1h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
EN LVDS SWING
Bits[7:2]
Bits[1:0]
Always write '0'
EN LVDS SWING: LVDS swing enable
These bits enable LVDS swing control using the LVDS SWING register bits.
00 = LVDS swing control using the LVDS SWING register bits is disabled
01 = Do not use
10 = Do not use
11 = LVDS swing control using the LVDS SWING register bits is enabled
Register Address F2h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
LOW SPEED MODE CH A
Bits[7:4]
Bit 3
Always write '0'
LOW SPEED MODE CH A: Channel A low-speed mode enable
This bit enables the low-speed mode for channel A. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel A
1 = Low-speed mode is enabled for channel A
Bits[2:0]
Always write '0'
Register Address 2h (Default = 00h)
7
0
6
5
0
4
3
2
0
1
0
0
HIGH PERF
MODE3
0
0
0
Bit 7
Bit 6
Always write '0'
HIGH PERF MODE3
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[5:0]
Always write '0'
Register Address D5h (Default = 00h)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
HIGH PERF
MODE4
HIGH PERF
MODE5
Bits[7:5]
Bit 4
Always write '0'
HIGH PERF MODE4
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bit 3
HIGH PERF MODE5
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[2:0]
Always write '0'
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Register Address D7h (Default = 00h)
7
0
6
0
5
0
4
3
2
1
0
0
0
HIGH PERF
MODE6
HIGH PERF
MODE7
0
Bits[7:4]
Bit 3
Always write '0'
HIGH PERF MODE6
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bit 2
HIGH PERF MODE7
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS)
Bits[1:0]
Always write '0'
Register Address DBh (Default = 00h)
7
0
6
0
5
4
3
2
1
0
0
HIGH PERF
MODE8
0
0
0
LOW SPEED MODE CH B
Bits[7:6]
Bit 5
Always write '0'
HIGH PERF MODE8
HIGH PERF MODE3 to HIGH PERF MODE8 must be set to '1' to ensure best performance at high
sampling speed (greater than 160 MSPS).
Bits[4:1]
Bit 0
Always write '0'
LOW SPEED MODE CH B: Channel B low-speed mode enable
This bit enables the low-speed mode for channel B. Set the EN LOW SPEED MODE bit to '1'
before using this bit.
0 = Low-speed mode is disabled for channel B
1 = Low-speed mode is enabled for channel B
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TYPICAL CHARACTERISTICS: ADS4249
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
INPUT SIGNAL (10 MHz)
INPUT SIGNAL (150 MHz)
0
−20
0
−20
SFDR = 85.3 dBc
SFDR = 80.2 dBc
SNR = 73 dBFS
SINAD = 72.6 dBFS
THD = 81.9 dBc
SNR = 71.7 dBFS
SINAD = 71 dBFS
THD = 78.8 dBc
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
Figure 12.
Figure 13.
INPUT SIGNAL (300 MHz)
TWO-TONE INPUT SIGNAL
0
−20
0
−20
SFDR = 77.9 dBc
SNR = 69.5 dBFS
SINAD = 69 dBFS
THD = 77.2 dBc
Each Tone at
−7 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
Two−Tone IMD = 81 dBFS
SFDR = 93.8 dBFS
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0
25
50
75
100
125
0
25
50
75
100
125
Frequency (MHz)
Frequency (MHz)
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
TWO-TONE INPUT SIGNAL
SFDR vs INPUT FREQUENCY
0
86
84
82
80
78
76
74
72
70
Each Tone at
−36 dBFS Amplitude
fIN1 = 185.1 MHz
fIN2 = 190.1 MHz
Two−Tone IMD = 105 dBFS
SFDR = 104.2 dBFS
−20
−40
−60
−80
−100
−120
0
25
50
75
100
125
0
50
100
150
200
250
300
350
400
Frequency (MHz)
Input Frequency (MHz)
Figure 16.
Figure 17.
SNR vs INPUT FREQUENCY
SFDR vs GAIN AND INPUT FREQUENCY
74
73
72
71
70
69
68
67
66
65
64
88
86
84
82
80
78
76
74
72
70
70 MHz
150 MHz
220 MHz
400 MHz
0
50
100
150
200
250
300
350
400
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Input Frequency (MHz)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
SINAD vs GAIN AND INPUT FREQUENCY
PERFORMANCE vs INPUT AMPLITUDE
110
100
90
75.5
75
73
72
71
70
69
68
67
66
65
64
63
Input Frequency = 40 MHz
74.5
74
80
70
73.5
73
60
50
72.5
72
SFDR (dBc)
SFDR (dBFS)
SNR
40
70 MHz
150 MHz
220 MHz
400 MHz
30
−50
71.5
−40
−30
−20
−10
0
Amplitude (dBFS)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Digital Gain (dB)
Figure 20.
Figure 21.
PERFORMANCE vs INPUT AMPLITUDE
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
110
100
90
80
70
60
50
40
30
20
74.5
83
73.5
Input Frequency = 150 MHz
Input Frequency = 40 MHz
74
82
81
80
79
78
77
73
73.5
73
72.5
72
72.5
72
71.5
71
71.5
71
SFDR (dBc)
SFDR (dBFS)
SNR
70.5
70
SFDR
SNR
70.5
−50
−40
−30
−20
−10
0
0.8
0.85
0.9
0.95
1
Amplitude (dBFS)
Input CommonMode Voltage (V)
Figure 22.
Figure 23.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT COMMON-MODE VOLTAGE
SFDR vs TEMPERATURE AND AVDD SUPPLY
84
73
89
87
85
83
81
79
77
75
73
71
Input Frequency = 150 MHz
Input Frequency = 40 MHz
83
82
81
80
79
78
77
76
72.5
72
71.5
71
70.5
70
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
69.5
69
SFDR
SNR
0.8
0.85
0.9
0.95
1
Input CommonMode Voltage (V)
−40
−15
10
35
60
85
Temperature (°C)
Figure 24.
Figure 25.
SNR vs TEMPERATURE AND AVDD SUPPLY
PERFORMANCE vs DRVDD SUPPLY VOLTAGE
82
81
80
79
78
77
76
72.5
74
73.5
73
Input Frequency = 150 MHz
Input Frequency = 40 MHz
72
71.5
71
72.5
72
70.5
70
AVDD = 1.7 V
AVDD = 1.75 V
AVDD = 1.8 V
AVDD = 1.85 V
AVDD = 1.9 V
AVDD = 1.95 V
AVDD = 2 V
71.5
71
SFDR
SNR
69.5
1.7
1.75
1.8
1.85
1.9
1.95
2
DRVDD Supply (V)
−40
−15
10
35
60
85
Temperature (°C)
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
PERFORMANCE vs INPUT CLOCK AMPLITUDE
PERFORMANCE vs INPUT CLOCK AMPLITUDE
90
88
86
84
82
80
78
76
74
74
83
82
81
80
79
78
77
76
75
72
Input Frequency = 40 MHz
Input Frequency = 150 MHz
73.5
71.5
73
71
72.5
72
70.5
70
71.5
71
69.5
69
70.5
68.5
SFDR
SNR
SFDR
SNR
70
2.2
68
2.2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Differential Clock Amplitude (VPP
)
Differential Clock Amplitudes (VPP)
Figure 28.
Figure 29.
PERFORMANCE vs INPUT CLOCK DUTY CYCLE
CMRR vs TEST SIGNAL FREQUENCY
82
80
78
76
74
72
70
68
66
64
62
76
0
Input Frequency = 10 MHz
Input Frequency = 40 MHz
50 mVPP Signal Superimposed on VCM
−5
75.5
75
−10
−15
−20
−25
−30
−35
−40
−45
−50
−55
−60
74.5
74
73.5
73
72.5
72
71.5
SNR
THD
71
25
30
35
40
45
50
55
60
65
70
75
Input Clock Duty Cycle (%)
0
50
100
150
200
250
300
Frequency of Input Common−Mode Signal (MHz)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
CMRR SPECTRUM
PSRR vs TEST SIGNAL FREQUENCY
0
0
−5
fIN = 40 MHz
Input Frequency = 10 MHz
50 mVPP Signal Superimposed on AVDD Supply
fIN = 40 MHz
fCM = 10 MHz, 50 mVPP
SFDR = 81.7 dBc
Amplitude (fIN) = -1 dBFS
-20
−10
−15
−20
−25
−30
−35
−40
−45
−50
Amplitude (fCM) = -108.2 dBFS
Amplitude (fIN + fCM) = -93.5 dBFS
Amplitude (fIN - fCM) = 93.9 dBFS
-40
-60
fIN - fCM = 30 MHz
fCM = 10 MHz
fIN + fCM = 50 MHz
-80
-100
-120
0
50
100
150
200
250
300
0
25
50
75
100
125
Frequency of Signal on Supply (MHz)
Frequency (MHz)
Figure 32.
Figure 33.
ZOOMED VIEW of PSRR SPECTRUM
ANALOG POWER vs SAMPLING FREQUENCY
0
350
310
270
230
190
150
110
70
fIN = 10 MHz
fPSRR = 2 MHz, 50 mVPP
AVDD = 1.8 V
Input Frequency = 2.5 MHz
fIN
Amplitude (fIN) = -1 dBFS
Amplitude (fPSRR) = -95.1 dBFS
-20
-40
Amplitude (fIN + fPSRR) = -96.4 dBFS
Amplitude (fIN - fPSRR) = -96.8 dBFS
-60
fIN + fPSRR
fPSRR
fIN - fPSRR
-80
-100
-120
0
25
50
75 100 125 150 175 200 225 250
Sampling Speed (MSPS)
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
Figure 34.
Figure 35.
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TYPICAL CHARACTERISTICS: ADS4249 (continued)
At TA = +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode enabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
DIGITAL POWER LVDS CMOS
DIGITAL POWER IN VARIOUS MODES
260
240
220
200
180
160
140
120
100
80
320
300
280
260
240
220
200
180
160
140
120
100
80
Fin = 2.5 MHz
Default
EN Digital = 1
EN Digital = 1, Offset Correction Enabled
60
40
LVDS, 350mV Swing
LVDS, 200mV Swing
CMOS
20
0
0
25
50
75 100 125 150 175 200 225 250
Sampling Speed (MSPS)
0
25
50
75 100 125 150 175 200 225 250
Sampling Speed (MSPS)
G001
G001
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS: Contour
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
SPURIOUS-FREE DYNAMIC RANGE (0-dB Gain)
250
240
82
220
82
82
82
79
200
180
160
140
120
100
75
82
79
82
85
75
82
85
79
88
71
88
82
82
85
79
88
75
80
60
85
91
0
50
100
150
200
Input Frequency (MHz)
250
300
350
400
72
74
76
78
80
82
84
86
88
90
70
SFDR (dBc)
Figure 38.
SPURIOUS-FREE DYNAMIC RANGE (6-dB Gain)
250
240
82
79
82
85
76
79
76
85
220
200
180
160
140
120
100
82
85
79
82
85
85
85
82
79
87
87
89
87
80
60
79
85
82
91
89
0
50
100
150
200
250
84
300
350
400
Input Frequency (MHz)
82
74
76
78
80
86
88
90
SFDR (dBc)
Figure 39.
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TYPICAL CHARACTERISTICS: Contour (continued)
All graphs are at +25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock. 1.5 VPP
differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, High-Performance Mode disabled, 0-dB
gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
SIGNAL-TO-NOISE RATIO (0-dB Gain)
250
71
240
71.5
69
220
200
180
160
140
120
100
70
72
72.5
71.5
71
68
72
69
72.5
70
71.5
73
71
71.5
71
150
72.5
72
80
60
73.5
70
69
73
50
68
0
100
200
Input Frequency (MHz)
70 71
250
300
350
400
68
69
72
73
SNR (dBFS)
Figure 40.
SIGNAL-TO-NOISE RATIO (6-dB Gain)
250
240
66.5
65.2
66.5
66.8
65.7
220
200
180
160
140
120
100
67.1
66.2
65.2
66.5
64.7
66.8
64.2
64.7
65.2
66.2
65.7
66.5
66.8
67.1
67.4
67.1
66.8
80
60
65.7
65.2
66.2
250
66.5
0
50
100
150
200
Input Frequency (MHz)
65.5 66
300
350
67
400
64
64.5
65
66.5
SNR (dBFS)
Figure 41.
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APPLICATION INFORMATION
THEORY OF OPERATION
The ADS4249 belongs to TI's ultralow-power family of dual-channel, 12-/14-bit analog-to-digital converters
(ADCs). At every rising edge of the input clock, the analog input signal of each channel is simultaneously
sampled. The sampled signal in each channel is converted by a pipeline of low-resolution stages. In each stage,
the sampled/held signal is converted by a high-speed, low-resolution, flash sub-ADC. The difference between the
stage input and the quantized equivalent is gained and propagates to the next stage. At every clock, each
succeeding stage resolves the sampled input with greater accuracy. The digital outputs from all stages are
combined in a digital correction logic block and digitally processed to create the final code after a data latency of
16 clock cycles. The digital output is available as either DDR LVDS or parallel CMOS and coded in either straight
offset binary or binary twos complement format. The dynamic offset of the first stage sub-ADC limits the
maximum analog input frequency to approximately 400 MHz (with 2-VPP amplitude) or approximately 600 MHz
(with 1-VPP amplitude).
ANALOG INPUT
The analog input consists of a switched-capacitor-based, differential sample-and-hold (S/H) architecture. This
differential topology results in very good ac performance even for high input frequencies at high sampling rates.
The INP and INM pins must be externally biased around a common-mode voltage of 0.95 V, available on the
VCM pin. For a full-scale differential input, each input pin (INP and INM) must swing symmetrically between
VCM + 0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The input sampling circuit has a high
3-dB bandwidth that extends up to 550 MHz (measured from the input pins to the sampled voltage). Figure 42
shows an equivalent circuit for the analog input.
Sampling
Switch
LPKG
Sampling
Capacitor
2 nH
10 W
RCR Filter
INP
RON
CBOND
1 pF
CPAR2
1 pF
CSAMP
2 pF
100 W
15 W
RESR
3 pF
200 W
CPAR1
0.5 pF
RON
10 W
3 pF
LPKG
2 nH
CSAMP
2 pF
100 W
RON
10 W
15 W
INM
CBOND
1 pF
CPAR2
1 pF
Sampling
Capacitor
RESR
Sampling
Switch
200 W
Figure 42. Analog Input Equivalent Circuit
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Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This operation improves the common-
mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each input pin is
recommended to damp out ringing caused by package parasitics.
SFDR performance can be limited as a result of several reasons, including the effects of sampling glitches;
nonlinearity of the sampling circuit; and nonlinearity of the quantizer that follows the sampling circuit. Depending
on the input frequency, sample rate, and input amplitude, one of these factors generally plays a dominant part in
limiting performance. At very high input frequencies (greater than approximately 300 MHz), SFDR is determined
largely by the device sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually
limits performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, glitches could limit performance, primarily at low
input frequencies (up to approximately 200 MHz). It is also necessary to present low impedance (less than 50 Ω)
for the common-mode switching currents. This configuration can be achieved by using two resistors from each
input terminated to the common-mode voltage (VCM pin).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but it reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches must then be
supplied by the external drive circuit. This tradeoff has limitations as a result of the presence of the package
bond-wire inductance.
In the ADS4249, the R-C component values have been optimized while supporting high input bandwidth (up to
550 MHz). However, in applications with input frequencies up to 200 MHz to 300 MHz, the filtering of the glitches
can be improved further using an external R-C-R filter; see Figure 45 and Figure 46.
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. Furthermore, the ADC input impedance must be considered.
Figure 43 and Figure 44 show the impedance (ZIN = RIN || CIN) looking into the ADC input pins.
100
5
4.5
4
10
3.5
3
1
2.5
2
0.1
0.01
1.5
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Input Frequency (GHz)
1
Figure 43. ADC Analog Input Resistance (RIN)
Across Frequency
Figure 44. ADC Analog Input Capacitance (CIN)
Across Frequency
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Driving Circuit
Three example driving circuit configurations are shown in Figure 45, Figure 46, and Figure 47. They are
optimized for low bandwidth (low input frequencies), high bandwidth (higher input frequencies), and very high
bandwidth (very high input frequencies), respectively. Note that three of the drive circuits have been terminated
by 50 Ω near the ADC side. The termination is accomplished by a 25-Ω resistor from each input to the 0.95-V
common-mode (VCM) from the device. This architecture allows the analog inputs to be biased around the
required common-mode voltage.
The mismatch in the transformer parasitic capacitance (between the windings) results in degraded even-order
harmonic performance. Connecting two identical RF transformers back-to-back helps minimize this mismatch;
good performance is obtained for high-frequency input signals. For example, ADT1-1WT transformers can be
used for the first two configurations (Figure 45 and Figure 46) while ADTL2-18 transformers can be used for the
third configuration (Figure 47). An optional termination resistor pair may be required between the two
transformers, as shown in Figure 45, Figure 46, and Figure 47. The center point of this termination is connected
to ground to improve the balance between the P and M sides. The values of the terminations between the
transformers and on the secondary side must be chosen to obtain an effective 50 Ω (in the case of 50-Ω source
impedance).
0.1 mF
5 W
INx_P
T1
T2
0.1 mF
25 W
25 W
25 W
0.1 mF
3.3 pF
25 W
RIN
CIN
INx_M
VCM
1:1
1:1
5 W
0.1 mF
Device
Figure 45. Drive Circuit with Low Bandwidth (for Low Input Frequencies Less Than 150 MHz)
0.1 mF
5 W
INx_P
T1
T2
0.1 mF
25 W
25 W
50 W
0.1 mF
3.3 pF
50 W
RIN
CIN
INx_M
VCM
1:1
1:1
5 W
0.1 mF
Device
Figure 46. Drive Circuit with High Bandwidth (for High Input Frequencies Greater Than 150 MHz and
Less Than 270 MHz)
0.1 mF
5 W
INx_P
T1
T2
0.1 mF
25 W
25 W
0.1 mF
RIN
CIN
INx_M
VCM
1:1
1:1
5 W
0.1 mF
Device
Figure 47. Drive Circuit with Very High Bandwidth (Greater than 270 MHz)
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All of these examples show 1:1 transformers being used with a 50-Ω source. As explained in the Drive Circuit
Requirements section, this configuration helps to present a low source impedance to absorb the sampling
glitches. With a 1:4 transformer, the source impedance is 200 Ω. The higher source impedance is unable to
absorb the sampling glitches effectively and can lead to degradation in performance (compared to using 1:1
transformers).
In almost all cases, either a band-pass or low-pass filter is required to obtain the desired dynamic performance,
as shown in Figure 48. Such filters present low source impedance at the high frequencies corresponding to the
sampling glitch and help avoid performance losses associated with the high source impedance.
5 W
INx_P
T1
100 W
Band-Pass
or
0.1 mF
0.1 mF
Differential
Input Signal
RIN
CIN
Low-Pass
Filter
100 W
INx_M
VCM
1:4
5 W
Device
Figure 48. Drive Circuit with a 1:4 Transformer
CLOCK INPUT
The ADS4249 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with
little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM
using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock
or ac-coupling for LVPECL and LVDS clock sources are shown in Figure 49, Figure 50 and Figure 51. The
internal clock buffer is shown in Figure 52.
(1) RT = termination resister, if necessary.
0.1 mF
0.1 mF
Zo
CLKP
CLKM
CLKP
Differential
Sine-Wave
Clock Input
RT
Typical LVDS
Clock Input
100 W
0.1 mF
Device
0.1 mF
Zo
CLKM
Device
Figure 49. Differential Sine-Wave Clock Driving
Circuit
Figure 50. LVDS Clock Driving Circuit
0.1 mF
Zo
CLKP
150 W
Typical LVPECL
Clock Input
100 W
0.1 mF
Zo
CLKM
Device
150 W
Figure 51. LVPECL Clock Driving Circuit
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Clock Buffer
LPKG
2 nH
20 W
CLKP
CBOND
CEQ
CEQ
5 kW
1 pF
RESR
2 pF
100 W
VCM
LPKG
2 nH
5 kW
20 W
CLKM
CBOND
1 pF
RESR
100 W
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 52. Internal Clock Buffer
A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF
capacitor, as shown in Figure 53. For best performance, the clock inputs must be driven differentially, thereby
reducing susceptibility to common-mode noise. For high input frequency sampling, it is recommended to use a
clock source with very low jitter. Band-pass filtering of the clock source can help reduce the effects of jitter. There
is no change in performance with a non-50% duty cycle clock input.
0.1 mF
CMOS
Clock Input
CLKP
VCM
0.1 mF
CLKM
Device
Figure 53. Single-Ended Clock Driving Circuit
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DIGITAL FUNCTIONS
The device has several useful digital functions (such as test patterns, gain, and offset correction). These
functions require extra clock cycles for operation and increase the overall latency and power of the device. These
digital functions are disabled by default after reset and the raw ADC output is routed to the output data pins with
a latency of 16 clock cycles. Figure 54 shows more details of the processing after the ADC. In order to use any
of the digital functions, the EN DIGITAL bit must be set to '1'. After this, the respective register bits must be
programmed as described in the following sections and in the Serial Register Map section.
Output
Interface
14-Bit
14-Bit
ADC
Digital Functions
(Gain, Offset Correction, Test Patterns)
DDR LVDS
or CMOS
EN DIGITAL Bit
Figure 54. Digital Processing Block
GAIN FOR SFDR/SNR TRADE-OFF
The ADS4249 includes gain settings that can be used to get improved SFDR performance (compared to no
gain). The gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-
scale range scales proportionally, as shown in Table 12.
The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades
approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result,
the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal
degradation in SNR. Therefore, the gain can be used as a trade-off between SFDR and SNR. Note that the
default gain after reset is 0 dB.
Table 12. Full-Scale Range Across Gains
GAIN (dB)
TYPE
FULL-SCALE (VPP)
0
1
2
3
4
5
6
Default after reset
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
2
1.78
1.59
1.42
1.26
1.12
1
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OFFSET CORRECTION
The ADS4249 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10 mV. The
correction can be enabled using the ENABLE OFFSET CORR serial register bit. Once enabled, the algorithm
estimates the channel offset and applies the correction every clock cycle. The time constant of the correction
loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR
TIME CONSTANT register bits, as described in Table 13.
After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 0. Once frozen,
the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is
disabled by default after reset.
Table 13. Time Constant of Offset Correction Algorithm
TIME CONSTANT, TCCLK
(Number of Clock Cycles)
OFFSET CORR TIME CONSTANT
TIME CONSTANT, TCCLK × 1/fS (ms)(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1 M
2 M
4
8
4 M
16
8 M
32
16 M
64
32 M
128
256
512
1024
2048
4096
8192
—
64 M
128 M
256 M
512 M
1 G
2 G
Reserved
Reserved
Reserved
Reserved
—
—
—
(1) Sampling frequency, fS = 250 MSPS.
POWER-DOWN
The ADS4249 has two power-down modes: global power-down and channel standby. These modes can be set
using either the serial register bits or using the control pins CTRL1 to CTRL3 (as shown in Table 14).
Table 14. Power-Down Settings
CTRL1
Low
CTRL2
Low
CTRL3
Low
DESCRIPTION
Default
Low
Low
High
Low
Not available
Not available
Not available
Global power-down
Low
High
High
Low
Low
High
Low
High
High
High
Low
High
Low
Channel A powered down, channel B is active
Not available
High
MUX mode of operation, channel A and B data is
multiplexed and output on DB[13:0] pins
High
High
High
50
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Global Power-Down
In this mode, the entire chip (including ADCs, internal reference, and output buffers) are powered down, resulting
in reduced total power dissipation of approximately 20 mW when the CTRL pins are used and 3mW when the
PDN GLOBAL serial register bit is used. The output buffers are in high-impedance state. The wake-up time from
global power-down to data becoming valid in normal mode is typically 100 µs.
Channel Standby
In this mode, each ADC channel can be powered down. The internal references are active, resulting in a quick
wake-up time of 50 µs. The total power dissipation in standby is approximately 240 mW at 250 MSPS.
Input Clock Stop
In addition to the previous modes, the converter enters a low-power mode when the input clock frequency falls
below 1 MSPS. The power dissipation is approximately 160 mW.
DIGITAL OUTPUT INFORMATION
The ADS4249 provides 14-bit digital data for each channel and an output clock synchronized with the data.
Output Interface
Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit or by setting the proper voltage on the SEN pin in parallel
configuration mode.
DDR LVDS Outputs
In this mode, the data bits and clock are output using low-voltage differential signal (LVDS) levels. Two data bits
are multiplexed and output on each LVDS differential pair, as shown in Figure 55.
Pins
CLKOUTP
Output
Clock
CLKOUTM
DB0_P
Data Bits
D0, D1
DB0_M
DB2_P
Data Bits
D2, D3
DB2_M
DB4_P
Data Bits
D4, D5
14-Bit ADC Data,
Channel B
DB4_M
DB6_P
DB6_M
Data Bits
D6, D7
DB8_P
DB8_M
Data Bits
D8, D9
DB10_P
DB10_M
Data Bits
D10, D11
DB12_P
DB12_M
Data Bits
D12, D13
Figure 55. LVDS Interface
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Even data bits (D0, D2, D4, etc.) are output at the CLKOUTP rising edge and the odd data bits (D1, D3, D5, etc.)
are output at the CLKOUTP falling edge. Both the CLKOUTP rising and falling edges must be used to capture all
the data bits, as shown in Figure 56.
CLKOUTM
CLKOUTP
DA0, DB0
DA2, DB2
DA4, DB4
D0
D2
D4
D1
D3
D5
D0
D2
D4
D1
D3
D5
DA6, DB6
DA8, DB8
D6
D8
D7
D9
D6
D8
D7
D9
DA10, DB10
DA12, DB12
D10
D12
D11
D13
D10
D12
D11
D13
Sample N
Sample N + 1
Figure 56. DDR LVDS Interface Timing
LVDS Buffer
The equivalent circuit of each LVDS output buffer is shown in Figure 57. After reset, the buffer presents an
output impedance of 100Ω to match with the external 100-Ω termination.
VDIFF
High
Low
OUTP
OUTM
External
100-W Load
VOCM
ROUT
VDIFF
High
Low
NOTE: Default swing across 100-Ω load is ±350 mV. Use the LVDS SWING bits to change the swing.
Figure 57. LVDS Buffer Equivalent Circuit
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The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination.
The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.
Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination, as
shown in Figure 58. This mode can be used when the output LVDS signal is routed to two separate receiver
chips, each using a 100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS
CLKOUT STRENGTH register bits for data and output clock buffers, respectively.
The buffer output impedance behaves in the same way as a source-side series termination. By absorbing
reflections from the receiver end, it helps to improve signal integrity.
Receiver Chip # 1
(for example, GC5330)
DAnP/M
CLKIN1 100 W
CLKOUTP
CLKOUTM
CLKIN2 100 W
DBnP/M
Receiver Chip # 2
Device
Make LVDS CLKOUT STRENGTH = 1
Figure 58. LVDS Buffer Differential Termination
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Parallel CMOS Interface
In the CMOS mode, each data bit is output on separate pins as CMOS voltage level, every clock cycle, as
Figure 59 shows. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. It is
recommended to minimize the load capacitance of the data and clock output pins by using short traces to the
receiver. Furthermore, match the output data and clock traces to minimize the skew between them.
DB0
DB1
14-Bit ADC Data,
Channel B
DB12
DB13
SDOUT
CLKOUT
DA0
DA1
14-Bit ADC Data,
Channel A
DA12
DA13
Figure 59. CMOS Outputs
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CMOS Interface Power Dissipation
With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every
output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock
cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined
by the average number of output bits switching, which is a function of the sampling frequency and the nature of
the analog input signal. This relationship is shown by the formula:
Digital current as a result of CMOS output switching = CL × DRVDD × (N × FAVG),
where CL = load capacitance, N × FAVG = average number of output bits switching.
Multiplexed Mode of Operation
In this mode, the digital outputs of both channels are multiplexed and output on a single bus (DB[11:0] pins), as
shown in Figure 60. The channel A output pins (DA[11:0]) are in 3-state. Because the output data rate on the DB
bus is effectively doubled, this mode is recommended only for low sampling frequencies (less than 80 MSPS).
This mode can be enabled using the POWER-DOWN MODE register bits or using the CTRL[3:1] parallel pins.
CLKM
Input
Clock
CLKP
tPDI
Output
CLKOUT
Clock
tSU
tH
Channel A
DAn(2)
Channel B
DBn(2)
Channel A
DAn(2)
Output
Data
DBn(1)
(1) In multiplexed mode, both channels outputs come on the channel B output pins.
(2) Dn = bits D0, D1, D2, etc.
Figure 60. Multiplexed Mode Timing Diagram
Output Data Format
Two output data formats are supported: twos complement and offset binary. The format can be selected using
the DATA FORMAT serial interface register bit or by controlling the DFS pin in parallel configuration mode.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 3FFFh for the ADS4249 in offset binary output format; the output code is 1FFFh for
the ADS4249 in twos complement output format. For a negative input overdrive, the output code is 0000h in
offset binary output format and 2000h for the ADS4249 in twos complement output format.
DEFINITION OF SPECIFICATIONS
Analog Bandwidth – The analog input frequency at which the power of the fundamental is reduced by 3 dB with
respect to the low-frequency value.
Aperture Delay – The delay in time between the rising edge of the input sampling clock and the actual time at
which the sampling occurs. This delay is different across channels. The maximum variation is specified as
aperture delay variation (channel-to-channel).
Aperture Uncertainty (Jitter) – The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle – The duty cycle of a clock signal is the ratio of the time the clock signal remains
at a logic high (clock pulse width) to the period of the clock signal. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock results in a 50% duty cycle.
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Maximum Conversion Rate – The maximum sampling rate at which specified operation is given. All parametric
testing is performed at this sampling rate unless otherwise noted.
Minimum Conversion Rate – The minimum sampling rate at which the ADC functions.
Differential Nonlinearity (DNL) – An ideal ADC exhibits code transitions at analog input values spaced exactly
1LSB apart. The DNL is the deviation of any single step from this ideal value, measured in units of LSBs.
Integral Nonlinearity (INL) – The INL is the deviation of the ADC transfer function from a best fit line determined
by a least squares curve fit of that transfer function, measured in units of LSBs.
Gain Error – Gain error is the deviation of the ADC actual input full-scale range from its ideal value. The gain
error is given as a percentage of the ideal input full-scale range. Gain error has two components: error as a
result of reference inaccuracy (EGREF) and error as a result of the channel (EGCHAN). Both errors are specified
independently as EGREF and EGCHAN
To a first-order approximation, the total gain error is ETOTAL ~ EGREF + EGCHAN
For example, if ETOTAL = ±0.5%, the full-scale input varies from (1 – 0.5/100) x FSideal to (1 + 0.5/100) x FSideal
.
.
.
Offset Error – The offset error is the difference, given in number of LSBs, between the ADC actual average idle
channel output code and the ideal average idle channel output code. This quantity is often mapped into millivolts.
Temperature Drift – The temperature drift coefficient (with respect to gain error and offset error) specifies the
change per degree Celsius of the parameter from TMIN to TMAX. It is calculated by dividing the maximum deviation
of the parameter across the TMIN to TMAX range by the difference TMAX – TMIN
.
Signal-to-Noise Ratio – SNR is the ratio of the power of the fundamental (PS) to the noise floor power (PN),
excluding the power at dc and the first nine harmonics.
PS
SNR = 10Log10
PN
(1)
SNR is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
Signal-to-Noise and Distortion (SINAD) – SINAD is the ratio of the power of the fundamental (PS) to the power
of all the other spectral components including noise (PN) and distortion (PD), but excluding dc.
PS
SINAD = 10Log10
PN + PD
(2)
SINAD is either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of the fundamental is extrapolated to the converter full-
scale range.
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Effective Number of Bits (ENOB) – ENOB is a measure of the converter performance as compared to the
theoretical limit based on quantization noise.
SINAD - 1.76
ENOB =
6.02
(3)
Total Harmonic Distortion (THD) – THD is the ratio of the power of the fundamental (PS) to the power of the
first nine harmonics (PD).
PS
THD = 10Log10
PN
(4)
THD is typically given in units of dBc (dB to carrier).
Spurious-Free Dynamic Range (SFDR) – The ratio of the power of the fundamental to the highest other
spectral component (either spur or harmonic). SFDR is typically given in units of dBc (dB to carrier).
Two-Tone Intermodulation Distortion – IMD3 is the ratio of the power of the fundamental (at frequencies f1
and f2) to the power of the worst spectral component at either frequency 2f1 – f2 or 2f2 – f1. IMD3 is either given
in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB
to full-scale) when the power of the fundamental is extrapolated to the converter full-scale range.
DC Power-Supply Rejection Ratio (DC PSRR) – DC PSSR is the ratio of the change in offset error to a change
in analog supply voltage. The dc PSRR is typically given in units of mV/V.
AC Power-Supply Rejection Ratio (AC PSRR) – AC PSRR is the measure of rejection of variations in the
supply voltage by the ADC. If ΔVSUP is the change in supply voltage and ΔVOUT is the resultant change of the
ADC output code (referred to the input), then:
DVOUT
PSRR = 20Log10
(Expressed in dBc)
DVSUP
(5)
Voltage Overload Recovery – The number of clock cycles taken to recover to less than 1% error after an
overload on the analog inputs. This is tested by separately applying a sine wave signal with 6 dB positive and
negative overload. The deviation of the first few samples after the overload (from the expected values) is noted.
Common-Mode Rejection Ratio (CMRR) – CMRR is the measure of rejection of variation in the analog input
common-mode by the ADC. If ΔVCM_IN is the change in the common-mode voltage of the input pins and ΔVOUT is
the resulting change of the ADC output code (referred to the input), then:
DVOUT
10
CMRR = 20Log
(Expressed in dBc)
DVCM
(6)
Crosstalk (only for multi-channel ADCs) – This is a measure of the internal coupling of a signal from an
adjacent channel into the channel of interest. It is specified separately for coupling from the immediate
neighboring channel (near-channel) and for coupling from channel across the package (far-channel). It is usually
measured by applying a full-scale signal in the adjacent channel. Crosstalk is the ratio of the power of the
coupling signal (as measured at the output of the channel of interest) to the power of the signal applied at the
adjacent channel input. It is typically expressed in dBc.
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BOARD DESIGN CONSIDERATIONS
Grounding
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A single ground plane is sufficient to give good performance, provided the analog, digital, and clock sections of
the board are cleanly partitioned. See the ADS4226 Evaluation Module (SLAU333) for details on layout and
grounding.
Supply Decoupling
Because the ADS4249 already includes internal decoupling, minimal external decoupling can be used without
loss in performance. Note that decoupling capacitors can help filter external power-supply noise; thus, the
optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed
very close to the converter supply pins.
Exposed Pad
In addition to providing a path for heat dissipation, the PowerPAD is also electrically connected internally to the
digital ground. Therefore, it is necessary to solder the exposed pad to the ground plane for best thermal and
electrical performance. For detailed information, see application notes QFN Layout Guidelines (SLOA122) and
QFN/SON PCB Attachment (SLUA271).
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Routing Analog Inputs
It is advisable to route differential analog input pairs (INP_x and INM_x) close to each other. To minimize the
possibility of coupling from a channel analog input to the sampling clock, the analog input pairs of both channels
should be routed perpendicular to the sampling clock; see the ADS4226 Evaluation Module (SLAU333) for
reference routing. Figure 61 shows a snapshot of the PCB layout from the ADS42xxEVM.
ADS42xx
Channel B
Channel A
Clock
Figure 61. ADS42xxEVM PCB Layout
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REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (September 2011) to Revision C
Page
•
•
•
•
•
•
Changed footnote 1 in Table 4 ............................................................................................................................................. 9
Changed register D5h bit names of bits D7, D4, D3, and D0 in Table 11 ......................................................................... 22
Changed register address D8 to DB in Table 11 ................................................................................................................ 22
Changed register address D5h to match change in Table 11 ............................................................................................ 33
Changed register address DB to match change in Table 11 .............................................................................................. 34
Changed conditions for ADS4249 Typical Characteristics section ..................................................................................... 35
Changes from Revision A (September 2011) to Revision B
Page
•
•
Changed document status to Production Data ..................................................................................................................... 1
Changed AC power-supply rejection ratio parameter test condition in ADS4249 Electrical Characteristics table ............... 5
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PACKAGE OPTION ADDENDUM
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9-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ADS4249IRGC25
ADS4249IRGCR
ADS4249IRGCT
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
VQFN
RGC
RGC
RGC
64
64
64
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS4249IRGCR
ADS4249IRGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
330.0
330.0
16.4
16.4
9.3
9.3
9.3
9.3
1.5
1.5
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ADS4249IRGCR
ADS4249IRGCT
VQFN
VQFN
RGC
RGC
64
64
2000
250
336.6
336.6
336.6
336.6
28.6
28.6
Pack Materials-Page 2
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