ADS5203_15 [TI]

Dual 10-Bit 40MPS Low-power ANALOG-TO-DIGITAL CONVERTER;


型号：	ADS5203_15
厂家：	TEXAS INSTRUMENTS
描述：	Dual 10-Bit 40MPS Low-power ANALOG-TO-DIGITAL CONVERTER
文件：	总18页 (文件大小：888K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Not Recommended For New Designs

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SBAS258A – JUNE 2002 – REVISED JULY 2002

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FEATURES

DESCRIPTION

3.3V Single-Supply Operation

The ADS5203 is a dual 10-bit, 40MSPS Analog-to-Digi-

tal Converter (ADC). It simultaneously converts each

analog input signal into a 10-bit, binary coded digital

word up to a maximum sampling rate of 40MSPS per

channel. All digital inputs and outputs are 3.3V

TTL/CMOS compatible.

Dual Simultaneous Sample-and-Hold Inputs

Differential or Single-Ended Analog Inputs

Single or Dual Parallel Bus Output

60dB SNR at f = 10.5MHz

73dB SFDR at f = 10.5MHz

Low Power: 240mW

An innovative dual-pipeline architecture implemented in

a CMOS process and the 3.3V supply results in very low

power dissipation. In order to provide maximum flexibil-

ity, both top and bottom voltage references can be set

from user-supplied voltages. Alternatively, if no external

references are available, the on-chip internal refer-

ences can be used. Both ADCs share a common refer-

ence to improve offset and gain matching. If external

reference voltage levels are available, the internal refer-

ences can be powered down independently from the

rest of the chip, resulting in even greater power savings.

300MHz Analog Input Bandwidth

3.3V TTL/CMOS-Compatible Digital I/O

Internal or External Reference

Adjustable Reference Input Range

Power-Down (Standby) Mode

TQFP-48 Package

APPLICATIONS

Digital Communications (Baseband Sampling)

Video Processing

Portable Instrumentation

Ultrasound

The ADS5203 is characterized for operation from

–40°C to +85°C and is available in a TQFP-48 package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Not Recommended For New Designs

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SBAS258A – JUNE 2002 – REVISED JULY 2002

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE–LEAD

(1)

ADS5203

TQFP–48

PFB

–40°C to +85°C

AZ5203

ADS5203IPFB

Tray, 250

ADS5203IPFBR

Tape and Reel, 1000

(1)

For the most current specifications and package information, refer to our web site at www.ti.com.

This integrated circuit can be damaged by

ESD. Texas Instruments recommends that

all integrated circuits be handled with

appropriate precautions. Failure to observe proper

handling and installation procedures can cause

damage.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

Supply Voltage: AV

to AGND, DV to DGND . . . . . . . . . . –0.5V to 3.6V

to DV , AGND to DGND . . . . . . . . . . –0.5V to 0.5V

Digital Input Voltage Range to DGND . . . . . . . . . . . . –0.5V to DV

Analog Input Voltage Range to AGND . . . . . . . . . . . . . –0.5V to AV

+ 0.5V

Digital Output Voltage Applied from Ext. Source to DGND . . . . . . . –0.5V to DV

+ 0.5V

ESD damage can range from subtle performance

degradation to complete device failure. Precision

integrated circuits may be more susceptible to damage

because very small parametric changes could cause

the device not to meet its published specifications.

Reference Voltage Input Range to AGND: V . . . . . . –0.5V to AV

, V

REFT REFB

Operating Free-Air Temperature Range, T (ADS5203I) . . . –40°C to +85°C

Storage Temperature Range, T

STG

. . . . . . . . . . . . . . . . . . –65°C to +150°C

Soldering Temperature 1.6mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . 300°C

(1)

Stresses above these ratings may cause permanent damage. Exposure to

absolute maximum conditions for extended periods may degrade device

reliability. These are stress ratings only, and functional operation of the device

at these or any other conditions beyond those specified is not implied.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, T , unless otherwise noted.

PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

Power Supply

3.0

3.3

3.6

Supply Voltage

DRV

Analog and Reference Inputs

Reference Input Voltage (top)

Reference Input Voltage (bottom)

Reference Voltage Differential

Reference Input Resistance

Reference Input Current

= 1MHz to 80MHz

1.9

2.0

1.0

2.15

1.1

REFT

CLK

0.95

REFB

– V

1.0

1.1

REFT

REFB

CLK

= 80MHz

1650

0.62

Ω

REF

CLK

REF

Analog Input Voltage, Differential

Analog Input Voltage, Single–Ended

Analog Input Capacitance

–1

(1)

CML – 1.0

CML + 1.0

(2)

Clock Input

Analog Outputs

CML Voltage

AV /2

CML Output Resistance

Digital Inputs

2.3

kΩ

High-Level Input Voltage

Low-Level Input Voltage

Input Capacitance

Clock Period

2.4

DGND

0.8

t (80MHz)

12.5

5.25

Pulse Duration

Clock Period

(80MHz)

w(CLKH), w(CLKL)

t (40MHz)

Clock HIGH or LOW

Pulse Duration

(40MHz)

11.25

w(CLKH) , w(CLKL)

(1)

(2)

Applies only when the signal reference input connects to CML.

Clock pin is referenced to AV /AV

DD SS

Not Recommended For New Designs

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ELECTRICAL CHARACTERISTICS

over recommended operating conditions with f

= 80MHz and use of internal voltage references, unless otherwise noted.

CLK

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

1.7

2.2

= DV

= DRV = 3.3V,

Operating Supply Current

C = 10pF, f = 3.5MHz, –1dBFS

DRV

PWDN_REF = ‘L’

PWDN_REF = ‘H’

240

220

290

240

150

Power Dissipation

Standby Power

STDBY = ‘H’, CLK Held HIGH or LOW

µW

µs

D(STBY)

Power-Up Time for All References from Standby

Wake Up Time

550

External Reference

Digital Inputs

High-Level Input Current on Digital Inputs incl. CLK

Low-Level Input Current on Digital Inputs incl. CLK

Digital Outputs

–1

µA

= DV

= DRV = 3.6V

= DV

= DRV = 3.0V at

High-Level Output Voltage

Low-Level Output Voltage

2.8

2.96

= 50µA, Digital Outputs Forced HIGH

= DV

= DRV = 3.0V at

= 50µA, Digital Outputs Forced LOW

0.04

0.2

Output Capacitance

µA

High-Impedance State Output Current to High-Level

High-Impedance State Output Current to Low-Level

–1

OZH

= DV

= DRV = 3.6V

OZL

LOAD

= 10pF, Single–Bus Mode

= 10pF, Dual–Bus Mode

Data Output Rise-and-Fall Time

LOAD

Reference Outputs

Reference Top Voltage

1.9

0.95

2.1

1.05

REFTO

REFBO

Absolute Min/Max Values Valid and

Tested for AV = 3.3V

Reference Bottom Voltage

Differential Reference Votage

DC Accuracy

REFT – REFB

1.0

Internal

References

Integral Nonlinearity, End Point

INL

= –40°C to +85°C

T = –40°C to +85°C

–1.5

–0.9

±0.4

±0.5

+1.5

LSB

(1)

Internal

References

Differential Nonlinearity

Missing Codes

DNL

(2)

No Missing Codes Assured

(3)

Zero Error

0.12

0.28

0.24

±1.5

%FS

= DV

= DRV

= 3.3V

(3)

Full–Scale Error

External References

Gain Error

(1)

Integralnonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs ½LSB

before the first code transition. The full-scale point is defined as a level ½LSB beyond the last code transition. The deviation is measured from

the center of each particular code to the best-fit line between these two endpoints.

(2)

An ideal ADC exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Therefore, this measure indicates

how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under test, (i.e., (last transition

level – first transition level)/(2 – 2)). Using this definition for DNL separates the effects of gain and offset error. A minimum DNL better than

–1LSB ensures no missing codes.

(3)

Zero error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC output

from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to ½LSB to the bottom reference level. The

voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).

Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that will switch the ADC

output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5LSB from the top

reference level. The voltage corresponding to 1LSB is found from the difference of top and bottom references divided by the number of ADC

output levels (1024).

Not Recommended For New Designs

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(1)

DYNAMIC PERFORMANCE

T = T

MIN

to T

, AV

= DV

= DRV

= 3.3V, f = –1dBFS, Internal Reference, f = 80MHz, f = 40MSPS, and Differential Input Range =2Vp–p,

IN CLK S

MAX

unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

9.7

MAX

UNIT

Bits

Effective Number of Bits

ENOB

THD

= 3.5MHz

= 10.5MHz

9.3

9.7

= 20MHz

= 3.5MHz

= 10.5MHz

9.6

Total Harmonic Distortion

Signal-to-Noise Ratio

–71

–68

60.5

–66

= 20MHz

= 3.5MHz

= 10.5MHz

SNR

= 20MHz

= 3.5MHz

= 10.5MHz

Signal-to-Noise Ratio + Distortion

Spurious-Free Dynamic Range

SINAD

SFDR

= 20MHz

= 3.5MHz

= 10.5MHz

= 20MHz

70.5

300

–68

–75

0.016

See Note (2)

f1 = 9.5MHz, f2 = 9.9MHz

Analog Input Bandwidth

MHz

dBc

2-Tone Intermodulation Distortion

A/B Channel Crosstalk

IMD

A/B Channel Offset Mismatch

1.75 % FS

1.0 % FS

A/B Channel Full-Scale Error Mismatch

(1)

These specifications refer to a 25Ω series resistor and 15pF differential capacitor between A/B+ and A/B– inputs; any source impedance will

bring the bandwidth down.

(2)

Analog input bandwidth is defined as the frequency at which the sampled input signal is 3dB down on unity gain and is limited by the input switch

impedance.

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PIN CONFIGURATION

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1,13

DRV

Supply Voltage for Output Drivers

Digital Ground for Output Drivers

DRV

12, 24

14-23

DA 9..0

Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus

or data from the A channel only. Pins SELB and MODE select the output mode. The data outputs are in tri-state during

power-down (refer to Timing Options table).

DB 9..0

Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B-channel when dual bus output mode

is selected. The data outputs are in tri-state during power-down and single-bus modes (refer to Timing Options table).

2-11

Output Enable. A LOW on this terminal will enable the data output bus, C

OUT

and C .

OUT

Latch Clock for the Data Outputs. C

OUT

is in tri-state during power-down.

OUT

Inverted Latch Clock or multiplexer control for the Data Outputs. C

OUT

is in tri-state during power–down.

OUT

SELB

Selects either single-bus data output or dual-bus data output. A LOW selects dual-bus data output.

Digital Ground

CLK

Clock Input. The input is sampled on each rising edge of CLK when using a 40MHz input and alternate rising edges when

using an 80MHz input. The clock pin is referenced to AV

and AV to reduce noise coupling from digital logic.

Digital Supply Voltage

27,37,41

Analog Supply Voltage

MODE

Selects the C

OUT

and C output mode.

OUT

Analog Ground

28,36,40

B–

Negative Input for the Analog B Channel

Positive Input for the Analog B Channel

B+

REFT

Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering

I/O

should be applied to this input: the use of 0.1µF capacitor between REFT and AV

is recommended. Additionally a 0.1µF

capacitor should be connected between REFT and REFB.

REFB

CML

Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient

I/O

filtering should be applied to this input: the use of 0.1µF capacitor between REFB and AV

a 0.1µF capacitor should be connected between REFT and REFB.

is recommended. Additionally

Common-Mode Level. This voltage is equal to (AV

– AV )/2. An external capacitor of 0.1µF should be connected

between this terminal and AV

when CML is used as a bias voltage. No capacitor is required if CML is not used.

PDWN_REF

Power-Down for Internal Reference Voltages. A HIGH on this terminal disables the internal reference circuit.

Standby Input. A HIGH on this terminal will power down the device.

Negative Input for the Analog A Channel

STBY

A–

A+

Positive Input for Analog A Channel

This pin must be connected to DV . It should not be left floating.

Not Recommended For New Designs

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TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input Clock Rate

MHz

CLK

Conversion Rate

MSPS

Clock Duty Cycle (40MHz)

Clock Duty Cycle (80MHz)

Output Delay Time

= 10pF

d(o)

s(m)

h(m)

Mux Setup Time

1.7

10.4

2.1

10.4

2.2

Mux Hold Time

= 10pF

Output Setup Time

s(o)

Output Hold Time

1.5

h(o)

MODE = 0, SELB = 0

MODE = 1, SELB = 0

MODE = 0, SELB = 1

MODE = 1, SELB = 1

Pipeline Delay (latency, channels A and B)

Pipeline Delay (latency, channel A)

Pipeline Delay (latency, channel B)

Pipeline Delay (latency, channel A)

Pipeline Delay (latency, channel B)

Aperture Delay Time

CLK Cycles

d(pipe)

d(a)

Aperture Jitter

1.5

ps, rms

J(a)

Disable Time, OE Rising to Hi–Z

Enable Time, OE Falling to Valid Data

dis

TIMING OPTIONS

OPERATING MODE

MODE

SELB

TIMING DIAGRAM FIGURE

80MHz Input Clock, Dual-Bus Output, C

= 40MHz

OUT

40MHz Input Clock, Dual-Bus Output, C

80MHz Input Clock, Single-Bus Output, C

= 40MHz

= 80MHz

OUT

80MHz Input Clock, Single-Bus Output, C

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TIMING DIAGRAMS

Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

ADC

OUT

t_d(pipe)

(3)

B[9:0]

ADC

t_d(o)

DA[9:0]

DB[9:0]

t_d(o)

DAB[19:0] is used to illustrate the placement of the busses DA and DB

DAB[19:0]

A&B 1

t_s(o)

A&B 2

t_h(o)

A&B 3

A&B 4

A&B 5

OUT

NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.

Figure 1. Dual Bus Output—Option 1.

Sample A1 and B1

Analog_A

Analog_B

(1)

(2)

CLK

t_d(pipe)

ADC

A[9:0]

OUT

t_d(pipe)

(2)

B[9:0]

OUT

t_d(o)

DA[9:0]

DB[9:0]

t_d(o)

DAB[19:0] is used to illustrate the combined busses DA and DB

DAB[19:0]

A&B 1

t_s(o)

A&B 2

t_h(o)

A&B 3

A&B 4

A&B 5

OUT

NOTE: (1) In this option CLK = 40MHz, per channel. (2) Internal signal only

Figure 2. Dual Bus Output—Option 2.

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TIMING DIAGRAMS (Cont.)

Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

OUT

ADC

t_d(pipe)

(3)

B[9:0]

t_d(o)

ADC

OUT

t_d(o)

DA[9:0]

A1 B1 A2 B2 A3 B3 A4 B4 A5 B5

t_h(o)

t_s(o)

OUT

t_h(o)

t_s(o)

NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.

Figure 3. Single Bus Output—Option 1.

Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

ADC

OUT

t_d(pipe)

(3)

B[9:0]

OUT

t_d(o)

DA[9:0]

A1 B1 A2 B2 A3 B3 A4 B4

t_h(o)

t_s(o)

OUT

t_s(m)

t_h(m)

OUT

NOTES: (1) In this option CLK = 80MHz. (2) CLK40INT refers to 40MHz Internal Clock, per channel. (3) Internal signal only.

Figure 4. Single Bus Output—Option 2.

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TYPICAL CHARACTERISTICS

At T = 25°C, AV

= DV

= DRV

= 3.3V, f = –0.5dBFS, Internal Reference, f = 80MHz, f = 40MSPS, Differential Input Range = 2Vp-p,

IN CLK S

25Ω series resistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.

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Typical Characteristics (Cont.)

At T = 25°C, AV

= DV

= DRV

= 3.3V, f = –0.5dBFS, Internal Reference, f = 80MHz, f = 40MSPS, Differential Input Range = 2Vp-p,

IN CLK S

25Ω series resistor, and 15pF differential capacitor at A/B+ and A/B– inputs, unless otherwise noted.

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The analog input signal is sampled on capacitors C

PRINCIPLE OF OPERATION

and C

while the internal device clock is low. The

The ADS5203 implements a dual high-speed, 10-bit,

40MSPS converter in a cost-effective CMOS process.

The differential inputs on each channel are sampled

simultaneously. Signal inputs are differential and the

clock signal is single-ended. The clock signal is either

80MHz or 40MHz, depending on the device

configuration set by the user. Powered from 3.3V, the

dual-pipeline design architecture ensures low-power

operation and 10-bit resolution. The digital inputs are

3.3V TTL/CMOS compatible. Internal voltage

references are included for both bottom and top

voltages. Alternatively, the user may apply externally

generated reference voltages. In doing so, the input

range can be modified to suit the application.

sampled voltage is transferred to capacitors C

and

and held on these while the internal device clock

is high. The SHA can sample both single-ended and

differential input signals.

The load presented to the AIN pin consists of the

switched input sampling capacitor C (approximately

2pF) and its various stray capacitances. A simplified

equivalent circuit for the switched capacitor input is

shown in Figure 6. The switched capacitor circuit is

modeled as a resistor R . f

is the clock frequency,

IN CLK

which is 40MHz at full speed, and C is the sampling

capacitor. Using 25Ω series resistors and a differential

15pF capacitor at the A/B+ and A/B– inputs is

recommended to reduce noise.

The ADC is a 5-stage pipelined ADC with 4 stages of

fully-differential switched capacitor sub-ADC/MDAC

pairs and a single sub-ADC in stage 5. All stages deliver

2 bits of the final conversion result. A digital error

correction is used to compensate for modest

comparator offsets in the sub-ADCs.

NOTE: AIN can be any variation

of A or B inputs.

= 40MHz

CLK

SAMPLE-AND-HOLD AMPLIFIER

Figure 5 shows the internal SHA architecture. The

circuit is balanced and fully differential for good supply

noise rejection. The sampling circuit has been kept as

simple as possible to obtain good performance for

high-frequency input signals.

= 0.5 S (V(A/B+) + V(A/B–))

Figure 6. Equivalent Circuit for the Switched

Capacitor Input.

ANALOG INPUT, DIFFERENTIAL

CONNECTION

The analog input of the ADS5203 is a differential

architecture that can be configured in various ways

depending on the signal source and the required level

of performance. A fully differential connection will

deliver the best performance from the converter. The

analog inputs must not go below AV or above AV

The inputs can be biased with any common-mode

voltage provided that the minimum and maximum input

voltages stay within the range AV

to AV . It is

recommended to bias the inputs with a common-mode

voltage around AV /2. This can be accomplished

easily with the output voltage source CML, which is

equal to AV /2. CML is made available to the user to

help simplify circuit design. This output voltage source

is not designed to be a reference or to be loaded but

makes an excellent DC bias source and stays well

within the analog input common-mode voltage range

over temperature.

Figure 5. SHA Architecture.

Not Recommended For New Designs

ꢀꢁ ꢂꢃ ꢄ ꢅ ꢆ

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SBAS258A – JUNE 2002 – REVISED JULY 2002

Table 1 lists the digital outputs for the corresponding

analog input voltages.

Table 1. Output Format for Differential Configuration

DIFFERENTIAL INPUT

= (A+/B+) – (A–/B–), REFT – REFB = 1V

ANALOG INPUT VOLTAGE

= +1V

DIGITAL OUTPUT CODE

3FF

= 0

200

000

= –1V

DC–COUPLED DIFFERENTIAL ANALOG

INPUT CIRCUIT

Figure 8. AC-Coupled Differential Input with

Transformer.

Driving the analog input differentially can be achieved

in various ways. Figure 7 gives an example where a

single-ended signal is converted into a differential signal

by using a fully differential amplifier such as the

ANALOG INPUT, SINGLE–ENDED

CONFIGURATION

THS4141. The input voltage applied to V

of the

OCM

For a single-ended configuration, the input signal is

applied to only one of the two inputs. The signal applied

THS4141 shifts the output signal into the desired

common-mode level. V can be connected to CML

OCM

to the analog input must not go below AV

or above

of the ADS5203, the common-mode level is shifted to

AV . The inputs can be biased with any common-mode

AV /2.

voltage provided that the minimum and maximum input

voltage stays within the range AV

to AV . It is

recommended to bias the inputs with a common-mode

voltage around AV /2. This can be accomplished easily

with the output voltage source CML, which is equal to

AV /2. An example for this is shown in Figure 9.

Figure 7. Single-Ended to Differential Conversion

Using the THS4141.

Figure 9. AC–Coupled, Single-Ended Configuration.

The signal amplitude to achieve full scale is 2Vp-p. The

signal, which is applied at A/B+ is centered at the bias

voltage. The input A/B– is also centered at the bias

voltage. The CML output is connected via a 4.7kΩ

resistor to bias the input signal. There is a direct

DC-coupling from CML to A/B– while this input is

AC-decoupled through the 10µF and 0.1µF capacitors.

The decoupling minimizes the coupling of A/B+ into the

A/B– path.

AC–COUPLED DIFFERENTIAL ANALOG

INPUT CIRCUIT

Driving the analog input differentially can be achieved by

using a transformer-coupling, as illustrated in Figure 8.

The center tap of the transformer is connected to the volt-

age source CML, which sets the common-mode voltage

to AV /2. No buffer is required at the output of CML since

the circuit is balanced and no current is drawn from CML.

Not Recommended For New Designs

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Table 2 lists the digital outputs for the corresponding

analog input voltages.

DIGITAL INPUTS

Digital inputs are CLK, STDBY, PWDN_REF, OE, MODE,

and SELB. These inputs don’t have a pull-down resistor

to ground, therefore, they should not be left floating.

Table 2. Output Format for Single-Ended Configu-

ration.

The CLK signal at high frequencies should be considered

as an ‘analog’ input. CLK should be referenced to AV

SINGLE–ENDED INPUT, REFT – REFB = 1V

ANALOG INPUT VOLTAGE

V(A/B+) = V + 1V

DIGITAL OUTPUT CODE

3FF

and AV to reduce noise coupling from the digital logic.

CML

Overshoot/undershoot should be minimized by proper

termination of the signal close to the ADS5203. An

important cause of performance degradation for a

high-speed ADC is clock jitter. Clock jitter causes

uncertainty in the sampling instant of the ADC, in addition

to the inherent uncertainty on the sampling instant caused

by the part itself, as specified by its aperture jitter. There

is a theoretical relationship between the frequency f and

V(A/B+) = V

CML

200

000

CML

– 1V

REFERENCE TERMINALS

The ADS5203’s input range is determined by the voltages

on its REFB and REFT pins. The ADS5203 has an inter-

nal voltage reference generator that sets the ADC refer-

ence voltages REFB = 1V and REFT = 2V. The internal

resolution (2 ) of a signal that needs to be sampled on

one hand, and on the other hand the maximum amount

ADC references must be decoupled to the PCB AV

plane. The recommended decoupling scheme is shown

in Figure 10. The internal reference voltages common-

mode voltage is 1.5V.

of aperture error dt

following relation:

that is tolerable. It is given by the

max

(N+1)

= 1/[π f 2

]

max

As an example, for a 10-bit converter with a 20MHz input,

the jitter needs to be kept less than 7.8ps in order not to

have changes in the LSB of the ADC output due to the

total aperture error.

DIGITAL OUTPUTS

The output of ADS5203 is an unsigned binary code.

Capacitive loading on the output should be kept as low as

possible (a maximum loading of 10pF is recommended)

to ensure best performance. Higher output loading

causes higher dynamic output currents and can,

therefore, increase noise coupling into the part’s analog

front end. To drive higher loads, the use of an output buffer

is recommended.

Figure 10. Recommended External Decoupling for

the Internal ADC Reference.

When clocking output data from ADS5203, it is important

External ADC references can also be chosen. The

ADS5203 internal references must be disabled by tying

PWDN_REF HIGH before applying the external

reference sources to the REFT and REFB pins. The

external reference voltages common-mode voltage

should be 1.5V for best ADC performance.

to observe its timing relation to C

. Please refer to the

OUT

timing section for detailed information on the pipeline

latency in the different modes.

For safest system timing, C

and C

should be used

OUT

to latch the output data, (see Figures 1 to 4). In Figure 4,

can be used by the receiving device to identify

OUT

whether the data presently on the bus is from channel A

or B.

LAYOUT, DECOUPLING, AND GROUNDING

RULES

Proper grounding and layout of the PCB on which the

ADS5203 is populated is essential to achieve the stated

performance. It is advised to use separate analog and

digital ground planes that are spliced underneath the IC.

The ADS5203 has digital and analog pins on opposite

sides of the package to make this easier. Since there is

no connection internally between analog and digital

grounds, they have to be joined on the PCB. It is advised

to do this at one point in close proximity to the ADS5203.

Figure 11. External ADC Reference Configuration.

Not Recommended For New Designs

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SBAS258A – JUNE 2002 – REVISED JULY 2002

As for power supplies, separate analog and digital

4. Analog Input Bandwidth—The analog input

bandwidth is defined as the max. frequency of a 1dBFS

input sine that can be applied to the device for which an

extra 3dB attenuation is observed in the reconstructed

output signal.

supply pins are provided on the part (AV /DV ). The

supply to the digital output drivers is kept separate as

well (DRV ). Lowering the voltage on this supply to

3.0V instead of the nominal 3.3V improves performance

because of the lower switching noise caused by the

output buffers.

5. Output Timing—Output timing t

is measured

d(o)

from the 1.5V level of the CLK input falling edge to the

10%/90% level of the digital output. The digital output

load is not higher than 10pF.

Due to the high sampling rate and switched-capacitor

architecture, the ADS5203 generates transients on the

supply and reference lines. Proper decoupling of these

lines is, therefore, essential.

Output hold time t

is measured from the 1.5V level

h(o)

of the C

input rising edge to the 10%/90% level of

OUT

the digital output. The digital output is load is not less

than 2pF. Aperture delay t is measured from the

NOTES

d(A)

1.5V level of the CLK input to the actual sampling

instant.

1. Integral Nonlinearity (INL)—Integral nonlinearity

refers to the deviation of each individual code from a line

drawn from zero to full-scale. The point used as zero

occurs ½LSB before the first code transition. The

full-scale point is defined as a level ½LSB beyond the

last code transition. The deviation is measured from the

center of each particular code to the true straight line

between these two endpoints.

The OE signal is asynchronous. OE timing t

dis

measured from the V

level of OE to the

high-impedance state of the output data. The digital

output load is not higher than 10pF. OE timing t is

IH(MIN)

measured from the V

level of OE to the instant

IL(MAX)

when the output data reaches V

or V

OH(min)

OL(max)

output levels. The digital output load is not higher than

10pF.

2. Differential Nonlinearity (DNL)—An ideal ADC

exhibits code transitions that are exactly 1LSB apart. DNL

is the deviation from this ideal value. Therefore, this

measure indicates how uniform the transfer function step

sizes are. The ideal step size is defined here as the step

size for the device under test (i.e., (last transition level –

6. Pipeline Delay (latency)—The number of clock

cycles between conversion initiation on an input sample

and the corresponding output data being made

available from the ADC pipeline. Once the data pipeline

is full, new valid output data is provided on every clock

cycle. The first valid data is available on the output pins

first transition level)/(2 – 2)). Using this definition for DNL

separates the effects of gain and offset error.

after the latency time plus the output delay time t

d(o)

through the digital output buffers. Note that a minimum

A minimum DNL better than –1LSB ensures no missing

codes.

is not guaranteed because data can transition

d(o)

before or after a CLK edge. It is possible to use CLK for

latching data, but at the risk of the prop delay varying

over temperature, causing data to transition one CLK

cycle earlier or later. The recommended method is to

3. Zero and Full-Scale Error—Zero error is defined as

the difference in analog input voltage—between the

ideal voltage and the actual voltage—that will switch the

ADC output from code 0 to code 1. The ideal voltage

level is determined by adding the voltage corresponding

to ½LSB to the bottom reference level. The voltage

corresponding to 1LSB is found from the difference of

top and bottom references divided by the number of

ADC output levels (1024).

use the latch signals C

and C

which are

OUT

designed to provide reliable setup and hold times with

respect to the data out.

7. Wake-Up Time—Wake-up time is from the

power-down state to accurate ADC samples being

taken, and is specified for external reference sources

applied to the device and an 80MHz clock applied at the

time of release of STDBY. Cells that need to power up

are the bandgap, bias generator, SHAs, and ADCs.

Full-scale error is defined as the difference in analog

input voltage—between the ideal voltage and the actual

voltage—that will switch the ADC output from code

1022 to code 1023. The ideal voltage level is

determined by subtracting the voltage corresponding to

1.5LSB from the top reference level. The voltage

corresponding to 1LSB is found from the difference of

top and bottom references divided by the number of

ADC output levels (1024).

8. Power-Up Time—Power-up time is from the

power-down state to accurate ADC samples being

taken with an 80MHz clock applied at the time of release

of STDBY. Cells that need to power up are the bandgap,

internal reference circuit, bias generator, SHAs, and

ADCs.

PACKAGE OPTION ADDENDUM

www.ti.com

5-Oct-2015

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ADS5203IPFB

ADS5203IPFBG4

ADS5203IPFBR

ADS5203IPFBRG4

OBSOLETE

TQFP

PFB

TBD

Call TI

-40 to 85

AZ5203

PFB

AZ5203

PFB

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

5,50 TYP

7,20

Gage Plane

6,80

9,20

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ADS5203_15 [TI]

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