ADS5204IPFBRG4Q1 [TI]

DUAL 10-BIT 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH PGA;


型号：	ADS5204IPFBRG4Q1
厂家：	TEXAS INSTRUMENTS
描述：	DUAL 10-BIT 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH PGA
文件：	总25页 (文件大小：964K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

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FEATURES

DESCRIPTION

The ADS5204 is a dual 10-bit, 40 MSPS analog-to-digital

converter (ADC). It simultaneously converts each analog

input signal into a 10-bit, binary coded digital word up to

a maximum sampling rate of 40 MSPS per channel. All

digital inputs and outputs are 3.3-V TTL/CMOS

compatible.

Qualified for Automotive Applications

3.3-V Single-Supply Operation

Dual Simultaneous Sample-and-Hold Inputs

Differential or Single-Ended Analog Inputs

Programmable Gain Amplifier: 0 dB to 18 dB

Separate Serial Control Interface

An innovative dual pipeline architecture implemented in

a CMOS process and the 3.3-V supply results in very

low power dissipation. In order to provide maximum

flexibility, both top and bottom voltage references can

be set from user-supplied voltages. Alternatively, if no

external references are available, the on-chip internal

references can be used. Both ADCs share a common

reference to improve offset and gain matching. If

external reference voltage levels are available, the

internal references can be powered down

independently from the rest of the chip, resulting in even

greater power savings.

Single or Dual Parallel Bus Output

60-dB SNR at f = 10.5 MHz

73-dB SFDR at f = 10.5 MHz

Low Power: 275 mW

300-MHz Analog Input Bandwidth

3.3-V TTL/CMOS-Compatible Digital I/O

Internal or External Reference

Adjustable Reference Input Range

Power-Down (Standby) Mode

TQFP-48 Package

The ADS5204 also features dual, onboard programmable

gain amplifiers (PGAs) that allow a setting of 0 dB to 18 dB

to adjust the gain of each set of inputs in order to match

the amplitude of the incoming signal.

APPLICATIONS

Digital Communications (Baseband Sampling)

Portable Instrumentation

The ADS5204 is characterized for operation from −40°C

to +85°C and is available in a TQFP-48 package.

Video Processing

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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www.ti.com

SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

BLOCK DIAGRAM

{

ORDERING INFORMATION

SPECIFIED

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

PACKAGE

MARKING

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE−LEAD

}

ADS5204

TQFP−48

PFB

−40°C to +85°C

AZ5204Q

ADS5204IPFBRQ1

Tape and Reel, 1000

†

‡

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site

at http://www.ti.com.

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

ADS5204−Q1

to AGND,

to DGND

VDD

−0.5 V to 3.6 V

Supply voltage

to D

VDD

−0.5 V to 0.5 V

AGND to DGND

Digital input voltage range to DGND

−0.5 V to D

+ 0.5 V

VDD

Now

Analog input voltage range to AGND

−0.5 V to A

−0.5 V to D

−0.5 V to A

+ 0.5 V

Digital output voltage applied from Ext. Source to DGND

Reference voltage input range to AGND

, V

REFT REFB

Operating free−air temperature range (ADS5204I

Storage temperature range

−40°C to 85°C

−65°C to 150°C

300°C

STG

Now

Soldering temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, T , unless otherwise noted

(1)

PARAMETER

CONDITIONS

MIN

NOM

MAX

UNIT

POWER SUPPLY

Supply voltage

3.3

3.6

DRV

ANALOG AND REFERENCE INPUTS

Reference input voltage (top)

Reference input voltage (bottom)

Reference voltage differential

Reference input resistance

Reference input current

= 1 MHz to 80 MHz

= 80 MHz

1.9

2.15

1.1

REFT

CLK

0.95

REFB

–V

REFT REFB

1.1

1650

0.62

Ω

REF

= 80 MHz

Analog input voltage, differential

Analog input voltage, single−ended

Analog input capacitance

−1

(1)

CML −1

CML +1

(2)

Clock input

ANALOG OUTPUTS

CML voltage

AV /2

CML output resistance

2.3

kΩ

DIGITAL INPUTS

High-level input voltage

Low-level input voltage

Input capacitance

Clock period

2.4

DGND

0.8

t (80 MHz)

12.5

5.25

w(CLKH), w(CLKL)

(80 MHz)

Pulse duration

Clock period

Pulse duration

Clock high or low

t (40 MHz)

w(CLKH)w, (CLKL)

(40 MHz)

11.25

(1)

(2)

Applies only when the signal reference input connects to CML.

Clock pin is referenced to AV /AV

DD SS

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

ELECTRICAL CHARACTERISTICS

over recommended operating conditions with f

= 80MHz and use of internal voltage references, and PGA Gain = 0dB, unless otherwise noted.

CLK

PARAMETER

TEST CONDITIONS

UNIT

MIN

TYP MAX

POWER SUPPLY

DRV

1.7

2.2

= DV

= DRV

= 3.3 V,

= 3.5 MHz, −1 dBFS

Operating Supply Current

= 10 pF, V

PWDN_REF = ‘L’

PWDN_REF = ‘H’

275

240

125

550

345

300

175

Power Dissipation

Standby Power

STDBY = ‘H’, CLK Held HIGH or LOW

µW

µs

D(STBY)

Power-up time for all references from standby

Wake-up time

External Reference

DIGITAL INPUTS

High-level input current on digital inputs include CLK

Low-level input current on digital inputs include CLK

−1

µA

AV = DV = DRV = 3.6 V

DIGITAL OUTPUTS

= DV

= DRV

= 3 V at

High−level output voltage

Low-level output voltage

2.8

2.96

= 50 µA, Digital outputs forced HIGH

= DV

= DRV

= 3 V at

0.04

0.2

= 50 µA, Digital outputs forced LOW

Output capacitance

µA

High- impedance state output current to high level

High-impedance state output current to low level

−1

OZH

OZL

AV = DV = DRV = 3.6 V

= 10 pF, Single-bus mode

= 10 pF, Dual-bus mode

LOAD

Data output rise and fall time

LOAD

REFERENCE OUTPUTS

Reference top voltage

1.85

0.925

2.1

1.05

REFTO

REFBO

Absolute Min/Max values valid and tested

for AV = 3.3 V

Reference bottom voltage

Differential reference voltage

REFT−REFB

1.0

DC ACCURACY

Internal

INL

Integral nonlinearity, end point .

= −40°C to 85°C

T = −40°C to 85°C

−1.5

−0.9

0.4

1.5

1.0

LSB

(1)

references

Internal

references

DNL

Differential nonlinearity

Missing codes

(2)

No Missing Codes Assured

(3)

Zero error

0.12

0.28

0.24

1.5

%FS

AV = DV = DRV = 3.3 V

External References

(3)

Full-scale error

Gain error

(1)

(2)

(3)

Integralnonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs 1/2 LSB

before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from

the center of each particular code to the best-fit line between these two endpoints.

Integralnonlinearity refers to the deviation of each individual code from a line drawn from zero to full-scale. The point used as zero occurs 1/2 LSB

before the first code transition. The full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from

the center of each particular code to the best-fit line between these two endpoints.

Zero error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that switches the ADC output

from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The

voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output levels (1024).

Full-scale error is defined as the difference in analog input voltage—between the ideal voltage and the actual voltage—that switches the ADC

output from code 1022 to code 1023. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top

reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by the number of ADC output

levels (1024).

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

(1)

DYNAMIC PERFORMANCE

= T

to T

, AV

= DV

= DRV

= 3.3 V, f = −1 dBFS, Internal Reference, f = 80 MHz, f = 40 MSPS, Differential Input Range

IN CLK S

MIN

MAX

= 2 Vp−p, and PGA Gain = 0 dB, unless otherwise noted

PARAMETER

TEST CONDITIONS

= 3.5 MHz

MIN

TYP MAX

UNIT

Bits

9.7

= 10.5 MHz

= 20 MHz

= 3.5 MHz

= 10.5 MHz

= 20 MHz

= 3.5 MHz

= 10.5 MHz

= 20 MHz

= 3.5 MHz

= 10.5 MHz

= 20 MHz

= 3.5 MHz

= 10.5 MHz

= 20 MHz

9.3

ENOB

THD

Effective number of bits

Total harmonic distortion

Signal-to-noise ratio

9.6

−71

−68

60.5

−63

SNR

SINAD Signal-to-noise ratio + distortion

SFDR

IMD

Spurious-free dynamic range

70.5

300

−68

−75

0.016

0.025

Analog input bandwidth

See Note (2)

f = 9.5 MHz, f = 9.9 MHz

MHz

dBc

2-Tone intermodulation distortion

A/B channel crosstalk

A/B channel offset mismatch

A/B channel full-scale error mismatch

1.75 % of FS

% of FS

(1)

(2)

These specifications refer to a 25-Ω series resistor and 15-pF differential capacitor between A/B+ and A/B− inputs; any source impedance brings

the bandwidth down.

Analog input bandwidth is defined as the frequency at which the sampled input signal is 3 dB down on unity gain and is limited by the input switch

impedance.

PGA SPECIFICATIONS

PARAMETER

MIN

TYP

MAX

UNIT

Gain Range

0 to 18

(1)

Gain Step Size

0.5826

0.025

(2)

Gain Error

−0.15

0.15

Control Bits Per Channel

Bits

(1)

(2)

See Table 2, PGA Gain Code. Ideal step size: 18.0618 dB / 31 = 0.5826 dB

Deviation from ideal. See Table 2, all gain settings.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

PIN CONFIGURATION

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

1,13

DRV

Supply Voltage for Output Drivers

Digital Ground for Output Drivers

DRV

12, 24

14-23

DA 9..0

Data Outputs for Bus A. D9 is MSB. This is the primary bus. Data from both input channels can be output on this bus

or data from channel A only. The data outputs are in 3-state during power-down (see the Register Configuration table).

DB 9..0

Data Outputs for Bus B. D9 is MSB. This is the second bus. Data is output from the B channel when dual bus output

2-11

mode is selected. The data outputs are in 3-state during power-down and single-bus modes (see the Timing Options

table).

Output Enable. A low on this terminal will enable the data output bus, C

and C

OUT

Latch Clock for the Data Outputs. C

is in 3-state during power down.

OUT

Inverted Latch Clock control for the Data Outputs. C

is in 3-state during power down.

OUT

SDI

Serial Data I/O

Digital Ground

CLK

Clock Input. The input is sampled on each rising edge of CLK when using a 40-MHz input and alternate rising edges

when using an 80-MHz input. The clock pin is referenced to AV and AV to reduce noise coupling from digital logic.

Digital Supply Voltage

27,37,41

Analog Supply Voltage

Serial Data Registers Chip Select

Analog Ground

28,36,40

B−

Negative Input for the Analog B Channel

Positive Input for the Analog B Channel

B+

REFT

Reference Voltage Top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient filtering

I/O

should be applied to this input: the use of 0.1-µF capacitor between REFT and AV

Additionally a 0.1-µF capacitor should be connected between REFT and REFB.

is highly recommended.

REFB

CML

Reference Voltage Bottom. The voltage at this terminal defines the bottom reference voltage for the ADC. Sufficient

I/O

filtering should be applied to this input: the use of 0.1-µF capacitor between REFB and AV is recommended.

Additionally, a 0.1-µF capacitor should be connected between REFT and REFB.

Common-Mode Level. This voltage is equal to (AV − AV )/2. An external capacitor of 0.1µF should be connected

between this terminal and AV when CML is used as a bias voltage. No capacitor is required if CML is not used.

PDWN_REF

STBY

A−

Power-Down for Internal Reference Voltages. A HIGH on this terminal disables the internal reference circuit.

Standby Input. A high on this terminal powers down the device.

Negative Input for the Analog A Channel

A+

Positive Input for Analog A Channel

SCLK

Serial Data Clock. Maximum clock rate is 20 MHz.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Input clock rate

Conversion rate

MHz

CLK

MSPS

Clock duty cycle (40MHz)

Clock duty cycle (80MHz)

Output delay time

= 10 pF

d(o)

Mux setup time

1.7

10.4

2.1

10.4

s(m)

h(m)

s(o)

Mux hold time

= 10 pF

Output setup time

Pipeline delay (latency, channels A and B)

Pipeline delay (latency, channel A)

Pipeline delay (latency, channel B)

Pipeline delay (latency, channel A)

Pipeline delay (latency, channel B)

Output hold time

CLK Cycles

MODE = 0, SELB = 0

MODE = 1, SELB = 0

MODE = 0, SELB = 1

MODE = 1, SELB = 1

d(pipe)

h(o)

1.5

2.2

= 10 pF

Aperture delay time

d(a)

Aperture jitter

1.5

ps, rms

J(a)

Disable time, OE rising to Hi-Z

Enable T\time, OE falling to valid data

dis

(1)

All internal operations are performed at a 40-MHz clock rate.

SERIAL INTERFACE TIMING

PARAMETER

MIN

TYP

MAX

UNIT

Maximum Clock Rate

SCLK Pulse Width high

SCLK Pulse Width low

MHz

SCLK

Setup Time, CS low Before First Negative SCLK Edge

CS HIGH Width

SU(CS_CK)

WH(CS)

Setup Time, 16th Negative SCLK Edge before CS Rising Edge

Setup Time, Data Ready Before SCLK Falling Edge

Hold Time, Data Held Valid After SCLK Falling Edge

SU(C16_CK)

SU(D)

SU(H)

TIMING OPTIONS

OPERATING MODE

MODE

SELB

TIMING DIAGRAM FIGURE

80-MHz Input Clock, Dual-Bus Output, C

40-MHz Input Clock, Dual-Bus Output, C

= 40 MHz

OUT

80-MHz Input Clock, Single-Bus Output, C

= 40 MHz

= 80 MHz

OUT

80-MHz Input Clock, Single-Bus Output, C

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

TIMING DIAGRAMS

Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

ADC

OUT

t_d(pipe)

(3)

B[9:0]

ADC

t_d(o)

DA[9:0]

t_d(o)

DB[9:0]

DAB[19:0] is used to illustrate the placement of the busses DA and DB

DAB[19:0]

A&B 1

t_s(o)

A&B 2

t_h(o)

A&B 3

A&B 4

A&B 5

OUT

(1)

In this option CLK = 80 MHz.

(2))

(3))

CLK40INT refers to 40-MHz Internal Clock, per channel.

Internal signal only.

Figure 1. Dual Bus Output—Option 1

Sample A1 and B1

Analog_A

Analog_B

(1)

(2)

CLK

t_d(pipe)

ADC

A[9:0]

OUT

t_d(pipe)

(2)

B[9:0]

OUT

t_d(o)

DA[9:0]

t_d(o)

DB[9:0]

DAB[19:0] is used to illustrate the combined busses DA and DB

DAB[19:0]

A&B 1

t_s(o)

A&B 2

t_h(o)

A&B 3

A&B 4

A&B 5

OUT

(1)

(2))

In this option CLK = 40 MHz, per channel.

Internal signal only.

Figure 2. Dual Bus Output—Option 2

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Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

OUT

ADC

t_d(pipe)

(3)

B[9:0]

t_d(o)

ADC

OUT

t_d(o)

DA[9:0]

A1 B1 A2 B2 A3 B3 A4 B4 A5 B5

t_h(o)

t_s(o)

OUT

t_h(o)

t_s(o)

(1)

In this option CLK = 80 MHz, per channel.

(2))

(3))

CLK40INT refers to 40-MHz internal Clock, per channel.

Internal signal only.

Figure 3. Single Bus Output—Option 1

Sample A1 and B1

Analog_A

Analog_B

10 11 12 13 14 15 16 17 18

(1)

CLK

(2)

CLK40INT

t_d(pipe)

(3)

A[9:0]

ADC

OUT

t_d(pipe)

(3)

B[9:0]

OUT

t_d(o)

DA[9:0]

A1 B1 A2 B2 A3 B3 A4 B4

t_h(o)

t_s(o)

OUT

t_s(m)

t_h(m)

OUT

(1)

(2))

(3))

In this option CLK = 80 MHz.

CLK40INT refers to 40-MHz internal Clock, per channel.

Internal signal only.

Figure 4. Single Bus Output—Option 2

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

t_WH

t_WL

SCLK

t_WH(CS)

t_{SU(CS_CK)}

t_{SU(C16_CS)}

t_SU(D)

t_H(D)

D15

SDI

D14

D13

D12

D01

D00

Figure 5. Serial Data Write

Table 1. Register Configuration

PGA4 PGA3 PGA2 PGA1 PGA0 PGA4 PGA3 PGA2 PGA1 PGA0

Reserved TWOS MODE SELB

Always write 0

Default (power up) condition for this register is all bits = 0.

The user register is updated on either the first rising edge

of SCLK after the 16th falling edge or CS rising, whichever

comes first. Raising CS before 16 falling SCLK edges

have been seen is an incomplete write error and no

resynchronized to the internal data conversion clock to

avoid data glitches caused by changing gain settings

while sampling the inputs.

Note that only the PGA data is resynchronized. The

TWOS, MODE, and SELB register bits take effect

immediately after a successful register write.

OUTPUT DATA FORMAT

The output data format can either be in Binary Two’s

Complement ouput mode or in unsigned binary mode,

which affects both A and B channels.

TWOS − Binary Two’s Complement Mode:

0 − Unsigned Binary

PGA gain control data is applied to the PGAs on the

second falling edge of the ADC sample clock

(CLK40INT) after a successful register write. This

resynchronization ensures that no analog glitch occurs

even when SCLK is asynchronous to CLK.

1 − Binary Two’s Complement Output.

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Table 2. PGA DB[0:4], 5−bit PGA gain code for channel A or B

GAIN (dB)

PGx4

PGx3

PGx2

PGx1

PGx0

0.5606

1.1599

1.6643

2.3806

2.8703

3.5218

4.0824

4.6817

5.1630

5.8451

6.3903

6.9807

7.6040

8.0497

8.7712

9.2831

9.8272

10.4078

11.0301

11.7005

12.0412

12.7970

13.2208

14.0944

14.5400

15.0666

15.5630

16.1623

16.7229

17.4181

18.0618

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

TYPICAL CHARACTERISTICS

At T = 25°C, AV

= DV

= DRV

= 3.3 V, f = −0.5 dBFS, Internal Reference, f = 80 MHz, f = 40 MSPS, Differential Input Range = 2 Vp-p,

IN CLK S

25-Ω series resistor, and 15-pF differential capacitor at A/B+ and A/B− inputs, unless otherwise noted.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

TYPICAL CHARACTERISTICS (Continued)

At T = 25°C, AV

= DV

= DRV

= 3.3 V, f = −0.5 dBFS, Internal Reference, f = 80 MHz, f = 40 MSPS, Differential Input Range = 2 Vp-p,

IN CLK S

25-Ω series resistor, and 15-pF differential capacitor at A/B+ and A/B− inputs, unless otherwise noted.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

The analog input signal is sampled on capacitors C

PRINCIPLE OF OPERATION

and C

while the internal device clock is low. The

The ADS5204 implements a dual high-speed 10-bit,

40MSPS converter in a cost-effective CMOS process.

The differential inputs on each channel are sampled

simultaneously. Signal inputs are differential and the clock

signal is single-ended. The clock signal is either 80 MHz

or 40 MHz, depending on the device configuration set by

the user. Powered from 3.3 V, the dual-pipeline design

architecture ensures low-power operation and 10-bit

resolution. The digital inputs are 3.3-V TTL/CMOS

compatible. Internal voltage references are included for

both bottom and top voltages. Alternatively, the user may

apply externally generated reference voltages. In doing

so, the input range can be modified to suit the application.

sampled voltage is transferred to capacitors C

and

and held on these while the internal device clock

is high. The SHA can sample both single-ended and

differential input signals.

The load presented to the AIN pin consists of the

switched input sampling capacitor C (approximately

2 pF) and its various stray capacitances. A simplified

equivalent circuit for the switched capacitor input is

shown in Figure 7. The switched capacitor circuit is

modeled as a resistor R . f

is the clock frequency,

IN CLK

which is 40 MHz at full speed, and C is the sampling

capacitor. The use of 25-Ω series resistors and a

differential 15-pF capacitor at the A/B+ and A/B− inputs

is recommended to reduce noise.

The ADC is a 5-stage pipelined ADC with four stages of

fully-differential switched capacitor sub-ADC/MDAC

pairs and a single sub-ADC in stage five. All stages

deliver two bits of the final conversion result. A digital

error correction is used to compensate for modest

comparator offsets in the sub-ADCs.

NOTE: AIN can be any variation

of A or B inputs.

= 40MHz

CLK

SAMPLE-AND-HOLD AMPLIFIER

Figure 6 shows the internal SHA/SHPGA architecture.

The circuit is balanced and fully differential for good

supply noise rejection. The sampling circuit has been

kept as simple as possible to obtain good performance

for high-frequency input signals.

= 0.5 S (V(A/B+) + V(A/B−))

Figure 7. Equivalent Circuit for the

Switched Capacitor Input

ANALOG INPUT, DIFFERENTIAL

CONNECTION

The analog input of the ADS5204 is a differential

architecture that can be configured in various ways

depending on the signal source and the required level

of performance. A fully differential connection will

deliver the best performance from the converter. The

analog inputs must not go below AV or above AV

The inputs can be biased with any common-mode

voltage provided that the minimum and maximum input

voltages stay within the range AV

to AV . It is

recommended to bias the inputs with a common-mode

voltage around AV /2. This can be accomplished

easily with the output voltage source CML, which is

equal to AV /2. CML is made available to the user to

help simplify circuit design. This output voltage source

is not designed to be a reference or to be loaded but

makes an excellent dc bias source and stays well within

the analog input common-mode voltage range over

temperature.

Figure 6. SHA/SHPGA Architecture

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

Table 3 lists the digital outputs for the corresponding

analog input voltages.

ADS5204

Table 3. Output Format for Differential Configuration

DIFFERENTIAL INPUT

= (A/B+) – (A/B−), REFT − REFB = 1 V, PGA = 0 dB

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

3FF

= +1 V

= 0

200

= −1 V

000

Figure 9. AC-Coupled Differential Input with

Transformer

DC-COUPLED DIFFERENTIAL ANALOG

INPUT CIRCUIT

ANALOG INPUT, SINGLE-ENDED

CONFIGURATION

Driving the analog input differentially can be achieved

in various ways. Figure 8 gives an example where a

single-ended signal is converted into a differential signal

by using a fully differential amplifier such as the

For a single-ended configuration, the input signal is

applied to only one of the two inputs. The signal applied

to the analog input must not go below AV

THS4141. The input voltage applied to V

of the

OCM

or above

THS4141 shifts the output signal into the desired

common-mode level. V can be connected to CML

AV . The inputs can be biased with any common-mode

OCM

voltage provided that the minimum and maximum input

of the ADS5204, the common-mode level is shifted to

AV /2.

voltage stays within the range AV

to AV . It is

recommended to bias the inputs with a common-mode

voltage around AV /2. This can be accomplished easily

with the output voltage source CML, which is equal to

ADS5204

AV /2. An example for this is shown in Figure 10.

ADS5204

Figure 8. Single-Ended to Differential Conversion

Using the THS4141

Figure 10. AC-Coupled, Single-Ended

Configuration

AC-COUPLED DIFFERENTIAL ANALOG

INPUT CIRCUIT

The signal amplitude to achieve full-scale is 2 Vp-p. The

signal, which is applied at A/B+ is centered at the bias

voltage. The input A/B− is also centered at the bias

voltage. The CML output is connected via a 4.7-kΩ

resistor to bias the input signal. There is a direct

dc-coupling from CML to A/B− while this input is

ac-decoupled through the 10-µF and 0.1-µF capacitors.

The decoupling minimizes the coupling of A/B+ into the

A/B− path.

Driving the analog input differentially can be achieved by

using a transformer coupling, as illustrated in NO TAG.

The center tap of the transformer is connected to the

voltage source CML, which sets the common-mode

voltage to AV /2. No buffer is required at the output of

CML since the circuit is balanced and no current is drawn

from CML.

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

Table 4 lists the digital outputs for the corresponding

analog input voltages.

DIGITAL INPUTS

Digital inputs are CLK, SCLK, SDI, CS, STDBY,

PWDN_REF, and OE. These inputs don’t have a

pulldown resistor to ground, therefore, they should not

be left floating.

Table 4. Output Format for Single-Ended Configuration

SINGLE-ENDED INPUT, REFT − REFB = 1V, PGA = 0dB

ANALOG INPUT VOLTAGE

V(A/B+) = V + 1V

DIGITAL OUTPUT CODE

3FF

The CLK signal at high frequencies should be

considered as an ‘analog’ input. CLK should be

CML

V(A/B+) = V

200

CML

− 1V

referenced to AV

and AV to reduce noise coupling

V(A/B+) = V

CML

000

from the digital logic. Overshoot/undershoot should be

minimized by proper termination of the signal close to

the ADS5204. An important cause of performance

degradation for a high-speed ADC is clock jitter. Clock

jitter causes uncertainty in the sampling instant of the

ADC, in addition to the inherent uncertainty on the

sampling instant caused by the part itself, as specified

by its aperture jitter. There is a theoretical relationship

REFERENCE TERMINALS

The ADS5204’s input range is determined by the voltages

on its REFB and REFT pins. The ADS5204 has an

internal voltage reference generator that sets the ADC

reference voltages REFB = 1 V and REFT = 2 V. The

internal ADC references must be decoupled to the PCB

between the frequency (f) and resolution (2 ) of a signal

that needs to be sampled on one hand, and on the other

hand the maximum amount of aperture error dt

is tolerable. It is given by the following relation:

plane. The recommended decoupling scheme is

shown in Figure 11. The common-mode reference

voltages should be 1.5 V for best ADC performance.

that

max

(N+1)

= 1/[π f 2

]

max

ADS5204

As an example, for a 10-bit converter with a 20MHz

input, the jitter needs to be kept less than 7.8ps in order

not to have changes in the LSB of the ADC output due

to the total aperture error.

DIGITAL OUTPUTS

The output of ADS5204 is an unsigned binary or Binary

Two’s Complement code. Capacitive loading on the

output should be kept as low as possible (a maximum

loading of 10 pF is recommended) to ensure best

performance. Higher output loading causes higher

dynamic output currents and can, therefore, increase

noise coupling into the part’s analog front end. To drive

higher loads, the use of an output buffer is

recommended.

Figure 11. Recommended External Decoupling for

the Internal ADC Reference

External ADC references can also be chosen. The

ADS5204 internal references must be disabled by tying

PWDN_REF high before applying the external reference

sources to the REFT and REFB pins. The common-mode

reference voltages should be 1.5 V for best ADC

performance.

When clocking output data from ADS5204, it is

important to observe its timing relation to C

. See the

OUT

Timing section for detailed information on the pipeline

latency in the different modes.

ADS5204

For safest system timing, C

and C

should be used

OUT

to latch the output data (see Figure 1 through Figure 4).

In Figure 4, C can be used by the receiving device to

OUT

identify whether the data presently on the bus is from

channel A or B.

Figure 12. External ADC Reference Configuration

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

first transition level)/(2 − 2)]. Using this definition for DNL

LAYOUT, DECOUPLING, AND GROUNDING

RULES

separates the effects of gain and offset error. A minimum

DNL better than –1LSB ensures no missing codes.

Proper grounding and layout of the PCB on which the

ADS5204 is populated is essential to achieve the stated

performance. It is advised to use separate analog and

digital ground planes that are spliced underneath the IC.

The ADS5204 has digital and analog pins on opposite

sides of the package to make this easier. Since there is

no connection internally between analog and digital

grounds, they have to be joined on the PCB. It is

advised to do this at one point in close proximity to the

ADS5204.

3. Zero and Full-Scale Error—Zero error is defined as

the difference in analog input voltage—between the

ideal voltage and the actual voltage—that switches the

ADC output from code 0 to code 1. The ideal voltage

level is determined by adding the voltage corresponding

to 1/5 LSB to the bottom reference level. The voltage

corresponding to 1 LSB is found from the difference of

top and bottom references divided by the number of

ADC output levels (1024).

As for power supplies, separate analog and digital supply

pins are provided on the part (AV /DV ). The supply to

Full-scale error is defined as the difference in analog input

voltage—between the ideal voltage and the actual

voltage—that switches the ADC output from code 1022 to

code 1023. The ideal voltage level is determined by

subtracting the voltage corresponding to 1. 5LSB from the

top reference level. The voltage corresponding to 1 LSB

is found from the difference of top and bottom references

divided by the number of ADC output levels (1024).

the digital output drivers is kept separate as well (DRV ).

Lowering the voltage on this supply to 3 V instead of the

nominal 3.3 V improves performance because of the

lower switching noise caused by the output buffers.

Due to the high sampling rate and switched-capacitor

architecture, the ADS5204 generates transients on the

supply and reference lines. Proper decoupling of these

lines is, therefore, essential.

4. Analog Input Bandwidth—The analog input

bandwidth is defined as the max. frequency of a 1-dBFS

input sine that can be applied to the device for which an

extra 3-dB attenuation is observed in the reconstructed

output signal.

SERIAL INTERFACE

A falling edge on CS enables the serial interface,

allowing the 16-bit control register date to be shifted

(MSB first) on subsequent falling edges of SCLK. The

data is loaded into the control register on the first rising

edge of SCLK after its 16th falling edge or CS rising,

whichever occurs first. CS rising before 16 falling SCLK

edges have been counted is an error and the control

5. Output Timing—Output timing t

from the 1.5-V level of the CLK input falling edge to the

10%/90% level of the digital output. The digital output

load is not higher than 10 pF. Output hold time t

measured from the 1.5-V level of the C

is measured

d(o)

h(o)

input rising

OUT

edge to the 10%/90% level of the digital output. The

digital output is load is not less than 2 pF. Aperture delay

is measured from the 1.5-V level of the CLK input

d(A)

The maximum update rate is:

to the actual sampling instant.

f_SCLK

20MHz

The OE signal is asynchronous. OE timing t

dis

f_UPDATEMAX

+ 1.25MHz

measured from the V

level of OE to the high-

IH(MIN)

impedance state of the output data. The digital output load

is not higher than 10 pF. OE timing t is measured from

NOTES

the V

level of OE to the instant when the output

IL(MAX)

1. Integral Nonlinearity (INL)—Integral nonlinearity

refers to the deviation of each individual code from a line

drawn from zero to full-scale. The point used as zero

occurs 1/2 LSB before the first code transition. The

full-scale point is defined as a level 1/2 LSB beyond the

last code transition. The deviation is measured from the

center of each particular code to the true straight line

between these two endpoints.

data reaches V

digital output load is not higher than 10 pF.

or V

output levels. The

OH(min)

OL(max)

6. Pipeline Delay (latency)—The number of clock

cycles between conversion initiation on an input sample

and the corresponding output data being made

available from the ADC pipeline. Once the data pipeline

is full, new valid output data is provided on every clock

cycle. The first valid data is available on the output pins

2. Differential Nonlinearity (DNL)—An ideal ADC

exhibits code transitions that are exactly 1 LSB apart. DNL

is the deviation from this ideal value. Therefore, this

measure indicates how uniform the transfer function step

sizes are. The ideal step size is defined here as the step

size for the device under test [ i.e. (last transition level −

after the latency time plus the output delay time t

d(o)

through the digital output buffers. Note that a minimum

is not assured because data can transition before

d(o)

or after a CLK edge. It is possible to use CLK for latching

data, but at the risk of the prop delay varying over

temperature, causing data to transition one CLK cycle

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SGLS271A − OCTOBER 2004 − REVISED JUNE 2008

earlier or later. The recommended method is to use the

8. Power-Up Time—Power-up time is from the

power-down state to accurate ADC samples being

taken with an 80-MHz clock applied at the time of

release of STDBY. Cells that need to power up are the

bandgap, internal reference circuit, bias generator,

SHAs, and ADCs.

latch signals C

and C

which are designed to

OUT

provide reliable setup and hold times with respect to the

data out.

7. Wake-Up Time—Wake-up time is from the

power-down state to accurate ADC samples being taken

and is specified for external reference sources applied to

the device and an 80-MHz clock applied at the time of

release of STDBY. Cells that need to power up are the

bandgap, bias generator, SHAs, and ADCs.

PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2011

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

ADS5204IPFBRG4Q1

ADS5204IPFBRQ1

ACTIVE

TQFP

PFB

1000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS5204-Q1 :

Catalog: ADS5204

•

NOTE: Qualified Version Definitions:

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2011

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS5204IPFBRG4Q1

ADS5204IPFBRQ1

TQFP

PFB

1000

330.0

16.4

9.6

1.5

12.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS5204IPFBRG4Q1

ADS5204IPFBRQ1

TQFP

PFB

1000

367.0

38.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

PFB (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

0,08

0,13 NOM

5,50 TYP

7,20

Gage Plane

6,80

9,20

8,80

0,25

0,05 MIN

0°–7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4073176/B 10/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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