ADS5231IPAG [TI]
双通道、12 位、40MSPS 模数转换器 (ADC) | PAG | 64 | -40 to 85;
| 型号： | ADS5231IPAG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道、12 位、40MSPS 模数转换器 (ADC) | PAG | 64 | -40 to 85 转换器 模数转换器 |
| 文件： | 总30页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SBAS295A–JULY 2004–REVISED JANUARY 2007
Dual, 12-Bit, 40MSPS, +3.3V
Analog-to-Digital Converter
FEATURES
DESCRIPTION
•
•
•
Single +3.3V Supply
The ADS5231 is a dual, high-speed, high dynamic
range, 12-bit pipelined analog-to-digital converter
(ADC). This converter includes a high-bandwidth
sample-and-hold amplifier that gives excellent
spurious performance up to and beyond the Nyquist
rate. The differential nature of the sample-and-hold
amplifier and ADC circuitry minimizes even-order
harmonics and gives excellent common-mode noise
immunity.
High SNR: 70.7dBFS at fIN = 5MHz
Total Power Dissipation:
Internal Reference: 321mW
External Reference: 285mW
•
•
•
•
Internal or External Reference
Low DNL: ±0.3LSB
Flexible Input Range: 1.5VPP to 2VPP
TQFP-64 Package
The ADS5231 provides for setting the full-scale
range of the converter without any external reference
circuitry. The internal reference can be disabled,
allowing low-drive, external references to be used for
improved tracking in multichannel systems.
APPLICATIONS
•
•
•
•
•
•
Communications IF Processing
Communications Base Stations
Test Equipment
Medical Imaging
Video Digitizing
The ADS5231 provides an over-range indicator flag
to indicate an input signal that exceeds the full-scale
input range of the converter. This flag can be used to
reduce the gain of front-end gain control circuitry.
There is also an output enable pin to allow for
multiplexing and testing on a printed circuit board
(PCB).
CCD Digitizing
The ADS5231 employs digital error correction
techniques to provide excellent differential linearity
for demanding imaging applications. The ADS5231 is
available in a TQFP-64 package.
AVDD SDATA SEN SCLK SEL
VDRV
OEA
ADS5231
Serial
Interface
DISABLE_PLL
D11A
·
12-Bit
Pipelined
ADC
INA
INA
Error
Correction
Logic
3-State
Output
VIN
·
S/H
·
D0A
OVRA
DVA
Timing/Duty Cycle
Adjust (PLL)
Internal
Reference
INT/EXT
CLK
CM
REFT
REFB
DVB
D11B
·
INB
INB
12-Bit
Pipelined
ADC
Error
Correction
Logic
3-State
Output
·
S/H
VIN
·
D0B
OVRB
STPD
OEB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
ADS5231
www.ti.com
SBAS295A–JULY 2004–REVISED JANUARY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS5231IPAG
Tray, 160
ADS5231
TQFP-64
PAG
–40°C to +85°C
ADS5231IPAG
ADS5231IPAGT Tape and Reel, 250
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD
Supply Voltage Range, VDRV
Voltage Between AVDD and VDRV
Voltage Applied to External REF Pins
Analog Input Pins(2)
–0.3V to +3.8V
–0.3V to +3.8V
–0.3V to +0.3V
–0.3V to +2.4V
–0.3V to min. [3.3V, (AVDD + 0.3V)]
+100°C
Case Temperature
Operating Free-Air Temperature Range, TA
Lead Temperature
–40°C to +85°C
+260°C
Junction Temperature
+105°C
Storage Temperature
–65°C to +150°C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
(2) The dc voltage applied on the input pins should not go below –0.3V. Also, the dc voltage should be limited to the lower of either 3.3V or
(AVDD + 0.3V). If the input can go higher than +3.3V, then a resistor greater than or equal to 25Ω should be added in series with each
of the input pins. Also, the duty cycle of the overshoot beyond +3.3V should be limited. The overshoot duty cycle can be defined either
as a percentage of the time of overshoot over a clock period, or over the entire device lifetime. For a peak voltage between +3.3V and
+3.5V, a duty cycle up to 10% is acceptable. For a peak voltage between +3.5V and +3.7V, the overshoot duty cycle should not exceed
1%. Any overshoot beyond +3.7V should be restricted to less than 0.1% duty cycle, and never exceed +3.9V.
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SBAS295A–JULY 2004–REVISED JANUARY 2007
RECOMMENDED OPERATING CONDITIONS
ADS5231
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, VDRV
REFT — External Reference Mode
REFB — External Reference Mode
REFCM = (REFT + REFB)/2 – External Reference Mode(1)
Reference = (REFT – REFB) – External Reference Mode
Analog Input Common-Mode Range(1)
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate
PLL Enabled (default)
3.0
3.0
3.3
3.3
3.6
3.6
V
V
V
V
V
V
V
1.875
0.95
2.0
2.05
1.125
1.0
V
CM ± 50mV
1.0
0.75
1.1
V
CM ± 50mV
20
2
40
30(2)
MSPS
MSPS
PLL Disabled
ADCLK Duty Cycle
PLL Enabled (default)
45
55
MSPS
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
Operating Free-Air Temperature, TA
Thermal Characteristics:
0.6
V
V
2.2
–40
+85
°C
θJA
42.8
18.7
°C/W
°C/W
θJC
(1) These voltages need to be set to 1.5V ± 50mV if they are derived independent of VCM
.
(2) When the PLL is disabled, the clock duty cycle needs to be controlled well, especially at higher speeds. A 45%–55% duty cycle variation
is acceptable up to a frequency of 30MSPS. If the device needs to be operated in the PLL disabled mode beyond 30MSPS, then the
duty cycle needs to be maintained within 48%–52% duty cycle.
3
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SBAS295A–JULY 2004–REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5231
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
Tested
±0.3
±0.4
±0.2
±6
DNL Differential Nonlinearity
INL Integral Nonlinearity
fIN = 5MHz
fIN = 5MHz
–0.9
–2.5
+0.9
+2.5
LSB
LSB
Offset Error(1)
–0.75
+0.75
% FS
ppm/°C
%FS
Offset Temperature Coefficient(2)
Fixed Attenuation in Channel(3)
Fixed Attenuation Matching Across Channels
Gain Error/Reference Error(4)
Gain Error Temperature Coefficient
POWER REQUIREMENTS(5)
Internal Reference
1
0.01
±1.0
±40
0.2
dB
–3.5
+3.5
% FS
ppm/°C
Power Dissipation(5)
Analog Only (AVDD)
Output Driver (VDRV)
235.5
85.5
321
271
109
380
mW
mW
mW
Total Power Dissipation
External Reference
Power Dissipation
Analog Only (AVDD)
Output Driver (VDRV)
200
85.5
mW
mW
mW
mW
Total Power Dissipation
Total Power-Down
285.5
Clock Running
83
REFERENCE VOLTAGES
VREFT Reference Top (internal)
VREFB Reference Bottom (internal)
VCM Common-Mode Voltage
VCM Output Current(6)
1.9
0.9
1.4
2.0
1.0
1.5
±2
2.1
1.1
1.6
V
V
V
±50mV Change in Voltage
mA
V
VREFT Reference Top (external)
VREFB Reference Bottom (external)
External Reference Common-Mode
External Reference Input Current(7)
1.875
1.125
V
V
CM ± 50mV
V
1.0
mA
(1) Offset error is the deviation of the average code from mid-code with –1dBFS sinusoid from ideal mid-code (2048). Offset error is
expressed in terms of % of full-scale.
(2) If the offset at temperatures T1 and T2 are O1 and O2, respectively (where O1 and O2 are measured in LSBs), the offset temperature
coefficient in ppm/°C is calculated as (O1 – O2)/(T1 – T2) × 1E6/4096.
(3) Fixed attenuation in the channel arises because of a fixed attenuation in the sample-and-hold amplifier. When the differential voltage at
the analog input pins is changed from –VREF to +VREF, the swing of the output code is expected to deviate from the full-scale code
(4096LSB) by the extent of this fixed attenuation. NOTE: VREF is defined as (REFT – REFB).
(4) The reference voltages are trimmed at production so that (VREFT – VREFB) is within ± 35mV of the ideal value of 1V. This specification
does not include fixed attenuation.
(5) Supply current can be calculated from dividing the power dissipation by the supply voltage of 3.3V.
(6) The VCM output current specified is the drive of the VCM buffer if loaded externally.
(7) Average current drawn from the reference pins in the external reference mode.
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SBAS295A–JULY 2004–REVISED JANUARY 2007
ELECTRICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
ADS5231
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Differential Input Capacitance
3
pF
V
Analog Input Common-Mode Range
Differential Input Voltage Range
V
CM ± 0.05
Internal Reference
External Reference
2.02
VPP
2.02 × (VREFT – VREFB)
VPP
Voltage Overload Recovery Time(8)
Input Bandwidth
3
CLK Cycles
–3dBFS Input, 25Ω Series
300
MHz
Resistance
DIGITAL DATA INPUTS
Logic Family
VIH High-Level Input Voltage
VIL Low-Level Input Voltage
CIN Input Capacitance
DIGITAL OUTPUTS
+3V CMOS Compatible
VIN = 3.3V
VIN = 3.3V
2.2
0.6
3
V
V
pF
Data Format
Straight Offset Binary(9)
Logic Family
CMOS
Logic Coding
Straight Offset Binary or BTC
Low Output Voltage (IOL = 50µA)
High Output Voltage (IOH = 50µA)
3-State Enable Time
+0.4
V
V
+2.4
2
2
3
Clocks
Clocks
pF
3-State Disable Time
Output Capacitance
SERIAL INTERFACE
SCLK Serial Clock Input Frequency
CONVERSION CHARACTERISTICS
Sample Rate
20
MHz
20
40
MSPS
Data Latency
6
CLK Cycles
(8) A differential ON/OFF pulse is applied to the ADC input. The differential amplitude of the pulse in its ON (high) state is twice the
full-scale range of the ADC, while the differential amplitude of the pulse in its OFF (low) state is zero. The overload recovery time of the
ADC is measured as the time required by the ADC output code to settle within 1% of full-scale, as measured from its mid-code value
when the pulse is switched from ON (high) to OFF (low).
(9) Option for Binary Two’s Complement Output.
5
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SBAS295A–JULY 2004–REVISED JANUARY 2007
AC CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, VDRV = 3.3V, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless otherwise noted.
ADS5231
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 5MHz
fIN = 32.5MHz
fIN = 70MHz
fIN = 5MHz
75
86
85
dBc
dBc
SFDR Spurious-Free Dynamic Range
HD2 2nd-Order Harmonic Distortion
HD3 3rd-Order Harmonic Distortion
SNR Signal-to-Noise Ratio
83
dBc
82
75
92
dBc
fIN = 32.5MHz
fIN = 70MHz
fIN = 5MHz
87
dBc
85
dBc
86
dBc
fIN = 32.5MHz
fIN = 70MHz
fIN = 5MHz
85
dBc
83
dBc
68
70.7
69.5
67.5
70.3
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
fIN = 32.5MHz
fIN = 70MHz
fIN = 5MHz
67.5
SINAD Signal-to-Noise and Distortion
Crosstalk
fIN = 32.5MHz
fIN = 70MHz
67
5MHz Full-Scale Signal Applied to 1 Channel;
Measurement Taken on the Channel with No Input Signal
–85
dBc
f1 = 4MHz at –7dBFS
f2 = 5MHz at –7dBFS
Two-Tone, Third-Order
IMD3
90.9
dBFS
Intermodulation Distortion
TIMING DIAGRAM
tA
N + 2
N + 4
N
Analog
Input
N + 3
N + 1
tC
CLK
t1
t2
DATA[D11:D0]
tDV
DV
OE
tOE
tOE
D11:D0
DATA
6
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SBAS295A–JULY 2004–REVISED JANUARY 2007
TIMING CHARACTERISTICS(1)
Typical values at TA = +25°C, AVDD = VDRV = 3.3V, sampling rate and PLL state are as indicated, input clock at 50% duty
cycle, and total capacitive loading = 10pF, unless otherwise noted.
PARAMETER
MIN
TYP
MAX
UNITS
40MSPS With PLL ON
tA Aperture Delay
Aperture Jitter
2.1
1.0
5.5
13.5
6
ns
ps
t1 Data Setup Time(2)
t2 Data Hold Time(3)
3.7
ns
11.5
ns
tD Data Latency
Clocks
ns
tDR, tDF Data Rise/Fall Time(4)
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3
30
13.5
40
16
55
%
18.5
ns
30MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
2.1
1.0
10
19
6
ns
ps
t1 Data Setup Time
8
ns
t2 Data Hold Time
14
ns
tD Data Latency
Clocks
ns
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3.5
55
21
30
16
45
19
%
ns
20MSPS With PLL ON
tA Aperture Delay
Aperture Jitter
2.1
1.0
12
25
6
ns
ps
t1 Data Setup Time
10
20
ns
t2 Data Hold Time
ns
tD Data Latency
Clocks
ns
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3.5
55
30
30
20
45
25
%
ns
20MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
2.1
1.0
12
25
6
ns
ps
t1 Data Setup Time
10
20
ns
t2 Data Hold Time
ns
tD Data Latency
Clocks
ns
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
2
3.5
55
30
30
20
45
25
%
ns
2MSPS With PLL OFF
tA Aperture Delay
Aperture Jitter
2.1
1.0
200
250
6
ns
ps
t1 Data Setup Time
150
200
ns
t2 Data Hold Time
ns
tD Data Latency
Clocks
ns
tDR, tDF Data Rise/Fall Time
Data Valid (DV) Duty Cycle
tDV Input Clock Rising to DV Fall Edge
0.5
30
2
3.5
55
45
%
200
225
250
ns
(1) Specifications assured by design and characterization; not production tested.
(2) Measured from data becoming valid (at a high level = 2.0V and a low level = 0.8V) to the 50% point of the falling edge of DV.
(3) Measured from the 50% point of the falling edge of DV to the data becoming invalid.
(4) Measured between 20% to 80% of logic levels.
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SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after SEN goes high.
CLK
SEN
Start Sequence
t6
t1
t7
Data latched on
t2
each rising edge of SCLK.
SCLK
t3
D7
SDATA
D6
D5
D4
D3
D2
D1
D0
(MSB)
t4
t5
NOTE: Data is shifted in MSB first.
PARAMETER
DESCRIPTION
Serial CLK Period
MIN
50
20
20
5
TYP
MAX
UNIT
t1
t2
t3
t4
t5
t6
t7
ns
ns
ns
ns
ns
ns
ns
Serial CLK High Time
Serial CLK Low Time
Data Setup Time
Data Hold Time
5
SEN Fall to SCLK Rise
SCLK Rise to SEN Rise
8
8
8
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SERIAL REGISTER MAP: Shown for the Case Where Serial Interface is Used(1)
ADDRESS
D6 D5
DATA
DESCRIPTION
D7
D4
0
D3
X
D2
X
D1
X
D0
0
0
0
0
0
0
0
Normal Mode
0
X
X
X
1
Power-Down Both Channels
0
0
0
0
0
0
0
0
X
X
X
X
0
1
X
X
Straight Offset Binary Output
Binary Two's Complement Output
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
1
X
X
X
X
X
X
X
X
Channel B Digital Outputs Enabled
Channel B Digital Outputs Tri-Stated
Channel A Digital Outputs Enabled
Channel A Digital Outputs Tri-Stated
X
X
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
Normal Mode
All Digital Outputs Set to '1'
All Digital Outputs Set to '0'
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
X
1
X
X
X
0
0
0
Normal Mode
Channel A Powered Down
Channel B Powered Down
X
0
0
0
0
1
1
1
1
X
X
X
X
0
1
0
0
PLL Enabled (default)
PLL Disabled
(1) X = don't care.
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SBAS295A–JULY 2004–REVISED JANUARY 2007
RECOMMENDED POWER-UP SEQUENCING
Shown for the case where the serial interface is used.
AVDD (3V to 3.6V)
VDRV (3V to 3.6V)
t1
AVDD
t2
VDRV
Device Ready
For ADC Operation
t3
t4
t7
t5
t6
SEL
SEN
Device Ready
For Serial Register Write
Device Ready
For ADC Operation
Start of Clock
CLK
t8
NOTE: 10ms < t1 < 50ms; 10ms < t2 < 50ms; -10ms < t3 < 10ms; t4 > 10ms; t5 > 100ns; t6 > 100ns; t7 > 10ms; and t8 > 100ms.
POWER-DOWN TIMING
1ms
500ms
STPD
Device Fully
Powers Down
Device Fully
Powers Up
NOTE: The shown power-up time is based on 1mF bypass capacitors on the reference pins.
See the Theory of Operation section for details.
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SBAS295A–JULY 2004–REVISED JANUARY 2007
PIN CONFIGURATION
Top View
TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
SEL
AGND
AVDD
GND
1
2
3
4
5
6
7
8
9
48 AGND
47 AGND
46 AVDD
45 STPD/SDATA
44 GND
VDRV
OEB
43 VDRV
GND
42 OEA/SCLK
41 MSBI/SEN
40 VDRV
VDRV
OVRB
ADS5231
D0_B (LSB) 10
D1_B 11
D2_B 12
D3_B 13
D4_B 14
D5_B 15
D6_B 16
39 OVRA
38 D11_A (MSB)
37 D10_A
36 D9_A
35 D8_A
34 D7_A
33 D6_A
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN DESCRIPTIONS
NAME
AGND
AVDD
PIN #
I/O
DESCRIPTION
2, 47–49, 55, 58, 59, 61, 64
Analog Ground
3, 46, 57
24
Analog Supply
CLK
I
Clock Input
CM
52
Common-Mode Voltage Output
Data Bit 12 (D0), Channel A
Data Bit 11 (D1), Channel A
Data Bit 10 (D2), Channel A
Data Bit 9 (D3), Channel A
Data Bit 8 (D4), Channel A
Data Bit 7 (D5), Channel A
Data Bit 6 (D6), Channel A
Data Bit 5 (D7), Channel A
Data Bit 4 (D8), Channel A
Data Bit 3 (D9), Channel A
Data Bit 2 (D10), Channel A
Data Bit 1 (D11), Channel A
Data Bit 12 (D0), Channel B
D0_A (LSB)
D1_A
27
O
O
O
O
O
O
O
O
O
O
O
O
O
28
D2_A
29
D3_A
30
D4_A
31
D5_A
32
D6_A
33
D7_A
34
D8_A
35
D9_A
36
D10_A
D11_A (MSB)
D0_B (LSB)
37
38
10
11
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PIN DESCRIPTIONS (continued)
NAME
D1_B
D2_B
D3_B
D4_B
D5_B
D6_B
D7_B
D8_B
D9_B
D10_B
D11_B (MSB)
DVA
PIN #
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
DESCRIPTION
11
Data Bit 11 (D1), Channel B
Data Bit 10 (D2), Channel B
Data Bit 9 (D3), Channel B
Data Bit 8 (D4), Channel B
Data Bit 7 (D5), Channel B
Data Bit 6 (D6), Channel B
Data Bit 5 (D7), Channel B
Data Bit 4 (D8), Channel B
Data Bit 3 (D9), Channel B
Data Bit 2 (D10), Channel B
Data Bit 1 (D11), Channel B
Data Valid, Channel A
12
13
14
15
16
17
18
19
20
21
26
DVB
22
Data Valid, Channel B
GND
4, 7, 23, 25, 44
Output Buffer Ground
INA
50
51
63
62
I
I
I
I
Analog Input, Channel A
IN A
Complementary Analog Input, Channel A
Analog Input, Channel B
INB
IN B
Complementary Analog Input, Channel B
Reference Select; 0 = External (Default), 1 = Internal; Force high to set for internal reference
operation.
INT/EXT
ISET
56
60
I
O
Bias Current Setting Resistor of 56.2kΩ to Ground
When SEL = 0, MSBI (Most Significant Bit Invert)
1 = Binary Two's Complement, 0 = Straight Offset Binary (Default)
When SEL = 1, SEN (Serial Write Enable)
MSBI/SEN
OEA/SCLK
41
42
I
I
When SEL = 0, OEA (Output Enable Channel A)
0 = Enabled (Default), 1 = Tri-State
When SEL = 1, SCLK (Serial Write Clock)
OE B
OVRA
OVRB
REFB
REFT
6
I
Output Enable, Channel B (0 = Enabled [Default], 1 = Tri-State)
Over-Range Indicator, Channel A
39
9
O
O
Over-Range Indicator, Channel B
54
53
I/O
I/O
Bottom Reference/Bypass (2Ω resistor in series with a 0.1µF capacitor to ground)
Top Reference/Bypass (2Ω resistor in series with a 0.1µF capacitor to ground)
Serial interface select signal. Setting SEL = 0 configures pins 41, 42, and 45 as MSBI, OEA, and
STPD, respectively. With SEL = 0, the serial interface is disabled. Setting SEL = 1 enables the serial
interface and configures pins 41, 42, and 45 as SEN, SCLK, and SDATA, respectively. Serial
registers can be programmed using these three signals. When used in this mode of operation, it is
essential to provide a low-going pulse on SEL in order to reset the serial interface registers as soon
as the device is powered up. SEL therefore also has the functionality of a RESET signal.
SEL
1
I
I
When SEL = 0, STPD (Power-Down)
0 = Normal Operation (Default), 1 = Enabled
When SEL = 1, SDATA (Serial Write Data)
STPD/SDATA
VDRV
45
5, 8, 40, 43
Output Buffer Supply
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DEFINITION OF SPECIFICATIONS
Minimum Conversion Rate
Analog Bandwidth
This is the minimum sampling rate where the ADC
still works.
The analog input frequency at which the spectral
power of the fundamental frequency (as determined
by FFT analysis) is reduced by 3dB.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral
components including noise (PN) and distortion (PD),
but not including dc.
PS
SINAD + 10Log
10 PN ) PD
Aperture Delay
The delay in time between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
Aperture Uncertainty (Jitter)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
The sample-to-sample variation in aperture delay.
Clock Duty Cycle
Pulse width high is the minimum amount of time that
the ADCLK pulse should be left in logic ‘1’ state to
achieve rated performance. Pulse width low is the
minimum time that the ADCLK pulse should be left in
a low state (logic ‘0’). At a given clock rate, these
specifications define an acceptable clock duty cycle.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and the first eight harmonics.
PS
SNR + 10Log
10 PN
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are
exactly 1 LSB apart. DNL is the deviation of any
single LSB transition at the digital output from an
ideal 1 LSB step at the analog input. If a device
claims to have no missing codes, it means that all
possible codes (for a 12-bit converter, 4096 codes)
are present over the full operating range.
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
full-scale range of the converter.
Spurious-Free Dynamic Range
Effective Number of Bits (ENOB)
The ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc
(dB to carrier).
The ENOB is a measure of converter performance
as compared to the theoretical limit based on
quantization noise.
SINAD * 1.76
ENOB +
6.02
Two-Tone, Third-Order Intermodulation
Distortion
Integral Nonlinearity (INL)
Two-tone IMD3 is the ratio of power of the
fundamental (at frequencies f1 and f2) to the power of
the worst spectral component of third-order
intermodulation distortion at either frequency 2f1 – f2
or 2f2 – f1. IMD3 is either given in units of dBc (dB to
carrier) when the absolute power of the fundamental
is used as the reference, or dBFS (dB to full-scale)
when the power of the fundamental is extrapolated to
the full-scale range of the converter.
INL is the deviation of the transfer function from a
reference line measured in fractions of 1 LSB using a
best straight line or best fit determined by a least
square curve fit. INL is independent from effects of
offset, gain or quantization errors.
Maximum Conversion Rate
The encode rate at which parametric testing is
performed. This is the maximum sampling rate where
certified operation is given.
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TYPICAL CHARACTERISTICS
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
-20
0
-20
fIN = 1MHz
fIN = 5MHz
SNR = 71.4dBFS
SINAD = 71.3dBFS
SFDR = 88.8dBFS
SNR = 71.3dBFS
SINAD = 71.1dBFS
SFDR = 87.8dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
0
0
4
8
12
16
20
0
4
8
12
16
20
Input Frequency (MHz)
Input Frequency (MHz)
Figure 1.
Figure 2.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
-20
0
-20
fIN = 20MHz
fIN = 70MHz
SNR = 70.9dBFS
SINAD = 70.7dBFS
SFDR = 85.9dBFS
SNR = 67.9dBFS
SINAD = 67.7dBFS
SFDR = 82.8dBFS
-40
-40
-60
-60
-80
-80
-100
-120
-100
-120
4
8
12
16
20
0
4
8
12
16
20
Input Frequency (MHz)
Input Frequency (MHz)
Figure 3.
Figure 4.
INTERMODULATION DISTORTION
DIFFERENTIAL NONLINEARITY
0.5
0.4
0
-20
fIN = 5MHz
f1 = 4MHz (-7dBFS)
f2 = 5MHz (-7dBFS)
IMD = -89.6dBFS
0.3
0.2
-40
0.1
-60
0
-0.1
-0.2
-0.3
-0.4
-0.5
-80
-100
-120
0
1024
2048
Code
3072
4096
4
8
12
16
20
Input Frequency (MHz)
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
INTEGRAL NONLINEARITY
IAVDD, IVDRV vs CLOCK FREQUENCY
1.00
0.75
0.50
0.25
0
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
fIN = 5MHz
fIN = 5MHz
IAVDD
-0.25
-0.50
-0.75
-1.00
IVDRV
0
1024
2048
Code
3072
4096
20
25
30
35
40
45
50
Sample Rate (MHz)
Figure 7.
Figure 8.
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
95
110
100
90
fIN = 5MHz
90
85
80
75
70
65
60
55
SFDR
SFDR
80
SNR
70
SNR
60
SINAD
50
40
30
20
25
30
35
40
45
50
55
60
65
70
0
20
40
60
80
100
Clock Frequency (MHz)
Input Frequency (MHz)
Figure 9.
Figure 10.
DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE
WITH PLL ENABLED (default)
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
110
100
90
95
External Reference:
REFT = 2V
fIN = 5MHz
90
85
80
75
70
65
60
REFB = 1V
SFDR
SNR
SFDR
80
70
SNR
60
50
40
30
0
20
40
60
80
100
30
35
40
45
50
55
60
65
70
Input Frequency (MHz)
Duty Cycle (%)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
TMIN = –40°C and TMAX = +85°C. Typical values are at TA = +25°C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, VDRV = 3.3V, transformer-coupled inputs, –1dBFS, ISET = 56.2kΩ, and internal voltage reference, unless
otherwise noted.
DYNAMIC PERFORMANCE vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
95
90
85
80
75
70
65
60
55
340
335
330
325
320
315
310
fIN = 5MHz
fIN = 5MHz
SFDR
SNR
-40
-15
+10
+35
+60
+85
-40
-15
+10
+35
+60
+85
Temperature (°C)
Temperature (°C)
Figure 13.
Figure 14.
OUTPUT NOISE
SWEPT INPUT POWER
4000
3500
3000
2500
2000
1500
1000
500
100
90
80
70
60
50
40
30
20
10
0
fIN = 5MHz
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
0
-70
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Code
Figure 15.
Figure 16.
SWEPT INPUT POWER
100
90
80
70
60
50
40
30
20
10
0
fIN = 20MHz
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
-70
-60
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Figure 17.
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APPLICATION INFORMATION
INPUT CONFIGURATION
THEORY OF OPERATION
The ADS5231 is
a
dual-channel, simultaneous
The analog input for the ADS5231 consists of a
differential sample-and-hold architecture
sampling analog-to-digital converter (ADC). Its low
power and high sampling rate of 40MSPS is
achieved using a state-of-the-art switched capacitor
pipeline architecture built on an advanced
low-voltage CMOS process. The ADS5231 operates
from a +3.3V supply voltage for both its analog and
digital supply connections. The ADC core of each
channel consists of a combination of multi-bit and
single-bit internal pipeline stages. Each stage feeds
its data into the digital error correction logic, ensuring
excellent differential linearity and no missing codes
at the 12-bit level. The conversion process is initiated
by the rising edge of the external clock. Once the
signal is captured by the input sample-and-hold
amplifier, the input sample is sequentially converted
within the pipeline stages. This process results in a
data latency of six clock cycles, after which the
output data is available as a 12-bit parallel word,
coded in either straight offset binary (SOB) or binary
two's complement (BTC) format. Since a common
clock controls the timing of both channels, the analog
signal is sampled simultaneously. The data on the
parallel ports is updated simultaneously as well.
Further processing can be timed using the individual
data valid output signal of each channel. The
ADS5231 features internal references that are
trimmed to ensure a high level of accuracy and
matching. The internal references can be disabled to
allow for external reference operation.
implemented using a switched capacitor technique;
see Figure 18. The sampling circuit consists of a
low-pass RC filter at the input to filter out noise
components that potentially could be differentially
coupled on the input pins. The inputs are sampled on
two 4pF capacitors. The RLC model is illustrated in
Figure 18.
INPUT DRIVER CONFIGURATIONS
Transformer-Coupled Interface
If the application requires a signal conversion from a
single-ended source to drive the ADS5231
differentially, an RF transformer could be a good
solution. The selected transformer must have a
center tap in order to apply the common-mode dc
voltage (VCMV) necessary to bias the converter
inputs. AC grounding the center tap will generate the
differential signal swing across the secondary
winding. Consider a step-up transformer to take
advantage of signal amplification without the
introduction of another noise source. Furthermore,
the reduced signal swing from the source may lead
to improved distortion performance. The differential
input configuration may provide
a
noticeable
advantage for achieving good SFDR performance
over a wide range of input frequencies. In this mode,
both inputs (IN and IN) of the ADS5231 see matched
impedances.
Figure 19 illustrates the schematic for the suggested
transformer-coupled interface circuit. The component
values of the RC low-pass filter may be optimized
depending on the desired roll-off frequency.
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IN
OUT
5nH
to 9nH
INP
1.5pF to
3.2pF
2.5pF
15W
15W
60W
to 4.8pF
to 25W
to 25W
to 120W
1W
IN
OUT
IN
OUT
OUT
OUTP
OUTN
1.5pF
to 1.9pF
IN
15W to 35W
3.2pF
15W
15W
60W
to 4.8pF
to 25W
to 25W
to 120W
IN
OUT
IN
OUT
5nH
to 9nH
INN
1.5pF to
2.5pF
Switches that are ON
in SAMPLE phase.
1W
Switches that are ON
in HOLD phase.
IN
OUT
Figure 18. Input Circuitry
RG
µ
0.1
F
VIN
Ω
49.9
Ω
24.9
1:n
IN
IN
OPA690
1/2
R1
RT 22pF
ADS5231
Ω
24.9
CM
+1.5V
R2
µ
0.1
F
One Channel of Two
Figure 19. Converting a Single-Ended Input Signal into a Differential Signal Using an RF-Transformer
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DC-Coupled Input with Differential Amplifier
REFERENCE CIRCUIT
Applications that have a requirement for DC-coupling
a differential amplifier, such as the THS4503, can be
used to drive the ADS5231; this design is shown in
Figure 20. The THS4503 amplifier easily allows a
single-ended to differential conversion, which
reduces component cost.
Internal Reference
All bias currents required for the proper operation of
the ADS5231 are set using an external resistor at
ISET (pin 60), as shown in Figure 21. Using a 56.2kΩ
resistor on ISET generates an internal reference
current of about 20µA. This current is mirrored
internally to generate the bias current for the internal
blocks. While a 5% resistor tolerance is adequate,
deviating from this resistor value alters and degrades
device performance. For example, using a larger
external resistor at ISET reduces the reference bias
current and thereby scales down the device
operating power.
CF
RS
RG
RF
+5V
AVDD
RT
VS
µ
10
µ
0.1 F
F
RISO
IN
IN
1/2
ADS5231
VOCM
THS4503
RISO
1µF
CM
RG
RF
CF
AVDD
ADS5231
INT/EXT
ISET
0.1µF
56.2kW
REFT
CM
REFB
Figure 20. Using the THS4503 with the ADS5231
2W
2W
In addition, the VOCM pin on the THS4503 can be
directly tied to the common-mode pin (CM) of the
ADS5231 to set up the necessary bias voltage for
the converter inputs. In the circuit example shown in
Figure 20, the THS4503 is configured for unity gain.
If required, a higher gain can easily be achieved as
well by adding small capacitors (such as 10pF) in
parallel with the feedback resistors to create a
low-pass filter. Since the THS4503 is driving a
capacitive load, small series resistors in the output
ensure stable operation. Further details of this and
the overall operation of the THS4503 may be found
in its product data sheet (available for download at
www.ti.com). In general, differential amplifiers
+
+
0.1mF
2.2mF
2.2mF
0.1mF
Figure 21. Internal Reference Circuit
As part of the internal reference circuit, the ADS5231
provides a common-mode voltage output at pin 52,
CM. This common-mode voltage is typically +1.5V.
While this is similar to the common-mode voltage
used internally within the ADC pipeline core, the
CM-pin has an independent buffer amplifier, which
can deliver up to ±2mA of current to an external
circuit for proper input signal level shifting and
biasing. In order to obtain optimum dynamic
performance, the analog inputs should be biased to
the recommended common-mode voltage (1.5V).
While good performance can be maintained over a
certain CM-range, larger deviations may compromise
device performance and could also negatively affect
the overload recovery behavior. Using the internal
reference mode requires the INT/EXT pin to be
forced high, as shown in Figure 21.
provide
a high-performance driver solution for
baseband applications, and other differential
amplifier models may be selected depending on the
system requirements.
Input Over-Voltage Recovery
The differential full-scale input range supported by
the ADS5231 is 2VPP. For a nominal value of VCM
(+1.5V), IN and IN can swing from 1V to 2V. The
ADS5231 is especially designed to handle an
over-voltage differential peak-to-peak voltage of 4V
(2.5V and 0.5V swings on IN and IN). If the input
common-mode voltage is not considerably different
from VCM during overload (less than 300mV),
recovery from an over-voltage input condition is
expected to be within three clock cycles. All of the
amplifiers in the sample-and-hold stage and the ADC
core are especially designed for excellent recovery
from an overload signal.
The ADS5231 requires solid high-frequency
bypassing on both reference pins, REFT and REFB;
see Figure 21. Use ceramic 0.1µF capacitors (size
0603, or smaller), located as close as possible to the
pins.
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External Reference
maintaining a good signal-to-noise ratio (SNR). This
condition is particularly critical in IF-sampling
applications; for example, where the sampling
frequency is lower than the input frequency
(under-sampling). The following equation can be
used to calculate the achievable SNR for a given
input frequency and clock jitter (tJA in psRMS):
The ADS5231 also supports the use of external
reference voltages. External reference voltage mode
involves applying an external top reference at REFT
(pin 53) and a bottom reference at REFB (pin 54).
Setting the ADS5231 for external reference mode
also requires taking the INT/EXT pin low. In this
mode, the internal reference buffer is tri-stated. Since
the switching current for the two ADC channels
comes from the externally-forced references, it is
possible for the device performance to be slightly
lower than when the internal references are used. It
should be noted that in external reference mode, VCM
and ISET continue to be generated from the internal
bandgap voltage, as they are in the internal
reference mode. Therefore, it is important to ensure
1
SNR + 20LOG10
ǒ
Ǔ
2pfIN tJA
(1)
The ADS5231 will enter into a power-down mode if
the sampling clock rate drops below a limit of
approximately 2MSPS. If the sampling rate is
increased above this threshold, the ADS5231 will
automatically resume normal operation.
PLL CONTROL
that
the
common-mode
voltage
of
the
externally-forced reference voltages matches to
within 50mV of VCM (+1.5VDC).
The ADS5231 has an internal PLL that is enabled by
default. The PLL enables a wide range of clock duty
cycles. Good performance is obtained for duty cycles
up to 40%–60%, though the ensured electrical
specifications presume that the duty cycle is between
45%–55%. The PLL automatically limits the minimum
frequency of operation to 20MSPS. For operation
below 20MSPS, the PLL can be disabled by
programming the internal registers through the serial
interface. With the PLL disabled, the clock speed can
go down to 2MSPS. With the PLL disabled, the clock
duty cycle needs to be constrained closer to 50%.
The external reference circuit must be designed to
drive the internal reference impedance seen between
the REFT and REFB pins. To establish the drive
requirements, consider that the external reference
circuit needs to supply an average switching current
of at least 1mA. This dynamic switching current
depends on the actual device sampling rate and the
signal level. The external reference voltages can
vary as long as the value of the external top
reference stays within the range of +1.875V to
+2.0V, and the external bottom reference stays
within +1.0V to +1.125V. Consequently, the full-scale
input range can be set between 1.5VPP and 2VPP
(FSR = 2x [REFT – REFB] ).
OUTPUT INFORMATION
The ADS5231 provides two channels with 12 data
outputs (D11 to D0, with D11 being the MSB and D0
the LSB), data-valid outputs (DVA, DVB, pin 26 and
pin 22, respectively), and individual out-of-range
indicator output pins (OVRA/OVRB, pin 39 and pin 9,
respectively).
CLOCK INPUT
The ADS5231 requires a single-ended clock source.
The
clock
input,
CLK,
represents
a
CMOS-compatible logic input with an input
impedance of about 5pF. For high input frequency
sampling, it is recommended to use a clock source
with very low jitter. A low-jitter clock is essential in
order to preserve the excellent ac performance of the
ADS5231. The converter itself is specified for a low
1.0ps (rms) jitter. Generally, as the input frequency
increases, clock jitter becomes more dominant in
The output circuitry of the ADS5231 has been
designed to minimize the noise produced by
transients of the data switching, and in particular its
coupling to the ADC analog circuitry.
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DATA OUTPUT FORMAT (MSBI)
range. It will change to high if the applied signal
exceeds the full-scale range. It should be noted that
each of the OVR outputs is updated along with the
data output corresponding to the particular sampled
analog input voltage. Therefore, the OVR state is
subject to the same pipeline delay as the digital data
(six clock cycles).
The ADS5231 makes two data output formats
available: the Straight Offset Binary code (SOB) or
the Binary Two's Complement code (BTC). The
selection of the output coding is controlled by the
MSBI (pin 41). Because the MSBI pin has an internal
pull-down, the ADS5231 will operate with the SOB
code as its default setting. Forcing the MSBI pin high
will enable BTC coding. The two code structures are
identical, with the exception that the MSB is inverted
for BTC format; as shown in Table 1.
OUTPUT LOADING
It is recommended that the capacitive loading on the
data output lines be kept as low as possible,
preferably below 15pF. Higher capacitive loading will
cause larger dynamic currents as the digital outputs
are changing. Such high current surges can feed
back to the analog portion of the ADS5231 and
adversely affect device performance. If necessary,
external buffers or latches close to the converter
output pins may be used to minimize the capacitive
loading.
OUTPUT ENABLE (OE)
Digital outputs of the ADS5231 can be set to
high-impedance (tri-state), exercising the output
enable pins, OEA (pin 42), and OEB (pin 6). Internal
pull-downs configure the output in enable mode for
normal operation. Applying a logic high voltage will
disable the outputs. Note that the OE-function is not
designed to be operated dynamically (that is, as a
fast multiplexer) because it may lead to corrupt
conversion results. Refer to the Electrical
Characteristics table to observe the specified tri-state
enable and disable times.
SERIAL INTERFACE
The ADS5231 has a serial interface that can be used
to program internal registers. The serial interface is
disabled if SEL is connected to 0.
When the serial interface is to be enabled, SEL
serves the function of a RESET signal. After the
supplies have stabilized, it is necessary to give the
device a low-going pulse on SEL. This results in all
internal registers resetting to their default value of 0
(inactive). Without a reset, it is possible that registers
may be in their non-default state on power-up. This
condition may cause the device to malfunction.
OVER-RANGE INDICATOR (OVR)
If the analog input voltage exceeds the full-scale
range set by the reference voltages, an over-range
condition exists. The ADS5231 incorporates
function that monitors the input voltage and detects
any such out-of-range condition. This operation
functions for each of the two channels independently.
The current state can be read at the over-range
indicator pins (pins 9 and 39). This output is low
when the input voltage is within the defined input
a
Table 1. Coding Table for Differential Input Configuration and 2VPP Full-Scale Input Range
STRAIGHT OFFSET BINARY (SOB; MSBI = 0) BINARY TWO'S COMPLEMENT (BTC; MSBI = 1)
DIFFERENTIAL INPUT
+FS (IN = +2V, IN = +1V)
+1/2 FS
D11............D0
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
D11............D0
0111 1111 1111
0100 0000 0000
0000 0000 0000
1100 0000 0000
1000 0000 0000
Bipolar Zero (IN = IN = CMV)
–1/2 FS
–FS (IN = +1V, IN = +2V)
21
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ADS5231
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SBAS295A–JULY 2004–REVISED JANUARY 2007
POWER-DOWN MODE
For capacitances on REFT and REFB less than 1µF,
the reference voltages settle to within 1% of their
steady-state values in less than 500µs. Either of the
two channels can also be selectively powered-down
through the serial interface when it is enabled.
The ADS5231 has a power-down pin, STPD (pin 45).
The internal pull-down is in default mode for the
device during normal operation. Forcing the STPD
pin high causes the device to enter into power-down
mode. In power-down mode, the reference and clock
circuitry as well as all the channels are powered
down. Device power consumption drops to less than
90mW. As previously mentioned, the ADS5231 also
enters into a power-down mode if the clock speed
drops below 2MSPS (see the Clock Input section).
The ADS5231 also has an internal circuit that
monitors the state of stopped clocks. If ADCLK is
stopped for longer than 250ns, or if it runs at a speed
less than 2MHz, this monitoring circuit generates a
logic signal that puts the device in
power-down state. As result, the power
consumption of the device is reduced when CLK is
stopped. The recovery from such partial
a partial
a
When STPD is pulled high, the internal buffers
driving REFT and REFB are tri-stated and the outputs
are forced to a voltage roughly equal to half of the
voltage on AVDD. Speed of recovery from the
power-down mode depends on the value of the
external capacitance on the REFT and REFB pins.
a
power-down takes approximately 100µs. This
constraint is described in Table 2.
Table 2. Time Constraints Associated with Device Recovery from Power-Down and Clock Stoppage
DESCRIPTION
TYP
500µs
10µs
REMARKS
Recovery from power-down mode (STPD = 1 to STPD = 0).
Recovery from momentary clock stoppage ( < 250ns).
Recovery from extended clock stoppage ( > 250ns).
Capacitors on REFT and REFB less than 1µF.
100µs
22
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ADS5231
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SBAS295A–JULY 2004–REVISED JANUARY 2007
LAYOUT AND DECOUPLING
CONSIDERATIONS
on the output buffer supply pins, VDRV. In order to
minimize the lead and trace inductance, the
capacitors should be located as close to the supply
pins as possible. Where double-sided component
mounting is allowed, they are best placed directly
under the package. In addition, larger bipolar
decoupling capacitors (2.2µF to 10µF), effective at
lower frequencies, may also be used on the main
supply pins. They can be placed on the PCB in
proximity (< 0.5") to the ADC.
Proper grounding and bypassing, short lead length,
and the use of ground planes are particularly
important for high-frequency designs. Achieving
optimum performance with a fast sampling converter
such as the ADS5231 requires careful attention to
the printed circuit board (PCB) layout to minimize the
effects of board parasitics and to optimize
component placement. A multilayer board usually
ensures best results and allows convenient
component placement.
If the analog inputs to the ADS5231 are driven
differentially, it is especially important to optimize
towards a highly symmetrical layout. Small trace
length differences may create phase shifts,
compromising a good distortion performance. For
this reason, the use of two single op amps rather
than one dual amplifier enables a more symmetrical
layout and a better match of parasitic capacitances.
The pin orientation of the ADS5231 quad-flat
package follows a flow-through design, with the
analog inputs located on one side of the package
while the digital outputs are located on the opposite
side. This design provides a good physical isolation
between the analog and digital connections. While
designing the layout, it is important to keep the
analog signal traces separated from any digital lines
to prevent noise coupling onto the analog portion.
The ADS5231 should be treated as an analog
component and the supply pins connected to clean
analog supplies. This layout ensures the most
consistent performance results, since digital supplies
often carry a high level of switching noise, which
could couple into the converter and degrade device
performance. As mentioned previously, the output
buffer supply pins (VDRV) should also be connected
to a low-noise supply. Supplies of adjacent digital
circuits may carry substantial current transients. The
supply voltage should be filtered before connecting
to the VDRV pin of the converter. All ground pins
should directly connect to an analog ground.
Because of its high sampling frequency, the
ADS5231
generates
high-frequency
current
Single-ended clock lines must be short and should
not cross any other signal traces.
transients and noise (clock feed-through) that are fed
back into the supply and reference lines. If not
sufficiently bypassed, this feed-through adds noise to
the conversion process. All AVDD pins may be
bypassed with 0.1µF ceramic chip capacitors (size
0603, or smaller). A similar approach may be used
Short circuit traces on the digital outputs will
minimize capacitive loading. Trace length should be
kept short to the receiving gate (< 2") with only one
CMOS gate connected to one digital output.
23
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ADS5231IPAG
ADS5231IPAGT
ACTIVE
ACTIVE
TQFP
TQFP
PAG
PAG
64
64
160
250
RoHS & Green
RoHS & Green
NIPDAU
Level-4-260C-72 HR
Level-4-260C-72 HR
-40 to 85
-40 to 85
ADS5231IPAG
ADS5231IPAG
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TRAY
Chamfer on Tray corner indicates Pin 1 orientation of packed units.
*All dimensions are nominal
Device
Package Package Pins SPQ Unit array
Max
matrix temperature
(°C)
L (mm)
W
K0
P1
CL
CW
Name
Type
(mm) (µm) (mm) (mm) (mm)
ADS5231IPAG
PAG
TQFP
64
160
8 x 20
150
315 135.9 7620 15.2
13.1
13
Pack Materials-Page 1
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
M
0,08
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
11,80
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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