ADS5275 [TI]
8-Channel, 10-Bit, 40MSPS ADC with Serial LVDS Interface; 8通道， 10位， 40MSPS ADC，具有串行LVDS接口
| 型号： | ADS5275 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Channel, 10-Bit, 40MSPS ADC with Serial LVDS Interface |
| 文件： | 总20页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
B
u
r
r
Ć
B
r
o
w
n
P
r
o
d
u
c
t
s
ADS5275
f
r
o
m
T
e
x
a
s
I
n
s
t
r
u
m
e
n
t
s
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
8-Channel, 10-Bit, 40MSPS ADC
with Serial LVDS Interface
The ADS5275 provides internal references, or can
FEATURES
optionally be driven with external references. Best
performance can be achieved through the internal
reference mode.
•
•
•
•
•
•
•
•
Maximum Sample Rate: 40MSPS
10-Bit Resolution
No Missing Codes
The ADS5275 is available in a PowerPAD TQFP-80
package and are specified over a -40°C to +85°C
operating range.
Power Dissipation: 768mW
CMOS Technology
Simultaneous Sample-and-Hold
60.5dB SNR at 10MHz IF
LCLKP
6X ADCLK
LCLKN
Serialized LVDS Outputs Meet or Exceed
Requirements of ANSI TIA/EIA-644-A Standard
PLL
ADCLKP
ADCLKN
1X ADCLK
ADCLK
•
•
•
Internal and External References
3.3V Digital/Analog Supply
IN1P
IN1N
OUT1P
OUT1N
10−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
Serializer
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
TQFP-80 PowerPAD™ Package
IN2P
IN2N
OUT2P
OUT2N
10−Bit
ADC
APPLICATIONS
•
•
•
Portable Ultrasound Systems
Tape Drives
Test Equipment
IN3P
IN3N
OUT3P
OUT3N
10−Bit
ADC
IN4P
IN4N
OUT4P
OUT4N
10−Bit
ADC
DESCRIPTION
IN5P
IN5N
OUT5P
OUT5N
10−Bit
ADC
The ADS5275 is
a high-performance, 40MSPS,
8-channel, parallel analog-to-digital converter (ADC).
Internal references are provided, simplifying system
design requirements. Low power consumption allows
for the highest of system integration densities. Serial
LVDS (low-voltage differential signaling) outputs re-
duce the number of interface lines and package size.
IN6P
IN6N
OUT6P
OUT6N
10−Bit
ADC
IN7P
IN7N
OUT7P
OUT7N
10−Bit
ADC
IN8P
IN8N
OUT8P
OUT8N
In LVDS, an integrated phase lock loop multiplies the
incoming ADC sampling clock by a factor of 6. This
high-frequency LVDS clock is used in the data
serialization and transmission process and is con-
verted to an LVDS signal for transmission in parallel
with the data. Providing this additional LVDS clock
allows for easy delay matching. The word output of
each internal ADC is serialized and transmitted either
MSB or LSB first. The bit following the rising edge of
the ADC clock output is the first bit of the word.
10−Bit
ADC
Serializer
Control
Registers
Reference
INT/EXT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the forma-
Copyright © 2004, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS5275IPFP
Tray, 96
ADS5275
HTQFP-80
PFP
-40°C to +85°C
ADS5275IPFP
ADS5275IPFPT Tape and Reel, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage Range, AVDD
-0.3V to +3.8V
Supply Voltage Range, LVDD
-0.3V to +3.8V
-0.3V to +0.3V
-0.3V to +0.3V
-0.3V to +2.4V
-0.3V to +2.4V
-0.3V to +2.7V
-30mA
Voltage Between AVSS and LVSS
Voltage Between AVDD and LVDD
Voltage Applied to External REF Pins
All LVDS Data and Clock Outputs
Analog Input Pins
Peak Total Input Current (all inputs)
Operating Free-Air Temperature Range, TA
Lead Temperature, 1.6mm (1/16" from case for 10s)
-40°C to +85°C
220°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
RELATED PRODUCTS
MODEL
ADS5270
ADS5271
ADS5272
ADS5273
ADS5276
ADS5277
RESOLUTION (BITS)
SAMPLE RATE (MSPS)
CHANNELS
12
12
12
12
10
10
40
50
65
70
50
65
8
8
8
8
8
8
2
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
RECOMMENDED OPERATING CONDITIONS
ADS5275
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
Output Driver Supply Voltage, LVDD
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL), 1/tC
Low-Level Voltage Clock Input
High-Level Voltage Clock Input
ADCLKP and ADCLKN Outputs (LVDS)
LCLKP and LCLKN Outputs (LVDS)(1)
Operating Free-Air Temperature, TA
Thermal Characteristics:
3.0
3.0
3.3
3.3
3.6
3.6
V
V
20
40
1
MSPS
V
2
V
20
120
-40
40
240
+85
MHz
MHz
°C
θJA
21
68
°C/W
°C/W
θJC
(1) 6 × ADCLK.
REFERENCE SELECTION
MODE
INT/EXT DESCRIPTION
2.0VPP Internal Reference
1
0
Default with internal pull-up.
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
External Reference
3
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted.
ADS5275
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
DNL Differential Nonlinearity
INL Integral Nonlinearity
Offset Error(1)
Assured
±0.5
±0.6
±0.2
14
fIN = 5MHz
fIN = 5MHz
-0.9
-2.0
+0.9
+2.0
LSB
LSB
-0.75
+0.75
%FS
Offset Temperature Coefficient
Fixed Attenuation in Channel(2)
Variable Attenuation in Channel(3)
Gain Error(4)
ppm/°C
%FS
1
±2.0
±1.0
44
%FS
REFT - REFB
-2.5
+2.5
%FS
Gain Temperature Coefficient(5)
ppm/°C
POWER SUPPLY
ICC Total Supply Current
VIN = FS, FIN = 5MHz
VIN = FS, FIN = 5MHz
275
221
mA
mA
I(AVDD) Analog Supply Current
VIN = FS, FIN = 5MHz,
LVDS into 100Ω Load
I(LVDD) Digital Output Driver Supply Current
54
mA
Power Dissipation
Power-Down
904
90
950
mW
mW
Clock Running
REFERENCE VOLTAGES
VREFT Reference Top (internal)
VREFB Reference Bottom (internal)
VCM Common-Mode Voltage
VCM Output Current(6)
1.95
0.95
1.45
2.0
1.0
2.05
1.05
1.55
V
V
1.5
V
±50mV Change in Voltage
±2.0
mA
V
VREFT Reference Top (external)
VREFB Reference Bottom (external)
External Reference Input Current(7)
ANALOG INPUT
1.875
1.125
V
2.0
70
mA
Differential Input Capacitance
Analog Input Common-Mode Range
Differential Input Voltage Range
pF
V
V
CM ± 0.05
1.5
2.02
VPP
Differential Input Signal at 4VPP
Recovery to Within 1% of Code
Voltage Overhead Recovery Time
4.0
CLK Cycles
MHz
Input Bandwidth
DIGITAL DATA OUTPUTS
Data Bit Rate
-3dBFS
300
240
480
MBPS
SERIAL INTERFACE
(1) Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
(2) Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential
voltage at the analog input pins are changed from -VREF to +VREF, the swing of the output code is expected to deviate from the full-scale
code (4096LSB) by the extent of this fixed attenuation.
NOTE: VREF is defined as (REFT - REFB).
(3) Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
(4) The reference voltages are trimmed at production so that (VREFT - VREFB) is within ± 25mV of the ideal value of 1V. It does not include
fixed attenuation.
(5) The gain temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the
variation of the reference voltages with temperature.
(6) VCM provides the common-mode current for the inputs of all eight channels when the inputs are AC-coupled. The VCM output current
specified is the additional drive of the VCM buffer if loaded externally.
(7) Average current drawn from the reference pins in the external reference mode.
4
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per
channel, unless otherwise noted.
ADS5275
PARAMETER
SCLK Serial Clock Input Frequency
VIN LOW Input Low Voltage
VIN HIGH Input High Voltage
Input Current
TEST CONDITIONS
MIN
TYP
MAX
20
UNITS
MHz
V
0
0.6
2.1
VDD
V
±10
µA
Input Pin Capacitance
5.0
pF
AC CHARACTERISCTICS
TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted.
ADS5275
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 1MHz
fIN = 5MHz
fIN = 10MHz
fIN = 20MHz
fIN = 10MHz
80
80
dBc
dBc
TBD
SFDR Spurious-Free Dynamic Range
HD2 2nd-Order Harmonic Distortion
HD3 3rd-Order Harmonic Distortion
SNR Signal-to-Noise Ratio
80
dBc
80
dBc
85
dBc
TBD
TBD
TBD
TBD
85
dBc
85
dBc
85
dBc
80
dBc
80
dBc
80
dBc
80
dBc
60.5
60.5
60.5
60.5
60
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
60
SINAD Signal-to-Noise and Distortion
60
60
ENOB Effective Number of Bits
Crosstalk
9.7
-85
Signal Applied to 7 Channels; Measurement Taken
on the Channel with No Input Signal
dBc
5
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100Ω, and CLOAD = 9pF. All LVDS specifications are functionally tested, but not
parametrically tested.
PARAMETER
DC SPECIFICATIONS
Output Voltage High, OUTP or OUTN
CONDITIONS
MIN
TYP
MAX UNITS
RLOAD = 100Ω± 1%; See LVDS Timing Diagram,
1340
1475
mV
VOH
Page 7
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100Ω± 1%
RLOAD = 100Ω± 1%
925
325
1038
350
mV
mV
V
|VOD
|
Output Differential Voltage
Output Offset Voltage
375
RLOAD = 100Ω± 1%; See LVDS Timing Diagram,
1.125 1.250 1.275
VOS
Page 7
RO Output Impedance, Single-Ended
∆RO Mismatch Between OUTP and OUTN
CO Output Capacitance
VCM = 1.0V and 1.4V
VCM = 1.0V and 1.4V
VCM = 1.0V and 1.4V
RLOAD = 100Ω± 1%
RLOAD = 100Ω± 1%
Drivers Shorted to Ground
Drivers Shorted Together
VCC = 0V
TBD
TBD
Ω
%
3
4
5
pF
|∆VOD
|
Change in |VOD| Between 0 and 1
25
25
40
12
10
mV
mV
mA
mA
mA
∆VOS Change Between 0 and 1
ISOUT Output Short-Circuit Current
ISOUTNP Output Current
|IXN|, |IXP
| Power-Off Output Leakage
DRIVER AC SPECIFICATIONS
Clock Clock Signal Duty Cycle
6 × ADCLK
45
50
55
50
%
|tpHLP - tpLHN| or |tpHLN - tpHLP|,
tSKEW1
Any Differential Pair on Package(1)
ps
Differential Skew
|tpDIFF[X] - tpDIFF[Y]|,
tSKEW2
Any Two Signals on Package(3)
100
ps
Channel-to-Channel Skew(2)
tRISE/tFALL VOD Rise Time or VOD Fall Time
ZLOAD = 100Ω, CI = 9pF, IO = 2.5mA
ZLOAD = 100Ω, CI = 9pF, IO = 3.5mA
ZLOAD = 100Ω, CI = 9pF, IO = 4.5mA
ZLOAD = 100Ω, CI = 9pF, IO = 6.0mA
400
250
200
150
ps
ps
ps
(1) Skew measurements are made at the 50% point of the transistion.
(2) Where x is any one of the parallel channels and y is any other channel.
(3) Skew measurements made at 0V differential (that is, the crossing of single-ended signals).
6
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
SWITCHING CHARACTERISTICS
TMIN = -40°C and TMAX = +85°C. Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty
cycle, AVDD = 3.3V, LVDD = 3.3V, -1dBFS, ISET = 56kΩ, internal voltage reference, and 2VPP differential input,unless
otherwise noted.
ADS5275
PARAMETER
SWITCHING SPECIFICATIONS
tSAMPLE
CONDITIONS
MIN
TYP
MAX
UNITS
25
50
ns
ps
tD(A) Aperature Delay
120
1
Aperature Jitter (uncertainty)
tD(pipeline) Latency
tPROP Propagation Delay
ps
6.5
5
Cycles
ns
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
Outputs change on
next rising clock edge
after CS goes high.
ADCLK
Start Sequence
CS
t1
Data latched on
each rising edge of SCLK.
t2
SCLK
t3
SDATA
MSB
D6
D5
D4
D3
D2
D1
D0
t4
t5
PARAMETER
DESCRIPTION
MIN
50
13
13
5
TYP
MAX
UNIT
ns
t1
t2
t3
t4
t5
Serial CLK Period
Serial CLK High Time
Serial CLK Low Time
ns
ns
ns
ns
Minimum Data Setup Time
Minimum Data Hold Time
5
7
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
DESCRIPTION
REMARKS
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0. LVDS BUFFERS
0
0
1
1
0
1
0
1
Normal ADC Output
Deskew Pattern
Patterns Get Reversed in MSB
First Mode of LVDS
Sync Pattern
Custom Pattern
0
0
1
1
0
1
0
1
Output Current in LVDS = 3.5mA
Output Current in LVDS = 2.5mA
Output Current in LVDS = 4.5mA
Output Current in LVDS = 6.0mA
1. LSB/MSB MODE
0
0
0
1
D3
0
D2
X
D1
X
D0
1
2X LVDS Clock Output Current
LSB Mode
0
0
X
X
0
1
X
X
MSB Mode
0
0
0
0
1
1
0
1
2. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
X
X
X
X
Example: 1010 Powers Down
Channels 4 and 2 and
Keeps Channels 1 and 3 Alive
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
3. POWER-DOWN ADC CHANNELS
D3
D2
D1
D0
X
X
X
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (registers 4-6)
D3
MSB
X
D2
X
D1
X
D0
X
0
0
0
1
1
1
0
0
1
0
1
0
X
X
X
Bits for Custom Pattern
X
X
X
LSB
TEST PATTERNS(1)
Deskew
Sync
101010101010
000000111111
Custom
Any 10-bit pattern that is defined in the custom pattern registers 4 to 6.
(1) Default is LSB first. If MSB is selected, the above patterns will be reversed.
8
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
LVDS TIMING DIAGRAM (PER ADC CHANNEL)
Sample n
Sample n+6
Input
1
fS
ADCLK
tSAMPLE
2
LCLKP
6X ADCLK
LCLKN
OUTP
SERIAL DATA
OUTN
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0
0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0
0
Sample n data
ADCLKP
1X ADCLK
ADCLKN
tPROP
6.5 Clock Cycles
RESET TIMING
t1
+AVDD
Power
Supply
t1 > TBD
0V
t2 > 100ns
+AVDD
0V
RESET
t2
POWER-DOWN TIMING
µ
10 s
Device Fully
Powers Down
PDN
Device Fully
Powers Up
µ
1
s
9
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
PIN CONFIGURATION
Top View
HTQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
60
59
AVDD
IN1P
AVDD
IN8N
IN1N
3
58 IN8P
57
4
AVSS
IN2P
AVSS
5
56 IN7N
55 IN7P
IN2N
6
7
54
AVDD
AVSS
IN3P
AVDD
8
53 AVSS
9
52
51
50
IN6N
IN6P
10
11
IN3N
ADS5275
AVSS
AVSS
IN4P 12
13
49 IN5N
48
IN4N
IN5P
AVDD 14
LVSS 15
47 AVDD
46 LVSS
16
45
PD
RESET
LVSS 17
44 LVSS
18
19
20
43
42
41
LVSS
LCLKP
LCLKN
LVSS
ADCLKN
ADCLKP
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
10
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
PIN DESCRIPTIONS
NAME
PIN #
NUMBER I/O DESCRIPTION
OF PINS
AVDD
AVSS
LVDD
LVSS
IN1P
IN1N
IN2P
IN2N
IN3P
IN3N
IN4P
IN4N
IN5P
IN5N
IN6P
IN6N
IN7P
IN7N
IN8P
IN8N
1, 7, 14, 47, 54, 60, 63, 70, 75
9
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog Power Supply
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
Analog Ground
25, 35
LVDS Power Supply
15, 17, 18, 26, 36, 43, 44, 46
LVDS Ground
2
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
3
5
6
9
10
12
13
48
49
51
52
55
56
58
59
Reference Top Voltage (1Ω resistor in series with a 0.1µF
capacitor to ground)
REFT
REFB
67
66
1
1
I/O
I/O
Reference Bottom Voltage (1Ω resistor in series with a 0.1µF
capacitor to ground)
VCM
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
O
I
Common-Mode Output Voltage
INT/EXT
PD
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
I
LCLKP
LCLKN
ADCLK
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
ADCLKP
O
O
I
Negative LVDS Clock
Data Converter Clock Input
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
11
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
PIN DESCRIPTIONS (continued)
NAME
PIN #
NUMBER I/O DESCRIPTION
OF PINS
ADCLKN
ISET
42
64
45
76
77
78
1
1
1
1
1
1
O
Negative LVDS ADC Clock Output
I/O Bias Current Setting Resistor of 56kΩ to Ground
RESET
CS
I
I
I
I
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data input
SDA
SCLK
Serial Data Clock
12
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V,
-1dBFS, ISET = 56kΩ, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
SPECTRAL PERFORMANCE
0
fIN = 10MHz
SNR = 60.5dBFS
SFDR = 85dBc
SINAD = 60dBFS
−
−
−
−
20
40
60
80
−
−
100
120
0
5
10
15
20
Frequency (MHz)
Figure 1.
13
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
DRIVING THE ANALOG INPUTS
THEORY OF OPERATION
The analog input biasing is shown in Figure 2. The
recommended method to drive the inputs is through
AC coupling. AC coupling removes the worry of
setting the common-mode of the driving circuit, since
the inputs are biased internally using two 600Ω
resistors. The sampling capacitor used to sample the
inputs is 4pF. The choice of the external AC coupling
capacitor is dictated by the attenuation at the lowest
desired input frequency of operation. The attenuation
resulting from using a 10nF AC coupling capacitor is
0.04%.
OVERVIEW
The ADS5275 is an 8-channel, high-speed, CMOS
ADC.
It
consists
of
a
high-performance
sample-and-hold circuit at the input, followed by a
10-bit ADC. The 10 bits given out by each channel
are serialized and sent out on a single pair of pins in
LVDS format. All eight channels of the ADS5275 run
off a single clock referred to as ADCLK. The sampling
clocks for each of the eight channels are generated
from the input clock using a carefully matched clock
buffer tree. The 12X clock required for the serializer is
generated internally from ADCLK using a phase lock
loop (PLL). A 6X and a 1X clock are also output in
LVDS format along with the data to enable easy data
capture. The ADS5275 operates from internally gen-
erated reference voltages that are trimmed to ensure
matching across multiple devices on a board. This
feature eliminates the need for external routing of
reference lines and also improves matching of the
gain across devices. The nominal values of REFT and
REFB are 2V and 1V, respectively. This implies that a
differential input of -1V corresponds to the zero code
of the ADC, and a differential input of +1V corre-
sponds to the full-scale code (4095 LSB). VCM
(common-mode voltage of REFT and REFB) is also
made available externally through a pin, and is
nominally 1.5V.
ADS5275
IN+
Ω
Ω
600
600
Input
Circuitry
−
IN
CM Buffer 1
CM Buffer 2
Internal
Voltage
Reference
VCM
The ADC employs a pipelined converter architecture
consisting of a combination of multi-bit and single-bit
internal stages. Each stage feeds its data into the
digital error correction logic, ensuring excellent differ-
ential linearity and no missing codes at the 10-bit
level. The pipeline architecture results in a data
latency of 6.5 clock cycles.
Figure 2. Analog Input Bias Circuitry
If the input is DC-coupled, then the output com-
mon-mode voltage of the circuit driving the ADS5275
should match the VCM (which is provided as an output
pin) to within ±50mV. It is recommended that the
output common-mode of the driving circuit be derived
from VCM provided by the device.
The output of the ADC goes to a serializer that
operates from a 12X clock generated by the PLL. The
10 data bits from each channel are serialized and
output LSB first. In addition to serializing the data, the
serializer also generates a 1X clock and a 6X clock.
These clocks are generated in the same way the
serialized data is generated, so these clocks maintain
perfect synchronization with the data. The data and
clock outputs of the serializer are buffered externally
using LVDS buffers. Using LVDS buffers to transmit
data externally has multiple advantages, such as
reduced number of output pins (saving routing space
on the board), reduced power consumption, and
reduced effects of digital noise coupling to the analog
circuit inside the ADS5275.
The sampling circuit consists of a low-pass RC filter
at the input to filter out noise components that might
be getting differentially coupled on the input pins. The
inputs are sampled on two 4pF capacitors. The
sampling on the capacitors is done with respect to an
internally generated common-mode voltage (INCM).
The switches connecting the sampling capacitors to
the INCM are opened out first (before the switches
connecting them to the analog inputs). This ensures
that the charge injection arising out of the switches
opening is independent of the input signal amplitude
to a first-order of approximation. SP refers to a
sampling clock whose falling edge comes an instant
before the SAMPLE clock. The falling edge of SP
determines the sampling instant.
The ADS5275 operates from two sets of supplies and
grounds. The analog supply/ground set is denoted as
AVDD/AVSS, while the digital set is denoted by
LVDD/LVSS.
14
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
and thereby scales down the device operating power.
However, it is recommended that the external resistor
be within 10% of the specified value of 56k so that
the internal bias margins for the various blocks are
proper.
INCM
(internally generated voltage)
SP
Sample
(defines sampling instant)
4pF
4pF
Buffering the internal bandgap voltage also generates
a voltage called VCM, which is set to the midlevel of
REFT and REFB, and is accessible on a pin. The
internal buffer driving VCM has a drive of ±4mA. It is
meant as a reference voltage to derive the input
common-mode in case the input is directly coupled.
Ω
Ω
15
IN+
1.5pF
1.7pF
SP
15
The device also supports the use of external refer-
ence voltages. This involves forcing REFT and REFB
externally. In this mode, the internal reference buffer
is tri-stated. Since the switching current for the eight
ADCs come from the externally-forced references, it
is possible for the performance to be slightly less than
when the internal references are used. It should be
noted that in this mode, VCM and ISET continue to be
generated from the internal bandgap voltage, as in
the internal reference mode. It is therefore important
to ensure that the common-mode voltage of the
externally-forced reference voltages matches to
−
IN
Sample
1.5pF
SP
INCM
Figure 3. Input Circuitry
INPUT OVER-VOLTAGE RECOVERY
The differential full-scale input peak-to-peak voltage
supported by the ADS5275 is 2V. For a nominal
value of VCM (1.5V), INP and INN can swing from 1V
to 2V. The ADS5275 is specially designed to handle
an over-voltage differential peak-to-peak voltage of
4V (2.5V and 0.5V swings on INP and INN). If the
input common-mode is less than 300mV from VCM
during overload, recovery from an over-voltage input
condition is expected to be within 4 clock cycles. All
of the amplifiers in the SHA and ADC are specially
designed for excellent recovery from an overload
signal.
within 50mV of VCM
.
CLOCKING
The eight channels on the chip run off a single
ADCLK input. To ensure that the aperture delay and
jitter are same for all the channels, a clock tree
network is used to generate individual sampling
clocks to each channel. The clock paths for all the
channels are matched from the source point all the
way to the sample-and-hold. This ensures that the
performance and timing for all the channels are
identical. The use of the clock tree for matching
introduces an aperture delay, which is defined as the
delay between the rising edge of ADCLK and the
actual instant of sampling. The aperture delays for all
the channels are matched, and vary between 2.5ns to
4.5ns across devices. Another critical specification is
the aperture jitter that is defined as the uncertainty of
the sampling instant. The gates in the clock path are
designed to give an rms jitter of about 1ps.
REFERENCE CIRCUIT DESIGN
The digital beam-forming algorithm relies heavily on
gain matching across all receiver channels. A typical
system would have about 10 octal ADCs on the
board. In such a case, it is critical to ensure that the
gain is matched, essentially requiring the reference
voltages seen by all the ADCs to be the same.
Matching references within the eight channels of a
chip is done by using a single internal reference
voltage buffer. Trimming the reference voltages on
each chip during production ensures the reference
voltages are well-matched across different chips.
The input ADCLK should ideally have a 50% duty
cycle. However, while routing ADCLK to different
components on board, the duty cycle of the ADCLK
reaching the ADS5275 could deviate from 50%. A
smaller (or larger) duty cycle eats into the time
available for sample or hold phases of each circuit,
and is therefore not optimal. For this reason, the
internal PLL is used to generate an internal clock that
has 50% duty cycle.
All bias currents required for the internal operation of
the device are set using an external resistor to
ground at pin ISET. Using a 56kΩ resistor on ISET
generates an internal reference current of 20µA. This
current is mirrored internally to generate the bias
current for the internal blocks. Using a larger external
resistor at ISET reduces the reference bias current
The use of the PLL automatically dictates the lower
frequency of operation to be about 20MHz.
15
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
LVDS BUFFERS
followed by six 1s. Using this mode, the 1X clock can
be used to determine the start of the data frame. In
addition to the deskew mode pattern and the sync
pattern, a custom pattern can be defined by the user
and output from the LVDS buffer.
The LVDS buffer has two current sources, as shown
in Figure 4. OUTP and OUTN are loaded externally by
a resistive load that is ideally about 100Ω. Depending
on the data being 0 or 1, the currents are directed in
one or the other direction through the resistor. The
LVDS buffer has four current settings. The default
current setting is 3.5mA, and gives a differential drop
of about ±350mV across the 100Ω resistor.
NOISE COUPLING ISSUES
High-speed mixed signals are sensitive to various
types of noise coupling. One of the main sources of
noise is the switching noise from the serializer and
the output buffers. Maximum care is taken to isolate
these noise sources from the sensitive analog blocks.
As a starting point, the analog and digital domains of
the chip are clearly demarcated. AVDD and AVSS
are used to denote the supplies for the analog
sections, while LVDD and LVSS are used to denote
the digital supplies. Care is taken to ensure that there
is minimal interaction between the supply sets within
the device. The extent of noise coupled and
transmitted from the digital to the analog sections
depends on the following:
External
Termination
Resistor
High
Low
OUTP
OUTN
Low
High
1. The effective inductances of each of the
supply/ground sets.
2. The isolation between the digital and analog
supply/ground sets.
Smaller effective inductance of the supply/ground
pins leads to better suppression of the noise. For this
reason, multiple pins are used to drive each
supply/ground. It is also critical to ensure that the
impedances of the supply and ground lines on board
are kept to the minimum possible values. Use of
ground planes in the board as well as large decoup-
ling capacitors between the supply and ground lines
are necessary to get the best possible SNR from the
device.
Figure 4. LVDS Buffer
The LVDS buffer gets data from a serializer that
takes the output data from each channel and
serializes it into a single data stream. For a clock
frequency of 40MHz, the data rate output by the
serializer is 480MBPS. The data comes out LSB first,
with a register programmability to revert to MSB first.
The serializer also gives out a 1X clock and a 6X
clock. The 6X clock (denoted as LCLKP/LCLKN) is
meant to synchronize the capture of the LVDS data.
The deskew mode can be enabled as well, using a
register setting. This mode gives out a data stream of
alternate 0s and 1s and can be used to determine the
relative delay between the 6X clock and the output
data for optimum capture. A 1X clock is also gener-
ated by the serializer and transmitted by the LVDS
It is recommended that the isolation be maintained
onboard by using separate supplies to drive AVDD
and LVDD, as well as separate ground planes for
AVSS and LVSS.
The use of LVDS buffers reduces the injected noise
considerably, compared to CMOS buffers. The cur-
rent in the LVDS buffer is independent of the direction
of switching. Also, the low output swing as well as the
differential nature of the LVDS buffer results in
low-noise coupling.
buffer.
The
1X
clock
(referred
to
as
ADCLKP/ADCLKN) is used to determine the start of
the 10-bit data frame. The sync mode (enabled
through a register setting) gives out a data of six 0s
16
ADS5275
www.ti.com
SBAS300–JANUARY 2004–REVISED NOVEMBER 2004
POWER-DOWN MODE
SUPPLY SEQUENCE
The device has a power-down pin, PD. Pulling PD
high causes the devices to enter the power-down
mode. In this mode, the reference and clock circuitry
as well as all the channels are powered down. Device
power consumption drops to less than 100mW in this
mode. Individual channels can also be selectively
powered down by programming registers.
The following supply sequence is recommended for
powering up the device:
1. AVDD is powered up.
2. LVDD is powered up.
After the supplies have stabilized, it is required to
give the device an active RESET pulse. This results
in all internal registers getting reset to their default
value of 0 (inactive). Without RESET, it is possible
that some registers might be in their non-default state
on power-up. This could cause the device to
malfunction.
The ADS5275 also has an internal circuit that moni-
tors the state of stopped clocks. If ADCLK is stopped
(or if it runs at a speed < 3MHz), this monitoring
circuit generates a logic signal that puts the device in
a power-down state. As a result, the power consump-
tion of the device goes to less than 100mW when
ADCLK is stopped. This circuit can also be disabled
using register options.
17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS5275IPFP
ADS5275IPFPT
PREVIEW
PREVIEW
HTQFP
HTQFP
PFP
PFP
80
80
96
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
相关型号：
ADS5277IPFPG4
Eight-Channel, 10-Bit, 65-MSPS Analog-to-Digital Converter (ADC) 80-HTQFP -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明